diff options
author | Seth Heasley <seth.heasley@intel.com> | 2012-04-17 17:09:22 -0400 |
---|---|---|
committer | Samuel Ortiz <sameo@linux.intel.com> | 2012-05-09 09:58:21 -0400 |
commit | 8ee3c2a79fe1df10bccd110d5b8cc13c5b9da709 (patch) | |
tree | 8b78e264fd03c9a61cf10e21c121e7106409c228 /drivers/mfd/lpc_sch.c | |
parent | 1fc9b1eade80b323f02a9cf7a29e1641eddf1052 (diff) |
lpc_sch: Add Intel Centerton Multifunction Device support
This patch adds the Intel Centerton processor DeviceID for the
Integrated Legacy Block (ILB).
The ILB provides GPIO, SMBus, and Watchdog functionality.
Signed-off-by: Seth Heasley <seth.heasley@intel.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat (limited to 'drivers/mfd/lpc_sch.c')
-rw-r--r-- | drivers/mfd/lpc_sch.c | 11 |
1 files changed, 9 insertions, 2 deletions
diff --git a/drivers/mfd/lpc_sch.c b/drivers/mfd/lpc_sch.c index 27026eb924cd..9bf08393d747 100644 --- a/drivers/mfd/lpc_sch.c +++ b/drivers/mfd/lpc_sch.c | |||
@@ -36,6 +36,7 @@ | |||
36 | 36 | ||
37 | #define GPIOBASE 0x44 | 37 | #define GPIOBASE 0x44 |
38 | #define GPIO_IO_SIZE 64 | 38 | #define GPIO_IO_SIZE 64 |
39 | #define GPIO_IO_SIZE_CENTERTON 128 | ||
39 | 40 | ||
40 | #define WDTBASE 0x84 | 41 | #define WDTBASE 0x84 |
41 | #define WDT_IO_SIZE 64 | 42 | #define WDT_IO_SIZE 64 |
@@ -77,6 +78,7 @@ static struct mfd_cell tunnelcreek_cells[] = { | |||
77 | static DEFINE_PCI_DEVICE_TABLE(lpc_sch_ids) = { | 78 | static DEFINE_PCI_DEVICE_TABLE(lpc_sch_ids) = { |
78 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_LPC) }, | 79 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_LPC) }, |
79 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ITC_LPC) }, | 80 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ITC_LPC) }, |
81 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CENTERTON_ILB) }, | ||
80 | { 0, } | 82 | { 0, } |
81 | }; | 83 | }; |
82 | MODULE_DEVICE_TABLE(pci, lpc_sch_ids); | 84 | MODULE_DEVICE_TABLE(pci, lpc_sch_ids); |
@@ -115,7 +117,11 @@ static int __devinit lpc_sch_probe(struct pci_dev *dev, | |||
115 | } | 117 | } |
116 | 118 | ||
117 | gpio_sch_resource.start = base_addr; | 119 | gpio_sch_resource.start = base_addr; |
118 | gpio_sch_resource.end = base_addr + GPIO_IO_SIZE - 1; | 120 | |
121 | if (id->device == PCI_DEVICE_ID_INTEL_CENTERTON_ILB) | ||
122 | gpio_sch_resource.end = base_addr + GPIO_IO_SIZE_CENTERTON - 1; | ||
123 | else | ||
124 | gpio_sch_resource.end = base_addr + GPIO_IO_SIZE - 1; | ||
119 | 125 | ||
120 | for (i=0; i < ARRAY_SIZE(lpc_sch_cells); i++) | 126 | for (i=0; i < ARRAY_SIZE(lpc_sch_cells); i++) |
121 | lpc_sch_cells[i].id = id->device; | 127 | lpc_sch_cells[i].id = id->device; |
@@ -125,7 +131,8 @@ static int __devinit lpc_sch_probe(struct pci_dev *dev, | |||
125 | if (ret) | 131 | if (ret) |
126 | goto out_dev; | 132 | goto out_dev; |
127 | 133 | ||
128 | if (id->device == PCI_DEVICE_ID_INTEL_ITC_LPC) { | 134 | if (id->device == PCI_DEVICE_ID_INTEL_ITC_LPC |
135 | || id->device == PCI_DEVICE_ID_INTEL_CENTERTON_ILB) { | ||
129 | pci_read_config_dword(dev, WDTBASE, &base_addr_cfg); | 136 | pci_read_config_dword(dev, WDTBASE, &base_addr_cfg); |
130 | if (!(base_addr_cfg & (1 << 31))) { | 137 | if (!(base_addr_cfg & (1 << 31))) { |
131 | dev_err(&dev->dev, "Decode of the WDT I/O range disabled\n"); | 138 | dev_err(&dev->dev, "Decode of the WDT I/O range disabled\n"); |