mfd: db8500 clock handling update

This updates the clock handling in the DB8500 PRCMU driver with
the latest findings and API changes related to changes in the
backing firmware in the PRCMU.

- Add the necessary interfaces to get the frequencies of the
  clocks and set the rate of some of the clocks.
- Add support for controlling the clocks PLLSOC0, PLLDSI,
  DSI0, DSI1 and DSI escape clocks (DSInESCCLK).
- Correct the PLLSDI enable/disable sequence by using the
  DSIPLL_CLAMPI bit.

After this we will have the interfaces and code to implement the
U8500 clock framework properly.

Reviewed-by: Jonas Aberg <jonas.aberg@stericsson.com>
Signed-off-by: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>

1 files changed, 86 insertions, 42 deletions

diff --git a/drivers/mfd/dbx500-prcmu-regs.h b/drivers/mfd/dbx500-prcmu-regs.h
index ec22e9f15d32..b9ab4ce62654 100644
--- a/drivers/mfd/dbx500-prcmu-regs.h
+++ b/drivers/mfd/dbx500-prcmu-regs.h
@@ -17,41 +17,41 @@
 
 #define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end))
 
-#define PRCM_SVACLK_MGT_OFF             0x008
-#define PRCM_SIACLK_MGT_OFF             0x00C
-#define PRCM_SGACLK_MGT_OFF             0x014
-#define PRCM_UARTCLK_MGT_OFF            0x018
-#define PRCM_MSP02CLK_MGT_OFF           0x01C
-#define PRCM_I2CCLK_MGT_OFF             0x020
-#define PRCM_SDMMCCLK_MGT_OFF           0x024
-#define PRCM_SLIMCLK_MGT_OFF            0x028
-#define PRCM_PER1CLK_MGT_OFF            0x02C
-#define PRCM_PER2CLK_MGT_OFF            0x030
-#define PRCM_PER3CLK_MGT_OFF            0x034
-#define PRCM_PER5CLK_MGT_OFF            0x038
-#define PRCM_PER6CLK_MGT_OFF            0x03C
-#define PRCM_PER7CLK_MGT_OFF            0x040
-#define PRCM_PWMCLK_MGT_OFF             0x044 /* for DB5500 */
-#define PRCM_IRDACLK_MGT_OFF            0x048 /* for DB5500 */
-#define PRCM_IRRCCLK_MGT_OFF            0x04C /* for DB5500 */
-#define PRCM_LCDCLK_MGT_OFF             0x044
-#define PRCM_BMLCLK_MGT_OFF             0x04C
-#define PRCM_HSITXCLK_MGT_OFF           0x050
-#define PRCM_HSIRXCLK_MGT_OFF           0x054
-#define PRCM_HDMICLK_MGT_OFF            0x058
-#define PRCM_APEATCLK_MGT_OFF           0x05C
-#define PRCM_APETRACECLK_MGT_OFF        0x060
-#define PRCM_MCDECLK_MGT_OFF            0x064
-#define PRCM_IPI2CCLK_MGT_OFF           0x068
-#define PRCM_DSIALTCLK_MGT_OFF          0x06C
-#define PRCM_DMACLK_MGT_OFF             0x074
-#define PRCM_B2R2CLK_MGT_OFF            0x078
-#define PRCM_TVCLK_MGT_OFF              0x07C
-#define PRCM_UNIPROCLK_MGT_OFF          0x278
-#define PRCM_SSPCLK_MGT_OFF             0x280
-#define PRCM_RNGCLK_MGT_OFF             0x284
-#define PRCM_UICCCLK_MGT_OFF            0x27C
-#define PRCM_MSP1CLK_MGT_OFF            0x288
+#define PRCM_CLK_MGT(_offset) (void __iomem *)(IO_ADDRESS(U8500_PRCMU_BASE) \
+        + _offset)
+#define PRCM_ACLK_MGT           PRCM_CLK_MGT(0x004)
+#define PRCM_SVACLK_MGT         PRCM_CLK_MGT(0x008)
+#define PRCM_SIACLK_MGT         PRCM_CLK_MGT(0x00C)
+#define PRCM_SGACLK_MGT         PRCM_CLK_MGT(0x014)
+#define PRCM_UARTCLK_MGT        PRCM_CLK_MGT(0x018)
+#define PRCM_MSP02CLK_MGT       PRCM_CLK_MGT(0x01C)
+#define PRCM_I2CCLK_MGT         PRCM_CLK_MGT(0x020)
+#define PRCM_SDMMCCLK_MGT       PRCM_CLK_MGT(0x024)
+#define PRCM_SLIMCLK_MGT        PRCM_CLK_MGT(0x028)
+#define PRCM_PER1CLK_MGT        PRCM_CLK_MGT(0x02C)
+#define PRCM_PER2CLK_MGT        PRCM_CLK_MGT(0x030)
+#define PRCM_PER3CLK_MGT        PRCM_CLK_MGT(0x034)
+#define PRCM_PER5CLK_MGT        PRCM_CLK_MGT(0x038)
+#define PRCM_PER6CLK_MGT        PRCM_CLK_MGT(0x03C)
+#define PRCM_PER7CLK_MGT        PRCM_CLK_MGT(0x040)
+#define PRCM_LCDCLK_MGT         PRCM_CLK_MGT(0x044)
+#define PRCM_BMLCLK_MGT         PRCM_CLK_MGT(0x04C)
+#define PRCM_HSITXCLK_MGT       PRCM_CLK_MGT(0x050)
+#define PRCM_HSIRXCLK_MGT       PRCM_CLK_MGT(0x054)
+#define PRCM_HDMICLK_MGT        PRCM_CLK_MGT(0x058)
+#define PRCM_APEATCLK_MGT       PRCM_CLK_MGT(0x05C)
+#define PRCM_APETRACECLK_MGT    PRCM_CLK_MGT(0x060)
+#define PRCM_MCDECLK_MGT        PRCM_CLK_MGT(0x064)
+#define PRCM_IPI2CCLK_MGT       PRCM_CLK_MGT(0x068)
+#define PRCM_DSIALTCLK_MGT      PRCM_CLK_MGT(0x06C)
+#define PRCM_DMACLK_MGT         PRCM_CLK_MGT(0x074)
+#define PRCM_B2R2CLK_MGT        PRCM_CLK_MGT(0x078)
+#define PRCM_TVCLK_MGT          PRCM_CLK_MGT(0x07C)
+#define PRCM_UNIPROCLK_MGT      PRCM_CLK_MGT(0x278)
+#define PRCM_SSPCLK_MGT         PRCM_CLK_MGT(0x280)
+#define PRCM_RNGCLK_MGT         PRCM_CLK_MGT(0x284)
+#define PRCM_UICCCLK_MGT        PRCM_CLK_MGT(0x27C)
+#define PRCM_MSP1CLK_MGT        PRCM_CLK_MGT(0x288)
 
 #define PRCM_ARM_PLLDIVPS       (_PRCMU_BASE + 0x118)
 #define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE          0x3f
@@ -131,20 +131,58 @@
 #define PRCM_MMIP_LS_CLAMP_SET     (_PRCMU_BASE + 0x420)
 #define PRCM_MMIP_LS_CLAMP_CLR     (_PRCMU_BASE + 0x424)
 
+#define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP         BIT(11)
+#define PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI        BIT(22)
+
 /* PRCMU clock/PLL/reset registers */
+#define PRCM_PLLSOC0_FREQ          (_PRCMU_BASE + 0x080)
+#define PRCM_PLLSOC1_FREQ          (_PRCMU_BASE + 0x084)
+#define PRCM_PLLDDR_FREQ           (_PRCMU_BASE + 0x08C)
+#define PRCM_PLL_FREQ_D_SHIFT   0
+#define PRCM_PLL_FREQ_D_MASK    BITS(0, 7)
+#define PRCM_PLL_FREQ_N_SHIFT   8
+#define PRCM_PLL_FREQ_N_MASK    BITS(8, 13)
+#define PRCM_PLL_FREQ_R_SHIFT   16
+#define PRCM_PLL_FREQ_R_MASK    BITS(16, 18)
+#define PRCM_PLL_FREQ_SELDIV2   BIT(24)
+#define PRCM_PLL_FREQ_DIV2EN    BIT(25)
+
 #define PRCM_PLLDSI_FREQ           (_PRCMU_BASE + 0x500)
 #define PRCM_PLLDSI_ENABLE         (_PRCMU_BASE + 0x504)
 #define PRCM_PLLDSI_LOCKP          (_PRCMU_BASE + 0x508)
-#define PRCM_LCDCLK_MGT            (_PRCMU_BASE + PRCM_LCDCLK_MGT_OFF)
-#define PRCM_MCDECLK_MGT           (_PRCMU_BASE + PRCM_MCDECLK_MGT_OFF)
-#define PRCM_HDMICLK_MGT           (_PRCMU_BASE + PRCM_HDMICLK_MGT_OFF)
-#define PRCM_TVCLK_MGT             (_PRCMU_BASE + PRCM_TVCLK_MGT_OFF)
 #define PRCM_DSI_PLLOUT_SEL        (_PRCMU_BASE + 0x530)
 #define PRCM_DSITVCLK_DIV          (_PRCMU_BASE + 0x52C)
 #define PRCM_PLLDSI_LOCKP          (_PRCMU_BASE + 0x508)
 #define PRCM_APE_RESETN_SET        (_PRCMU_BASE + 0x1E4)
 #define PRCM_APE_RESETN_CLR        (_PRCMU_BASE + 0x1E8)
 
+#define PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE BIT(0)
+
+#define PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10   BIT(0)
+#define PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3    BIT(1)
+
+#define PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT    0
+#define PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK     BITS(0, 2)
+#define PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT    8
+#define PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK     BITS(8, 10)
+
+#define PRCM_DSI_PLLOUT_SEL_OFF         0
+#define PRCM_DSI_PLLOUT_SEL_PHI         1
+#define PRCM_DSI_PLLOUT_SEL_PHI_2       2
+#define PRCM_DSI_PLLOUT_SEL_PHI_4       3
+
+#define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT        0
+#define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK         BITS(0, 7)
+#define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT        8
+#define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK         BITS(8, 15)
+#define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT        16
+#define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK         BITS(16, 23)
+#define PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN               BIT(24)
+#define PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN               BIT(25)
+#define PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN               BIT(26)
+
+#define PRCM_APE_RESETN_DSIPLL_RESETN BIT(14)
+
 #define PRCM_CLKOCR                (_PRCMU_BASE + 0x1CC)
 #define PRCM_CLKOCR_CLKOUT0_REF_CLK     (1 << 0)
 #define PRCM_CLKOCR_CLKOUT0_MASK        BITS(0, 13)
@@ -183,9 +221,15 @@
 #define PRCM_CLKOCR_CLKOSEL1_MASK       BITS(22, 24)
 #define PRCM_CLKOCR_CLK1TYPE            BIT(28)
 
-#define PRCM_CLK_MGT_CLKPLLDIV_MASK     BITS(0, 4)
-#define PRCM_CLK_MGT_CLKPLLSW_MASK      BITS(5, 7)
-#define PRCM_CLK_MGT_CLKEN              BIT(8)
+#define PRCM_CLK_MGT_CLKPLLDIV_MASK             BITS(0, 4)
+#define PRCM_CLK_MGT_CLKPLLSW_SOC0              BIT(5)
+#define PRCM_CLK_MGT_CLKPLLSW_SOC1              BIT(6)
+#define PRCM_CLK_MGT_CLKPLLSW_DDR               BIT(7)
+#define PRCM_CLK_MGT_CLKPLLSW_MASK              BITS(5, 7)
+#define PRCM_CLK_MGT_CLKEN                      BIT(8)
+#define PRCM_CLK_MGT_CLK38                      BIT(9)
+#define PRCM_CLK_MGT_CLK38DIV                   BIT(11)
+#define PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN     BIT(12)
 
 /* GPIOCR register */
 #define PRCM_GPIOCR_SPI2_SELECT BIT(23)