diff options
author | Mark Brown <broonie@opensource.wolfsonmicro.com> | 2010-12-11 08:08:57 -0500 |
---|---|---|
committer | Samuel Ortiz <sameo@linux.intel.com> | 2011-01-14 06:37:52 -0500 |
commit | 0f76aaebe8015d6a850cb03622382bacb7860398 (patch) | |
tree | d560db97aea8323ea36d6b4d1c2fe0cc67d26705 /drivers/mfd/asic3.c | |
parent | 49f89d9acb6cba6475923e42a3d13540a70a926e (diff) |
mfd: Convert ASIC3 to new irq_ APIs
The interrupt controller APIs are being updated to pass a struct irq_data
rather than the interrupt number.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Ian Molton <ian@mnementh.co.uk>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat (limited to 'drivers/mfd/asic3.c')
-rw-r--r-- | drivers/mfd/asic3.c | 56 |
1 files changed, 28 insertions, 28 deletions
diff --git a/drivers/mfd/asic3.c b/drivers/mfd/asic3.c index 3c7dc5ebfe4d..6a1f94042612 100644 --- a/drivers/mfd/asic3.c +++ b/drivers/mfd/asic3.c | |||
@@ -226,14 +226,14 @@ static inline int asic3_irq_to_index(struct asic3 *asic, int irq) | |||
226 | return (irq - asic->irq_base) & 0xf; | 226 | return (irq - asic->irq_base) & 0xf; |
227 | } | 227 | } |
228 | 228 | ||
229 | static void asic3_mask_gpio_irq(unsigned int irq) | 229 | static void asic3_mask_gpio_irq(struct irq_data *data) |
230 | { | 230 | { |
231 | struct asic3 *asic = get_irq_chip_data(irq); | 231 | struct asic3 *asic = irq_data_get_irq_chip_data(data); |
232 | u32 val, bank, index; | 232 | u32 val, bank, index; |
233 | unsigned long flags; | 233 | unsigned long flags; |
234 | 234 | ||
235 | bank = asic3_irq_to_bank(asic, irq); | 235 | bank = asic3_irq_to_bank(asic, data->irq); |
236 | index = asic3_irq_to_index(asic, irq); | 236 | index = asic3_irq_to_index(asic, data->irq); |
237 | 237 | ||
238 | spin_lock_irqsave(&asic->lock, flags); | 238 | spin_lock_irqsave(&asic->lock, flags); |
239 | val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); | 239 | val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); |
@@ -242,9 +242,9 @@ static void asic3_mask_gpio_irq(unsigned int irq) | |||
242 | spin_unlock_irqrestore(&asic->lock, flags); | 242 | spin_unlock_irqrestore(&asic->lock, flags); |
243 | } | 243 | } |
244 | 244 | ||
245 | static void asic3_mask_irq(unsigned int irq) | 245 | static void asic3_mask_irq(struct irq_data *data) |
246 | { | 246 | { |
247 | struct asic3 *asic = get_irq_chip_data(irq); | 247 | struct asic3 *asic = irq_data_get_irq_chip_data(data); |
248 | int regval; | 248 | int regval; |
249 | unsigned long flags; | 249 | unsigned long flags; |
250 | 250 | ||
@@ -254,7 +254,7 @@ static void asic3_mask_irq(unsigned int irq) | |||
254 | ASIC3_INTR_INT_MASK); | 254 | ASIC3_INTR_INT_MASK); |
255 | 255 | ||
256 | regval &= ~(ASIC3_INTMASK_MASK0 << | 256 | regval &= ~(ASIC3_INTMASK_MASK0 << |
257 | (irq - (asic->irq_base + ASIC3_NUM_GPIOS))); | 257 | (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS))); |
258 | 258 | ||
259 | asic3_write_register(asic, | 259 | asic3_write_register(asic, |
260 | ASIC3_INTR_BASE + | 260 | ASIC3_INTR_BASE + |
@@ -263,14 +263,14 @@ static void asic3_mask_irq(unsigned int irq) | |||
263 | spin_unlock_irqrestore(&asic->lock, flags); | 263 | spin_unlock_irqrestore(&asic->lock, flags); |
264 | } | 264 | } |
265 | 265 | ||
266 | static void asic3_unmask_gpio_irq(unsigned int irq) | 266 | static void asic3_unmask_gpio_irq(struct irq_data *data) |
267 | { | 267 | { |
268 | struct asic3 *asic = get_irq_chip_data(irq); | 268 | struct asic3 *asic = irq_data_get_irq_chip_data(data); |
269 | u32 val, bank, index; | 269 | u32 val, bank, index; |
270 | unsigned long flags; | 270 | unsigned long flags; |
271 | 271 | ||
272 | bank = asic3_irq_to_bank(asic, irq); | 272 | bank = asic3_irq_to_bank(asic, data->irq); |
273 | index = asic3_irq_to_index(asic, irq); | 273 | index = asic3_irq_to_index(asic, data->irq); |
274 | 274 | ||
275 | spin_lock_irqsave(&asic->lock, flags); | 275 | spin_lock_irqsave(&asic->lock, flags); |
276 | val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); | 276 | val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK); |
@@ -279,9 +279,9 @@ static void asic3_unmask_gpio_irq(unsigned int irq) | |||
279 | spin_unlock_irqrestore(&asic->lock, flags); | 279 | spin_unlock_irqrestore(&asic->lock, flags); |
280 | } | 280 | } |
281 | 281 | ||
282 | static void asic3_unmask_irq(unsigned int irq) | 282 | static void asic3_unmask_irq(struct irq_data *data) |
283 | { | 283 | { |
284 | struct asic3 *asic = get_irq_chip_data(irq); | 284 | struct asic3 *asic = irq_data_get_irq_chip_data(data); |
285 | int regval; | 285 | int regval; |
286 | unsigned long flags; | 286 | unsigned long flags; |
287 | 287 | ||
@@ -291,7 +291,7 @@ static void asic3_unmask_irq(unsigned int irq) | |||
291 | ASIC3_INTR_INT_MASK); | 291 | ASIC3_INTR_INT_MASK); |
292 | 292 | ||
293 | regval |= (ASIC3_INTMASK_MASK0 << | 293 | regval |= (ASIC3_INTMASK_MASK0 << |
294 | (irq - (asic->irq_base + ASIC3_NUM_GPIOS))); | 294 | (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS))); |
295 | 295 | ||
296 | asic3_write_register(asic, | 296 | asic3_write_register(asic, |
297 | ASIC3_INTR_BASE + | 297 | ASIC3_INTR_BASE + |
@@ -300,15 +300,15 @@ static void asic3_unmask_irq(unsigned int irq) | |||
300 | spin_unlock_irqrestore(&asic->lock, flags); | 300 | spin_unlock_irqrestore(&asic->lock, flags); |
301 | } | 301 | } |
302 | 302 | ||
303 | static int asic3_gpio_irq_type(unsigned int irq, unsigned int type) | 303 | static int asic3_gpio_irq_type(struct irq_data *data, unsigned int type) |
304 | { | 304 | { |
305 | struct asic3 *asic = get_irq_chip_data(irq); | 305 | struct asic3 *asic = irq_data_get_irq_chip_data(data); |
306 | u32 bank, index; | 306 | u32 bank, index; |
307 | u16 trigger, level, edge, bit; | 307 | u16 trigger, level, edge, bit; |
308 | unsigned long flags; | 308 | unsigned long flags; |
309 | 309 | ||
310 | bank = asic3_irq_to_bank(asic, irq); | 310 | bank = asic3_irq_to_bank(asic, data->irq); |
311 | index = asic3_irq_to_index(asic, irq); | 311 | index = asic3_irq_to_index(asic, data->irq); |
312 | bit = 1<<index; | 312 | bit = 1<<index; |
313 | 313 | ||
314 | spin_lock_irqsave(&asic->lock, flags); | 314 | spin_lock_irqsave(&asic->lock, flags); |
@@ -318,7 +318,7 @@ static int asic3_gpio_irq_type(unsigned int irq, unsigned int type) | |||
318 | bank + ASIC3_GPIO_EDGE_TRIGGER); | 318 | bank + ASIC3_GPIO_EDGE_TRIGGER); |
319 | trigger = asic3_read_register(asic, | 319 | trigger = asic3_read_register(asic, |
320 | bank + ASIC3_GPIO_TRIGGER_TYPE); | 320 | bank + ASIC3_GPIO_TRIGGER_TYPE); |
321 | asic->irq_bothedge[(irq - asic->irq_base) >> 4] &= ~bit; | 321 | asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] &= ~bit; |
322 | 322 | ||
323 | if (type == IRQ_TYPE_EDGE_RISING) { | 323 | if (type == IRQ_TYPE_EDGE_RISING) { |
324 | trigger |= bit; | 324 | trigger |= bit; |
@@ -328,11 +328,11 @@ static int asic3_gpio_irq_type(unsigned int irq, unsigned int type) | |||
328 | edge &= ~bit; | 328 | edge &= ~bit; |
329 | } else if (type == IRQ_TYPE_EDGE_BOTH) { | 329 | } else if (type == IRQ_TYPE_EDGE_BOTH) { |
330 | trigger |= bit; | 330 | trigger |= bit; |
331 | if (asic3_gpio_get(&asic->gpio, irq - asic->irq_base)) | 331 | if (asic3_gpio_get(&asic->gpio, data->irq - asic->irq_base)) |
332 | edge &= ~bit; | 332 | edge &= ~bit; |
333 | else | 333 | else |
334 | edge |= bit; | 334 | edge |= bit; |
335 | asic->irq_bothedge[(irq - asic->irq_base) >> 4] |= bit; | 335 | asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] |= bit; |
336 | } else if (type == IRQ_TYPE_LEVEL_LOW) { | 336 | } else if (type == IRQ_TYPE_LEVEL_LOW) { |
337 | trigger &= ~bit; | 337 | trigger &= ~bit; |
338 | level &= ~bit; | 338 | level &= ~bit; |
@@ -359,17 +359,17 @@ static int asic3_gpio_irq_type(unsigned int irq, unsigned int type) | |||
359 | 359 | ||
360 | static struct irq_chip asic3_gpio_irq_chip = { | 360 | static struct irq_chip asic3_gpio_irq_chip = { |
361 | .name = "ASIC3-GPIO", | 361 | .name = "ASIC3-GPIO", |
362 | .ack = asic3_mask_gpio_irq, | 362 | .irq_ack = asic3_mask_gpio_irq, |
363 | .mask = asic3_mask_gpio_irq, | 363 | .irq_mask = asic3_mask_gpio_irq, |
364 | .unmask = asic3_unmask_gpio_irq, | 364 | .irq_unmask = asic3_unmask_gpio_irq, |
365 | .set_type = asic3_gpio_irq_type, | 365 | .irq_set_type = asic3_gpio_irq_type, |
366 | }; | 366 | }; |
367 | 367 | ||
368 | static struct irq_chip asic3_irq_chip = { | 368 | static struct irq_chip asic3_irq_chip = { |
369 | .name = "ASIC3", | 369 | .name = "ASIC3", |
370 | .ack = asic3_mask_irq, | 370 | .irq_ack = asic3_mask_irq, |
371 | .mask = asic3_mask_irq, | 371 | .irq_mask = asic3_mask_irq, |
372 | .unmask = asic3_unmask_irq, | 372 | .irq_unmask = asic3_unmask_irq, |
373 | }; | 373 | }; |
374 | 374 | ||
375 | static int __init asic3_irq_probe(struct platform_device *pdev) | 375 | static int __init asic3_irq_probe(struct platform_device *pdev) |