diff options
author | Lee Jones <lee.jones@linaro.org> | 2012-11-19 06:20:03 -0500 |
---|---|---|
committer | Lee Jones <lee.jones@linaro.org> | 2013-03-06 23:29:10 -0500 |
commit | 971480f520a5ed9e54443a9b2b5711eedf51c77a (patch) | |
tree | 413603552268bde70dd20679f85f5d382cb6a97a /drivers/mfd/ab8500-debugfs.c | |
parent | f38487f22dee6eaca8d06cac99377693803cda8f (diff) |
mfd: ab8500-debug: Add register map for ab8540.
Required to read out correct debug information from the AB chip.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat (limited to 'drivers/mfd/ab8500-debugfs.c')
-rw-r--r-- | drivers/mfd/ab8500-debugfs.c | 422 |
1 files changed, 419 insertions, 3 deletions
diff --git a/drivers/mfd/ab8500-debugfs.c b/drivers/mfd/ab8500-debugfs.c index 4779e2f834b4..862dbfeb619e 100644 --- a/drivers/mfd/ab8500-debugfs.c +++ b/drivers/mfd/ab8500-debugfs.c | |||
@@ -846,6 +846,422 @@ struct ab8500_prcmu_ranges ab8505_debug_ranges[AB8500_NUM_BANKS] = { | |||
846 | }, | 846 | }, |
847 | }; | 847 | }; |
848 | 848 | ||
849 | struct ab8500_prcmu_ranges ab8540_debug_ranges[AB8500_NUM_BANKS] = { | ||
850 | [AB8500_M_FSM_RANK] = { | ||
851 | .num_ranges = 1, | ||
852 | .range = (struct ab8500_reg_range[]) { | ||
853 | { | ||
854 | .first = 0x00, | ||
855 | .last = 0x0B, | ||
856 | }, | ||
857 | }, | ||
858 | }, | ||
859 | [AB8500_SYS_CTRL1_BLOCK] = { | ||
860 | .num_ranges = 6, | ||
861 | .range = (struct ab8500_reg_range[]) { | ||
862 | { | ||
863 | .first = 0x00, | ||
864 | .last = 0x04, | ||
865 | }, | ||
866 | { | ||
867 | .first = 0x42, | ||
868 | .last = 0x42, | ||
869 | }, | ||
870 | { | ||
871 | .first = 0x50, | ||
872 | .last = 0x54, | ||
873 | }, | ||
874 | { | ||
875 | .first = 0x57, | ||
876 | .last = 0x57, | ||
877 | }, | ||
878 | { | ||
879 | .first = 0x80, | ||
880 | .last = 0x83, | ||
881 | }, | ||
882 | { | ||
883 | .first = 0x90, | ||
884 | .last = 0x90, | ||
885 | }, | ||
886 | }, | ||
887 | }, | ||
888 | [AB8500_SYS_CTRL2_BLOCK] = { | ||
889 | .num_ranges = 5, | ||
890 | .range = (struct ab8500_reg_range[]) { | ||
891 | { | ||
892 | .first = 0x00, | ||
893 | .last = 0x0D, | ||
894 | }, | ||
895 | { | ||
896 | .first = 0x0F, | ||
897 | .last = 0x10, | ||
898 | }, | ||
899 | { | ||
900 | .first = 0x20, | ||
901 | .last = 0x21, | ||
902 | }, | ||
903 | { | ||
904 | .first = 0x32, | ||
905 | .last = 0x3C, | ||
906 | }, | ||
907 | { | ||
908 | .first = 0x40, | ||
909 | .last = 0x42, | ||
910 | }, | ||
911 | }, | ||
912 | }, | ||
913 | [AB8500_REGU_CTRL1] = { | ||
914 | .num_ranges = 4, | ||
915 | .range = (struct ab8500_reg_range[]) { | ||
916 | { | ||
917 | .first = 0x03, | ||
918 | .last = 0x15, | ||
919 | }, | ||
920 | { | ||
921 | .first = 0x20, | ||
922 | .last = 0x20, | ||
923 | }, | ||
924 | { | ||
925 | .first = 0x80, | ||
926 | .last = 0x85, | ||
927 | }, | ||
928 | { | ||
929 | .first = 0x87, | ||
930 | .last = 0x88, | ||
931 | }, | ||
932 | }, | ||
933 | }, | ||
934 | [AB8500_REGU_CTRL2] = { | ||
935 | .num_ranges = 8, | ||
936 | .range = (struct ab8500_reg_range[]) { | ||
937 | { | ||
938 | .first = 0x00, | ||
939 | .last = 0x06, | ||
940 | }, | ||
941 | { | ||
942 | .first = 0x08, | ||
943 | .last = 0x15, | ||
944 | }, | ||
945 | { | ||
946 | .first = 0x17, | ||
947 | .last = 0x19, | ||
948 | }, | ||
949 | { | ||
950 | .first = 0x1B, | ||
951 | .last = 0x1D, | ||
952 | }, | ||
953 | { | ||
954 | .first = 0x1F, | ||
955 | .last = 0x2F, | ||
956 | }, | ||
957 | { | ||
958 | .first = 0x31, | ||
959 | .last = 0x3A, | ||
960 | }, | ||
961 | { | ||
962 | .first = 0x43, | ||
963 | .last = 0x44, | ||
964 | }, | ||
965 | { | ||
966 | .first = 0x48, | ||
967 | .last = 0x49, | ||
968 | }, | ||
969 | }, | ||
970 | }, | ||
971 | [AB8500_USB] = { | ||
972 | .num_ranges = 3, | ||
973 | .range = (struct ab8500_reg_range[]) { | ||
974 | { | ||
975 | .first = 0x80, | ||
976 | .last = 0x83, | ||
977 | }, | ||
978 | { | ||
979 | .first = 0x87, | ||
980 | .last = 0x8A, | ||
981 | }, | ||
982 | { | ||
983 | .first = 0x91, | ||
984 | .last = 0x94, | ||
985 | }, | ||
986 | }, | ||
987 | }, | ||
988 | [AB8500_TVOUT] = { | ||
989 | .num_ranges = 0, | ||
990 | .range = NULL | ||
991 | }, | ||
992 | [AB8500_DBI] = { | ||
993 | .num_ranges = 4, | ||
994 | .range = (struct ab8500_reg_range[]) { | ||
995 | { | ||
996 | .first = 0x00, | ||
997 | .last = 0x07, | ||
998 | }, | ||
999 | { | ||
1000 | .first = 0x10, | ||
1001 | .last = 0x11, | ||
1002 | }, | ||
1003 | { | ||
1004 | .first = 0x20, | ||
1005 | .last = 0x21, | ||
1006 | }, | ||
1007 | { | ||
1008 | .first = 0x30, | ||
1009 | .last = 0x43, | ||
1010 | }, | ||
1011 | }, | ||
1012 | }, | ||
1013 | [AB8500_ECI_AV_ACC] = { | ||
1014 | .num_ranges = 2, | ||
1015 | .range = (struct ab8500_reg_range[]) { | ||
1016 | { | ||
1017 | .first = 0x00, | ||
1018 | .last = 0x03, | ||
1019 | }, | ||
1020 | { | ||
1021 | .first = 0x80, | ||
1022 | .last = 0x82, | ||
1023 | }, | ||
1024 | }, | ||
1025 | }, | ||
1026 | [AB8500_RESERVED] = { | ||
1027 | .num_ranges = 0, | ||
1028 | .range = NULL, | ||
1029 | }, | ||
1030 | [AB8500_GPADC] = { | ||
1031 | .num_ranges = 4, | ||
1032 | .range = (struct ab8500_reg_range[]) { | ||
1033 | { | ||
1034 | .first = 0x00, | ||
1035 | .last = 0x01, | ||
1036 | }, | ||
1037 | { | ||
1038 | .first = 0x04, | ||
1039 | .last = 0x06, | ||
1040 | }, | ||
1041 | { | ||
1042 | .first = 0x09, | ||
1043 | .last = 0x0A, | ||
1044 | }, | ||
1045 | { | ||
1046 | .first = 0x10, | ||
1047 | .last = 0x14, | ||
1048 | }, | ||
1049 | }, | ||
1050 | }, | ||
1051 | [AB8500_CHARGER] = { | ||
1052 | .num_ranges = 10, | ||
1053 | .range = (struct ab8500_reg_range[]) { | ||
1054 | { | ||
1055 | .first = 0x00, | ||
1056 | .last = 0x00, | ||
1057 | }, | ||
1058 | { | ||
1059 | .first = 0x02, | ||
1060 | .last = 0x05, | ||
1061 | }, | ||
1062 | { | ||
1063 | .first = 0x40, | ||
1064 | .last = 0x44, | ||
1065 | }, | ||
1066 | { | ||
1067 | .first = 0x50, | ||
1068 | .last = 0x57, | ||
1069 | }, | ||
1070 | { | ||
1071 | .first = 0x60, | ||
1072 | .last = 0x60, | ||
1073 | }, | ||
1074 | { | ||
1075 | .first = 0x70, | ||
1076 | .last = 0x70, | ||
1077 | }, | ||
1078 | { | ||
1079 | .first = 0xA0, | ||
1080 | .last = 0xA9, | ||
1081 | }, | ||
1082 | { | ||
1083 | .first = 0xAF, | ||
1084 | .last = 0xB2, | ||
1085 | }, | ||
1086 | { | ||
1087 | .first = 0xC0, | ||
1088 | .last = 0xC6, | ||
1089 | }, | ||
1090 | { | ||
1091 | .first = 0xF5, | ||
1092 | .last = 0xF5, | ||
1093 | }, | ||
1094 | }, | ||
1095 | }, | ||
1096 | [AB8500_GAS_GAUGE] = { | ||
1097 | .num_ranges = 3, | ||
1098 | .range = (struct ab8500_reg_range[]) { | ||
1099 | { | ||
1100 | .first = 0x00, | ||
1101 | .last = 0x00, | ||
1102 | }, | ||
1103 | { | ||
1104 | .first = 0x07, | ||
1105 | .last = 0x0A, | ||
1106 | }, | ||
1107 | { | ||
1108 | .first = 0x10, | ||
1109 | .last = 0x14, | ||
1110 | }, | ||
1111 | }, | ||
1112 | }, | ||
1113 | [AB8500_AUDIO] = { | ||
1114 | .num_ranges = 1, | ||
1115 | .range = (struct ab8500_reg_range[]) { | ||
1116 | { | ||
1117 | .first = 0x00, | ||
1118 | .last = 0x9f, | ||
1119 | }, | ||
1120 | }, | ||
1121 | }, | ||
1122 | [AB8500_INTERRUPT] = { | ||
1123 | .num_ranges = 6, | ||
1124 | .range = (struct ab8500_reg_range[]) { | ||
1125 | { | ||
1126 | .first = 0x00, | ||
1127 | .last = 0x05, | ||
1128 | }, | ||
1129 | { | ||
1130 | .first = 0x0B, | ||
1131 | .last = 0x0D, | ||
1132 | }, | ||
1133 | { | ||
1134 | .first = 0x12, | ||
1135 | .last = 0x20, | ||
1136 | }, | ||
1137 | /* Latch registers should not be read here */ | ||
1138 | { | ||
1139 | .first = 0x40, | ||
1140 | .last = 0x45, | ||
1141 | }, | ||
1142 | { | ||
1143 | .first = 0x4B, | ||
1144 | .last = 0x4D, | ||
1145 | }, | ||
1146 | { | ||
1147 | .first = 0x52, | ||
1148 | .last = 0x60, | ||
1149 | }, | ||
1150 | /* LatchHier registers should not be read here */ | ||
1151 | }, | ||
1152 | }, | ||
1153 | [AB8500_RTC] = { | ||
1154 | .num_ranges = 3, | ||
1155 | .range = (struct ab8500_reg_range[]) { | ||
1156 | { | ||
1157 | .first = 0x00, | ||
1158 | .last = 0x07, | ||
1159 | }, | ||
1160 | { | ||
1161 | .first = 0x0B, | ||
1162 | .last = 0x18, | ||
1163 | }, | ||
1164 | { | ||
1165 | .first = 0x20, | ||
1166 | .last = 0x25, | ||
1167 | }, | ||
1168 | }, | ||
1169 | }, | ||
1170 | [AB8500_MISC] = { | ||
1171 | .num_ranges = 9, | ||
1172 | .range = (struct ab8500_reg_range[]) { | ||
1173 | { | ||
1174 | .first = 0x00, | ||
1175 | .last = 0x06, | ||
1176 | }, | ||
1177 | { | ||
1178 | .first = 0x10, | ||
1179 | .last = 0x16, | ||
1180 | }, | ||
1181 | { | ||
1182 | .first = 0x20, | ||
1183 | .last = 0x26, | ||
1184 | }, | ||
1185 | { | ||
1186 | .first = 0x30, | ||
1187 | .last = 0x36, | ||
1188 | }, | ||
1189 | { | ||
1190 | .first = 0x40, | ||
1191 | .last = 0x49, | ||
1192 | }, | ||
1193 | { | ||
1194 | .first = 0x50, | ||
1195 | .last = 0x50, | ||
1196 | }, | ||
1197 | { | ||
1198 | .first = 0x60, | ||
1199 | .last = 0x6B, | ||
1200 | }, | ||
1201 | { | ||
1202 | .first = 0x70, | ||
1203 | .last = 0x74, | ||
1204 | }, | ||
1205 | { | ||
1206 | .first = 0x80, | ||
1207 | .last = 0x82, | ||
1208 | }, | ||
1209 | }, | ||
1210 | }, | ||
1211 | [AB8500_DEVELOPMENT] = { | ||
1212 | .num_ranges = 3, | ||
1213 | .range = (struct ab8500_reg_range[]) { | ||
1214 | { | ||
1215 | .first = 0x00, | ||
1216 | .last = 0x01, | ||
1217 | }, | ||
1218 | { | ||
1219 | .first = 0x06, | ||
1220 | .last = 0x06, | ||
1221 | }, | ||
1222 | { | ||
1223 | .first = 0x10, | ||
1224 | .last = 0x21, | ||
1225 | }, | ||
1226 | }, | ||
1227 | }, | ||
1228 | [AB8500_DEBUG] = { | ||
1229 | .num_ranges = 3, | ||
1230 | .range = (struct ab8500_reg_range[]) { | ||
1231 | { | ||
1232 | .first = 0x01, | ||
1233 | .last = 0x0C, | ||
1234 | }, | ||
1235 | { | ||
1236 | .first = 0x0E, | ||
1237 | .last = 0x11, | ||
1238 | }, | ||
1239 | { | ||
1240 | .first = 0x80, | ||
1241 | .last = 0x81, | ||
1242 | }, | ||
1243 | }, | ||
1244 | }, | ||
1245 | [AB8500_PROD_TEST] = { | ||
1246 | .num_ranges = 0, | ||
1247 | .range = NULL, | ||
1248 | }, | ||
1249 | [AB8500_STE_TEST] = { | ||
1250 | .num_ranges = 0, | ||
1251 | .range = NULL, | ||
1252 | }, | ||
1253 | [AB8500_OTP_EMUL] = { | ||
1254 | .num_ranges = 1, | ||
1255 | .range = (struct ab8500_reg_range[]) { | ||
1256 | { | ||
1257 | .first = 0x00, | ||
1258 | .last = 0x3F, | ||
1259 | }, | ||
1260 | }, | ||
1261 | }, | ||
1262 | }; | ||
1263 | |||
1264 | |||
849 | static irqreturn_t ab8500_debug_handler(int irq, void *data) | 1265 | static irqreturn_t ab8500_debug_handler(int irq, void *data) |
850 | { | 1266 | { |
851 | char buf[16]; | 1267 | char buf[16]; |
@@ -937,7 +1353,7 @@ static int ab8500_print_all_banks(struct seq_file *s, void *p) | |||
937 | 1353 | ||
938 | seq_printf(s, AB8500_NAME_STRING " register values:\n"); | 1354 | seq_printf(s, AB8500_NAME_STRING " register values:\n"); |
939 | 1355 | ||
940 | for (i = 1; i < AB8500_NUM_BANKS; i++) { | 1356 | for (i = 0; i < AB8500_NUM_BANKS; i++) { |
941 | err = seq_printf(s, " bank 0x%02X:\n", i); | 1357 | err = seq_printf(s, " bank 0x%02X:\n", i); |
942 | 1358 | ||
943 | ab8500_registers_print(dev, i, s); | 1359 | ab8500_registers_print(dev, i, s); |
@@ -979,7 +1395,7 @@ void ab8500_dump_all_banks_to_mem(void) | |||
979 | pr_info("Saving all ABB registers at \"ab8500_complete_register_dump\" " | 1395 | pr_info("Saving all ABB registers at \"ab8500_complete_register_dump\" " |
980 | "for crash analyze.\n"); | 1396 | "for crash analyze.\n"); |
981 | 1397 | ||
982 | for (bank = 1; bank < AB8500_NUM_BANKS; bank++) { | 1398 | for (bank = 0; bank < AB8500_NUM_BANKS; bank++) { |
983 | for (i = 0; i < debug_ranges[bank].num_ranges; i++) { | 1399 | for (i = 0; i < debug_ranges[bank].num_ranges; i++) { |
984 | u8 reg; | 1400 | u8 reg; |
985 | 1401 | ||
@@ -2653,7 +3069,7 @@ static int ab8500_debug_probe(struct platform_device *plf) | |||
2653 | debug_ranges = ab8505_debug_ranges; | 3069 | debug_ranges = ab8505_debug_ranges; |
2654 | num_interrupt_lines = AB9540_NR_IRQS; | 3070 | num_interrupt_lines = AB9540_NR_IRQS; |
2655 | } else if (is_ab8540(ab8500)) { | 3071 | } else if (is_ab8540(ab8500)) { |
2656 | debug_ranges = ab8505_debug_ranges; | 3072 | debug_ranges = ab8540_debug_ranges; |
2657 | num_interrupt_lines = AB8540_NR_IRQS; | 3073 | num_interrupt_lines = AB8540_NR_IRQS; |
2658 | } | 3074 | } |
2659 | 3075 | ||