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authorMoore, Eric Dean <Eric.Moore@lsil.com>2005-05-11 19:46:52 -0400
committerJames Bottomley <jejb@mulgrave.(none)>2005-05-20 16:47:53 -0400
commit3fadc59d603caf70e7a5295158e4f6eb06dffb8f (patch)
tree1f8de49cf6af0972c8cca2cfd13dc5a95e2b79b3 /drivers/message/fusion/mptbase.c
parent793698ce28e20f4736250a9766270368beae5668 (diff)
[SCSI] fusion - Adding pci recog support for Fibre 949X and 939X chips
* adding pci id support for new Fibre chips, 949X and 939X * adding errata workaround - disabling PIO access except during fwdlb. Signed-off-by: Eric Moore <Eric.Moore@lsil.com> Signed-off-by: James Bottomley <James.Bottomley@SteelEye.com>
Diffstat (limited to 'drivers/message/fusion/mptbase.c')
-rw-r--r--drivers/message/fusion/mptbase.c41
1 files changed, 40 insertions, 1 deletions
diff --git a/drivers/message/fusion/mptbase.c b/drivers/message/fusion/mptbase.c
index d2a3c086a995..673cdd955eed 100644
--- a/drivers/message/fusion/mptbase.c
+++ b/drivers/message/fusion/mptbase.c
@@ -186,6 +186,26 @@ static void __exit fusion_exit (void);
186#define CHIPREG_PIO_WRITE32(addr,val) outl(val, (unsigned long)addr) 186#define CHIPREG_PIO_WRITE32(addr,val) outl(val, (unsigned long)addr)
187#define CHIPREG_PIO_READ32(addr) inl((unsigned long)addr) 187#define CHIPREG_PIO_READ32(addr) inl((unsigned long)addr)
188 188
189static void
190pci_disable_io_access(struct pci_dev *pdev)
191{
192 u16 command_reg;
193
194 pci_read_config_word(pdev, PCI_COMMAND, &command_reg);
195 command_reg &= ~1;
196 pci_write_config_word(pdev, PCI_COMMAND, command_reg);
197}
198
199static void
200pci_enable_io_access(struct pci_dev *pdev)
201{
202 u16 command_reg;
203
204 pci_read_config_word(pdev, PCI_COMMAND, &command_reg);
205 command_reg |= 1;
206 pci_write_config_word(pdev, PCI_COMMAND, command_reg);
207}
208
189/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/ 209/*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*/
190/* 210/*
191 * mpt_interrupt - MPT adapter (IOC) specific interrupt handler. 211 * mpt_interrupt - MPT adapter (IOC) specific interrupt handler.
@@ -1161,6 +1181,16 @@ mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1161 pcixcmd &= 0x8F; 1181 pcixcmd &= 0x8F;
1162 pci_write_config_byte(pdev, 0x6a, pcixcmd); 1182 pci_write_config_byte(pdev, 0x6a, pcixcmd);
1163 } 1183 }
1184 else if (pdev->device == MPI_MANUFACTPAGE_DEVICEID_FC939X) {
1185 ioc->prod_name = "LSIFC939X";
1186 ioc->bus_type = FC;
1187 ioc->errata_flag_1064 = 1;
1188 }
1189 else if (pdev->device == MPI_MANUFACTPAGE_DEVICEID_FC949X) {
1190 ioc->prod_name = "LSIFC949X";
1191 ioc->bus_type = FC;
1192 ioc->errata_flag_1064 = 1;
1193 }
1164 else if (pdev->device == MPI_MANUFACTPAGE_DEVID_53C1030) { 1194 else if (pdev->device == MPI_MANUFACTPAGE_DEVID_53C1030) {
1165 ioc->prod_name = "LSI53C1030"; 1195 ioc->prod_name = "LSI53C1030";
1166 ioc->bus_type = SCSI; 1196 ioc->bus_type = SCSI;
@@ -1179,6 +1209,9 @@ mpt_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1179 ioc->bus_type = SCSI; 1209 ioc->bus_type = SCSI;
1180 } 1210 }
1181 1211
1212 if (ioc->errata_flag_1064)
1213 pci_disable_io_access(pdev);
1214
1182 sprintf(ioc->name, "ioc%d", ioc->id); 1215 sprintf(ioc->name, "ioc%d", ioc->id);
1183 1216
1184 spin_lock_init(&ioc->FreeQlock); 1217 spin_lock_init(&ioc->FreeQlock);
@@ -2667,7 +2700,7 @@ mpt_downloadboot(MPT_ADAPTER *ioc, int sleepFlag)
2667 /* prevent a second downloadboot and memory free with alt_ioc */ 2700 /* prevent a second downloadboot and memory free with alt_ioc */
2668 if (ioc->alt_ioc && ioc->alt_ioc->cached_fw) 2701 if (ioc->alt_ioc && ioc->alt_ioc->cached_fw)
2669 ioc->alt_ioc->cached_fw = NULL; 2702 ioc->alt_ioc->cached_fw = NULL;
2670 2703
2671 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF); 2704 CHIPREG_WRITE32(&ioc->chip->WriteSequence, 0xFF);
2672 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE); 2705 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_1ST_KEY_VALUE);
2673 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE); 2706 CHIPREG_WRITE32(&ioc->chip->WriteSequence, MPI_WRSEQ_2ND_KEY_VALUE);
@@ -2725,6 +2758,9 @@ mpt_downloadboot(MPT_ADAPTER *ioc, int sleepFlag)
2725 /* Write the LoadStartAddress to the DiagRw Address Register 2758 /* Write the LoadStartAddress to the DiagRw Address Register
2726 * using Programmed IO 2759 * using Programmed IO
2727 */ 2760 */
2761 if (ioc->errata_flag_1064)
2762 pci_enable_io_access(ioc->pcidev);
2763
2728 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->LoadStartAddress); 2764 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, pFwHeader->LoadStartAddress);
2729 ddlprintk((MYIOC_s_INFO_FMT "LoadStart addr written 0x%x \n", 2765 ddlprintk((MYIOC_s_INFO_FMT "LoadStart addr written 0x%x \n",
2730 ioc->name, pFwHeader->LoadStartAddress)); 2766 ioc->name, pFwHeader->LoadStartAddress));
@@ -2771,6 +2807,9 @@ mpt_downloadboot(MPT_ADAPTER *ioc, int sleepFlag)
2771 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000); 2807 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwAddress, 0x3F000000);
2772 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, diagRwData); 2808 CHIPREG_PIO_WRITE32(&ioc->pio_chip->DiagRwData, diagRwData);
2773 2809
2810 if (ioc->errata_flag_1064)
2811 pci_disable_io_access(ioc->pcidev);
2812
2774 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic); 2813 diag0val = CHIPREG_READ32(&ioc->chip->Diagnostic);
2775 ddlprintk((MYIOC_s_INFO_FMT "downloadboot diag0val=%x, turning off PREVENT_IOC_BOOT, DISABLE_ARM\n", 2814 ddlprintk((MYIOC_s_INFO_FMT "downloadboot diag0val=%x, turning off PREVENT_IOC_BOOT, DISABLE_ARM\n",
2776 ioc->name, diag0val)); 2815 ioc->name, diag0val));