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authorDavid S. Miller <davem@davemloft.net>2008-03-18 03:37:55 -0400
committerDavid S. Miller <davem@davemloft.net>2008-03-18 03:37:55 -0400
commit577f99c1d08cf9cbdafd4e858dd13ff04d855090 (patch)
tree0f726bbda9b18d311d4c95198bbd96cb7ac01db0 /drivers/memstick/host
parent26c0f03f6b77c513cb7bc37b73a06819bdbb791b (diff)
parent2f633928cbba8a5858bb39b11e7219a41b0fbef5 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
Conflicts: drivers/net/wireless/rt2x00/rt2x00dev.c net/8021q/vlan_dev.c
Diffstat (limited to 'drivers/memstick/host')
-rw-r--r--drivers/memstick/host/Kconfig10
-rw-r--r--drivers/memstick/host/Makefile6
-rw-r--r--drivers/memstick/host/jmb38x_ms.c945
-rw-r--r--drivers/memstick/host/tifm_ms.c569
4 files changed, 1237 insertions, 293 deletions
diff --git a/drivers/memstick/host/Kconfig b/drivers/memstick/host/Kconfig
index c002fcc3c879..4ce5c8dffb68 100644
--- a/drivers/memstick/host/Kconfig
+++ b/drivers/memstick/host/Kconfig
@@ -20,3 +20,13 @@ config MEMSTICK_TIFM_MS
20 To compile this driver as a module, choose M here: the 20 To compile this driver as a module, choose M here: the
21 module will be called tifm_ms. 21 module will be called tifm_ms.
22 22
23config MEMSTICK_JMICRON_38X
24 tristate "JMicron JMB38X MemoryStick interface support (EXPERIMENTAL)"
25 depends on EXPERIMENTAL && PCI
26
27 help
28 Say Y here if you want to be able to access MemoryStick cards with
29 the JMicron(R) JMB38X MemoryStick card reader.
30
31 To compile this driver as a module, choose M here: the
32 module will be called jmb38x_ms.
diff --git a/drivers/memstick/host/Makefile b/drivers/memstick/host/Makefile
index ee666380efa1..12530e4311d3 100644
--- a/drivers/memstick/host/Makefile
+++ b/drivers/memstick/host/Makefile
@@ -3,8 +3,8 @@
3# 3#
4 4
5ifeq ($(CONFIG_MEMSTICK_DEBUG),y) 5ifeq ($(CONFIG_MEMSTICK_DEBUG),y)
6 EXTRA_CFLAGS += -DDEBUG 6 EXTRA_CFLAGS += -DDEBUG
7endif 7endif
8 8
9obj-$(CONFIG_MEMSTICK_TIFM_MS) += tifm_ms.o 9obj-$(CONFIG_MEMSTICK_TIFM_MS) += tifm_ms.o
10 10obj-$(CONFIG_MEMSTICK_JMICRON_38X) += jmb38x_ms.o
diff --git a/drivers/memstick/host/jmb38x_ms.c b/drivers/memstick/host/jmb38x_ms.c
new file mode 100644
index 000000000000..03fe8783b1ee
--- /dev/null
+++ b/drivers/memstick/host/jmb38x_ms.c
@@ -0,0 +1,945 @@
1/*
2 * jmb38x_ms.c - JMicron jmb38x MemoryStick card reader
3 *
4 * Copyright (C) 2008 Alex Dubov <oakad@yahoo.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <linux/spinlock.h>
13#include <linux/interrupt.h>
14#include <linux/pci.h>
15#include <linux/delay.h>
16#include <linux/highmem.h>
17#include <linux/memstick.h>
18
19#define DRIVER_NAME "jmb38x_ms"
20
21static int no_dma;
22module_param(no_dma, bool, 0644);
23
24enum {
25 DMA_ADDRESS = 0x00,
26 BLOCK = 0x04,
27 DMA_CONTROL = 0x08,
28 TPC_P0 = 0x0c,
29 TPC_P1 = 0x10,
30 TPC = 0x14,
31 HOST_CONTROL = 0x18,
32 DATA = 0x1c,
33 STATUS = 0x20,
34 INT_STATUS = 0x24,
35 INT_STATUS_ENABLE = 0x28,
36 INT_SIGNAL_ENABLE = 0x2c,
37 TIMER = 0x30,
38 TIMER_CONTROL = 0x34,
39 PAD_OUTPUT_ENABLE = 0x38,
40 PAD_PU_PD = 0x3c,
41 CLOCK_DELAY = 0x40,
42 ADMA_ADDRESS = 0x44,
43 CLOCK_CONTROL = 0x48,
44 LED_CONTROL = 0x4c,
45 VERSION = 0x50
46};
47
48struct jmb38x_ms_host {
49 struct jmb38x_ms *chip;
50 void __iomem *addr;
51 spinlock_t lock;
52 int id;
53 char host_id[DEVICE_ID_SIZE];
54 int irq;
55 unsigned int block_pos;
56 unsigned long timeout_jiffies;
57 struct timer_list timer;
58 struct memstick_request *req;
59 unsigned char eject:1,
60 use_dma:1;
61 unsigned char cmd_flags;
62 unsigned char io_pos;
63 unsigned int io_word[2];
64};
65
66struct jmb38x_ms {
67 struct pci_dev *pdev;
68 int host_cnt;
69 struct memstick_host *hosts[];
70};
71
72#define BLOCK_COUNT_MASK 0xffff0000
73#define BLOCK_SIZE_MASK 0x00000fff
74
75#define DMA_CONTROL_ENABLE 0x00000001
76
77#define TPC_DATA_SEL 0x00008000
78#define TPC_DIR 0x00004000
79#define TPC_WAIT_INT 0x00002000
80#define TPC_GET_INT 0x00000800
81#define TPC_CODE_SZ_MASK 0x00000700
82#define TPC_DATA_SZ_MASK 0x00000007
83
84#define HOST_CONTROL_RESET_REQ 0x00008000
85#define HOST_CONTROL_REI 0x00004000
86#define HOST_CONTROL_LED 0x00000400
87#define HOST_CONTROL_FAST_CLK 0x00000200
88#define HOST_CONTROL_RESET 0x00000100
89#define HOST_CONTROL_POWER_EN 0x00000080
90#define HOST_CONTROL_CLOCK_EN 0x00000040
91#define HOST_CONTROL_IF_SHIFT 4
92
93#define HOST_CONTROL_IF_SERIAL 0x0
94#define HOST_CONTROL_IF_PAR4 0x1
95#define HOST_CONTROL_IF_PAR8 0x3
96
97#define STATUS_HAS_MEDIA 0x00000400
98#define STATUS_FIFO_EMPTY 0x00000200
99#define STATUS_FIFO_FULL 0x00000100
100
101#define INT_STATUS_TPC_ERR 0x00080000
102#define INT_STATUS_CRC_ERR 0x00040000
103#define INT_STATUS_TIMER_TO 0x00020000
104#define INT_STATUS_HSK_TO 0x00010000
105#define INT_STATUS_ANY_ERR 0x00008000
106#define INT_STATUS_FIFO_WRDY 0x00000080
107#define INT_STATUS_FIFO_RRDY 0x00000040
108#define INT_STATUS_MEDIA_OUT 0x00000010
109#define INT_STATUS_MEDIA_IN 0x00000008
110#define INT_STATUS_DMA_BOUNDARY 0x00000004
111#define INT_STATUS_EOTRAN 0x00000002
112#define INT_STATUS_EOTPC 0x00000001
113
114#define INT_STATUS_ALL 0x000f801f
115
116#define PAD_OUTPUT_ENABLE_MS 0x0F3F
117
118#define PAD_PU_PD_OFF 0x7FFF0000
119#define PAD_PU_PD_ON_MS_SOCK0 0x5f8f0000
120#define PAD_PU_PD_ON_MS_SOCK1 0x0f0f0000
121
122enum {
123 CMD_READY = 0x01,
124 FIFO_READY = 0x02,
125 REG_DATA = 0x04,
126 AUTO_GET_INT = 0x08
127};
128
129static unsigned int jmb38x_ms_read_data(struct jmb38x_ms_host *host,
130 unsigned char *buf, unsigned int length)
131{
132 unsigned int off = 0;
133
134 while (host->io_pos && length) {
135 buf[off++] = host->io_word[0] & 0xff;
136 host->io_word[0] >>= 8;
137 length--;
138 host->io_pos--;
139 }
140
141 if (!length)
142 return off;
143
144 while (!(STATUS_FIFO_EMPTY & readl(host->addr + STATUS))) {
145 if (length < 4)
146 break;
147 *(unsigned int *)(buf + off) = __raw_readl(host->addr + DATA);
148 length -= 4;
149 off += 4;
150 }
151
152 if (length
153 && !(STATUS_FIFO_EMPTY & readl(host->addr + STATUS))) {
154 host->io_word[0] = readl(host->addr + DATA);
155 for (host->io_pos = 4; host->io_pos; --host->io_pos) {
156 buf[off++] = host->io_word[0] & 0xff;
157 host->io_word[0] >>= 8;
158 length--;
159 if (!length)
160 break;
161 }
162 }
163
164 return off;
165}
166
167static unsigned int jmb38x_ms_read_reg_data(struct jmb38x_ms_host *host,
168 unsigned char *buf,
169 unsigned int length)
170{
171 unsigned int off = 0;
172
173 while (host->io_pos > 4 && length) {
174 buf[off++] = host->io_word[0] & 0xff;
175 host->io_word[0] >>= 8;
176 length--;
177 host->io_pos--;
178 }
179
180 if (!length)
181 return off;
182
183 while (host->io_pos && length) {
184 buf[off++] = host->io_word[1] & 0xff;
185 host->io_word[1] >>= 8;
186 length--;
187 host->io_pos--;
188 }
189
190 return off;
191}
192
193static unsigned int jmb38x_ms_write_data(struct jmb38x_ms_host *host,
194 unsigned char *buf,
195 unsigned int length)
196{
197 unsigned int off = 0;
198
199 if (host->io_pos) {
200 while (host->io_pos < 4 && length) {
201 host->io_word[0] |= buf[off++] << (host->io_pos * 8);
202 host->io_pos++;
203 length--;
204 }
205 }
206
207 if (host->io_pos == 4
208 && !(STATUS_FIFO_FULL & readl(host->addr + STATUS))) {
209 writel(host->io_word[0], host->addr + DATA);
210 host->io_pos = 0;
211 host->io_word[0] = 0;
212 } else if (host->io_pos) {
213 return off;
214 }
215
216 if (!length)
217 return off;
218
219 while (!(STATUS_FIFO_FULL & readl(host->addr + STATUS))) {
220 if (length < 4)
221 break;
222
223 __raw_writel(*(unsigned int *)(buf + off),
224 host->addr + DATA);
225 length -= 4;
226 off += 4;
227 }
228
229 switch (length) {
230 case 3:
231 host->io_word[0] |= buf[off + 2] << 16;
232 host->io_pos++;
233 case 2:
234 host->io_word[0] |= buf[off + 1] << 8;
235 host->io_pos++;
236 case 1:
237 host->io_word[0] |= buf[off];
238 host->io_pos++;
239 }
240
241 off += host->io_pos;
242
243 return off;
244}
245
246static unsigned int jmb38x_ms_write_reg_data(struct jmb38x_ms_host *host,
247 unsigned char *buf,
248 unsigned int length)
249{
250 unsigned int off = 0;
251
252 while (host->io_pos < 4 && length) {
253 host->io_word[0] &= ~(0xff << (host->io_pos * 8));
254 host->io_word[0] |= buf[off++] << (host->io_pos * 8);
255 host->io_pos++;
256 length--;
257 }
258
259 if (!length)
260 return off;
261
262 while (host->io_pos < 8 && length) {
263 host->io_word[1] &= ~(0xff << (host->io_pos * 8));
264 host->io_word[1] |= buf[off++] << (host->io_pos * 8);
265 host->io_pos++;
266 length--;
267 }
268
269 return off;
270}
271
272static int jmb38x_ms_transfer_data(struct jmb38x_ms_host *host)
273{
274 unsigned int length;
275 unsigned int off;
276 unsigned int t_size, p_off, p_cnt;
277 unsigned char *buf;
278 struct page *pg;
279 unsigned long flags = 0;
280
281 if (host->req->long_data) {
282 length = host->req->sg.length - host->block_pos;
283 off = host->req->sg.offset + host->block_pos;
284 } else {
285 length = host->req->data_len - host->block_pos;
286 off = 0;
287 }
288
289 while (length) {
290 if (host->req->long_data) {
291 pg = nth_page(sg_page(&host->req->sg),
292 off >> PAGE_SHIFT);
293 p_off = offset_in_page(off);
294 p_cnt = PAGE_SIZE - p_off;
295 p_cnt = min(p_cnt, length);
296
297 local_irq_save(flags);
298 buf = kmap_atomic(pg, KM_BIO_SRC_IRQ) + p_off;
299 } else {
300 buf = host->req->data + host->block_pos;
301 p_cnt = host->req->data_len - host->block_pos;
302 }
303
304 if (host->req->data_dir == WRITE)
305 t_size = !(host->cmd_flags & REG_DATA)
306 ? jmb38x_ms_write_data(host, buf, p_cnt)
307 : jmb38x_ms_write_reg_data(host, buf, p_cnt);
308 else
309 t_size = !(host->cmd_flags & REG_DATA)
310 ? jmb38x_ms_read_data(host, buf, p_cnt)
311 : jmb38x_ms_read_reg_data(host, buf, p_cnt);
312
313 if (host->req->long_data) {
314 kunmap_atomic(buf - p_off, KM_BIO_SRC_IRQ);
315 local_irq_restore(flags);
316 }
317
318 if (!t_size)
319 break;
320 host->block_pos += t_size;
321 length -= t_size;
322 off += t_size;
323 }
324
325 if (!length && host->req->data_dir == WRITE) {
326 if (host->cmd_flags & REG_DATA) {
327 writel(host->io_word[0], host->addr + TPC_P0);
328 writel(host->io_word[1], host->addr + TPC_P1);
329 } else if (host->io_pos) {
330 writel(host->io_word[0], host->addr + DATA);
331 }
332 }
333
334 return length;
335}
336
337static int jmb38x_ms_issue_cmd(struct memstick_host *msh)
338{
339 struct jmb38x_ms_host *host = memstick_priv(msh);
340 unsigned char *data;
341 unsigned int data_len, cmd, t_val;
342
343 if (!(STATUS_HAS_MEDIA & readl(host->addr + STATUS))) {
344 dev_dbg(msh->cdev.dev, "no media status\n");
345 host->req->error = -ETIME;
346 return host->req->error;
347 }
348
349 dev_dbg(msh->cdev.dev, "control %08x\n",
350 readl(host->addr + HOST_CONTROL));
351 dev_dbg(msh->cdev.dev, "status %08x\n", readl(host->addr + INT_STATUS));
352 dev_dbg(msh->cdev.dev, "hstatus %08x\n", readl(host->addr + STATUS));
353
354 host->cmd_flags = 0;
355 host->block_pos = 0;
356 host->io_pos = 0;
357 host->io_word[0] = 0;
358 host->io_word[1] = 0;
359
360 cmd = host->req->tpc << 16;
361 cmd |= TPC_DATA_SEL;
362
363 if (host->req->data_dir == READ)
364 cmd |= TPC_DIR;
365 if (host->req->need_card_int)
366 cmd |= TPC_WAIT_INT;
367 if (host->req->get_int_reg)
368 cmd |= TPC_GET_INT;
369
370 data = host->req->data;
371
372 host->use_dma = !no_dma;
373
374 if (host->req->long_data) {
375 data_len = host->req->sg.length;
376 } else {
377 data_len = host->req->data_len;
378 host->use_dma = 0;
379 }
380
381 if (data_len <= 8) {
382 cmd &= ~(TPC_DATA_SEL | 0xf);
383 host->cmd_flags |= REG_DATA;
384 cmd |= data_len & 0xf;
385 host->use_dma = 0;
386 }
387
388 if (host->use_dma) {
389 if (1 != pci_map_sg(host->chip->pdev, &host->req->sg, 1,
390 host->req->data_dir == READ
391 ? PCI_DMA_FROMDEVICE
392 : PCI_DMA_TODEVICE)) {
393 host->req->error = -ENOMEM;
394 return host->req->error;
395 }
396 data_len = sg_dma_len(&host->req->sg);
397 writel(sg_dma_address(&host->req->sg),
398 host->addr + DMA_ADDRESS);
399 writel(((1 << 16) & BLOCK_COUNT_MASK)
400 | (data_len & BLOCK_SIZE_MASK),
401 host->addr + BLOCK);
402 writel(DMA_CONTROL_ENABLE, host->addr + DMA_CONTROL);
403 } else if (!(host->cmd_flags & REG_DATA)) {
404 writel(((1 << 16) & BLOCK_COUNT_MASK)
405 | (data_len & BLOCK_SIZE_MASK),
406 host->addr + BLOCK);
407 t_val = readl(host->addr + INT_STATUS_ENABLE);
408 t_val |= host->req->data_dir == READ
409 ? INT_STATUS_FIFO_RRDY
410 : INT_STATUS_FIFO_WRDY;
411
412 writel(t_val, host->addr + INT_STATUS_ENABLE);
413 writel(t_val, host->addr + INT_SIGNAL_ENABLE);
414 } else {
415 cmd &= ~(TPC_DATA_SEL | 0xf);
416 host->cmd_flags |= REG_DATA;
417 cmd |= data_len & 0xf;
418
419 if (host->req->data_dir == WRITE) {
420 jmb38x_ms_transfer_data(host);
421 writel(host->io_word[0], host->addr + TPC_P0);
422 writel(host->io_word[1], host->addr + TPC_P1);
423 }
424 }
425
426 mod_timer(&host->timer, jiffies + host->timeout_jiffies);
427 writel(HOST_CONTROL_LED | readl(host->addr + HOST_CONTROL),
428 host->addr + HOST_CONTROL);
429 host->req->error = 0;
430
431 writel(cmd, host->addr + TPC);
432 dev_dbg(msh->cdev.dev, "executing TPC %08x, len %x\n", cmd, data_len);
433
434 return 0;
435}
436
437static void jmb38x_ms_complete_cmd(struct memstick_host *msh, int last)
438{
439 struct jmb38x_ms_host *host = memstick_priv(msh);
440 unsigned int t_val = 0;
441 int rc;
442
443 del_timer(&host->timer);
444
445 dev_dbg(msh->cdev.dev, "c control %08x\n",
446 readl(host->addr + HOST_CONTROL));
447 dev_dbg(msh->cdev.dev, "c status %08x\n",
448 readl(host->addr + INT_STATUS));
449 dev_dbg(msh->cdev.dev, "c hstatus %08x\n", readl(host->addr + STATUS));
450
451 if (host->req->get_int_reg) {
452 t_val = readl(host->addr + TPC_P0);
453 host->req->int_reg = (t_val & 0xff);
454 }
455
456 if (host->use_dma) {
457 writel(0, host->addr + DMA_CONTROL);
458 pci_unmap_sg(host->chip->pdev, &host->req->sg, 1,
459 host->req->data_dir == READ
460 ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE);
461 } else {
462 t_val = readl(host->addr + INT_STATUS_ENABLE);
463 if (host->req->data_dir == READ)
464 t_val &= ~INT_STATUS_FIFO_RRDY;
465 else
466 t_val &= ~INT_STATUS_FIFO_WRDY;
467
468 writel(t_val, host->addr + INT_STATUS_ENABLE);
469 writel(t_val, host->addr + INT_SIGNAL_ENABLE);
470 }
471
472 writel((~HOST_CONTROL_LED) & readl(host->addr + HOST_CONTROL),
473 host->addr + HOST_CONTROL);
474
475 if (!last) {
476 do {
477 rc = memstick_next_req(msh, &host->req);
478 } while (!rc && jmb38x_ms_issue_cmd(msh));
479 } else {
480 do {
481 rc = memstick_next_req(msh, &host->req);
482 if (!rc)
483 host->req->error = -ETIME;
484 } while (!rc);
485 }
486}
487
488static irqreturn_t jmb38x_ms_isr(int irq, void *dev_id)
489{
490 struct memstick_host *msh = dev_id;
491 struct jmb38x_ms_host *host = memstick_priv(msh);
492 unsigned int irq_status;
493
494 spin_lock(&host->lock);
495 irq_status = readl(host->addr + INT_STATUS);
496 dev_dbg(&host->chip->pdev->dev, "irq_status = %08x\n", irq_status);
497 if (irq_status == 0 || irq_status == (~0)) {
498 spin_unlock(&host->lock);
499 return IRQ_NONE;
500 }
501
502 if (host->req) {
503 if (irq_status & INT_STATUS_ANY_ERR) {
504 if (irq_status & INT_STATUS_CRC_ERR)
505 host->req->error = -EILSEQ;
506 else
507 host->req->error = -ETIME;
508 } else {
509 if (host->use_dma) {
510 if (irq_status & INT_STATUS_EOTRAN)
511 host->cmd_flags |= FIFO_READY;
512 } else {
513 if (irq_status & (INT_STATUS_FIFO_RRDY
514 | INT_STATUS_FIFO_WRDY))
515 jmb38x_ms_transfer_data(host);
516
517 if (irq_status & INT_STATUS_EOTRAN) {
518 jmb38x_ms_transfer_data(host);
519 host->cmd_flags |= FIFO_READY;
520 }
521 }
522
523 if (irq_status & INT_STATUS_EOTPC) {
524 host->cmd_flags |= CMD_READY;
525 if (host->cmd_flags & REG_DATA) {
526 if (host->req->data_dir == READ) {
527 host->io_word[0]
528 = readl(host->addr
529 + TPC_P0);
530 host->io_word[1]
531 = readl(host->addr
532 + TPC_P1);
533 host->io_pos = 8;
534
535 jmb38x_ms_transfer_data(host);
536 }
537 host->cmd_flags |= FIFO_READY;
538 }
539 }
540 }
541 }
542
543 if (irq_status & (INT_STATUS_MEDIA_IN | INT_STATUS_MEDIA_OUT)) {
544 dev_dbg(&host->chip->pdev->dev, "media changed\n");
545 memstick_detect_change(msh);
546 }
547
548 writel(irq_status, host->addr + INT_STATUS);
549
550 if (host->req
551 && (((host->cmd_flags & CMD_READY)
552 && (host->cmd_flags & FIFO_READY))
553 || host->req->error))
554 jmb38x_ms_complete_cmd(msh, 0);
555
556 spin_unlock(&host->lock);
557 return IRQ_HANDLED;
558}
559
560static void jmb38x_ms_abort(unsigned long data)
561{
562 struct memstick_host *msh = (struct memstick_host *)data;
563 struct jmb38x_ms_host *host = memstick_priv(msh);
564 unsigned long flags;
565
566 dev_dbg(&host->chip->pdev->dev, "abort\n");
567 spin_lock_irqsave(&host->lock, flags);
568 if (host->req) {
569 host->req->error = -ETIME;
570 jmb38x_ms_complete_cmd(msh, 0);
571 }
572 spin_unlock_irqrestore(&host->lock, flags);
573}
574
575static void jmb38x_ms_request(struct memstick_host *msh)
576{
577 struct jmb38x_ms_host *host = memstick_priv(msh);
578 unsigned long flags;
579 int rc;
580
581 spin_lock_irqsave(&host->lock, flags);
582 if (host->req) {
583 spin_unlock_irqrestore(&host->lock, flags);
584 BUG();
585 return;
586 }
587
588 do {
589 rc = memstick_next_req(msh, &host->req);
590 } while (!rc && jmb38x_ms_issue_cmd(msh));
591 spin_unlock_irqrestore(&host->lock, flags);
592}
593
594static void jmb38x_ms_reset(struct jmb38x_ms_host *host)
595{
596 unsigned int host_ctl = readl(host->addr + HOST_CONTROL);
597
598 writel(host_ctl | HOST_CONTROL_RESET_REQ | HOST_CONTROL_RESET,
599 host->addr + HOST_CONTROL);
600
601 while (HOST_CONTROL_RESET_REQ
602 & (host_ctl = readl(host->addr + HOST_CONTROL))) {
603 ndelay(100);
604 dev_dbg(&host->chip->pdev->dev, "reset\n");
605 }
606
607 writel(INT_STATUS_ALL, host->addr + INT_STATUS_ENABLE);
608 writel(INT_STATUS_ALL, host->addr + INT_SIGNAL_ENABLE);
609
610 dev_dbg(&host->chip->pdev->dev, "reset\n");
611}
612
613static void jmb38x_ms_set_param(struct memstick_host *msh,
614 enum memstick_param param,
615 int value)
616{
617 struct jmb38x_ms_host *host = memstick_priv(msh);
618 unsigned int host_ctl;
619 unsigned long flags;
620
621 spin_lock_irqsave(&host->lock, flags);
622
623 switch (param) {
624 case MEMSTICK_POWER:
625 if (value == MEMSTICK_POWER_ON) {
626 jmb38x_ms_reset(host);
627
628 writel(host->id ? PAD_PU_PD_ON_MS_SOCK1
629 : PAD_PU_PD_ON_MS_SOCK0,
630 host->addr + PAD_PU_PD);
631
632 writel(PAD_OUTPUT_ENABLE_MS,
633 host->addr + PAD_OUTPUT_ENABLE);
634
635 host_ctl = readl(host->addr + HOST_CONTROL);
636 host_ctl |= 7;
637 writel(host_ctl | (HOST_CONTROL_POWER_EN
638 | HOST_CONTROL_CLOCK_EN),
639 host->addr + HOST_CONTROL);
640
641 dev_dbg(&host->chip->pdev->dev, "power on\n");
642 } else if (value == MEMSTICK_POWER_OFF) {
643 writel(readl(host->addr + HOST_CONTROL)
644 & ~(HOST_CONTROL_POWER_EN
645 | HOST_CONTROL_CLOCK_EN),
646 host->addr + HOST_CONTROL);
647 writel(0, host->addr + PAD_OUTPUT_ENABLE);
648 writel(PAD_PU_PD_OFF, host->addr + PAD_PU_PD);
649 dev_dbg(&host->chip->pdev->dev, "power off\n");
650 }
651 break;
652 case MEMSTICK_INTERFACE:
653 /* jmb38x_ms_reset(host); */
654
655 host_ctl = readl(host->addr + HOST_CONTROL);
656 host_ctl &= ~(3 << HOST_CONTROL_IF_SHIFT);
657 /* host_ctl |= 7; */
658
659 if (value == MEMSTICK_SERIAL) {
660 host_ctl &= ~HOST_CONTROL_FAST_CLK;
661 host_ctl |= HOST_CONTROL_IF_SERIAL
662 << HOST_CONTROL_IF_SHIFT;
663 host_ctl |= HOST_CONTROL_REI;
664 writel(0, host->addr + CLOCK_DELAY);
665 } else if (value == MEMSTICK_PAR4) {
666 host_ctl |= HOST_CONTROL_FAST_CLK;
667 host_ctl |= HOST_CONTROL_IF_PAR4
668 << HOST_CONTROL_IF_SHIFT;
669 host_ctl &= ~HOST_CONTROL_REI;
670 writel(4, host->addr + CLOCK_DELAY);
671 } else if (value == MEMSTICK_PAR8) {
672 host_ctl |= HOST_CONTROL_FAST_CLK;
673 host_ctl |= HOST_CONTROL_IF_PAR8
674 << HOST_CONTROL_IF_SHIFT;
675 host_ctl &= ~HOST_CONTROL_REI;
676 writel(4, host->addr + CLOCK_DELAY);
677 }
678 writel(host_ctl, host->addr + HOST_CONTROL);
679 break;
680 };
681
682 spin_unlock_irqrestore(&host->lock, flags);
683}
684
685#ifdef CONFIG_PM
686
687static int jmb38x_ms_suspend(struct pci_dev *dev, pm_message_t state)
688{
689 struct jmb38x_ms *jm = pci_get_drvdata(dev);
690 int cnt;
691
692 for (cnt = 0; cnt < jm->host_cnt; ++cnt) {
693 if (!jm->hosts[cnt])
694 break;
695 memstick_suspend_host(jm->hosts[cnt]);
696 }
697
698 pci_save_state(dev);
699 pci_enable_wake(dev, pci_choose_state(dev, state), 0);
700 pci_disable_device(dev);
701 pci_set_power_state(dev, pci_choose_state(dev, state));
702 return 0;
703}
704
705static int jmb38x_ms_resume(struct pci_dev *dev)
706{
707 struct jmb38x_ms *jm = pci_get_drvdata(dev);
708 int rc;
709
710 pci_set_power_state(dev, PCI_D0);
711 pci_restore_state(dev);
712 rc = pci_enable_device(dev);
713 if (rc)
714 return rc;
715 pci_set_master(dev);
716
717 pci_read_config_dword(dev, 0xac, &rc);
718 pci_write_config_dword(dev, 0xac, rc | 0x00470000);
719
720 for (rc = 0; rc < jm->host_cnt; ++rc) {
721 if (!jm->hosts[rc])
722 break;
723 memstick_resume_host(jm->hosts[rc]);
724 memstick_detect_change(jm->hosts[rc]);
725 }
726
727 return 0;
728}
729
730#else
731
732#define jmb38x_ms_suspend NULL
733#define jmb38x_ms_resume NULL
734
735#endif /* CONFIG_PM */
736
737static int jmb38x_ms_count_slots(struct pci_dev *pdev)
738{
739 int cnt, rc = 0;
740
741 for (cnt = 0; cnt < PCI_ROM_RESOURCE; ++cnt) {
742 if (!(IORESOURCE_MEM & pci_resource_flags(pdev, cnt)))
743 break;
744
745 if (256 != pci_resource_len(pdev, cnt))
746 break;
747
748 ++rc;
749 }
750 return rc;
751}
752
753static struct memstick_host *jmb38x_ms_alloc_host(struct jmb38x_ms *jm, int cnt)
754{
755 struct memstick_host *msh;
756 struct jmb38x_ms_host *host;
757
758 msh = memstick_alloc_host(sizeof(struct jmb38x_ms_host),
759 &jm->pdev->dev);
760 if (!msh)
761 return NULL;
762
763 host = memstick_priv(msh);
764 host->chip = jm;
765 host->addr = ioremap(pci_resource_start(jm->pdev, cnt),
766 pci_resource_len(jm->pdev, cnt));
767 if (!host->addr)
768 goto err_out_free;
769
770 spin_lock_init(&host->lock);
771 host->id = cnt;
772 snprintf(host->host_id, DEVICE_ID_SIZE, DRIVER_NAME ":slot%d",
773 host->id);
774 host->irq = jm->pdev->irq;
775 host->timeout_jiffies = msecs_to_jiffies(4000);
776 msh->request = jmb38x_ms_request;
777 msh->set_param = jmb38x_ms_set_param;
778 /*
779 msh->caps = MEMSTICK_CAP_AUTO_GET_INT | MEMSTICK_CAP_PAR4
780 | MEMSTICK_CAP_PAR8;
781 */
782 msh->caps = MEMSTICK_CAP_PAR4 | MEMSTICK_CAP_PAR8;
783
784 setup_timer(&host->timer, jmb38x_ms_abort, (unsigned long)msh);
785
786 if (!request_irq(host->irq, jmb38x_ms_isr, IRQF_SHARED, host->host_id,
787 msh))
788 return msh;
789
790 iounmap(host->addr);
791err_out_free:
792 kfree(msh);
793 return NULL;
794}
795
796static void jmb38x_ms_free_host(struct memstick_host *msh)
797{
798 struct jmb38x_ms_host *host = memstick_priv(msh);
799
800 free_irq(host->irq, msh);
801 iounmap(host->addr);
802 memstick_free_host(msh);
803}
804
805static int jmb38x_ms_probe(struct pci_dev *pdev,
806 const struct pci_device_id *dev_id)
807{
808 struct jmb38x_ms *jm;
809 int pci_dev_busy = 0;
810 int rc, cnt;
811
812 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
813 if (rc)
814 return rc;
815
816 rc = pci_enable_device(pdev);
817 if (rc)
818 return rc;
819
820 pci_set_master(pdev);
821
822 rc = pci_request_regions(pdev, DRIVER_NAME);
823 if (rc) {
824 pci_dev_busy = 1;
825 goto err_out;
826 }
827
828 pci_read_config_dword(pdev, 0xac, &rc);
829 pci_write_config_dword(pdev, 0xac, rc | 0x00470000);
830
831 cnt = jmb38x_ms_count_slots(pdev);
832 if (!cnt) {
833 rc = -ENODEV;
834 pci_dev_busy = 1;
835 goto err_out;
836 }
837
838 jm = kzalloc(sizeof(struct jmb38x_ms)
839 + cnt * sizeof(struct memstick_host *), GFP_KERNEL);
840 if (!jm) {
841 rc = -ENOMEM;
842 goto err_out_int;
843 }
844
845 jm->pdev = pdev;
846 jm->host_cnt = cnt;
847 pci_set_drvdata(pdev, jm);
848
849 for (cnt = 0; cnt < jm->host_cnt; ++cnt) {
850 jm->hosts[cnt] = jmb38x_ms_alloc_host(jm, cnt);
851 if (!jm->hosts[cnt])
852 break;
853
854 rc = memstick_add_host(jm->hosts[cnt]);
855
856 if (rc) {
857 jmb38x_ms_free_host(jm->hosts[cnt]);
858 jm->hosts[cnt] = NULL;
859 break;
860 }
861 }
862
863 if (cnt)
864 return 0;
865
866 rc = -ENODEV;
867
868 pci_set_drvdata(pdev, NULL);
869 kfree(jm);
870err_out_int:
871 pci_release_regions(pdev);
872err_out:
873 if (!pci_dev_busy)
874 pci_disable_device(pdev);
875 return rc;
876}
877
878static void jmb38x_ms_remove(struct pci_dev *dev)
879{
880 struct jmb38x_ms *jm = pci_get_drvdata(dev);
881 struct jmb38x_ms_host *host;
882 int cnt;
883 unsigned long flags;
884
885 for (cnt = 0; cnt < jm->host_cnt; ++cnt) {
886 if (!jm->hosts[cnt])
887 break;
888
889 host = memstick_priv(jm->hosts[cnt]);
890
891 writel(0, host->addr + INT_SIGNAL_ENABLE);
892 writel(0, host->addr + INT_STATUS_ENABLE);
893 mmiowb();
894 dev_dbg(&jm->pdev->dev, "interrupts off\n");
895 spin_lock_irqsave(&host->lock, flags);
896 if (host->req) {
897 host->req->error = -ETIME;
898 jmb38x_ms_complete_cmd(jm->hosts[cnt], 1);
899 }
900 spin_unlock_irqrestore(&host->lock, flags);
901
902 memstick_remove_host(jm->hosts[cnt]);
903 dev_dbg(&jm->pdev->dev, "host removed\n");
904
905 jmb38x_ms_free_host(jm->hosts[cnt]);
906 }
907
908 pci_set_drvdata(dev, NULL);
909 pci_release_regions(dev);
910 pci_disable_device(dev);
911 kfree(jm);
912}
913
914static struct pci_device_id jmb38x_ms_id_tbl [] = {
915 { PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_MS, PCI_ANY_ID,
916 PCI_ANY_ID, 0, 0, 0 },
917 { }
918};
919
920static struct pci_driver jmb38x_ms_driver = {
921 .name = DRIVER_NAME,
922 .id_table = jmb38x_ms_id_tbl,
923 .probe = jmb38x_ms_probe,
924 .remove = jmb38x_ms_remove,
925 .suspend = jmb38x_ms_suspend,
926 .resume = jmb38x_ms_resume
927};
928
929static int __init jmb38x_ms_init(void)
930{
931 return pci_register_driver(&jmb38x_ms_driver);
932}
933
934static void __exit jmb38x_ms_exit(void)
935{
936 pci_unregister_driver(&jmb38x_ms_driver);
937}
938
939MODULE_AUTHOR("Alex Dubov");
940MODULE_DESCRIPTION("JMicron jmb38x MemoryStick driver");
941MODULE_LICENSE("GPL");
942MODULE_DEVICE_TABLE(pci, jmb38x_ms_id_tbl);
943
944module_init(jmb38x_ms_init);
945module_exit(jmb38x_ms_exit);
diff --git a/drivers/memstick/host/tifm_ms.c b/drivers/memstick/host/tifm_ms.c
index 4fb24215bd95..2b5bf52a8302 100644
--- a/drivers/memstick/host/tifm_ms.c
+++ b/drivers/memstick/host/tifm_ms.c
@@ -20,293 +20,315 @@
20#include <asm/io.h> 20#include <asm/io.h>
21 21
22#define DRIVER_NAME "tifm_ms" 22#define DRIVER_NAME "tifm_ms"
23#define DRIVER_VERSION "0.1"
24 23
25static int no_dma; 24static int no_dma;
26module_param(no_dma, bool, 0644); 25module_param(no_dma, bool, 0644);
27 26
28#define TIFM_MS_TIMEOUT 0x00100 27/*
29#define TIFM_MS_BADCRC 0x00200 28 * Some control bits of TIFM appear to conform to Sony's reference design,
30#define TIFM_MS_EOTPC 0x01000 29 * so I'm just assuming they all are.
31#define TIFM_MS_INT 0x02000 30 */
32
33/* The meaning of the bit majority in this constant is unknown. */
34#define TIFM_MS_SERIAL 0x04010
35 31
36#define TIFM_MS_SYS_LATCH 0x00100 32#define TIFM_MS_STAT_DRQ 0x04000
37#define TIFM_MS_SYS_NOT_RDY 0x00800 33#define TIFM_MS_STAT_MSINT 0x02000
38#define TIFM_MS_SYS_DATA 0x10000 34#define TIFM_MS_STAT_RDY 0x01000
35#define TIFM_MS_STAT_CRC 0x00200
36#define TIFM_MS_STAT_TOE 0x00100
37#define TIFM_MS_STAT_EMP 0x00020
38#define TIFM_MS_STAT_FUL 0x00010
39#define TIFM_MS_STAT_CED 0x00008
40#define TIFM_MS_STAT_ERR 0x00004
41#define TIFM_MS_STAT_BRQ 0x00002
42#define TIFM_MS_STAT_CNK 0x00001
43
44#define TIFM_MS_SYS_DMA 0x10000
45#define TIFM_MS_SYS_RESET 0x08000
46#define TIFM_MS_SYS_SRAC 0x04000
47#define TIFM_MS_SYS_INTEN 0x02000
48#define TIFM_MS_SYS_NOCRC 0x01000
49#define TIFM_MS_SYS_INTCLR 0x00800
50#define TIFM_MS_SYS_MSIEN 0x00400
51#define TIFM_MS_SYS_FCLR 0x00200
52#define TIFM_MS_SYS_FDIR 0x00100
53#define TIFM_MS_SYS_DAM 0x00080
54#define TIFM_MS_SYS_DRM 0x00040
55#define TIFM_MS_SYS_DRQSL 0x00020
56#define TIFM_MS_SYS_REI 0x00010
57#define TIFM_MS_SYS_REO 0x00008
58#define TIFM_MS_SYS_BSY_MASK 0x00007
59
60#define TIFM_MS_SYS_FIFO (TIFM_MS_SYS_INTEN | TIFM_MS_SYS_MSIEN \
61 | TIFM_MS_SYS_FCLR | TIFM_MS_SYS_BSY_MASK)
39 62
40/* Hardware flags */ 63/* Hardware flags */
41enum { 64enum {
42 CMD_READY = 0x0001, 65 CMD_READY = 0x01,
43 FIFO_READY = 0x0002, 66 FIFO_READY = 0x02,
44 CARD_READY = 0x0004, 67 CARD_INT = 0x04
45 DATA_CARRY = 0x0008
46}; 68};
47 69
48struct tifm_ms { 70struct tifm_ms {
49 struct tifm_dev *dev; 71 struct tifm_dev *dev;
50 unsigned short eject:1, 72 struct timer_list timer;
51 no_dma:1; 73 struct memstick_request *req;
52 unsigned short cmd_flags;
53 unsigned int mode_mask; 74 unsigned int mode_mask;
54 unsigned int block_pos; 75 unsigned int block_pos;
55 unsigned long timeout_jiffies; 76 unsigned long timeout_jiffies;
56 77 unsigned char eject:1,
57 struct timer_list timer; 78 use_dma:1;
58 struct memstick_request *req; 79 unsigned char cmd_flags;
80 unsigned char io_pos;
59 unsigned int io_word; 81 unsigned int io_word;
60}; 82};
61 83
62static void tifm_ms_read_fifo(struct tifm_ms *host, unsigned int fifo_offset, 84static unsigned int tifm_ms_read_data(struct tifm_ms *host,
63 struct page *pg, unsigned int page_off, 85 unsigned char *buf, unsigned int length)
64 unsigned int length)
65{ 86{
66 struct tifm_dev *sock = host->dev; 87 struct tifm_dev *sock = host->dev;
67 unsigned int cnt = 0, off = 0; 88 unsigned int off = 0;
68 unsigned char *buf = kmap_atomic(pg, KM_BIO_DST_IRQ) + page_off; 89
90 while (host->io_pos && length) {
91 buf[off++] = host->io_word & 0xff;
92 host->io_word >>= 8;
93 length--;
94 host->io_pos--;
95 }
69 96
70 if (host->cmd_flags & DATA_CARRY) { 97 if (!length)
71 while ((fifo_offset & 3) && length) { 98 return off;
99
100 while (!(TIFM_MS_STAT_EMP & readl(sock->addr + SOCK_MS_STATUS))) {
101 if (length < 4)
102 break;
103 *(unsigned int *)(buf + off) = __raw_readl(sock->addr
104 + SOCK_MS_DATA);
105 length -= 4;
106 off += 4;
107 }
108
109 if (length
110 && !(TIFM_MS_STAT_EMP & readl(sock->addr + SOCK_MS_STATUS))) {
111 host->io_word = readl(sock->addr + SOCK_MS_DATA);
112 for (host->io_pos = 4; host->io_pos; --host->io_pos) {
72 buf[off++] = host->io_word & 0xff; 113 buf[off++] = host->io_word & 0xff;
73 host->io_word >>= 8; 114 host->io_word >>= 8;
74 length--; 115 length--;
75 fifo_offset++; 116 if (!length)
117 break;
76 } 118 }
77 if (!(fifo_offset & 3))
78 host->cmd_flags &= ~DATA_CARRY;
79 if (!length)
80 return;
81 } 119 }
82 120
83 do { 121 return off;
84 host->io_word = readl(sock->addr + SOCK_FIFO_ACCESS
85 + fifo_offset);
86 cnt = 4;
87 while (length && cnt) {
88 buf[off++] = (host->io_word >> 8) & 0xff;
89 cnt--;
90 length--;
91 }
92 fifo_offset += 4 - cnt;
93 } while (length);
94
95 if (cnt)
96 host->cmd_flags |= DATA_CARRY;
97
98 kunmap_atomic(buf - page_off, KM_BIO_DST_IRQ);
99} 122}
100 123
101static void tifm_ms_write_fifo(struct tifm_ms *host, unsigned int fifo_offset, 124static unsigned int tifm_ms_write_data(struct tifm_ms *host,
102 struct page *pg, unsigned int page_off, 125 unsigned char *buf, unsigned int length)
103 unsigned int length)
104{ 126{
105 struct tifm_dev *sock = host->dev; 127 struct tifm_dev *sock = host->dev;
106 unsigned int cnt = 0, off = 0; 128 unsigned int off = 0;
107 unsigned char *buf = kmap_atomic(pg, KM_BIO_SRC_IRQ) + page_off;
108 129
109 if (host->cmd_flags & DATA_CARRY) { 130 if (host->io_pos) {
110 while (fifo_offset & 3) { 131 while (host->io_pos < 4 && length) {
111 host->io_word |= buf[off++] << (8 * (fifo_offset & 3)); 132 host->io_word |= buf[off++] << (host->io_pos * 8);
133 host->io_pos++;
112 length--; 134 length--;
113 fifo_offset++;
114 } 135 }
115 if (!(fifo_offset & 3)) {
116 writel(host->io_word, sock->addr + SOCK_FIFO_ACCESS
117 + fifo_offset - 4);
118
119 host->cmd_flags &= ~DATA_CARRY;
120 }
121 if (!length)
122 return;
123 } 136 }
124 137
125 do { 138 if (host->io_pos == 4
126 cnt = 4; 139 && !(TIFM_MS_STAT_FUL & readl(sock->addr + SOCK_MS_STATUS))) {
140 writel(TIFM_MS_SYS_FDIR | readl(sock->addr + SOCK_MS_SYSTEM),
141 sock->addr + SOCK_MS_SYSTEM);
142 writel(host->io_word, sock->addr + SOCK_MS_DATA);
143 host->io_pos = 0;
127 host->io_word = 0; 144 host->io_word = 0;
128 while (length && cnt) { 145 } else if (host->io_pos) {
129 host->io_word |= buf[off++] << (4 - cnt); 146 return off;
130 cnt--; 147 }
131 length--;
132 }
133 fifo_offset += 4 - cnt;
134 if (!cnt)
135 writel(host->io_word, sock->addr + SOCK_FIFO_ACCESS
136 + fifo_offset - 4);
137
138 } while (length);
139
140 if (cnt)
141 host->cmd_flags |= DATA_CARRY;
142 148
143 kunmap_atomic(buf - page_off, KM_BIO_SRC_IRQ); 149 if (!length)
144} 150 return off;
145 151
146static void tifm_ms_move_block(struct tifm_ms *host, unsigned int length) 152 while (!(TIFM_MS_STAT_FUL & readl(sock->addr + SOCK_MS_STATUS))) {
147{ 153 if (length < 4)
148 unsigned int t_size; 154 break;
149 unsigned int off = host->req->sg.offset + host->block_pos; 155 writel(TIFM_MS_SYS_FDIR | readl(sock->addr + SOCK_MS_SYSTEM),
150 unsigned int p_off, p_cnt; 156 sock->addr + SOCK_MS_SYSTEM);
151 struct page *pg; 157 __raw_writel(*(unsigned int *)(buf + off),
152 unsigned long flags; 158 sock->addr + SOCK_MS_DATA);
159 length -= 4;
160 off += 4;
161 }
153 162
154 dev_dbg(&host->dev->dev, "moving block\n"); 163 switch (length) {
155 local_irq_save(flags); 164 case 3:
156 t_size = length; 165 host->io_word |= buf[off + 2] << 16;
157 while (t_size) { 166 host->io_pos++;
158 pg = nth_page(sg_page(&host->req->sg), off >> PAGE_SHIFT); 167 case 2:
159 p_off = offset_in_page(off); 168 host->io_word |= buf[off + 1] << 8;
160 p_cnt = PAGE_SIZE - p_off; 169 host->io_pos++;
161 p_cnt = min(p_cnt, t_size); 170 case 1:
171 host->io_word |= buf[off];
172 host->io_pos++;
173 }
162 174
163 if (host->req->data_dir == WRITE) 175 off += host->io_pos;
164 tifm_ms_write_fifo(host, length - t_size,
165 pg, p_off, p_cnt);
166 else
167 tifm_ms_read_fifo(host, length - t_size,
168 pg, p_off, p_cnt);
169 176
170 t_size -= p_cnt; 177 return off;
171 }
172 local_irq_restore(flags);
173} 178}
174 179
175static int tifm_ms_transfer_data(struct tifm_ms *host, int skip) 180static unsigned int tifm_ms_transfer_data(struct tifm_ms *host)
176{ 181{
177 struct tifm_dev *sock = host->dev; 182 struct tifm_dev *sock = host->dev;
178 unsigned int length = host->req->sg.length - host->block_pos; 183 unsigned int length;
184 unsigned int off;
185 unsigned int t_size, p_off, p_cnt;
186 unsigned char *buf;
187 struct page *pg;
188 unsigned long flags = 0;
189
190 if (host->req->long_data) {
191 length = host->req->sg.length - host->block_pos;
192 off = host->req->sg.offset + host->block_pos;
193 } else {
194 length = host->req->data_len - host->block_pos;
195 off = 0;
196 }
197 dev_dbg(&sock->dev, "fifo data transfer, %d, %d\n", length,
198 host->block_pos);
199
200 while (length) {
201 if (host->req->long_data) {
202 pg = nth_page(sg_page(&host->req->sg),
203 off >> PAGE_SHIFT);
204 p_off = offset_in_page(off);
205 p_cnt = PAGE_SIZE - p_off;
206 p_cnt = min(p_cnt, length);
207
208 local_irq_save(flags);
209 buf = kmap_atomic(pg, KM_BIO_SRC_IRQ) + p_off;
210 } else {
211 buf = host->req->data + host->block_pos;
212 p_cnt = host->req->data_len - host->block_pos;
213 }
179 214
180 if (!length) 215 t_size = host->req->data_dir == WRITE
181 return 1; 216 ? tifm_ms_write_data(host, buf, p_cnt)
217 : tifm_ms_read_data(host, buf, p_cnt);
182 218
183 if (length > TIFM_FIFO_SIZE) 219 if (host->req->long_data) {
184 length = TIFM_FIFO_SIZE; 220 kunmap_atomic(buf - p_off, KM_BIO_SRC_IRQ);
221 local_irq_restore(flags);
222 }
185 223
186 if (!skip) { 224 if (!t_size)
187 tifm_ms_move_block(host, length); 225 break;
188 host->block_pos += length; 226 host->block_pos += t_size;
227 length -= t_size;
228 off += t_size;
189 } 229 }
190 230
191 if ((host->req->data_dir == READ) 231 dev_dbg(&sock->dev, "fifo data transfer, %d remaining\n", length);
192 && (host->block_pos == host->req->sg.length)) 232 if (!length && (host->req->data_dir == WRITE)) {
193 return 1; 233 if (host->io_pos) {
194 234 writel(TIFM_MS_SYS_FDIR
195 writel(ilog2(length) - 2, sock->addr + SOCK_FIFO_PAGE_SIZE); 235 | readl(sock->addr + SOCK_MS_SYSTEM),
196 if (host->req->data_dir == WRITE) 236 sock->addr + SOCK_MS_SYSTEM);
197 writel((1 << 8) | TIFM_DMA_TX, sock->addr + SOCK_DMA_CONTROL); 237 writel(host->io_word, sock->addr + SOCK_MS_DATA);
198 else 238 }
199 writel((1 << 8), sock->addr + SOCK_DMA_CONTROL); 239 writel(TIFM_MS_SYS_FDIR
240 | readl(sock->addr + SOCK_MS_SYSTEM),
241 sock->addr + SOCK_MS_SYSTEM);
242 writel(0, sock->addr + SOCK_MS_DATA);
243 } else {
244 readl(sock->addr + SOCK_MS_DATA);
245 }
200 246
201 return 0; 247 return length;
202} 248}
203 249
204static int tifm_ms_issue_cmd(struct tifm_ms *host) 250static int tifm_ms_issue_cmd(struct tifm_ms *host)
205{ 251{
206 struct tifm_dev *sock = host->dev; 252 struct tifm_dev *sock = host->dev;
207 unsigned char *data; 253 unsigned char *data;
208 unsigned int data_len = 0, cmd = 0, cmd_mask = 0, cnt, tval = 0; 254 unsigned int data_len, cmd, sys_param;
209 255
210 host->cmd_flags = 0; 256 host->cmd_flags = 0;
257 host->block_pos = 0;
258 host->io_pos = 0;
259 host->io_word = 0;
260 host->cmd_flags = 0;
211 261
212 if (host->req->io_type == MEMSTICK_IO_SG) { 262 data = host->req->data;
213 if (!host->no_dma) {
214 if (1 != tifm_map_sg(sock, &host->req->sg, 1,
215 host->req->data_dir == READ
216 ? PCI_DMA_FROMDEVICE
217 : PCI_DMA_TODEVICE)) {
218 host->req->error = -ENOMEM;
219 return host->req->error;
220 }
221 data_len = sg_dma_len(&host->req->sg);
222 } else
223 data_len = host->req->sg.length;
224
225 writel(TIFM_FIFO_INT_SETALL,
226 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
227 writel(TIFM_FIFO_ENABLE,
228 sock->addr + SOCK_FIFO_CONTROL);
229 writel(TIFM_FIFO_INTMASK,
230 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
231 263
232 if (!host->no_dma) { 264 host->use_dma = !no_dma;
233 writel(ilog2(data_len) - 2,
234 sock->addr + SOCK_FIFO_PAGE_SIZE);
235 writel(sg_dma_address(&host->req->sg),
236 sock->addr + SOCK_DMA_ADDRESS);
237 if (host->req->data_dir == WRITE)
238 writel((1 << 8) | TIFM_DMA_TX | TIFM_DMA_EN,
239 sock->addr + SOCK_DMA_CONTROL);
240 else
241 writel((1 << 8) | TIFM_DMA_EN,
242 sock->addr + SOCK_DMA_CONTROL);
243 } else {
244 tifm_ms_transfer_data(host,
245 host->req->data_dir == READ);
246 }
247 265
248 cmd_mask = readl(sock->addr + SOCK_MS_SYSTEM); 266 if (host->req->long_data) {
249 cmd_mask |= TIFM_MS_SYS_DATA | TIFM_MS_SYS_NOT_RDY; 267 data_len = host->req->sg.length;
250 writel(cmd_mask, sock->addr + SOCK_MS_SYSTEM); 268 if (!is_power_of_2(data_len))
251 } else if (host->req->io_type == MEMSTICK_IO_VAL) { 269 host->use_dma = 0;
252 data = host->req->data; 270 } else {
253 data_len = host->req->data_len; 271 data_len = host->req->data_len;
272 host->use_dma = 0;
273 }
254 274
255 cmd_mask = host->mode_mask | 0x2607; /* unknown constant */ 275 writel(TIFM_FIFO_INT_SETALL,
256 276 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
257 if (host->req->data_dir == WRITE) { 277 writel(TIFM_FIFO_ENABLE,
258 cmd_mask |= TIFM_MS_SYS_LATCH; 278 sock->addr + SOCK_FIFO_CONTROL);
259 writel(cmd_mask, sock->addr + SOCK_MS_SYSTEM); 279
260 for (cnt = 0; (data_len - cnt) >= 4; cnt += 4) { 280 if (host->use_dma) {
261 writel(TIFM_MS_SYS_LATCH 281 if (1 != tifm_map_sg(sock, &host->req->sg, 1,
262 | readl(sock->addr + SOCK_MS_SYSTEM), 282 host->req->data_dir == READ
263 sock->addr + SOCK_MS_SYSTEM); 283 ? PCI_DMA_FROMDEVICE
264 __raw_writel(*(unsigned int *)(data + cnt), 284 : PCI_DMA_TODEVICE)) {
265 sock->addr + SOCK_MS_DATA); 285 host->req->error = -ENOMEM;
266 dev_dbg(&sock->dev, "writing %x\n", 286 return host->req->error;
267 *(int *)(data + cnt)); 287 }
268 } 288 data_len = sg_dma_len(&host->req->sg);
269 switch (data_len - cnt) {
270 case 3:
271 tval |= data[cnt + 2] << 16;
272 case 2:
273 tval |= data[cnt + 1] << 8;
274 case 1:
275 tval |= data[cnt];
276 writel(TIFM_MS_SYS_LATCH
277 | readl(sock->addr + SOCK_MS_SYSTEM),
278 sock->addr + SOCK_MS_SYSTEM);
279 writel(tval, sock->addr + SOCK_MS_DATA);
280 dev_dbg(&sock->dev, "writing %x\n", tval);
281 }
282 289
283 writel(TIFM_MS_SYS_LATCH 290 writel(ilog2(data_len) - 2,
284 | readl(sock->addr + SOCK_MS_SYSTEM), 291 sock->addr + SOCK_FIFO_PAGE_SIZE);
285 sock->addr + SOCK_MS_SYSTEM); 292 writel(TIFM_FIFO_INTMASK,
286 writel(0, sock->addr + SOCK_MS_DATA); 293 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
287 dev_dbg(&sock->dev, "writing %x\n", 0); 294 sys_param = TIFM_DMA_EN | (1 << 8);
295 if (host->req->data_dir == WRITE)
296 sys_param |= TIFM_DMA_TX;
297
298 writel(TIFM_FIFO_INTMASK,
299 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
288 300
289 } else 301 writel(sg_dma_address(&host->req->sg),
290 writel(cmd_mask, sock->addr + SOCK_MS_SYSTEM); 302 sock->addr + SOCK_DMA_ADDRESS);
303 writel(sys_param, sock->addr + SOCK_DMA_CONTROL);
304 } else {
305 writel(host->mode_mask | TIFM_MS_SYS_FIFO,
306 sock->addr + SOCK_MS_SYSTEM);
291 307
292 cmd_mask = readl(sock->addr + SOCK_MS_SYSTEM); 308 writel(TIFM_FIFO_MORE,
293 cmd_mask &= ~TIFM_MS_SYS_DATA; 309 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
294 cmd_mask |= TIFM_MS_SYS_NOT_RDY; 310 }
295 dev_dbg(&sock->dev, "mask %x\n", cmd_mask);
296 writel(cmd_mask, sock->addr + SOCK_MS_SYSTEM);
297 } else
298 BUG();
299 311
300 mod_timer(&host->timer, jiffies + host->timeout_jiffies); 312 mod_timer(&host->timer, jiffies + host->timeout_jiffies);
301 writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL), 313 writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
302 sock->addr + SOCK_CONTROL); 314 sock->addr + SOCK_CONTROL);
303 host->req->error = 0; 315 host->req->error = 0;
304 316
317 sys_param = readl(sock->addr + SOCK_MS_SYSTEM);
318 sys_param |= TIFM_MS_SYS_INTCLR;
319
320 if (host->use_dma)
321 sys_param |= TIFM_MS_SYS_DMA;
322 else
323 sys_param &= ~TIFM_MS_SYS_DMA;
324
325 writel(sys_param, sock->addr + SOCK_MS_SYSTEM);
326
305 cmd = (host->req->tpc & 0xf) << 12; 327 cmd = (host->req->tpc & 0xf) << 12;
306 cmd |= data_len; 328 cmd |= data_len;
307 writel(cmd, sock->addr + SOCK_MS_COMMAND); 329 writel(cmd, sock->addr + SOCK_MS_COMMAND);
308 330
309 dev_dbg(&sock->dev, "executing TPC %x, %x\n", cmd, cmd_mask); 331 dev_dbg(&sock->dev, "executing TPC %x, %x\n", cmd, sys_param);
310 return 0; 332 return 0;
311} 333}
312 334
@@ -314,47 +336,20 @@ static void tifm_ms_complete_cmd(struct tifm_ms *host)
314{ 336{
315 struct tifm_dev *sock = host->dev; 337 struct tifm_dev *sock = host->dev;
316 struct memstick_host *msh = tifm_get_drvdata(sock); 338 struct memstick_host *msh = tifm_get_drvdata(sock);
317 unsigned int tval = 0, data_len;
318 unsigned char *data;
319 int rc; 339 int rc;
320 340
321 del_timer(&host->timer); 341 del_timer(&host->timer);
322 if (host->req->io_type == MEMSTICK_IO_SG) {
323 if (!host->no_dma)
324 tifm_unmap_sg(sock, &host->req->sg, 1,
325 host->req->data_dir == READ
326 ? PCI_DMA_FROMDEVICE
327 : PCI_DMA_TODEVICE);
328 } else if (host->req->io_type == MEMSTICK_IO_VAL) {
329 writel(~TIFM_MS_SYS_DATA & readl(sock->addr + SOCK_MS_SYSTEM),
330 sock->addr + SOCK_MS_SYSTEM);
331
332 data = host->req->data;
333 data_len = host->req->data_len;
334 342
335 if (host->req->data_dir == READ) { 343 if (host->use_dma)
336 for (rc = 0; (data_len - rc) >= 4; rc += 4) 344 tifm_unmap_sg(sock, &host->req->sg, 1,
337 *(int *)(data + rc) 345 host->req->data_dir == READ
338 = __raw_readl(sock->addr 346 ? PCI_DMA_FROMDEVICE
339 + SOCK_MS_DATA); 347 : PCI_DMA_TODEVICE);
340
341 if (data_len - rc)
342 tval = readl(sock->addr + SOCK_MS_DATA);
343 switch (data_len - rc) {
344 case 3:
345 data[rc + 2] = (tval >> 16) & 0xff;
346 case 2:
347 data[rc + 1] = (tval >> 8) & 0xff;
348 case 1:
349 data[rc] = tval & 0xff;
350 }
351 readl(sock->addr + SOCK_MS_DATA);
352 }
353 }
354 348
355 writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL), 349 writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
356 sock->addr + SOCK_CONTROL); 350 sock->addr + SOCK_CONTROL);
357 351
352 dev_dbg(&sock->dev, "TPC complete\n");
358 do { 353 do {
359 rc = memstick_next_req(msh, &host->req); 354 rc = memstick_next_req(msh, &host->req);
360 } while (!rc && tifm_ms_issue_cmd(host)); 355 } while (!rc && tifm_ms_issue_cmd(host));
@@ -365,11 +360,10 @@ static int tifm_ms_check_status(struct tifm_ms *host)
365 if (!host->req->error) { 360 if (!host->req->error) {
366 if (!(host->cmd_flags & CMD_READY)) 361 if (!(host->cmd_flags & CMD_READY))
367 return 1; 362 return 1;
368 if ((host->req->io_type == MEMSTICK_IO_SG) 363 if (!(host->cmd_flags & FIFO_READY))
369 && !(host->cmd_flags & FIFO_READY))
370 return 1; 364 return 1;
371 if (host->req->need_card_int 365 if (host->req->need_card_int
372 && !(host->cmd_flags & CARD_READY)) 366 && !(host->cmd_flags & CARD_INT))
373 return 1; 367 return 1;
374 } 368 }
375 return 0; 369 return 0;
@@ -379,18 +373,24 @@ static int tifm_ms_check_status(struct tifm_ms *host)
379static void tifm_ms_data_event(struct tifm_dev *sock) 373static void tifm_ms_data_event(struct tifm_dev *sock)
380{ 374{
381 struct tifm_ms *host; 375 struct tifm_ms *host;
382 unsigned int fifo_status = 0; 376 unsigned int fifo_status = 0, host_status = 0;
383 int rc = 1; 377 int rc = 1;
384 378
385 spin_lock(&sock->lock); 379 spin_lock(&sock->lock);
386 host = memstick_priv((struct memstick_host *)tifm_get_drvdata(sock)); 380 host = memstick_priv((struct memstick_host *)tifm_get_drvdata(sock));
387 fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS); 381 fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
388 dev_dbg(&sock->dev, "data event: fifo_status %x, flags %x\n", 382 host_status = readl(sock->addr + SOCK_MS_STATUS);
389 fifo_status, host->cmd_flags); 383 dev_dbg(&sock->dev,
384 "data event: fifo_status %x, host_status %x, flags %x\n",
385 fifo_status, host_status, host->cmd_flags);
390 386
391 if (host->req) { 387 if (host->req) {
392 if (fifo_status & TIFM_FIFO_READY) { 388 if (host->use_dma && (fifo_status & 1)) {
393 if (!host->no_dma || tifm_ms_transfer_data(host, 0)) { 389 host->cmd_flags |= FIFO_READY;
390 rc = tifm_ms_check_status(host);
391 }
392 if (!host->use_dma && (fifo_status & TIFM_FIFO_MORE)) {
393 if (!tifm_ms_transfer_data(host)) {
394 host->cmd_flags |= FIFO_READY; 394 host->cmd_flags |= FIFO_READY;
395 rc = tifm_ms_check_status(host); 395 rc = tifm_ms_check_status(host);
396 } 396 }
@@ -419,9 +419,9 @@ static void tifm_ms_card_event(struct tifm_dev *sock)
419 host_status, host->cmd_flags); 419 host_status, host->cmd_flags);
420 420
421 if (host->req) { 421 if (host->req) {
422 if (host_status & TIFM_MS_TIMEOUT) 422 if (host_status & TIFM_MS_STAT_TOE)
423 host->req->error = -ETIME; 423 host->req->error = -ETIME;
424 else if (host_status & TIFM_MS_BADCRC) 424 else if (host_status & TIFM_MS_STAT_CRC)
425 host->req->error = -EILSEQ; 425 host->req->error = -EILSEQ;
426 426
427 if (host->req->error) { 427 if (host->req->error) {
@@ -430,18 +430,17 @@ static void tifm_ms_card_event(struct tifm_dev *sock)
430 writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL); 430 writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
431 } 431 }
432 432
433 if (host_status & TIFM_MS_EOTPC) 433 if (host_status & TIFM_MS_STAT_RDY)
434 host->cmd_flags |= CMD_READY; 434 host->cmd_flags |= CMD_READY;
435 if (host_status & TIFM_MS_INT) 435
436 host->cmd_flags |= CARD_READY; 436 if (host_status & TIFM_MS_STAT_MSINT)
437 host->cmd_flags |= CARD_INT;
437 438
438 rc = tifm_ms_check_status(host); 439 rc = tifm_ms_check_status(host);
439 440
440 } 441 }
441 442
442 writel(TIFM_MS_SYS_NOT_RDY | readl(sock->addr + SOCK_MS_SYSTEM), 443 writel(TIFM_MS_SYS_INTCLR | readl(sock->addr + SOCK_MS_SYSTEM),
443 sock->addr + SOCK_MS_SYSTEM);
444 writel((~TIFM_MS_SYS_DATA) & readl(sock->addr + SOCK_MS_SYSTEM),
445 sock->addr + SOCK_MS_SYSTEM); 444 sock->addr + SOCK_MS_SYSTEM);
446 445
447 if (!rc) 446 if (!rc)
@@ -497,15 +496,26 @@ static void tifm_ms_set_param(struct memstick_host *msh,
497 496
498 switch (param) { 497 switch (param) {
499 case MEMSTICK_POWER: 498 case MEMSTICK_POWER:
500 /* this is set by card detection mechanism */ 499 /* also affected by media detection mechanism */
500 if (value == MEMSTICK_POWER_ON) {
501 host->mode_mask = TIFM_MS_SYS_SRAC | TIFM_MS_SYS_REI;
502 writel(TIFM_MS_SYS_RESET, sock->addr + SOCK_MS_SYSTEM);
503 writel(TIFM_MS_SYS_FCLR | TIFM_MS_SYS_INTCLR,
504 sock->addr + SOCK_MS_SYSTEM);
505 writel(0xffffffff, sock->addr + SOCK_MS_STATUS);
506 } else if (value == MEMSTICK_POWER_OFF) {
507 writel(TIFM_MS_SYS_FCLR | TIFM_MS_SYS_INTCLR,
508 sock->addr + SOCK_MS_SYSTEM);
509 writel(0xffffffff, sock->addr + SOCK_MS_STATUS);
510 }
501 break; 511 break;
502 case MEMSTICK_INTERFACE: 512 case MEMSTICK_INTERFACE:
503 if (value == MEMSTICK_SERIAL) { 513 if (value == MEMSTICK_SERIAL) {
504 host->mode_mask = TIFM_MS_SERIAL; 514 host->mode_mask = TIFM_MS_SYS_SRAC | TIFM_MS_SYS_REI;
505 writel((~TIFM_CTRL_FAST_CLK) 515 writel((~TIFM_CTRL_FAST_CLK)
506 & readl(sock->addr + SOCK_CONTROL), 516 & readl(sock->addr + SOCK_CONTROL),
507 sock->addr + SOCK_CONTROL); 517 sock->addr + SOCK_CONTROL);
508 } else if (value == MEMSTICK_PARALLEL) { 518 } else if (value == MEMSTICK_PAR4) {
509 host->mode_mask = 0; 519 host->mode_mask = 0;
510 writel(TIFM_CTRL_FAST_CLK 520 writel(TIFM_CTRL_FAST_CLK
511 | readl(sock->addr + SOCK_CONTROL), 521 | readl(sock->addr + SOCK_CONTROL),
@@ -532,21 +542,6 @@ static void tifm_ms_abort(unsigned long data)
532 tifm_eject(host->dev); 542 tifm_eject(host->dev);
533} 543}
534 544
535static int tifm_ms_initialize_host(struct tifm_ms *host)
536{
537 struct tifm_dev *sock = host->dev;
538 struct memstick_host *msh = tifm_get_drvdata(sock);
539
540 host->mode_mask = TIFM_MS_SERIAL;
541 writel(0x8000, sock->addr + SOCK_MS_SYSTEM);
542 writel(0x0200 | TIFM_MS_SYS_NOT_RDY, sock->addr + SOCK_MS_SYSTEM);
543 writel(0xffffffff, sock->addr + SOCK_MS_STATUS);
544 if (tifm_has_ms_pif(sock))
545 msh->caps |= MEMSTICK_CAP_PARALLEL;
546
547 return 0;
548}
549
550static int tifm_ms_probe(struct tifm_dev *sock) 545static int tifm_ms_probe(struct tifm_dev *sock)
551{ 546{
552 struct memstick_host *msh; 547 struct memstick_host *msh;
@@ -568,7 +563,6 @@ static int tifm_ms_probe(struct tifm_dev *sock)
568 tifm_set_drvdata(sock, msh); 563 tifm_set_drvdata(sock, msh);
569 host->dev = sock; 564 host->dev = sock;
570 host->timeout_jiffies = msecs_to_jiffies(1000); 565 host->timeout_jiffies = msecs_to_jiffies(1000);
571 host->no_dma = no_dma;
572 566
573 setup_timer(&host->timer, tifm_ms_abort, (unsigned long)host); 567 setup_timer(&host->timer, tifm_ms_abort, (unsigned long)host);
574 568
@@ -576,10 +570,10 @@ static int tifm_ms_probe(struct tifm_dev *sock)
576 msh->set_param = tifm_ms_set_param; 570 msh->set_param = tifm_ms_set_param;
577 sock->card_event = tifm_ms_card_event; 571 sock->card_event = tifm_ms_card_event;
578 sock->data_event = tifm_ms_data_event; 572 sock->data_event = tifm_ms_data_event;
579 rc = tifm_ms_initialize_host(host); 573 if (tifm_has_ms_pif(sock))
574 msh->caps |= MEMSTICK_CAP_PAR4;
580 575
581 if (!rc) 576 rc = memstick_add_host(msh);
582 rc = memstick_add_host(msh);
583 if (!rc) 577 if (!rc)
584 return 0; 578 return 0;
585 579
@@ -601,7 +595,7 @@ static void tifm_ms_remove(struct tifm_dev *sock)
601 writel(TIFM_FIFO_INT_SETALL, 595 writel(TIFM_FIFO_INT_SETALL,
602 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR); 596 sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
603 writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL); 597 writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
604 if ((host->req->io_type == MEMSTICK_IO_SG) && !host->no_dma) 598 if (host->use_dma)
605 tifm_unmap_sg(sock, &host->req->sg, 1, 599 tifm_unmap_sg(sock, &host->req->sg, 1,
606 host->req->data_dir == READ 600 host->req->data_dir == READ
607 ? PCI_DMA_TODEVICE 601 ? PCI_DMA_TODEVICE
@@ -617,10 +611,6 @@ static void tifm_ms_remove(struct tifm_dev *sock)
617 spin_unlock_irqrestore(&sock->lock, flags); 611 spin_unlock_irqrestore(&sock->lock, flags);
618 612
619 memstick_remove_host(msh); 613 memstick_remove_host(msh);
620
621 writel(0x0200 | TIFM_MS_SYS_NOT_RDY, sock->addr + SOCK_MS_SYSTEM);
622 writel(0xffffffff, sock->addr + SOCK_MS_STATUS);
623
624 memstick_free_host(msh); 614 memstick_free_host(msh);
625} 615}
626 616
@@ -628,17 +618,17 @@ static void tifm_ms_remove(struct tifm_dev *sock)
628 618
629static int tifm_ms_suspend(struct tifm_dev *sock, pm_message_t state) 619static int tifm_ms_suspend(struct tifm_dev *sock, pm_message_t state)
630{ 620{
621 struct memstick_host *msh = tifm_get_drvdata(sock);
622
623 memstick_suspend_host(msh);
631 return 0; 624 return 0;
632} 625}
633 626
634static int tifm_ms_resume(struct tifm_dev *sock) 627static int tifm_ms_resume(struct tifm_dev *sock)
635{ 628{
636 struct memstick_host *msh = tifm_get_drvdata(sock); 629 struct memstick_host *msh = tifm_get_drvdata(sock);
637 struct tifm_ms *host = memstick_priv(msh);
638
639 tifm_ms_initialize_host(host);
640 memstick_detect_change(msh);
641 630
631 memstick_resume_host(msh);
642 return 0; 632 return 0;
643} 633}
644 634
@@ -679,7 +669,6 @@ MODULE_AUTHOR("Alex Dubov");
679MODULE_DESCRIPTION("TI FlashMedia MemoryStick driver"); 669MODULE_DESCRIPTION("TI FlashMedia MemoryStick driver");
680MODULE_LICENSE("GPL"); 670MODULE_LICENSE("GPL");
681MODULE_DEVICE_TABLE(tifm, tifm_ms_id_tbl); 671MODULE_DEVICE_TABLE(tifm, tifm_ms_id_tbl);
682MODULE_VERSION(DRIVER_VERSION);
683 672
684module_init(tifm_ms_init); 673module_init(tifm_ms_init);
685module_exit(tifm_ms_exit); 674module_exit(tifm_ms_exit);
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 12:28:06 -0500