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authorScott Wood <scottwood@freescale.com>2014-12-10 19:56:22 -0500
committerScott Wood <scottwood@freescale.com>2015-01-29 23:57:43 -0500
commitc3e09b3a90850b299aa805c32945163e5101ddcd (patch)
tree8cfe39bb064ff552ba8d30b57a7b41cc86fbc828 /drivers/memory
parent2727ed54716e606673121d5863934512bd4a5eb8 (diff)
memory/fsl-corenet-cf: Add t1040 support
T1040 has a different version of corenet-cf, despite being incorrectly labelled with a fsl,corenet2-cf compatible. The t1040 version of corenet-cf has a version register that can be read to distinguish. The t4240/b4860 version officially does not, but testing shows that it does and has a different value, so use that. If somehow this ends up not being reliable and we treat a t4240/b4860 as a t1040 (the reverse should not happen, as t1040's version register is official), currently the worst that should happen is writing to reserved bits to enable events that don't exist. The changes to the t1040 version of corenet-cf that this driver cares about are the addition of two new error events. There are also changes to the format of cecar2, which is printed, but not interpreted, by this driver. Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'drivers/memory')
-rw-r--r--drivers/memory/fsl-corenet-cf.c36
1 files changed, 34 insertions, 2 deletions
diff --git a/drivers/memory/fsl-corenet-cf.c b/drivers/memory/fsl-corenet-cf.c
index fc7ab5a3561e..d708ded5457b 100644
--- a/drivers/memory/fsl-corenet-cf.c
+++ b/drivers/memory/fsl-corenet-cf.c
@@ -27,18 +27,29 @@ enum ccf_version {
27struct ccf_info { 27struct ccf_info {
28 enum ccf_version version; 28 enum ccf_version version;
29 int err_reg_offs; 29 int err_reg_offs;
30 bool has_brr;
30}; 31};
31 32
32static const struct ccf_info ccf1_info = { 33static const struct ccf_info ccf1_info = {
33 .version = CCF1, 34 .version = CCF1,
34 .err_reg_offs = 0xa00, 35 .err_reg_offs = 0xa00,
36 .has_brr = false,
35}; 37};
36 38
37static const struct ccf_info ccf2_info = { 39static const struct ccf_info ccf2_info = {
38 .version = CCF2, 40 .version = CCF2,
39 .err_reg_offs = 0xe40, 41 .err_reg_offs = 0xe40,
42 .has_brr = true,
40}; 43};
41 44
45/*
46 * This register is present but not documented, with different values for
47 * IP_ID, on other chips with fsl,corenet2-cf such as t4240 and b4860.
48 */
49#define CCF_BRR 0xbf8
50#define CCF_BRR_IPID 0xffff0000
51#define CCF_BRR_IPID_T1040 0x09310000
52
42static const struct of_device_id ccf_matches[] = { 53static const struct of_device_id ccf_matches[] = {
43 { 54 {
44 .compatible = "fsl,corenet1-cf", 55 .compatible = "fsl,corenet1-cf",
@@ -66,6 +77,8 @@ struct ccf_err_regs {
66/* LAE/CV also valid for errdis and errinten */ 77/* LAE/CV also valid for errdis and errinten */
67#define ERRDET_LAE (1 << 0) /* Local Access Error */ 78#define ERRDET_LAE (1 << 0) /* Local Access Error */
68#define ERRDET_CV (1 << 1) /* Coherency Violation */ 79#define ERRDET_CV (1 << 1) /* Coherency Violation */
80#define ERRDET_UTID (1 << 2) /* Unavailable Target ID (t1040) */
81#define ERRDET_MCST (1 << 3) /* Multicast Stash (t1040) */
69#define ERRDET_CTYPE_SHIFT 26 /* Capture Type (ccf2 only) */ 82#define ERRDET_CTYPE_SHIFT 26 /* Capture Type (ccf2 only) */
70#define ERRDET_CTYPE_MASK (0x1f << ERRDET_CTYPE_SHIFT) 83#define ERRDET_CTYPE_MASK (0x1f << ERRDET_CTYPE_SHIFT)
71#define ERRDET_CAP (1 << 31) /* Capture Valid (ccf2 only) */ 84#define ERRDET_CAP (1 << 31) /* Capture Valid (ccf2 only) */
@@ -84,6 +97,7 @@ struct ccf_private {
84 struct device *dev; 97 struct device *dev;
85 void __iomem *regs; 98 void __iomem *regs;
86 struct ccf_err_regs __iomem *err_regs; 99 struct ccf_err_regs __iomem *err_regs;
100 bool t1040;
87}; 101};
88 102
89static irqreturn_t ccf_irq(int irq, void *dev_id) 103static irqreturn_t ccf_irq(int irq, void *dev_id)
@@ -142,6 +156,12 @@ static irqreturn_t ccf_irq(int irq, void *dev_id)
142 if (errdet & ERRDET_CV) 156 if (errdet & ERRDET_CV)
143 dev_crit(ccf->dev, "Coherency Violation\n"); 157 dev_crit(ccf->dev, "Coherency Violation\n");
144 158
159 if (errdet & ERRDET_UTID)
160 dev_crit(ccf->dev, "Unavailable Target ID\n");
161
162 if (errdet & ERRDET_MCST)
163 dev_crit(ccf->dev, "Multicast Stash\n");
164
145 if (cap_valid) { 165 if (cap_valid) {
146 dev_crit(ccf->dev, "address 0x%09llx, src id 0x%x\n", 166 dev_crit(ccf->dev, "address 0x%09llx, src id 0x%x\n",
147 addr, src_id); 167 addr, src_id);
@@ -157,6 +177,7 @@ static int ccf_probe(struct platform_device *pdev)
157 struct ccf_private *ccf; 177 struct ccf_private *ccf;
158 struct resource *r; 178 struct resource *r;
159 const struct of_device_id *match; 179 const struct of_device_id *match;
180 u32 errinten;
160 int ret, irq; 181 int ret, irq;
161 182
162 match = of_match_device(ccf_matches, &pdev->dev); 183 match = of_match_device(ccf_matches, &pdev->dev);
@@ -183,6 +204,13 @@ static int ccf_probe(struct platform_device *pdev)
183 ccf->info = match->data; 204 ccf->info = match->data;
184 ccf->err_regs = ccf->regs + ccf->info->err_reg_offs; 205 ccf->err_regs = ccf->regs + ccf->info->err_reg_offs;
185 206
207 if (ccf->info->has_brr) {
208 u32 brr = ioread32be(ccf->regs + CCF_BRR);
209
210 if ((brr & CCF_BRR_IPID) == CCF_BRR_IPID_T1040)
211 ccf->t1040 = true;
212 }
213
186 dev_set_drvdata(&pdev->dev, ccf); 214 dev_set_drvdata(&pdev->dev, ccf);
187 215
188 irq = platform_get_irq(pdev, 0); 216 irq = platform_get_irq(pdev, 0);
@@ -197,15 +225,19 @@ static int ccf_probe(struct platform_device *pdev)
197 return ret; 225 return ret;
198 } 226 }
199 227
228 errinten = ERRDET_LAE | ERRDET_CV;
229 if (ccf->t1040)
230 errinten |= ERRDET_UTID | ERRDET_MCST;
231
200 switch (ccf->info->version) { 232 switch (ccf->info->version) {
201 case CCF1: 233 case CCF1:
202 /* On CCF1 this register enables rather than disables. */ 234 /* On CCF1 this register enables rather than disables. */
203 iowrite32be(ERRDET_LAE | ERRDET_CV, &ccf->err_regs->errdis); 235 iowrite32be(errinten, &ccf->err_regs->errdis);
204 break; 236 break;
205 237
206 case CCF2: 238 case CCF2:
207 iowrite32be(0, &ccf->err_regs->errdis); 239 iowrite32be(0, &ccf->err_regs->errdis);
208 iowrite32be(ERRDET_LAE | ERRDET_CV, &ccf->err_regs->errinten); 240 iowrite32be(errinten, &ccf->err_regs->errinten);
209 break; 241 break;
210 } 242 }
211 243