diff options
author | Jonathan Corbet <corbet@lwn.net> | 2010-03-21 16:33:50 -0400 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2010-05-17 23:51:19 -0400 |
commit | 97693f9178ba83068f6b4e419a47ffd3d1a20897 (patch) | |
tree | 04a2bf0747371e202f2ee858b7656e3c98d5b039 /drivers/media | |
parent | 4a3eaee4d0d2724d86cbb18ad4b0088ce0b7f8a2 (diff) |
V4L/DVB: ov7670: Use CCIR601 in all video modes
Also provide for a longer delay after reset - the XO 1.5 needs it.
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media')
-rw-r--r-- | drivers/media/video/ov7670.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/media/video/ov7670.c b/drivers/media/video/ov7670.c index aaa50f9b8e78..b44762adb1e9 100644 --- a/drivers/media/video/ov7670.c +++ b/drivers/media/video/ov7670.c | |||
@@ -351,7 +351,7 @@ static struct regval_list ov7670_default_regs[] = { | |||
351 | static struct regval_list ov7670_fmt_yuv422[] = { | 351 | static struct regval_list ov7670_fmt_yuv422[] = { |
352 | { REG_COM7, 0x0 }, /* Selects YUV mode */ | 352 | { REG_COM7, 0x0 }, /* Selects YUV mode */ |
353 | { REG_RGB444, 0 }, /* No RGB444 please */ | 353 | { REG_RGB444, 0 }, /* No RGB444 please */ |
354 | { REG_COM1, 0 }, | 354 | { REG_COM1, 0 }, /* CCIR601 */ |
355 | { REG_COM15, COM15_R00FF }, | 355 | { REG_COM15, COM15_R00FF }, |
356 | { REG_COM9, 0x18 }, /* 4x gain ceiling; 0x8 is reserved bit */ | 356 | { REG_COM9, 0x18 }, /* 4x gain ceiling; 0x8 is reserved bit */ |
357 | { 0x4f, 0x80 }, /* "matrix coefficient 1" */ | 357 | { 0x4f, 0x80 }, /* "matrix coefficient 1" */ |
@@ -367,7 +367,7 @@ static struct regval_list ov7670_fmt_yuv422[] = { | |||
367 | static struct regval_list ov7670_fmt_rgb565[] = { | 367 | static struct regval_list ov7670_fmt_rgb565[] = { |
368 | { REG_COM7, COM7_RGB }, /* Selects RGB mode */ | 368 | { REG_COM7, COM7_RGB }, /* Selects RGB mode */ |
369 | { REG_RGB444, 0 }, /* No RGB444 please */ | 369 | { REG_RGB444, 0 }, /* No RGB444 please */ |
370 | { REG_COM1, 0x0 }, | 370 | { REG_COM1, 0x0 }, /* CCIR601 */ |
371 | { REG_COM15, COM15_RGB565 }, | 371 | { REG_COM15, COM15_RGB565 }, |
372 | { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ | 372 | { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ |
373 | { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ | 373 | { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ |
@@ -383,7 +383,7 @@ static struct regval_list ov7670_fmt_rgb565[] = { | |||
383 | static struct regval_list ov7670_fmt_rgb444[] = { | 383 | static struct regval_list ov7670_fmt_rgb444[] = { |
384 | { REG_COM7, COM7_RGB }, /* Selects RGB mode */ | 384 | { REG_COM7, COM7_RGB }, /* Selects RGB mode */ |
385 | { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */ | 385 | { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */ |
386 | { REG_COM1, 0x40 }, /* Magic reserved bit */ | 386 | { REG_COM1, 0x0 }, /* CCIR601 */ |
387 | { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */ | 387 | { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */ |
388 | { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ | 388 | { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */ |
389 | { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ | 389 | { 0x4f, 0xb3 }, /* "matrix coefficient 1" */ |
@@ -432,7 +432,7 @@ static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg, | |||
432 | int ret = i2c_smbus_write_byte_data(client, reg, value); | 432 | int ret = i2c_smbus_write_byte_data(client, reg, value); |
433 | 433 | ||
434 | if (reg == REG_COM7 && (value & COM7_RESET)) | 434 | if (reg == REG_COM7 && (value & COM7_RESET)) |
435 | msleep(2); /* Wait for reset to run */ | 435 | msleep(5); /* Wait for reset to run */ |
436 | return ret; | 436 | return ret; |
437 | } | 437 | } |
438 | 438 | ||