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authorSteven Toth <stoth@hauppauge.com>2008-03-29 16:30:26 -0400
committerMauro Carvalho Chehab <mchehab@infradead.org>2008-04-01 18:35:45 -0400
commit31c8cc9742daa6ffedf7ba8a9bc465b10dee4b52 (patch)
treeb1fd6a728070fa3e23a9435994e7c637a945474e /drivers/media
parent1a002ebf60c011ed6574b8e3ed9aa85f1ead6a95 (diff)
V4L/DVB (7464): Convert driver to use a single SRAM memory map
This reduces the memory footprint and removes the need to manually configure each map, which lead to a bug where the Fusion EXP 5 board broke for a while. This also fixes digital support again for the DViCO FusionHDTV5Express. Signed-off-by: Steven Toth <stoth@hauppauge.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'drivers/media')
-rw-r--r--drivers/media/video/cx23885/cx23885-core.c134
1 files changed, 1 insertions, 133 deletions
diff --git a/drivers/media/video/cx23885/cx23885-core.c b/drivers/media/video/cx23885/cx23885-core.c
index 8e40c7bcc06d..7f10b273598f 100644
--- a/drivers/media/video/cx23885/cx23885-core.c
+++ b/drivers/media/video/cx23885/cx23885-core.c
@@ -56,137 +56,6 @@ LIST_HEAD(cx23885_devlist);
56 56
57#define NO_SYNC_LINE (-1U) 57#define NO_SYNC_LINE (-1U)
58 58
59/*
60 * CX23885 Assumptions
61 * 1 line = 16 bytes of CDT
62 * cmds size = 80
63 * cdt size = 16 * linesize
64 * iqsize = 64
65 * maxlines = 6
66 *
67 * Address Space:
68 * 0x00000000 0x00008fff FIFO clusters
69 * 0x00010000 0x000104af Channel Management Data Structures
70 * 0x000104b0 0x000104ff Free
71 * 0x00010500 0x000108bf 15 channels * iqsize
72 * 0x000108c0 0x000108ff Free
73 * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
74 * 15 channels * (iqsize + (maxlines * linesize))
75 * 0x00010ea0 0x00010xxx Free
76 */
77
78static struct sram_channel cx23885_sram_channels[] = {
79 [SRAM_CH01] = {
80 .name = "VID A",
81 .cmds_start = 0x10000,
82 .ctrl_start = 0x105b0,
83 .cdt = 0x107b0,
84 .fifo_start = 0x40,
85 .fifo_size = 0x2800,
86 .ptr1_reg = DMA1_PTR1,
87 .ptr2_reg = DMA1_PTR2,
88 .cnt1_reg = DMA1_CNT1,
89 .cnt2_reg = DMA1_CNT2,
90 .jumponly = 1,
91 },
92 [SRAM_CH02] = {
93 .name = "ch2",
94 .cmds_start = 0x0,
95 .ctrl_start = 0x0,
96 .cdt = 0x0,
97 .fifo_start = 0x0,
98 .fifo_size = 0x0,
99 .ptr1_reg = DMA2_PTR1,
100 .ptr2_reg = DMA2_PTR2,
101 .cnt1_reg = DMA2_CNT1,
102 .cnt2_reg = DMA2_CNT2,
103 },
104 [SRAM_CH03] = {
105 .name = "TS1 B",
106 .cmds_start = 0x100A0,
107 .ctrl_start = 0x10630,
108 .cdt = 0x10870,
109 .fifo_start = 0x5000,
110 .fifo_size = 0x1000,
111 .ptr1_reg = DMA3_PTR1,
112 .ptr2_reg = DMA3_PTR2,
113 .cnt1_reg = DMA3_CNT1,
114 .cnt2_reg = DMA3_CNT2,
115 },
116 [SRAM_CH04] = {
117 .name = "ch4",
118 .cmds_start = 0x0,
119 .ctrl_start = 0x0,
120 .cdt = 0x0,
121 .fifo_start = 0x0,
122 .fifo_size = 0x0,
123 .ptr1_reg = DMA4_PTR1,
124 .ptr2_reg = DMA4_PTR2,
125 .cnt1_reg = DMA4_CNT1,
126 .cnt2_reg = DMA4_CNT2,
127 },
128 [SRAM_CH05] = {
129 .name = "ch5",
130 .cmds_start = 0x0,
131 .ctrl_start = 0x0,
132 .cdt = 0x0,
133 .fifo_start = 0x0,
134 .fifo_size = 0x0,
135 .ptr1_reg = DMA5_PTR1,
136 .ptr2_reg = DMA5_PTR2,
137 .cnt1_reg = DMA5_CNT1,
138 .cnt2_reg = DMA5_CNT2,
139 },
140 [SRAM_CH06] = {
141 .name = "TS2 C",
142 .cmds_start = 0x10140,
143 .ctrl_start = 0x10680,
144 .cdt = 0x108d0,
145 .fifo_start = 0x6000,
146 .fifo_size = 0x1000,
147 .ptr1_reg = DMA5_PTR1,
148 .ptr2_reg = DMA5_PTR2,
149 .cnt1_reg = DMA5_CNT1,
150 .cnt2_reg = DMA5_CNT2,
151 },
152 [SRAM_CH07] = {
153 .name = "ch7",
154 .cmds_start = 0x0,
155 .ctrl_start = 0x0,
156 .cdt = 0x0,
157 .fifo_start = 0x0,
158 .fifo_size = 0x0,
159 .ptr1_reg = DMA6_PTR1,
160 .ptr2_reg = DMA6_PTR2,
161 .cnt1_reg = DMA6_CNT1,
162 .cnt2_reg = DMA6_CNT2,
163 },
164 [SRAM_CH08] = {
165 .name = "ch8",
166 .cmds_start = 0x0,
167 .ctrl_start = 0x0,
168 .cdt = 0x0,
169 .fifo_start = 0x0,
170 .fifo_size = 0x0,
171 .ptr1_reg = DMA7_PTR1,
172 .ptr2_reg = DMA7_PTR2,
173 .cnt1_reg = DMA7_CNT1,
174 .cnt2_reg = DMA7_CNT2,
175 },
176 [SRAM_CH09] = {
177 .name = "ch9",
178 .cmds_start = 0x0,
179 .ctrl_start = 0x0,
180 .cdt = 0x0,
181 .fifo_start = 0x0,
182 .fifo_size = 0x0,
183 .ptr1_reg = DMA8_PTR1,
184 .ptr2_reg = DMA8_PTR2,
185 .cnt1_reg = DMA8_CNT1,
186 .cnt2_reg = DMA8_CNT2,
187 },
188};
189
190/* FIXME, these allocations will change when 59/* FIXME, these allocations will change when
191 * analog arrives. The be reviewed. 60 * analog arrives. The be reviewed.
192 * CX23887 Assumptions 61 * CX23887 Assumptions
@@ -754,6 +623,7 @@ static int cx23885_dev_setup(struct cx23885_dev *dev)
754 atomic_inc(&dev->refcount); 623 atomic_inc(&dev->refcount);
755 624
756 dev->nr = cx23885_devcount++; 625 dev->nr = cx23885_devcount++;
626 dev->sram_channels = cx23887_sram_channels;
757 sprintf(dev->name, "cx23885[%d]", dev->nr); 627 sprintf(dev->name, "cx23885[%d]", dev->nr);
758 628
759 mutex_lock(&devlist); 629 mutex_lock(&devlist);
@@ -763,13 +633,11 @@ static int cx23885_dev_setup(struct cx23885_dev *dev)
763 /* Configure the internal memory */ 633 /* Configure the internal memory */
764 if(dev->pci->device == 0x8880) { 634 if(dev->pci->device == 0x8880) {
765 dev->bridge = CX23885_BRIDGE_887; 635 dev->bridge = CX23885_BRIDGE_887;
766 dev->sram_channels = cx23887_sram_channels;
767 /* Apply a sensible clock frequency for the PCIe bridge */ 636 /* Apply a sensible clock frequency for the PCIe bridge */
768 dev->clk_freq = 25000000; 637 dev->clk_freq = 25000000;
769 } else 638 } else
770 if(dev->pci->device == 0x8852) { 639 if(dev->pci->device == 0x8852) {
771 dev->bridge = CX23885_BRIDGE_885; 640 dev->bridge = CX23885_BRIDGE_885;
772 dev->sram_channels = cx23885_sram_channels;
773 /* Apply a sensible clock frequency for the PCIe bridge */ 641 /* Apply a sensible clock frequency for the PCIe bridge */
774 dev->clk_freq = 28000000; 642 dev->clk_freq = 28000000;
775 } else 643 } else
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-30 20:19:39 -0400