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authorIgor M. Liplianin <liplianin@netup.ru>2009-11-06 21:46:32 -0500
committerMauro Carvalho Chehab <mchehab@redhat.com>2009-12-05 15:41:26 -0500
commita3a4f7e167e77066b0b98b8f056efcda2d302f97 (patch)
tree06e4eae2779d16f10d4745d8d2ddcf2ac81bde00 /drivers/media
parent1e0c397d5ee261b4d855bf38c1e9987caf0e37ca (diff)
V4L/DVB (13341): stv0900: big rework to support cut 3.0.
Patch 4 of 4. Also patch changes logic to prevent code repetitions and big indents. It makes checkpatch silent :) Signed-off-by: Igor M. Liplianin <liplianin@netup.ru> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media')
-rw-r--r--drivers/media/dvb/frontends/stv0900_sw.c3144
1 files changed, 1148 insertions, 1996 deletions
diff --git a/drivers/media/dvb/frontends/stv0900_sw.c b/drivers/media/dvb/frontends/stv0900_sw.c
index 8c83c8b306a6..b8da87fa637f 100644
--- a/drivers/media/dvb/frontends/stv0900_sw.c
+++ b/drivers/media/dvb/frontends/stv0900_sw.c
@@ -27,56 +27,45 @@
27#include "stv0900_reg.h" 27#include "stv0900_reg.h"
28#include "stv0900_priv.h" 28#include "stv0900_priv.h"
29 29
30int stv0900_check_signal_presence(struct stv0900_internal *i_params, 30s32 shiftx(s32 x, int demod, s32 shift)
31{
32 if (demod == 1)
33 return x - shift;
34
35 return x;
36}
37
38int stv0900_check_signal_presence(struct stv0900_internal *intp,
31 enum fe_stv0900_demod_num demod) 39 enum fe_stv0900_demod_num demod)
32{ 40{
33 s32 carr_offset, 41 s32 carr_offset,
34 agc2_integr, 42 agc2_integr,
35 max_carrier; 43 max_carrier;
36 44
37 int no_signal; 45 int no_signal = FALSE;
38 46
39 switch (demod) { 47 carr_offset = (stv0900_read_reg(intp, CFR2) << 8)
40 case STV0900_DEMOD_1: 48 | stv0900_read_reg(intp, CFR1);
41 default: 49 carr_offset = ge2comp(carr_offset, 16);
42 carr_offset = (stv0900_read_reg(i_params, R0900_P1_CFR2) << 8) 50 agc2_integr = (stv0900_read_reg(intp, AGC2I1) << 8)
43 | stv0900_read_reg(i_params, 51 | stv0900_read_reg(intp, AGC2I0);
44 R0900_P1_CFR1); 52 max_carrier = intp->srch_range[demod] / 1000;
45 carr_offset = ge2comp(carr_offset, 16);
46 agc2_integr = (stv0900_read_reg(i_params, R0900_P1_AGC2I1) << 8)
47 | stv0900_read_reg(i_params,
48 R0900_P1_AGC2I0);
49 max_carrier = i_params->dmd1_srch_range / 1000;
50 break;
51 case STV0900_DEMOD_2:
52 carr_offset = (stv0900_read_reg(i_params, R0900_P2_CFR2) << 8)
53 | stv0900_read_reg(i_params,
54 R0900_P2_CFR1);
55 carr_offset = ge2comp(carr_offset, 16);
56 agc2_integr = (stv0900_read_reg(i_params, R0900_P2_AGC2I1) << 8)
57 | stv0900_read_reg(i_params,
58 R0900_P2_AGC2I0);
59 max_carrier = i_params->dmd2_srch_range / 1000;
60 break;
61 }
62 53
63 max_carrier += (max_carrier / 10); 54 max_carrier += (max_carrier / 10);
64 max_carrier = 65536 * (max_carrier / 2); 55 max_carrier = 65536 * (max_carrier / 2);
65 max_carrier /= i_params->mclk / 1000; 56 max_carrier /= intp->mclk / 1000;
66 if (max_carrier > 0x4000) 57 if (max_carrier > 0x4000)
67 max_carrier = 0x4000; 58 max_carrier = 0x4000;
68 59
69 if ((agc2_integr > 0x2000) 60 if ((agc2_integr > 0x2000)
70 || (carr_offset > + 2*max_carrier) 61 || (carr_offset > (2 * max_carrier))
71 || (carr_offset < -2*max_carrier)) 62 || (carr_offset < (-2 * max_carrier)))
72 no_signal = TRUE; 63 no_signal = TRUE;
73 else
74 no_signal = FALSE;
75 64
76 return no_signal; 65 return no_signal;
77} 66}
78 67
79static void stv0900_get_sw_loop_params(struct stv0900_internal *i_params, 68static void stv0900_get_sw_loop_params(struct stv0900_internal *intp,
80 s32 *frequency_inc, s32 *sw_timeout, 69 s32 *frequency_inc, s32 *sw_timeout,
81 s32 *steps, 70 s32 *steps,
82 enum fe_stv0900_demod_num demod) 71 enum fe_stv0900_demod_num demod)
@@ -85,30 +74,19 @@ static void stv0900_get_sw_loop_params(struct stv0900_internal *i_params,
85 74
86 enum fe_stv0900_search_standard standard; 75 enum fe_stv0900_search_standard standard;
87 76
88 switch (demod) { 77 srate = intp->symbol_rate[demod];
89 case STV0900_DEMOD_1: 78 max_carrier = intp->srch_range[demod] / 1000;
90 default: 79 max_carrier += max_carrier / 10;
91 srate = i_params->dmd1_symbol_rate; 80 standard = intp->srch_standard[demod];
92 max_carrier = i_params->dmd1_srch_range / 1000;
93 max_carrier += max_carrier / 10;
94 standard = i_params->dmd1_srch_standard;
95 break;
96 case STV0900_DEMOD_2:
97 srate = i_params->dmd2_symbol_rate;
98 max_carrier = i_params->dmd2_srch_range / 1000;
99 max_carrier += max_carrier / 10;
100 standard = i_params->dmd2_srch_stndrd;
101 break;
102 }
103 81
104 max_carrier = 65536 * (max_carrier / 2); 82 max_carrier = 65536 * (max_carrier / 2);
105 max_carrier /= i_params->mclk / 1000; 83 max_carrier /= intp->mclk / 1000;
106 84
107 if (max_carrier > 0x4000) 85 if (max_carrier > 0x4000)
108 max_carrier = 0x4000; 86 max_carrier = 0x4000;
109 87
110 freq_inc = srate; 88 freq_inc = srate;
111 freq_inc /= i_params->mclk >> 10; 89 freq_inc /= intp->mclk >> 10;
112 freq_inc = freq_inc << 6; 90 freq_inc = freq_inc << 6;
113 91
114 switch (standard) { 92 switch (standard) {
@@ -154,7 +132,7 @@ static void stv0900_get_sw_loop_params(struct stv0900_internal *i_params,
154 132
155} 133}
156 134
157static int stv0900_search_carr_sw_loop(struct stv0900_internal *i_params, 135static int stv0900_search_carr_sw_loop(struct stv0900_internal *intp,
158 s32 FreqIncr, s32 Timeout, int zigzag, 136 s32 FreqIncr, s32 Timeout, int zigzag,
159 s32 MaxStep, enum fe_stv0900_demod_num demod) 137 s32 MaxStep, enum fe_stv0900_demod_num demod)
160{ 138{
@@ -164,20 +142,11 @@ static int stv0900_search_carr_sw_loop(struct stv0900_internal *i_params,
164 freqOffset, 142 freqOffset,
165 max_carrier; 143 max_carrier;
166 144
167 switch (demod) { 145 max_carrier = intp->srch_range[demod] / 1000;
168 case STV0900_DEMOD_1: 146 max_carrier += (max_carrier / 10);
169 default:
170 max_carrier = i_params->dmd1_srch_range / 1000;
171 max_carrier += (max_carrier / 10);
172 break;
173 case STV0900_DEMOD_2:
174 max_carrier = i_params->dmd2_srch_range / 1000;
175 max_carrier += (max_carrier / 10);
176 break;
177 }
178 147
179 max_carrier = 65536 * (max_carrier / 2); 148 max_carrier = 65536 * (max_carrier / 2);
180 max_carrier /= i_params->mclk / 1000; 149 max_carrier /= intp->mclk / 1000;
181 150
182 if (max_carrier > 0x4000) 151 if (max_carrier > 0x4000)
183 max_carrier = 0x4000; 152 max_carrier = 0x4000;
@@ -190,40 +159,15 @@ static int stv0900_search_carr_sw_loop(struct stv0900_internal *i_params,
190 stepCpt = 0; 159 stepCpt = 0;
191 160
192 do { 161 do {
193 switch (demod) { 162 stv0900_write_reg(intp, DMDISTATE, 0x1c);
194 case STV0900_DEMOD_1: 163 stv0900_write_reg(intp, CFRINIT1, (freqOffset / 256) & 0xff);
195 default: 164 stv0900_write_reg(intp, CFRINIT0, freqOffset & 0xff);
196 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1C); 165 stv0900_write_reg(intp, DMDISTATE, 0x18);
197 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, 166 stv0900_write_bits(intp, ALGOSWRST, 1);
198 (freqOffset / 256) & 0xFF); 167
199 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, 168 if (intp->chip_id == 0x12) {
200 freqOffset & 0xFF); 169 stv0900_write_bits(intp, RST_HWARE, 1);
201 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18); 170 stv0900_write_bits(intp, RST_HWARE, 0);
202 stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 1);
203
204 if (i_params->chip_id == 0x12) {
205 stv0900_write_bits(i_params,
206 F0900_P1_RST_HWARE, 1);
207 stv0900_write_bits(i_params,
208 F0900_P1_RST_HWARE, 0);
209 }
210 break;
211 case STV0900_DEMOD_2:
212 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1C);
213 stv0900_write_reg(i_params, R0900_P2_CFRINIT1,
214 (freqOffset / 256) & 0xFF);
215 stv0900_write_reg(i_params, R0900_P2_CFRINIT0,
216 freqOffset & 0xFF);
217 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
218 stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 1);
219
220 if (i_params->chip_id == 0x12) {
221 stv0900_write_bits(i_params,
222 F0900_P2_RST_HWARE, 1);
223 stv0900_write_bits(i_params,
224 F0900_P2_RST_HWARE, 0);
225 }
226 break;
227 } 171 }
228 172
229 if (zigzag == TRUE) { 173 if (zigzag == TRUE) {
@@ -235,8 +179,8 @@ static int stv0900_search_carr_sw_loop(struct stv0900_internal *i_params,
235 freqOffset += + 2 * FreqIncr; 179 freqOffset += + 2 * FreqIncr;
236 180
237 stepCpt++; 181 stepCpt++;
238 lock = stv0900_get_demod_lock(i_params, demod, Timeout); 182 lock = stv0900_get_demod_lock(intp, demod, Timeout);
239 no_signal = stv0900_check_signal_presence(i_params, demod); 183 no_signal = stv0900_check_signal_presence(intp, demod);
240 184
241 } while ((lock == FALSE) 185 } while ((lock == FALSE)
242 && (no_signal == FALSE) 186 && (no_signal == FALSE)
@@ -244,269 +188,138 @@ static int stv0900_search_carr_sw_loop(struct stv0900_internal *i_params,
244 && ((freqOffset + FreqIncr) > -max_carrier) 188 && ((freqOffset + FreqIncr) > -max_carrier)
245 && (stepCpt < MaxStep)); 189 && (stepCpt < MaxStep));
246 190
247 switch (demod) { 191 stv0900_write_bits(intp, ALGOSWRST, 0);
248 case STV0900_DEMOD_1:
249 default:
250 stv0900_write_bits(i_params, F0900_P1_ALGOSWRST, 0);
251 break;
252 case STV0900_DEMOD_2:
253 stv0900_write_bits(i_params, F0900_P2_ALGOSWRST, 0);
254 break;
255 }
256 192
257 return lock; 193 return lock;
258} 194}
259 195
260int stv0900_sw_algo(struct stv0900_internal *i_params, 196int stv0900_sw_algo(struct stv0900_internal *intp,
261 enum fe_stv0900_demod_num demod) 197 enum fe_stv0900_demod_num demod)
262{ 198{
263 int lock = FALSE; 199 int lock = FALSE,
264 200 no_signal,
265 int no_signal, 201 zigzag;
266 zigzag; 202 s32 s2fw,
267 s32 dvbs2_fly_wheel; 203 fqc_inc,
268 204 sft_stp_tout,
269 s32 freqIncrement, softStepTimeout, trialCounter, max_steps; 205 trial_cntr,
270 206 max_steps;
271 stv0900_get_sw_loop_params(i_params, &freqIncrement, &softStepTimeout, 207
208 stv0900_get_sw_loop_params(intp, &fqc_inc, &sft_stp_tout,
272 &max_steps, demod); 209 &max_steps, demod);
273 switch (demod) { 210 switch (intp->srch_standard[demod]) {
274 case STV0900_DEMOD_1: 211 case STV0900_SEARCH_DVBS1:
275 default: 212 case STV0900_SEARCH_DSS:
276 switch (i_params->dmd1_srch_standard) { 213 if (intp->chip_id >= 0x20)
277 case STV0900_SEARCH_DVBS1: 214 stv0900_write_reg(intp, CARFREQ, 0x3b);
278 case STV0900_SEARCH_DSS: 215 else
279 if (i_params->chip_id >= 0x20) 216 stv0900_write_reg(intp, CARFREQ, 0xef);
280 stv0900_write_reg(i_params, R0900_P1_CARFREQ,
281 0x3B);
282 else
283 stv0900_write_reg(i_params, R0900_P1_CARFREQ,
284 0xef);
285
286 stv0900_write_reg(i_params, R0900_P1_DMDCFGMD, 0x49);
287 zigzag = FALSE;
288 break;
289 case STV0900_SEARCH_DVBS2:
290 if (i_params->chip_id >= 0x20)
291 stv0900_write_reg(i_params, R0900_P1_CORRELABS,
292 0x79);
293 else
294 stv0900_write_reg(i_params, R0900_P1_CORRELABS,
295 0x68);
296 217
297 stv0900_write_reg(i_params, R0900_P1_DMDCFGMD, 218 stv0900_write_reg(intp, DMDCFGMD, 0x49);
298 0x89); 219 zigzag = FALSE;
220 break;
221 case STV0900_SEARCH_DVBS2:
222 if (intp->chip_id >= 0x20)
223 stv0900_write_reg(intp, CORRELABS, 0x79);
224 else
225 stv0900_write_reg(intp, CORRELABS, 0x68);
299 226
300 zigzag = TRUE; 227 stv0900_write_reg(intp, DMDCFGMD, 0x89);
301 break;
302 case STV0900_AUTO_SEARCH:
303 default:
304 if (i_params->chip_id >= 0x20) {
305 stv0900_write_reg(i_params, R0900_P1_CARFREQ,
306 0x3B);
307 stv0900_write_reg(i_params, R0900_P1_CORRELABS,
308 0x79);
309 } else {
310 stv0900_write_reg(i_params, R0900_P1_CARFREQ,
311 0xef);
312 stv0900_write_reg(i_params, R0900_P1_CORRELABS,
313 0x68);
314 }
315 228
316 stv0900_write_reg(i_params, R0900_P1_DMDCFGMD, 229 zigzag = TRUE;
317 0xc9); 230 break;
318 zigzag = FALSE; 231 case STV0900_AUTO_SEARCH:
319 break; 232 default:
233 if (intp->chip_id >= 0x20) {
234 stv0900_write_reg(intp, CARFREQ, 0x3b);
235 stv0900_write_reg(intp, CORRELABS, 0x79);
236 } else {
237 stv0900_write_reg(intp, CARFREQ, 0xef);
238 stv0900_write_reg(intp, CORRELABS, 0x68);
320 } 239 }
321 240
322 trialCounter = 0; 241 stv0900_write_reg(intp, DMDCFGMD, 0xc9);
323 do { 242 zigzag = FALSE;
324 lock = stv0900_search_carr_sw_loop(i_params,
325 freqIncrement,
326 softStepTimeout,
327 zigzag,
328 max_steps,
329 demod);
330 no_signal = stv0900_check_signal_presence(i_params,
331 demod);
332 trialCounter++;
333 if ((lock == TRUE)
334 || (no_signal == TRUE)
335 || (trialCounter == 2)) {
336
337 if (i_params->chip_id >= 0x20) {
338 stv0900_write_reg(i_params,
339 R0900_P1_CARFREQ,
340 0x49);
341 stv0900_write_reg(i_params,
342 R0900_P1_CORRELABS,
343 0x9e);
344 } else {
345 stv0900_write_reg(i_params,
346 R0900_P1_CARFREQ,
347 0xed);
348 stv0900_write_reg(i_params,
349 R0900_P1_CORRELABS,
350 0x88);
351 }
352
353 if ((lock == TRUE) && (stv0900_get_bits(i_params, F0900_P1_HEADER_MODE) == STV0900_DVBS2_FOUND)) {
354 msleep(softStepTimeout);
355 dvbs2_fly_wheel = stv0900_get_bits(i_params, F0900_P1_FLYWHEEL_CPT);
356
357 if (dvbs2_fly_wheel < 0xd) {
358 msleep(softStepTimeout);
359 dvbs2_fly_wheel = stv0900_get_bits(i_params, F0900_P1_FLYWHEEL_CPT);
360 }
361
362 if (dvbs2_fly_wheel < 0xd) {
363 lock = FALSE;
364
365 if (trialCounter < 2) {
366 if (i_params->chip_id >= 0x20)
367 stv0900_write_reg(i_params, R0900_P1_CORRELABS, 0x79);
368 else
369 stv0900_write_reg(i_params, R0900_P1_CORRELABS, 0x68);
370
371 stv0900_write_reg(i_params, R0900_P1_DMDCFGMD, 0x89);
372 }
373 }
374 }
375 }
376
377 } while ((lock == FALSE)
378 && (trialCounter < 2)
379 && (no_signal == FALSE));
380
381 break; 243 break;
382 case STV0900_DEMOD_2: 244 }
383 switch (i_params->dmd2_srch_stndrd) {
384 case STV0900_SEARCH_DVBS1:
385 case STV0900_SEARCH_DSS:
386 if (i_params->chip_id >= 0x20)
387 stv0900_write_reg(i_params, R0900_P2_CARFREQ,
388 0x3b);
389 else
390 stv0900_write_reg(i_params, R0900_P2_CARFREQ,
391 0xef);
392
393 stv0900_write_reg(i_params, R0900_P2_DMDCFGMD,
394 0x49);
395 zigzag = FALSE;
396 break;
397 case STV0900_SEARCH_DVBS2:
398 if (i_params->chip_id >= 0x20)
399 stv0900_write_reg(i_params, R0900_P2_CORRELABS,
400 0x79);
401 else
402 stv0900_write_reg(i_params, R0900_P2_CORRELABS,
403 0x68);
404 245
405 stv0900_write_reg(i_params, R0900_P2_DMDCFGMD, 0x89); 246 trial_cntr = 0;
406 zigzag = TRUE; 247 do {
407 break; 248 lock = stv0900_search_carr_sw_loop(intp,
408 case STV0900_AUTO_SEARCH: 249 fqc_inc,
409 default: 250 sft_stp_tout,
410 if (i_params->chip_id >= 0x20) { 251 zigzag,
411 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 252 max_steps,
412 0x3b); 253 demod);
413 stv0900_write_reg(i_params, R0900_P2_CORRELABS, 254 no_signal = stv0900_check_signal_presence(intp, demod);
414 0x79); 255 trial_cntr++;
256 if ((lock == TRUE)
257 || (no_signal == TRUE)
258 || (trial_cntr == 2)) {
259
260 if (intp->chip_id >= 0x20) {
261 stv0900_write_reg(intp, CARFREQ, 0x49);
262 stv0900_write_reg(intp, CORRELABS, 0x9e);
415 } else { 263 } else {
416 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 264 stv0900_write_reg(intp, CARFREQ, 0xed);
417 0xef); 265 stv0900_write_reg(intp, CORRELABS, 0x88);
418 stv0900_write_reg(i_params, R0900_P2_CORRELABS,
419 0x68);
420 } 266 }
421 267
422 stv0900_write_reg(i_params, R0900_P2_DMDCFGMD, 0xc9); 268 if ((stv0900_get_bits(intp, HEADER_MODE) ==
423 269 STV0900_DVBS2_FOUND) &&
424 zigzag = FALSE; 270 (lock == TRUE)) {
425 break; 271 msleep(sft_stp_tout);
426 } 272 s2fw = stv0900_get_bits(intp, FLYWHEEL_CPT);
427 273
428 trialCounter = 0; 274 if (s2fw < 0xd) {
429 275 msleep(sft_stp_tout);
430 do { 276 s2fw = stv0900_get_bits(intp,
431 lock = stv0900_search_carr_sw_loop(i_params, 277 FLYWHEEL_CPT);
432 freqIncrement,
433 softStepTimeout,
434 zigzag,
435 max_steps,
436 demod);
437 no_signal = stv0900_check_signal_presence(i_params,
438 demod);
439 trialCounter++;
440 if ((lock == TRUE)
441 || (no_signal == TRUE)
442 || (trialCounter == 2)) {
443 if (i_params->chip_id >= 0x20) {
444 stv0900_write_reg(i_params,
445 R0900_P2_CARFREQ,
446 0x49);
447 stv0900_write_reg(i_params,
448 R0900_P2_CORRELABS,
449 0x9e);
450 } else {
451 stv0900_write_reg(i_params,
452 R0900_P2_CARFREQ,
453 0xed);
454 stv0900_write_reg(i_params,
455 R0900_P2_CORRELABS,
456 0x88);
457 } 278 }
458 279
459 if ((lock == TRUE) && (stv0900_get_bits(i_params, F0900_P2_HEADER_MODE) == STV0900_DVBS2_FOUND)) { 280 if (s2fw < 0xd) {
460 msleep(softStepTimeout); 281 lock = FALSE;
461 dvbs2_fly_wheel = stv0900_get_bits(i_params, F0900_P2_FLYWHEEL_CPT);
462 if (dvbs2_fly_wheel < 0xd) {
463 msleep(softStepTimeout);
464 dvbs2_fly_wheel = stv0900_get_bits(i_params, F0900_P2_FLYWHEEL_CPT);
465 }
466 282
467 if (dvbs2_fly_wheel < 0xd) { 283 if (trial_cntr < 2) {
468 lock = FALSE; 284 if (intp->chip_id >= 0x20)
469 if (trialCounter < 2) { 285 stv0900_write_reg(intp,
470 if (i_params->chip_id >= 0x20) 286 CORRELABS,
471 stv0900_write_reg(i_params, R0900_P2_CORRELABS, 0x79); 287 0x79);
472 else 288 else
473 stv0900_write_reg(i_params, R0900_P2_CORRELABS, 0x68); 289 stv0900_write_reg(intp,
290 CORRELABS,
291 0x68);
474 292
475 stv0900_write_reg(i_params, R0900_P2_DMDCFGMD, 0x89); 293 stv0900_write_reg(intp,
476 } 294 DMDCFGMD,
295 0x89);
477 } 296 }
478 } 297 }
479 } 298 }
299 }
480 300
481 } while ((lock == FALSE) && (trialCounter < 2) && (no_signal == FALSE)); 301 } while ((lock == FALSE)
482 302 && (trial_cntr < 2)
483 break; 303 && (no_signal == FALSE));
484 }
485 304
486 return lock; 305 return lock;
487} 306}
488 307
489static u32 stv0900_get_symbol_rate(struct stv0900_internal *i_params, 308static u32 stv0900_get_symbol_rate(struct stv0900_internal *intp,
490 u32 mclk, 309 u32 mclk,
491 enum fe_stv0900_demod_num demod) 310 enum fe_stv0900_demod_num demod)
492{ 311{
493 s32 sfr_field3, sfr_field2, sfr_field1, sfr_field0, 312 s32 rem1, rem2, intval1, intval2, srate;
494 rem1, rem2, intval1, intval2, srate; 313
495 314 srate = (stv0900_get_bits(intp, SYMB_FREQ3) << 24) +
496 dmd_reg(sfr_field3, F0900_P1_SYMB_FREQ3, F0900_P2_SYMB_FREQ3); 315 (stv0900_get_bits(intp, SYMB_FREQ2) << 16) +
497 dmd_reg(sfr_field2, F0900_P1_SYMB_FREQ2, F0900_P2_SYMB_FREQ2); 316 (stv0900_get_bits(intp, SYMB_FREQ1) << 8) +
498 dmd_reg(sfr_field1, F0900_P1_SYMB_FREQ1, F0900_P2_SYMB_FREQ1); 317 (stv0900_get_bits(intp, SYMB_FREQ0));
499 dmd_reg(sfr_field0, F0900_P1_SYMB_FREQ0, F0900_P2_SYMB_FREQ0);
500
501 srate = (stv0900_get_bits(i_params, sfr_field3) << 24) +
502 (stv0900_get_bits(i_params, sfr_field2) << 16) +
503 (stv0900_get_bits(i_params, sfr_field1) << 8) +
504 (stv0900_get_bits(i_params, sfr_field0));
505 dprintk("lock: srate=%d r0=0x%x r1=0x%x r2=0x%x r3=0x%x \n", 318 dprintk("lock: srate=%d r0=0x%x r1=0x%x r2=0x%x r3=0x%x \n",
506 srate, stv0900_get_bits(i_params, sfr_field0), 319 srate, stv0900_get_bits(intp, SYMB_FREQ0),
507 stv0900_get_bits(i_params, sfr_field1), 320 stv0900_get_bits(intp, SYMB_FREQ1),
508 stv0900_get_bits(i_params, sfr_field2), 321 stv0900_get_bits(intp, SYMB_FREQ2),
509 stv0900_get_bits(i_params, sfr_field3)); 322 stv0900_get_bits(intp, SYMB_FREQ3));
510 323
511 intval1 = (mclk) >> 16; 324 intval1 = (mclk) >> 16;
512 intval2 = (srate) >> 16; 325 intval2 = (srate) >> 16;
@@ -520,18 +333,15 @@ static u32 stv0900_get_symbol_rate(struct stv0900_internal *i_params,
520 return srate; 333 return srate;
521} 334}
522 335
523static void stv0900_set_symbol_rate(struct stv0900_internal *i_params, 336static void stv0900_set_symbol_rate(struct stv0900_internal *intp,
524 u32 mclk, u32 srate, 337 u32 mclk, u32 srate,
525 enum fe_stv0900_demod_num demod) 338 enum fe_stv0900_demod_num demod)
526{ 339{
527 s32 sfr_init_reg;
528 u32 symb; 340 u32 symb;
529 341
530 dprintk("%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk, 342 dprintk("%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk,
531 srate, demod); 343 srate, demod);
532 344
533 dmd_reg(sfr_init_reg, R0900_P1_SFRINIT1, R0900_P2_SFRINIT1);
534
535 if (srate > 60000000) { 345 if (srate > 60000000) {
536 symb = srate << 4; 346 symb = srate << 4;
537 symb /= (mclk >> 12); 347 symb /= (mclk >> 12);
@@ -543,19 +353,16 @@ static void stv0900_set_symbol_rate(struct stv0900_internal *i_params,
543 symb /= (mclk >> 7); 353 symb /= (mclk >> 7);
544 } 354 }
545 355
546 stv0900_write_reg(i_params, sfr_init_reg, (symb >> 8) & 0x7F); 356 stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0x7f);
547 stv0900_write_reg(i_params, sfr_init_reg + 1, (symb & 0xFF)); 357 stv0900_write_reg(intp, SFRINIT1 + 1, (symb & 0xff));
548} 358}
549 359
550static void stv0900_set_max_symbol_rate(struct stv0900_internal *i_params, 360static void stv0900_set_max_symbol_rate(struct stv0900_internal *intp,
551 u32 mclk, u32 srate, 361 u32 mclk, u32 srate,
552 enum fe_stv0900_demod_num demod) 362 enum fe_stv0900_demod_num demod)
553{ 363{
554 s32 sfr_max_reg;
555 u32 symb; 364 u32 symb;
556 365
557 dmd_reg(sfr_max_reg, R0900_P1_SFRUP1, R0900_P2_SFRUP1);
558
559 srate = 105 * (srate / 100); 366 srate = 105 * (srate / 100);
560 367
561 if (srate > 60000000) { 368 if (srate > 60000000) {
@@ -570,23 +377,20 @@ static void stv0900_set_max_symbol_rate(struct stv0900_internal *i_params,
570 } 377 }
571 378
572 if (symb < 0x7fff) { 379 if (symb < 0x7fff) {
573 stv0900_write_reg(i_params, sfr_max_reg, (symb >> 8) & 0x7F); 380 stv0900_write_reg(intp, SFRUP1, (symb >> 8) & 0x7f);
574 stv0900_write_reg(i_params, sfr_max_reg + 1, (symb & 0xFF)); 381 stv0900_write_reg(intp, SFRUP1 + 1, (symb & 0xff));
575 } else { 382 } else {
576 stv0900_write_reg(i_params, sfr_max_reg, 0x7F); 383 stv0900_write_reg(intp, SFRUP1, 0x7f);
577 stv0900_write_reg(i_params, sfr_max_reg + 1, 0xFF); 384 stv0900_write_reg(intp, SFRUP1 + 1, 0xff);
578 } 385 }
579} 386}
580 387
581static void stv0900_set_min_symbol_rate(struct stv0900_internal *i_params, 388static void stv0900_set_min_symbol_rate(struct stv0900_internal *intp,
582 u32 mclk, u32 srate, 389 u32 mclk, u32 srate,
583 enum fe_stv0900_demod_num demod) 390 enum fe_stv0900_demod_num demod)
584{ 391{
585 s32 sfr_min_reg;
586 u32 symb; 392 u32 symb;
587 393
588 dmd_reg(sfr_min_reg, R0900_P1_SFRLOW1, R0900_P2_SFRLOW1);
589
590 srate = 95 * (srate / 100); 394 srate = 95 * (srate / 100);
591 if (srate > 60000000) { 395 if (srate > 60000000) {
592 symb = srate << 4; 396 symb = srate << 4;
@@ -601,22 +405,20 @@ static void stv0900_set_min_symbol_rate(struct stv0900_internal *i_params,
601 symb /= (mclk >> 7); 405 symb /= (mclk >> 7);
602 } 406 }
603 407
604 stv0900_write_reg(i_params, sfr_min_reg, (symb >> 8) & 0xFF); 408 stv0900_write_reg(intp, SFRLOW1, (symb >> 8) & 0xff);
605 stv0900_write_reg(i_params, sfr_min_reg + 1, (symb & 0xFF)); 409 stv0900_write_reg(intp, SFRLOW1 + 1, (symb & 0xff));
606} 410}
607 411
608static s32 stv0900_get_timing_offst(struct stv0900_internal *i_params, 412static s32 stv0900_get_timing_offst(struct stv0900_internal *intp,
609 u32 srate, 413 u32 srate,
610 enum fe_stv0900_demod_num demod) 414 enum fe_stv0900_demod_num demod)
611{ 415{
612 s32 tmgreg, 416 s32 timingoffset;
613 timingoffset;
614 417
615 dmd_reg(tmgreg, R0900_P1_TMGREG2, R0900_P2_TMGREG2);
616 418
617 timingoffset = (stv0900_read_reg(i_params, tmgreg) << 16) + 419 timingoffset = (stv0900_read_reg(intp, TMGREG2) << 16) +
618 (stv0900_read_reg(i_params, tmgreg + 1) << 8) + 420 (stv0900_read_reg(intp, TMGREG2 + 1) << 8) +
619 (stv0900_read_reg(i_params, tmgreg + 2)); 421 (stv0900_read_reg(intp, TMGREG2 + 2));
620 422
621 timingoffset = ge2comp(timingoffset, 24); 423 timingoffset = ge2comp(timingoffset, 24);
622 424
@@ -630,22 +432,19 @@ static s32 stv0900_get_timing_offst(struct stv0900_internal *i_params,
630 return timingoffset; 432 return timingoffset;
631} 433}
632 434
633static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *i_params, 435static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *intp,
634 enum fe_stv0900_demod_num demod) 436 enum fe_stv0900_demod_num demod)
635{ 437{
636 s32 rolloff, man_fld, matstr_reg, rolloff_ctl_fld; 438 s32 rolloff;
637 439
638 dmd_reg(man_fld, F0900_P1_MANUAL_ROLLOFF, F0900_P2_MANUAL_ROLLOFF); 440 if (intp->chip_id == 0x10) {
639 dmd_reg(matstr_reg, R0900_P1_MATSTR1, R0900_P2_MATSTR1); 441 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
640 dmd_reg(rolloff_ctl_fld, F0900_P1_ROLLOFF_CONTROL, 442 rolloff = stv0900_read_reg(intp, MATSTR1) & 0x03;
641 F0900_P2_ROLLOFF_CONTROL); 443 stv0900_write_bits(intp, ROLLOFF_CONTROL, rolloff);
642 444 } else if (intp->chip_id <= 0x20)
643 if (i_params->chip_id == 0x10) { 445 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 0);
644 stv0900_write_bits(i_params, man_fld, 1); 446 else /* cut 3.0 */
645 rolloff = stv0900_read_reg(i_params, matstr_reg) & 0x03; 447 stv0900_write_bits(intp, MANUALS2_ROLLOFF, 0);
646 stv0900_write_bits(i_params, rolloff_ctl_fld, rolloff);
647 } else
648 stv0900_write_bits(i_params, man_fld, 0);
649} 448}
650 449
651static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro) 450static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro)
@@ -668,84 +467,47 @@ static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro)
668 return srate + (srate * rolloff) / 100; 467 return srate + (srate * rolloff) / 100;
669} 468}
670 469
671static int stv0900_check_timing_lock(struct stv0900_internal *i_params, 470static int stv0900_check_timing_lock(struct stv0900_internal *intp,
672 enum fe_stv0900_demod_num demod) 471 enum fe_stv0900_demod_num demod)
673{ 472{
674 int timingLock = FALSE; 473 int timingLock = FALSE;
675 s32 i, 474 s32 i,
676 timingcpt = 0; 475 timingcpt = 0;
677 u8 carFreq, 476 u8 car_freq,
678 tmgTHhigh, 477 tmg_th_high,
679 tmgTHLow; 478 tmg_th_low;
680 479
681 switch (demod) { 480 car_freq = stv0900_read_reg(intp, CARFREQ);
682 case STV0900_DEMOD_1: 481 tmg_th_high = stv0900_read_reg(intp, TMGTHRISE);
683 default: 482 tmg_th_low = stv0900_read_reg(intp, TMGTHFALL);
684 carFreq = stv0900_read_reg(i_params, R0900_P1_CARFREQ); 483 stv0900_write_reg(intp, TMGTHRISE, 0x20);
685 tmgTHhigh = stv0900_read_reg(i_params, R0900_P1_TMGTHRISE); 484 stv0900_write_reg(intp, TMGTHFALL, 0x0);
686 tmgTHLow = stv0900_read_reg(i_params, R0900_P1_TMGTHFALL); 485 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
687 stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0x20); 486 stv0900_write_reg(intp, RTC, 0x80);
688 stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0x0); 487 stv0900_write_reg(intp, RTCS2, 0x40);
689 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0); 488 stv0900_write_reg(intp, CARFREQ, 0x0);
690 stv0900_write_reg(i_params, R0900_P1_RTC, 0x80); 489 stv0900_write_reg(intp, CFRINIT1, 0x0);
691 stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x40); 490 stv0900_write_reg(intp, CFRINIT0, 0x0);
692 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x0); 491 stv0900_write_reg(intp, AGC2REF, 0x65);
693 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, 0x0); 492 stv0900_write_reg(intp, DMDISTATE, 0x18);
694 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, 0x0); 493 msleep(7);
695 stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x65); 494
696 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18); 495 for (i = 0; i < 10; i++) {
697 msleep(7); 496 if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
698 497 timingcpt++;
699 for (i = 0; i < 10; i++) { 498
700 if (stv0900_get_bits(i_params, F0900_P1_TMGLOCK_QUALITY) >= 2) 499 msleep(1);
701 timingcpt++; 500 }
702
703 msleep(1);
704 }
705
706 if (timingcpt >= 3)
707 timingLock = TRUE;
708
709 stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x38);
710 stv0900_write_reg(i_params, R0900_P1_RTC, 0x88);
711 stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x68);
712 stv0900_write_reg(i_params, R0900_P1_CARFREQ, carFreq);
713 stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, tmgTHhigh);
714 stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, tmgTHLow);
715 break;
716 case STV0900_DEMOD_2:
717 carFreq = stv0900_read_reg(i_params, R0900_P2_CARFREQ);
718 tmgTHhigh = stv0900_read_reg(i_params, R0900_P2_TMGTHRISE);
719 tmgTHLow = stv0900_read_reg(i_params, R0900_P2_TMGTHFALL);
720 stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0x20);
721 stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0);
722 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
723 stv0900_write_reg(i_params, R0900_P2_RTC, 0x80);
724 stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x40);
725 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x0);
726 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, 0x0);
727 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, 0x0);
728 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x65);
729 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
730 msleep(5);
731 for (i = 0; i < 10; i++) {
732 if (stv0900_get_bits(i_params, F0900_P2_TMGLOCK_QUALITY) >= 2)
733 timingcpt++;
734 501
735 msleep(1); 502 if (timingcpt >= 3)
736 } 503 timingLock = TRUE;
737 504
738 if (timingcpt >= 3) 505 stv0900_write_reg(intp, AGC2REF, 0x38);
739 timingLock = TRUE; 506 stv0900_write_reg(intp, RTC, 0x88);
740 507 stv0900_write_reg(intp, RTCS2, 0x68);
741 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x38); 508 stv0900_write_reg(intp, CARFREQ, car_freq);
742 stv0900_write_reg(i_params, R0900_P2_RTC, 0x88); 509 stv0900_write_reg(intp, TMGTHRISE, tmg_th_high);
743 stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x68); 510 stv0900_write_reg(intp, TMGTHFALL, tmg_th_low);
744 stv0900_write_reg(i_params, R0900_P2_CARFREQ, carFreq);
745 stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, tmgTHhigh);
746 stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, tmgTHLow);
747 break;
748 }
749 511
750 return timingLock; 512 return timingLock;
751} 513}
@@ -754,142 +516,114 @@ static int stv0900_get_demod_cold_lock(struct dvb_frontend *fe,
754 s32 demod_timeout) 516 s32 demod_timeout)
755{ 517{
756 struct stv0900_state *state = fe->demodulator_priv; 518 struct stv0900_state *state = fe->demodulator_priv;
757 struct stv0900_internal *i_params = state->internal; 519 struct stv0900_internal *intp = state->internal;
758 enum fe_stv0900_demod_num demod = state->demod; 520 enum fe_stv0900_demod_num demod = state->demod;
521 int lock = FALSE,
522 d = demod;
523 s32 srate,
524 search_range,
525 locktimeout,
526 currier_step,
527 nb_steps,
528 current_step,
529 direction,
530 tuner_freq,
531 timeout,
532 freq;
759 533
760 int lock = FALSE; 534 srate = intp->symbol_rate[d];
761 s32 srate, search_range, locktimeout, 535 search_range = intp->srch_range[d];
762 currier_step, nb_steps, current_step,
763 direction, tuner_freq, timeout;
764
765 switch (demod) {
766 case STV0900_DEMOD_1:
767 default:
768 srate = i_params->dmd1_symbol_rate;
769 search_range = i_params->dmd1_srch_range;
770 break;
771
772 case STV0900_DEMOD_2:
773 srate = i_params->dmd2_symbol_rate;
774 search_range = i_params->dmd2_srch_range;
775 break;
776 }
777 536
778 if (srate >= 10000000) 537 if (srate >= 10000000)
779 locktimeout = demod_timeout / 3; 538 locktimeout = demod_timeout / 3;
780 else 539 else
781 locktimeout = demod_timeout / 2; 540 locktimeout = demod_timeout / 2;
782 541
783 lock = stv0900_get_demod_lock(i_params, demod, locktimeout); 542 lock = stv0900_get_demod_lock(intp, d, locktimeout);
784
785 if (lock == FALSE) {
786 if (srate >= 10000000) {
787 if (stv0900_check_timing_lock(i_params, demod) == TRUE) {
788 switch (demod) {
789 case STV0900_DEMOD_1:
790 default:
791 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1f);
792 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
793 break;
794 case STV0900_DEMOD_2:
795 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1f);
796 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
797 break;
798 }
799 543
800 lock = stv0900_get_demod_lock(i_params, demod, demod_timeout); 544 if (lock != FALSE)
801 } else 545 return lock;
802 lock = FALSE; 546
803 } else { 547 if (srate >= 10000000) {
804 if (srate <= 4000000) 548 if (stv0900_check_timing_lock(intp, d) == TRUE) {
805 currier_step = 1000; 549 stv0900_write_reg(intp, DMDISTATE, 0x1f);
806 else if (srate <= 7000000) 550 stv0900_write_reg(intp, DMDISTATE, 0x15);
807 currier_step = 2000; 551 lock = stv0900_get_demod_lock(intp, d, demod_timeout);
808 else if (srate <= 10000000) 552 } else
809 currier_step = 3000; 553 lock = FALSE;
810 else 554
811 currier_step = 5000; 555 return lock;
812 556 }
813 nb_steps = ((search_range / 1000) / currier_step); 557
814 nb_steps /= 2; 558 if (intp->chip_id <= 0x20) {
815 nb_steps = (2 * (nb_steps + 1)); 559 if (srate <= 1000000)
816 if (nb_steps < 0) 560 currier_step = 500;
817 nb_steps = 2; 561 else if (srate <= 4000000)
818 else if (nb_steps > 12) 562 currier_step = 1000;
819 nb_steps = 12; 563 else if (srate <= 7000000)
820 564 currier_step = 2000;
821 current_step = 1; 565 else if (srate <= 10000000)
822 direction = 1; 566 currier_step = 3000;
567 else
568 currier_step = 5000;
569
570 if (srate >= 2000000) {
823 timeout = (demod_timeout / 3); 571 timeout = (demod_timeout / 3);
824 if (timeout > 1000) 572 if (timeout > 1000)
825 timeout = 1000; 573 timeout = 1000;
574 } else
575 timeout = (demod_timeout / 2);
576 } else {
577 /*cut 3.0 */
578 currier_step = srate / 4000;
579 timeout = (demod_timeout * 3) / 4;
580 }
826 581
827 switch (demod) { 582 nb_steps = ((search_range / 1000) / currier_step);
828 case STV0900_DEMOD_1:
829 default:
830 if (lock == FALSE) {
831 tuner_freq = i_params->tuner1_freq;
832 i_params->tuner1_bw = stv0900_carrier_width(i_params->dmd1_symbol_rate, i_params->rolloff) + i_params->dmd1_symbol_rate;
833 583
834 while ((current_step <= nb_steps) && (lock == FALSE)) { 584 if ((nb_steps % 2) != 0)
585 nb_steps += 1;
835 586
836 if (direction > 0) 587 if (nb_steps <= 0)
837 tuner_freq += (current_step * currier_step); 588 nb_steps = 2;
838 else 589 else if (nb_steps > 12)
839 tuner_freq -= (current_step * currier_step); 590 nb_steps = 12;
840
841 stv0900_set_tuner(fe, tuner_freq, i_params->tuner1_bw);
842 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1C);
843 if (i_params->dmd1_srch_standard == STV0900_SEARCH_DVBS2) {
844 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 0);
845 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
846 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
847 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
848 }
849
850 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, 0);
851 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, 0);
852 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1F);
853 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15);
854 lock = stv0900_get_demod_lock(i_params, demod, timeout);
855 direction *= -1;
856 current_step++;
857 }
858 }
859 break;
860 case STV0900_DEMOD_2:
861 if (lock == FALSE) {
862 tuner_freq = i_params->tuner2_freq;
863 i_params->tuner2_bw = stv0900_carrier_width(srate, i_params->rolloff) + srate;
864 591
865 while ((current_step <= nb_steps) && (lock == FALSE)) { 592 current_step = 1;
593 direction = 1;
866 594
867 if (direction > 0) 595 if (intp->chip_id <= 0x20) {
868 tuner_freq += (current_step * currier_step); 596 tuner_freq = intp->freq[d];
869 else 597 intp->bw[d] = stv0900_carrier_width(intp->symbol_rate[d],
870 tuner_freq -= (current_step * currier_step); 598 intp->rolloff) + intp->symbol_rate[d];
871 599 } else
872 stv0900_set_tuner(fe, tuner_freq, i_params->tuner2_bw); 600 tuner_freq = 0;
873 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1C); 601
874 if (i_params->dmd2_srch_stndrd == STV0900_SEARCH_DVBS2) { 602 while ((current_step <= nb_steps) && (lock == FALSE)) {
875 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 0); 603 if (direction > 0)
876 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0); 604 tuner_freq += (current_step * currier_step);
877 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1); 605 else
878 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1); 606 tuner_freq -= (current_step * currier_step);
879 } 607
880 608 if (intp->chip_id <= 0x20) {
881 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, 0); 609 stv0900_set_tuner(fe, tuner_freq, intp->bw[d]);
882 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, 0); 610 stv0900_write_reg(intp, DMDISTATE, 0x1c);
883 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1F); 611 stv0900_write_reg(intp, CFRINIT1, 0);
884 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15); 612 stv0900_write_reg(intp, CFRINIT0, 0);
885 lock = stv0900_get_demod_lock(i_params, demod, timeout); 613 stv0900_write_reg(intp, DMDISTATE, 0x1f);
886 direction *= -1; 614 stv0900_write_reg(intp, DMDISTATE, 0x15);
887 current_step++; 615 } else {
888 } 616 stv0900_write_reg(intp, DMDISTATE, 0x1c);
889 } 617 freq = (tuner_freq * 65536) / (intp->mclk / 1000);
890 break; 618 stv0900_write_bits(intp, CFR_INIT1, MSB(freq));
891 } 619 stv0900_write_bits(intp, CFR_INIT0, LSB(freq));
620 stv0900_write_reg(intp, DMDISTATE, 0x1f);
621 stv0900_write_reg(intp, DMDISTATE, 0x05);
892 } 622 }
623
624 lock = stv0900_get_demod_lock(intp, d, timeout);
625 direction *= -1;
626 current_step++;
893 } 627 }
894 628
895 return lock; 629 return lock;
@@ -931,9 +665,7 @@ static void stv0900_get_lock_timeout(s32 *demod_timeout, s32 *fec_timeout,
931 } else if (srate <= 20000000) { 665 } else if (srate <= 20000000) {
932 (*demod_timeout) = 400; 666 (*demod_timeout) = 400;
933 (*fec_timeout) = 130; 667 (*fec_timeout) = 130;
934 } 668 } else {
935
936 else {
937 (*demod_timeout) = 300; 669 (*demod_timeout) = 300;
938 (*fec_timeout) = 100; 670 (*fec_timeout) = 100;
939 } 671 }
@@ -946,95 +678,77 @@ static void stv0900_get_lock_timeout(s32 *demod_timeout, s32 *fec_timeout,
946 (*demod_timeout) /= 2; 678 (*demod_timeout) /= 2;
947} 679}
948 680
949static void stv0900_set_viterbi_tracq(struct stv0900_internal *i_params, 681static void stv0900_set_viterbi_tracq(struct stv0900_internal *intp,
950 enum fe_stv0900_demod_num demod) 682 enum fe_stv0900_demod_num demod)
951{ 683{
952 684
953 s32 vth_reg; 685 s32 vth_reg = VTH12;
954 686
955 dprintk("%s\n", __func__); 687 dprintk("%s\n", __func__);
956 688
957 dmd_reg(vth_reg, R0900_P1_VTH12, R0900_P2_VTH12); 689 stv0900_write_reg(intp, vth_reg++, 0xd0);
958 690 stv0900_write_reg(intp, vth_reg++, 0x7d);
959 stv0900_write_reg(i_params, vth_reg++, 0xd0); 691 stv0900_write_reg(intp, vth_reg++, 0x53);
960 stv0900_write_reg(i_params, vth_reg++, 0x7d); 692 stv0900_write_reg(intp, vth_reg++, 0x2f);
961 stv0900_write_reg(i_params, vth_reg++, 0x53); 693 stv0900_write_reg(intp, vth_reg++, 0x24);
962 stv0900_write_reg(i_params, vth_reg++, 0x2F); 694 stv0900_write_reg(intp, vth_reg++, 0x1f);
963 stv0900_write_reg(i_params, vth_reg++, 0x24);
964 stv0900_write_reg(i_params, vth_reg++, 0x1F);
965} 695}
966 696
967static void stv0900_set_viterbi_standard(struct stv0900_internal *i_params, 697static void stv0900_set_viterbi_standard(struct stv0900_internal *intp,
968 enum fe_stv0900_search_standard Standard, 698 enum fe_stv0900_search_standard standard,
969 enum fe_stv0900_fec PunctureRate, 699 enum fe_stv0900_fec fec,
970 enum fe_stv0900_demod_num demod) 700 enum fe_stv0900_demod_num demod)
971{ 701{
972
973 s32 fecmReg,
974 prvitReg;
975
976 dprintk("%s: ViterbiStandard = ", __func__); 702 dprintk("%s: ViterbiStandard = ", __func__);
977 703
978 switch (demod) { 704 switch (standard) {
979 case STV0900_DEMOD_1:
980 default:
981 fecmReg = R0900_P1_FECM;
982 prvitReg = R0900_P1_PRVIT;
983 break;
984 case STV0900_DEMOD_2:
985 fecmReg = R0900_P2_FECM;
986 prvitReg = R0900_P2_PRVIT;
987 break;
988 }
989
990 switch (Standard) {
991 case STV0900_AUTO_SEARCH: 705 case STV0900_AUTO_SEARCH:
992 dprintk("Auto\n"); 706 dprintk("Auto\n");
993 stv0900_write_reg(i_params, fecmReg, 0x10); 707 stv0900_write_reg(intp, FECM, 0x10);
994 stv0900_write_reg(i_params, prvitReg, 0x3F); 708 stv0900_write_reg(intp, PRVIT, 0x3f);
995 break; 709 break;
996 case STV0900_SEARCH_DVBS1: 710 case STV0900_SEARCH_DVBS1:
997 dprintk("DVBS1\n"); 711 dprintk("DVBS1\n");
998 stv0900_write_reg(i_params, fecmReg, 0x00); 712 stv0900_write_reg(intp, FECM, 0x00);
999 switch (PunctureRate) { 713 switch (fec) {
1000 case STV0900_FEC_UNKNOWN: 714 case STV0900_FEC_UNKNOWN:
1001 default: 715 default:
1002 stv0900_write_reg(i_params, prvitReg, 0x2F); 716 stv0900_write_reg(intp, PRVIT, 0x2f);
1003 break; 717 break;
1004 case STV0900_FEC_1_2: 718 case STV0900_FEC_1_2:
1005 stv0900_write_reg(i_params, prvitReg, 0x01); 719 stv0900_write_reg(intp, PRVIT, 0x01);
1006 break; 720 break;
1007 case STV0900_FEC_2_3: 721 case STV0900_FEC_2_3:
1008 stv0900_write_reg(i_params, prvitReg, 0x02); 722 stv0900_write_reg(intp, PRVIT, 0x02);
1009 break; 723 break;
1010 case STV0900_FEC_3_4: 724 case STV0900_FEC_3_4:
1011 stv0900_write_reg(i_params, prvitReg, 0x04); 725 stv0900_write_reg(intp, PRVIT, 0x04);
1012 break; 726 break;
1013 case STV0900_FEC_5_6: 727 case STV0900_FEC_5_6:
1014 stv0900_write_reg(i_params, prvitReg, 0x08); 728 stv0900_write_reg(intp, PRVIT, 0x08);
1015 break; 729 break;
1016 case STV0900_FEC_7_8: 730 case STV0900_FEC_7_8:
1017 stv0900_write_reg(i_params, prvitReg, 0x20); 731 stv0900_write_reg(intp, PRVIT, 0x20);
1018 break; 732 break;
1019 } 733 }
1020 734
1021 break; 735 break;
1022 case STV0900_SEARCH_DSS: 736 case STV0900_SEARCH_DSS:
1023 dprintk("DSS\n"); 737 dprintk("DSS\n");
1024 stv0900_write_reg(i_params, fecmReg, 0x80); 738 stv0900_write_reg(intp, FECM, 0x80);
1025 switch (PunctureRate) { 739 switch (fec) {
1026 case STV0900_FEC_UNKNOWN: 740 case STV0900_FEC_UNKNOWN:
1027 default: 741 default:
1028 stv0900_write_reg(i_params, prvitReg, 0x13); 742 stv0900_write_reg(intp, PRVIT, 0x13);
1029 break; 743 break;
1030 case STV0900_FEC_1_2: 744 case STV0900_FEC_1_2:
1031 stv0900_write_reg(i_params, prvitReg, 0x01); 745 stv0900_write_reg(intp, PRVIT, 0x01);
1032 break; 746 break;
1033 case STV0900_FEC_2_3: 747 case STV0900_FEC_2_3:
1034 stv0900_write_reg(i_params, prvitReg, 0x02); 748 stv0900_write_reg(intp, PRVIT, 0x02);
1035 break; 749 break;
1036 case STV0900_FEC_6_7: 750 case STV0900_FEC_6_7:
1037 stv0900_write_reg(i_params, prvitReg, 0x10); 751 stv0900_write_reg(intp, PRVIT, 0x10);
1038 break; 752 break;
1039 } 753 }
1040 break; 754 break;
@@ -1043,340 +757,277 @@ static void stv0900_set_viterbi_standard(struct stv0900_internal *i_params,
1043 } 757 }
1044} 758}
1045 759
1046static void stv0900_track_optimization(struct dvb_frontend *fe) 760static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *intp,
761 enum fe_stv0900_demod_num demod)
1047{ 762{
1048 struct stv0900_state *state = fe->demodulator_priv; 763 enum fe_stv0900_fec prate;
1049 struct stv0900_internal *i_params = state->internal; 764 s32 rate_fld = stv0900_get_bits(intp, VIT_CURPUN);
1050 enum fe_stv0900_demod_num demod = state->demod;
1051 765
1052 s32 srate, pilots, aclc, freq1, freq0, 766 switch (rate_fld) {
1053 i = 0, timed, timef, blindTunSw = 0; 767 case 13:
768 prate = STV0900_FEC_1_2;
769 break;
770 case 18:
771 prate = STV0900_FEC_2_3;
772 break;
773 case 21:
774 prate = STV0900_FEC_3_4;
775 break;
776 case 24:
777 prate = STV0900_FEC_5_6;
778 break;
779 case 25:
780 prate = STV0900_FEC_6_7;
781 break;
782 case 26:
783 prate = STV0900_FEC_7_8;
784 break;
785 default:
786 prate = STV0900_FEC_UNKNOWN;
787 break;
788 }
1054 789
1055 enum fe_stv0900_rolloff rolloff; 790 return prate;
1056 enum fe_stv0900_modcode foundModcod; 791}
1057 792
1058 dprintk("%s\n", __func__); 793void stv0900_set_dvbs1_track_car_loop(struct stv0900_internal *intp,
794 enum fe_stv0900_demod_num demod,
795 u32 srate)
796{
797 if (intp->chip_id >= 0x30) {
798 if (srate >= 15000000) {
799 stv0900_write_reg(intp, ACLC, 0x2b);
800 stv0900_write_reg(intp, BCLC, 0x1a);
801 } else if ((srate >= 7000000) && (15000000 > srate)) {
802 stv0900_write_reg(intp, ACLC, 0x0c);
803 stv0900_write_reg(intp, BCLC, 0x1b);
804 } else if (srate < 7000000) {
805 stv0900_write_reg(intp, ACLC, 0x2c);
806 stv0900_write_reg(intp, BCLC, 0x1c);
807 }
1059 808
1060 srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod); 809 } else { /*cut 2.0 and 1.x*/
1061 srate += stv0900_get_timing_offst(i_params, srate, demod); 810 stv0900_write_reg(intp, ACLC, 0x1a);
811 stv0900_write_reg(intp, BCLC, 0x09);
812 }
1062 813
1063 switch (demod) { 814}
1064 case STV0900_DEMOD_1:
1065 default:
1066 switch (i_params->dmd1_rslts.standard) {
1067 case STV0900_DVBS1_STANDARD:
1068 if (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH) {
1069 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
1070 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
1071 }
1072 815
1073 stv0900_write_bits(i_params, F0900_P1_ROLLOFF_CONTROL, i_params->rolloff); 816static void stv0900_track_optimization(struct dvb_frontend *fe)
1074 stv0900_write_bits(i_params, F0900_P1_MANUAL_ROLLOFF, 1); 817{
1075 stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x75); 818 struct stv0900_state *state = fe->demodulator_priv;
1076 break; 819 struct stv0900_internal *intp = state->internal;
1077 case STV0900_DSS_STANDARD: 820 enum fe_stv0900_demod_num demod = state->demod;
1078 if (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH) {
1079 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
1080 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
1081 }
1082 821
1083 stv0900_write_bits(i_params, F0900_P1_ROLLOFF_CONTROL, i_params->rolloff); 822 s32 srate,
1084 stv0900_write_bits(i_params, F0900_P1_MANUAL_ROLLOFF, 1); 823 pilots,
1085 stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x75); 824 aclc,
1086 break; 825 freq1,
1087 case STV0900_DVBS2_STANDARD: 826 freq0,
1088 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 0); 827 i = 0,
1089 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1); 828 timed,
1090 stv0900_write_reg(i_params, R0900_P1_ACLC, 0); 829 timef,
1091 stv0900_write_reg(i_params, R0900_P1_BCLC, 0); 830 blind_tun_sw = 0,
1092 if (i_params->dmd1_rslts.frame_length == STV0900_LONG_FRAME) { 831 modulation;
1093 foundModcod = stv0900_get_bits(i_params, F0900_P1_DEMOD_MODCOD);
1094 pilots = stv0900_get_bits(i_params, F0900_P1_DEMOD_TYPE) & 0x01;
1095 aclc = stv0900_get_optim_carr_loop(srate, foundModcod, pilots, i_params->chip_id);
1096 if (foundModcod <= STV0900_QPSK_910)
1097 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, aclc);
1098 else if (foundModcod <= STV0900_8PSK_910) {
1099 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
1100 stv0900_write_reg(i_params, R0900_P1_ACLC2S28, aclc);
1101 }
1102 832
1103 if ((i_params->demod_mode == STV0900_SINGLE) && (foundModcod > STV0900_8PSK_910)) { 833 enum fe_stv0900_rolloff rolloff;
1104 if (foundModcod <= STV0900_16APSK_910) { 834 enum fe_stv0900_modcode foundModcod;
1105 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
1106 stv0900_write_reg(i_params, R0900_P1_ACLC2S216A, aclc);
1107 } else if (foundModcod <= STV0900_32APSK_910) {
1108 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
1109 stv0900_write_reg(i_params, R0900_P1_ACLC2S232A, aclc);
1110 }
1111 }
1112 835
1113 } else { 836 dprintk("%s\n", __func__);
1114 aclc = stv0900_get_optim_short_carr_loop(srate, i_params->dmd1_rslts.modulation, i_params->chip_id);
1115 if (i_params->dmd1_rslts.modulation == STV0900_QPSK)
1116 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, aclc);
1117
1118 else if (i_params->dmd1_rslts.modulation == STV0900_8PSK) {
1119 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
1120 stv0900_write_reg(i_params, R0900_P1_ACLC2S28, aclc);
1121 } else if (i_params->dmd1_rslts.modulation == STV0900_16APSK) {
1122 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
1123 stv0900_write_reg(i_params, R0900_P1_ACLC2S216A, aclc);
1124 } else if (i_params->dmd1_rslts.modulation == STV0900_32APSK) {
1125 stv0900_write_reg(i_params, R0900_P1_ACLC2S2Q, 0x2a);
1126 stv0900_write_reg(i_params, R0900_P1_ACLC2S232A, aclc);
1127 }
1128 837
1129 } 838 srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
839 srate += stv0900_get_timing_offst(intp, srate, demod);
1130 840
1131 if (i_params->chip_id <= 0x11) { 841 switch (intp->result[demod].standard) {
1132 if (i_params->demod_mode != STV0900_SINGLE) 842 case STV0900_DVBS1_STANDARD:
1133 stv0900_activate_s2_modcode(i_params, demod); 843 case STV0900_DSS_STANDARD:
844 dprintk("%s: found DVB-S or DSS\n", __func__);
845 if (intp->srch_standard[demod] == STV0900_AUTO_SEARCH) {
846 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
847 stv0900_write_bits(intp, DVBS2_ENABLE, 0);
848 }
1134 849
1135 } 850 stv0900_write_bits(intp, ROLLOFF_CONTROL, intp->rolloff);
851 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
1136 852
1137 stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x67); 853 if (intp->chip_id < 0x30) {
1138 break; 854 stv0900_write_reg(intp, ERRCTRL1, 0x75);
1139 case STV0900_UNKNOWN_STANDARD:
1140 default:
1141 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
1142 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
1143 break; 855 break;
1144 } 856 }
1145 857
1146 freq1 = stv0900_read_reg(i_params, R0900_P1_CFR2); 858 if (stv0900_get_vit_fec(intp, demod) == STV0900_FEC_1_2) {
1147 freq0 = stv0900_read_reg(i_params, R0900_P1_CFR1); 859 stv0900_write_reg(intp, GAUSSR0, 0x98);
1148 rolloff = stv0900_get_bits(i_params, F0900_P1_ROLLOFF_STATUS); 860 stv0900_write_reg(intp, CCIR0, 0x18);
1149 if (i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) { 861 } else {
1150 stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x00); 862 stv0900_write_reg(intp, GAUSSR0, 0x18);
1151 stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 0); 863 stv0900_write_reg(intp, CCIR0, 0x18);
1152 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
1153 stv0900_write_reg(i_params, R0900_P1_TMGCFG2, 0x01);
1154 stv0900_set_symbol_rate(i_params, i_params->mclk, srate, demod);
1155 stv0900_set_max_symbol_rate(i_params, i_params->mclk, srate, demod);
1156 stv0900_set_min_symbol_rate(i_params, i_params->mclk, srate, demod);
1157 blindTunSw = 1;
1158 } 864 }
1159 865
1160 if (i_params->chip_id >= 0x20) { 866 stv0900_write_reg(intp, ERRCTRL1, 0x75);
1161 if ((i_params->dmd1_srch_standard == STV0900_SEARCH_DVBS1) || (i_params->dmd1_srch_standard == STV0900_SEARCH_DSS) || (i_params->dmd1_srch_standard == STV0900_AUTO_SEARCH)) { 867 break;
1162 stv0900_write_reg(i_params, R0900_P1_VAVSRVIT, 0x0a); 868 case STV0900_DVBS2_STANDARD:
1163 stv0900_write_reg(i_params, R0900_P1_VITSCALE, 0x0); 869 dprintk("%s: found DVB-S2\n", __func__);
870 stv0900_write_bits(intp, DVBS1_ENABLE, 0);
871 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
872 stv0900_write_reg(intp, ACLC, 0);
873 stv0900_write_reg(intp, BCLC, 0);
874 if (intp->result[demod].frame_len == STV0900_LONG_FRAME) {
875 foundModcod = stv0900_get_bits(intp, DEMOD_MODCOD);
876 pilots = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
877 aclc = stv0900_get_optim_carr_loop(srate,
878 foundModcod,
879 pilots,
880 intp->chip_id);
881 if (foundModcod <= STV0900_QPSK_910)
882 stv0900_write_reg(intp, ACLC2S2Q, aclc);
883 else if (foundModcod <= STV0900_8PSK_910) {
884 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
885 stv0900_write_reg(intp, ACLC2S28, aclc);
1164 } 886 }
1165 }
1166 887
1167 if (i_params->chip_id < 0x20) 888 if ((intp->demod_mode == STV0900_SINGLE) &&
1168 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x08); 889 (foundModcod > STV0900_8PSK_910)) {
1169 890 if (foundModcod <= STV0900_16APSK_910) {
1170 if (i_params->chip_id == 0x10) 891 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
1171 stv0900_write_reg(i_params, R0900_P1_CORRELEXP, 0x0A); 892 stv0900_write_reg(intp, ACLC2S216A,
1172 893 aclc);
1173 stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x38); 894 } else if (foundModcod <= STV0900_32APSK_910) {
1174 895 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
1175 if ((i_params->chip_id >= 0x20) || (blindTunSw == 1) || (i_params->dmd1_symbol_rate < 10000000)) { 896 stv0900_write_reg(intp, ACLC2S232A,
1176 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1); 897 aclc);
1177 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0); 898 }
1178 i_params->tuner1_bw = stv0900_carrier_width(srate, i_params->rolloff) + 10000000;
1179
1180 if ((i_params->chip_id >= 0x20) || (blindTunSw == 1)) {
1181 if (i_params->dmd1_srch_algo != STV0900_WARM_START)
1182 stv0900_set_bandwidth(fe, i_params->tuner1_bw);
1183 } 899 }
1184 900
1185 if ((i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) || (i_params->dmd1_symbol_rate < 10000000)) 901 } else {
1186 msleep(50); 902 modulation = intp->result[demod].modulation;
1187 else 903 aclc = stv0900_get_optim_short_carr_loop(srate,
1188 msleep(5); 904 modulation, intp->chip_id);
1189 905 if (modulation == STV0900_QPSK)
1190 stv0900_get_lock_timeout(&timed, &timef, srate, STV0900_WARM_START); 906 stv0900_write_reg(intp, ACLC2S2Q, aclc);
1191 907 else if (modulation == STV0900_8PSK) {
1192 if (stv0900_get_demod_lock(i_params, demod, timed / 2) == FALSE) { 908 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
1193 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1F); 909 stv0900_write_reg(intp, ACLC2S28, aclc);
1194 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1); 910 } else if (modulation == STV0900_16APSK) {
1195 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0); 911 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
1196 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18); 912 stv0900_write_reg(intp, ACLC2S216A, aclc);
1197 i = 0; 913 } else if (modulation == STV0900_32APSK) {
1198 while ((stv0900_get_demod_lock(i_params, demod, timed / 2) == FALSE) && (i <= 2)) { 914 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
1199 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1F); 915 stv0900_write_reg(intp, ACLC2S232A, aclc);
1200 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1);
1201 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0);
1202 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18);
1203 i++;
1204 }
1205 } 916 }
1206 917
1207 } 918 }
1208 919
1209 if (i_params->chip_id >= 0x20) 920 if (intp->chip_id <= 0x11) {
1210 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x49); 921 if (intp->demod_mode != STV0900_SINGLE)
922 stv0900_activate_s2_modcod(intp, demod);
1211 923
1212 if ((i_params->dmd1_rslts.standard == STV0900_DVBS1_STANDARD) || (i_params->dmd1_rslts.standard == STV0900_DSS_STANDARD)) 924 }
1213 stv0900_set_viterbi_tracq(i_params, demod);
1214 925
926 stv0900_write_reg(intp, ERRCTRL1, 0x67);
1215 break; 927 break;
928 case STV0900_UNKNOWN_STANDARD:
929 default:
930 dprintk("%s: found unknown standard\n", __func__);
931 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
932 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
933 break;
934 }
1216 935
1217 case STV0900_DEMOD_2: 936 freq1 = stv0900_read_reg(intp, CFR2);
1218 switch (i_params->dmd2_rslts.standard) { 937 freq0 = stv0900_read_reg(intp, CFR1);
1219 case STV0900_DVBS1_STANDARD: 938 rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
1220 939 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
1221 if (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH) { 940 stv0900_write_reg(intp, SFRSTEP, 0x00);
1222 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1); 941 stv0900_write_bits(intp, SCAN_ENABLE, 0);
1223 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0); 942 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1224 } 943 stv0900_write_reg(intp, TMGCFG2, 0xc1);
944 stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
945 blind_tun_sw = 1;
946 if (intp->result[demod].standard != STV0900_DVBS2_STANDARD)
947 stv0900_set_dvbs1_track_car_loop(intp, demod, srate);
1225 948
1226 stv0900_write_bits(i_params, F0900_P2_ROLLOFF_CONTROL, i_params->rolloff); 949 }
1227 stv0900_write_bits(i_params, F0900_P2_MANUAL_ROLLOFF, 1);
1228 stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x75);
1229 break;
1230 case STV0900_DSS_STANDARD:
1231 if (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH) {
1232 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
1233 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
1234 }
1235
1236 stv0900_write_bits(i_params, F0900_P2_ROLLOFF_CONTROL, i_params->rolloff);
1237 stv0900_write_bits(i_params, F0900_P2_MANUAL_ROLLOFF, 1);
1238 stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x75);
1239 break;
1240 case STV0900_DVBS2_STANDARD:
1241 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 0);
1242 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
1243 stv0900_write_reg(i_params, R0900_P2_ACLC, 0);
1244 stv0900_write_reg(i_params, R0900_P2_BCLC, 0);
1245 if (i_params->dmd2_rslts.frame_length == STV0900_LONG_FRAME) {
1246 foundModcod = stv0900_get_bits(i_params, F0900_P2_DEMOD_MODCOD);
1247 pilots = stv0900_get_bits(i_params, F0900_P2_DEMOD_TYPE) & 0x01;
1248 aclc = stv0900_get_optim_carr_loop(srate, foundModcod, pilots, i_params->chip_id);
1249 if (foundModcod <= STV0900_QPSK_910)
1250 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, aclc);
1251 else if (foundModcod <= STV0900_8PSK_910) {
1252 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
1253 stv0900_write_reg(i_params, R0900_P2_ACLC2S28, aclc);
1254 }
1255
1256 if ((i_params->demod_mode == STV0900_SINGLE) && (foundModcod > STV0900_8PSK_910)) {
1257 if (foundModcod <= STV0900_16APSK_910) {
1258 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
1259 stv0900_write_reg(i_params, R0900_P2_ACLC2S216A, aclc);
1260 } else if (foundModcod <= STV0900_32APSK_910) {
1261 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
1262 stv0900_write_reg(i_params, R0900_P2_ACLC2S232A, aclc);
1263 }
1264 950
1265 } 951 if (intp->chip_id >= 0x20) {
952 if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
953 (intp->srch_standard[demod] ==
954 STV0900_SEARCH_DSS) ||
955 (intp->srch_standard[demod] ==
956 STV0900_AUTO_SEARCH)) {
957 stv0900_write_reg(intp, VAVSRVIT, 0x0a);
958 stv0900_write_reg(intp, VITSCALE, 0x0);
959 }
960 }
1266 961
1267 } else { 962 if (intp->chip_id < 0x20)
1268 aclc = stv0900_get_optim_short_carr_loop(srate, 963 stv0900_write_reg(intp, CARHDR, 0x08);
1269 i_params->dmd2_rslts.modulation,
1270 i_params->chip_id);
1271
1272 if (i_params->dmd2_rslts.modulation == STV0900_QPSK)
1273 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, aclc);
1274
1275 else if (i_params->dmd2_rslts.modulation == STV0900_8PSK) {
1276 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
1277 stv0900_write_reg(i_params, R0900_P2_ACLC2S28, aclc);
1278 } else if (i_params->dmd2_rslts.modulation == STV0900_16APSK) {
1279 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
1280 stv0900_write_reg(i_params, R0900_P2_ACLC2S216A, aclc);
1281 } else if (i_params->dmd2_rslts.modulation == STV0900_32APSK) {
1282 stv0900_write_reg(i_params, R0900_P2_ACLC2S2Q, 0x2a);
1283 stv0900_write_reg(i_params, R0900_P2_ACLC2S232A, aclc);
1284 }
1285 }
1286 964
1287 stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x67); 965 if (intp->chip_id == 0x10)
966 stv0900_write_reg(intp, CORRELEXP, 0x0a);
1288 967
1289 break; 968 stv0900_write_reg(intp, AGC2REF, 0x38);
1290 case STV0900_UNKNOWN_STANDARD:
1291 default:
1292 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
1293 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
1294 break;
1295 }
1296 969
1297 freq1 = stv0900_read_reg(i_params, R0900_P2_CFR2); 970 if ((intp->chip_id >= 0x20) ||
1298 freq0 = stv0900_read_reg(i_params, R0900_P2_CFR1); 971 (blind_tun_sw == 1) ||
1299 rolloff = stv0900_get_bits(i_params, F0900_P2_ROLLOFF_STATUS); 972 (intp->symbol_rate[demod] < 10000000)) {
1300 if (i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) { 973 stv0900_write_reg(intp, CFRINIT1, freq1);
1301 stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x00); 974 stv0900_write_reg(intp, CFRINIT0, freq0);
1302 stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 0); 975 intp->bw[demod] = stv0900_carrier_width(srate,
1303 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0); 976 intp->rolloff) + 10000000;
1304 stv0900_write_reg(i_params, R0900_P2_TMGCFG2, 0x01);
1305 stv0900_set_symbol_rate(i_params, i_params->mclk, srate, demod);
1306 stv0900_set_max_symbol_rate(i_params, i_params->mclk, srate, demod);
1307 stv0900_set_min_symbol_rate(i_params, i_params->mclk, srate, demod);
1308 blindTunSw = 1;
1309 }
1310 977
1311 if (i_params->chip_id >= 0x20) { 978 if ((intp->chip_id >= 0x20) || (blind_tun_sw == 1)) {
1312 if ((i_params->dmd2_srch_stndrd == STV0900_SEARCH_DVBS1) || (i_params->dmd2_srch_stndrd == STV0900_SEARCH_DSS) || (i_params->dmd2_srch_stndrd == STV0900_AUTO_SEARCH)) { 979 if (intp->srch_algo[demod] != STV0900_WARM_START)
1313 stv0900_write_reg(i_params, R0900_P2_VAVSRVIT, 0x0a); 980 stv0900_set_bandwidth(fe, intp->bw[demod]);
1314 stv0900_write_reg(i_params, R0900_P2_VITSCALE, 0x0);
1315 }
1316 } 981 }
1317 982
1318 if (i_params->chip_id < 0x20) 983 if ((intp->srch_algo[demod] == STV0900_BLIND_SEARCH) ||
1319 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x08); 984 (intp->symbol_rate[demod] < 10000000))
1320 985 msleep(50);
1321 if (i_params->chip_id == 0x10) 986 else
1322 stv0900_write_reg(i_params, R0900_P2_CORRELEXP, 0x0a); 987 msleep(5);
1323
1324 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x38);
1325 if ((i_params->chip_id >= 0x20) || (blindTunSw == 1) || (i_params->dmd2_symbol_rate < 10000000)) {
1326 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
1327 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
1328 i_params->tuner2_bw = stv0900_carrier_width(srate, i_params->rolloff) + 10000000;
1329 988
1330 if ((i_params->chip_id >= 0x20) || (blindTunSw == 1)) { 989 stv0900_get_lock_timeout(&timed, &timef, srate,
1331 if (i_params->dmd2_srch_algo != STV0900_WARM_START) 990 STV0900_WARM_START);
1332 stv0900_set_bandwidth(fe, i_params->tuner2_bw);
1333 }
1334 991
1335 if ((i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) || (i_params->dmd2_symbol_rate < 10000000)) 992 if (stv0900_get_demod_lock(intp, demod, timed / 2) == FALSE) {
1336 msleep(50); 993 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1337 else 994 stv0900_write_reg(intp, CFRINIT1, freq1);
1338 msleep(5); 995 stv0900_write_reg(intp, CFRINIT0, freq0);
1339 996 stv0900_write_reg(intp, DMDISTATE, 0x18);
1340 stv0900_get_lock_timeout(&timed, &timef, srate, STV0900_WARM_START); 997 i = 0;
1341 if (stv0900_get_demod_lock(i_params, demod, timed / 2) == FALSE) { 998 while ((stv0900_get_demod_lock(intp,
1342 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1F); 999 demod,
1343 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1); 1000 timed / 2) == FALSE) &&
1344 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0); 1001 (i <= 2)) {
1345 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18); 1002 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1346 i = 0; 1003 stv0900_write_reg(intp, CFRINIT1, freq1);
1347 while ((stv0900_get_demod_lock(i_params, demod, timed / 2) == FALSE) && (i <= 2)) { 1004 stv0900_write_reg(intp, CFRINIT0, freq0);
1348 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1F); 1005 stv0900_write_reg(intp, DMDISTATE, 0x18);
1349 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1); 1006 i++;
1350 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
1351 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
1352 i++;
1353 }
1354 } 1007 }
1355 } 1008 }
1356 1009
1357 if (i_params->chip_id >= 0x20) 1010 }
1358 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x49);
1359 1011
1360 if ((i_params->dmd2_rslts.standard == STV0900_DVBS1_STANDARD) || (i_params->dmd2_rslts.standard == STV0900_DSS_STANDARD)) 1012 if (intp->chip_id >= 0x20)
1361 stv0900_set_viterbi_tracq(i_params, demod); 1013 stv0900_write_reg(intp, CARFREQ, 0x49);
1014
1015 if ((intp->result[demod].standard == STV0900_DVBS1_STANDARD) ||
1016 (intp->result[demod].standard == STV0900_DSS_STANDARD))
1017 stv0900_set_viterbi_tracq(intp, demod);
1362 1018
1363 break;
1364 }
1365} 1019}
1366 1020
1367static int stv0900_get_fec_lock(struct stv0900_internal *i_params, enum fe_stv0900_demod_num demod, s32 time_out) 1021static int stv0900_get_fec_lock(struct stv0900_internal *intp,
1022 enum fe_stv0900_demod_num demod, s32 time_out)
1368{ 1023{
1369 s32 timer = 0, lock = 0, header_field, pktdelin_field, lock_vit_field; 1024 s32 timer = 0, lock = 0;
1370 1025
1371 enum fe_stv0900_search_state dmd_state; 1026 enum fe_stv0900_search_state dmd_state;
1372 1027
1373 dprintk("%s\n", __func__); 1028 dprintk("%s\n", __func__);
1374 1029
1375 dmd_reg(header_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE); 1030 dmd_state = stv0900_get_bits(intp, HEADER_MODE);
1376 dmd_reg(pktdelin_field, F0900_P1_PKTDELIN_LOCK, F0900_P2_PKTDELIN_LOCK);
1377 dmd_reg(lock_vit_field, F0900_P1_LOCKEDVIT, F0900_P2_LOCKEDVIT);
1378
1379 dmd_state = stv0900_get_bits(i_params, header_field);
1380 1031
1381 while ((timer < time_out) && (lock == 0)) { 1032 while ((timer < time_out) && (lock == 0)) {
1382 switch (dmd_state) { 1033 switch (dmd_state) {
@@ -1386,10 +1037,10 @@ static int stv0900_get_fec_lock(struct stv0900_internal *i_params, enum fe_stv09
1386 lock = 0; 1037 lock = 0;
1387 break; 1038 break;
1388 case STV0900_DVBS2_FOUND: 1039 case STV0900_DVBS2_FOUND:
1389 lock = stv0900_get_bits(i_params, pktdelin_field); 1040 lock = stv0900_get_bits(intp, PKTDELIN_LOCK);
1390 break; 1041 break;
1391 case STV0900_DVBS_FOUND: 1042 case STV0900_DVBS_FOUND:
1392 lock = stv0900_get_bits(i_params, lock_vit_field); 1043 lock = stv0900_get_bits(intp, LOCKEDVIT);
1393 break; 1044 break;
1394 } 1045 }
1395 1046
@@ -1400,38 +1051,35 @@ static int stv0900_get_fec_lock(struct stv0900_internal *i_params, enum fe_stv09
1400 } 1051 }
1401 1052
1402 if (lock) 1053 if (lock)
1403 dprintk("DEMOD FEC LOCK OK\n"); 1054 dprintk("%s: DEMOD FEC LOCK OK\n", __func__);
1404 else 1055 else
1405 dprintk("DEMOD FEC LOCK FAIL\n"); 1056 dprintk("%s: DEMOD FEC LOCK FAIL\n", __func__);
1406 1057
1407 return lock; 1058 return lock;
1408} 1059}
1409 1060
1410static int stv0900_wait_for_lock(struct stv0900_internal *i_params, 1061static int stv0900_wait_for_lock(struct stv0900_internal *intp,
1411 enum fe_stv0900_demod_num demod, 1062 enum fe_stv0900_demod_num demod,
1412 s32 dmd_timeout, s32 fec_timeout) 1063 s32 dmd_timeout, s32 fec_timeout)
1413{ 1064{
1414 1065
1415 s32 timer = 0, lock = 0, str_merg_rst_fld, str_merg_lock_fld; 1066 s32 timer = 0, lock = 0;
1416 1067
1417 dprintk("%s\n", __func__); 1068 dprintk("%s\n", __func__);
1418 1069
1419 dmd_reg(str_merg_rst_fld, F0900_P1_RST_HWARE, F0900_P2_RST_HWARE); 1070 lock = stv0900_get_demod_lock(intp, demod, dmd_timeout);
1420 dmd_reg(str_merg_lock_fld, F0900_P1_TSFIFO_LINEOK, F0900_P2_TSFIFO_LINEOK);
1421
1422 lock = stv0900_get_demod_lock(i_params, demod, dmd_timeout);
1423 1071
1424 if (lock) 1072 if (lock)
1425 lock = lock && stv0900_get_fec_lock(i_params, demod, fec_timeout); 1073 lock = lock && stv0900_get_fec_lock(intp, demod, fec_timeout);
1426 1074
1427 if (lock) { 1075 if (lock) {
1428 lock = 0; 1076 lock = 0;
1429 1077
1430 dprintk("%s: Timer = %d, time_out = %d\n", __func__, timer, 1078 dprintk("%s: Timer = %d, time_out = %d\n",
1431 fec_timeout); 1079 __func__, timer, fec_timeout);
1432 1080
1433 while ((timer < fec_timeout) && (lock == 0)) { 1081 while ((timer < fec_timeout) && (lock == 0)) {
1434 lock = stv0900_get_bits(i_params, str_merg_lock_fld); 1082 lock = stv0900_get_bits(intp, TSFIFO_LINEOK);
1435 msleep(1); 1083 msleep(1);
1436 timer++; 1084 timer++;
1437 } 1085 }
@@ -1452,43 +1100,43 @@ enum fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe,
1452 enum fe_stv0900_demod_num demod) 1100 enum fe_stv0900_demod_num demod)
1453{ 1101{
1454 struct stv0900_state *state = fe->demodulator_priv; 1102 struct stv0900_state *state = fe->demodulator_priv;
1455 struct stv0900_internal *i_params = state->internal; 1103 struct stv0900_internal *intp = state->internal;
1456 enum fe_stv0900_tracking_standard fnd_standard; 1104 enum fe_stv0900_tracking_standard fnd_standard;
1457 s32 state_field,
1458 dss_dvb_field;
1459
1460 dprintk("%s\n", __func__);
1461 1105
1462 dmd_reg(state_field, F0900_P1_HEADER_MODE, F0900_P2_HEADER_MODE); 1106 int hdr_mode = stv0900_get_bits(intp, HEADER_MODE);
1463 dmd_reg(dss_dvb_field, F0900_P1_DSS_DVB, F0900_P2_DSS_DVB);
1464 1107
1465 if (stv0900_get_bits(i_params, state_field) == 2) 1108 switch (hdr_mode) {
1109 case 2:
1466 fnd_standard = STV0900_DVBS2_STANDARD; 1110 fnd_standard = STV0900_DVBS2_STANDARD;
1467 1111 break;
1468 else if (stv0900_get_bits(i_params, state_field) == 3) { 1112 case 3:
1469 if (stv0900_get_bits(i_params, dss_dvb_field) == 1) 1113 if (stv0900_get_bits(intp, DSS_DVB) == 1)
1470 fnd_standard = STV0900_DSS_STANDARD; 1114 fnd_standard = STV0900_DSS_STANDARD;
1471 else 1115 else
1472 fnd_standard = STV0900_DVBS1_STANDARD; 1116 fnd_standard = STV0900_DVBS1_STANDARD;
1473 } else 1117
1118 break;
1119 default:
1474 fnd_standard = STV0900_UNKNOWN_STANDARD; 1120 fnd_standard = STV0900_UNKNOWN_STANDARD;
1121 }
1122
1123 dprintk("%s: standard %d\n", __func__, fnd_standard);
1475 1124
1476 return fnd_standard; 1125 return fnd_standard;
1477} 1126}
1478 1127
1479static s32 stv0900_get_carr_freq(struct stv0900_internal *i_params, u32 mclk, 1128static s32 stv0900_get_carr_freq(struct stv0900_internal *intp, u32 mclk,
1480 enum fe_stv0900_demod_num demod) 1129 enum fe_stv0900_demod_num demod)
1481{ 1130{
1482 s32 cfr_field2, cfr_field1, cfr_field0, 1131 s32 derot,
1483 derot, rem1, rem2, intval1, intval2; 1132 rem1,
1484 1133 rem2,
1485 dmd_reg(cfr_field2, F0900_P1_CAR_FREQ2, F0900_P2_CAR_FREQ2); 1134 intval1,
1486 dmd_reg(cfr_field1, F0900_P1_CAR_FREQ1, F0900_P2_CAR_FREQ1); 1135 intval2;
1487 dmd_reg(cfr_field0, F0900_P1_CAR_FREQ0, F0900_P2_CAR_FREQ0);
1488 1136
1489 derot = (stv0900_get_bits(i_params, cfr_field2) << 16) + 1137 derot = (stv0900_get_bits(intp, CAR_FREQ2) << 16) +
1490 (stv0900_get_bits(i_params, cfr_field1) << 8) + 1138 (stv0900_get_bits(intp, CAR_FREQ1) << 8) +
1491 (stv0900_get_bits(i_params, cfr_field0)); 1139 (stv0900_get_bits(intp, CAR_FREQ0));
1492 1140
1493 derot = ge2comp(derot, 24); 1141 derot = ge2comp(derot, 24);
1494 intval1 = mclk >> 12; 1142 intval1 = mclk >> 12;
@@ -1506,7 +1154,7 @@ static u32 stv0900_get_tuner_freq(struct dvb_frontend *fe)
1506{ 1154{
1507 struct dvb_frontend_ops *frontend_ops = NULL; 1155 struct dvb_frontend_ops *frontend_ops = NULL;
1508 struct dvb_tuner_ops *tuner_ops = NULL; 1156 struct dvb_tuner_ops *tuner_ops = NULL;
1509 u32 frequency = 0; 1157 u32 freq = 0;
1510 1158
1511 if (&fe->ops) 1159 if (&fe->ops)
1512 frontend_ops = &fe->ops; 1160 frontend_ops = &fe->ops;
@@ -1515,304 +1163,159 @@ static u32 stv0900_get_tuner_freq(struct dvb_frontend *fe)
1515 tuner_ops = &frontend_ops->tuner_ops; 1163 tuner_ops = &frontend_ops->tuner_ops;
1516 1164
1517 if (tuner_ops->get_frequency) { 1165 if (tuner_ops->get_frequency) {
1518 if ((tuner_ops->get_frequency(fe, &frequency)) < 0) 1166 if ((tuner_ops->get_frequency(fe, &freq)) < 0)
1519 dprintk("%s: Invalid parameter\n", __func__); 1167 dprintk("%s: Invalid parameter\n", __func__);
1520 else 1168 else
1521 dprintk("%s: Frequency=%d\n", __func__, frequency); 1169 dprintk("%s: Frequency=%d\n", __func__, freq);
1522 1170
1523 } 1171 }
1524 1172
1525 return frequency; 1173 return freq;
1526} 1174}
1527 1175
1528static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *i_params, 1176static enum
1529 enum fe_stv0900_demod_num demod) 1177fe_stv0900_signal_type stv0900_get_signal_params(struct dvb_frontend *fe)
1530{
1531 s32 rate_fld, vit_curpun_fld;
1532 enum fe_stv0900_fec prate;
1533
1534 dmd_reg(vit_curpun_fld, F0900_P1_VIT_CURPUN, F0900_P2_VIT_CURPUN);
1535 rate_fld = stv0900_get_bits(i_params, vit_curpun_fld);
1536
1537 switch (rate_fld) {
1538 case 13:
1539 prate = STV0900_FEC_1_2;
1540 break;
1541 case 18:
1542 prate = STV0900_FEC_2_3;
1543 break;
1544 case 21:
1545 prate = STV0900_FEC_3_4;
1546 break;
1547 case 24:
1548 prate = STV0900_FEC_5_6;
1549 break;
1550 case 25:
1551 prate = STV0900_FEC_6_7;
1552 break;
1553 case 26:
1554 prate = STV0900_FEC_7_8;
1555 break;
1556 default:
1557 prate = STV0900_FEC_UNKNOWN;
1558 break;
1559 }
1560
1561 return prate;
1562}
1563
1564static enum fe_stv0900_signal_type stv0900_get_signal_params(struct dvb_frontend *fe)
1565{ 1178{
1566 struct stv0900_state *state = fe->demodulator_priv; 1179 struct stv0900_state *state = fe->demodulator_priv;
1567 struct stv0900_internal *i_params = state->internal; 1180 struct stv0900_internal *intp = state->internal;
1568 enum fe_stv0900_demod_num demod = state->demod; 1181 enum fe_stv0900_demod_num demod = state->demod;
1569 enum fe_stv0900_signal_type range = STV0900_OUTOFRANGE; 1182 enum fe_stv0900_signal_type range = STV0900_OUTOFRANGE;
1570 s32 offsetFreq, 1183 struct stv0900_signal_info *result = &intp->result[demod];
1571 srate_offset, 1184 s32 offsetFreq,
1572 i = 0; 1185 srate_offset;
1186 int i = 0,
1187 d = demod;
1573 1188
1574 u8 timing; 1189 u8 timing;
1575 1190
1576 msleep(5); 1191 msleep(5);
1577 switch (demod) { 1192 if (intp->srch_algo[d] == STV0900_BLIND_SEARCH) {
1578 case STV0900_DEMOD_1: 1193 timing = stv0900_read_reg(intp, TMGREG2);
1579 default: 1194 i = 0;
1580 if (i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) { 1195 stv0900_write_reg(intp, SFRSTEP, 0x5c);
1581 timing = stv0900_read_reg(i_params, R0900_P1_TMGREG2); 1196
1582 i = 0; 1197 while ((i <= 50) && (timing != 0) && (timing != 0xff)) {
1583 stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x5c); 1198 timing = stv0900_read_reg(intp, TMGREG2);
1584 1199 msleep(5);
1585 while ((i <= 50) && (timing != 0) && (timing != 0xFF)) { 1200 i += 5;
1586 timing = stv0900_read_reg(i_params, R0900_P1_TMGREG2);
1587 msleep(5);
1588 i += 5;
1589 }
1590 }
1591
1592 i_params->dmd1_rslts.standard = stv0900_get_standard(fe, demod);
1593 i_params->dmd1_rslts.frequency = stv0900_get_tuner_freq(fe);
1594 offsetFreq = stv0900_get_carr_freq(i_params, i_params->mclk, demod) / 1000;
1595 i_params->dmd1_rslts.frequency += offsetFreq;
1596 i_params->dmd1_rslts.symbol_rate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
1597 srate_offset = stv0900_get_timing_offst(i_params, i_params->dmd1_rslts.symbol_rate, demod);
1598 i_params->dmd1_rslts.symbol_rate += srate_offset;
1599 i_params->dmd1_rslts.fec = stv0900_get_vit_fec(i_params, demod);
1600 i_params->dmd1_rslts.modcode = stv0900_get_bits(i_params, F0900_P1_DEMOD_MODCOD);
1601 i_params->dmd1_rslts.pilot = stv0900_get_bits(i_params, F0900_P1_DEMOD_TYPE) & 0x01;
1602 i_params->dmd1_rslts.frame_length = ((u32)stv0900_get_bits(i_params, F0900_P1_DEMOD_TYPE)) >> 1;
1603 i_params->dmd1_rslts.rolloff = stv0900_get_bits(i_params, F0900_P1_ROLLOFF_STATUS);
1604 switch (i_params->dmd1_rslts.standard) {
1605 case STV0900_DVBS2_STANDARD:
1606 i_params->dmd1_rslts.spectrum = stv0900_get_bits(i_params, F0900_P1_SPECINV_DEMOD);
1607 if (i_params->dmd1_rslts.modcode <= STV0900_QPSK_910)
1608 i_params->dmd1_rslts.modulation = STV0900_QPSK;
1609 else if (i_params->dmd1_rslts.modcode <= STV0900_8PSK_910)
1610 i_params->dmd1_rslts.modulation = STV0900_8PSK;
1611 else if (i_params->dmd1_rslts.modcode <= STV0900_16APSK_910)
1612 i_params->dmd1_rslts.modulation = STV0900_16APSK;
1613 else if (i_params->dmd1_rslts.modcode <= STV0900_32APSK_910)
1614 i_params->dmd1_rslts.modulation = STV0900_32APSK;
1615 else
1616 i_params->dmd1_rslts.modulation = STV0900_UNKNOWN;
1617 break;
1618 case STV0900_DVBS1_STANDARD:
1619 case STV0900_DSS_STANDARD:
1620 i_params->dmd1_rslts.spectrum = stv0900_get_bits(i_params, F0900_P1_IQINV);
1621 i_params->dmd1_rslts.modulation = STV0900_QPSK;
1622 break;
1623 default:
1624 break;
1625 } 1201 }
1202 }
1626 1203
1627 if ((i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) || (i_params->dmd1_symbol_rate < 10000000)) { 1204 result->standard = stv0900_get_standard(fe, d);
1628 offsetFreq = i_params->dmd1_rslts.frequency - i_params->tuner1_freq; 1205 result->frequency = stv0900_get_tuner_freq(fe);
1629 i_params->tuner1_freq = stv0900_get_tuner_freq(fe); 1206 offsetFreq = stv0900_get_carr_freq(intp, intp->mclk, d) / 1000;
1630 if (ABS(offsetFreq) <= ((i_params->dmd1_srch_range / 2000) + 500)) 1207 result->frequency += offsetFreq;
1631 range = STV0900_RANGEOK; 1208 result->symbol_rate = stv0900_get_symbol_rate(intp, intp->mclk, d);
1632 else 1209 srate_offset = stv0900_get_timing_offst(intp, result->symbol_rate, d);
1633 if (ABS(offsetFreq) <= (stv0900_carrier_width(i_params->dmd1_rslts.symbol_rate, i_params->dmd1_rslts.rolloff) / 2000)) 1210 result->symbol_rate += srate_offset;
1634 range = STV0900_RANGEOK; 1211 result->fec = stv0900_get_vit_fec(intp, d);
1635 else 1212 result->modcode = stv0900_get_bits(intp, DEMOD_MODCOD);
1636 range = STV0900_OUTOFRANGE; 1213 result->pilot = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
1637 1214 result->frame_len = ((u32)stv0900_get_bits(intp, DEMOD_TYPE)) >> 1;
1638 } else { 1215 result->rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
1639 if (ABS(offsetFreq) <= ((i_params->dmd1_srch_range / 2000) + 500)) 1216 switch (result->standard) {
1640 range = STV0900_RANGEOK; 1217 case STV0900_DVBS2_STANDARD:
1641 else 1218 result->spectrum = stv0900_get_bits(intp, SPECINV_DEMOD);
1642 range = STV0900_OUTOFRANGE; 1219 if (result->modcode <= STV0900_QPSK_910)
1643 } 1220 result->modulation = STV0900_QPSK;
1221 else if (result->modcode <= STV0900_8PSK_910)
1222 result->modulation = STV0900_8PSK;
1223 else if (result->modcode <= STV0900_16APSK_910)
1224 result->modulation = STV0900_16APSK;
1225 else if (result->modcode <= STV0900_32APSK_910)
1226 result->modulation = STV0900_32APSK;
1227 else
1228 result->modulation = STV0900_UNKNOWN;
1644 break; 1229 break;
1645 case STV0900_DEMOD_2: 1230 case STV0900_DVBS1_STANDARD:
1646 if (i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) { 1231 case STV0900_DSS_STANDARD:
1647 timing = stv0900_read_reg(i_params, R0900_P2_TMGREG2); 1232 result->spectrum = stv0900_get_bits(intp, IQINV);
1648 i = 0; 1233 result->modulation = STV0900_QPSK;
1649 stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x5c); 1234 break;
1650 1235 default:
1651 while ((i <= 50) && (timing != 0) && (timing != 0xff)) { 1236 break;
1652 timing = stv0900_read_reg(i_params, R0900_P2_TMGREG2); 1237 }
1653 msleep(5);
1654 i += 5;
1655 }
1656 }
1657
1658 i_params->dmd2_rslts.standard = stv0900_get_standard(fe, demod);
1659 i_params->dmd2_rslts.frequency = stv0900_get_tuner_freq(fe);
1660 offsetFreq = stv0900_get_carr_freq(i_params, i_params->mclk, demod) / 1000;
1661 i_params->dmd2_rslts.frequency += offsetFreq;
1662 i_params->dmd2_rslts.symbol_rate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
1663 srate_offset = stv0900_get_timing_offst(i_params, i_params->dmd2_rslts.symbol_rate, demod);
1664 i_params->dmd2_rslts.symbol_rate += srate_offset;
1665 i_params->dmd2_rslts.fec = stv0900_get_vit_fec(i_params, demod);
1666 i_params->dmd2_rslts.modcode = stv0900_get_bits(i_params, F0900_P2_DEMOD_MODCOD);
1667 i_params->dmd2_rslts.pilot = stv0900_get_bits(i_params, F0900_P2_DEMOD_TYPE) & 0x01;
1668 i_params->dmd2_rslts.frame_length = ((u32)stv0900_get_bits(i_params, F0900_P2_DEMOD_TYPE)) >> 1;
1669 i_params->dmd2_rslts.rolloff = stv0900_get_bits(i_params, F0900_P2_ROLLOFF_STATUS);
1670 switch (i_params->dmd2_rslts.standard) {
1671 case STV0900_DVBS2_STANDARD:
1672 i_params->dmd2_rslts.spectrum = stv0900_get_bits(i_params, F0900_P2_SPECINV_DEMOD);
1673 if (i_params->dmd2_rslts.modcode <= STV0900_QPSK_910)
1674 i_params->dmd2_rslts.modulation = STV0900_QPSK;
1675 else if (i_params->dmd2_rslts.modcode <= STV0900_8PSK_910)
1676 i_params->dmd2_rslts.modulation = STV0900_8PSK;
1677 else if (i_params->dmd2_rslts.modcode <= STV0900_16APSK_910)
1678 i_params->dmd2_rslts.modulation = STV0900_16APSK;
1679 else if (i_params->dmd2_rslts.modcode <= STV0900_32APSK_910)
1680 i_params->dmd2_rslts.modulation = STV0900_32APSK;
1681 else
1682 i_params->dmd2_rslts.modulation = STV0900_UNKNOWN;
1683 break;
1684 case STV0900_DVBS1_STANDARD:
1685 case STV0900_DSS_STANDARD:
1686 i_params->dmd2_rslts.spectrum = stv0900_get_bits(i_params, F0900_P2_IQINV);
1687 i_params->dmd2_rslts.modulation = STV0900_QPSK;
1688 break;
1689 default:
1690 break;
1691 }
1692 1238
1693 if ((i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) || (i_params->dmd2_symbol_rate < 10000000)) { 1239 if ((intp->srch_algo[d] == STV0900_BLIND_SEARCH) ||
1694 offsetFreq = i_params->dmd2_rslts.frequency - i_params->tuner2_freq; 1240 (intp->symbol_rate[d] < 10000000)) {
1695 i_params->tuner2_freq = stv0900_get_tuner_freq(fe); 1241 offsetFreq = result->frequency - intp->freq[d];
1242 intp->freq[d] = stv0900_get_tuner_freq(fe);
1243 if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
1244 range = STV0900_RANGEOK;
1245 else if (ABS(offsetFreq) <=
1246 (stv0900_carrier_width(result->symbol_rate,
1247 result->rolloff) / 2000))
1248 range = STV0900_RANGEOK;
1696 1249
1697 if (ABS(offsetFreq) <= ((i_params->dmd2_srch_range / 2000) + 500)) 1250 } else if (ABS(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
1698 range = STV0900_RANGEOK; 1251 range = STV0900_RANGEOK;
1699 else
1700 if (ABS(offsetFreq) <= (stv0900_carrier_width(i_params->dmd2_rslts.symbol_rate, i_params->dmd2_rslts.rolloff) / 2000))
1701 range = STV0900_RANGEOK;
1702 else
1703 range = STV0900_OUTOFRANGE;
1704 } else {
1705 if (ABS(offsetFreq) <= ((i_params->dmd2_srch_range / 2000) + 500))
1706 range = STV0900_RANGEOK;
1707 else
1708 range = STV0900_OUTOFRANGE;
1709 }
1710 1252
1711 break; 1253 dprintk("%s: range %d\n", __func__, range);
1712 }
1713 1254
1714 return range; 1255 return range;
1715} 1256}
1716 1257
1717static enum fe_stv0900_signal_type stv0900_dvbs1_acq_workaround(struct dvb_frontend *fe) 1258static enum
1259fe_stv0900_signal_type stv0900_dvbs1_acq_workaround(struct dvb_frontend *fe)
1718{ 1260{
1719 struct stv0900_state *state = fe->demodulator_priv; 1261 struct stv0900_state *state = fe->demodulator_priv;
1720 struct stv0900_internal *i_params = state->internal; 1262 struct stv0900_internal *intp = state->internal;
1721 enum fe_stv0900_demod_num demod = state->demod; 1263 enum fe_stv0900_demod_num demod = state->demod;
1722
1723 s32 srate, demod_timeout,
1724 fec_timeout, freq1, freq0;
1725 enum fe_stv0900_signal_type signal_type = STV0900_NODATA; 1264 enum fe_stv0900_signal_type signal_type = STV0900_NODATA;
1726 1265
1727 switch (demod) { 1266 s32 srate,
1728 case STV0900_DEMOD_1: 1267 demod_timeout,
1729 default: 1268 fec_timeout,
1730 i_params->dmd1_rslts.locked = FALSE; 1269 freq1,
1731 if (stv0900_get_bits(i_params, F0900_P1_HEADER_MODE) == STV0900_DVBS_FOUND) { 1270 freq0;
1732 srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod); 1271
1733 srate += stv0900_get_timing_offst(i_params, srate, demod); 1272 intp->result[demod].locked = FALSE;
1734 if (i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) 1273
1735 stv0900_set_symbol_rate(i_params, i_params->mclk, srate, demod); 1274 if (stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) {
1736 1275 srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1737 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, srate, STV0900_WARM_START); 1276 srate += stv0900_get_timing_offst(intp, srate, demod);
1738 freq1 = stv0900_read_reg(i_params, R0900_P1_CFR2); 1277 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH)
1739 freq0 = stv0900_read_reg(i_params, R0900_P1_CFR1); 1278 stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
1740 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0); 1279
1741 stv0900_write_bits(i_params, F0900_P1_SPECINV_CONTROL, STV0900_IQ_FORCE_SWAPPED); 1280 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
1742 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1C); 1281 srate, STV0900_WARM_START);
1743 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1); 1282 freq1 = stv0900_read_reg(intp, CFR2);
1744 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0); 1283 freq0 = stv0900_read_reg(intp, CFR1);
1745 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18); 1284 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1746 if (stv0900_wait_for_lock(i_params, demod, demod_timeout, fec_timeout) == TRUE) { 1285 stv0900_write_bits(intp, SPECINV_CONTROL,
1747 i_params->dmd1_rslts.locked = TRUE; 1286 STV0900_IQ_FORCE_SWAPPED);
1748 signal_type = stv0900_get_signal_params(fe); 1287 stv0900_write_reg(intp, DMDISTATE, 0x1c);
1749 stv0900_track_optimization(fe); 1288 stv0900_write_reg(intp, CFRINIT1, freq1);
1750 } else { 1289 stv0900_write_reg(intp, CFRINIT0, freq0);
1751 stv0900_write_bits(i_params, F0900_P1_SPECINV_CONTROL, STV0900_IQ_FORCE_NORMAL); 1290 stv0900_write_reg(intp, DMDISTATE, 0x18);
1752 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1c); 1291 if (stv0900_wait_for_lock(intp, demod,
1753 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, freq1); 1292 demod_timeout, fec_timeout) == TRUE) {
1754 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, freq0); 1293 intp->result[demod].locked = TRUE;
1755 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x18); 1294 signal_type = stv0900_get_signal_params(fe);
1756 if (stv0900_wait_for_lock(i_params, demod, demod_timeout, fec_timeout) == TRUE) { 1295 stv0900_track_optimization(fe);
1757 i_params->dmd1_rslts.locked = TRUE; 1296 } else {
1758 signal_type = stv0900_get_signal_params(fe); 1297 stv0900_write_bits(intp, SPECINV_CONTROL,
1759 stv0900_track_optimization(fe); 1298 STV0900_IQ_FORCE_NORMAL);
1760 } 1299 stv0900_write_reg(intp, DMDISTATE, 0x1c);
1761 1300 stv0900_write_reg(intp, CFRINIT1, freq1);
1762 } 1301 stv0900_write_reg(intp, CFRINIT0, freq0);
1763 1302 stv0900_write_reg(intp, DMDISTATE, 0x18);
1764 } else 1303 if (stv0900_wait_for_lock(intp, demod,
1765 i_params->dmd1_rslts.locked = FALSE; 1304 demod_timeout, fec_timeout) == TRUE) {
1766 1305 intp->result[demod].locked = TRUE;
1767 break;
1768 case STV0900_DEMOD_2:
1769 i_params->dmd2_rslts.locked = FALSE;
1770 if (stv0900_get_bits(i_params, F0900_P2_HEADER_MODE) == STV0900_DVBS_FOUND) {
1771 srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
1772 srate += stv0900_get_timing_offst(i_params, srate, demod);
1773
1774 if (i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH)
1775 stv0900_set_symbol_rate(i_params, i_params->mclk, srate, demod);
1776
1777 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, srate, STV0900_WARM_START);
1778 freq1 = stv0900_read_reg(i_params, R0900_P2_CFR2);
1779 freq0 = stv0900_read_reg(i_params, R0900_P2_CFR1);
1780 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0);
1781 stv0900_write_bits(i_params, F0900_P2_SPECINV_CONTROL, STV0900_IQ_FORCE_SWAPPED);
1782 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1C);
1783 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
1784 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
1785 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
1786
1787 if (stv0900_wait_for_lock(i_params, demod, demod_timeout, fec_timeout) == TRUE) {
1788 i_params->dmd2_rslts.locked = TRUE;
1789 signal_type = stv0900_get_signal_params(fe); 1306 signal_type = stv0900_get_signal_params(fe);
1790 stv0900_track_optimization(fe); 1307 stv0900_track_optimization(fe);
1791 } else {
1792 stv0900_write_bits(i_params, F0900_P2_SPECINV_CONTROL, STV0900_IQ_FORCE_NORMAL);
1793 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1c);
1794 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, freq1);
1795 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, freq0);
1796 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x18);
1797
1798 if (stv0900_wait_for_lock(i_params, demod, demod_timeout, fec_timeout) == TRUE) {
1799 i_params->dmd2_rslts.locked = TRUE;
1800 signal_type = stv0900_get_signal_params(fe);
1801 stv0900_track_optimization(fe);
1802 }
1803
1804 } 1308 }
1805 1309
1806 } else 1310 }
1807 i_params->dmd1_rslts.locked = FALSE;
1808 1311
1809 break; 1312 } else
1810 } 1313 intp->result[demod].locked = FALSE;
1811 1314
1812 return signal_type; 1315 return signal_type;
1813} 1316}
1814 1317
1815static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *i_params, 1318static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *intp,
1816 enum fe_stv0900_demod_num demod) 1319 enum fe_stv0900_demod_num demod)
1817{ 1320{
1818 u32 minagc2level = 0xffff, 1321 u32 minagc2level = 0xffff,
@@ -1823,103 +1326,52 @@ static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *i_params,
1823 1326
1824 dprintk("%s\n", __func__); 1327 dprintk("%s\n", __func__);
1825 1328
1826 switch (demod) { 1329 stv0900_write_reg(intp, AGC2REF, 0x38);
1827 case STV0900_DEMOD_1: 1330 stv0900_write_bits(intp, SCAN_ENABLE, 0);
1828 default: 1331 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1829 stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x38);
1830 stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 1);
1831 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 1);
1832
1833 stv0900_write_reg(i_params, R0900_P1_SFRUP1, 0x83);
1834 stv0900_write_reg(i_params, R0900_P1_SFRUP0, 0xc0);
1835 1332
1836 stv0900_write_reg(i_params, R0900_P1_SFRLOW1, 0x82); 1333 stv0900_write_bits(intp, AUTO_GUP, 1);
1837 stv0900_write_reg(i_params, R0900_P1_SFRLOW0, 0xa0); 1334 stv0900_write_bits(intp, AUTO_GLOW, 1);
1838 stv0900_write_reg(i_params, R0900_P1_DMDT0M, 0x0);
1839 1335
1840 stv0900_set_symbol_rate(i_params, i_params->mclk, 1000000, demod); 1336 stv0900_write_reg(intp, DMDT0M, 0x0);
1841 nb_steps = -1 + (i_params->dmd1_srch_range / 1000000);
1842 nb_steps /= 2;
1843 nb_steps = (2 * nb_steps) + 1;
1844 1337
1845 if (nb_steps < 0) 1338 stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
1846 nb_steps = 1; 1339 nb_steps = -1 + (intp->srch_range[demod] / 1000000);
1340 nb_steps /= 2;
1341 nb_steps = (2 * nb_steps) + 1;
1847 1342
1848 direction = 1; 1343 if (nb_steps < 0)
1344 nb_steps = 1;
1849 1345
1850 freq_step = (1000000 << 8) / (i_params->mclk >> 8); 1346 direction = 1;
1851 1347
1852 init_freq = 0; 1348 freq_step = (1000000 << 8) / (intp->mclk >> 8);
1853
1854 for (i = 0; i < nb_steps; i++) {
1855 if (direction > 0)
1856 init_freq = init_freq + (freq_step * i);
1857 else
1858 init_freq = init_freq - (freq_step * i);
1859
1860 direction *= -1;
1861 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5C);
1862 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, (init_freq >> 8) & 0xff);
1863 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, init_freq & 0xff);
1864 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x58);
1865 msleep(10);
1866 agc2level = 0;
1867 1349
1868 for (j = 0; j < 10; j++) 1350 init_freq = 0;
1869 agc2level += (stv0900_read_reg(i_params, R0900_P1_AGC2I1) << 8)
1870 | stv0900_read_reg(i_params, R0900_P1_AGC2I0);
1871 1351
1872 agc2level /= 10; 1352 for (i = 0; i < nb_steps; i++) {
1873 1353 if (direction > 0)
1874 if (agc2level < minagc2level) 1354 init_freq = init_freq + (freq_step * i);
1875 minagc2level = agc2level; 1355 else
1876 } 1356 init_freq = init_freq - (freq_step * i);
1877 break;
1878 case STV0900_DEMOD_2:
1879 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x38);
1880 stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 1);
1881 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 1);
1882 stv0900_write_reg(i_params, R0900_P2_SFRUP1, 0x83);
1883 stv0900_write_reg(i_params, R0900_P2_SFRUP0, 0xc0);
1884 stv0900_write_reg(i_params, R0900_P2_SFRLOW1, 0x82);
1885 stv0900_write_reg(i_params, R0900_P2_SFRLOW0, 0xa0);
1886 stv0900_write_reg(i_params, R0900_P2_DMDT0M, 0x0);
1887 stv0900_set_symbol_rate(i_params, i_params->mclk, 1000000, demod);
1888 nb_steps = -1 + (i_params->dmd2_srch_range / 1000000);
1889 nb_steps /= 2;
1890 nb_steps = (2 * nb_steps) + 1;
1891
1892 if (nb_steps < 0)
1893 nb_steps = 1;
1894
1895 direction = 1;
1896 freq_step = (1000000 << 8) / (i_params->mclk >> 8);
1897 init_freq = 0;
1898 for (i = 0; i < nb_steps; i++) {
1899 if (direction > 0)
1900 init_freq = init_freq + (freq_step * i);
1901 else
1902 init_freq = init_freq - (freq_step * i);
1903 1357
1904 direction *= -1; 1358 direction *= -1;
1359 stv0900_write_reg(intp, DMDISTATE, 0x5C);
1360 stv0900_write_reg(intp, CFRINIT1, (init_freq >> 8) & 0xff);
1361 stv0900_write_reg(intp, CFRINIT0, init_freq & 0xff);
1362 stv0900_write_reg(intp, DMDISTATE, 0x58);
1363 msleep(10);
1364 agc2level = 0;
1905 1365
1906 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5C); 1366 for (j = 0; j < 10; j++)
1907 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, (init_freq >> 8) & 0xff); 1367 agc2level += (stv0900_read_reg(intp, AGC2I1) << 8)
1908 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, init_freq & 0xff); 1368 | stv0900_read_reg(intp, AGC2I0);
1909 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x58);
1910 1369
1911 msleep(10); 1370 agc2level /= 10;
1912 agc2level = 0;
1913 for (j = 0; j < 10; j++)
1914 agc2level += (stv0900_read_reg(i_params, R0900_P2_AGC2I1) << 8)
1915 | stv0900_read_reg(i_params, R0900_P2_AGC2I0);
1916 1371
1917 agc2level /= 10; 1372 if (agc2level < minagc2level)
1373 minagc2level = agc2level;
1918 1374
1919 if (agc2level < minagc2level)
1920 minagc2level = agc2level;
1921 }
1922 break;
1923 } 1375 }
1924 1376
1925 return (u16)minagc2level; 1377 return (u16)minagc2level;
@@ -1928,336 +1380,192 @@ static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *i_params,
1928static u32 stv0900_search_srate_coarse(struct dvb_frontend *fe) 1380static u32 stv0900_search_srate_coarse(struct dvb_frontend *fe)
1929{ 1381{
1930 struct stv0900_state *state = fe->demodulator_priv; 1382 struct stv0900_state *state = fe->demodulator_priv;
1931 struct stv0900_internal *i_params = state->internal; 1383 struct stv0900_internal *intp = state->internal;
1932 enum fe_stv0900_demod_num demod = state->demod; 1384 enum fe_stv0900_demod_num demod = state->demod;
1933 int timingLock = FALSE; 1385 int timing_lck = FALSE;
1934 s32 i, timingcpt = 0, 1386 s32 i, timingcpt = 0,
1935 direction = 1, 1387 direction = 1,
1936 nb_steps, 1388 nb_steps,
1937 current_step = 0, 1389 current_step = 0,
1938 tuner_freq; 1390 tuner_freq;
1391 u32 agc2_th,
1392 coarse_srate = 0,
1393 agc2_integr = 0,
1394 currier_step = 1200;
1939 1395
1940 u32 coarse_srate = 0, agc2_integr = 0, currier_step = 1200; 1396 if (intp->chip_id >= 0x30)
1941 1397 agc2_th = 0x2e00;
1942 switch (demod) { 1398 else
1943 case STV0900_DEMOD_1: 1399 agc2_th = 0x1f00;
1944 default: 1400
1945 stv0900_write_bits(i_params, F0900_P1_I2C_DEMOD_MODE, 0x1F); 1401 stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
1946 stv0900_write_reg(i_params, R0900_P1_TMGCFG, 0x12); 1402 stv0900_write_reg(intp, TMGCFG, 0x12);
1947 stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0xf0); 1403 stv0900_write_reg(intp, TMGTHRISE, 0xf0);
1948 stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0xe0); 1404 stv0900_write_reg(intp, TMGTHFALL, 0xe0);
1949 stv0900_write_bits(i_params, F0900_P1_SCAN_ENABLE, 1); 1405 stv0900_write_bits(intp, SCAN_ENABLE, 1);
1950 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 1); 1406 stv0900_write_bits(intp, CFR_AUTOSCAN, 1);
1951 stv0900_write_reg(i_params, R0900_P1_SFRUP1, 0x83); 1407 stv0900_write_reg(intp, SFRUP1, 0x83);
1952 stv0900_write_reg(i_params, R0900_P1_SFRUP0, 0xc0); 1408 stv0900_write_reg(intp, SFRUP0, 0xc0);
1953 stv0900_write_reg(i_params, R0900_P1_SFRLOW1, 0x82); 1409 stv0900_write_reg(intp, SFRLOW1, 0x82);
1954 stv0900_write_reg(i_params, R0900_P1_SFRLOW0, 0xa0); 1410 stv0900_write_reg(intp, SFRLOW0, 0xa0);
1955 stv0900_write_reg(i_params, R0900_P1_DMDT0M, 0x0); 1411 stv0900_write_reg(intp, DMDT0M, 0x0);
1956 stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x50); 1412 stv0900_write_reg(intp, AGC2REF, 0x50);
1957 1413
1958 if (i_params->chip_id >= 0x20) { 1414 if (intp->chip_id >= 0x30) {
1959 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x6a); 1415 stv0900_write_reg(intp, CARFREQ, 0x99);
1960 stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x95); 1416 stv0900_write_reg(intp, SFRSTEP, 0x98);
1961 } else { 1417 } else if (intp->chip_id >= 0x20) {
1962 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xed); 1418 stv0900_write_reg(intp, CARFREQ, 0x6a);
1963 stv0900_write_reg(i_params, R0900_P1_SFRSTEP, 0x73); 1419 stv0900_write_reg(intp, SFRSTEP, 0x95);
1964 } 1420 } else {
1421 stv0900_write_reg(intp, CARFREQ, 0xed);
1422 stv0900_write_reg(intp, SFRSTEP, 0x73);
1423 }
1965 1424
1966 if (i_params->dmd1_symbol_rate <= 2000000) 1425 if (intp->symbol_rate[demod] <= 2000000)
1967 currier_step = 1000; 1426 currier_step = 1000;
1968 else if (i_params->dmd1_symbol_rate <= 5000000) 1427 else if (intp->symbol_rate[demod] <= 5000000)
1969 currier_step = 2000; 1428 currier_step = 2000;
1970 else if (i_params->dmd1_symbol_rate <= 12000000) 1429 else if (intp->symbol_rate[demod] <= 12000000)
1971 currier_step = 3000; 1430 currier_step = 3000;
1972 else 1431 else
1973 currier_step = 5000; 1432 currier_step = 5000;
1974 1433
1975 nb_steps = -1 + ((i_params->dmd1_srch_range / 1000) / currier_step); 1434 nb_steps = -1 + ((intp->srch_range[demod] / 1000) / currier_step);
1976 nb_steps /= 2; 1435 nb_steps /= 2;
1977 nb_steps = (2 * nb_steps) + 1; 1436 nb_steps = (2 * nb_steps) + 1;
1978
1979 if (nb_steps < 0)
1980 nb_steps = 1;
1981
1982 else if (nb_steps > 10) {
1983 nb_steps = 11;
1984 currier_step = (i_params->dmd1_srch_range / 1000) / 10;
1985 }
1986
1987 current_step = 0;
1988
1989 direction = 1;
1990 tuner_freq = i_params->tuner1_freq;
1991 1437
1992 while ((timingLock == FALSE) && (current_step < nb_steps)) { 1438 if (nb_steps < 0)
1993 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5F); 1439 nb_steps = 1;
1994 stv0900_write_bits(i_params, F0900_P1_I2C_DEMOD_MODE, 0x0); 1440 else if (nb_steps > 10) {
1995 1441 nb_steps = 11;
1996 msleep(50); 1442 currier_step = (intp->srch_range[demod] / 1000) / 10;
1997 1443 }
1998 for (i = 0; i < 10; i++) {
1999 if (stv0900_get_bits(i_params, F0900_P1_TMGLOCK_QUALITY) >= 2)
2000 timingcpt++;
2001
2002 agc2_integr += (stv0900_read_reg(i_params, R0900_P1_AGC2I1) << 8) | stv0900_read_reg(i_params, R0900_P1_AGC2I0);
2003 1444
2004 } 1445 current_step = 0;
1446 direction = 1;
2005 1447
2006 agc2_integr /= 10; 1448 tuner_freq = intp->freq[demod];
2007 coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
2008 current_step++;
2009 direction *= -1;
2010 1449
2011 dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started. tuner freq=%d agc2=0x%x srate_coarse=%d tmg_cpt=%d\n", tuner_freq, agc2_integr, coarse_srate, timingcpt); 1450 while ((timing_lck == FALSE) && (current_step < nb_steps)) {
1451 stv0900_write_reg(intp, DMDISTATE, 0x5f);
1452 stv0900_write_bits(intp, DEMOD_MODE, 0);
2012 1453
2013 if ((timingcpt >= 5) && (agc2_integr < 0x1F00) && (coarse_srate < 55000000) && (coarse_srate > 850000)) { 1454 msleep(50);
2014 timingLock = TRUE;
2015 }
2016 1455
2017 else if (current_step < nb_steps) { 1456 for (i = 0; i < 10; i++) {
2018 if (direction > 0) 1457 if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
2019 tuner_freq += (current_step * currier_step); 1458 timingcpt++;
2020 else
2021 tuner_freq -= (current_step * currier_step);
2022
2023 stv0900_set_tuner(fe, tuner_freq, i_params->tuner1_bw);
2024 }
2025 }
2026
2027 if (timingLock == FALSE)
2028 coarse_srate = 0;
2029 else
2030 coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
2031 break;
2032 case STV0900_DEMOD_2:
2033 stv0900_write_bits(i_params, F0900_P2_I2C_DEMOD_MODE, 0x1F);
2034 stv0900_write_reg(i_params, R0900_P2_TMGCFG, 0x12);
2035 stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0xf0);
2036 stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0xe0);
2037 stv0900_write_bits(i_params, F0900_P2_SCAN_ENABLE, 1);
2038 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 1);
2039 stv0900_write_reg(i_params, R0900_P2_SFRUP1, 0x83);
2040 stv0900_write_reg(i_params, R0900_P2_SFRUP0, 0xc0);
2041 stv0900_write_reg(i_params, R0900_P2_SFRLOW1, 0x82);
2042 stv0900_write_reg(i_params, R0900_P2_SFRLOW0, 0xa0);
2043 stv0900_write_reg(i_params, R0900_P2_DMDT0M, 0x0);
2044 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x50);
2045
2046 if (i_params->chip_id >= 0x20) {
2047 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x6a);
2048 stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x95);
2049 } else {
2050 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xed);
2051 stv0900_write_reg(i_params, R0900_P2_SFRSTEP, 0x73);
2052 }
2053
2054 if (i_params->dmd2_symbol_rate <= 2000000)
2055 currier_step = 1000;
2056 else if (i_params->dmd2_symbol_rate <= 5000000)
2057 currier_step = 2000;
2058 else if (i_params->dmd2_symbol_rate <= 12000000)
2059 currier_step = 3000;
2060 else
2061 currier_step = 5000;
2062
2063
2064 nb_steps = -1 + ((i_params->dmd2_srch_range / 1000) / currier_step);
2065 nb_steps /= 2;
2066 nb_steps = (2 * nb_steps) + 1;
2067 1459
2068 if (nb_steps < 0) 1460 agc2_integr += (stv0900_read_reg(intp, AGC2I1) << 8) |
2069 nb_steps = 1; 1461 stv0900_read_reg(intp, AGC2I0);
2070 else if (nb_steps > 10) {
2071 nb_steps = 11;
2072 currier_step = (i_params->dmd2_srch_range / 1000) / 10;
2073 } 1462 }
2074 1463
2075 current_step = 0; 1464 agc2_integr /= 10;
2076 direction = 1; 1465 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
2077 tuner_freq = i_params->tuner2_freq; 1466 current_step++;
2078 1467 direction *= -1;
2079 while ((timingLock == FALSE) && (current_step < nb_steps)) { 1468
2080 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5F); 1469 dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started."
2081 stv0900_write_bits(i_params, F0900_P2_I2C_DEMOD_MODE, 0x0); 1470 " tuner freq=%d agc2=0x%x srate_coarse=%d tmg_cpt=%d\n",
2082 1471 tuner_freq, agc2_integr, coarse_srate, timingcpt);
2083 msleep(50); 1472
2084 timingcpt = 0; 1473 if ((timingcpt >= 5) &&
2085 1474 (agc2_integr < agc2_th) &&
2086 for (i = 0; i < 20; i++) { 1475 (coarse_srate < 55000000) &&
2087 if (stv0900_get_bits(i_params, F0900_P2_TMGLOCK_QUALITY) >= 2) 1476 (coarse_srate > 850000))
2088 timingcpt++; 1477 timing_lck = TRUE;
2089 agc2_integr += (stv0900_read_reg(i_params, R0900_P2_AGC2I1) << 8) 1478 else if (current_step < nb_steps) {
2090 | stv0900_read_reg(i_params, R0900_P2_AGC2I0); 1479 if (direction > 0)
2091 } 1480 tuner_freq += (current_step * currier_step);
2092 1481 else
2093 agc2_integr /= 20; 1482 tuner_freq -= (current_step * currier_step);
2094 coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
2095 if ((timingcpt >= 10) && (agc2_integr < 0x1F00) && (coarse_srate < 55000000) && (coarse_srate > 850000))
2096 timingLock = TRUE;
2097 else {
2098 current_step++;
2099 direction *= -1;
2100
2101 if (direction > 0)
2102 tuner_freq += (current_step * currier_step);
2103 else
2104 tuner_freq -= (current_step * currier_step);
2105 1483
2106 stv0900_set_tuner(fe, tuner_freq, i_params->tuner2_bw); 1484 stv0900_set_tuner(fe, tuner_freq, intp->bw[demod]);
2107 }
2108 } 1485 }
2109
2110 if (timingLock == FALSE)
2111 coarse_srate = 0;
2112 else
2113 coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod);
2114 break;
2115 } 1486 }
2116 1487
1488 if (timing_lck == FALSE)
1489 coarse_srate = 0;
1490 else
1491 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1492
2117 return coarse_srate; 1493 return coarse_srate;
2118} 1494}
2119 1495
2120static u32 stv0900_search_srate_fine(struct dvb_frontend *fe) 1496static u32 stv0900_search_srate_fine(struct dvb_frontend *fe)
2121{ 1497{
2122 struct stv0900_state *state = fe->demodulator_priv; 1498 struct stv0900_state *state = fe->demodulator_priv;
2123 struct stv0900_internal *i_params = state->internal; 1499 struct stv0900_internal *intp = state->internal;
2124 enum fe_stv0900_demod_num demod = state->demod; 1500 enum fe_stv0900_demod_num demod = state->demod;
2125 u32 coarse_srate, 1501 u32 coarse_srate,
2126 coarse_freq, 1502 coarse_freq,
2127 symb; 1503 symb,
1504 symbmax,
1505 symbmin,
1506 symbcomp;
1507
1508 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1509
1510 if (coarse_srate > 3000000) {
1511 symbmax = 13 * (coarse_srate / 10);
1512 symbmax = (symbmax / 1000) * 65536;
1513 symbmax /= (intp->mclk / 1000);
1514
1515 symbmin = 10 * (coarse_srate / 13);
1516 symbmin = (symbmin / 1000)*65536;
1517 symbmin /= (intp->mclk / 1000);
1518
1519 symb = (coarse_srate / 1000) * 65536;
1520 symb /= (intp->mclk / 1000);
1521 } else {
1522 symbmax = 13 * (coarse_srate / 10);
1523 symbmax = (symbmax / 100) * 65536;
1524 symbmax /= (intp->mclk / 100);
2128 1525
2129 coarse_srate = stv0900_get_symbol_rate(i_params, i_params->mclk, demod); 1526 symbmin = 10 * (coarse_srate / 14);
1527 symbmin = (symbmin / 100) * 65536;
1528 symbmin /= (intp->mclk / 100);
2130 1529
2131 switch (demod) { 1530 symb = (coarse_srate / 100) * 65536;
2132 case STV0900_DEMOD_1: 1531 symb /= (intp->mclk / 100);
2133 default: 1532 }
2134 coarse_freq = (stv0900_read_reg(i_params, R0900_P1_CFR2) << 8)
2135 | stv0900_read_reg(i_params, R0900_P1_CFR1);
2136 symb = 13 * (coarse_srate / 10);
2137
2138 if (symb < i_params->dmd1_symbol_rate)
2139 coarse_srate = 0;
2140 else {
2141 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x1F);
2142 stv0900_write_reg(i_params, R0900_P1_TMGCFG2, 0x01);
2143 stv0900_write_reg(i_params, R0900_P1_TMGTHRISE, 0x20);
2144 stv0900_write_reg(i_params, R0900_P1_TMGTHFALL, 0x00);
2145 stv0900_write_reg(i_params, R0900_P1_TMGCFG, 0xd2);
2146 stv0900_write_bits(i_params, F0900_P1_CFR_AUTOSCAN, 0);
2147
2148 if (i_params->chip_id >= 0x20)
2149 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0x49);
2150 else
2151 stv0900_write_reg(i_params, R0900_P1_CARFREQ, 0xed);
2152
2153 if (coarse_srate > 3000000) {
2154 symb = 13 * (coarse_srate / 10);
2155 symb = (symb / 1000) * 65536;
2156 symb /= (i_params->mclk / 1000);
2157 stv0900_write_reg(i_params, R0900_P1_SFRUP1, (symb >> 8) & 0x7F);
2158 stv0900_write_reg(i_params, R0900_P1_SFRUP0, (symb & 0xFF));
2159
2160 symb = 10 * (coarse_srate / 13);
2161 symb = (symb / 1000) * 65536;
2162 symb /= (i_params->mclk / 1000);
2163
2164 stv0900_write_reg(i_params, R0900_P1_SFRLOW1, (symb >> 8) & 0x7F);
2165 stv0900_write_reg(i_params, R0900_P1_SFRLOW0, (symb & 0xFF));
2166
2167 symb = (coarse_srate / 1000) * 65536;
2168 symb /= (i_params->mclk / 1000);
2169 stv0900_write_reg(i_params, R0900_P1_SFRINIT1, (symb >> 8) & 0xFF);
2170 stv0900_write_reg(i_params, R0900_P1_SFRINIT0, (symb & 0xFF));
2171 } else {
2172 symb = 13 * (coarse_srate / 10);
2173 symb = (symb / 100) * 65536;
2174 symb /= (i_params->mclk / 100);
2175 stv0900_write_reg(i_params, R0900_P1_SFRUP1, (symb >> 8) & 0x7F);
2176 stv0900_write_reg(i_params, R0900_P1_SFRUP0, (symb & 0xFF));
2177
2178 symb = 10 * (coarse_srate / 14);
2179 symb = (symb / 100) * 65536;
2180 symb /= (i_params->mclk / 100);
2181 stv0900_write_reg(i_params, R0900_P1_SFRLOW1, (symb >> 8) & 0x7F);
2182 stv0900_write_reg(i_params, R0900_P1_SFRLOW0, (symb & 0xFF));
2183
2184 symb = (coarse_srate / 100) * 65536;
2185 symb /= (i_params->mclk / 100);
2186 stv0900_write_reg(i_params, R0900_P1_SFRINIT1, (symb >> 8) & 0xFF);
2187 stv0900_write_reg(i_params, R0900_P1_SFRINIT0, (symb & 0xFF));
2188 }
2189 1533
2190 stv0900_write_reg(i_params, R0900_P1_DMDT0M, 0x20); 1534 symbcomp = 13 * (coarse_srate / 10);
2191 stv0900_write_reg(i_params, R0900_P1_CFRINIT1, (coarse_freq >> 8) & 0xff); 1535 coarse_freq = (stv0900_read_reg(intp, CFR2) << 8)
2192 stv0900_write_reg(i_params, R0900_P1_CFRINIT0, coarse_freq & 0xff); 1536 | stv0900_read_reg(intp, CFR1);
2193 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x15); 1537
2194 } 1538 if (symbcomp < intp->symbol_rate[demod])
2195 break; 1539 coarse_srate = 0;
2196 case STV0900_DEMOD_2: 1540 else {
2197 coarse_freq = (stv0900_read_reg(i_params, R0900_P2_CFR2) << 8) 1541 stv0900_write_reg(intp, DMDISTATE, 0x1f);
2198 | stv0900_read_reg(i_params, R0900_P2_CFR1); 1542 stv0900_write_reg(intp, TMGCFG2, 0xc1);
2199 1543 stv0900_write_reg(intp, TMGTHRISE, 0x20);
2200 symb = 13 * (coarse_srate / 10); 1544 stv0900_write_reg(intp, TMGTHFALL, 0x00);
2201 1545 stv0900_write_reg(intp, TMGCFG, 0xd2);
2202 if (symb < i_params->dmd2_symbol_rate) 1546 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
2203 coarse_srate = 0; 1547 stv0900_write_reg(intp, AGC2REF, 0x38);
2204 else { 1548
2205 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x1F); 1549 if (intp->chip_id >= 0x30)
2206 stv0900_write_reg(i_params, R0900_P2_TMGCFG2, 0x01); 1550 stv0900_write_reg(intp, CARFREQ, 0x79);
2207 stv0900_write_reg(i_params, R0900_P2_TMGTHRISE, 0x20); 1551 else if (intp->chip_id >= 0x20)
2208 stv0900_write_reg(i_params, R0900_P2_TMGTHFALL, 0x00); 1552 stv0900_write_reg(intp, CARFREQ, 0x49);
2209 stv0900_write_reg(i_params, R0900_P2_TMGCFG, 0xd2); 1553 else
2210 stv0900_write_bits(i_params, F0900_P2_CFR_AUTOSCAN, 0); 1554 stv0900_write_reg(intp, CARFREQ, 0xed);
2211
2212 if (i_params->chip_id >= 0x20)
2213 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0x49);
2214 else
2215 stv0900_write_reg(i_params, R0900_P2_CARFREQ, 0xed);
2216
2217 if (coarse_srate > 3000000) {
2218 symb = 13 * (coarse_srate / 10);
2219 symb = (symb / 1000) * 65536;
2220 symb /= (i_params->mclk / 1000);
2221 stv0900_write_reg(i_params, R0900_P2_SFRUP1, (symb >> 8) & 0x7F);
2222 stv0900_write_reg(i_params, R0900_P2_SFRUP0, (symb & 0xFF));
2223
2224 symb = 10 * (coarse_srate / 13);
2225 symb = (symb / 1000) * 65536;
2226 symb /= (i_params->mclk / 1000);
2227
2228 stv0900_write_reg(i_params, R0900_P2_SFRLOW1, (symb >> 8) & 0x7F);
2229 stv0900_write_reg(i_params, R0900_P2_SFRLOW0, (symb & 0xFF));
2230
2231 symb = (coarse_srate / 1000) * 65536;
2232 symb /= (i_params->mclk / 1000);
2233 stv0900_write_reg(i_params, R0900_P2_SFRINIT1, (symb >> 8) & 0xFF);
2234 stv0900_write_reg(i_params, R0900_P2_SFRINIT0, (symb & 0xFF));
2235 } else {
2236 symb = 13 * (coarse_srate / 10);
2237 symb = (symb / 100) * 65536;
2238 symb /= (i_params->mclk / 100);
2239 stv0900_write_reg(i_params, R0900_P2_SFRUP1, (symb >> 8) & 0x7F);
2240 stv0900_write_reg(i_params, R0900_P2_SFRUP0, (symb & 0xFF));
2241
2242 symb = 10 * (coarse_srate / 14);
2243 symb = (symb / 100) * 65536;
2244 symb /= (i_params->mclk / 100);
2245 stv0900_write_reg(i_params, R0900_P2_SFRLOW1, (symb >> 8) & 0x7F);
2246 stv0900_write_reg(i_params, R0900_P2_SFRLOW0, (symb & 0xFF));
2247
2248 symb = (coarse_srate / 100) * 65536;
2249 symb /= (i_params->mclk / 100);
2250 stv0900_write_reg(i_params, R0900_P2_SFRINIT1, (symb >> 8) & 0xFF);
2251 stv0900_write_reg(i_params, R0900_P2_SFRINIT0, (symb & 0xFF));
2252 }
2253 1555
2254 stv0900_write_reg(i_params, R0900_P2_DMDT0M, 0x20); 1556 stv0900_write_reg(intp, SFRUP1, (symbmax >> 8) & 0x7f);
2255 stv0900_write_reg(i_params, R0900_P2_CFRINIT1, (coarse_freq >> 8) & 0xff); 1557 stv0900_write_reg(intp, SFRUP0, (symbmax & 0xff));
2256 stv0900_write_reg(i_params, R0900_P2_CFRINIT0, coarse_freq & 0xff);
2257 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x15);
2258 }
2259 1558
2260 break; 1559 stv0900_write_reg(intp, SFRLOW1, (symbmin >> 8) & 0x7f);
1560 stv0900_write_reg(intp, SFRLOW0, (symbmin & 0xff));
1561
1562 stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0xff);
1563 stv0900_write_reg(intp, SFRINIT0, (symb & 0xff));
1564
1565 stv0900_write_reg(intp, DMDT0M, 0x20);
1566 stv0900_write_reg(intp, CFRINIT1, (coarse_freq >> 8) & 0xff);
1567 stv0900_write_reg(intp, CFRINIT0, coarse_freq & 0xff);
1568 stv0900_write_reg(intp, DMDISTATE, 0x15);
2261 } 1569 }
2262 1570
2263 return coarse_srate; 1571 return coarse_srate;
@@ -2266,163 +1574,135 @@ static u32 stv0900_search_srate_fine(struct dvb_frontend *fe)
2266static int stv0900_blind_search_algo(struct dvb_frontend *fe) 1574static int stv0900_blind_search_algo(struct dvb_frontend *fe)
2267{ 1575{
2268 struct stv0900_state *state = fe->demodulator_priv; 1576 struct stv0900_state *state = fe->demodulator_priv;
2269 struct stv0900_internal *i_params = state->internal; 1577 struct stv0900_internal *intp = state->internal;
2270 enum fe_stv0900_demod_num demod = state->demod; 1578 enum fe_stv0900_demod_num demod = state->demod;
2271 u8 k_ref_tmg, k_ref_tmg_max, k_ref_tmg_min; 1579 u8 k_ref_tmg,
2272 u32 coarse_srate; 1580 k_ref_tmg_max,
2273 int lock = FALSE, coarse_fail = FALSE; 1581 k_ref_tmg_min;
2274 s32 demod_timeout = 500, fec_timeout = 50, kref_tmg_reg, fail_cpt, i, agc2_overflow; 1582 u32 coarse_srate,
2275 u16 agc2_integr; 1583 agc2_th;
2276 u8 dstatus2; 1584 int lock = FALSE,
1585 coarse_fail = FALSE;
1586 s32 demod_timeout = 500,
1587 fec_timeout = 50,
1588 fail_cpt,
1589 i,
1590 agc2_overflow;
1591 u16 agc2_int;
1592 u8 dstatus2;
2277 1593
2278 dprintk("%s\n", __func__); 1594 dprintk("%s\n", __func__);
2279 1595
2280 if (i_params->chip_id < 0x20) { 1596 if (intp->chip_id < 0x20) {
2281 k_ref_tmg_max = 233; 1597 k_ref_tmg_max = 233;
2282 k_ref_tmg_min = 143; 1598 k_ref_tmg_min = 143;
2283 } else { 1599 } else {
2284 k_ref_tmg_max = 120; 1600 k_ref_tmg_max = 110;
2285 k_ref_tmg_min = 30; 1601 k_ref_tmg_min = 10;
2286 } 1602 }
2287 1603
2288 agc2_integr = stv0900_blind_check_agc2_min_level(i_params, demod); 1604 if (intp->chip_id <= 0x20)
2289 1605 agc2_th = STV0900_BLIND_SEARCH_AGC2_TH;
2290 if (agc2_integr > STV0900_BLIND_SEARCH_AGC2_TH) { 1606 else
2291 lock = FALSE; 1607 agc2_th = STV0900_BLIND_SEARCH_AGC2_TH_CUT30;
2292
2293 } else {
2294 switch (demod) {
2295 case STV0900_DEMOD_1:
2296 default:
2297 if (i_params->chip_id == 0x10)
2298 stv0900_write_reg(i_params, R0900_P1_CORRELEXP, 0xAA);
2299
2300 if (i_params->chip_id < 0x20)
2301 stv0900_write_reg(i_params, R0900_P1_CARHDR, 0x55);
2302
2303 stv0900_write_reg(i_params, R0900_P1_CARCFG, 0xC4);
2304 stv0900_write_reg(i_params, R0900_P1_RTCS2, 0x44);
2305
2306 if (i_params->chip_id >= 0x20) {
2307 stv0900_write_reg(i_params, R0900_P1_EQUALCFG, 0x41);
2308 stv0900_write_reg(i_params, R0900_P1_FFECFG, 0x41);
2309 stv0900_write_reg(i_params, R0900_P1_VITSCALE, 0x82);
2310 stv0900_write_reg(i_params, R0900_P1_VAVSRVIT, 0x0);
2311 }
2312
2313 kref_tmg_reg = R0900_P1_KREFTMG;
2314 break;
2315 case STV0900_DEMOD_2:
2316 if (i_params->chip_id == 0x10)
2317 stv0900_write_reg(i_params, R0900_P2_CORRELEXP, 0xAA);
2318
2319 if (i_params->chip_id < 0x20)
2320 stv0900_write_reg(i_params, R0900_P2_CARHDR, 0x55);
2321 1608
2322 stv0900_write_reg(i_params, R0900_P2_CARCFG, 0xC4); 1609 agc2_int = stv0900_blind_check_agc2_min_level(intp, demod);
2323 stv0900_write_reg(i_params, R0900_P2_RTCS2, 0x44);
2324 1610
2325 if (i_params->chip_id >= 0x20) { 1611 if (agc2_int > STV0900_BLIND_SEARCH_AGC2_TH)
2326 stv0900_write_reg(i_params, R0900_P2_EQUALCFG, 0x41); 1612 return FALSE;
2327 stv0900_write_reg(i_params, R0900_P2_FFECFG, 0x41);
2328 stv0900_write_reg(i_params, R0900_P2_VITSCALE, 0x82);
2329 stv0900_write_reg(i_params, R0900_P2_VAVSRVIT, 0x0);
2330 }
2331 1613
2332 kref_tmg_reg = R0900_P2_KREFTMG; 1614 if (intp->chip_id == 0x10)
2333 break; 1615 stv0900_write_reg(intp, CORRELEXP, 0xaa);
2334 }
2335 1616
2336 k_ref_tmg = k_ref_tmg_max; 1617 if (intp->chip_id < 0x20)
1618 stv0900_write_reg(intp, CARHDR, 0x55);
1619 else
1620 stv0900_write_reg(intp, CARHDR, 0x20);
2337 1621
2338 do { 1622 if (intp->chip_id <= 0x20)
2339 stv0900_write_reg(i_params, kref_tmg_reg, k_ref_tmg); 1623 stv0900_write_reg(intp, CARCFG, 0xc4);
2340 if (stv0900_search_srate_coarse(fe) != 0) { 1624 else
2341 coarse_srate = stv0900_search_srate_fine(fe); 1625 stv0900_write_reg(intp, CARCFG, 0x6);
2342 1626
2343 if (coarse_srate != 0) { 1627 stv0900_write_reg(intp, RTCS2, 0x44);
2344 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, coarse_srate, STV0900_BLIND_SEARCH);
2345 lock = stv0900_get_demod_lock(i_params, demod, demod_timeout);
2346 } else
2347 lock = FALSE;
2348 } else {
2349 fail_cpt = 0;
2350 agc2_overflow = 0;
2351 1628
2352 switch (demod) { 1629 if (intp->chip_id >= 0x20) {
2353 case STV0900_DEMOD_1: 1630 stv0900_write_reg(intp, EQUALCFG, 0x41);
2354 default: 1631 stv0900_write_reg(intp, FFECFG, 0x41);
2355 for (i = 0; i < 10; i++) { 1632 stv0900_write_reg(intp, VITSCALE, 0x82);
2356 agc2_integr = (stv0900_read_reg(i_params, R0900_P1_AGC2I1) << 8) 1633 stv0900_write_reg(intp, VAVSRVIT, 0x0);
2357 | stv0900_read_reg(i_params, R0900_P1_AGC2I0); 1634 }
2358 1635
2359 if (agc2_integr >= 0xff00) 1636 k_ref_tmg = k_ref_tmg_max;
2360 agc2_overflow++;
2361 1637
2362 dstatus2 = stv0900_read_reg(i_params, R0900_P1_DSTATUS2); 1638 do {
1639 stv0900_write_reg(intp, KREFTMG, k_ref_tmg);
1640 if (stv0900_search_srate_coarse(fe) != 0) {
1641 coarse_srate = stv0900_search_srate_fine(fe);
1642
1643 if (coarse_srate != 0) {
1644 stv0900_get_lock_timeout(&demod_timeout,
1645 &fec_timeout,
1646 coarse_srate,
1647 STV0900_BLIND_SEARCH);
1648 lock = stv0900_get_demod_lock(intp,
1649 demod,
1650 demod_timeout);
1651 } else
1652 lock = FALSE;
1653 } else {
1654 fail_cpt = 0;
1655 agc2_overflow = 0;
2363 1656
2364 if (((dstatus2 & 0x1) == 0x1) && ((dstatus2 >> 7) == 1)) 1657 for (i = 0; i < 10; i++) {
2365 fail_cpt++; 1658 agc2_int = (stv0900_read_reg(intp, AGC2I1) << 8)
2366 } 1659 | stv0900_read_reg(intp, AGC2I0);
2367 break;
2368 case STV0900_DEMOD_2:
2369 for (i = 0; i < 10; i++) {
2370 agc2_integr = (stv0900_read_reg(i_params, R0900_P2_AGC2I1) << 8)
2371 | stv0900_read_reg(i_params, R0900_P2_AGC2I0);
2372 1660
2373 if (agc2_integr >= 0xff00) 1661 if (agc2_int >= 0xff00)
2374 agc2_overflow++; 1662 agc2_overflow++;
2375 1663
2376 dstatus2 = stv0900_read_reg(i_params, R0900_P2_DSTATUS2); 1664 dstatus2 = stv0900_read_reg(intp, DSTATUS2);
2377 1665
2378 if (((dstatus2 & 0x1) == 0x1) && ((dstatus2 >> 7) == 1)) 1666 if (((dstatus2 & 0x1) == 0x1) &&
2379 fail_cpt++; 1667 ((dstatus2 >> 7) == 1))
2380 } 1668 fail_cpt++;
2381 break; 1669 }
2382 }
2383 1670
2384 if ((fail_cpt > 7) || (agc2_overflow > 7)) 1671 if ((fail_cpt > 7) || (agc2_overflow > 7))
2385 coarse_fail = TRUE; 1672 coarse_fail = TRUE;
2386 1673
2387 lock = FALSE; 1674 lock = FALSE;
2388 } 1675 }
2389 k_ref_tmg -= 30; 1676 k_ref_tmg -= 30;
2390 } while ((k_ref_tmg >= k_ref_tmg_min) && (lock == FALSE) && (coarse_fail == FALSE)); 1677 } while ((k_ref_tmg >= k_ref_tmg_min) &&
2391 } 1678 (lock == FALSE) &&
1679 (coarse_fail == FALSE));
2392 1680
2393 return lock; 1681 return lock;
2394} 1682}
2395 1683
2396static void stv0900_set_viterbi_acq(struct stv0900_internal *i_params, 1684static void stv0900_set_viterbi_acq(struct stv0900_internal *intp,
2397 enum fe_stv0900_demod_num demod) 1685 enum fe_stv0900_demod_num demod)
2398{ 1686{
2399 s32 vth_reg; 1687 s32 vth_reg = VTH12;
2400 1688
2401 dprintk("%s\n", __func__); 1689 dprintk("%s\n", __func__);
2402 1690
2403 dmd_reg(vth_reg, R0900_P1_VTH12, R0900_P2_VTH12); 1691 stv0900_write_reg(intp, vth_reg++, 0x96);
2404 1692 stv0900_write_reg(intp, vth_reg++, 0x64);
2405 stv0900_write_reg(i_params, vth_reg++, 0x96); 1693 stv0900_write_reg(intp, vth_reg++, 0x36);
2406 stv0900_write_reg(i_params, vth_reg++, 0x64); 1694 stv0900_write_reg(intp, vth_reg++, 0x23);
2407 stv0900_write_reg(i_params, vth_reg++, 0x36); 1695 stv0900_write_reg(intp, vth_reg++, 0x1e);
2408 stv0900_write_reg(i_params, vth_reg++, 0x23); 1696 stv0900_write_reg(intp, vth_reg++, 0x19);
2409 stv0900_write_reg(i_params, vth_reg++, 0x1E);
2410 stv0900_write_reg(i_params, vth_reg++, 0x19);
2411} 1697}
2412 1698
2413static void stv0900_set_search_standard(struct stv0900_internal *i_params, 1699static void stv0900_set_search_standard(struct stv0900_internal *intp,
2414 enum fe_stv0900_demod_num demod) 1700 enum fe_stv0900_demod_num demod)
2415{ 1701{
2416 1702
2417 int sstndrd;
2418
2419 dprintk("%s\n", __func__); 1703 dprintk("%s\n", __func__);
2420 1704
2421 sstndrd = i_params->dmd1_srch_standard; 1705 switch (intp->srch_standard[demod]) {
2422 if (demod == 1)
2423 sstndrd = i_params->dmd2_srch_stndrd;
2424
2425 switch (sstndrd) {
2426 case STV0900_SEARCH_DVBS1: 1706 case STV0900_SEARCH_DVBS1:
2427 dprintk("Search Standard = DVBS1\n"); 1707 dprintk("Search Standard = DVBS1\n");
2428 break; 1708 break;
@@ -2437,129 +1717,74 @@ static void stv0900_set_search_standard(struct stv0900_internal *i_params,
2437 break; 1717 break;
2438 } 1718 }
2439 1719
2440 switch (demod) { 1720 switch (intp->srch_standard[demod]) {
2441 case STV0900_DEMOD_1: 1721 case STV0900_SEARCH_DVBS1:
2442 default: 1722 case STV0900_SEARCH_DSS:
2443 switch (i_params->dmd1_srch_standard) { 1723 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
2444 case STV0900_SEARCH_DVBS1: 1724 stv0900_write_bits(intp, DVBS2_ENABLE, 0);
2445 case STV0900_SEARCH_DSS: 1725 stv0900_write_bits(intp, STOP_CLKVIT, 0);
2446 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1); 1726 stv0900_set_dvbs1_track_car_loop(intp,
2447 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0); 1727 demod,
2448 1728 intp->symbol_rate[demod]);
2449 stv0900_write_bits(i_params, F0900_STOP_CLKVIT1, 0); 1729 stv0900_write_reg(intp, CAR2CFG, 0x22);
2450 stv0900_write_reg(i_params, R0900_P1_ACLC, 0x1a); 1730
2451 stv0900_write_reg(i_params, R0900_P1_BCLC, 0x09); 1731 stv0900_set_viterbi_acq(intp, demod);
2452 stv0900_write_reg(i_params, R0900_P1_CAR2CFG, 0x22); 1732 stv0900_set_viterbi_standard(intp,
2453 1733 intp->srch_standard[demod],
2454 stv0900_set_viterbi_acq(i_params, demod); 1734 intp->fec[demod], demod);
2455 stv0900_set_viterbi_standard(i_params,
2456 i_params->dmd1_srch_standard,
2457 i_params->dmd1_fec, demod);
2458
2459 break;
2460 case STV0900_SEARCH_DVBS2:
2461 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 0);
2462 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
2463 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
2464 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
2465 stv0900_write_bits(i_params, F0900_STOP_CLKVIT1, 1);
2466 stv0900_write_reg(i_params, R0900_P1_ACLC, 0x1a);
2467 stv0900_write_reg(i_params, R0900_P1_BCLC, 0x09);
2468 stv0900_write_reg(i_params, R0900_P1_CAR2CFG, 0x26);
2469 if (i_params->demod_mode != STV0900_SINGLE) {
2470 if (i_params->chip_id <= 0x11)
2471 stv0900_stop_all_s2_modcod(i_params, demod);
2472 else
2473 stv0900_activate_s2_modcode(i_params, demod);
2474
2475 } else
2476 stv0900_activate_s2_modcode_single(i_params, demod);
2477
2478 stv0900_set_viterbi_tracq(i_params, demod);
2479
2480 break;
2481 case STV0900_AUTO_SEARCH:
2482 default:
2483 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 0);
2484 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 0);
2485 stv0900_write_bits(i_params, F0900_P1_DVBS1_ENABLE, 1);
2486 stv0900_write_bits(i_params, F0900_P1_DVBS2_ENABLE, 1);
2487 stv0900_write_bits(i_params, F0900_STOP_CLKVIT1, 0);
2488 stv0900_write_reg(i_params, R0900_P1_ACLC, 0x1a);
2489 stv0900_write_reg(i_params, R0900_P1_BCLC, 0x09);
2490 stv0900_write_reg(i_params, R0900_P1_CAR2CFG, 0x26);
2491 if (i_params->demod_mode != STV0900_SINGLE) {
2492 if (i_params->chip_id <= 0x11)
2493 stv0900_stop_all_s2_modcod(i_params, demod);
2494 else
2495 stv0900_activate_s2_modcode(i_params, demod);
2496 1735
2497 } else 1736 break;
2498 stv0900_activate_s2_modcode_single(i_params, demod); 1737 case STV0900_SEARCH_DVBS2:
1738 stv0900_write_bits(intp, DVBS1_ENABLE, 0);
1739 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
1740 stv0900_write_bits(intp, STOP_CLKVIT, 1);
1741 stv0900_write_reg(intp, ACLC, 0x1a);
1742 stv0900_write_reg(intp, BCLC, 0x09);
1743 if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
1744 stv0900_write_reg(intp, CAR2CFG, 0x26);
1745 else
1746 stv0900_write_reg(intp, CAR2CFG, 0x66);
2499 1747
2500 if (i_params->dmd1_symbol_rate >= 2000000) 1748 if (intp->demod_mode != STV0900_SINGLE) {
2501 stv0900_set_viterbi_acq(i_params, demod); 1749 if (intp->chip_id <= 0x11)
1750 stv0900_stop_all_s2_modcod(intp, demod);
2502 else 1751 else
2503 stv0900_set_viterbi_tracq(i_params, demod); 1752 stv0900_activate_s2_modcod(intp, demod);
2504 1753
2505 stv0900_set_viterbi_standard(i_params, i_params->dmd1_srch_standard, i_params->dmd1_fec, demod); 1754 } else
1755 stv0900_activate_s2_modcod_single(intp, demod);
2506 1756
2507 break; 1757 stv0900_set_viterbi_tracq(intp, demod);
2508 }
2509 break;
2510 case STV0900_DEMOD_2:
2511 switch (i_params->dmd2_srch_stndrd) {
2512 case STV0900_SEARCH_DVBS1:
2513 case STV0900_SEARCH_DSS:
2514 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
2515 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
2516 stv0900_write_bits(i_params, F0900_STOP_CLKVIT2, 0);
2517 stv0900_write_reg(i_params, R0900_P2_ACLC, 0x1a);
2518 stv0900_write_reg(i_params, R0900_P2_BCLC, 0x09);
2519 stv0900_write_reg(i_params, R0900_P2_CAR2CFG, 0x22);
2520 stv0900_set_viterbi_acq(i_params, demod);
2521 stv0900_set_viterbi_standard(i_params, i_params->dmd2_srch_stndrd, i_params->dmd2_fec, demod);
2522 break;
2523 case STV0900_SEARCH_DVBS2:
2524 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 0);
2525 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0);
2526 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1);
2527 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1);
2528 stv0900_write_bits(i_params, F0900_STOP_CLKVIT2, 1);
2529 stv0900_write_reg(i_params, R0900_P2_ACLC, 0x1a);
2530 stv0900_write_reg(i_params, R0900_P2_BCLC, 0x09);
2531 stv0900_write_reg(i_params, R0900_P2_CAR2CFG, 0x26);
2532 if (i_params->demod_mode != STV0900_SINGLE)
2533 stv0900_activate_s2_modcode(i_params, demod);
2534 else
2535 stv0900_activate_s2_modcode_single(i_params, demod);
2536 1758
2537 stv0900_set_viterbi_tracq(i_params, demod); 1759 break;
2538 break; 1760 case STV0900_AUTO_SEARCH:
2539 case STV0900_AUTO_SEARCH: 1761 default:
2540 default: 1762 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
2541 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 0); 1763 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
2542 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 0); 1764 stv0900_write_bits(intp, STOP_CLKVIT, 0);
2543 stv0900_write_bits(i_params, F0900_P2_DVBS1_ENABLE, 1); 1765 stv0900_write_reg(intp, ACLC, 0x1a);
2544 stv0900_write_bits(i_params, F0900_P2_DVBS2_ENABLE, 1); 1766 stv0900_write_reg(intp, BCLC, 0x09);
2545 stv0900_write_bits(i_params, F0900_STOP_CLKVIT2, 0); 1767 stv0900_set_dvbs1_track_car_loop(intp,
2546 stv0900_write_reg(i_params, R0900_P2_ACLC, 0x1a); 1768 demod,
2547 stv0900_write_reg(i_params, R0900_P2_BCLC, 0x09); 1769 intp->symbol_rate[demod]);
2548 stv0900_write_reg(i_params, R0900_P2_CAR2CFG, 0x26); 1770 if (intp->chip_id <= 0x20) /*cut 1.x and 2.0*/
2549 if (i_params->demod_mode != STV0900_SINGLE) 1771 stv0900_write_reg(intp, CAR2CFG, 0x26);
2550 stv0900_activate_s2_modcode(i_params, demod); 1772 else
2551 else 1773 stv0900_write_reg(intp, CAR2CFG, 0x66);
2552 stv0900_activate_s2_modcode_single(i_params, demod);
2553 1774
2554 if (i_params->dmd2_symbol_rate >= 2000000) 1775 if (intp->demod_mode != STV0900_SINGLE) {
2555 stv0900_set_viterbi_acq(i_params, demod); 1776 if (intp->chip_id <= 0x11)
1777 stv0900_stop_all_s2_modcod(intp, demod);
2556 else 1778 else
2557 stv0900_set_viterbi_tracq(i_params, demod); 1779 stv0900_activate_s2_modcod(intp, demod);
2558 1780
2559 stv0900_set_viterbi_standard(i_params, i_params->dmd2_srch_stndrd, i_params->dmd2_fec, demod); 1781 } else
1782 stv0900_activate_s2_modcod_single(intp, demod);
2560 1783
2561 break; 1784 stv0900_set_viterbi_tracq(intp, demod);
2562 } 1785 stv0900_set_viterbi_standard(intp,
1786 intp->srch_standard[demod],
1787 intp->fec[demod], demod);
2563 1788
2564 break; 1789 break;
2565 } 1790 }
@@ -2568,10 +1793,11 @@ static void stv0900_set_search_standard(struct stv0900_internal *i_params,
2568enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe) 1793enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
2569{ 1794{
2570 struct stv0900_state *state = fe->demodulator_priv; 1795 struct stv0900_state *state = fe->demodulator_priv;
2571 struct stv0900_internal *i_params = state->internal; 1796 struct stv0900_internal *intp = state->internal;
2572 enum fe_stv0900_demod_num demod = state->demod; 1797 enum fe_stv0900_demod_num demod = state->demod;
2573 1798
2574 s32 demod_timeout = 500, fec_timeout = 50, stream_merger_field; 1799 s32 demod_timeout = 500, fec_timeout = 50;
1800 s32 aq_power, agc1_power, i;
2575 1801
2576 int lock = FALSE, low_sr = FALSE; 1802 int lock = FALSE, low_sr = FALSE;
2577 1803
@@ -2581,155 +1807,115 @@ enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
2581 1807
2582 dprintk("%s\n", __func__); 1808 dprintk("%s\n", __func__);
2583 1809
2584 switch (demod) { 1810 algo = intp->srch_algo[demod];
2585 case STV0900_DEMOD_1: 1811 stv0900_write_bits(intp, RST_HWARE, 1);
2586 default: 1812 stv0900_write_reg(intp, DMDISTATE, 0x5c);
2587 algo = i_params->dmd1_srch_algo; 1813 if (intp->chip_id >= 0x20) {
2588 1814 if (intp->symbol_rate[demod] > 5000000)
2589 stv0900_write_bits(i_params, F0900_P1_RST_HWARE, 1); 1815 stv0900_write_reg(intp, CORRELABS, 0x9e);
2590 stream_merger_field = F0900_P1_RST_HWARE;
2591
2592 stv0900_write_reg(i_params, R0900_P1_DMDISTATE, 0x5C);
2593
2594 if (i_params->chip_id >= 0x20)
2595 stv0900_write_reg(i_params, R0900_P1_CORRELABS, 0x9e);
2596 else 1816 else
2597 stv0900_write_reg(i_params, R0900_P1_CORRELABS, 0x88); 1817 stv0900_write_reg(intp, CORRELABS, 0x82);
2598 1818 } else
2599 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, i_params->dmd1_symbol_rate, i_params->dmd1_srch_algo); 1819 stv0900_write_reg(intp, CORRELABS, 0x88);
2600
2601 if (i_params->dmd1_srch_algo == STV0900_BLIND_SEARCH) {
2602 i_params->tuner1_bw = 2 * 36000000;
2603
2604 stv0900_write_reg(i_params, R0900_P1_TMGCFG2, 0x00);
2605 stv0900_write_reg(i_params, R0900_P1_CORRELMANT, 0x70);
2606
2607 stv0900_set_symbol_rate(i_params, i_params->mclk, 1000000, demod);
2608 } else {
2609 stv0900_write_reg(i_params, R0900_P1_DMDT0M, 0x20);
2610 stv0900_write_reg(i_params, R0900_P1_TMGCFG, 0xd2);
2611
2612 if (i_params->dmd1_symbol_rate < 2000000)
2613 stv0900_write_reg(i_params, R0900_P1_CORRELMANT, 0x63);
2614 else
2615 stv0900_write_reg(i_params, R0900_P1_CORRELMANT, 0x70);
2616
2617 stv0900_write_reg(i_params, R0900_P1_AGC2REF, 0x38);
2618 if (i_params->chip_id >= 0x20) {
2619 stv0900_write_reg(i_params, R0900_P1_KREFTMG, 0x5a);
2620
2621 if (i_params->dmd1_srch_algo == STV0900_COLD_START)
2622 i_params->tuner1_bw = (15 * (stv0900_carrier_width(i_params->dmd1_symbol_rate, i_params->rolloff) + 10000000)) / 10;
2623 else if (i_params->dmd1_srch_algo == STV0900_WARM_START)
2624 i_params->tuner1_bw = stv0900_carrier_width(i_params->dmd1_symbol_rate, i_params->rolloff) + 10000000;
2625 } else {
2626 stv0900_write_reg(i_params, R0900_P1_KREFTMG, 0xc1);
2627 i_params->tuner1_bw = (15 * (stv0900_carrier_width(i_params->dmd1_symbol_rate, i_params->rolloff) + 10000000)) / 10;
2628 }
2629
2630 stv0900_write_reg(i_params, R0900_P1_TMGCFG2, 0x01);
2631
2632 stv0900_set_symbol_rate(i_params, i_params->mclk, i_params->dmd1_symbol_rate, demod);
2633 stv0900_set_max_symbol_rate(i_params, i_params->mclk, i_params->dmd1_symbol_rate, demod);
2634 stv0900_set_min_symbol_rate(i_params, i_params->mclk, i_params->dmd1_symbol_rate, demod);
2635 if (i_params->dmd1_symbol_rate >= 10000000)
2636 low_sr = FALSE;
2637 else
2638 low_sr = TRUE;
2639
2640 }
2641
2642 stv0900_set_tuner(fe, i_params->tuner1_freq, i_params->tuner1_bw);
2643
2644 stv0900_write_bits(i_params, F0900_P1_SPECINV_CONTROL, i_params->dmd1_srch_iq_inv);
2645 stv0900_write_bits(i_params, F0900_P1_MANUAL_ROLLOFF, 1);
2646
2647 stv0900_set_search_standard(i_params, demod);
2648 1820
2649 if (i_params->dmd1_srch_algo != STV0900_BLIND_SEARCH) 1821 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
2650 stv0900_start_search(i_params, demod); 1822 intp->symbol_rate[demod],
2651 break; 1823 intp->srch_algo[demod]);
2652 case STV0900_DEMOD_2:
2653 algo = i_params->dmd2_srch_algo;
2654 1824
2655 stv0900_write_bits(i_params, F0900_P2_RST_HWARE, 1); 1825 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
1826 intp->bw[demod] = 2 * 36000000;
2656 1827
2657 stream_merger_field = F0900_P2_RST_HWARE; 1828 stv0900_write_reg(intp, TMGCFG2, 0xc0);
1829 stv0900_write_reg(intp, CORRELMANT, 0x70);
2658 1830
2659 stv0900_write_reg(i_params, R0900_P2_DMDISTATE, 0x5C); 1831 stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
1832 } else {
1833 stv0900_write_reg(intp, DMDT0M, 0x20);
1834 stv0900_write_reg(intp, TMGCFG, 0xd2);
2660 1835
2661 if (i_params->chip_id >= 0x20) 1836 if (intp->symbol_rate[demod] < 2000000)
2662 stv0900_write_reg(i_params, R0900_P2_CORRELABS, 0x9e); 1837 stv0900_write_reg(intp, CORRELMANT, 0x63);
2663 else 1838 else
2664 stv0900_write_reg(i_params, R0900_P2_CORRELABS, 0x88); 1839 stv0900_write_reg(intp, CORRELMANT, 0x70);
2665 1840
2666 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout, i_params->dmd2_symbol_rate, i_params->dmd2_srch_algo); 1841 stv0900_write_reg(intp, AGC2REF, 0x38);
2667 1842
2668 if (i_params->dmd2_srch_algo == STV0900_BLIND_SEARCH) { 1843 intp->bw[demod] =
2669 i_params->tuner2_bw = 2 * 36000000; 1844 stv0900_carrier_width(intp->symbol_rate[demod],
1845 intp->rolloff);
1846 if (intp->chip_id >= 0x20) {
1847 stv0900_write_reg(intp, KREFTMG, 0x5a);
2670 1848
2671 stv0900_write_reg(i_params, R0900_P2_TMGCFG2, 0x00); 1849 if (intp->srch_algo[demod] == STV0900_COLD_START) {
2672 stv0900_write_reg(i_params, R0900_P2_CORRELMANT, 0x70); 1850 intp->bw[demod] += 10000000;
1851 intp->bw[demod] *= 15;
1852 intp->bw[demod] /= 10;
1853 } else if (intp->srch_algo[demod] == STV0900_WARM_START)
1854 intp->bw[demod] += 10000000;
2673 1855
2674 stv0900_set_symbol_rate(i_params, i_params->mclk, 1000000, demod);
2675 } else { 1856 } else {
2676 stv0900_write_reg(i_params, R0900_P2_DMDT0M, 0x20); 1857 stv0900_write_reg(intp, KREFTMG, 0xc1);
2677 stv0900_write_reg(i_params, R0900_P2_TMGCFG, 0xd2); 1858 intp->bw[demod] += 10000000;
1859 intp->bw[demod] *= 15;
1860 intp->bw[demod] /= 10;
1861 }
2678 1862
2679 if (i_params->dmd2_symbol_rate < 2000000) 1863 stv0900_write_reg(intp, TMGCFG2, 0xc1);
2680 stv0900_write_reg(i_params, R0900_P2_CORRELMANT, 0x63);
2681 else
2682 stv0900_write_reg(i_params, R0900_P2_CORRELMANT, 0x70);
2683 1864
2684 if (i_params->dmd2_symbol_rate >= 10000000) 1865 stv0900_set_symbol_rate(intp, intp->mclk,
2685 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x38); 1866 intp->symbol_rate[demod], demod);
2686 else 1867 stv0900_set_max_symbol_rate(intp, intp->mclk,
2687 stv0900_write_reg(i_params, R0900_P2_AGC2REF, 0x60); 1868 intp->symbol_rate[demod], demod);
1869 stv0900_set_min_symbol_rate(intp, intp->mclk,
1870 intp->symbol_rate[demod], demod);
1871 if (intp->symbol_rate[demod] >= 10000000)
1872 low_sr = FALSE;
1873 else
1874 low_sr = TRUE;
2688 1875
2689 if (i_params->chip_id >= 0x20) { 1876 }
2690 stv0900_write_reg(i_params, R0900_P2_KREFTMG, 0x5a);
2691 1877
2692 if (i_params->dmd2_srch_algo == STV0900_COLD_START) 1878 stv0900_set_tuner(fe, intp->freq[demod], intp->bw[demod]);
2693 i_params->tuner2_bw = (15 * (stv0900_carrier_width(i_params->dmd2_symbol_rate,
2694 i_params->rolloff) + 10000000)) / 10;
2695 else if (i_params->dmd2_srch_algo == STV0900_WARM_START)
2696 i_params->tuner2_bw = stv0900_carrier_width(i_params->dmd2_symbol_rate,
2697 i_params->rolloff) + 10000000;
2698 } else {
2699 stv0900_write_reg(i_params, R0900_P2_KREFTMG, 0xc1);
2700 i_params->tuner2_bw = (15 * (stv0900_carrier_width(i_params->dmd2_symbol_rate,
2701 i_params->rolloff) + 10000000)) / 10;
2702 }
2703 1879
2704 stv0900_write_reg(i_params, R0900_P2_TMGCFG2, 0x01); 1880 agc1_power = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
1881 stv0900_get_bits(intp, AGCIQ_VALUE0));
2705 1882
2706 stv0900_set_symbol_rate(i_params, i_params->mclk, i_params->dmd2_symbol_rate, demod); 1883 aq_power = 0;
2707 stv0900_set_max_symbol_rate(i_params, i_params->mclk, i_params->dmd2_symbol_rate, demod);
2708 stv0900_set_min_symbol_rate(i_params, i_params->mclk, i_params->dmd2_symbol_rate, demod);
2709 if (i_params->dmd2_symbol_rate >= 10000000)
2710 low_sr = FALSE;
2711 else
2712 low_sr = TRUE;
2713 1884
2714 } 1885 if (agc1_power == 0) {
1886 for (i = 0; i < 5; i++)
1887 aq_power += (stv0900_get_bits(intp, POWER_I) +
1888 stv0900_get_bits(intp, POWER_Q)) / 2;
2715 1889
2716 stv0900_set_tuner(fe, i_params->tuner2_freq, i_params->tuner2_bw); 1890 aq_power /= 5;
1891 }
2717 1892
2718 stv0900_write_bits(i_params, F0900_P2_SPECINV_CONTROL, i_params->dmd2_srch_iq_inv); 1893 if ((agc1_power == 0) && (aq_power < IQPOWER_THRESHOLD)) {
2719 stv0900_write_bits(i_params, F0900_P2_MANUAL_ROLLOFF, 1); 1894 intp->result[demod].locked = FALSE;
1895 signal_type = STV0900_NOAGC1;
1896 dprintk("%s: NO AGC1, POWERI, POWERQ\n", __func__);
1897 } else {
1898 stv0900_write_bits(intp, SPECINV_CONTROL,
1899 intp->srch_iq_inv[demod]);
1900 if (intp->chip_id <= 0x20) /*cut 2.0*/
1901 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
1902 else /*cut 3.0*/
1903 stv0900_write_bits(intp, MANUALS2_ROLLOFF, 1);
2720 1904
2721 stv0900_set_search_standard(i_params, demod); 1905 stv0900_set_search_standard(intp, demod);
2722 1906
2723 if (i_params->dmd2_srch_algo != STV0900_BLIND_SEARCH) 1907 if (intp->srch_algo[demod] != STV0900_BLIND_SEARCH)
2724 stv0900_start_search(i_params, demod); 1908 stv0900_start_search(intp, demod);
2725 break;
2726 } 1909 }
2727 1910
2728 if (i_params->chip_id == 0x12) { 1911 if (signal_type == STV0900_NOAGC1)
2729 stv0900_write_bits(i_params, stream_merger_field, 0); 1912 return signal_type;
1913
1914 if (intp->chip_id == 0x12) {
1915 stv0900_write_bits(intp, RST_HWARE, 0);
2730 msleep(3); 1916 msleep(3);
2731 stv0900_write_bits(i_params, stream_merger_field, 1); 1917 stv0900_write_bits(intp, RST_HWARE, 1);
2732 stv0900_write_bits(i_params, stream_merger_field, 0); 1918 stv0900_write_bits(intp, RST_HWARE, 0);
2733 } 1919 }
2734 1920
2735 if (algo == STV0900_BLIND_SEARCH) 1921 if (algo == STV0900_BLIND_SEARCH)
@@ -2737,12 +1923,12 @@ enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
2737 else if (algo == STV0900_COLD_START) 1923 else if (algo == STV0900_COLD_START)
2738 lock = stv0900_get_demod_cold_lock(fe, demod_timeout); 1924 lock = stv0900_get_demod_cold_lock(fe, demod_timeout);
2739 else if (algo == STV0900_WARM_START) 1925 else if (algo == STV0900_WARM_START)
2740 lock = stv0900_get_demod_lock(i_params, demod, demod_timeout); 1926 lock = stv0900_get_demod_lock(intp, demod, demod_timeout);
2741 1927
2742 if ((lock == FALSE) && (algo == STV0900_COLD_START)) { 1928 if ((lock == FALSE) && (algo == STV0900_COLD_START)) {
2743 if (low_sr == FALSE) { 1929 if (low_sr == FALSE) {
2744 if (stv0900_check_timing_lock(i_params, demod) == TRUE) 1930 if (stv0900_check_timing_lock(intp, demod) == TRUE)
2745 lock = stv0900_sw_algo(i_params, demod); 1931 lock = stv0900_sw_algo(intp, demod);
2746 } 1932 }
2747 } 1933 }
2748 1934
@@ -2751,98 +1937,64 @@ enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
2751 1937
2752 if ((lock == TRUE) && (signal_type == STV0900_RANGEOK)) { 1938 if ((lock == TRUE) && (signal_type == STV0900_RANGEOK)) {
2753 stv0900_track_optimization(fe); 1939 stv0900_track_optimization(fe);
2754 if (i_params->chip_id <= 0x11) { 1940 if (intp->chip_id <= 0x11) {
2755 if ((stv0900_get_standard(fe, STV0900_DEMOD_1) == STV0900_DVBS1_STANDARD) && (stv0900_get_standard(fe, STV0900_DEMOD_2) == STV0900_DVBS1_STANDARD)) { 1941 if ((stv0900_get_standard(fe, 0) ==
1942 STV0900_DVBS1_STANDARD) &&
1943 (stv0900_get_standard(fe, 1) ==
1944 STV0900_DVBS1_STANDARD)) {
2756 msleep(20); 1945 msleep(20);
2757 stv0900_write_bits(i_params, stream_merger_field, 0); 1946 stv0900_write_bits(intp, RST_HWARE, 0);
2758 } else { 1947 } else {
2759 stv0900_write_bits(i_params, stream_merger_field, 0); 1948 stv0900_write_bits(intp, RST_HWARE, 0);
2760 msleep(3); 1949 msleep(3);
2761 stv0900_write_bits(i_params, stream_merger_field, 1); 1950 stv0900_write_bits(intp, RST_HWARE, 1);
2762 stv0900_write_bits(i_params, stream_merger_field, 0); 1951 stv0900_write_bits(intp, RST_HWARE, 0);
2763 } 1952 }
2764 } else if (i_params->chip_id == 0x20) { 1953
2765 stv0900_write_bits(i_params, stream_merger_field, 0); 1954 } else if (intp->chip_id >= 0x20) {
1955 stv0900_write_bits(intp, RST_HWARE, 0);
2766 msleep(3); 1956 msleep(3);
2767 stv0900_write_bits(i_params, stream_merger_field, 1); 1957 stv0900_write_bits(intp, RST_HWARE, 1);
2768 stv0900_write_bits(i_params, stream_merger_field, 0); 1958 stv0900_write_bits(intp, RST_HWARE, 0);
2769 } 1959 }
2770 1960
2771 if (stv0900_wait_for_lock(i_params, demod, fec_timeout, fec_timeout) == TRUE) { 1961 if (stv0900_wait_for_lock(intp, demod,
1962 fec_timeout, fec_timeout) == TRUE) {
2772 lock = TRUE; 1963 lock = TRUE;
2773 switch (demod) { 1964 intp->result[demod].locked = TRUE;
2774 case STV0900_DEMOD_1: 1965 if (intp->result[demod].standard ==
2775 default: 1966 STV0900_DVBS2_STANDARD) {
2776 i_params->dmd1_rslts.locked = TRUE; 1967 stv0900_set_dvbs2_rolloff(intp, demod);
2777 if (i_params->dmd1_rslts.standard == STV0900_DVBS2_STANDARD) { 1968 stv0900_write_bits(intp, RESET_UPKO_COUNT, 1);
2778 stv0900_set_dvbs2_rolloff(i_params, demod); 1969 stv0900_write_bits(intp, RESET_UPKO_COUNT, 0);
2779 stv0900_write_reg(i_params, R0900_P1_PDELCTRL2, 0x40); 1970 stv0900_write_reg(intp, ERRCTRL1, 0x67);
2780 stv0900_write_reg(i_params, R0900_P1_PDELCTRL2, 0); 1971 } else {
2781 stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x67); 1972 stv0900_write_reg(intp, ERRCTRL1, 0x75);
2782 } else {
2783 stv0900_write_reg(i_params, R0900_P1_ERRCTRL1, 0x75);
2784 }
2785
2786 stv0900_write_reg(i_params, R0900_P1_FBERCPT4, 0);
2787 stv0900_write_reg(i_params, R0900_P1_ERRCTRL2, 0xc1);
2788 break;
2789 case STV0900_DEMOD_2:
2790 i_params->dmd2_rslts.locked = TRUE;
2791
2792 if (i_params->dmd2_rslts.standard == STV0900_DVBS2_STANDARD) {
2793 stv0900_set_dvbs2_rolloff(i_params, demod);
2794 stv0900_write_reg(i_params, R0900_P2_PDELCTRL2, 0x60);
2795 stv0900_write_reg(i_params, R0900_P2_PDELCTRL2, 0x20);
2796 stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x67);
2797 } else {
2798 stv0900_write_reg(i_params, R0900_P2_ERRCTRL1, 0x75);
2799 }
2800
2801 stv0900_write_reg(i_params, R0900_P2_FBERCPT4, 0);
2802
2803 stv0900_write_reg(i_params, R0900_P2_ERRCTRL2, 0xc1);
2804 break;
2805 } 1973 }
1974
1975 stv0900_write_reg(intp, FBERCPT4, 0);
1976 stv0900_write_reg(intp, ERRCTRL2, 0xc1);
2806 } else { 1977 } else {
2807 lock = FALSE; 1978 lock = FALSE;
2808 signal_type = STV0900_NODATA; 1979 signal_type = STV0900_NODATA;
2809 no_signal = stv0900_check_signal_presence(i_params, demod); 1980 no_signal = stv0900_check_signal_presence(intp, demod);
2810 1981
2811 switch (demod) { 1982 intp->result[demod].locked = FALSE;
2812 case STV0900_DEMOD_1:
2813 default:
2814 i_params->dmd1_rslts.locked = FALSE;
2815 break;
2816 case STV0900_DEMOD_2:
2817 i_params->dmd2_rslts.locked = FALSE;
2818 break;
2819 }
2820 } 1983 }
2821 } 1984 }
2822 1985
2823 if ((signal_type == STV0900_NODATA) && (no_signal == FALSE)) { 1986 if ((signal_type != STV0900_NODATA) || (no_signal != FALSE))
2824 switch (demod) { 1987 return signal_type;
2825 case STV0900_DEMOD_1:
2826 default:
2827 if (i_params->chip_id <= 0x11) {
2828 if ((stv0900_get_bits(i_params, F0900_P1_HEADER_MODE) == STV0900_DVBS_FOUND) &&
2829 (i_params->dmd1_srch_iq_inv <= STV0900_IQ_AUTO_NORMAL_FIRST))
2830 signal_type = stv0900_dvbs1_acq_workaround(fe);
2831 } else
2832 i_params->dmd1_rslts.locked = FALSE;
2833 1988
2834 break; 1989 if (intp->chip_id > 0x11) {
2835 case STV0900_DEMOD_2: 1990 intp->result[demod].locked = FALSE;
2836 if (i_params->chip_id <= 0x11) { 1991 return signal_type;
2837 if ((stv0900_get_bits(i_params, F0900_P2_HEADER_MODE) == STV0900_DVBS_FOUND) &&
2838 (i_params->dmd2_srch_iq_inv <= STV0900_IQ_AUTO_NORMAL_FIRST))
2839 signal_type = stv0900_dvbs1_acq_workaround(fe);
2840 } else
2841 i_params->dmd2_rslts.locked = FALSE;
2842 break;
2843 }
2844 } 1992 }
2845 1993
1994 if ((stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) &&
1995 (intp->srch_iq_inv[demod] <= STV0900_IQ_AUTO_NORMAL_FIRST))
1996 signal_type = stv0900_dvbs1_acq_workaround(fe);
1997
2846 return signal_type; 1998 return signal_type;
2847} 1999}
2848 2000
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