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authorJuan J. Garcia de Soria <skandalfo@gmail.com>2011-03-16 16:14:52 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2011-03-22 15:38:31 -0400
commit620a32bba4a2dd57ccf1d5f87b9e6d2402ffec22 (patch)
tree7304e9abbec324f370e443b27aa1c4032fe7811d /drivers/media
parentbaf075eca42f217e8d297914ed6fecfd2452a0e4 (diff)
[media] rc: New rc-based ite-cir driver for several ITE CIRs
This is a second version of an rc-core based driver for the ITE Tech IT8712F CIR and now for a pair of other variants of the IT8512 CIR too. This driver should replace the lirc_it87 and lirc_ite8709 currently living in the LIRC staging directory. The driver should support the ITE8704, ITE8713, ITE8708 and ITE8709 (this last one yet untested) PNP ID's. The code doesn'te reuse code from the pre-existing LIRC drivers, but has been written from scratch using the nuvoton.cir driver as a skeleton. This new driver shouldn't exhibit timing problems when running under load (or with interrupts disabled for relatively long times). It works OOTB with the RC6 MCE remote bundled with the ASUS EEEBox. TX support is implemented, but I'm unable to test it since my hardware lacks TX capability. Signed-off-by: Juan J. Garcia de Soria <skandalfo@gmail.com> Tested-by: Stephan Raue <stephan@openelec.tv> Signed-off-by: Jarod Wilson <jarod@redhat.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media')
-rw-r--r--drivers/media/rc/Kconfig13
-rw-r--r--drivers/media/rc/Makefile1
-rw-r--r--drivers/media/rc/ite-cir.c1734
-rw-r--r--drivers/media/rc/ite-cir.h478
4 files changed, 2226 insertions, 0 deletions
diff --git a/drivers/media/rc/Kconfig b/drivers/media/rc/Kconfig
index 1143845dd688..7f03142a329f 100644
--- a/drivers/media/rc/Kconfig
+++ b/drivers/media/rc/Kconfig
@@ -135,6 +135,19 @@ config IR_MCEUSB
135 To compile this driver as a module, choose M here: the 135 To compile this driver as a module, choose M here: the
136 module will be called mceusb. 136 module will be called mceusb.
137 137
138config IR_ITE_CIR
139 tristate "ITE Tech Inc. IT8712/IT8512 Consumer Infrared Transceiver"
140 depends on PNP
141 depends on RC_CORE
142 ---help---
143 Say Y here to enable support for integrated infrared receivers
144 /transceivers made by ITE Tech Inc. These are found in
145 several ASUS devices, like the ASUS Digimatrix or the ASUS
146 EEEBox 1501U.
147
148 To compile this driver as a module, choose M here: the
149 module will be called ite-cir.
150
138config IR_NUVOTON 151config IR_NUVOTON
139 tristate "Nuvoton w836x7hg Consumer Infrared Transceiver" 152 tristate "Nuvoton w836x7hg Consumer Infrared Transceiver"
140 depends on PNP 153 depends on PNP
diff --git a/drivers/media/rc/Makefile b/drivers/media/rc/Makefile
index 67b4f7fe2577..c6cfe70d862f 100644
--- a/drivers/media/rc/Makefile
+++ b/drivers/media/rc/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_IR_LIRC_CODEC) += ir-lirc-codec.o
14 14
15# stand-alone IR receivers/transmitters 15# stand-alone IR receivers/transmitters
16obj-$(CONFIG_IR_IMON) += imon.o 16obj-$(CONFIG_IR_IMON) += imon.o
17obj-$(CONFIG_IR_ITE_CIR) += ite-cir.o
17obj-$(CONFIG_IR_MCEUSB) += mceusb.o 18obj-$(CONFIG_IR_MCEUSB) += mceusb.o
18obj-$(CONFIG_IR_NUVOTON) += nuvoton-cir.o 19obj-$(CONFIG_IR_NUVOTON) += nuvoton-cir.o
19obj-$(CONFIG_IR_ENE) += ene_ir.o 20obj-$(CONFIG_IR_ENE) += ene_ir.o
diff --git a/drivers/media/rc/ite-cir.c b/drivers/media/rc/ite-cir.c
new file mode 100644
index 000000000000..10358d5b3189
--- /dev/null
+++ b/drivers/media/rc/ite-cir.c
@@ -0,0 +1,1734 @@
1/*
2 * Driver for ITE Tech Inc. IT8712F/IT8512 CIR
3 *
4 * Copyright (C) 2010 Juan Jesús García de Soria <skandalfo@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of the
9 * License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
19 * USA.
20 *
21 * Inspired by the original lirc_it87 and lirc_ite8709 drivers, on top of the
22 * skeleton provided by the nuvoton-cir driver.
23 *
24 * The lirc_it87 driver was originally written by Hans-Gunter Lutke Uphues
25 * <hg_lu@web.de> in 2001, with enhancements by Christoph Bartelmus
26 * <lirc@bartelmus.de>, Andrew Calkin <r_tay@hotmail.com> and James Edwards
27 * <jimbo-lirc@edwardsclan.net>.
28 *
29 * The lirc_ite8709 driver was written by Grégory Lardière
30 * <spmf2004-lirc@yahoo.fr> in 2008.
31 */
32
33#include <linux/kernel.h>
34#include <linux/module.h>
35#include <linux/pnp.h>
36#include <linux/io.h>
37#include <linux/interrupt.h>
38#include <linux/sched.h>
39#include <linux/slab.h>
40#include <linux/input.h>
41#include <linux/bitops.h>
42#include <media/rc-core.h>
43#include <linux/pci_ids.h>
44
45#include "ite-cir.h"
46
47/* module parameters */
48
49/* debug level */
50static int debug;
51module_param(debug, int, S_IRUGO | S_IWUSR);
52MODULE_PARM_DESC(debug, "Enable debugging output");
53
54/* low limit for RX carrier freq, Hz, 0 for no RX demodulation */
55static int rx_low_carrier_freq;
56module_param(rx_low_carrier_freq, int, S_IRUGO | S_IWUSR);
57MODULE_PARM_DESC(rx_low_carrier_freq, "Override low RX carrier frequency, Hz, "
58 "0 for no RX demodulation");
59
60/* high limit for RX carrier freq, Hz, 0 for no RX demodulation */
61static int rx_high_carrier_freq;
62module_param(rx_high_carrier_freq, int, S_IRUGO | S_IWUSR);
63MODULE_PARM_DESC(rx_high_carrier_freq, "Override high RX carrier frequency, "
64 "Hz, 0 for no RX demodulation");
65
66/* override tx carrier frequency */
67static int tx_carrier_freq;
68module_param(tx_carrier_freq, int, S_IRUGO | S_IWUSR);
69MODULE_PARM_DESC(tx_carrier_freq, "Override TX carrier frequency, Hz");
70
71/* override tx duty cycle */
72static int tx_duty_cycle;
73module_param(tx_duty_cycle, int, S_IRUGO | S_IWUSR);
74MODULE_PARM_DESC(tx_duty_cycle, "Override TX duty cycle, 1-100");
75
76/* override default sample period */
77static long sample_period;
78module_param(sample_period, long, S_IRUGO | S_IWUSR);
79MODULE_PARM_DESC(sample_period, "Override carrier sample period, us");
80
81/* override detected model id */
82static int model_number = -1;
83module_param(model_number, int, S_IRUGO | S_IWUSR);
84MODULE_PARM_DESC(model_number, "Use this model number, don't autodetect");
85
86
87/* HW-independent code functions */
88
89/* check whether carrier frequency is high frequency */
90static inline bool ite_is_high_carrier_freq(unsigned int freq)
91{
92 return freq >= ITE_HCF_MIN_CARRIER_FREQ;
93}
94
95/* get the bits required to program the carrier frequency in CFQ bits,
96 * unshifted */
97static u8 ite_get_carrier_freq_bits(unsigned int freq)
98{
99 if (ite_is_high_carrier_freq(freq)) {
100 if (freq < 425000)
101 return ITE_CFQ_400;
102
103 else if (freq < 465000)
104 return ITE_CFQ_450;
105
106 else if (freq < 490000)
107 return ITE_CFQ_480;
108
109 else
110 return ITE_CFQ_500;
111 } else {
112 /* trim to limits */
113 if (freq < ITE_LCF_MIN_CARRIER_FREQ)
114 freq = ITE_LCF_MIN_CARRIER_FREQ;
115 if (freq > ITE_LCF_MAX_CARRIER_FREQ)
116 freq = ITE_LCF_MAX_CARRIER_FREQ;
117
118 /* convert to kHz and subtract the base freq */
119 freq =
120 DIV_ROUND_CLOSEST(freq - ITE_LCF_MIN_CARRIER_FREQ,
121 1000);
122
123 return (u8) freq;
124 }
125}
126
127/* get the bits required to program the pulse with in TXMPW */
128static u8 ite_get_pulse_width_bits(unsigned int freq, int duty_cycle)
129{
130 unsigned long period_ns, on_ns;
131
132 /* sanitize freq into range */
133 if (freq < ITE_LCF_MIN_CARRIER_FREQ)
134 freq = ITE_LCF_MIN_CARRIER_FREQ;
135 if (freq > ITE_HCF_MAX_CARRIER_FREQ)
136 freq = ITE_HCF_MAX_CARRIER_FREQ;
137
138 period_ns = 1000000000UL / freq;
139 on_ns = period_ns * duty_cycle / 100;
140
141 if (ite_is_high_carrier_freq(freq)) {
142 if (on_ns < 750)
143 return ITE_TXMPW_A;
144
145 else if (on_ns < 850)
146 return ITE_TXMPW_B;
147
148 else if (on_ns < 950)
149 return ITE_TXMPW_C;
150
151 else if (on_ns < 1080)
152 return ITE_TXMPW_D;
153
154 else
155 return ITE_TXMPW_E;
156 } else {
157 if (on_ns < 6500)
158 return ITE_TXMPW_A;
159
160 else if (on_ns < 7850)
161 return ITE_TXMPW_B;
162
163 else if (on_ns < 9650)
164 return ITE_TXMPW_C;
165
166 else if (on_ns < 11950)
167 return ITE_TXMPW_D;
168
169 else
170 return ITE_TXMPW_E;
171 }
172}
173
174/* decode raw bytes as received by the hardware, and push them to the ir-core
175 * layer */
176static void ite_decode_bytes(struct ite_dev *dev, const u8 * data, int
177 length)
178{
179 u32 sample_period;
180 unsigned long *ldata;
181 unsigned int next_one, next_zero, size;
182 DEFINE_IR_RAW_EVENT(ev);
183
184 if (length == 0)
185 return;
186
187 sample_period = dev->params.sample_period;
188 ldata = (unsigned long *)data;
189 size = length << 3;
190 next_one = generic_find_next_le_bit(ldata, size, 0);
191 if (next_one > 0) {
192 ev.pulse = true;
193 ev.duration =
194 ITE_BITS_TO_NS(next_one, sample_period);
195 ir_raw_event_store_with_filter(dev->rdev, &ev);
196 }
197
198 while (next_one < size) {
199 next_zero = generic_find_next_zero_le_bit(ldata, size, next_one + 1);
200 ev.pulse = false;
201 ev.duration = ITE_BITS_TO_NS(next_zero - next_one, sample_period);
202 ir_raw_event_store_with_filter(dev->rdev, &ev);
203
204 if (next_zero < size) {
205 next_one =
206 generic_find_next_le_bit(ldata,
207 size,
208 next_zero + 1);
209 ev.pulse = true;
210 ev.duration =
211 ITE_BITS_TO_NS(next_one - next_zero,
212 sample_period);
213 ir_raw_event_store_with_filter
214 (dev->rdev, &ev);
215 } else
216 next_one = size;
217 }
218
219 ir_raw_event_handle(dev->rdev);
220
221 ite_dbg_verbose("decoded %d bytes.", length);
222}
223
224/* set all the rx/tx carrier parameters; this must be called with the device
225 * spinlock held */
226static void ite_set_carrier_params(struct ite_dev *dev)
227{
228 unsigned int freq, low_freq, high_freq;
229 int allowance;
230 bool use_demodulator;
231 bool for_tx = dev->transmitting;
232
233 ite_dbg("%s called", __func__);
234
235 if (for_tx) {
236 /* we don't need no stinking calculations */
237 freq = dev->params.tx_carrier_freq;
238 allowance = ITE_RXDCR_DEFAULT;
239 use_demodulator = false;
240 } else {
241 low_freq = dev->params.rx_low_carrier_freq;
242 high_freq = dev->params.rx_high_carrier_freq;
243
244 if (low_freq == 0) {
245 /* don't demodulate */
246 freq =
247 ITE_DEFAULT_CARRIER_FREQ;
248 allowance = ITE_RXDCR_DEFAULT;
249 use_demodulator = false;
250 } else {
251 /* calculate the middle freq */
252 freq = (low_freq + high_freq) / 2;
253
254 /* calculate the allowance */
255 allowance =
256 DIV_ROUND_CLOSEST(10000 * (high_freq - low_freq),
257 ITE_RXDCR_PER_10000_STEP
258 * (high_freq + low_freq));
259
260 if (allowance < 1)
261 allowance = 1;
262
263 if (allowance > ITE_RXDCR_MAX)
264 allowance = ITE_RXDCR_MAX;
265 }
266 }
267
268 /* set the carrier parameters in a device-dependent way */
269 dev->params.set_carrier_params(dev, ite_is_high_carrier_freq(freq),
270 use_demodulator, ite_get_carrier_freq_bits(freq), allowance,
271 ite_get_pulse_width_bits(freq, dev->params.tx_duty_cycle));
272}
273
274/* interrupt service routine for incoming and outgoing CIR data */
275static irqreturn_t ite_cir_isr(int irq, void *data)
276{
277 struct ite_dev *dev = data;
278 unsigned long flags;
279 irqreturn_t ret = IRQ_RETVAL(IRQ_NONE);
280 u8 rx_buf[ITE_RX_FIFO_LEN];
281 int rx_bytes;
282 int iflags;
283
284 ite_dbg_verbose("%s firing", __func__);
285
286 /* grab the spinlock */
287 spin_lock_irqsave(&dev->lock, flags);
288
289 /* read the interrupt flags */
290 iflags = dev->params.get_irq_causes(dev);
291
292 /* check for the receive interrupt */
293 if (iflags & (ITE_IRQ_RX_FIFO | ITE_IRQ_RX_FIFO_OVERRUN)) {
294 /* read the FIFO bytes */
295 rx_bytes =
296 dev->params.get_rx_bytes(dev, rx_buf,
297 ITE_RX_FIFO_LEN);
298
299 if (rx_bytes > 0) {
300 /* drop the spinlock, since the ir-core layer
301 * may call us back again through
302 * ite_s_idle() */
303 spin_unlock_irqrestore(&dev->
304 lock,
305 flags);
306
307 /* decode the data we've just received */
308 ite_decode_bytes(dev, rx_buf,
309 rx_bytes);
310
311 /* reacquire the spinlock */
312 spin_lock_irqsave(&dev->lock,
313 flags);
314
315 /* mark the interrupt as serviced */
316 ret = IRQ_RETVAL(IRQ_HANDLED);
317 }
318 } else if (iflags & ITE_IRQ_TX_FIFO) {
319 /* FIFO space available interrupt */
320 ite_dbg_verbose("got interrupt for TX FIFO");
321
322 /* wake any sleeping transmitter */
323 wake_up_interruptible(&dev->tx_queue);
324
325 /* mark the interrupt as serviced */
326 ret = IRQ_RETVAL(IRQ_HANDLED);
327 }
328
329 /* drop the spinlock */
330 spin_unlock_irqrestore(&dev->lock, flags);
331
332 ite_dbg_verbose("%s done returning %d", __func__, (int)ret);
333
334 return ret;
335}
336
337/* set the rx carrier freq range, guess it's in Hz... */
338static int ite_set_rx_carrier_range(struct rc_dev *rcdev, u32 carrier_low, u32
339 carrier_high)
340{
341 unsigned long flags;
342 struct ite_dev *dev = rcdev->priv;
343
344 spin_lock_irqsave(&dev->lock, flags);
345 dev->params.rx_low_carrier_freq = carrier_low;
346 dev->params.rx_high_carrier_freq = carrier_high;
347 ite_set_carrier_params(dev);
348 spin_unlock_irqrestore(&dev->lock, flags);
349
350 return 0;
351}
352
353/* set the tx carrier freq, guess it's in Hz... */
354static int ite_set_tx_carrier(struct rc_dev *rcdev, u32 carrier)
355{
356 unsigned long flags;
357 struct ite_dev *dev = rcdev->priv;
358
359 spin_lock_irqsave(&dev->lock, flags);
360 dev->params.tx_carrier_freq = carrier;
361 ite_set_carrier_params(dev);
362 spin_unlock_irqrestore(&dev->lock, flags);
363
364 return 0;
365}
366
367/* set the tx duty cycle by controlling the pulse width */
368static int ite_set_tx_duty_cycle(struct rc_dev *rcdev, u32 duty_cycle)
369{
370 unsigned long flags;
371 struct ite_dev *dev = rcdev->priv;
372
373 spin_lock_irqsave(&dev->lock, flags);
374 dev->params.tx_duty_cycle = duty_cycle;
375 ite_set_carrier_params(dev);
376 spin_unlock_irqrestore(&dev->lock, flags);
377
378 return 0;
379}
380
381/* transmit out IR pulses; what you get here is a batch of alternating
382 * pulse/space/pulse/space lengths that we should write out completely through
383 * the FIFO, blocking on a full FIFO */
384static int ite_tx_ir(struct rc_dev *rcdev, int *txbuf, u32 n)
385{
386 unsigned long flags;
387 struct ite_dev *dev = rcdev->priv;
388 bool is_pulse = false;
389 int remaining_us, fifo_avail, fifo_remaining, last_idx = 0;
390 int max_rle_us, next_rle_us;
391 int ret = n;
392 u8 last_sent[ITE_TX_FIFO_LEN];
393 u8 val;
394
395 ite_dbg("%s called", __func__);
396
397 /* clear the array just in case */
398 memset(last_sent, 0, ARRAY_SIZE(last_sent));
399
400 /* n comes in bytes; convert to ints */
401 n /= sizeof(int);
402
403 spin_lock_irqsave(&dev->lock, flags);
404
405 /* let everybody know we're now transmitting */
406 dev->transmitting = true;
407
408 /* and set the carrier values for transmission */
409 ite_set_carrier_params(dev);
410
411 /* calculate how much time we can send in one byte */
412 max_rle_us =
413 (ITE_BAUDRATE_DIVISOR * dev->params.sample_period *
414 ITE_TX_MAX_RLE) / 1000;
415
416 /* disable the receiver */
417 dev->params.disable_rx(dev);
418
419 /* this is where we'll begin filling in the FIFO, until it's full.
420 * then we'll just activate the interrupt, wait for it to wake us up
421 * again, disable it, continue filling the FIFO... until everything
422 * has been pushed out */
423 fifo_avail =
424 ITE_TX_FIFO_LEN - dev->params.get_tx_used_slots(dev);
425
426 while (n > 0 && dev->in_use) {
427 /* transmit the next sample */
428 is_pulse = !is_pulse;
429 remaining_us = *(txbuf++);
430 n--;
431
432 ite_dbg("%s: %ld",
433 ((is_pulse) ? "pulse" : "space"),
434 (long int)
435 remaining_us);
436
437 /* repeat while the pulse is non-zero length */
438 while (remaining_us > 0 && dev->in_use) {
439 if (remaining_us > max_rle_us)
440 next_rle_us = max_rle_us;
441
442 else
443 next_rle_us = remaining_us;
444
445 remaining_us -= next_rle_us;
446
447 /* check what's the length we have to pump out */
448 val = (ITE_TX_MAX_RLE * next_rle_us) / max_rle_us;
449
450 /* put it into the sent buffer */
451 last_sent[last_idx++] = val;
452 last_idx &= (ITE_TX_FIFO_LEN);
453
454 /* encode it for 7 bits */
455 val = (val - 1) & ITE_TX_RLE_MASK;
456
457 /* take into account pulse/space prefix */
458 if (is_pulse)
459 val |= ITE_TX_PULSE;
460
461 else
462 val |= ITE_TX_SPACE;
463
464 /* if we get to 0 available, read again, just in case
465 * some other slot got freed */
466 if (fifo_avail <= 0)
467 fifo_avail = ITE_TX_FIFO_LEN - dev->params.get_tx_used_slots(dev);
468
469 /* if it's still full */
470 if (fifo_avail <= 0) {
471 /* enable the tx interrupt */
472 dev->params.
473 enable_tx_interrupt(dev);
474
475 /* drop the spinlock */
476 spin_unlock_irqrestore(&dev->lock, flags);
477
478 /* wait for the FIFO to empty enough */
479 wait_event_interruptible(dev->tx_queue, (fifo_avail = ITE_TX_FIFO_LEN - dev->params.get_tx_used_slots(dev)) >= 8);
480
481 /* get the spinlock again */
482 spin_lock_irqsave(&dev->lock, flags);
483
484 /* disable the tx interrupt again. */
485 dev->params.
486 disable_tx_interrupt(dev);
487 }
488
489 /* now send the byte through the FIFO */
490 dev->params.put_tx_byte(dev, val);
491 fifo_avail--;
492 }
493 }
494
495 /* wait and don't return until the whole FIFO has been sent out;
496 * otherwise we could configure the RX carrier params instead of the
497 * TX ones while the transmission is still being performed! */
498 fifo_remaining = dev->params.get_tx_used_slots(dev);
499 remaining_us = 0;
500 while (fifo_remaining > 0) {
501 fifo_remaining--;
502 last_idx--;
503 last_idx &= (ITE_TX_FIFO_LEN - 1);
504 remaining_us += last_sent[last_idx];
505 }
506 remaining_us = (remaining_us * max_rle_us) / (ITE_TX_MAX_RLE);
507
508 /* drop the spinlock while we sleep */
509 spin_unlock_irqrestore(&dev->lock, flags);
510
511 /* sleep remaining_us microseconds */
512 mdelay(DIV_ROUND_UP(remaining_us, 1000));
513
514 /* reacquire the spinlock */
515 spin_lock_irqsave(&dev->lock, flags);
516
517 /* now we're not transmitting anymore */
518 dev->transmitting = false;
519
520 /* and set the carrier values for reception */
521 ite_set_carrier_params(dev);
522
523 /* reenable the receiver */
524 if (dev->in_use)
525 dev->params.enable_rx(dev);
526
527 /* notify transmission end */
528 wake_up_interruptible(&dev->tx_ended);
529
530 spin_unlock_irqrestore(&dev->lock, flags);
531
532 return ret;
533}
534
535/* idle the receiver if needed */
536static void ite_s_idle(struct rc_dev *rcdev, bool enable)
537{
538 unsigned long flags;
539 struct ite_dev *dev = rcdev->priv;
540
541 ite_dbg("%s called", __func__);
542
543 if (enable) {
544 spin_lock_irqsave(&dev->lock, flags);
545 dev->params.idle_rx(dev);
546 spin_unlock_irqrestore(&dev->lock, flags);
547 }
548}
549
550
551/* IT8712F HW-specific functions */
552
553/* retrieve a bitmask of the current causes for a pending interrupt; this may
554 * be composed of ITE_IRQ_TX_FIFO, ITE_IRQ_RX_FIFO and ITE_IRQ_RX_FIFO_OVERRUN
555 * */
556static int it87_get_irq_causes(struct ite_dev *dev)
557{
558 u8 iflags;
559 int ret = 0;
560
561 ite_dbg("%s called", __func__);
562
563 /* read the interrupt flags */
564 iflags = inb(dev->cir_addr + IT87_IIR) & IT87_II;
565
566 switch (iflags) {
567 case IT87_II_RXDS:
568 ret = ITE_IRQ_RX_FIFO;
569 break;
570 case IT87_II_RXFO:
571 ret = ITE_IRQ_RX_FIFO_OVERRUN;
572 break;
573 case IT87_II_TXLDL:
574 ret = ITE_IRQ_TX_FIFO;
575 break;
576 }
577
578 return ret;
579}
580
581/* set the carrier parameters; to be called with the spinlock held */
582static void it87_set_carrier_params(struct ite_dev *dev, bool high_freq,
583 bool use_demodulator,
584 u8 carrier_freq_bits, u8 allowance_bits,
585 u8 pulse_width_bits)
586{
587 u8 val;
588
589 ite_dbg("%s called", __func__);
590
591 /* program the RCR register */
592 val = inb(dev->cir_addr + IT87_RCR)
593 & ~(IT87_HCFS | IT87_RXEND | IT87_RXDCR);
594
595 if (high_freq)
596 val |= IT87_HCFS;
597
598 if (use_demodulator)
599 val |= IT87_RXEND;
600
601 val |= allowance_bits;
602
603 outb(val, dev->cir_addr + IT87_RCR);
604
605 /* program the TCR2 register */
606 outb((carrier_freq_bits << IT87_CFQ_SHIFT) | pulse_width_bits,
607 dev->cir_addr + IT87_TCR2);
608}
609
610/* read up to buf_size bytes from the RX FIFO; to be called with the spinlock
611 * held */
612static int it87_get_rx_bytes(struct ite_dev *dev, u8 * buf, int buf_size)
613{
614 int fifo, read = 0;
615
616 ite_dbg("%s called", __func__);
617
618 /* read how many bytes are still in the FIFO */
619 fifo = inb(dev->cir_addr + IT87_RSR) & IT87_RXFBC;
620
621 while (fifo > 0 && buf_size > 0) {
622 *(buf++) = inb(dev->cir_addr + IT87_DR);
623 fifo--;
624 read++;
625 buf_size--;
626 }
627
628 return read;
629}
630
631/* return how many bytes are still in the FIFO; this will be called
632 * with the device spinlock NOT HELD while waiting for the TX FIFO to get
633 * empty; let's expect this won't be a problem */
634static int it87_get_tx_used_slots(struct ite_dev *dev)
635{
636 ite_dbg("%s called", __func__);
637
638 return inb(dev->cir_addr + IT87_TSR) & IT87_TXFBC;
639}
640
641/* put a byte to the TX fifo; this should be called with the spinlock held */
642static void it87_put_tx_byte(struct ite_dev *dev, u8 value)
643{
644 outb(value, dev->cir_addr + IT87_DR);
645}
646
647/* idle the receiver so that we won't receive samples until another
648 pulse is detected; this must be called with the device spinlock held */
649static void it87_idle_rx(struct ite_dev *dev)
650{
651 ite_dbg("%s called", __func__);
652
653 /* disable streaming by clearing RXACT writing it as 1 */
654 outb(inb(dev->cir_addr + IT87_RCR) | IT87_RXACT,
655 dev->cir_addr + IT87_RCR);
656
657 /* clear the FIFO */
658 outb(inb(dev->cir_addr + IT87_TCR1) | IT87_FIFOCLR,
659 dev->cir_addr + IT87_TCR1);
660}
661
662/* disable the receiver; this must be called with the device spinlock held */
663static void it87_disable_rx(struct ite_dev *dev)
664{
665 ite_dbg("%s called", __func__);
666
667 /* disable the receiver interrupts */
668 outb(inb(dev->cir_addr + IT87_IER) & ~(IT87_RDAIE | IT87_RFOIE),
669 dev->cir_addr + IT87_IER);
670
671 /* disable the receiver */
672 outb(inb(dev->cir_addr + IT87_RCR) & ~IT87_RXEN,
673 dev->cir_addr + IT87_RCR);
674
675 /* clear the FIFO and RXACT (actually RXACT should have been cleared
676 * in the previous outb() call) */
677 it87_idle_rx(dev);
678}
679
680/* enable the receiver; this must be called with the device spinlock held */
681static void it87_enable_rx(struct ite_dev *dev)
682{
683 ite_dbg("%s called", __func__);
684
685 /* enable the receiver by setting RXEN */
686 outb(inb(dev->cir_addr + IT87_RCR) | IT87_RXEN,
687 dev->cir_addr + IT87_RCR);
688
689 /* just prepare it to idle for the next reception */
690 it87_idle_rx(dev);
691
692 /* enable the receiver interrupts and master enable flag */
693 outb(inb(dev->cir_addr + IT87_IER) | IT87_RDAIE | IT87_RFOIE | IT87_IEC,
694 dev->cir_addr + IT87_IER);
695}
696
697/* disable the transmitter interrupt; this must be called with the device
698 * spinlock held */
699static void it87_disable_tx_interrupt(struct ite_dev *dev)
700{
701 ite_dbg("%s called", __func__);
702
703 /* disable the transmitter interrupts */
704 outb(inb(dev->cir_addr + IT87_IER) & ~IT87_TLDLIE,
705 dev->cir_addr + IT87_IER);
706}
707
708/* enable the transmitter interrupt; this must be called with the device
709 * spinlock held */
710static void it87_enable_tx_interrupt(struct ite_dev *dev)
711{
712 ite_dbg("%s called", __func__);
713
714 /* enable the transmitter interrupts and master enable flag */
715 outb(inb(dev->cir_addr + IT87_IER) | IT87_TLDLIE | IT87_IEC,
716 dev->cir_addr + IT87_IER);
717}
718
719/* disable the device; this must be called with the device spinlock held */
720static void it87_disable(struct ite_dev *dev)
721{
722 ite_dbg("%s called", __func__);
723
724 /* clear out all interrupt enable flags */
725 outb(inb(dev->cir_addr + IT87_IER) &
726 ~(IT87_IEC | IT87_RFOIE | IT87_RDAIE | IT87_TLDLIE),
727 dev->cir_addr + IT87_IER);
728
729 /* disable the receiver */
730 it87_disable_rx(dev);
731
732 /* erase the FIFO */
733 outb(IT87_FIFOCLR | inb(dev->cir_addr + IT87_TCR1),
734 dev->cir_addr + IT87_TCR1);
735}
736
737/* initialize the hardware */
738static void it87_init_hardware(struct ite_dev *dev)
739{
740 ite_dbg("%s called", __func__);
741
742 /* enable just the baud rate divisor register,
743 disabling all the interrupts at the same time */
744 outb((inb(dev->cir_addr + IT87_IER) &
745 ~(IT87_IEC | IT87_RFOIE | IT87_RDAIE | IT87_TLDLIE)) | IT87_BR,
746 dev->cir_addr + IT87_IER);
747
748 /* write out the baud rate divisor */
749 outb(ITE_BAUDRATE_DIVISOR & 0xff, dev->cir_addr + IT87_BDLR);
750 outb((ITE_BAUDRATE_DIVISOR >> 8) & 0xff, dev->cir_addr + IT87_BDHR);
751
752 /* disable the baud rate divisor register again */
753 outb(inb(dev->cir_addr + IT87_IER) & ~IT87_BR,
754 dev->cir_addr + IT87_IER);
755
756 /* program the RCR register defaults */
757 outb(ITE_RXDCR_DEFAULT, dev->cir_addr + IT87_RCR);
758
759 /* program the TCR1 register */
760 outb(IT87_TXMPM_DEFAULT | IT87_TXENDF | IT87_TXRLE
761 | IT87_FIFOTL_DEFAULT | IT87_FIFOCLR,
762 dev->cir_addr + IT87_TCR1);
763
764 /* program the carrier parameters */
765 ite_set_carrier_params(dev);
766}
767
768/* IT8512F on ITE8708 HW-specific functions */
769
770/* retrieve a bitmask of the current causes for a pending interrupt; this may
771 * be composed of ITE_IRQ_TX_FIFO, ITE_IRQ_RX_FIFO and ITE_IRQ_RX_FIFO_OVERRUN
772 * */
773static int it8708_get_irq_causes(struct ite_dev *dev)
774{
775 u8 iflags;
776 int ret = 0;
777
778 ite_dbg("%s called", __func__);
779
780 /* read the interrupt flags */
781 iflags = inb(dev->cir_addr + IT8708_C0IIR);
782
783 if (iflags & IT85_TLDLI)
784 ret |= ITE_IRQ_TX_FIFO;
785 if (iflags & IT85_RDAI)
786 ret |= ITE_IRQ_RX_FIFO;
787 if (iflags & IT85_RFOI)
788 ret |= ITE_IRQ_RX_FIFO_OVERRUN;
789
790 return ret;
791}
792
793/* set the carrier parameters; to be called with the spinlock held */
794static void it8708_set_carrier_params(struct ite_dev *dev, bool high_freq,
795 bool use_demodulator,
796 u8 carrier_freq_bits, u8 allowance_bits,
797 u8 pulse_width_bits)
798{
799 u8 val;
800
801 ite_dbg("%s called", __func__);
802
803 /* program the C0CFR register, with HRAE=1 */
804 outb(inb(dev->cir_addr + IT8708_BANKSEL) | IT8708_HRAE,
805 dev->cir_addr + IT8708_BANKSEL);
806
807 val = (inb(dev->cir_addr + IT8708_C0CFR)
808 & ~(IT85_HCFS | IT85_CFQ)) | carrier_freq_bits;
809
810 if (high_freq)
811 val |= IT85_HCFS;
812
813 outb(val, dev->cir_addr + IT8708_C0CFR);
814
815 outb(inb(dev->cir_addr + IT8708_BANKSEL) & ~IT8708_HRAE,
816 dev->cir_addr + IT8708_BANKSEL);
817
818 /* program the C0RCR register */
819 val = inb(dev->cir_addr + IT8708_C0RCR)
820 & ~(IT85_RXEND | IT85_RXDCR);
821
822 if (use_demodulator)
823 val |= IT85_RXEND;
824
825 val |= allowance_bits;
826
827 outb(val, dev->cir_addr + IT8708_C0RCR);
828
829 /* program the C0TCR register */
830 val = inb(dev->cir_addr + IT8708_C0TCR) & ~IT85_TXMPW;
831 val |= pulse_width_bits;
832 outb(val, dev->cir_addr + IT8708_C0TCR);
833}
834
835/* read up to buf_size bytes from the RX FIFO; to be called with the spinlock
836 * held */
837static int it8708_get_rx_bytes(struct ite_dev *dev, u8 * buf, int buf_size)
838{
839 int fifo, read = 0;
840
841 ite_dbg("%s called", __func__);
842
843 /* read how many bytes are still in the FIFO */
844 fifo = inb(dev->cir_addr + IT8708_C0RFSR) & IT85_RXFBC;
845
846 while (fifo > 0 && buf_size > 0) {
847 *(buf++) = inb(dev->cir_addr + IT8708_C0DR);
848 fifo--;
849 read++;
850 buf_size--;
851 }
852
853 return read;
854}
855
856/* return how many bytes are still in the FIFO; this will be called
857 * with the device spinlock NOT HELD while waiting for the TX FIFO to get
858 * empty; let's expect this won't be a problem */
859static int it8708_get_tx_used_slots(struct ite_dev *dev)
860{
861 ite_dbg("%s called", __func__);
862
863 return inb(dev->cir_addr + IT8708_C0TFSR) & IT85_TXFBC;
864}
865
866/* put a byte to the TX fifo; this should be called with the spinlock held */
867static void it8708_put_tx_byte(struct ite_dev *dev, u8 value)
868{
869 outb(value, dev->cir_addr + IT8708_C0DR);
870}
871
872/* idle the receiver so that we won't receive samples until another
873 pulse is detected; this must be called with the device spinlock held */
874static void it8708_idle_rx(struct ite_dev *dev)
875{
876 ite_dbg("%s called", __func__);
877
878 /* disable streaming by clearing RXACT writing it as 1 */
879 outb(inb(dev->cir_addr + IT8708_C0RCR) | IT85_RXACT,
880 dev->cir_addr + IT8708_C0RCR);
881
882 /* clear the FIFO */
883 outb(inb(dev->cir_addr + IT8708_C0MSTCR) | IT85_FIFOCLR,
884 dev->cir_addr + IT8708_C0MSTCR);
885}
886
887/* disable the receiver; this must be called with the device spinlock held */
888static void it8708_disable_rx(struct ite_dev *dev)
889{
890 ite_dbg("%s called", __func__);
891
892 /* disable the receiver interrupts */
893 outb(inb(dev->cir_addr + IT8708_C0IER) &
894 ~(IT85_RDAIE | IT85_RFOIE),
895 dev->cir_addr + IT8708_C0IER);
896
897 /* disable the receiver */
898 outb(inb(dev->cir_addr + IT8708_C0RCR) & ~IT85_RXEN,
899 dev->cir_addr + IT8708_C0RCR);
900
901 /* clear the FIFO and RXACT (actually RXACT should have been cleared
902 * in the previous outb() call) */
903 it8708_idle_rx(dev);
904}
905
906/* enable the receiver; this must be called with the device spinlock held */
907static void it8708_enable_rx(struct ite_dev *dev)
908{
909 ite_dbg("%s called", __func__);
910
911 /* enable the receiver by setting RXEN */
912 outb(inb(dev->cir_addr + IT8708_C0RCR) | IT85_RXEN,
913 dev->cir_addr + IT8708_C0RCR);
914
915 /* just prepare it to idle for the next reception */
916 it8708_idle_rx(dev);
917
918 /* enable the receiver interrupts and master enable flag */
919 outb(inb(dev->cir_addr + IT8708_C0IER)
920 |IT85_RDAIE | IT85_RFOIE | IT85_IEC,
921 dev->cir_addr + IT8708_C0IER);
922}
923
924/* disable the transmitter interrupt; this must be called with the device
925 * spinlock held */
926static void it8708_disable_tx_interrupt(struct ite_dev *dev)
927{
928 ite_dbg("%s called", __func__);
929
930 /* disable the transmitter interrupts */
931 outb(inb(dev->cir_addr + IT8708_C0IER) & ~IT85_TLDLIE,
932 dev->cir_addr + IT8708_C0IER);
933}
934
935/* enable the transmitter interrupt; this must be called with the device
936 * spinlock held */
937static void it8708_enable_tx_interrupt(struct ite_dev *dev)
938{
939 ite_dbg("%s called", __func__);
940
941 /* enable the transmitter interrupts and master enable flag */
942 outb(inb(dev->cir_addr + IT8708_C0IER)
943 |IT85_TLDLIE | IT85_IEC,
944 dev->cir_addr + IT8708_C0IER);
945}
946
947/* disable the device; this must be called with the device spinlock held */
948static void it8708_disable(struct ite_dev *dev)
949{
950 ite_dbg("%s called", __func__);
951
952 /* clear out all interrupt enable flags */
953 outb(inb(dev->cir_addr + IT8708_C0IER) &
954 ~(IT85_IEC | IT85_RFOIE | IT85_RDAIE | IT85_TLDLIE),
955 dev->cir_addr + IT8708_C0IER);
956
957 /* disable the receiver */
958 it8708_disable_rx(dev);
959
960 /* erase the FIFO */
961 outb(IT85_FIFOCLR | inb(dev->cir_addr + IT8708_C0MSTCR),
962 dev->cir_addr + IT8708_C0MSTCR);
963}
964
965/* initialize the hardware */
966static void it8708_init_hardware(struct ite_dev *dev)
967{
968 ite_dbg("%s called", __func__);
969
970 /* disable all the interrupts */
971 outb(inb(dev->cir_addr + IT8708_C0IER) &
972 ~(IT85_IEC | IT85_RFOIE | IT85_RDAIE | IT85_TLDLIE),
973 dev->cir_addr + IT8708_C0IER);
974
975 /* program the baud rate divisor */
976 outb(inb(dev->cir_addr + IT8708_BANKSEL) | IT8708_HRAE,
977 dev->cir_addr + IT8708_BANKSEL);
978
979 outb(ITE_BAUDRATE_DIVISOR & 0xff, dev->cir_addr + IT8708_C0BDLR);
980 outb((ITE_BAUDRATE_DIVISOR >> 8) & 0xff,
981 dev->cir_addr + IT8708_C0BDHR);
982
983 outb(inb(dev->cir_addr + IT8708_BANKSEL) & ~IT8708_HRAE,
984 dev->cir_addr + IT8708_BANKSEL);
985
986 /* program the C0MSTCR register defaults */
987 outb((inb(dev->cir_addr + IT8708_C0MSTCR) &
988 ~(IT85_ILSEL | IT85_ILE | IT85_FIFOTL |
989 IT85_FIFOCLR | IT85_RESET)) |
990 IT85_FIFOTL_DEFAULT,
991 dev->cir_addr + IT8708_C0MSTCR);
992
993 /* program the C0RCR register defaults */
994 outb((inb(dev->cir_addr + IT8708_C0RCR) &
995 ~(IT85_RXEN | IT85_RDWOS | IT85_RXEND |
996 IT85_RXACT | IT85_RXDCR)) |
997 ITE_RXDCR_DEFAULT,
998 dev->cir_addr + IT8708_C0RCR);
999
1000 /* program the C0TCR register defaults */
1001 outb((inb(dev->cir_addr + IT8708_C0TCR) &
1002 ~(IT85_TXMPM | IT85_TXMPW))
1003 |IT85_TXRLE | IT85_TXENDF |
1004 IT85_TXMPM_DEFAULT | IT85_TXMPW_DEFAULT,
1005 dev->cir_addr + IT8708_C0TCR);
1006
1007 /* program the carrier parameters */
1008 ite_set_carrier_params(dev);
1009}
1010
1011/* IT8512F on ITE8709 HW-specific functions */
1012
1013/* read a byte from the SRAM module */
1014static inline u8 it8709_rm(struct ite_dev *dev, int index)
1015{
1016 outb(index, dev->cir_addr + IT8709_RAM_IDX);
1017 return inb(dev->cir_addr + IT8709_RAM_VAL);
1018}
1019
1020/* write a byte to the SRAM module */
1021static inline void it8709_wm(struct ite_dev *dev, u8 val, int index)
1022{
1023 outb(index, dev->cir_addr + IT8709_RAM_IDX);
1024 outb(val, dev->cir_addr + IT8709_RAM_VAL);
1025}
1026
1027static void it8709_wait(struct ite_dev *dev)
1028{
1029 int i = 0;
1030 /*
1031 * loop until device tells it's ready to continue
1032 * iterations count is usually ~750 but can sometimes achieve 13000
1033 */
1034 for (i = 0; i < 15000; i++) {
1035 udelay(2);
1036 if (it8709_rm(dev, IT8709_MODE) == IT8709_IDLE)
1037 break;
1038 }
1039}
1040
1041/* read the value of a CIR register */
1042static u8 it8709_rr(struct ite_dev *dev, int index)
1043{
1044 /* just wait in case the previous access was a write */
1045 it8709_wait(dev);
1046 it8709_wm(dev, index, IT8709_REG_IDX);
1047 it8709_wm(dev, IT8709_READ, IT8709_MODE);
1048
1049 /* wait for the read data to be available */
1050 it8709_wait(dev);
1051
1052 /* return the read value */
1053 return it8709_rm(dev, IT8709_REG_VAL);
1054}
1055
1056/* write the value of a CIR register */
1057static void it8709_wr(struct ite_dev *dev, u8 val, int index)
1058{
1059 /* we wait before writing, and not afterwards, since this allows us to
1060 * pipeline the host CPU with the microcontroller */
1061 it8709_wait(dev);
1062 it8709_wm(dev, val, IT8709_REG_VAL);
1063 it8709_wm(dev, index, IT8709_REG_IDX);
1064 it8709_wm(dev, IT8709_WRITE, IT8709_MODE);
1065}
1066
1067/* retrieve a bitmask of the current causes for a pending interrupt; this may
1068 * be composed of ITE_IRQ_TX_FIFO, ITE_IRQ_RX_FIFO and ITE_IRQ_RX_FIFO_OVERRUN
1069 * */
1070static int it8709_get_irq_causes(struct ite_dev *dev)
1071{
1072 u8 iflags;
1073 int ret = 0;
1074
1075 ite_dbg("%s called", __func__);
1076
1077 /* read the interrupt flags */
1078 iflags = it8709_rm(dev, IT8709_IIR);
1079
1080 if (iflags & IT85_TLDLI)
1081 ret |= ITE_IRQ_TX_FIFO;
1082 if (iflags & IT85_RDAI)
1083 ret |= ITE_IRQ_RX_FIFO;
1084 if (iflags & IT85_RFOI)
1085 ret |= ITE_IRQ_RX_FIFO_OVERRUN;
1086
1087 return ret;
1088}
1089
1090/* set the carrier parameters; to be called with the spinlock held */
1091static void it8709_set_carrier_params(struct ite_dev *dev, bool high_freq,
1092 bool use_demodulator,
1093 u8 carrier_freq_bits, u8 allowance_bits,
1094 u8 pulse_width_bits)
1095{
1096 u8 val;
1097
1098 ite_dbg("%s called", __func__);
1099
1100 val = (it8709_rr(dev, IT85_C0CFR)
1101 &~(IT85_HCFS | IT85_CFQ)) |
1102 carrier_freq_bits;
1103
1104 if (high_freq)
1105 val |= IT85_HCFS;
1106
1107 it8709_wr(dev, val, IT85_C0CFR);
1108
1109 /* program the C0RCR register */
1110 val = it8709_rr(dev, IT85_C0RCR)
1111 & ~(IT85_RXEND | IT85_RXDCR);
1112
1113 if (use_demodulator)
1114 val |= IT85_RXEND;
1115
1116 val |= allowance_bits;
1117
1118 it8709_wr(dev, val, IT85_C0RCR);
1119
1120 /* program the C0TCR register */
1121 val = it8709_rr(dev, IT85_C0TCR) & ~IT85_TXMPW;
1122 val |= pulse_width_bits;
1123 it8709_wr(dev, val, IT85_C0TCR);
1124}
1125
1126/* read up to buf_size bytes from the RX FIFO; to be called with the spinlock
1127 * held */
1128static int it8709_get_rx_bytes(struct ite_dev *dev, u8 * buf, int buf_size)
1129{
1130 int fifo, read = 0;
1131
1132 ite_dbg("%s called", __func__);
1133
1134 /* read how many bytes are still in the FIFO */
1135 fifo = it8709_rm(dev, IT8709_RFSR) & IT85_RXFBC;
1136
1137 while (fifo > 0 && buf_size > 0) {
1138 *(buf++) = it8709_rm(dev, IT8709_FIFO + read);
1139 fifo--;
1140 read++;
1141 buf_size--;
1142 }
1143
1144 /* 'clear' the FIFO by setting the writing index to 0; this is
1145 * completely bound to be racy, but we can't help it, since it's a
1146 * limitation of the protocol */
1147 it8709_wm(dev, 0, IT8709_RFSR);
1148
1149 return read;
1150}
1151
1152/* return how many bytes are still in the FIFO; this will be called
1153 * with the device spinlock NOT HELD while waiting for the TX FIFO to get
1154 * empty; let's expect this won't be a problem */
1155static int it8709_get_tx_used_slots(struct ite_dev *dev)
1156{
1157 ite_dbg("%s called", __func__);
1158
1159 return it8709_rr(dev, IT85_C0TFSR) & IT85_TXFBC;
1160}
1161
1162/* put a byte to the TX fifo; this should be called with the spinlock held */
1163static void it8709_put_tx_byte(struct ite_dev *dev, u8 value)
1164{
1165 it8709_wr(dev, value, IT85_C0DR);
1166}
1167
1168/* idle the receiver so that we won't receive samples until another
1169 pulse is detected; this must be called with the device spinlock held */
1170static void it8709_idle_rx(struct ite_dev *dev)
1171{
1172 ite_dbg("%s called", __func__);
1173
1174 /* disable streaming by clearing RXACT writing it as 1 */
1175 it8709_wr(dev, it8709_rr(dev, IT85_C0RCR) | IT85_RXACT,
1176 IT85_C0RCR);
1177
1178 /* clear the FIFO */
1179 it8709_wr(dev, it8709_rr(dev, IT85_C0MSTCR) | IT85_FIFOCLR,
1180 IT85_C0MSTCR);
1181}
1182
1183/* disable the receiver; this must be called with the device spinlock held */
1184static void it8709_disable_rx(struct ite_dev *dev)
1185{
1186 ite_dbg("%s called", __func__);
1187
1188 /* disable the receiver interrupts */
1189 it8709_wr(dev, it8709_rr(dev, IT85_C0IER) &
1190 ~(IT85_RDAIE | IT85_RFOIE),
1191 IT85_C0IER);
1192
1193 /* disable the receiver */
1194 it8709_wr(dev, it8709_rr(dev, IT85_C0RCR) & ~IT85_RXEN,
1195 IT85_C0RCR);
1196
1197 /* clear the FIFO and RXACT (actually RXACT should have been cleared
1198 * in the previous it8709_wr(dev, ) call) */
1199 it8709_idle_rx(dev);
1200}
1201
1202/* enable the receiver; this must be called with the device spinlock held */
1203static void it8709_enable_rx(struct ite_dev *dev)
1204{
1205 ite_dbg("%s called", __func__);
1206
1207 /* enable the receiver by setting RXEN */
1208 it8709_wr(dev, it8709_rr(dev, IT85_C0RCR) | IT85_RXEN,
1209 IT85_C0RCR);
1210
1211 /* just prepare it to idle for the next reception */
1212 it8709_idle_rx(dev);
1213
1214 /* enable the receiver interrupts and master enable flag */
1215 it8709_wr(dev, it8709_rr(dev, IT85_C0IER)
1216 |IT85_RDAIE | IT85_RFOIE | IT85_IEC,
1217 IT85_C0IER);
1218}
1219
1220/* disable the transmitter interrupt; this must be called with the device
1221 * spinlock held */
1222static void it8709_disable_tx_interrupt(struct ite_dev *dev)
1223{
1224 ite_dbg("%s called", __func__);
1225
1226 /* disable the transmitter interrupts */
1227 it8709_wr(dev, it8709_rr(dev, IT85_C0IER) & ~IT85_TLDLIE,
1228 IT85_C0IER);
1229}
1230
1231/* enable the transmitter interrupt; this must be called with the device
1232 * spinlock held */
1233static void it8709_enable_tx_interrupt(struct ite_dev *dev)
1234{
1235 ite_dbg("%s called", __func__);
1236
1237 /* enable the transmitter interrupts and master enable flag */
1238 it8709_wr(dev, it8709_rr(dev, IT85_C0IER)
1239 |IT85_TLDLIE | IT85_IEC,
1240 IT85_C0IER);
1241}
1242
1243/* disable the device; this must be called with the device spinlock held */
1244static void it8709_disable(struct ite_dev *dev)
1245{
1246 ite_dbg("%s called", __func__);
1247
1248 /* clear out all interrupt enable flags */
1249 it8709_wr(dev,
1250 it8709_rr(dev,
1251 IT85_C0IER) & ~(IT85_IEC | IT85_RFOIE |
1252 IT85_RDAIE |
1253 IT85_TLDLIE), IT85_C0IER);
1254
1255 /* disable the receiver */
1256 it8709_disable_rx(dev);
1257
1258 /* erase the FIFO */
1259 it8709_wr(dev, IT85_FIFOCLR | it8709_rr(dev, IT85_C0MSTCR),
1260 IT85_C0MSTCR);
1261}
1262
1263/* initialize the hardware */
1264static void it8709_init_hardware(struct ite_dev *dev)
1265{
1266 ite_dbg("%s called", __func__);
1267
1268 /* disable all the interrupts */
1269 it8709_wr(dev,
1270 it8709_rr(dev,
1271 IT85_C0IER) & ~(IT85_IEC | IT85_RFOIE |
1272 IT85_RDAIE |
1273 IT85_TLDLIE), IT85_C0IER);
1274
1275 /* program the baud rate divisor */
1276 it8709_wr(dev, ITE_BAUDRATE_DIVISOR & 0xff, IT85_C0BDLR);
1277 it8709_wr(dev, (ITE_BAUDRATE_DIVISOR >> 8) & 0xff,
1278 IT85_C0BDHR);
1279
1280 /* program the C0MSTCR register defaults */
1281 it8709_wr(dev, (it8709_rr(dev, IT85_C0MSTCR) & ~(IT85_ILSEL |
1282 IT85_ILE
1283 | IT85_FIFOTL
1284 |
1285 IT85_FIFOCLR
1286 |
1287 IT85_RESET))
1288 | IT85_FIFOTL_DEFAULT, IT85_C0MSTCR);
1289
1290 /* program the C0RCR register defaults */
1291 it8709_wr(dev,
1292 (it8709_rr(dev, IT85_C0RCR) &
1293 ~(IT85_RXEN | IT85_RDWOS | IT85_RXEND
1294 | IT85_RXACT | IT85_RXDCR)) |
1295 ITE_RXDCR_DEFAULT, IT85_C0RCR);
1296
1297 /* program the C0TCR register defaults */
1298 it8709_wr(dev, (it8709_rr(dev, IT85_C0TCR)
1299 &~(IT85_TXMPM | IT85_TXMPW))
1300 |IT85_TXRLE | IT85_TXENDF |
1301 IT85_TXMPM_DEFAULT |
1302 IT85_TXMPW_DEFAULT, IT85_C0TCR);
1303
1304 /* program the carrier parameters */
1305 ite_set_carrier_params(dev);
1306}
1307
1308
1309/* generic hardware setup/teardown code */
1310
1311/* activate the device for use */
1312static int ite_open(struct rc_dev *rcdev)
1313{
1314 struct ite_dev *dev = rcdev->priv;
1315 unsigned long flags;
1316
1317 ite_dbg("%s called", __func__);
1318
1319 spin_lock_irqsave(&dev->lock, flags);
1320 dev->in_use = true;
1321
1322 /* enable the receiver */
1323 dev->params.enable_rx(dev);
1324
1325 spin_unlock_irqrestore(&dev->lock, flags);
1326
1327 return 0;
1328}
1329
1330/* deactivate the device for use */
1331static void ite_close(struct rc_dev *rcdev)
1332{
1333 struct ite_dev *dev = rcdev->priv;
1334 unsigned long flags;
1335
1336 ite_dbg("%s called", __func__);
1337
1338 spin_lock_irqsave(&dev->lock, flags);
1339 dev->in_use = false;
1340
1341 /* wait for any transmission to end */
1342 spin_unlock_irqrestore(&dev->lock, flags);
1343 wait_event_interruptible(dev->tx_ended, !dev->transmitting);
1344 spin_lock_irqsave(&dev->lock, flags);
1345
1346 dev->params.disable(dev);
1347
1348 spin_unlock_irqrestore(&dev->lock, flags);
1349}
1350
1351/* supported models and their parameters */
1352static const struct ite_dev_params ite_dev_descs[] = {
1353 { /* 0: ITE8704 */
1354 .model = "ITE8704 CIR transceiver",
1355 .io_region_size = IT87_IOREG_LENGTH,
1356 .hw_tx_capable = true,
1357 .sample_period = (u32) (1000000000ULL / 115200),
1358 .tx_carrier_freq = 38000,
1359 .tx_duty_cycle = 33,
1360 .rx_low_carrier_freq = 0,
1361 .rx_high_carrier_freq = 0,
1362
1363 /* operations */
1364 .get_irq_causes = it87_get_irq_causes,
1365 .enable_rx = it87_enable_rx,
1366 .idle_rx = it87_idle_rx,
1367 .disable_rx = it87_idle_rx,
1368 .get_rx_bytes = it87_get_rx_bytes,
1369 .enable_tx_interrupt = it87_enable_tx_interrupt,
1370 .disable_tx_interrupt = it87_disable_tx_interrupt,
1371 .get_tx_used_slots = it87_get_tx_used_slots,
1372 .put_tx_byte = it87_put_tx_byte,
1373 .disable = it87_disable,
1374 .init_hardware = it87_init_hardware,
1375 .set_carrier_params = it87_set_carrier_params,
1376 },
1377 { /* 1: ITE8713 */
1378 .model = "ITE8713 CIR transceiver",
1379 .io_region_size = IT87_IOREG_LENGTH,
1380 .hw_tx_capable = true,
1381 .sample_period = (u32) (1000000000ULL / 115200),
1382 .tx_carrier_freq = 38000,
1383 .tx_duty_cycle = 33,
1384 .rx_low_carrier_freq = 0,
1385 .rx_high_carrier_freq = 0,
1386
1387 /* operations */
1388 .get_irq_causes = it87_get_irq_causes,
1389 .enable_rx = it87_enable_rx,
1390 .idle_rx = it87_idle_rx,
1391 .disable_rx = it87_idle_rx,
1392 .get_rx_bytes = it87_get_rx_bytes,
1393 .enable_tx_interrupt = it87_enable_tx_interrupt,
1394 .disable_tx_interrupt = it87_disable_tx_interrupt,
1395 .get_tx_used_slots = it87_get_tx_used_slots,
1396 .put_tx_byte = it87_put_tx_byte,
1397 .disable = it87_disable,
1398 .init_hardware = it87_init_hardware,
1399 .set_carrier_params = it87_set_carrier_params,
1400 },
1401 { /* 2: ITE8708 */
1402 .model = "ITE8708 CIR transceiver",
1403 .io_region_size = IT8708_IOREG_LENGTH,
1404 .hw_tx_capable = true,
1405 .sample_period = (u32) (1000000000ULL / 115200),
1406 .tx_carrier_freq = 38000,
1407 .tx_duty_cycle = 33,
1408 .rx_low_carrier_freq = 0,
1409 .rx_high_carrier_freq = 0,
1410
1411 /* operations */
1412 .get_irq_causes = it8708_get_irq_causes,
1413 .enable_rx = it8708_enable_rx,
1414 .idle_rx = it8708_idle_rx,
1415 .disable_rx = it8708_idle_rx,
1416 .get_rx_bytes = it8708_get_rx_bytes,
1417 .enable_tx_interrupt = it8708_enable_tx_interrupt,
1418 .disable_tx_interrupt =
1419 it8708_disable_tx_interrupt,
1420 .get_tx_used_slots = it8708_get_tx_used_slots,
1421 .put_tx_byte = it8708_put_tx_byte,
1422 .disable = it8708_disable,
1423 .init_hardware = it8708_init_hardware,
1424 .set_carrier_params = it8708_set_carrier_params,
1425 },
1426 { /* 3: ITE8709 */
1427 .model = "ITE8709 CIR transceiver",
1428 .io_region_size = IT8709_IOREG_LENGTH,
1429 .hw_tx_capable = true,
1430 .sample_period = (u32) (1000000000ULL / 115200),
1431 .tx_carrier_freq = 38000,
1432 .tx_duty_cycle = 33,
1433 .rx_low_carrier_freq = 0,
1434 .rx_high_carrier_freq = 0,
1435
1436 /* operations */
1437 .get_irq_causes = it8709_get_irq_causes,
1438 .enable_rx = it8709_enable_rx,
1439 .idle_rx = it8709_idle_rx,
1440 .disable_rx = it8709_idle_rx,
1441 .get_rx_bytes = it8709_get_rx_bytes,
1442 .enable_tx_interrupt = it8709_enable_tx_interrupt,
1443 .disable_tx_interrupt =
1444 it8709_disable_tx_interrupt,
1445 .get_tx_used_slots = it8709_get_tx_used_slots,
1446 .put_tx_byte = it8709_put_tx_byte,
1447 .disable = it8709_disable,
1448 .init_hardware = it8709_init_hardware,
1449 .set_carrier_params = it8709_set_carrier_params,
1450 },
1451};
1452
1453static const struct pnp_device_id ite_ids[] = {
1454 {"ITE8704", 0}, /* Default model */
1455 {"ITE8713", 1}, /* CIR found in EEEBox 1501U */
1456 {"ITE8708", 2}, /* Bridged IT8512 */
1457 {"ITE8709", 3}, /* SRAM-Bridged IT8512 */
1458 {"", 0},
1459};
1460
1461/* allocate memory, probe hardware, and initialize everything */
1462static int ite_probe(struct pnp_dev *pdev, const struct pnp_device_id
1463 *dev_id)
1464{
1465 const struct ite_dev_params *dev_desc = NULL;
1466 struct ite_dev *itdev = NULL;
1467 struct rc_dev *rdev = NULL;
1468 int ret = -ENOMEM;
1469 int model_no;
1470
1471 ite_dbg("%s called", __func__);
1472
1473 itdev = kzalloc(sizeof(struct ite_dev), GFP_KERNEL);
1474 if (!itdev)
1475 return ret;
1476
1477 /* input device for IR remote (and tx) */
1478 rdev = rc_allocate_device();
1479 if (!rdev)
1480 goto failure;
1481
1482 ret = -ENODEV;
1483
1484 /* get the model number */
1485 model_no = (int)dev_id->driver_data;
1486 ite_pr(KERN_NOTICE, "Auto-detected model: %s\n",
1487 ite_dev_descs[model_no].model);
1488
1489 if (model_number >= 0 && model_number < ARRAY_SIZE(ite_dev_descs)) {
1490 model_no = model_number;
1491 ite_pr(KERN_NOTICE, "The model has been fixed by a module "
1492 "parameter.");
1493 }
1494
1495 ite_pr(KERN_NOTICE, "Using model: %s\n", ite_dev_descs[model_no].model);
1496
1497 /* get the description for the device */
1498 dev_desc = &ite_dev_descs[model_no];
1499
1500 /* validate pnp resources */
1501 if (!pnp_port_valid(pdev, 0) ||
1502 pnp_port_len(pdev, 0) != dev_desc->io_region_size) {
1503 dev_err(&pdev->dev, "IR PNP Port not valid!\n");
1504 goto failure;
1505 }
1506
1507 if (!pnp_irq_valid(pdev, 0)) {
1508 dev_err(&pdev->dev, "PNP IRQ not valid!\n");
1509 goto failure;
1510 }
1511
1512 /* store resource values */
1513 itdev->cir_addr = pnp_port_start(pdev, 0);
1514 itdev->cir_irq =pnp_irq(pdev, 0);
1515
1516 /* initialize spinlocks */
1517 spin_lock_init(&itdev->lock);
1518
1519 /* initialize raw event */
1520 init_ir_raw_event(&itdev->rawir);
1521
1522 ret = -EBUSY;
1523 /* now claim resources */
1524 if (!request_region(itdev->cir_addr,
1525 dev_desc->io_region_size, ITE_DRIVER_NAME))
1526 goto failure;
1527
1528 if (request_irq(itdev->cir_irq, ite_cir_isr, IRQF_SHARED,
1529 ITE_DRIVER_NAME, (void *)itdev))
1530 goto failure;
1531
1532 /* set driver data into the pnp device */
1533 pnp_set_drvdata(pdev, itdev);
1534 itdev->pdev = pdev;
1535
1536 /* initialize waitqueues for transmission */
1537 init_waitqueue_head(&itdev->tx_queue);
1538 init_waitqueue_head(&itdev->tx_ended);
1539
1540 /* copy model-specific parameters */
1541 itdev->params = *dev_desc;
1542
1543 /* apply any overrides */
1544 if (sample_period > 0)
1545 itdev->params.sample_period = sample_period;
1546
1547 if (tx_carrier_freq > 0)
1548 itdev->params.tx_carrier_freq = tx_carrier_freq;
1549
1550 if (tx_duty_cycle > 0 && tx_duty_cycle <= 100)
1551 itdev->params.tx_duty_cycle = tx_duty_cycle;
1552
1553 if (rx_low_carrier_freq > 0)
1554 itdev->params.rx_low_carrier_freq = rx_low_carrier_freq;
1555
1556 if (rx_high_carrier_freq > 0)
1557 itdev->params.rx_high_carrier_freq = rx_high_carrier_freq;
1558
1559 /* print out parameters */
1560 ite_pr(KERN_NOTICE, "TX-capable: %d\n", (int)
1561 itdev->params.hw_tx_capable);
1562 ite_pr(KERN_NOTICE, "Sample period (ns): %ld\n", (long)
1563 itdev->params.sample_period);
1564 ite_pr(KERN_NOTICE, "TX carrier frequency (Hz): %d\n", (int)
1565 itdev->params.tx_carrier_freq);
1566 ite_pr(KERN_NOTICE, "TX duty cycle (%%): %d\n", (int)
1567 itdev->params.tx_duty_cycle);
1568 ite_pr(KERN_NOTICE, "RX low carrier frequency (Hz): %d\n", (int)
1569 itdev->params.rx_low_carrier_freq);
1570 ite_pr(KERN_NOTICE, "RX high carrier frequency (Hz): %d\n", (int)
1571 itdev->params.rx_high_carrier_freq);
1572
1573 /* set up hardware initial state */
1574 itdev->params.init_hardware(itdev);
1575
1576 /* set up ir-core props */
1577 rdev->priv = itdev;
1578 rdev->driver_type = RC_DRIVER_IR_RAW;
1579 rdev->allowed_protos = RC_TYPE_ALL;
1580 rdev->open = ite_open;
1581 rdev->close = ite_close;
1582 rdev->s_idle = ite_s_idle;
1583 rdev->s_rx_carrier_range = ite_set_rx_carrier_range;
1584 rdev->min_timeout = ITE_MIN_IDLE_TIMEOUT;
1585 rdev->max_timeout = ITE_MAX_IDLE_TIMEOUT;
1586 rdev->timeout = ITE_IDLE_TIMEOUT;
1587 rdev->rx_resolution = ITE_BAUDRATE_DIVISOR *
1588 itdev->params.sample_period;
1589 rdev->tx_resolution = ITE_BAUDRATE_DIVISOR *
1590 itdev->params.sample_period;
1591
1592 /* set up transmitter related values if needed */
1593 if (itdev->params.hw_tx_capable) {
1594 rdev->tx_ir = ite_tx_ir;
1595 rdev->s_tx_carrier = ite_set_tx_carrier;
1596 rdev->s_tx_duty_cycle = ite_set_tx_duty_cycle;
1597 }
1598
1599 rdev->input_name = dev_desc->model;
1600 rdev->input_id.bustype = BUS_HOST;
1601 rdev->input_id.vendor = PCI_VENDOR_ID_ITE;
1602 rdev->input_id.product = 0;
1603 rdev->input_id.version = 0;
1604 rdev->driver_name = ITE_DRIVER_NAME;
1605 rdev->map_name = RC_MAP_RC6_MCE;
1606
1607 ret = rc_register_device(rdev);
1608 if (ret)
1609 goto failure;
1610
1611 itdev->rdev = rdev;
1612 ite_pr(KERN_NOTICE, "driver has been successfully loaded\n");
1613
1614 return 0;
1615
1616failure:
1617 if (itdev->cir_irq)
1618 free_irq(itdev->cir_irq, itdev);
1619
1620 if (itdev->cir_addr)
1621 release_region(itdev->cir_addr, itdev->params.io_region_size);
1622
1623 rc_free_device(rdev);
1624 kfree(itdev);
1625
1626 return ret;
1627}
1628
1629static void __devexit ite_remove(struct pnp_dev *pdev)
1630{
1631 struct ite_dev *dev = pnp_get_drvdata(pdev);
1632 unsigned long flags;
1633
1634 ite_dbg("%s called", __func__);
1635
1636 spin_lock_irqsave(&dev->lock, flags);
1637
1638 /* disable hardware */
1639 dev->params.disable(dev);
1640
1641 spin_unlock_irqrestore(&dev->lock, flags);
1642
1643 /* free resources */
1644 free_irq(dev->cir_irq, dev);
1645 release_region(dev->cir_addr, dev->params.io_region_size);
1646
1647 rc_unregister_device(dev->rdev);
1648
1649 kfree(dev);
1650}
1651
1652static int ite_suspend(struct pnp_dev *pdev, pm_message_t state)
1653{
1654 struct ite_dev *dev = pnp_get_drvdata(pdev);
1655 unsigned long flags;
1656
1657 ite_dbg("%s called", __func__);
1658
1659 spin_lock_irqsave(&dev->lock, flags);
1660
1661 /* disable all interrupts */
1662 dev->params.disable(dev);
1663
1664 spin_unlock_irqrestore(&dev->lock, flags);
1665
1666 return 0;
1667}
1668
1669static int ite_resume(struct pnp_dev *pdev)
1670{
1671 int ret = 0;
1672 struct ite_dev *dev = pnp_get_drvdata(pdev);
1673 unsigned long flags;
1674
1675 ite_dbg("%s called", __func__);
1676
1677 spin_lock_irqsave(&dev->lock, flags);
1678
1679 if (dev->transmitting) {
1680 /* wake up the transmitter */
1681 wake_up_interruptible(&dev->tx_queue);
1682 } else {
1683 /* enable the receiver */
1684 dev->params.enable_rx(dev);
1685 }
1686
1687 spin_unlock_irqrestore(&dev->lock, flags);
1688
1689 return ret;
1690}
1691
1692static void ite_shutdown(struct pnp_dev *pdev)
1693{
1694 struct ite_dev *dev = pnp_get_drvdata(pdev);
1695 unsigned long flags;
1696
1697 ite_dbg("%s called", __func__);
1698
1699 spin_lock_irqsave(&dev->lock, flags);
1700
1701 /* disable all interrupts */
1702 dev->params.disable(dev);
1703
1704 spin_unlock_irqrestore(&dev->lock, flags);
1705}
1706
1707static struct pnp_driver ite_driver = {
1708 .name = ITE_DRIVER_NAME,
1709 .id_table = ite_ids,
1710 .probe = ite_probe,
1711 .remove = __devexit_p(ite_remove),
1712 .suspend = ite_suspend,
1713 .resume = ite_resume,
1714 .shutdown = ite_shutdown,
1715};
1716
1717int ite_init(void)
1718{
1719 return pnp_register_driver(&ite_driver);
1720}
1721
1722void ite_exit(void)
1723{
1724 pnp_unregister_driver(&ite_driver);
1725}
1726
1727MODULE_DEVICE_TABLE(pnp, ite_ids);
1728MODULE_DESCRIPTION("ITE Tech Inc. IT8712F/ITE8512F CIR driver");
1729
1730MODULE_AUTHOR("Juan J. Garcia de Soria <skandalfo@gmail.com>");
1731MODULE_LICENSE("GPL");
1732
1733module_init(ite_init);
1734module_exit(ite_exit);
diff --git a/drivers/media/rc/ite-cir.h b/drivers/media/rc/ite-cir.h
new file mode 100644
index 000000000000..43bac8dc5088
--- /dev/null
+++ b/drivers/media/rc/ite-cir.h
@@ -0,0 +1,478 @@
1/*
2 * Driver for ITE Tech Inc. IT8712F/IT8512F CIR
3 *
4 * Copyright (C) 2010 Juan Jesús García de Soria <skandalfo@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of the
9 * License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
19 * USA.
20 */
21
22/* platform driver name to register */
23#define ITE_DRIVER_NAME "ite-cir"
24
25/* logging macros */
26#define ite_pr(level, text, ...) \
27 printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__)
28#define ite_dbg(text, ...) \
29 if (debug) \
30 printk(KERN_DEBUG \
31 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
32#define ite_dbg_verbose(text, ...) \
33 if (debug > 1) \
34 printk(KERN_DEBUG \
35 KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
36
37/* FIFO sizes */
38#define ITE_TX_FIFO_LEN 32
39#define ITE_RX_FIFO_LEN 32
40
41/* interrupt types */
42#define ITE_IRQ_TX_FIFO 1
43#define ITE_IRQ_RX_FIFO 2
44#define ITE_IRQ_RX_FIFO_OVERRUN 4
45
46/* forward declaration */
47struct ite_dev;
48
49/* struct for storing the parameters of different recognized devices */
50struct ite_dev_params {
51 /* model of the device */
52 const char *model;
53
54 /* size of the I/O region */
55 int io_region_size;
56
57 /* true if the hardware supports transmission */
58 bool hw_tx_capable;
59
60 /* base sampling period, in ns */
61 u32 sample_period;
62
63 /* rx low carrier frequency, in Hz, 0 means no demodulation */
64 unsigned int rx_low_carrier_freq;
65
66 /* tx high carrier frequency, in Hz, 0 means no demodulation */
67 unsigned int rx_high_carrier_freq;
68
69 /* tx carrier frequency, in Hz */
70 unsigned int tx_carrier_freq;
71
72 /* duty cycle, 0-100 */
73 int tx_duty_cycle;
74
75 /* hw-specific operation function pointers; most of these must be
76 * called while holding the spin lock, except for the TX FIFO length
77 * one */
78 /* get pending interrupt causes */
79 int (*get_irq_causes) (struct ite_dev * dev);
80
81 /* enable rx */
82 void (*enable_rx) (struct ite_dev * dev);
83
84 /* make rx enter the idle state; keep listening for a pulse, but stop
85 * streaming space bytes */
86 void (*idle_rx) (struct ite_dev * dev);
87
88 /* disable rx completely */
89 void (*disable_rx) (struct ite_dev * dev);
90
91 /* read bytes from RX FIFO; return read count */
92 int (*get_rx_bytes) (struct ite_dev * dev, u8 * buf, int buf_size);
93
94 /* enable tx FIFO space available interrupt */
95 void (*enable_tx_interrupt) (struct ite_dev * dev);
96
97 /* disable tx FIFO space available interrupt */
98 void (*disable_tx_interrupt) (struct ite_dev * dev);
99
100 /* get number of full TX FIFO slots */
101 int (*get_tx_used_slots) (struct ite_dev * dev);
102
103 /* put a byte to the TX FIFO */
104 void (*put_tx_byte) (struct ite_dev * dev, u8 value);
105
106 /* disable hardware completely */
107 void (*disable) (struct ite_dev * dev);
108
109 /* initialize the hardware */
110 void (*init_hardware) (struct ite_dev * dev);
111
112 /* set the carrier parameters */
113 void (*set_carrier_params) (struct ite_dev * dev, bool high_freq,
114 bool use_demodulator, u8 carrier_freq_bits,
115 u8 allowance_bits, u8 pulse_width_bits);
116};
117
118/* ITE CIR device structure */
119struct ite_dev {
120 struct pnp_dev *pdev;
121 struct rc_dev *rdev;
122 struct ir_raw_event rawir;
123
124 /* sync data */
125 spinlock_t lock;
126 bool in_use, transmitting;
127
128 /* transmit support */
129 int tx_fifo_allowance;
130 wait_queue_head_t tx_queue, tx_ended;
131
132 /* hardware I/O settings */
133 unsigned long cir_addr;
134 int cir_irq;
135
136 /* overridable copy of model parameters */
137 struct ite_dev_params params;
138};
139
140/* common values for all kinds of hardware */
141
142/* baud rate divisor default */
143#define ITE_BAUDRATE_DIVISOR 1
144
145/* low-speed carrier frequency limits (Hz) */
146#define ITE_LCF_MIN_CARRIER_FREQ 27000
147#define ITE_LCF_MAX_CARRIER_FREQ 58000
148
149/* high-speed carrier frequency limits (Hz) */
150#define ITE_HCF_MIN_CARRIER_FREQ 400000
151#define ITE_HCF_MAX_CARRIER_FREQ 500000
152
153/* default carrier freq for when demodulator is off (Hz) */
154#define ITE_DEFAULT_CARRIER_FREQ 38000
155
156/* default idling timeout in ns (0.2 seconds) */
157#define ITE_IDLE_TIMEOUT 200000000UL
158
159/* limit timeout values */
160#define ITE_MIN_IDLE_TIMEOUT 100000000UL
161#define ITE_MAX_IDLE_TIMEOUT 1000000000UL
162
163/* convert bits to us */
164#define ITE_BITS_TO_NS(bits, sample_period) \
165((u32) ((bits) * ITE_BAUDRATE_DIVISOR * sample_period))
166
167/*
168 * n in RDCR produces a tolerance of +/- n * 6.25% around the center
169 * carrier frequency...
170 *
171 * From two limit frequencies, L (low) and H (high), we can get both the
172 * center frequency F = (L + H) / 2 and the variation from the center
173 * frequency A = (H - L) / (H + L). We can use this in order to honor the
174 * s_rx_carrier_range() call in ir-core. We'll suppose that any request
175 * setting L=0 means we must shut down the demodulator.
176 */
177#define ITE_RXDCR_PER_10000_STEP 625
178
179/* high speed carrier freq values */
180#define ITE_CFQ_400 0x03
181#define ITE_CFQ_450 0x08
182#define ITE_CFQ_480 0x0b
183#define ITE_CFQ_500 0x0d
184
185/* values for pulse widths */
186#define ITE_TXMPW_A 0x02
187#define ITE_TXMPW_B 0x03
188#define ITE_TXMPW_C 0x04
189#define ITE_TXMPW_D 0x05
190#define ITE_TXMPW_E 0x06
191
192/* values for demodulator carrier range allowance */
193#define ITE_RXDCR_DEFAULT 0x01 /* default carrier range */
194#define ITE_RXDCR_MAX 0x07 /* default carrier range */
195
196/* DR TX bits */
197#define ITE_TX_PULSE 0x00
198#define ITE_TX_SPACE 0x80
199#define ITE_TX_MAX_RLE 0x80
200#define ITE_TX_RLE_MASK 0x7f
201
202/*
203 * IT8712F
204 *
205 * hardware data obtained from:
206 *
207 * IT8712F
208 * Environment Control – Low Pin Count Input / Output
209 * (EC - LPC I/O)
210 * Preliminary Specification V0. 81
211 */
212
213/* register offsets */
214#define IT87_DR 0x00 /* data register */
215#define IT87_IER 0x01 /* interrupt enable register */
216#define IT87_RCR 0x02 /* receiver control register */
217#define IT87_TCR1 0x03 /* transmitter control register 1 */
218#define IT87_TCR2 0x04 /* transmitter control register 2 */
219#define IT87_TSR 0x05 /* transmitter status register */
220#define IT87_RSR 0x06 /* receiver status register */
221#define IT87_BDLR 0x05 /* baud rate divisor low byte register */
222#define IT87_BDHR 0x06 /* baud rate divisor high byte register */
223#define IT87_IIR 0x07 /* interrupt identification register */
224
225#define IT87_IOREG_LENGTH 0x08 /* length of register file */
226
227/* IER bits */
228#define IT87_TLDLIE 0x01 /* transmitter low data interrupt enable */
229#define IT87_RDAIE 0x02 /* receiver data available interrupt enable */
230#define IT87_RFOIE 0x04 /* receiver FIFO overrun interrupt enable */
231#define IT87_IEC 0x08 /* interrupt enable control */
232#define IT87_BR 0x10 /* baud rate register enable */
233#define IT87_RESET 0x20 /* reset */
234
235/* RCR bits */
236#define IT87_RXDCR 0x07 /* receiver demodulation carrier range mask */
237#define IT87_RXACT 0x08 /* receiver active */
238#define IT87_RXEND 0x10 /* receiver demodulation enable */
239#define IT87_RXEN 0x20 /* receiver enable */
240#define IT87_HCFS 0x40 /* high-speed carrier frequency select */
241#define IT87_RDWOS 0x80 /* receiver data without sync */
242
243/* TCR1 bits */
244#define IT87_TXMPM 0x03 /* transmitter modulation pulse mode mask */
245#define IT87_TXMPM_DEFAULT 0x00 /* modulation pulse mode default */
246#define IT87_TXENDF 0x04 /* transmitter deferral */
247#define IT87_TXRLE 0x08 /* transmitter run length enable */
248#define IT87_FIFOTL 0x30 /* FIFO level threshold mask */
249#define IT87_FIFOTL_DEFAULT 0x20 /* FIFO level threshold default
250 * 0x00 -> 1, 0x10 -> 7, 0x20 -> 17,
251 * 0x30 -> 25 */
252#define IT87_ILE 0x40 /* internal loopback enable */
253#define IT87_FIFOCLR 0x80 /* FIFO clear bit */
254
255/* TCR2 bits */
256#define IT87_TXMPW 0x07 /* transmitter modulation pulse width mask */
257#define IT87_TXMPW_DEFAULT 0x04 /* default modulation pulse width */
258#define IT87_CFQ 0xf8 /* carrier frequency mask */
259#define IT87_CFQ_SHIFT 3 /* carrier frequency bit shift */
260
261/* TSR bits */
262#define IT87_TXFBC 0x3f /* transmitter FIFO byte count mask */
263
264/* RSR bits */
265#define IT87_RXFBC 0x3f /* receiver FIFO byte count mask */
266#define IT87_RXFTO 0x80 /* receiver FIFO time-out */
267
268/* IIR bits */
269#define IT87_IP 0x01 /* interrupt pending */
270#define IT87_II 0x06 /* interrupt identification mask */
271#define IT87_II_NOINT 0x00 /* no interrupt */
272#define IT87_II_TXLDL 0x02 /* transmitter low data level */
273#define IT87_II_RXDS 0x04 /* receiver data stored */
274#define IT87_II_RXFO 0x06 /* receiver FIFO overrun */
275
276/*
277 * IT8512E/F
278 *
279 * Hardware data obtained from:
280 *
281 * IT8512E/F
282 * Embedded Controller
283 * Preliminary Specification V0.4.1
284 *
285 * Note that the CIR registers are not directly available to the host, because
286 * they only are accessible to the integrated microcontroller. Thus, in order
287 * use it, some kind of bridging is required. As the bridging may depend on
288 * the controller firmware in use, we are going to use the PNP ID in order to
289 * determine the strategy and ports available. See after these generic
290 * IT8512E/F register definitions for register definitions for those
291 * strategies.
292 */
293
294/* register offsets */
295#define IT85_C0DR 0x00 /* data register */
296#define IT85_C0MSTCR 0x01 /* master control register */
297#define IT85_C0IER 0x02 /* interrupt enable register */
298#define IT85_C0IIR 0x03 /* interrupt identification register */
299#define IT85_C0CFR 0x04 /* carrier frequency register */
300#define IT85_C0RCR 0x05 /* receiver control register */
301#define IT85_C0TCR 0x06 /* transmitter control register */
302#define IT85_C0SCK 0x07 /* slow clock control register */
303#define IT85_C0BDLR 0x08 /* baud rate divisor low byte register */
304#define IT85_C0BDHR 0x09 /* baud rate divisor high byte register */
305#define IT85_C0TFSR 0x0a /* transmitter FIFO status register */
306#define IT85_C0RFSR 0x0b /* receiver FIFO status register */
307#define IT85_C0WCL 0x0d /* wakeup code length register */
308#define IT85_C0WCR 0x0e /* wakeup code read/write register */
309#define IT85_C0WPS 0x0f /* wakeup power control/status register */
310
311#define IT85_IOREG_LENGTH 0x10 /* length of register file */
312
313/* C0MSTCR bits */
314#define IT85_RESET 0x01 /* reset */
315#define IT85_FIFOCLR 0x02 /* FIFO clear bit */
316#define IT85_FIFOTL 0x0c /* FIFO level threshold mask */
317#define IT85_FIFOTL_DEFAULT 0x08 /* FIFO level threshold default
318 * 0x00 -> 1, 0x04 -> 7, 0x08 -> 17,
319 * 0x0c -> 25 */
320#define IT85_ILE 0x10 /* internal loopback enable */
321#define IT85_ILSEL 0x20 /* internal loopback select */
322
323/* C0IER bits */
324#define IT85_TLDLIE 0x01 /* TX low data level interrupt enable */
325#define IT85_RDAIE 0x02 /* RX data available interrupt enable */
326#define IT85_RFOIE 0x04 /* RX FIFO overrun interrupt enable */
327#define IT85_IEC 0x80 /* interrupt enable function control */
328
329/* C0IIR bits */
330#define IT85_TLDLI 0x01 /* transmitter low data level interrupt */
331#define IT85_RDAI 0x02 /* receiver data available interrupt */
332#define IT85_RFOI 0x04 /* receiver FIFO overrun interrupt */
333#define IT85_NIP 0x80 /* no interrupt pending */
334
335/* C0CFR bits */
336#define IT85_CFQ 0x1f /* carrier frequency mask */
337#define IT85_HCFS 0x20 /* high speed carrier frequency select */
338
339/* C0RCR bits */
340#define IT85_RXDCR 0x07 /* receiver demodulation carrier range mask */
341#define IT85_RXACT 0x08 /* receiver active */
342#define IT85_RXEND 0x10 /* receiver demodulation enable */
343#define IT85_RDWOS 0x20 /* receiver data without sync */
344#define IT85_RXEN 0x80 /* receiver enable */
345
346/* C0TCR bits */
347#define IT85_TXMPW 0x07 /* transmitter modulation pulse width mask */
348#define IT85_TXMPW_DEFAULT 0x04 /* default modulation pulse width */
349#define IT85_TXMPM 0x18 /* transmitter modulation pulse mode mask */
350#define IT85_TXMPM_DEFAULT 0x00 /* modulation pulse mode default */
351#define IT85_TXENDF 0x20 /* transmitter deferral */
352#define IT85_TXRLE 0x40 /* transmitter run length enable */
353
354/* C0SCK bits */
355#define IT85_SCKS 0x01 /* slow clock select */
356#define IT85_TXDCKG 0x02 /* TXD clock gating */
357#define IT85_DLL1P8E 0x04 /* DLL 1.8432M enable */
358#define IT85_DLLTE 0x08 /* DLL test enable */
359#define IT85_BRCM 0x70 /* baud rate count mode */
360#define IT85_DLLOCK 0x80 /* DLL lock */
361
362/* C0TFSR bits */
363#define IT85_TXFBC 0x3f /* transmitter FIFO count mask */
364
365/* C0RFSR bits */
366#define IT85_RXFBC 0x3f /* receiver FIFO count mask */
367#define IT85_RXFTO 0x80 /* receiver FIFO time-out */
368
369/* C0WCL bits */
370#define IT85_WCL 0x3f /* wakeup code length mask */
371
372/* C0WPS bits */
373#define IT85_CIRPOSIE 0x01 /* power on/off status interrupt enable */
374#define IT85_CIRPOIS 0x02 /* power on/off interrupt status */
375#define IT85_CIRPOII 0x04 /* power on/off interrupt identification */
376#define IT85_RCRST 0x10 /* wakeup code reading counter reset bit */
377#define IT85_WCRST 0x20 /* wakeup code writing counter reset bit */
378
379/*
380 * ITE8708
381 *
382 * Hardware data obtained from hacked driver for IT8512 in this forum post:
383 *
384 * http://ubuntuforums.org/showthread.php?t=1028640
385 *
386 * Although there's no official documentation for that driver, analysis would
387 * suggest that it maps the 16 registers of IT8512 onto two 8-register banks,
388 * selectable by a single bank-select bit that's mapped onto both banks. The
389 * IT8512 registers are mapped in a different order, so that the first bank
390 * maps the ones that are used more often, and two registers that share a
391 * reserved high-order bit are placed at the same offset in both banks in
392 * order to reuse the reserved bit as the bank select bit.
393 */
394
395/* register offsets */
396
397/* mapped onto both banks */
398#define IT8708_BANKSEL 0x07 /* bank select register */
399#define IT8708_HRAE 0x80 /* high registers access enable */
400
401/* mapped onto the low bank */
402#define IT8708_C0DR 0x00 /* data register */
403#define IT8708_C0MSTCR 0x01 /* master control register */
404#define IT8708_C0IER 0x02 /* interrupt enable register */
405#define IT8708_C0IIR 0x03 /* interrupt identification register */
406#define IT8708_C0RFSR 0x04 /* receiver FIFO status register */
407#define IT8708_C0RCR 0x05 /* receiver control register */
408#define IT8708_C0TFSR 0x06 /* transmitter FIFO status register */
409#define IT8708_C0TCR 0x07 /* transmitter control register */
410
411/* mapped onto the high bank */
412#define IT8708_C0BDLR 0x01 /* baud rate divisor low byte register */
413#define IT8708_C0BDHR 0x02 /* baud rate divisor high byte register */
414#define IT8708_C0CFR 0x04 /* carrier frequency register */
415
416/* registers whose bank mapping we don't know, since they weren't being used
417 * in the hacked driver... most probably they belong to the high bank too,
418 * since they fit in the holes the other registers leave */
419#define IT8708_C0SCK 0x03 /* slow clock control register */
420#define IT8708_C0WCL 0x05 /* wakeup code length register */
421#define IT8708_C0WCR 0x06 /* wakeup code read/write register */
422#define IT8708_C0WPS 0x07 /* wakeup power control/status register */
423
424#define IT8708_IOREG_LENGTH 0x08 /* length of register file */
425
426/* two more registers that are defined in the hacked driver, but can't be
427 * found in the data sheets; no idea what they are or how they are accessed,
428 * since the hacked driver doesn't seem to use them */
429#define IT8708_CSCRR 0x00
430#define IT8708_CGPINTR 0x01
431
432/* CSCRR bits */
433#define IT8708_CSCRR_SCRB 0x3f
434#define IT8708_CSCRR_PM 0x80
435
436/* CGPINTR bits */
437#define IT8708_CGPINT 0x01
438
439/*
440 * ITE8709
441 *
442 * Hardware interfacing data obtained from the original lirc_ite8709 driver.
443 * Verbatim from its sources:
444 *
445 * The ITE8709 device seems to be the combination of IT8512 superIO chip and
446 * a specific firmware running on the IT8512's embedded micro-controller.
447 * In addition of the embedded micro-controller, the IT8512 chip contains a
448 * CIR module and several other modules. A few modules are directly accessible
449 * by the host CPU, but most of them are only accessible by the
450 * micro-controller. The CIR module is only accessible by the
451 * micro-controller.
452 *
453 * The battery-backed SRAM module is accessible by the host CPU and the
454 * micro-controller. So one of the MC's firmware role is to act as a bridge
455 * between the host CPU and the CIR module. The firmware implements a kind of
456 * communication protocol using the SRAM module as a shared memory. The IT8512
457 * specification is publicly available on ITE's web site, but the
458 * communication protocol is not, so it was reverse-engineered.
459 */
460
461/* register offsets */
462#define IT8709_RAM_IDX 0x00 /* index into the SRAM module bytes */
463#define IT8709_RAM_VAL 0x01 /* read/write data to the indexed byte */
464
465#define IT8709_IOREG_LENGTH 0x02 /* length of register file */
466
467/* register offsets inside the SRAM module */
468#define IT8709_MODE 0x1a /* request/ack byte */
469#define IT8709_REG_IDX 0x1b /* index of the CIR register to access */
470#define IT8709_REG_VAL 0x1c /* value read/to be written */
471#define IT8709_IIR 0x1e /* interrupt identification register */
472#define IT8709_RFSR 0x1f /* receiver FIFO status register */
473#define IT8709_FIFO 0x20 /* start of in RAM RX FIFO copy */
474
475/* MODE values */
476#define IT8709_IDLE 0x00
477#define IT8709_WRITE 0x01
478#define IT8709_READ 0x02
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 19:40:55 -0500