diff options
author | Mike Isely <isely@pobox.com> | 2008-03-28 04:36:25 -0400 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@infradead.org> | 2008-04-24 13:09:47 -0400 |
commit | 448cb48e6e2fcd3a948cc549c5c6ab7f84440a54 (patch) | |
tree | 71aee20c4f71f7a097e9556af5ded132543ee9f4 /drivers/media | |
parent | ad0992e97c5416e431e19dcfd4f6c84448dc1bc2 (diff) |
V4L/DVB (7700): pvrusb2: Make FX2 command codes unsigned constants
Signed-off-by: Mike Isely <isely@pobox.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'drivers/media')
-rw-r--r-- | drivers/media/video/pvrusb2/pvrusb2-fx2-cmd.h | 48 |
1 files changed, 24 insertions, 24 deletions
diff --git a/drivers/media/video/pvrusb2/pvrusb2-fx2-cmd.h b/drivers/media/video/pvrusb2/pvrusb2-fx2-cmd.h index a866c949243c..abaada31e66e 100644 --- a/drivers/media/video/pvrusb2/pvrusb2-fx2-cmd.h +++ b/drivers/media/video/pvrusb2/pvrusb2-fx2-cmd.h | |||
@@ -22,41 +22,41 @@ | |||
22 | #ifndef _PVRUSB2_FX2_CMD_H_ | 22 | #ifndef _PVRUSB2_FX2_CMD_H_ |
23 | #define _PVRUSB2_FX2_CMD_H_ | 23 | #define _PVRUSB2_FX2_CMD_H_ |
24 | 24 | ||
25 | #define FX2CMD_MEM_WRITE_DWORD 0x01 | 25 | #define FX2CMD_MEM_WRITE_DWORD 0x01u |
26 | #define FX2CMD_MEM_READ_DWORD 0x02 | 26 | #define FX2CMD_MEM_READ_DWORD 0x02u |
27 | 27 | ||
28 | #define FX2CMD_MEM_READ_64BYTES 0x28 | 28 | #define FX2CMD_MEM_READ_64BYTES 0x28u |
29 | 29 | ||
30 | #define FX2CMD_REG_WRITE 0x04 | 30 | #define FX2CMD_REG_WRITE 0x04u |
31 | #define FX2CMD_REG_READ 0x05 | 31 | #define FX2CMD_REG_READ 0x05u |
32 | #define FX2CMD_MEMSEL 0x06 | 32 | #define FX2CMD_MEMSEL 0x06u |
33 | 33 | ||
34 | #define FX2CMD_I2C_WRITE 0x08 | 34 | #define FX2CMD_I2C_WRITE 0x08u |
35 | #define FX2CMD_I2C_READ 0x09 | 35 | #define FX2CMD_I2C_READ 0x09u |
36 | 36 | ||
37 | #define FX2CMD_GET_USB_SPEED 0x0b | 37 | #define FX2CMD_GET_USB_SPEED 0x0bu |
38 | 38 | ||
39 | #define FX2CMD_STREAMING_ON 0x36 | 39 | #define FX2CMD_STREAMING_ON 0x36u |
40 | #define FX2CMD_STREAMING_OFF 0x37 | 40 | #define FX2CMD_STREAMING_OFF 0x37u |
41 | 41 | ||
42 | #define FX2CMD_FWPOST1 0x52 | 42 | #define FX2CMD_FWPOST1 0x52u |
43 | 43 | ||
44 | #define FX2CMD_POWER_OFF 0xdc | 44 | #define FX2CMD_POWER_OFF 0xdcu |
45 | #define FX2CMD_POWER_ON 0xde | 45 | #define FX2CMD_POWER_ON 0xdeu |
46 | 46 | ||
47 | #define FX2CMD_DEEP_RESET 0xdd | 47 | #define FX2CMD_DEEP_RESET 0xddu |
48 | 48 | ||
49 | #define FX2CMD_GET_EEPROM_ADDR 0xeb | 49 | #define FX2CMD_GET_EEPROM_ADDR 0xebu |
50 | #define FX2CMD_GET_IR_CODE 0xec | 50 | #define FX2CMD_GET_IR_CODE 0xecu |
51 | 51 | ||
52 | #define FX2CMD_HCW_DEMOD_RESETIN 0xf0 | 52 | #define FX2CMD_HCW_DEMOD_RESETIN 0xf0u |
53 | #define FX2CMD_HCW_DTV_STREAMING_ON 0xf1 | 53 | #define FX2CMD_HCW_DTV_STREAMING_ON 0xf1u |
54 | #define FX2CMD_HCW_DTV_STREAMING_OFF 0xf2 | 54 | #define FX2CMD_HCW_DTV_STREAMING_OFF 0xf2u |
55 | 55 | ||
56 | #define FX2CMD_ONAIR_DTV_STREAMING_ON 0xa0 | 56 | #define FX2CMD_ONAIR_DTV_STREAMING_ON 0xa0u |
57 | #define FX2CMD_ONAIR_DTV_STREAMING_OFF 0xa1 | 57 | #define FX2CMD_ONAIR_DTV_STREAMING_OFF 0xa1u |
58 | #define FX2CMD_ONAIR_DTV_POWER_ON 0xa2 | 58 | #define FX2CMD_ONAIR_DTV_POWER_ON 0xa2u |
59 | #define FX2CMD_ONAIR_DTV_POWER_OFF 0xa3 | 59 | #define FX2CMD_ONAIR_DTV_POWER_OFF 0xa3u |
60 | 60 | ||
61 | #endif /* _PVRUSB2_FX2_CMD_H_ */ | 61 | #endif /* _PVRUSB2_FX2_CMD_H_ */ |
62 | 62 | ||