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authorSri Deevi <Srinivasa.Deevi@conexant.com>2009-03-21 21:00:20 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2009-04-06 20:44:07 -0400
commitecc67d108d6ade14d79c8546f5db36613c780d59 (patch)
tree638c133624821d7f409fce13c1a71524d4ce6215 /drivers/media
parentb1196126b016d0f28a99c16b27c403d0ecac501a (diff)
V4L/DVB (11129): cx231xx: Use generic names for each device block
Signed-off-by: Srinivasa Deevi <srinivasa.deevi@conexant.com> Reviewed-by: Hans Verkuil <hverkuil@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media')
-rw-r--r--drivers/media/video/cx231xx/cx231xx-avcore.c1171
-rw-r--r--drivers/media/video/cx231xx/cx231xx-core.c16
-rw-r--r--drivers/media/video/cx231xx/cx231xx-pcb-cfg.h8
-rw-r--r--drivers/media/video/cx231xx/cx231xx-video.c48
-rw-r--r--drivers/media/video/cx231xx/cx231xx.h36
5 files changed, 538 insertions, 741 deletions
diff --git a/drivers/media/video/cx231xx/cx231xx-avcore.c b/drivers/media/video/cx231xx/cx231xx-avcore.c
index 226299d62d7e..1be3881be991 100644
--- a/drivers/media/video/cx231xx/cx231xx-avcore.c
+++ b/drivers/media/video/cx231xx/cx231xx-avcore.c
@@ -40,54 +40,77 @@
40#include "cx231xx.h" 40#include "cx231xx.h"
41 41
42/****************************************************************************** 42/******************************************************************************
43 * C O L I B R I - B L O C K C O N T R O L functions * 43 -: BLOCK ARRANGEMENT :-
44 I2S block ----------------------|
45 [I2S audio] |
46 |
47 Analog Front End --> Direct IF -|-> Cx25840 --> Audio
48 [video & audio] | [Audio]
49 |
50 |-> Cx25840 --> Video
51 [Video]
52
53*******************************************************************************/
54
55/******************************************************************************
56 * A F E - B L O C K C O N T R O L functions *
57 * [ANALOG FRONT END] *
44 ******************************************************************************/ 58 ******************************************************************************/
45int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count) 59static int afe_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
60{
61 return cx231xx_write_i2c_data(dev, AFE_DEVICE_ADDRESS,
62 saddr, 2, data, 1);
63}
64
65static int afe_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
66{
67 int status;
68 u32 temp = 0;
69
70 status = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
71 saddr, 2, &temp, 1);
72 *data = (u8) temp;
73 return status;
74}
75
76int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count)
46{ 77{
47 int status = 0; 78 int status = 0;
48 u8 temp = 0; 79 u8 temp = 0;
49 u32 colibri_power_status = 0; 80 u8 afe_power_status = 0;
50 int i = 0; 81 int i = 0;
51 82
52 /* super block initialize */ 83 /* super block initialize */
53 temp = (u8) (ref_count & 0xff); 84 temp = (u8) (ref_count & 0xff);
54 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 85 status = afe_write_byte(dev, SUP_BLK_TUNE2, temp);
55 SUP_BLK_TUNE2, 2, temp, 1);
56 if (status < 0) 86 if (status < 0)
57 return status; 87 return status;
58 88
59 status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, 89 status = afe_read_byte(dev, SUP_BLK_TUNE2, &afe_power_status);
60 SUP_BLK_TUNE2, 2,
61 &colibri_power_status, 1);
62 if (status < 0) 90 if (status < 0)
63 return status; 91 return status;
64 92
65 temp = (u8) ((ref_count & 0x300) >> 8); 93 temp = (u8) ((ref_count & 0x300) >> 8);
66 temp |= 0x40; 94 temp |= 0x40;
67 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 95 status = afe_write_byte(dev, SUP_BLK_TUNE1, temp);
68 SUP_BLK_TUNE1, 2, temp, 1);
69 if (status < 0) 96 if (status < 0)
70 return status; 97 return status;
71 98
72 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 99 status = afe_write_byte(dev, SUP_BLK_PLL2, 0x0f);
73 SUP_BLK_PLL2, 2, 0x0f, 1);
74 if (status < 0) 100 if (status < 0)
75 return status; 101 return status;
76 102
77 /* enable pll */ 103 /* enable pll */
78 while (colibri_power_status != 0x18) { 104 while (afe_power_status != 0x18) {
79 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 105 status = afe_write_byte(dev, SUP_BLK_PWRDN, 0x18);
80 SUP_BLK_PWRDN, 2, 0x18, 1);
81 if (status < 0) { 106 if (status < 0) {
82 cx231xx_info( 107 cx231xx_info(
83 ": Init Super Block failed in send cmd\n"); 108 ": Init Super Block failed in send cmd\n");
84 break; 109 break;
85 } 110 }
86 111
87 status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, 112 status = afe_read_byte(dev, SUP_BLK_PWRDN, &afe_power_status);
88 SUP_BLK_PWRDN, 2, 113 afe_power_status &= 0xff;
89 &colibri_power_status, 1);
90 colibri_power_status &= 0xff;
91 if (status < 0) { 114 if (status < 0) {
92 cx231xx_info( 115 cx231xx_info(
93 ": Init Super Block failed in receive cmd\n"); 116 ": Init Super Block failed in receive cmd\n");
@@ -106,101 +129,75 @@ int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count)
106 return status; 129 return status;
107 130
108 /* start tuning filter */ 131 /* start tuning filter */
109 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 132 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x40);
110 SUP_BLK_TUNE3, 2, 0x40, 1);
111 if (status < 0) 133 if (status < 0)
112 return status; 134 return status;
113 135
114 msleep(5); 136 msleep(5);
115 137
116 /* exit tuning */ 138 /* exit tuning */
117 status = 139 status = afe_write_byte(dev, SUP_BLK_TUNE3, 0x00);
118 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, SUP_BLK_TUNE3,
119 2, 0x00, 1);
120 140
121 return status; 141 return status;
122} 142}
123 143
124int cx231xx_colibri_init_channels(struct cx231xx *dev) 144int cx231xx_afe_init_channels(struct cx231xx *dev)
125{ 145{
126 int status = 0; 146 int status = 0;
127 147
128 /* power up all 3 channels, clear pd_buffer */ 148 /* power up all 3 channels, clear pd_buffer */
129 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 149 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1, 0x00);
130 ADC_PWRDN_CLAMP_CH1, 2, 0x00, 1); 150 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, 0x00);
131 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 151 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3, 0x00);
132 ADC_PWRDN_CLAMP_CH2, 2, 0x00, 1);
133 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
134 ADC_PWRDN_CLAMP_CH3, 2, 0x00, 1);
135 152
136 /* Enable quantizer calibration */ 153 /* Enable quantizer calibration */
137 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 154 status = afe_write_byte(dev, ADC_COM_QUANT, 0x02);
138 ADC_COM_QUANT, 2, 0x02, 1);
139 155
140 /* channel initialize, force modulator (fb) reset */ 156 /* channel initialize, force modulator (fb) reset */
141 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 157 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x17);
142 ADC_FB_FRCRST_CH1, 2, 0x17, 1); 158 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x17);
143 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 159 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x17);
144 ADC_FB_FRCRST_CH2, 2, 0x17, 1);
145 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
146 ADC_FB_FRCRST_CH3, 2, 0x17, 1);
147 160
148 /* start quantilizer calibration */ 161 /* start quantilizer calibration */
149 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 162 status = afe_write_byte(dev, ADC_CAL_ATEST_CH1, 0x10);
150 ADC_CAL_ATEST_CH1, 2, 0x10, 1); 163 status = afe_write_byte(dev, ADC_CAL_ATEST_CH2, 0x10);
151 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 164 status = afe_write_byte(dev, ADC_CAL_ATEST_CH3, 0x10);
152 ADC_CAL_ATEST_CH2, 2, 0x10, 1);
153 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
154 ADC_CAL_ATEST_CH3, 2, 0x10, 1);
155 msleep(5); 165 msleep(5);
156 166
157 /* exit modulator (fb) reset */ 167 /* exit modulator (fb) reset */
158 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 168 status = afe_write_byte(dev, ADC_FB_FRCRST_CH1, 0x07);
159 ADC_FB_FRCRST_CH1, 2, 0x07, 1); 169 status = afe_write_byte(dev, ADC_FB_FRCRST_CH2, 0x07);
160 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 170 status = afe_write_byte(dev, ADC_FB_FRCRST_CH3, 0x07);
161 ADC_FB_FRCRST_CH2, 2, 0x07, 1);
162 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
163 ADC_FB_FRCRST_CH3, 2, 0x07, 1);
164 171
165 /* enable the pre_clamp in each channel for single-ended input */ 172 /* enable the pre_clamp in each channel for single-ended input */
166 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 173 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH1, 0xf0);
167 ADC_NTF_PRECLMP_EN_CH1, 2, 0xf0, 1); 174 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH2, 0xf0);
168 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 175 status = afe_write_byte(dev, ADC_NTF_PRECLMP_EN_CH3, 0xf0);
169 ADC_NTF_PRECLMP_EN_CH2, 2, 0xf0, 1);
170 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
171 ADC_NTF_PRECLMP_EN_CH3, 2, 0xf0, 1);
172 176
173 /* use diode instead of resistor, so set term_en to 0, res_en to 0 */ 177 /* use diode instead of resistor, so set term_en to 0, res_en to 0 */
174 status = cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8, 178 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
175 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00); 179 ADC_QGAIN_RES_TRM_CH1, 3, 7, 0x00);
176 status = cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8, 180 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
177 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00); 181 ADC_QGAIN_RES_TRM_CH2, 3, 7, 0x00);
178 status = cx231xx_reg_mask_write(dev, Colibri_DEVICE_ADDRESS, 8, 182 status = cx231xx_reg_mask_write(dev, AFE_DEVICE_ADDRESS, 8,
179 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00); 183 ADC_QGAIN_RES_TRM_CH3, 3, 7, 0x00);
180 184
181 /* dynamic element matching off */ 185 /* dynamic element matching off */
182 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 186 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH1, 0x03);
183 ADC_DCSERVO_DEM_CH1, 2, 0x03, 1); 187 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH2, 0x03);
184 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 188 status = afe_write_byte(dev, ADC_DCSERVO_DEM_CH3, 0x03);
185 ADC_DCSERVO_DEM_CH2, 2, 0x03, 1);
186 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
187 ADC_DCSERVO_DEM_CH3, 2, 0x03, 1);
188 189
189 return status; 190 return status;
190} 191}
191 192
192int cx231xx_colibri_setup_AFE_for_baseband(struct cx231xx *dev) 193int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev)
193{ 194{
194 u32 c_value = 0; 195 u8 c_value = 0;
195 int status = 0; 196 int status = 0;
196 197
197 status = 198 status = afe_read_byte(dev, ADC_PWRDN_CLAMP_CH2, &c_value);
198 cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
199 ADC_PWRDN_CLAMP_CH2, 2, &c_value, 1);
200 c_value &= (~(0x50)); 199 c_value &= (~(0x50));
201 status = 200 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2, c_value);
202 cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
203 ADC_PWRDN_CLAMP_CH2, 2, c_value, 1);
204 201
205 return status; 202 return status;
206} 203}
@@ -214,52 +211,44 @@ int cx231xx_colibri_setup_AFE_for_baseband(struct cx231xx *dev)
214 channel 2 ----- pin 5 to pin8(in reg is 5-8) 211 channel 2 ----- pin 5 to pin8(in reg is 5-8)
215 channel 3 ----- pin 9 to pin 12(in reg is 9-11) 212 channel 3 ----- pin 9 to pin 12(in reg is 9-11)
216*/ 213*/
217int cx231xx_colibri_set_input_mux(struct cx231xx *dev, u32 input_mux) 214int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux)
218{ 215{
219 u8 ch1_setting = (u8) input_mux; 216 u8 ch1_setting = (u8) input_mux;
220 u8 ch2_setting = (u8) (input_mux >> 8); 217 u8 ch2_setting = (u8) (input_mux >> 8);
221 u8 ch3_setting = (u8) (input_mux >> 16); 218 u8 ch3_setting = (u8) (input_mux >> 16);
222 int status = 0; 219 int status = 0;
223 u32 value = 0; 220 u8 value = 0;
224 221
225 if (ch1_setting != 0) { 222 if (ch1_setting != 0) {
226 status = 223 status = afe_read_byte(dev, ADC_INPUT_CH1, &value);
227 cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
228 ADC_INPUT_CH1, 2, &value, 1);
229 value &= (!INPUT_SEL_MASK); 224 value &= (!INPUT_SEL_MASK);
230 value |= (ch1_setting - 1) << 4; 225 value |= (ch1_setting - 1) << 4;
231 value &= 0xff; 226 value &= 0xff;
232 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 227 status = afe_write_byte(dev, ADC_INPUT_CH1, value);
233 ADC_INPUT_CH1, 2, value, 1);
234 } 228 }
235 229
236 if (ch2_setting != 0) { 230 if (ch2_setting != 0) {
237 status = 231 status = afe_read_byte(dev, ADC_INPUT_CH2, &value);
238 cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
239 ADC_INPUT_CH2, 2, &value, 1);
240 value &= (!INPUT_SEL_MASK); 232 value &= (!INPUT_SEL_MASK);
241 value |= (ch2_setting - 1) << 4; 233 value |= (ch2_setting - 1) << 4;
242 value &= 0xff; 234 value &= 0xff;
243 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 235 status = afe_write_byte(dev, ADC_INPUT_CH2, value);
244 ADC_INPUT_CH2, 2, value, 1);
245 } 236 }
246 237
247 /* For ch3_setting, the value to put in the register is 238 /* For ch3_setting, the value to put in the register is
248 7 less than the input number */ 239 7 less than the input number */
249 if (ch3_setting != 0) { 240 if (ch3_setting != 0) {
250 status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, 241 status = afe_read_byte(dev, ADC_INPUT_CH3, &value);
251 ADC_INPUT_CH3, 2, &value, 1);
252 value &= (!INPUT_SEL_MASK); 242 value &= (!INPUT_SEL_MASK);
253 value |= (ch3_setting - 1) << 4; 243 value |= (ch3_setting - 1) << 4;
254 value &= 0xff; 244 value &= 0xff;
255 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 245 status = afe_write_byte(dev, ADC_INPUT_CH3, value);
256 ADC_INPUT_CH3, 2, value, 1);
257 } 246 }
258 247
259 return status; 248 return status;
260} 249}
261 250
262int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode) 251int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
263{ 252{
264 int status = 0; 253 int status = 0;
265 254
@@ -273,7 +262,7 @@ int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
273 /* SetupAFEforLowIF(); */ 262 /* SetupAFEforLowIF(); */
274 break; 263 break;
275 case AFE_MODE_BASEBAND: 264 case AFE_MODE_BASEBAND:
276 status = cx231xx_colibri_setup_AFE_for_baseband(dev); 265 status = cx231xx_afe_setup_AFE_for_baseband(dev);
277 break; 266 break;
278 case AFE_MODE_EU_HI_IF: 267 case AFE_MODE_EU_HI_IF:
279 /* SetupAFEforEuHiIF(); */ 268 /* SetupAFEforEuHiIF(); */
@@ -286,110 +275,76 @@ int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
286 break; 275 break;
287 } 276 }
288 277
289 if ((mode != dev->colibri_mode) && 278 if ((mode != dev->afe_mode) &&
290 (dev->video_input == CX231XX_VMUX_TELEVISION)) 279 (dev->video_input == CX231XX_VMUX_TELEVISION))
291 status = cx231xx_colibri_adjust_ref_count(dev, 280 status = cx231xx_afe_adjust_ref_count(dev,
292 CX231XX_VMUX_TELEVISION); 281 CX231XX_VMUX_TELEVISION);
293 282
294 dev->colibri_mode = mode; 283 dev->afe_mode = mode;
295 284
296 return status; 285 return status;
297} 286}
298 287
299int cx231xx_colibri_update_power_control(struct cx231xx *dev, 288int cx231xx_afe_update_power_control(struct cx231xx *dev,
300 enum AV_MODE avmode) 289 enum AV_MODE avmode)
301{ 290{
302 u32 colibri_power_status = 0; 291 u8 afe_power_status = 0;
303 int status = 0; 292 int status = 0;
304 293
305 switch (dev->model) { 294 switch (dev->model) {
306 case CX231XX_BOARD_CNXT_RDE_250: 295 case CX231XX_BOARD_CNXT_RDE_250:
307 case CX231XX_BOARD_CNXT_RDU_250: 296 case CX231XX_BOARD_CNXT_RDU_250:
308 if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 297 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
309 while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS | 298 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
310 FLD_PWRDN_ENABLE_PLL)) { 299 FLD_PWRDN_ENABLE_PLL)) {
311 status = cx231xx_write_i2c_data(dev, 300 status = afe_write_byte(dev, SUP_BLK_PWRDN,
312 Colibri_DEVICE_ADDRESS,
313 SUP_BLK_PWRDN, 2,
314 FLD_PWRDN_TUNING_BIAS | 301 FLD_PWRDN_TUNING_BIAS |
315 FLD_PWRDN_ENABLE_PLL, 302 FLD_PWRDN_ENABLE_PLL);
316 1); 303 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
317 status |= cx231xx_read_i2c_data(dev, 304 &afe_power_status);
318 Colibri_DEVICE_ADDRESS,
319 SUP_BLK_PWRDN, 2,
320 &colibri_power_status,
321 1);
322 if (status < 0) 305 if (status < 0)
323 break; 306 break;
324 } 307 }
325 308
326 status = cx231xx_write_i2c_data(dev, 309 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
327 Colibri_DEVICE_ADDRESS, 310 0x00);
328 ADC_PWRDN_CLAMP_CH1, 2, 0x00, 311 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
329 1); 312 0x00);
330 status |= cx231xx_write_i2c_data(dev, 313 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
331 Colibri_DEVICE_ADDRESS, 314 0x00);
332 ADC_PWRDN_CLAMP_CH2, 2, 0x00,
333 1);
334 status |= cx231xx_write_i2c_data(dev,
335 Colibri_DEVICE_ADDRESS,
336 ADC_PWRDN_CLAMP_CH3, 2, 0x00,
337 1);
338 } else if (avmode == POLARIS_AVMODE_DIGITAL) { 315 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
339 status = cx231xx_write_i2c_data(dev, 316 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
340 Colibri_DEVICE_ADDRESS, 317 0x70);
341 ADC_PWRDN_CLAMP_CH1, 2, 0x70, 318 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
342 1); 319 0x70);
343 status |= cx231xx_write_i2c_data(dev, 320 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
344 Colibri_DEVICE_ADDRESS, 321 0x70);
345 ADC_PWRDN_CLAMP_CH2, 2, 0x70, 322
346 1); 323 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
347 status |= cx231xx_write_i2c_data(dev, 324 &afe_power_status);
348 Colibri_DEVICE_ADDRESS, 325 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
349 ADC_PWRDN_CLAMP_CH3, 2, 0x70,
350 1);
351
352 status |= cx231xx_read_i2c_data(dev,
353 Colibri_DEVICE_ADDRESS,
354 SUP_BLK_PWRDN, 2,
355 &colibri_power_status, 1);
356 colibri_power_status |= FLD_PWRDN_PD_BANDGAP |
357 FLD_PWRDN_PD_BIAS | 326 FLD_PWRDN_PD_BIAS |
358 FLD_PWRDN_PD_TUNECK; 327 FLD_PWRDN_PD_TUNECK;
359 status |= cx231xx_write_i2c_data(dev, 328 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
360 Colibri_DEVICE_ADDRESS, 329 afe_power_status);
361 SUP_BLK_PWRDN, 2,
362 colibri_power_status, 1);
363 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 330 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
364 while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS | 331 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
365 FLD_PWRDN_ENABLE_PLL)) { 332 FLD_PWRDN_ENABLE_PLL)) {
366 status = cx231xx_write_i2c_data(dev, 333 status = afe_write_byte(dev, SUP_BLK_PWRDN,
367 Colibri_DEVICE_ADDRESS,
368 SUP_BLK_PWRDN, 2,
369 FLD_PWRDN_TUNING_BIAS | 334 FLD_PWRDN_TUNING_BIAS |
370 FLD_PWRDN_ENABLE_PLL, 335 FLD_PWRDN_ENABLE_PLL);
371 1); 336 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
372 status |= cx231xx_read_i2c_data(dev, 337 &afe_power_status);
373 Colibri_DEVICE_ADDRESS,
374 SUP_BLK_PWRDN, 2,
375 &colibri_power_status,
376 1);
377 if (status < 0) 338 if (status < 0)
378 break; 339 break;
379 } 340 }
380 341
381 status |= cx231xx_write_i2c_data(dev, 342 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
382 Colibri_DEVICE_ADDRESS, 343 0x00);
383 ADC_PWRDN_CLAMP_CH1, 2, 0x00, 344 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
384 1); 345 0x00);
385 status |= cx231xx_write_i2c_data(dev, 346 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
386 Colibri_DEVICE_ADDRESS, 347 0x00);
387 ADC_PWRDN_CLAMP_CH2, 2, 0x00,
388 1);
389 status |= cx231xx_write_i2c_data(dev,
390 Colibri_DEVICE_ADDRESS,
391 ADC_PWRDN_CLAMP_CH3, 2, 0x00,
392 1);
393 } else { 348 } else {
394 cx231xx_info("Invalid AV mode input\n"); 349 cx231xx_info("Invalid AV mode input\n");
395 status = -1; 350 status = -1;
@@ -397,92 +352,56 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev,
397 break; 352 break;
398 default: 353 default:
399 if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 354 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
400 while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS | 355 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
401 FLD_PWRDN_ENABLE_PLL)) { 356 FLD_PWRDN_ENABLE_PLL)) {
402 status = cx231xx_write_i2c_data(dev, 357 status = afe_write_byte(dev, SUP_BLK_PWRDN,
403 Colibri_DEVICE_ADDRESS,
404 SUP_BLK_PWRDN, 2,
405 FLD_PWRDN_TUNING_BIAS | 358 FLD_PWRDN_TUNING_BIAS |
406 FLD_PWRDN_ENABLE_PLL, 359 FLD_PWRDN_ENABLE_PLL);
407 1); 360 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
408 status |= cx231xx_read_i2c_data(dev, 361 &afe_power_status);
409 Colibri_DEVICE_ADDRESS,
410 SUP_BLK_PWRDN, 2,
411 &colibri_power_status,
412 1);
413 if (status < 0) 362 if (status < 0)
414 break; 363 break;
415 } 364 }
416 365
417 status |= cx231xx_write_i2c_data(dev, 366 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
418 Colibri_DEVICE_ADDRESS, 367 0x40);
419 ADC_PWRDN_CLAMP_CH1, 2, 368 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
420 0x40, 1); 369 0x40);
421 status |= cx231xx_write_i2c_data(dev, 370 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
422 Colibri_DEVICE_ADDRESS, 371 0x00);
423 ADC_PWRDN_CLAMP_CH2, 2,
424 0x40, 1);
425 status |= cx231xx_write_i2c_data(dev,
426 Colibri_DEVICE_ADDRESS,
427 ADC_PWRDN_CLAMP_CH3, 2,
428 0x00, 1);
429 } else if (avmode == POLARIS_AVMODE_DIGITAL) { 372 } else if (avmode == POLARIS_AVMODE_DIGITAL) {
430 status = cx231xx_write_i2c_data(dev, 373 status = afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
431 Colibri_DEVICE_ADDRESS, 374 0x70);
432 ADC_PWRDN_CLAMP_CH1, 2, 375 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
433 0x70, 1); 376 0x70);
434 status |= cx231xx_write_i2c_data(dev, 377 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
435 Colibri_DEVICE_ADDRESS, 378 0x70);
436 ADC_PWRDN_CLAMP_CH2, 2, 379
437 0x70, 1); 380 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
438 status |= cx231xx_write_i2c_data(dev, 381 &afe_power_status);
439 Colibri_DEVICE_ADDRESS, 382 afe_power_status |= FLD_PWRDN_PD_BANDGAP |
440 ADC_PWRDN_CLAMP_CH3, 2,
441 0x70, 1);
442
443 status |= cx231xx_read_i2c_data(dev,
444 Colibri_DEVICE_ADDRESS,
445 SUP_BLK_PWRDN, 2,
446 &colibri_power_status,
447 1);
448 colibri_power_status |= FLD_PWRDN_PD_BANDGAP |
449 FLD_PWRDN_PD_BIAS | 383 FLD_PWRDN_PD_BIAS |
450 FLD_PWRDN_PD_TUNECK; 384 FLD_PWRDN_PD_TUNECK;
451 status |= cx231xx_write_i2c_data(dev, 385 status |= afe_write_byte(dev, SUP_BLK_PWRDN,
452 Colibri_DEVICE_ADDRESS, 386 afe_power_status);
453 SUP_BLK_PWRDN, 2,
454 colibri_power_status,
455 1);
456 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 387 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
457 while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS | 388 while (afe_power_status != (FLD_PWRDN_TUNING_BIAS |
458 FLD_PWRDN_ENABLE_PLL)) { 389 FLD_PWRDN_ENABLE_PLL)) {
459 status = cx231xx_write_i2c_data(dev, 390 status = afe_write_byte(dev, SUP_BLK_PWRDN,
460 Colibri_DEVICE_ADDRESS,
461 SUP_BLK_PWRDN, 2,
462 FLD_PWRDN_TUNING_BIAS | 391 FLD_PWRDN_TUNING_BIAS |
463 FLD_PWRDN_ENABLE_PLL, 392 FLD_PWRDN_ENABLE_PLL);
464 1); 393 status |= afe_read_byte(dev, SUP_BLK_PWRDN,
465 status |= cx231xx_read_i2c_data(dev, 394 &afe_power_status);
466 Colibri_DEVICE_ADDRESS,
467 SUP_BLK_PWRDN, 2,
468 &colibri_power_status,
469 1);
470 if (status < 0) 395 if (status < 0)
471 break; 396 break;
472 } 397 }
473 398
474 status |= cx231xx_write_i2c_data(dev, 399 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH1,
475 Colibri_DEVICE_ADDRESS, 400 0x00);
476 ADC_PWRDN_CLAMP_CH1, 2, 401 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH2,
477 0x00, 1); 402 0x00);
478 status |= cx231xx_write_i2c_data(dev, 403 status |= afe_write_byte(dev, ADC_PWRDN_CLAMP_CH3,
479 Colibri_DEVICE_ADDRESS, 404 0x40);
480 ADC_PWRDN_CLAMP_CH2, 2,
481 0x00, 1);
482 status |= cx231xx_write_i2c_data(dev,
483 Colibri_DEVICE_ADDRESS,
484 ADC_PWRDN_CLAMP_CH3, 2,
485 0x40, 1);
486 } else { 405 } else {
487 cx231xx_info("Invalid AV mode input\n"); 406 cx231xx_info("Invalid AV mode input\n");
488 status = -1; 407 status = -1;
@@ -492,48 +411,44 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev,
492 return status; 411 return status;
493} 412}
494 413
495int cx231xx_colibri_adjust_ref_count(struct cx231xx *dev, u32 video_input) 414int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input)
496{ 415{
497 u32 input_mode = 0; 416 u8 input_mode = 0;
498 u32 ntf_mode = 0; 417 u8 ntf_mode = 0;
499 int status = 0; 418 int status = 0;
500 419
501 dev->video_input = video_input; 420 dev->video_input = video_input;
502 421
503 if (video_input == CX231XX_VMUX_TELEVISION) { 422 if (video_input == CX231XX_VMUX_TELEVISION) {
504 status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, 423 status = afe_read_byte(dev, ADC_INPUT_CH3, &input_mode);
505 ADC_INPUT_CH3, 2, &input_mode, 1); 424 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH3,
506 status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, 425 &ntf_mode);
507 ADC_NTF_PRECLMP_EN_CH3, 2, &ntf_mode,
508 1);
509 } else { 426 } else {
510 status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, 427 status = afe_read_byte(dev, ADC_INPUT_CH1, &input_mode);
511 ADC_INPUT_CH1, 2, &input_mode, 1); 428 status = afe_read_byte(dev, ADC_NTF_PRECLMP_EN_CH1,
512 status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, 429 &ntf_mode);
513 ADC_NTF_PRECLMP_EN_CH1, 2, &ntf_mode,
514 1);
515 } 430 }
516 431
517 input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1); 432 input_mode = (ntf_mode & 0x3) | ((input_mode & 0x6) << 1);
518 433
519 switch (input_mode) { 434 switch (input_mode) {
520 case SINGLE_ENDED: 435 case SINGLE_ENDED:
521 dev->colibri_ref_count = 0x23C; 436 dev->afe_ref_count = 0x23C;
522 break; 437 break;
523 case LOW_IF: 438 case LOW_IF:
524 dev->colibri_ref_count = 0x24C; 439 dev->afe_ref_count = 0x24C;
525 break; 440 break;
526 case EU_IF: 441 case EU_IF:
527 dev->colibri_ref_count = 0x258; 442 dev->afe_ref_count = 0x258;
528 break; 443 break;
529 case US_IF: 444 case US_IF:
530 dev->colibri_ref_count = 0x260; 445 dev->afe_ref_count = 0x260;
531 break; 446 break;
532 default: 447 default:
533 break; 448 break;
534 } 449 }
535 450
536 status = cx231xx_colibri_init_super_block(dev, dev->colibri_ref_count); 451 status = cx231xx_afe_init_super_block(dev, dev->afe_ref_count);
537 452
538 return status; 453 return status;
539} 454}
@@ -541,6 +456,35 @@ int cx231xx_colibri_adjust_ref_count(struct cx231xx *dev, u32 video_input)
541/****************************************************************************** 456/******************************************************************************
542 * V I D E O / A U D I O D E C O D E R C O N T R O L functions * 457 * V I D E O / A U D I O D E C O D E R C O N T R O L functions *
543 ******************************************************************************/ 458 ******************************************************************************/
459static int vid_blk_write_byte(struct cx231xx *dev, u16 saddr, u8 data)
460{
461 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
462 saddr, 2, data, 1);
463}
464
465static int vid_blk_read_byte(struct cx231xx *dev, u16 saddr, u8 *data)
466{
467 int status;
468 u32 temp = 0;
469
470 status = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
471 saddr, 2, &temp, 1);
472 *data = (u8) temp;
473 return status;
474}
475
476static int vid_blk_write_word(struct cx231xx *dev, u16 saddr, u32 data)
477{
478 return cx231xx_write_i2c_data(dev, VID_BLK_I2C_ADDRESS,
479 saddr, 2, data, 4);
480}
481
482static int vid_blk_read_word(struct cx231xx *dev, u16 saddr, u32 *data)
483{
484 return cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
485 saddr, 2, data, 4);
486}
487
544int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) 488int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
545{ 489{
546 int status = 0; 490 int status = 0;
@@ -601,29 +545,27 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev,
601 u32 value = 0; 545 u32 value = 0;
602 546
603 if (pin_type != dev->video_input) { 547 if (pin_type != dev->video_input) {
604 status = cx231xx_colibri_adjust_ref_count(dev, pin_type); 548 status = cx231xx_afe_adjust_ref_count(dev, pin_type);
605 if (status < 0) { 549 if (status < 0) {
606 cx231xx_errdev("%s: adjust_ref_count :Failed to set" 550 cx231xx_errdev("%s: adjust_ref_count :Failed to set"
607 "Colibri input mux - errCode [%d]!\n", 551 "AFE input mux - errCode [%d]!\n",
608 __func__, status); 552 __func__, status);
609 return status; 553 return status;
610 } 554 }
611 } 555 }
612 556
613 /* call colibri block to set video inputs */ 557 /* call afe block to set video inputs */
614 status = cx231xx_colibri_set_input_mux(dev, input); 558 status = cx231xx_afe_set_input_mux(dev, input);
615 if (status < 0) { 559 if (status < 0) {
616 cx231xx_errdev("%s: set_input_mux :Failed to set" 560 cx231xx_errdev("%s: set_input_mux :Failed to set"
617 " Colibri input mux - errCode [%d]!\n", 561 " AFE input mux - errCode [%d]!\n",
618 __func__, status); 562 __func__, status);
619 return status; 563 return status;
620 } 564 }
621 565
622 switch (pin_type) { 566 switch (pin_type) {
623 case CX231XX_VMUX_COMPOSITE1: 567 case CX231XX_VMUX_COMPOSITE1:
624 status = cx231xx_read_i2c_data(dev, 568 status = vid_blk_read_word(dev, AFE_CTRL, &value);
625 HAMMERHEAD_I2C_ADDRESS,
626 AFE_CTRL, 2, &value, 4);
627 value |= (0 << 13) | (1 << 4); 569 value |= (0 << 13) | (1 << 4);
628 value &= ~(1 << 5); 570 value &= ~(1 << 5);
629 571
@@ -631,18 +573,15 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev,
631 value &= (~(0x1ff8000)); 573 value &= (~(0x1ff8000));
632 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ 574 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
633 value |= 0x1000000; 575 value |= 0x1000000;
634 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 576 status = vid_blk_write_word(dev, AFE_CTRL, value);
635 AFE_CTRL, 2, value, 4);
636 577
637 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 578 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
638 OUT_CTRL1, 2, &value, 4);
639 value |= (1 << 7); 579 value |= (1 << 7);
640 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 580 status = vid_blk_write_word(dev, OUT_CTRL1, value);
641 OUT_CTRL1, 2, value, 4);
642 581
643 /* Set vip 1.1 output mode */ 582 /* Set vip 1.1 output mode */
644 status = cx231xx_read_modify_write_i2c_dword(dev, 583 status = cx231xx_read_modify_write_i2c_dword(dev,
645 HAMMERHEAD_I2C_ADDRESS, 584 VID_BLK_I2C_ADDRESS,
646 OUT_CTRL1, 585 OUT_CTRL1,
647 FLD_OUT_MODE, 586 FLD_OUT_MODE,
648 OUT_MODE_VIP11); 587 OUT_MODE_VIP11);
@@ -657,8 +596,7 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev,
657 } 596 }
658 597
659 /* Read the DFE_CTRL1 register */ 598 /* Read the DFE_CTRL1 register */
660 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 599 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
661 DFE_CTRL1, 2, &value, 4);
662 600
663 /* enable the VBI_GATE_EN */ 601 /* enable the VBI_GATE_EN */
664 value |= FLD_VBI_GATE_EN; 602 value |= FLD_VBI_GATE_EN;
@@ -667,35 +605,31 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev,
667 value |= FLD_VGA_AUTO_EN; 605 value |= FLD_VGA_AUTO_EN;
668 606
669 /* Write it back */ 607 /* Write it back */
670 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 608 status = vid_blk_write_word(dev, DFE_CTRL1, value);
671 DFE_CTRL1, 2, value, 4);
672 609
673 /* Disable auto config of registers */ 610 /* Disable auto config of registers */
674 status = cx231xx_read_modify_write_i2c_dword(dev, 611 status = cx231xx_read_modify_write_i2c_dword(dev,
675 HAMMERHEAD_I2C_ADDRESS, 612 VID_BLK_I2C_ADDRESS,
676 MODE_CTRL, FLD_ACFG_DIS, 613 MODE_CTRL, FLD_ACFG_DIS,
677 cx231xx_set_field(FLD_ACFG_DIS, 1)); 614 cx231xx_set_field(FLD_ACFG_DIS, 1));
678 615
679 /* Set CVBS input mode */ 616 /* Set CVBS input mode */
680 status = cx231xx_read_modify_write_i2c_dword(dev, 617 status = cx231xx_read_modify_write_i2c_dword(dev,
681 HAMMERHEAD_I2C_ADDRESS, 618 VID_BLK_I2C_ADDRESS,
682 MODE_CTRL, FLD_INPUT_MODE, 619 MODE_CTRL, FLD_INPUT_MODE,
683 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0)); 620 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_CVBS_0));
684 break; 621 break;
685 case CX231XX_VMUX_SVIDEO: 622 case CX231XX_VMUX_SVIDEO:
686 /* Disable the use of DIF */ 623 /* Disable the use of DIF */
687 624
688 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 625 status = vid_blk_read_word(dev, AFE_CTRL, &value);
689 AFE_CTRL, 2, &value, 4);
690 626
691 /* set [24:23] [22:15] to 0 */ 627 /* set [24:23] [22:15] to 0 */
692 value &= (~(0x1ff8000)); 628 value &= (~(0x1ff8000));
693 /* set FUNC_MODE[24:23] = 2 629 /* set FUNC_MODE[24:23] = 2
694 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */ 630 IF_MOD[22:15] = 0 DCR_BYP_CH2[4:4] = 1; */
695 value |= 0x1000010; 631 value |= 0x1000010;
696 status = cx231xx_write_i2c_data(dev, 632 status = vid_blk_write_word(dev, AFE_CTRL, value);
697 HAMMERHEAD_I2C_ADDRESS,
698 AFE_CTRL, 2, value, 4);
699 633
700 /* Tell DIF object to go to baseband mode */ 634 /* Tell DIF object to go to baseband mode */
701 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND); 635 status = cx231xx_dif_set_standard(dev, DIF_USE_BASEBAND);
@@ -707,9 +641,7 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev,
707 } 641 }
708 642
709 /* Read the DFE_CTRL1 register */ 643 /* Read the DFE_CTRL1 register */
710 status = cx231xx_read_i2c_data(dev, 644 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
711 HAMMERHEAD_I2C_ADDRESS,
712 DFE_CTRL1, 2, &value, 4);
713 645
714 /* enable the VBI_GATE_EN */ 646 /* enable the VBI_GATE_EN */
715 value |= FLD_VBI_GATE_EN; 647 value |= FLD_VBI_GATE_EN;
@@ -718,27 +650,23 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev,
718 value |= FLD_VGA_AUTO_EN; 650 value |= FLD_VGA_AUTO_EN;
719 651
720 /* Write it back */ 652 /* Write it back */
721 status = cx231xx_write_i2c_data(dev, 653 status = vid_blk_write_word(dev, DFE_CTRL1, value);
722 HAMMERHEAD_I2C_ADDRESS,
723 DFE_CTRL1, 2, value, 4);
724 654
725 /* Disable auto config of registers */ 655 /* Disable auto config of registers */
726 status = cx231xx_read_modify_write_i2c_dword(dev, 656 status = cx231xx_read_modify_write_i2c_dword(dev,
727 HAMMERHEAD_I2C_ADDRESS, 657 VID_BLK_I2C_ADDRESS,
728 MODE_CTRL, FLD_ACFG_DIS, 658 MODE_CTRL, FLD_ACFG_DIS,
729 cx231xx_set_field(FLD_ACFG_DIS, 1)); 659 cx231xx_set_field(FLD_ACFG_DIS, 1));
730 660
731 /* Set YC input mode */ 661 /* Set YC input mode */
732 status = cx231xx_read_modify_write_i2c_dword(dev, 662 status = cx231xx_read_modify_write_i2c_dword(dev,
733 HAMMERHEAD_I2C_ADDRESS, 663 VID_BLK_I2C_ADDRESS,
734 MODE_CTRL, 664 MODE_CTRL,
735 FLD_INPUT_MODE, 665 FLD_INPUT_MODE,
736 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1)); 666 cx231xx_set_field(FLD_INPUT_MODE, INPUT_MODE_YC_1));
737 667
738 /* Chroma to ADC2 */ 668 /* Chroma to ADC2 */
739 status = cx231xx_read_i2c_data(dev, 669 status = vid_blk_read_word(dev, AFE_CTRL, &value);
740 HAMMERHEAD_I2C_ADDRESS,
741 AFE_CTRL, 2, &value, 4);
742 value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */ 670 value |= FLD_CHROMA_IN_SEL; /* set the chroma in select */
743 671
744 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8) 672 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8)
@@ -746,11 +674,9 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev,
746 rather than audio. Only one of the two will be in use. */ 674 rather than audio. Only one of the two will be in use. */
747 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3); 675 value &= ~(FLD_VGA_SEL_CH2 | FLD_VGA_SEL_CH3);
748 676
749 status = cx231xx_write_i2c_data(dev, 677 status = vid_blk_write_word(dev, AFE_CTRL, value);
750 HAMMERHEAD_I2C_ADDRESS,
751 AFE_CTRL, 2, value, 4);
752 678
753 status = cx231xx_colibri_set_mode(dev, AFE_MODE_BASEBAND); 679 status = cx231xx_afe_set_mode(dev, AFE_MODE_BASEBAND);
754 break; 680 break;
755 case CX231XX_VMUX_TELEVISION: 681 case CX231XX_VMUX_TELEVISION:
756 case CX231XX_VMUX_CABLE: 682 case CX231XX_VMUX_CABLE:
@@ -760,10 +686,7 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev,
760 case CX231XX_BOARD_CNXT_RDU_250: 686 case CX231XX_BOARD_CNXT_RDU_250:
761 /* Disable the use of DIF */ 687 /* Disable the use of DIF */
762 688
763 status = cx231xx_read_i2c_data(dev, 689 status = vid_blk_read_word(dev, AFE_CTRL, &value);
764 HAMMERHEAD_I2C_ADDRESS,
765 AFE_CTRL, 2,
766 &value, 4);
767 value |= (0 << 13) | (1 << 4); 690 value |= (0 << 13) | (1 << 4);
768 value &= ~(1 << 5); 691 value &= ~(1 << 5);
769 692
@@ -771,24 +694,15 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev,
771 value &= (~(0x1FF8000)); 694 value &= (~(0x1FF8000));
772 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */ 695 /* set FUNC_MODE[24:23] = 2 IF_MOD[22:15] = 0 */
773 value |= 0x1000000; 696 value |= 0x1000000;
774 status = cx231xx_write_i2c_data(dev, 697 status = vid_blk_write_word(dev, AFE_CTRL, value);
775 HAMMERHEAD_I2C_ADDRESS, 698
776 AFE_CTRL, 2, 699 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
777 value, 4);
778
779 status = cx231xx_read_i2c_data(dev,
780 HAMMERHEAD_I2C_ADDRESS,
781 OUT_CTRL1, 2,
782 &value, 4);
783 value |= (1 << 7); 700 value |= (1 << 7);
784 status = cx231xx_write_i2c_data(dev, 701 status = vid_blk_write_word(dev, OUT_CTRL1, value);
785 HAMMERHEAD_I2C_ADDRESS,
786 OUT_CTRL1, 2,
787 value, 4);
788 702
789 /* Set vip 1.1 output mode */ 703 /* Set vip 1.1 output mode */
790 status = cx231xx_read_modify_write_i2c_dword(dev, 704 status = cx231xx_read_modify_write_i2c_dword(dev,
791 HAMMERHEAD_I2C_ADDRESS, 705 VID_BLK_I2C_ADDRESS,
792 OUT_CTRL1, FLD_OUT_MODE, 706 OUT_CTRL1, FLD_OUT_MODE,
793 OUT_MODE_VIP11); 707 OUT_MODE_VIP11);
794 708
@@ -803,10 +717,7 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev,
803 } 717 }
804 718
805 /* Read the DFE_CTRL1 register */ 719 /* Read the DFE_CTRL1 register */
806 status = cx231xx_read_i2c_data(dev, 720 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
807 HAMMERHEAD_I2C_ADDRESS,
808 DFE_CTRL1, 2,
809 &value, 4);
810 721
811 /* enable the VBI_GATE_EN */ 722 /* enable the VBI_GATE_EN */
812 value |= FLD_VBI_GATE_EN; 723 value |= FLD_VBI_GATE_EN;
@@ -815,20 +726,17 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev,
815 value |= FLD_VGA_AUTO_EN; 726 value |= FLD_VGA_AUTO_EN;
816 727
817 /* Write it back */ 728 /* Write it back */
818 status = cx231xx_write_i2c_data(dev, 729 status = vid_blk_write_word(dev, DFE_CTRL1, value);
819 HAMMERHEAD_I2C_ADDRESS,
820 DFE_CTRL1, 2,
821 value, 4);
822 730
823 /* Disable auto config of registers */ 731 /* Disable auto config of registers */
824 status = cx231xx_read_modify_write_i2c_dword(dev, 732 status = cx231xx_read_modify_write_i2c_dword(dev,
825 HAMMERHEAD_I2C_ADDRESS, 733 VID_BLK_I2C_ADDRESS,
826 MODE_CTRL, FLD_ACFG_DIS, 734 MODE_CTRL, FLD_ACFG_DIS,
827 cx231xx_set_field(FLD_ACFG_DIS, 1)); 735 cx231xx_set_field(FLD_ACFG_DIS, 1));
828 736
829 /* Set CVBS input mode */ 737 /* Set CVBS input mode */
830 status = cx231xx_read_modify_write_i2c_dword(dev, 738 status = cx231xx_read_modify_write_i2c_dword(dev,
831 HAMMERHEAD_I2C_ADDRESS, 739 VID_BLK_I2C_ADDRESS,
832 MODE_CTRL, FLD_INPUT_MODE, 740 MODE_CTRL, FLD_INPUT_MODE,
833 cx231xx_set_field(FLD_INPUT_MODE, 741 cx231xx_set_field(FLD_INPUT_MODE,
834 INPUT_MODE_CVBS_0)); 742 INPUT_MODE_CVBS_0));
@@ -846,25 +754,16 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev,
846 } 754 }
847 755
848 /* Make sure bypass is cleared */ 756 /* Make sure bypass is cleared */
849 status = cx231xx_read_i2c_data(dev, 757 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &value);
850 HAMMERHEAD_I2C_ADDRESS,
851 DIF_MISC_CTRL,
852 2, &value, 4);
853 758
854 /* Clear the bypass bit */ 759 /* Clear the bypass bit */
855 value &= ~FLD_DIF_DIF_BYPASS; 760 value &= ~FLD_DIF_DIF_BYPASS;
856 761
857 /* Enable the use of the DIF block */ 762 /* Enable the use of the DIF block */
858 status = cx231xx_write_i2c_data(dev, 763 status = vid_blk_write_word(dev, DIF_MISC_CTRL, value);
859 HAMMERHEAD_I2C_ADDRESS,
860 DIF_MISC_CTRL,
861 2, value, 4);
862 764
863 /* Read the DFE_CTRL1 register */ 765 /* Read the DFE_CTRL1 register */
864 status = cx231xx_read_i2c_data(dev, 766 status = vid_blk_read_word(dev, DFE_CTRL1, &value);
865 HAMMERHEAD_I2C_ADDRESS,
866 DFE_CTRL1, 2,
867 &value, 4);
868 767
869 /* Disable the VBI_GATE_EN */ 768 /* Disable the VBI_GATE_EN */
870 value &= ~FLD_VBI_GATE_EN; 769 value &= ~FLD_VBI_GATE_EN;
@@ -874,10 +773,7 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev,
874 value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000; 773 value |= FLD_VGA_AUTO_EN | FLD_AGC_AUTO_EN | 0x00200000;
875 774
876 /* Write it back */ 775 /* Write it back */
877 status = cx231xx_write_i2c_data(dev, 776 status = vid_blk_write_word(dev, DFE_CTRL1, value);
878 HAMMERHEAD_I2C_ADDRESS,
879 DFE_CTRL1, 2,
880 value, 4);
881 777
882 /* Wait until AGC locks up */ 778 /* Wait until AGC locks up */
883 msleep(1); 779 msleep(1);
@@ -886,39 +782,30 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev,
886 value &= ~(FLD_VGA_AUTO_EN); 782 value &= ~(FLD_VGA_AUTO_EN);
887 783
888 /* Write it back */ 784 /* Write it back */
889 status = cx231xx_write_i2c_data(dev, 785 status = vid_blk_write_word(dev, DFE_CTRL1, value);
890 HAMMERHEAD_I2C_ADDRESS,
891 DFE_CTRL1, 2,
892 value, 4);
893 786
894 /* Enable Polaris B0 AGC output */ 787 /* Enable Polaris B0 AGC output */
895 status = cx231xx_read_i2c_data(dev, 788 status = vid_blk_read_word(dev, PIN_CTRL, &value);
896 HAMMERHEAD_I2C_ADDRESS,
897 PIN_CTRL, 2,
898 &value, 4);
899 value |= (FLD_OEF_AGC_RF) | 789 value |= (FLD_OEF_AGC_RF) |
900 (FLD_OEF_AGC_IFVGA) | 790 (FLD_OEF_AGC_IFVGA) |
901 (FLD_OEF_AGC_IF); 791 (FLD_OEF_AGC_IF);
902 status = cx231xx_write_i2c_data(dev, 792 status = vid_blk_write_word(dev, PIN_CTRL, value);
903 HAMMERHEAD_I2C_ADDRESS,
904 PIN_CTRL, 2,
905 value, 4);
906 793
907 /* Set vip 1.1 output mode */ 794 /* Set vip 1.1 output mode */
908 status = cx231xx_read_modify_write_i2c_dword(dev, 795 status = cx231xx_read_modify_write_i2c_dword(dev,
909 HAMMERHEAD_I2C_ADDRESS, 796 VID_BLK_I2C_ADDRESS,
910 OUT_CTRL1, FLD_OUT_MODE, 797 OUT_CTRL1, FLD_OUT_MODE,
911 OUT_MODE_VIP11); 798 OUT_MODE_VIP11);
912 799
913 /* Disable auto config of registers */ 800 /* Disable auto config of registers */
914 status = cx231xx_read_modify_write_i2c_dword(dev, 801 status = cx231xx_read_modify_write_i2c_dword(dev,
915 HAMMERHEAD_I2C_ADDRESS, 802 VID_BLK_I2C_ADDRESS,
916 MODE_CTRL, FLD_ACFG_DIS, 803 MODE_CTRL, FLD_ACFG_DIS,
917 cx231xx_set_field(FLD_ACFG_DIS, 1)); 804 cx231xx_set_field(FLD_ACFG_DIS, 1));
918 805
919 /* Set CVBS input mode */ 806 /* Set CVBS input mode */
920 status = cx231xx_read_modify_write_i2c_dword(dev, 807 status = cx231xx_read_modify_write_i2c_dword(dev,
921 HAMMERHEAD_I2C_ADDRESS, 808 VID_BLK_I2C_ADDRESS,
922 MODE_CTRL, FLD_INPUT_MODE, 809 MODE_CTRL, FLD_INPUT_MODE,
923 cx231xx_set_field(FLD_INPUT_MODE, 810 cx231xx_set_field(FLD_INPUT_MODE,
924 INPUT_MODE_CVBS_0)); 811 INPUT_MODE_CVBS_0));
@@ -928,17 +815,11 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev,
928 /* Clear clamp for channels 2 and 3 (bit 16-17) */ 815 /* Clear clamp for channels 2 and 3 (bit 16-17) */
929 /* Clear droop comp (bit 19-20) */ 816 /* Clear droop comp (bit 19-20) */
930 /* Set VGA_SEL (for audio control) (bit 7-8) */ 817 /* Set VGA_SEL (for audio control) (bit 7-8) */
931 status = cx231xx_read_i2c_data(dev, 818 status = vid_blk_read_word(dev, AFE_CTRL, &value);
932 HAMMERHEAD_I2C_ADDRESS,
933 AFE_CTRL, 2,
934 &value, 4);
935 819
936 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2; 820 value |= FLD_VGA_SEL_CH3 | FLD_VGA_SEL_CH2;
937 821
938 status = cx231xx_write_i2c_data(dev, 822 status = vid_blk_write_word(dev, AFE_CTRL, value);
939 HAMMERHEAD_I2C_ADDRESS,
940 AFE_CTRL, 2,
941 value, 4);
942 break; 823 break;
943 824
944 } 825 }
@@ -947,17 +828,14 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev,
947 828
948 /* Set raw VBI mode */ 829 /* Set raw VBI mode */
949 status = cx231xx_read_modify_write_i2c_dword(dev, 830 status = cx231xx_read_modify_write_i2c_dword(dev,
950 HAMMERHEAD_I2C_ADDRESS, 831 VID_BLK_I2C_ADDRESS,
951 OUT_CTRL1, FLD_VBIHACTRAW_EN, 832 OUT_CTRL1, FLD_VBIHACTRAW_EN,
952 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1)); 833 cx231xx_set_field(FLD_VBIHACTRAW_EN, 1));
953 834
954 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 835 status = vid_blk_read_word(dev, OUT_CTRL1, &value);
955 OUT_CTRL1, 2,
956 &value, 4);
957 if (value & 0x02) { 836 if (value & 0x02) {
958 value |= (1 << 19); 837 value |= (1 << 19);
959 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 838 status = vid_blk_write_word(dev, OUT_CTRL1, value);
960 OUT_CTRL1, 2, value, 4);
961 } 839 }
962 840
963 return status; 841 return status;
@@ -976,9 +854,7 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
976 (unsigned int)dev->norm); 854 (unsigned int)dev->norm);
977 855
978 /* Change the DFE_CTRL3 bp_percent to fix flagging */ 856 /* Change the DFE_CTRL3 bp_percent to fix flagging */
979 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 857 status = vid_blk_write_word(dev, DFE_CTRL3, 0xCD3F0280);
980 DFE_CTRL3, 2,
981 0xCD3F0280, 4);
982 858
983 if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) { 859 if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
984 cx231xx_info("do_mode_ctrl_overrides NTSC\n"); 860 cx231xx_info("do_mode_ctrl_overrides NTSC\n");
@@ -986,22 +862,22 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
986 /* Move the close caption lines out of active video, 862 /* Move the close caption lines out of active video,
987 adjust the active video start point */ 863 adjust the active video start point */
988 status = cx231xx_read_modify_write_i2c_dword(dev, 864 status = cx231xx_read_modify_write_i2c_dword(dev,
989 HAMMERHEAD_I2C_ADDRESS, 865 VID_BLK_I2C_ADDRESS,
990 VERT_TIM_CTRL, 866 VERT_TIM_CTRL,
991 FLD_VBLANK_CNT, 0x18); 867 FLD_VBLANK_CNT, 0x18);
992 status = cx231xx_read_modify_write_i2c_dword(dev, 868 status = cx231xx_read_modify_write_i2c_dword(dev,
993 HAMMERHEAD_I2C_ADDRESS, 869 VID_BLK_I2C_ADDRESS,
994 VERT_TIM_CTRL, 870 VERT_TIM_CTRL,
995 FLD_VACTIVE_CNT, 871 FLD_VACTIVE_CNT,
996 0x1E6000); 872 0x1E6000);
997 status = cx231xx_read_modify_write_i2c_dword(dev, 873 status = cx231xx_read_modify_write_i2c_dword(dev,
998 HAMMERHEAD_I2C_ADDRESS, 874 VID_BLK_I2C_ADDRESS,
999 VERT_TIM_CTRL, 875 VERT_TIM_CTRL,
1000 FLD_V656BLANK_CNT, 876 FLD_V656BLANK_CNT,
1001 0x1E000000); 877 0x1E000000);
1002 878
1003 status = cx231xx_read_modify_write_i2c_dword(dev, 879 status = cx231xx_read_modify_write_i2c_dword(dev,
1004 HAMMERHEAD_I2C_ADDRESS, 880 VID_BLK_I2C_ADDRESS,
1005 HORIZ_TIM_CTRL, 881 HORIZ_TIM_CTRL,
1006 FLD_HBLANK_CNT, 882 FLD_HBLANK_CNT,
1007 cx231xx_set_field 883 cx231xx_set_field
@@ -1009,12 +885,12 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
1009 } else if (dev->norm & V4L2_STD_SECAM) { 885 } else if (dev->norm & V4L2_STD_SECAM) {
1010 cx231xx_info("do_mode_ctrl_overrides SECAM\n"); 886 cx231xx_info("do_mode_ctrl_overrides SECAM\n");
1011 status = cx231xx_read_modify_write_i2c_dword(dev, 887 status = cx231xx_read_modify_write_i2c_dword(dev,
1012 HAMMERHEAD_I2C_ADDRESS, 888 VID_BLK_I2C_ADDRESS,
1013 VERT_TIM_CTRL, 889 VERT_TIM_CTRL,
1014 FLD_VBLANK_CNT, 0x24); 890 FLD_VBLANK_CNT, 0x24);
1015 /* Adjust the active video horizontal start point */ 891 /* Adjust the active video horizontal start point */
1016 status = cx231xx_read_modify_write_i2c_dword(dev, 892 status = cx231xx_read_modify_write_i2c_dword(dev,
1017 HAMMERHEAD_I2C_ADDRESS, 893 VID_BLK_I2C_ADDRESS,
1018 HORIZ_TIM_CTRL, 894 HORIZ_TIM_CTRL,
1019 FLD_HBLANK_CNT, 895 FLD_HBLANK_CNT,
1020 cx231xx_set_field 896 cx231xx_set_field
@@ -1022,12 +898,12 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
1022 } else { 898 } else {
1023 cx231xx_info("do_mode_ctrl_overrides PAL\n"); 899 cx231xx_info("do_mode_ctrl_overrides PAL\n");
1024 status = cx231xx_read_modify_write_i2c_dword(dev, 900 status = cx231xx_read_modify_write_i2c_dword(dev,
1025 HAMMERHEAD_I2C_ADDRESS, 901 VID_BLK_I2C_ADDRESS,
1026 VERT_TIM_CTRL, 902 VERT_TIM_CTRL,
1027 FLD_VBLANK_CNT, 0x24); 903 FLD_VBLANK_CNT, 0x24);
1028 /* Adjust the active video horizontal start point */ 904 /* Adjust the active video horizontal start point */
1029 status = cx231xx_read_modify_write_i2c_dword(dev, 905 status = cx231xx_read_modify_write_i2c_dword(dev,
1030 HAMMERHEAD_I2C_ADDRESS, 906 VID_BLK_I2C_ADDRESS,
1031 HORIZ_TIM_CTRL, 907 HORIZ_TIM_CTRL,
1032 FLD_HBLANK_CNT, 908 FLD_HBLANK_CNT,
1033 cx231xx_set_field 909 cx231xx_set_field
@@ -1047,7 +923,7 @@ int cx231xx_set_audio_input(struct cx231xx *dev, u8 input)
1047 ainput = AUDIO_INPUT_TUNER_TV; 923 ainput = AUDIO_INPUT_TUNER_TV;
1048 break; 924 break;
1049 case CX231XX_AMUX_LINE_IN: 925 case CX231XX_AMUX_LINE_IN:
1050 status = cx231xx_flatiron_set_audio_input(dev, input); 926 status = cx231xx_i2s_blk_set_audio_input(dev, input);
1051 ainput = AUDIO_INPUT_LINE; 927 ainput = AUDIO_INPUT_LINE;
1052 break; 928 break;
1053 default: 929 default:
@@ -1064,71 +940,55 @@ int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
1064{ 940{
1065 u32 dwval; 941 u32 dwval;
1066 int status; 942 int status;
1067 u32 gen_ctrl; 943 u8 gen_ctrl;
1068 u32 value = 0; 944 u32 value = 0;
1069 945
1070 /* Put it in soft reset */ 946 /* Put it in soft reset */
1071 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 947 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1072 GENERAL_CTL, 2, &gen_ctrl, 1);
1073 gen_ctrl |= 1; 948 gen_ctrl |= 1;
1074 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 949 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1075 GENERAL_CTL, 2, gen_ctrl, 1);
1076 950
1077 switch (audio_input) { 951 switch (audio_input) {
1078 case AUDIO_INPUT_LINE: 952 case AUDIO_INPUT_LINE:
1079 /* setup AUD_IO control from Merlin paralle output */ 953 /* setup AUD_IO control from Merlin paralle output */
1080 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC, 954 value = cx231xx_set_field(FLD_AUD_CHAN1_SRC,
1081 AUD_CHAN_SRC_PARALLEL); 955 AUD_CHAN_SRC_PARALLEL);
1082 status = cx231xx_write_i2c_data(dev, 956 status = vid_blk_write_word(dev, AUD_IO_CTRL, value);
1083 HAMMERHEAD_I2C_ADDRESS,
1084 AUD_IO_CTRL, 2, value, 4);
1085 957
1086 /* setup input to Merlin, SRC2 connect to AC97 958 /* setup input to Merlin, SRC2 connect to AC97
1087 bypass upsample-by-2, slave mode, sony mode, left justify 959 bypass upsample-by-2, slave mode, sony mode, left justify
1088 adr 091c, dat 01000000 */ 960 adr 091c, dat 01000000 */
1089 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 961 status = vid_blk_read_word(dev, AC97_CTL, &dwval);
1090 AC97_CTL,
1091 2, &dwval, 4);
1092 962
1093 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 963 status = vid_blk_write_word(dev, AC97_CTL,
1094 AC97_CTL, 2, 964 (dwval | FLD_AC97_UP2X_BYPASS));
1095 (dwval | FLD_AC97_UP2X_BYPASS), 4);
1096 965
1097 /* select the parallel1 and SRC3 */ 966 /* select the parallel1 and SRC3 */
1098 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 967 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1099 BAND_OUT_SEL, 2,
1100 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) | 968 cx231xx_set_field(FLD_SRC3_IN_SEL, 0x0) |
1101 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) | 969 cx231xx_set_field(FLD_SRC3_CLK_SEL, 0x0) |
1102 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0), 970 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x0));
1103 4);
1104 971
1105 /* unmute all, AC97 in, independence mode 972 /* unmute all, AC97 in, independence mode
1106 adr 08d0, data 0x00063073 */ 973 adr 08d0, data 0x00063073 */
1107 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 974 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063073);
1108 PATH1_CTL1, 2, 0x00063073, 4);
1109 975
1110 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */ 976 /* set AVC maximum threshold, adr 08d4, dat ffff0024 */
1111 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 977 status = vid_blk_read_word(dev, PATH1_VOL_CTL, &dwval);
1112 PATH1_VOL_CTL, 2, &dwval, 4); 978 status = vid_blk_write_word(dev, PATH1_VOL_CTL,
1113 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 979 (dwval | FLD_PATH1_AVC_THRESHOLD));
1114 PATH1_VOL_CTL, 2,
1115 (dwval | FLD_PATH1_AVC_THRESHOLD),
1116 4);
1117 980
1118 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */ 981 /* set SC maximum threshold, adr 08ec, dat ffffb3a3 */
1119 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 982 status = vid_blk_read_word(dev, PATH1_SC_CTL, &dwval);
1120 PATH1_SC_CTL, 2, &dwval, 4); 983 status = vid_blk_write_word(dev, PATH1_SC_CTL,
1121 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 984 (dwval | FLD_PATH1_SC_THRESHOLD));
1122 PATH1_SC_CTL, 2,
1123 (dwval | FLD_PATH1_SC_THRESHOLD), 4);
1124 break; 985 break;
1125 986
1126 case AUDIO_INPUT_TUNER_TV: 987 case AUDIO_INPUT_TUNER_TV:
1127 default: 988 default:
1128 989
1129 /* Setup SRC sources and clocks */ 990 /* Setup SRC sources and clocks */
1130 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 991 status = vid_blk_write_word(dev, BAND_OUT_SEL,
1131 BAND_OUT_SEL, 2,
1132 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) | 992 cx231xx_set_field(FLD_SRC6_IN_SEL, 0x00) |
1133 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) | 993 cx231xx_set_field(FLD_SRC6_CLK_SEL, 0x01) |
1134 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) | 994 cx231xx_set_field(FLD_SRC5_IN_SEL, 0x00) |
@@ -1141,29 +1001,26 @@ int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
1141 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) | 1001 cx231xx_set_field(FLD_AC97_SRC_SEL, 0x03) |
1142 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) | 1002 cx231xx_set_field(FLD_I2S_SRC_SEL, 0x00) |
1143 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) | 1003 cx231xx_set_field(FLD_PARALLEL2_SRC_SEL, 0x02) |
1144 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01), 4); 1004 cx231xx_set_field(FLD_PARALLEL1_SRC_SEL, 0x01));
1145 1005
1146 /* Setup the AUD_IO control */ 1006 /* Setup the AUD_IO control */
1147 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1007 status = vid_blk_write_word(dev, AUD_IO_CTRL,
1148 AUD_IO_CTRL, 2,
1149 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) | 1008 cx231xx_set_field(FLD_I2S_PORT_DIR, 0x00) |
1150 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) | 1009 cx231xx_set_field(FLD_I2S_OUT_SRC, 0x00) |
1151 cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) | 1010 cx231xx_set_field(FLD_AUD_CHAN3_SRC, 0x00) |
1152 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) | 1011 cx231xx_set_field(FLD_AUD_CHAN2_SRC, 0x00) |
1153 cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03), 4); 1012 cx231xx_set_field(FLD_AUD_CHAN1_SRC, 0x03));
1154 1013
1155 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1014 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F063870);
1156 PATH1_CTL1, 2, 0x1F063870, 4);
1157 1015
1158 /* setAudioStandard(_audio_standard); */ 1016 /* setAudioStandard(_audio_standard); */
1159 1017
1160 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1018 status = vid_blk_write_word(dev, PATH1_CTL1, 0x00063870);
1161 PATH1_CTL1, 2, 0x00063870, 4);
1162 switch (dev->model) { 1019 switch (dev->model) {
1163 case CX231XX_BOARD_CNXT_RDE_250: 1020 case CX231XX_BOARD_CNXT_RDE_250:
1164 case CX231XX_BOARD_CNXT_RDU_250: 1021 case CX231XX_BOARD_CNXT_RDU_250:
1165 status = cx231xx_read_modify_write_i2c_dword(dev, 1022 status = cx231xx_read_modify_write_i2c_dword(dev,
1166 HAMMERHEAD_I2C_ADDRESS, 1023 VID_BLK_I2C_ADDRESS,
1167 CHIP_CTRL, 1024 CHIP_CTRL,
1168 FLD_SIF_EN, 1025 FLD_SIF_EN,
1169 cx231xx_set_field(FLD_SIF_EN, 1)); 1026 cx231xx_set_field(FLD_SIF_EN, 1));
@@ -1181,17 +1038,14 @@ int cx231xx_set_audio_decoder_input(struct cx231xx *dev,
1181 break; 1038 break;
1182 1039
1183 case AUDIO_INPUT_MUTE: 1040 case AUDIO_INPUT_MUTE:
1184 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1041 status = vid_blk_write_word(dev, PATH1_CTL1, 0x1F011012);
1185 PATH1_CTL1, 2, 0x1F011012, 4);
1186 break; 1042 break;
1187 } 1043 }
1188 1044
1189 /* Take it out of soft reset */ 1045 /* Take it out of soft reset */
1190 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1046 status = vid_blk_read_byte(dev, GENERAL_CTL, &gen_ctrl);
1191 GENERAL_CTL, 2, &gen_ctrl, 1);
1192 gen_ctrl &= ~1; 1047 gen_ctrl &= ~1;
1193 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1048 status = vid_blk_write_byte(dev, GENERAL_CTL, gen_ctrl);
1194 GENERAL_CTL, 2, gen_ctrl, 1);
1195 1049
1196 return status; 1050 return status;
1197} 1051}
@@ -1209,12 +1063,10 @@ int cx231xx_resolution_set(struct cx231xx *dev)
1209 get_scale(dev, width, height, &hscale, &vscale); 1063 get_scale(dev, width, height, &hscale, &vscale);
1210 1064
1211 /* set horzontal scale */ 1065 /* set horzontal scale */
1212 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1066 status = vid_blk_write_word(dev, HSCALE_CTRL, hscale);
1213 HSCALE_CTRL, 2, hscale, 4);
1214 1067
1215 /* set vertical scale */ 1068 /* set vertical scale */
1216 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1069 status = vid_blk_write_word(dev, VSCALE_CTRL, vscale);
1217 VSCALE_CTRL, 2, vscale, 4);
1218 1070
1219 return status; 1071 return status;
1220} 1072}
@@ -1227,11 +1079,9 @@ int cx231xx_init_ctrl_pin_status(struct cx231xx *dev)
1227 u32 value; 1079 u32 value;
1228 int status = 0; 1080 int status = 0;
1229 1081
1230 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, 1082 status = vid_blk_read_word(dev, PIN_CTRL, &value);
1231 2, &value, 4);
1232 value |= (~dev->board.ctl_pin_status_mask); 1083 value |= (~dev->board.ctl_pin_status_mask);
1233 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, PIN_CTRL, 1084 status = vid_blk_write_word(dev, PIN_CTRL, value);
1234 2, value, 4);
1235 1085
1236 return status; 1086 return status;
1237} 1087}
@@ -1296,82 +1146,82 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1296 /* C2HH */ 1146 /* C2HH */
1297 /* lo if big signal */ 1147 /* lo if big signal */
1298 status = cx231xx_reg_mask_write(dev, 1148 status = cx231xx_reg_mask_write(dev,
1299 HAMMERHEAD_I2C_ADDRESS, 32, 1149 VID_BLK_I2C_ADDRESS, 32,
1300 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1150 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1301 /* FUNC_MODE = DIF */ 1151 /* FUNC_MODE = DIF */
1302 status = cx231xx_reg_mask_write(dev, 1152 status = cx231xx_reg_mask_write(dev,
1303 HAMMERHEAD_I2C_ADDRESS, 32, 1153 VID_BLK_I2C_ADDRESS, 32,
1304 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode); 1154 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, function_mode);
1305 /* IF_MODE */ 1155 /* IF_MODE */
1306 status = cx231xx_reg_mask_write(dev, 1156 status = cx231xx_reg_mask_write(dev,
1307 HAMMERHEAD_I2C_ADDRESS, 32, 1157 VID_BLK_I2C_ADDRESS, 32,
1308 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF); 1158 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xFF);
1309 /* no inv */ 1159 /* no inv */
1310 status = cx231xx_reg_mask_write(dev, 1160 status = cx231xx_reg_mask_write(dev,
1311 HAMMERHEAD_I2C_ADDRESS, 32, 1161 VID_BLK_I2C_ADDRESS, 32,
1312 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1162 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1313 } else if (standard != DIF_USE_BASEBAND) { 1163 } else if (standard != DIF_USE_BASEBAND) {
1314 if (standard & V4L2_STD_MN) { 1164 if (standard & V4L2_STD_MN) {
1315 /* lo if big signal */ 1165 /* lo if big signal */
1316 status = cx231xx_reg_mask_write(dev, 1166 status = cx231xx_reg_mask_write(dev,
1317 HAMMERHEAD_I2C_ADDRESS, 32, 1167 VID_BLK_I2C_ADDRESS, 32,
1318 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1168 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1319 /* FUNC_MODE = DIF */ 1169 /* FUNC_MODE = DIF */
1320 status = cx231xx_reg_mask_write(dev, 1170 status = cx231xx_reg_mask_write(dev,
1321 HAMMERHEAD_I2C_ADDRESS, 32, 1171 VID_BLK_I2C_ADDRESS, 32,
1322 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1172 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1323 function_mode); 1173 function_mode);
1324 /* IF_MODE */ 1174 /* IF_MODE */
1325 status = cx231xx_reg_mask_write(dev, 1175 status = cx231xx_reg_mask_write(dev,
1326 HAMMERHEAD_I2C_ADDRESS, 32, 1176 VID_BLK_I2C_ADDRESS, 32,
1327 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb); 1177 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xb);
1328 /* no inv */ 1178 /* no inv */
1329 status = cx231xx_reg_mask_write(dev, 1179 status = cx231xx_reg_mask_write(dev,
1330 HAMMERHEAD_I2C_ADDRESS, 32, 1180 VID_BLK_I2C_ADDRESS, 32,
1331 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1181 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1332 /* 0x124, AUD_CHAN1_SRC = 0x3 */ 1182 /* 0x124, AUD_CHAN1_SRC = 0x3 */
1333 status = cx231xx_reg_mask_write(dev, 1183 status = cx231xx_reg_mask_write(dev,
1334 HAMMERHEAD_I2C_ADDRESS, 32, 1184 VID_BLK_I2C_ADDRESS, 32,
1335 AUD_IO_CTRL, 0, 31, 0x00000003); 1185 AUD_IO_CTRL, 0, 31, 0x00000003);
1336 } else if ((standard == V4L2_STD_PAL_I) | 1186 } else if ((standard == V4L2_STD_PAL_I) |
1337 (standard & V4L2_STD_SECAM)) { 1187 (standard & V4L2_STD_SECAM)) {
1338 /* C2HH setup */ 1188 /* C2HH setup */
1339 /* lo if big signal */ 1189 /* lo if big signal */
1340 status = cx231xx_reg_mask_write(dev, 1190 status = cx231xx_reg_mask_write(dev,
1341 HAMMERHEAD_I2C_ADDRESS, 32, 1191 VID_BLK_I2C_ADDRESS, 32,
1342 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1192 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1343 /* FUNC_MODE = DIF */ 1193 /* FUNC_MODE = DIF */
1344 status = cx231xx_reg_mask_write(dev, 1194 status = cx231xx_reg_mask_write(dev,
1345 HAMMERHEAD_I2C_ADDRESS, 32, 1195 VID_BLK_I2C_ADDRESS, 32,
1346 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1196 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1347 function_mode); 1197 function_mode);
1348 /* IF_MODE */ 1198 /* IF_MODE */
1349 status = cx231xx_reg_mask_write(dev, 1199 status = cx231xx_reg_mask_write(dev,
1350 HAMMERHEAD_I2C_ADDRESS, 32, 1200 VID_BLK_I2C_ADDRESS, 32,
1351 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); 1201 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);
1352 /* no inv */ 1202 /* no inv */
1353 status = cx231xx_reg_mask_write(dev, 1203 status = cx231xx_reg_mask_write(dev,
1354 HAMMERHEAD_I2C_ADDRESS, 32, 1204 VID_BLK_I2C_ADDRESS, 32,
1355 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1205 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1356 } else { 1206 } else {
1357 /* default PAL BG */ 1207 /* default PAL BG */
1358 /* C2HH setup */ 1208 /* C2HH setup */
1359 /* lo if big signal */ 1209 /* lo if big signal */
1360 status = cx231xx_reg_mask_write(dev, 1210 status = cx231xx_reg_mask_write(dev,
1361 HAMMERHEAD_I2C_ADDRESS, 32, 1211 VID_BLK_I2C_ADDRESS, 32,
1362 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1); 1212 AFE_CTRL_C2HH_SRC_CTRL, 30, 31, 0x1);
1363 /* FUNC_MODE = DIF */ 1213 /* FUNC_MODE = DIF */
1364 status = cx231xx_reg_mask_write(dev, 1214 status = cx231xx_reg_mask_write(dev,
1365 HAMMERHEAD_I2C_ADDRESS, 32, 1215 VID_BLK_I2C_ADDRESS, 32,
1366 AFE_CTRL_C2HH_SRC_CTRL, 23, 24, 1216 AFE_CTRL_C2HH_SRC_CTRL, 23, 24,
1367 function_mode); 1217 function_mode);
1368 /* IF_MODE */ 1218 /* IF_MODE */
1369 status = cx231xx_reg_mask_write(dev, 1219 status = cx231xx_reg_mask_write(dev,
1370 HAMMERHEAD_I2C_ADDRESS, 32, 1220 VID_BLK_I2C_ADDRESS, 32,
1371 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); 1221 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
1372 /* no inv */ 1222 /* no inv */
1373 status = cx231xx_reg_mask_write(dev, 1223 status = cx231xx_reg_mask_write(dev,
1374 HAMMERHEAD_I2C_ADDRESS, 32, 1224 VID_BLK_I2C_ADDRESS, 32,
1375 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1225 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1376 } 1226 }
1377 } 1227 }
@@ -1387,9 +1237,7 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1387 1237
1388 cx231xx_info("%s: setStandard to %x\n", __func__, standard); 1238 cx231xx_info("%s: setStandard to %x\n", __func__, standard);
1389 1239
1390 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1240 status = vid_blk_read_word(dev, DIF_MISC_CTRL, &dif_misc_ctrl_value);
1391 DIF_MISC_CTRL, 2, &dif_misc_ctrl_value,
1392 4);
1393 if (standard != DIF_USE_BASEBAND) 1241 if (standard != DIF_USE_BASEBAND)
1394 dev->norm = standard; 1242 dev->norm = standard;
1395 1243
@@ -1408,182 +1256,154 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1408 if (standard == DIF_USE_BASEBAND) { /* base band */ 1256 if (standard == DIF_USE_BASEBAND) { /* base band */
1409 /* There is a different SRC_PHASE_INC value 1257 /* There is a different SRC_PHASE_INC value
1410 for baseband vs. DIF */ 1258 for baseband vs. DIF */
1411 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1259 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC, 0xDF7DF83);
1412 DIF_SRC_PHASE_INC, 2, 0xDF7DF83, 1260 status = vid_blk_read_word(dev, DIF_MISC_CTRL,
1413 4); 1261 &dif_misc_ctrl_value);
1414 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1415 DIF_MISC_CTRL, 2,
1416 &dif_misc_ctrl_value, 4);
1417 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS; 1262 dif_misc_ctrl_value |= FLD_DIF_DIF_BYPASS;
1418 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1263 status = vid_blk_write_word(dev, DIF_MISC_CTRL,
1419 DIF_MISC_CTRL, 2, 1264 dif_misc_ctrl_value);
1420 dif_misc_ctrl_value, 4);
1421 } else if (standard & V4L2_STD_PAL_D) { 1265 } else if (standard & V4L2_STD_PAL_D) {
1422 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1266 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1423 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1267 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1424 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1268 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1425 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1269 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1426 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1270 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1427 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1271 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1428 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1272 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1429 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1273 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1430 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1274 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1431 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 1275 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1432 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1276 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1433 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 1277 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1434 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1278 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1435 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 1279 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1436 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1280 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1437 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 1281 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1438 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1282 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1439 DIF_AGC_IF_INT_CURRENT, 0, 31, 1283 DIF_AGC_IF_INT_CURRENT, 0, 31,
1440 0x26001700); 1284 0x26001700);
1441 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1285 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1442 DIF_AGC_RF_CURRENT, 0, 31, 1286 DIF_AGC_RF_CURRENT, 0, 31,
1443 0x00002660); 1287 0x00002660);
1444 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1288 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1445 DIF_VIDEO_AGC_CTRL, 0, 31, 1289 DIF_VIDEO_AGC_CTRL, 0, 31,
1446 0x72500800); 1290 0x72500800);
1447 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1291 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1448 DIF_VID_AUD_OVERRIDE, 0, 31, 1292 DIF_VID_AUD_OVERRIDE, 0, 31,
1449 0x27000100); 1293 0x27000100);
1450 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1294 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1451 DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA); 1295 DIF_AV_SEP_CTRL, 0, 31, 0x3F3934EA);
1452 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1296 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1453 DIF_COMP_FLT_CTRL, 0, 31, 1297 DIF_COMP_FLT_CTRL, 0, 31,
1454 0x00000000); 1298 0x00000000);
1455 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1299 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1456 DIF_SRC_PHASE_INC, 0, 31, 1300 DIF_SRC_PHASE_INC, 0, 31,
1457 0x1befbf06); 1301 0x1befbf06);
1458 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1302 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1459 DIF_SRC_GAIN_CONTROL, 0, 31, 1303 DIF_SRC_GAIN_CONTROL, 0, 31,
1460 0x000035e8); 1304 0x000035e8);
1461 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1305 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1462 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1306 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1463 /* Save the Spec Inversion value */ 1307 /* Save the Spec Inversion value */
1464 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1308 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1465 dif_misc_ctrl_value |= 0x3a023F11; 1309 dif_misc_ctrl_value |= 0x3a023F11;
1466 } else if (standard & V4L2_STD_PAL_I) { 1310 } else if (standard & V4L2_STD_PAL_I) {
1467 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1311 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1468 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1312 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1469 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1313 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1470 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1314 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1471 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1315 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1472 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1316 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1473 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1317 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1474 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1318 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1475 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1319 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1476 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 1320 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1477 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1321 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1478 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 1322 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1479 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1323 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1480 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 1324 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1481 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1325 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1482 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 1326 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1483 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1327 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1484 DIF_AGC_IF_INT_CURRENT, 0, 31, 1328 DIF_AGC_IF_INT_CURRENT, 0, 31,
1485 0x26001700); 1329 0x26001700);
1486 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1330 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1487 DIF_AGC_RF_CURRENT, 0, 31, 1331 DIF_AGC_RF_CURRENT, 0, 31,
1488 0x00002660); 1332 0x00002660);
1489 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1333 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1490 DIF_VIDEO_AGC_CTRL, 0, 31, 1334 DIF_VIDEO_AGC_CTRL, 0, 31,
1491 0x72500800); 1335 0x72500800);
1492 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1336 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1493 DIF_VID_AUD_OVERRIDE, 0, 31, 1337 DIF_VID_AUD_OVERRIDE, 0, 31,
1494 0x27000100); 1338 0x27000100);
1495 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1339 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1496 DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934); 1340 DIF_AV_SEP_CTRL, 0, 31, 0x5F39A934);
1497 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1341 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1498 DIF_COMP_FLT_CTRL, 0, 31, 1342 DIF_COMP_FLT_CTRL, 0, 31,
1499 0x00000000); 1343 0x00000000);
1500 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1344 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1501 DIF_SRC_PHASE_INC, 0, 31, 1345 DIF_SRC_PHASE_INC, 0, 31,
1502 0x1befbf06); 1346 0x1befbf06);
1503 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1347 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1504 DIF_SRC_GAIN_CONTROL, 0, 31, 1348 DIF_SRC_GAIN_CONTROL, 0, 31,
1505 0x000035e8); 1349 0x000035e8);
1506 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1350 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1507 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1351 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1508 /* Save the Spec Inversion value */ 1352 /* Save the Spec Inversion value */
1509 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1353 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1510 dif_misc_ctrl_value |= 0x3a033F11; 1354 dif_misc_ctrl_value |= 0x3a033F11;
1511 } else if (standard & V4L2_STD_PAL_M) { 1355 } else if (standard & V4L2_STD_PAL_M) {
1512 /* improved Low Frequency Phase Noise */ 1356 /* improved Low Frequency Phase Noise */
1513 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1357 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1514 DIF_PLL_CTRL, 2, 0xFF01FF0C, 4); 1358 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1515 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1359 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1516 DIF_PLL_CTRL1, 2, 0xbd038c85, 1360 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1517 4); 1361 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1518 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1362 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1519 DIF_PLL_CTRL2, 2, 0x1db4640a, 4); 1363 0x26001700);
1520 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1364 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1521 DIF_PLL_CTRL3, 2, 0x00008800, 4); 1365 0x00002660);
1522 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1366 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1523 DIF_AGC_IF_REF, 2, 0x444C1380, 4); 1367 0x72500800);
1524 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1368 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1525 DIF_AGC_IF_INT_CURRENT, 2, 1369 0x27000100);
1526 0x26001700, 4); 1370 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x012c405d);
1527 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1371 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1528 DIF_AGC_RF_CURRENT, 2, 0x00002660, 1372 0x009f50c1);
1529 4); 1373 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1530 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1374 0x1befbf06);
1531 DIF_VIDEO_AGC_CTRL, 2, 0x72500800, 1375 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1532 4); 1376 0x000035e8);
1533 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1377 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1534 DIF_VID_AUD_OVERRIDE, 2, 0x27000100, 1378 0x00000000);
1535 4);
1536 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1537 DIF_AV_SEP_CTRL, 2, 0x012c405d, 4);
1538 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1539 DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4);
1540 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1541 DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4);
1542 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1543 DIF_SRC_GAIN_CONTROL, 2, 0x000035e8,
1544 4);
1545 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1546 DIF_SOFT_RST_CTRL_REVB, 2,
1547 0x00000000, 4);
1548 /* Save the Spec Inversion value */ 1379 /* Save the Spec Inversion value */
1549 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1380 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1550 dif_misc_ctrl_value |= 0x3A0A3F10; 1381 dif_misc_ctrl_value |= 0x3A0A3F10;
1551 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { 1382 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
1552 /* improved Low Frequency Phase Noise */ 1383 /* improved Low Frequency Phase Noise */
1553 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1384 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0xFF01FF0C);
1554 DIF_PLL_CTRL, 2, 0xFF01FF0C, 4); 1385 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xbd038c85);
1555 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1386 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1db4640a);
1556 DIF_PLL_CTRL1, 2, 0xbd038c85, 4); 1387 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1557 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1388 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C1380);
1558 DIF_PLL_CTRL2, 2, 0x1db4640a, 4); 1389 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1559 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1390 0x26001700);
1560 DIF_PLL_CTRL3, 2, 0x00008800, 4); 1391 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1561 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1392 0x00002660);
1562 DIF_AGC_IF_REF, 2, 0x444C1380, 4); 1393 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1563 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1394 0x72500800);
1564 DIF_AGC_IF_INT_CURRENT, 2, 1395 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1565 0x26001700, 4); 1396 0x27000100);
1566 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1397 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL,
1567 DIF_AGC_RF_CURRENT, 2, 0x00002660, 1398 0x012c405d);
1568 4); 1399 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1569 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1400 0x009f50c1);
1570 DIF_VIDEO_AGC_CTRL, 2, 0x72500800, 1401 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1571 4); 1402 0x1befbf06);
1572 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1403 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1573 DIF_VID_AUD_OVERRIDE, 2, 0x27000100, 1404 0x000035e8);
1574 4); 1405 status = vid_blk_write_word(dev, DIF_SOFT_RST_CTRL_REVB,
1575 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1406 0x00000000);
1576 DIF_AV_SEP_CTRL, 2, 0x012c405d, 4);
1577 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1578 DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4);
1579 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1580 DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4);
1581 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1582 DIF_SRC_GAIN_CONTROL, 2, 0x000035e8,
1583 4);
1584 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1585 DIF_SOFT_RST_CTRL_REVB, 2,
1586 0x00000000, 4);
1587 /* Save the Spec Inversion value */ 1407 /* Save the Spec Inversion value */
1588 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1408 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1589 dif_misc_ctrl_value = 0x3A093F10; 1409 dif_misc_ctrl_value = 0x3A093F10;
@@ -1591,45 +1411,45 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1591 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | 1411 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
1592 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) { 1412 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
1593 1413
1594 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1414 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1595 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1415 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1596 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1416 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1597 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1417 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1598 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1418 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1599 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1419 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1600 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1420 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1601 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1421 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1602 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1422 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1603 DIF_AGC_IF_REF, 0, 31, 0x888C0380); 1423 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1604 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1424 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1605 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); 1425 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1606 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1426 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1607 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); 1427 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1608 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1428 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1609 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); 1429 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1610 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1430 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1611 DIF_AGC_IF_INT_CURRENT, 0, 31, 1431 DIF_AGC_IF_INT_CURRENT, 0, 31,
1612 0x26001700); 1432 0x26001700);
1613 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1433 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1614 DIF_AGC_RF_CURRENT, 0, 31, 1434 DIF_AGC_RF_CURRENT, 0, 31,
1615 0x00002660); 1435 0x00002660);
1616 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1436 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1617 DIF_VID_AUD_OVERRIDE, 0, 31, 1437 DIF_VID_AUD_OVERRIDE, 0, 31,
1618 0x27000100); 1438 0x27000100);
1619 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1439 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1620 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); 1440 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1621 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1441 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1622 DIF_COMP_FLT_CTRL, 0, 31, 1442 DIF_COMP_FLT_CTRL, 0, 31,
1623 0x00000000); 1443 0x00000000);
1624 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1444 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1625 DIF_SRC_PHASE_INC, 0, 31, 1445 DIF_SRC_PHASE_INC, 0, 31,
1626 0x1befbf06); 1446 0x1befbf06);
1627 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1447 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1628 DIF_SRC_GAIN_CONTROL, 0, 31, 1448 DIF_SRC_GAIN_CONTROL, 0, 31,
1629 0x000035e8); 1449 0x000035e8);
1630 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1450 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1631 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1451 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1632 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1452 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1633 DIF_VIDEO_AGC_CTRL, 0, 31, 1453 DIF_VIDEO_AGC_CTRL, 0, 31,
1634 0xf4000000); 1454 0xf4000000);
1635 1455
@@ -1638,45 +1458,45 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1638 dif_misc_ctrl_value |= 0x3a023F11; 1458 dif_misc_ctrl_value |= 0x3a023F11;
1639 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) { 1459 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
1640 /* Is it SECAM_L1? */ 1460 /* Is it SECAM_L1? */
1641 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1461 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1642 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1462 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1643 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1463 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1644 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1464 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1645 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1465 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1646 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1466 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1647 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1467 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1648 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1468 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1649 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1469 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1650 DIF_AGC_IF_REF, 0, 31, 0x888C0380); 1470 DIF_AGC_IF_REF, 0, 31, 0x888C0380);
1651 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1471 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1652 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600); 1472 DIF_AGC_CTRL_IF, 0, 31, 0xe0262600);
1653 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1473 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1654 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700); 1474 DIF_AGC_CTRL_INT, 0, 31, 0xc2171700);
1655 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1475 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1656 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600); 1476 DIF_AGC_CTRL_RF, 0, 31, 0xc2262600);
1657 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1477 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1658 DIF_AGC_IF_INT_CURRENT, 0, 31, 1478 DIF_AGC_IF_INT_CURRENT, 0, 31,
1659 0x26001700); 1479 0x26001700);
1660 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1480 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1661 DIF_AGC_RF_CURRENT, 0, 31, 1481 DIF_AGC_RF_CURRENT, 0, 31,
1662 0x00002660); 1482 0x00002660);
1663 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1483 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1664 DIF_VID_AUD_OVERRIDE, 0, 31, 1484 DIF_VID_AUD_OVERRIDE, 0, 31,
1665 0x27000100); 1485 0x27000100);
1666 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1486 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1667 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec); 1487 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530ec);
1668 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1488 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1669 DIF_COMP_FLT_CTRL, 0, 31, 1489 DIF_COMP_FLT_CTRL, 0, 31,
1670 0x00000000); 1490 0x00000000);
1671 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1491 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1672 DIF_SRC_PHASE_INC, 0, 31, 1492 DIF_SRC_PHASE_INC, 0, 31,
1673 0x1befbf06); 1493 0x1befbf06);
1674 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1494 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1675 DIF_SRC_GAIN_CONTROL, 0, 31, 1495 DIF_SRC_GAIN_CONTROL, 0, 31,
1676 0x000035e8); 1496 0x000035e8);
1677 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1497 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1678 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1498 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1679 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1499 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1680 DIF_VIDEO_AGC_CTRL, 0, 31, 1500 DIF_VIDEO_AGC_CTRL, 0, 31,
1681 0xf2560000); 1501 0xf2560000);
1682 1502
@@ -1694,91 +1514,78 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1694 the pll freq word is 0x03420c49 1514 the pll freq word is 0x03420c49
1695 */ 1515 */
1696 1516
1697 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1517 status = vid_blk_write_word(dev, DIF_PLL_CTRL, 0x6503BC0C);
1698 DIF_PLL_CTRL, 2, 0x6503BC0C, 4); 1518 status = vid_blk_write_word(dev, DIF_PLL_CTRL1, 0xBD038C85);
1699 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1519 status = vid_blk_write_word(dev, DIF_PLL_CTRL2, 0x1DB4640A);
1700 DIF_PLL_CTRL1, 2, 0xBD038C85, 4); 1520 status = vid_blk_write_word(dev, DIF_PLL_CTRL3, 0x00008800);
1701 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1521 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, 0x444C0380);
1702 DIF_PLL_CTRL2, 2, 0x1DB4640A, 4); 1522 status = vid_blk_write_word(dev, DIF_AGC_IF_INT_CURRENT,
1703 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1523 0x26001700);
1704 DIF_PLL_CTRL3, 2, 0x00008800, 4); 1524 status = vid_blk_write_word(dev, DIF_AGC_RF_CURRENT,
1705 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1525 0x00002660);
1706 DIF_AGC_IF_REF, 2, 0x444C0380, 4); 1526 status = vid_blk_write_word(dev, DIF_VIDEO_AGC_CTRL,
1707 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1527 0x04000800);
1708 DIF_AGC_IF_INT_CURRENT, 2, 1528 status = vid_blk_write_word(dev, DIF_VID_AUD_OVERRIDE,
1709 0x26001700, 4); 1529 0x27000100);
1710 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1530 status = vid_blk_write_word(dev, DIF_AV_SEP_CTRL, 0x01296e1f);
1711 DIF_AGC_RF_CURRENT, 2, 0x00002660, 1531
1712 4); 1532 status = vid_blk_write_word(dev, DIF_COMP_FLT_CTRL,
1713 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1533 0x009f50c1);
1714 DIF_VIDEO_AGC_CTRL, 2, 0x04000800, 1534 status = vid_blk_write_word(dev, DIF_SRC_PHASE_INC,
1715 4); 1535 0x1befbf06);
1716 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1536 status = vid_blk_write_word(dev, DIF_SRC_GAIN_CONTROL,
1717 DIF_VID_AUD_OVERRIDE, 2, 0x27000100, 1537 0x000035e8);
1718 4); 1538
1719 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1539 status = vid_blk_write_word(dev, DIF_AGC_CTRL_IF, 0xC2262600);
1720 DIF_AV_SEP_CTRL, 2, 0x01296e1f, 4); 1540 status = vid_blk_write_word(dev, DIF_AGC_CTRL_INT,
1721 1541 0xC2262600);
1722 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1542 status = vid_blk_write_word(dev, DIF_AGC_CTRL_RF, 0xC2262600);
1723 DIF_COMP_FLT_CTRL, 2, 0x009f50c1, 4);
1724 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1725 DIF_SRC_PHASE_INC, 2, 0x1befbf06, 4);
1726 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1727 DIF_SRC_GAIN_CONTROL, 2, 0x000035e8,
1728 4);
1729
1730 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1731 DIF_AGC_CTRL_IF, 2, 0xC2262600, 4);
1732 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1733 DIF_AGC_CTRL_INT, 2, 0xC2262600, 4);
1734 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1735 DIF_AGC_CTRL_RF, 2, 0xC2262600, 4);
1736 1543
1737 /* Save the Spec Inversion value */ 1544 /* Save the Spec Inversion value */
1738 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1545 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1739 dif_misc_ctrl_value |= 0x3a003F10; 1546 dif_misc_ctrl_value |= 0x3a003F10;
1740 } else { 1547 } else {
1741 /* default PAL BG */ 1548 /* default PAL BG */
1742 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1549 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1743 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1550 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1744 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1551 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1745 DIF_PLL_CTRL1, 0, 31, 0xbd038c85); 1552 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1746 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1553 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1747 DIF_PLL_CTRL2, 0, 31, 0x1db4640a); 1554 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1748 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1555 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1749 DIF_PLL_CTRL3, 0, 31, 0x00008800); 1556 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1750 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1557 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1751 DIF_AGC_IF_REF, 0, 31, 0x444C1380); 1558 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1752 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1559 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1753 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600); 1560 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1754 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1561 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1755 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700); 1562 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1756 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1563 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1757 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600); 1564 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1758 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1565 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1759 DIF_AGC_IF_INT_CURRENT, 0, 31, 1566 DIF_AGC_IF_INT_CURRENT, 0, 31,
1760 0x26001700); 1567 0x26001700);
1761 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1568 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1762 DIF_AGC_RF_CURRENT, 0, 31, 1569 DIF_AGC_RF_CURRENT, 0, 31,
1763 0x00002660); 1570 0x00002660);
1764 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1571 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1765 DIF_VIDEO_AGC_CTRL, 0, 31, 1572 DIF_VIDEO_AGC_CTRL, 0, 31,
1766 0x72500800); 1573 0x72500800);
1767 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1574 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1768 DIF_VID_AUD_OVERRIDE, 0, 31, 1575 DIF_VID_AUD_OVERRIDE, 0, 31,
1769 0x27000100); 1576 0x27000100);
1770 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1577 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1771 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC); 1578 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
1772 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1579 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1773 DIF_COMP_FLT_CTRL, 0, 31, 1580 DIF_COMP_FLT_CTRL, 0, 31,
1774 0x00A653A8); 1581 0x00A653A8);
1775 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1582 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1776 DIF_SRC_PHASE_INC, 0, 31, 1583 DIF_SRC_PHASE_INC, 0, 31,
1777 0x1befbf06); 1584 0x1befbf06);
1778 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1585 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1779 DIF_SRC_GAIN_CONTROL, 0, 31, 1586 DIF_SRC_GAIN_CONTROL, 0, 31,
1780 0x000035e8); 1587 0x000035e8);
1781 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1588 status = cx231xx_reg_mask_write(dev, VID_BLK_I2C_ADDRESS, 32,
1782 DIF_RPT_VARIANCE, 0, 31, 0x00000000); 1589 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1783 /* Save the Spec Inversion value */ 1590 /* Save the Spec Inversion value */
1784 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1591 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
@@ -1796,9 +1603,7 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1796 dif_misc_ctrl_value = 0x7a080000; 1603 dif_misc_ctrl_value = 0x7a080000;
1797 1604
1798 /* Write the calculated value for misc ontrol register */ 1605 /* Write the calculated value for misc ontrol register */
1799 status = 1606 status = vid_blk_write_word(dev, DIF_MISC_CTRL, dif_misc_ctrl_value);
1800 cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, DIF_MISC_CTRL,
1801 2, dif_misc_ctrl_value, 4);
1802 1607
1803 return status; 1608 return status;
1804} 1609}
@@ -1809,13 +1614,11 @@ int cx231xx_tuner_pre_channel_change(struct cx231xx *dev)
1809 u32 dwval; 1614 u32 dwval;
1810 1615
1811 /* Set the RF and IF k_agc values to 3 */ 1616 /* Set the RF and IF k_agc values to 3 */
1812 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1617 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
1813 DIF_AGC_IF_REF, 2, &dwval, 4);
1814 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); 1618 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
1815 dwval |= 0x33000000; 1619 dwval |= 0x33000000;
1816 1620
1817 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1621 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
1818 DIF_AGC_IF_REF, 2, dwval, 4);
1819 1622
1820 return status; 1623 return status;
1821} 1624}
@@ -1827,8 +1630,7 @@ int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
1827 1630
1828 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for 1631 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
1829 * SECAM L/B/D standards */ 1632 * SECAM L/B/D standards */
1830 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1633 status = vid_blk_read_word(dev, DIF_AGC_IF_REF, &dwval);
1831 DIF_AGC_IF_REF, 2, &dwval, 4);
1832 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); 1634 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
1833 1635
1834 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B | 1636 if (dev->norm & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_B |
@@ -1837,63 +1639,62 @@ int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
1837 else 1639 else
1838 dwval |= 0x44000000; 1640 dwval |= 0x44000000;
1839 1641
1840 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1642 status = vid_blk_write_word(dev, DIF_AGC_IF_REF, dwval);
1841 DIF_AGC_IF_REF, 2, dwval, 4);
1842 1643
1843 return status; 1644 return status;
1844} 1645}
1845 1646
1846/****************************************************************************** 1647/******************************************************************************
1847 * F L A T I R O N - B L O C K C O N T R O L functions * 1648 * I 2 S - B L O C K C O N T R O L functions *
1848 ******************************************************************************/ 1649 ******************************************************************************/
1849int cx231xx_flatiron_initialize(struct cx231xx *dev) 1650int cx231xx_i2s_blk_initialize(struct cx231xx *dev)
1850{ 1651{
1851 int status = 0; 1652 int status = 0;
1852 u32 value; 1653 u32 value;
1853 1654
1854 status = cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS, 1655 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1855 CH_PWR_CTRL1, 1, &value, 1); 1656 CH_PWR_CTRL1, 1, &value, 1);
1856 /* enables clock to delta-sigma and decimation filter */ 1657 /* enables clock to delta-sigma and decimation filter */
1857 value |= 0x80; 1658 value |= 0x80;
1858 status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, 1659 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1859 CH_PWR_CTRL1, 1, value, 1); 1660 CH_PWR_CTRL1, 1, value, 1);
1860 /* power up all channel */ 1661 /* power up all channel */
1861 status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, 1662 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1862 CH_PWR_CTRL2, 1, 0x00, 1); 1663 CH_PWR_CTRL2, 1, 0x00, 1);
1863 1664
1864 return status; 1665 return status;
1865} 1666}
1866 1667
1867int cx231xx_flatiron_update_power_control(struct cx231xx *dev, 1668int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
1868 enum AV_MODE avmode) 1669 enum AV_MODE avmode)
1869{ 1670{
1870 int status = 0; 1671 int status = 0;
1871 u32 value = 0; 1672 u32 value = 0;
1872 1673
1873 if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) { 1674 if (avmode != POLARIS_AVMODE_ENXTERNAL_AV) {
1874 status = cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS, 1675 status = cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1875 CH_PWR_CTRL2, 1, &value, 1); 1676 CH_PWR_CTRL2, 1, &value, 1);
1876 value |= 0xfe; 1677 value |= 0xfe;
1877 status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, 1678 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1878 CH_PWR_CTRL2, 1, value, 1); 1679 CH_PWR_CTRL2, 1, value, 1);
1879 } else { 1680 } else {
1880 status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, 1681 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1881 CH_PWR_CTRL2, 1, 0x00, 1); 1682 CH_PWR_CTRL2, 1, 0x00, 1);
1882 } 1683 }
1883 1684
1884 return status; 1685 return status;
1885} 1686}
1886 1687
1887/* set flatiron for audio input types */ 1688/* set i2s_blk for audio input types */
1888int cx231xx_flatiron_set_audio_input(struct cx231xx *dev, u8 audio_input) 1689int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input)
1889{ 1690{
1890 int status = 0; 1691 int status = 0;
1891 1692
1892 switch (audio_input) { 1693 switch (audio_input) {
1893 case CX231XX_AMUX_LINE_IN: 1694 case CX231XX_AMUX_LINE_IN:
1894 status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, 1695 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1895 CH_PWR_CTRL2, 1, 0x00, 1); 1696 CH_PWR_CTRL2, 1, 0x00, 1);
1896 status = cx231xx_write_i2c_data(dev, Flatrion_DEVICE_ADDRESS, 1697 status = cx231xx_write_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1897 CH_PWR_CTRL1, 1, 0x80, 1); 1698 CH_PWR_CTRL1, 1, 0x80, 1);
1898 break; 1699 break;
1899 case CX231XX_AMUX_VIDEO: 1700 case CX231XX_AMUX_VIDEO:
@@ -2114,11 +1915,11 @@ int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
2114 msleep(PWR_SLEEP_INTERVAL); 1915 msleep(PWR_SLEEP_INTERVAL);
2115 } 1916 }
2116 1917
2117 /* update power control for colibri */ 1918 /* update power control for afe */
2118 status = cx231xx_colibri_update_power_control(dev, mode); 1919 status = cx231xx_afe_update_power_control(dev, mode);
2119 1920
2120 /* update power control for flatiron */ 1921 /* update power control for i2s_blk */
2121 status = cx231xx_flatiron_update_power_control(dev, mode); 1922 status = cx231xx_i2s_blk_update_power_control(dev, mode);
2122 1923
2123 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value, 1924 status = cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, PWR_CTL_EN, value,
2124 4); 1925 4);
diff --git a/drivers/media/video/cx231xx/cx231xx-core.c b/drivers/media/video/cx231xx/cx231xx-core.c
index 80deffee984a..d0a4d4ddeb8a 100644
--- a/drivers/media/video/cx231xx/cx231xx-core.c
+++ b/drivers/media/video/cx231xx/cx231xx-core.c
@@ -883,7 +883,7 @@ int cx231xx_dev_init(struct cx231xx *dev)
883 883
884 /* init hardware */ 884 /* init hardware */
885 /* Note : with out calling set power mode function, 885 /* Note : with out calling set power mode function,
886 colibri can not be set up correctly */ 886 afe can not be set up correctly */
887 errCode = cx231xx_set_power_mode(dev, POLARIS_AVMODE_ANALOGT_TV); 887 errCode = cx231xx_set_power_mode(dev, POLARIS_AVMODE_ANALOGT_TV);
888 if (errCode < 0) { 888 if (errCode < 0) {
889 cx231xx_errdev 889 cx231xx_errdev
@@ -893,17 +893,17 @@ int cx231xx_dev_init(struct cx231xx *dev)
893 } 893 }
894 894
895 /* initialize Colibri block */ 895 /* initialize Colibri block */
896 errCode = cx231xx_colibri_init_super_block(dev, 0x23c); 896 errCode = cx231xx_afe_init_super_block(dev, 0x23c);
897 if (errCode < 0) { 897 if (errCode < 0) {
898 cx231xx_errdev 898 cx231xx_errdev
899 ("%s: cx231xx_colibri init super block - errCode [%d]!\n", 899 ("%s: cx231xx_afe init super block - errCode [%d]!\n",
900 __func__, errCode); 900 __func__, errCode);
901 return errCode; 901 return errCode;
902 } 902 }
903 errCode = cx231xx_colibri_init_channels(dev); 903 errCode = cx231xx_afe_init_channels(dev);
904 if (errCode < 0) { 904 if (errCode < 0) {
905 cx231xx_errdev 905 cx231xx_errdev
906 ("%s: cx231xx_colibri init channels - errCode [%d]!\n", 906 ("%s: cx231xx_afe init channels - errCode [%d]!\n",
907 __func__, errCode); 907 __func__, errCode);
908 return errCode; 908 return errCode;
909 } 909 }
@@ -917,11 +917,11 @@ int cx231xx_dev_init(struct cx231xx *dev)
917 return errCode; 917 return errCode;
918 } 918 }
919 919
920 /* flatiron related functions */ 920 /* I2S block related functions */
921 errCode = cx231xx_flatiron_initialize(dev); 921 errCode = cx231xx_i2s_blk_initialize(dev);
922 if (errCode < 0) { 922 if (errCode < 0) {
923 cx231xx_errdev 923 cx231xx_errdev
924 ("%s: cx231xx_flatiron initialize - errCode [%d]!\n", 924 ("%s: cx231xx_i2s block initialize - errCode [%d]!\n",
925 __func__, errCode); 925 __func__, errCode);
926 return errCode; 926 return errCode;
927 } 927 }
diff --git a/drivers/media/video/cx231xx/cx231xx-pcb-cfg.h b/drivers/media/video/cx231xx/cx231xx-pcb-cfg.h
index 86fec113f5c5..f5e46e89f3ab 100644
--- a/drivers/media/video/cx231xx/cx231xx-pcb-cfg.h
+++ b/drivers/media/video/cx231xx/cx231xx-pcb-cfg.h
@@ -91,10 +91,10 @@ enum TS_PORT{
91#define EAVP_MASK 0x8 91#define EAVP_MASK 0x8
92enum EAV_PRESENT{ 92enum EAV_PRESENT{
93 NO_EXTERNAL_AV = 0x0, /* 0: No External A/V inputs 93 NO_EXTERNAL_AV = 0x0, /* 0: No External A/V inputs
94 (no need for Flatiron), 94 (no need for i2s blcok),
95 Analog Tuner must be present */ 95 Analog Tuner must be present */
96 EXTERNAL_AV = 0x8 /* 1: External A/V inputs 96 EXTERNAL_AV = 0x8 /* 1: External A/V inputs
97 present (requires Flatiron) */ 97 present (requires i2s blk) */
98}; 98};
99 99
100#define ATM_MASK 0x30 100#define ATM_MASK 0x30
@@ -123,10 +123,6 @@ enum AVDEC_STATUS{
123}; 123};
124 124
125#define BO_1_MASK 0x100 125#define BO_1_MASK 0x100
126enum HAMMERHEAD__STATUS{
127 HAMMERHEAD_ONLY = 0x0, /* 0:Hammerhead Only */
128 HAMMERHEAD_SC = 0x100 /* 1:Hammerhead and SC */
129};
130 126
131#define BUSPOWER_MASK 0xC4 /* for Polaris spec 0.8 */ 127#define BUSPOWER_MASK 0xC4 /* for Polaris spec 0.8 */
132#define SELFPOWER_MASK 0x86 128#define SELFPOWER_MASK 0x86
diff --git a/drivers/media/video/cx231xx/cx231xx-video.c b/drivers/media/video/cx231xx/cx231xx-video.c
index 65430ecc180c..c8d6e9a04723 100644
--- a/drivers/media/video/cx231xx/cx231xx-video.c
+++ b/drivers/media/video/cx231xx/cx231xx-video.c
@@ -1421,36 +1421,36 @@ static int vidioc_g_register(struct file *file, void *priv,
1421 reg->val = value[0] | value[1] << 8 | 1421 reg->val = value[0] | value[1] << 8 |
1422 value[2] << 16 | value[3] << 24; 1422 value[2] << 16 | value[3] << 24;
1423 break; 1423 break;
1424 case 1: /* Colibri - read byte */ 1424 case 1: /* AFE - read byte */
1425 ret = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, 1425 ret = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
1426 (u16)reg->reg, 2, &data, 1); 1426 (u16)reg->reg, 2, &data, 1);
1427 reg->val = le32_to_cpu(data & 0xff); 1427 reg->val = le32_to_cpu(data & 0xff);
1428 break; 1428 break;
1429 case 14: /* Colibri - read dword */ 1429 case 14: /* AFE - read dword */
1430 ret = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, 1430 ret = cx231xx_read_i2c_data(dev, AFE_DEVICE_ADDRESS,
1431 (u16)reg->reg, 2, &data, 4); 1431 (u16)reg->reg, 2, &data, 4);
1432 reg->val = le32_to_cpu(data); 1432 reg->val = le32_to_cpu(data);
1433 break; 1433 break;
1434 case 2: /* Hammerhead - read byte */ 1434 case 2: /* Video Block - read byte */
1435 ret = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1435 ret = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
1436 (u16)reg->reg, 2, &data, 1); 1436 (u16)reg->reg, 2, &data, 1);
1437 reg->val = le32_to_cpu(data & 0xff); 1437 reg->val = le32_to_cpu(data & 0xff);
1438 break; 1438 break;
1439 case 24: /* Hammerhead - read dword */ 1439 case 24: /* Video Block - read dword */
1440 ret = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1440 ret = cx231xx_read_i2c_data(dev, VID_BLK_I2C_ADDRESS,
1441 (u16)reg->reg, 2, &data, 4); 1441 (u16)reg->reg, 2, &data, 4);
1442 reg->val = le32_to_cpu(data); 1442 reg->val = le32_to_cpu(data);
1443 break; 1443 break;
1444 case 3: /* flatiron - read byte */ 1444 case 3: /* I2S block - read byte */
1445 ret = cx231xx_read_i2c_data(dev, 1445 ret = cx231xx_read_i2c_data(dev,
1446 Flatrion_DEVICE_ADDRESS, 1446 I2S_BLK_DEVICE_ADDRESS,
1447 (u16)reg->reg, 1, 1447 (u16)reg->reg, 1,
1448 &data, 1); 1448 &data, 1);
1449 reg->val = le32_to_cpu(data & 0xff); 1449 reg->val = le32_to_cpu(data & 0xff);
1450 break; 1450 break;
1451 case 34: /* flatiron - read dword */ 1451 case 34: /* I2S Block - read dword */
1452 ret = 1452 ret =
1453 cx231xx_read_i2c_data(dev, Flatrion_DEVICE_ADDRESS, 1453 cx231xx_read_i2c_data(dev, I2S_BLK_DEVICE_ADDRESS,
1454 (u16)reg->reg, 1, &data, 4); 1454 (u16)reg->reg, 1, &data, 4);
1455 reg->val = le32_to_cpu(data); 1455 reg->val = le32_to_cpu(data);
1456 break; 1456 break;
@@ -1503,43 +1503,43 @@ static int vidioc_s_register(struct file *file, void *priv,
1503 (u16)reg->reg, data, 1503 (u16)reg->reg, data,
1504 4); 1504 4);
1505 break; 1505 break;
1506 case 1: /* Colibri - read byte */ 1506 case 1: /* AFE - read byte */
1507 ret = cx231xx_write_i2c_data(dev, 1507 ret = cx231xx_write_i2c_data(dev,
1508 Colibri_DEVICE_ADDRESS, 1508 AFE_DEVICE_ADDRESS,
1509 (u16)reg->reg, 2, 1509 (u16)reg->reg, 2,
1510 value, 1); 1510 value, 1);
1511 break; 1511 break;
1512 case 14: /* Colibri - read dword */ 1512 case 14: /* AFE - read dword */
1513 ret = cx231xx_write_i2c_data(dev, 1513 ret = cx231xx_write_i2c_data(dev,
1514 Colibri_DEVICE_ADDRESS, 1514 AFE_DEVICE_ADDRESS,
1515 (u16)reg->reg, 2, 1515 (u16)reg->reg, 2,
1516 value, 4); 1516 value, 4);
1517 break; 1517 break;
1518 case 2: /* Hammerhead - read byte */ 1518 case 2: /* Video Block - read byte */
1519 ret = 1519 ret =
1520 cx231xx_write_i2c_data(dev, 1520 cx231xx_write_i2c_data(dev,
1521 HAMMERHEAD_I2C_ADDRESS, 1521 VID_BLK_I2C_ADDRESS,
1522 (u16)reg->reg, 2, 1522 (u16)reg->reg, 2,
1523 value, 1); 1523 value, 1);
1524 break; 1524 break;
1525 case 24: /* Hammerhead - read dword */ 1525 case 24: /* Video Block - read dword */
1526 ret = 1526 ret =
1527 cx231xx_write_i2c_data(dev, 1527 cx231xx_write_i2c_data(dev,
1528 HAMMERHEAD_I2C_ADDRESS, 1528 VID_BLK_I2C_ADDRESS,
1529 (u16)reg->reg, 2, 1529 (u16)reg->reg, 2,
1530 value, 4); 1530 value, 4);
1531 break; 1531 break;
1532 case 3: /* flatiron - read byte */ 1532 case 3: /* I2S block - read byte */
1533 ret = 1533 ret =
1534 cx231xx_write_i2c_data(dev, 1534 cx231xx_write_i2c_data(dev,
1535 Flatrion_DEVICE_ADDRESS, 1535 I2S_BLK_DEVICE_ADDRESS,
1536 (u16)reg->reg, 1, 1536 (u16)reg->reg, 1,
1537 value, 1); 1537 value, 1);
1538 break; 1538 break;
1539 case 34: /* flatiron - read dword */ 1539 case 34: /* I2S block - read dword */
1540 ret = 1540 ret =
1541 cx231xx_write_i2c_data(dev, 1541 cx231xx_write_i2c_data(dev,
1542 Flatrion_DEVICE_ADDRESS, 1542 I2S_BLK_DEVICE_ADDRESS,
1543 (u16)reg->reg, 1, 1543 (u16)reg->reg, 1,
1544 value, 4); 1544 value, 4);
1545 break; 1545 break;
diff --git a/drivers/media/video/cx231xx/cx231xx.h b/drivers/media/video/cx231xx/cx231xx.h
index d658e3599d86..aa4a23ef491a 100644
--- a/drivers/media/video/cx231xx/cx231xx.h
+++ b/drivers/media/video/cx231xx/cx231xx.h
@@ -46,9 +46,9 @@
46#define PWR_SLEEP_INTERVAL 5 46#define PWR_SLEEP_INTERVAL 5
47 47
48/* I2C addresses for control block in Cx231xx */ 48/* I2C addresses for control block in Cx231xx */
49#define Colibri_DEVICE_ADDRESS 0x60 49#define AFE_DEVICE_ADDRESS 0x60
50#define Flatrion_DEVICE_ADDRESS 0x98 50#define I2S_BLK_DEVICE_ADDRESS 0x98
51#define HAMMERHEAD_I2C_ADDRESS 0x88 51#define VID_BLK_I2C_ADDRESS 0x88
52#define DIF_USE_BASEBAND 0xFFFFFFFF 52#define DIF_USE_BASEBAND 0xFFFFFFFF
53 53
54/* Boards supported by driver */ 54/* Boards supported by driver */
@@ -540,9 +540,9 @@ struct cx231xx {
540 /* Power Modes */ 540 /* Power Modes */
541 int power_mode; 541 int power_mode;
542 542
543 /* colibri parameters */ 543 /* afe parameters */
544 enum AFE_MODE colibri_mode; 544 enum AFE_MODE afe_mode;
545 u32 colibri_ref_count; 545 u32 afe_ref_count;
546 546
547 /* video related parameters */ 547 /* video related parameters */
548 u32 video_input; 548 u32 video_input;
@@ -588,21 +588,21 @@ int cx231xx_read_modify_write_i2c_dword(struct cx231xx *dev, u8 dev_addr,
588 u16 saddr, u32 mask, u32 value); 588 u16 saddr, u32 mask, u32 value);
589u32 cx231xx_set_field(u32 field_mask, u32 data); 589u32 cx231xx_set_field(u32 field_mask, u32 data);
590 590
591/* Colibri related functions */ 591/* afe related functions */
592int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count); 592int cx231xx_afe_init_super_block(struct cx231xx *dev, u32 ref_count);
593int cx231xx_colibri_init_channels(struct cx231xx *dev); 593int cx231xx_afe_init_channels(struct cx231xx *dev);
594int cx231xx_colibri_setup_AFE_for_baseband(struct cx231xx *dev); 594int cx231xx_afe_setup_AFE_for_baseband(struct cx231xx *dev);
595int cx231xx_colibri_set_input_mux(struct cx231xx *dev, u32 input_mux); 595int cx231xx_afe_set_input_mux(struct cx231xx *dev, u32 input_mux);
596int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode); 596int cx231xx_afe_set_mode(struct cx231xx *dev, enum AFE_MODE mode);
597int cx231xx_colibri_update_power_control(struct cx231xx *dev, 597int cx231xx_afe_update_power_control(struct cx231xx *dev,
598 enum AV_MODE avmode); 598 enum AV_MODE avmode);
599int cx231xx_colibri_adjust_ref_count(struct cx231xx *dev, u32 video_input); 599int cx231xx_afe_adjust_ref_count(struct cx231xx *dev, u32 video_input);
600 600
601/* flatiron related functions */ 601/* i2s block related functions */
602int cx231xx_flatiron_initialize(struct cx231xx *dev); 602int cx231xx_i2s_blk_initialize(struct cx231xx *dev);
603int cx231xx_flatiron_update_power_control(struct cx231xx *dev, 603int cx231xx_i2s_blk_update_power_control(struct cx231xx *dev,
604 enum AV_MODE avmode); 604 enum AV_MODE avmode);
605int cx231xx_flatiron_set_audio_input(struct cx231xx *dev, u8 audio_input); 605int cx231xx_i2s_blk_set_audio_input(struct cx231xx *dev, u8 audio_input);
606 606
607/* DIF related functions */ 607/* DIF related functions */
608int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode, 608int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 11:37:25 -0500