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authorJavier Martin <javier.martin@vista-silicon.com>2012-07-26 04:53:35 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2012-08-06 08:02:23 -0400
commit186b250a07253770717f41eee911b8c5467be04e (patch)
tree87cfd2cdc921acb8aeccd84afe8aa2bbb8c615fa /drivers/media/video
parent6d8c4529f8058b4e8c902fe689786877f2224060 (diff)
[media] media: coda: Add driver for Coda video codec
Coda is a range of video codecs from Chips&Media that support H.264, H.263, MPEG4 and other video standards. Currently only support for the codadx6 included in the i.MX27 SoC is added. H.264 and MPEG4 video encoding are the only supported capabilities by now. [mchehab@redhat.com: Add missing include linux/of.h] Signed-off-by: Javier Martin <javier.martin@vista-silicon.com> Reviewed-by: Philipp Zabel<p.zabel@pengutronix.de> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/video')
-rw-r--r--drivers/media/video/Kconfig9
-rw-r--r--drivers/media/video/Makefile1
-rw-r--r--drivers/media/video/coda.c1849
-rw-r--r--drivers/media/video/coda.h216
4 files changed, 2075 insertions, 0 deletions
diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
index c128fac0ce2c..c95954d9692b 100644
--- a/drivers/media/video/Kconfig
+++ b/drivers/media/video/Kconfig
@@ -1224,6 +1224,15 @@ config VIDEO_MEM2MEM_TESTDEV
1224 This is a virtual test device for the memory-to-memory driver 1224 This is a virtual test device for the memory-to-memory driver
1225 framework. 1225 framework.
1226 1226
1227config VIDEO_CODA
1228 tristate "Chips&Media Coda multi-standard codec IP"
1229 depends on VIDEO_DEV && VIDEO_V4L2
1230 select VIDEOBUF2_DMA_CONTIG
1231 select V4L2_MEM2MEM_DEV
1232 ---help---
1233 Coda is a range of video codec IPs that supports
1234 H.264, MPEG-4, and other video formats.
1235
1227config VIDEO_SAMSUNG_S5P_G2D 1236config VIDEO_SAMSUNG_S5P_G2D
1228 tristate "Samsung S5P and EXYNOS4 G2D 2d graphics accelerator driver" 1237 tristate "Samsung S5P and EXYNOS4 G2D 2d graphics accelerator driver"
1229 depends on VIDEO_DEV && VIDEO_V4L2 && PLAT_S5P 1238 depends on VIDEO_DEV && VIDEO_V4L2 && PLAT_S5P
diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
index b7da9faa3b0a..09f704a7f47c 100644
--- a/drivers/media/video/Makefile
+++ b/drivers/media/video/Makefile
@@ -188,6 +188,7 @@ obj-$(CONFIG_VIDEO_OMAP1) += omap1_camera.o
188obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel-isi.o 188obj-$(CONFIG_VIDEO_ATMEL_ISI) += atmel-isi.o
189 189
190obj-$(CONFIG_VIDEO_MX2_EMMAPRP) += mx2_emmaprp.o 190obj-$(CONFIG_VIDEO_MX2_EMMAPRP) += mx2_emmaprp.o
191obj-$(CONFIG_VIDEO_CODA) += coda.o
191 192
192obj-$(CONFIG_VIDEO_SAMSUNG_S5P_FIMC) += s5p-fimc/ 193obj-$(CONFIG_VIDEO_SAMSUNG_S5P_FIMC) += s5p-fimc/
193obj-$(CONFIG_VIDEO_SAMSUNG_S5P_JPEG) += s5p-jpeg/ 194obj-$(CONFIG_VIDEO_SAMSUNG_S5P_JPEG) += s5p-jpeg/
diff --git a/drivers/media/video/coda.c b/drivers/media/video/coda.c
new file mode 100644
index 000000000000..0d6e0a095607
--- /dev/null
+++ b/drivers/media/video/coda.c
@@ -0,0 +1,1849 @@
1/*
2 * Coda multi-standard codec IP
3 *
4 * Copyright (C) 2012 Vista Silicon S.L.
5 * Javier Martin, <javier.martin@vista-silicon.com>
6 * Xavier Duret
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/firmware.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/irq.h>
20#include <linux/module.h>
21#include <linux/of_device.h>
22#include <linux/platform_device.h>
23#include <linux/slab.h>
24#include <linux/videodev2.h>
25#include <linux/of.h>
26
27#include <media/v4l2-ctrls.h>
28#include <media/v4l2-device.h>
29#include <media/v4l2-ioctl.h>
30#include <media/v4l2-mem2mem.h>
31#include <media/videobuf2-core.h>
32#include <media/videobuf2-dma-contig.h>
33
34#include "coda.h"
35
36#define CODA_NAME "coda"
37
38#define CODA_MAX_INSTANCES 4
39
40#define CODA_FMO_BUF_SIZE 32
41#define CODADX6_WORK_BUF_SIZE (288 * 1024 + CODA_FMO_BUF_SIZE * 8 * 1024)
42#define CODA7_WORK_BUF_SIZE (512 * 1024 + CODA_FMO_BUF_SIZE * 8 * 1024)
43#define CODA_PARA_BUF_SIZE (10 * 1024)
44#define CODA_ISRAM_SIZE (2048 * 2)
45
46#define CODA_OUTPUT_BUFS 4
47#define CODA_CAPTURE_BUFS 2
48
49#define MAX_W 720
50#define MAX_H 576
51#define CODA_MAX_FRAME_SIZE 0x90000
52#define FMO_SLICE_SAVE_BUF_SIZE (32)
53#define CODA_DEFAULT_GAMMA 4096
54
55#define MIN_W 176
56#define MIN_H 144
57#define MAX_W 720
58#define MAX_H 576
59
60#define S_ALIGN 1 /* multiple of 2 */
61#define W_ALIGN 1 /* multiple of 2 */
62#define H_ALIGN 1 /* multiple of 2 */
63
64#define fh_to_ctx(__fh) container_of(__fh, struct coda_ctx, fh)
65
66static int coda_debug;
67module_param(coda_debug, int, 0);
68MODULE_PARM_DESC(coda_debug, "Debug level (0-1)");
69
70enum {
71 V4L2_M2M_SRC = 0,
72 V4L2_M2M_DST = 1,
73};
74
75enum coda_fmt_type {
76 CODA_FMT_ENC,
77 CODA_FMT_RAW,
78};
79
80enum coda_inst_type {
81 CODA_INST_ENCODER,
82 CODA_INST_DECODER,
83};
84
85enum coda_product {
86 CODA_DX6 = 0xf001,
87};
88
89struct coda_fmt {
90 char *name;
91 u32 fourcc;
92 enum coda_fmt_type type;
93};
94
95struct coda_devtype {
96 char *firmware;
97 enum coda_product product;
98 struct coda_fmt *formats;
99 unsigned int num_formats;
100 size_t workbuf_size;
101};
102
103/* Per-queue, driver-specific private data */
104struct coda_q_data {
105 unsigned int width;
106 unsigned int height;
107 unsigned int sizeimage;
108 struct coda_fmt *fmt;
109};
110
111struct coda_aux_buf {
112 void *vaddr;
113 dma_addr_t paddr;
114 u32 size;
115};
116
117struct coda_dev {
118 struct v4l2_device v4l2_dev;
119 struct video_device vfd;
120 struct platform_device *plat_dev;
121 struct coda_devtype *devtype;
122
123 void __iomem *regs_base;
124 struct clk *clk_per;
125 struct clk *clk_ahb;
126
127 struct coda_aux_buf codebuf;
128 struct coda_aux_buf workbuf;
129
130 spinlock_t irqlock;
131 struct mutex dev_mutex;
132 struct v4l2_m2m_dev *m2m_dev;
133 struct vb2_alloc_ctx *alloc_ctx;
134 int instances;
135};
136
137struct coda_params {
138 u8 h264_intra_qp;
139 u8 h264_inter_qp;
140 u8 mpeg4_intra_qp;
141 u8 mpeg4_inter_qp;
142 u8 gop_size;
143 int codec_mode;
144 enum v4l2_mpeg_video_multi_slice_mode slice_mode;
145 u32 framerate;
146 u16 bitrate;
147 u32 slice_max_mb;
148};
149
150struct coda_ctx {
151 struct coda_dev *dev;
152 int aborting;
153 int rawstreamon;
154 int compstreamon;
155 u32 isequence;
156 struct coda_q_data q_data[2];
157 enum coda_inst_type inst_type;
158 enum v4l2_colorspace colorspace;
159 struct coda_params params;
160 struct v4l2_m2m_ctx *m2m_ctx;
161 struct v4l2_ctrl_handler ctrls;
162 struct v4l2_fh fh;
163 struct vb2_buffer *reference;
164 int gopcounter;
165 char vpu_header[3][64];
166 int vpu_header_size[3];
167 struct coda_aux_buf parabuf;
168 int idx;
169};
170
171static inline void coda_write(struct coda_dev *dev, u32 data, u32 reg)
172{
173 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
174 "%s: data=0x%x, reg=0x%x\n", __func__, data, reg);
175 writel(data, dev->regs_base + reg);
176}
177
178static inline unsigned int coda_read(struct coda_dev *dev, u32 reg)
179{
180 u32 data;
181 data = readl(dev->regs_base + reg);
182 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
183 "%s: data=0x%x, reg=0x%x\n", __func__, data, reg);
184 return data;
185}
186
187static inline unsigned long coda_isbusy(struct coda_dev *dev)
188{
189 return coda_read(dev, CODA_REG_BIT_BUSY);
190}
191
192static inline int coda_is_initialized(struct coda_dev *dev)
193{
194 return (coda_read(dev, CODA_REG_BIT_CUR_PC) != 0);
195}
196
197static int coda_wait_timeout(struct coda_dev *dev)
198{
199 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
200
201 while (coda_isbusy(dev)) {
202 if (time_after(jiffies, timeout))
203 return -ETIMEDOUT;
204 }
205 return 0;
206}
207
208static void coda_command_async(struct coda_ctx *ctx, int cmd)
209{
210 struct coda_dev *dev = ctx->dev;
211 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
212
213 coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
214 coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
215 coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
216}
217
218static int coda_command_sync(struct coda_ctx *ctx, int cmd)
219{
220 struct coda_dev *dev = ctx->dev;
221
222 coda_command_async(ctx, cmd);
223 return coda_wait_timeout(dev);
224}
225
226static struct coda_q_data *get_q_data(struct coda_ctx *ctx,
227 enum v4l2_buf_type type)
228{
229 switch (type) {
230 case V4L2_BUF_TYPE_VIDEO_OUTPUT:
231 return &(ctx->q_data[V4L2_M2M_SRC]);
232 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
233 return &(ctx->q_data[V4L2_M2M_DST]);
234 default:
235 BUG();
236 }
237 return NULL;
238}
239
240/*
241 * Add one array of supported formats for each version of Coda:
242 * i.MX27 -> codadx6
243 * i.MX51 -> coda7
244 * i.MX6 -> coda960
245 */
246static struct coda_fmt codadx6_formats[] = {
247 {
248 .name = "YUV 4:2:0 Planar",
249 .fourcc = V4L2_PIX_FMT_YUV420,
250 .type = CODA_FMT_RAW,
251 },
252 {
253 .name = "H264 Encoded Stream",
254 .fourcc = V4L2_PIX_FMT_H264,
255 .type = CODA_FMT_ENC,
256 },
257 {
258 .name = "MPEG4 Encoded Stream",
259 .fourcc = V4L2_PIX_FMT_MPEG4,
260 .type = CODA_FMT_ENC,
261 },
262};
263
264static struct coda_fmt *find_format(struct coda_dev *dev, struct v4l2_format *f)
265{
266 struct coda_fmt *formats = dev->devtype->formats;
267 int num_formats = dev->devtype->num_formats;
268 unsigned int k;
269
270 for (k = 0; k < num_formats; k++) {
271 if (formats[k].fourcc == f->fmt.pix.pixelformat)
272 break;
273 }
274
275 if (k == num_formats)
276 return NULL;
277
278 return &formats[k];
279}
280
281/*
282 * V4L2 ioctl() operations.
283 */
284static int vidioc_querycap(struct file *file, void *priv,
285 struct v4l2_capability *cap)
286{
287 strlcpy(cap->driver, CODA_NAME, sizeof(cap->driver));
288 strlcpy(cap->card, CODA_NAME, sizeof(cap->card));
289 strlcpy(cap->bus_info, CODA_NAME, sizeof(cap->bus_info));
290 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT
291 | V4L2_CAP_STREAMING;
292 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
293
294 return 0;
295}
296
297static int enum_fmt(void *priv, struct v4l2_fmtdesc *f,
298 enum coda_fmt_type type)
299{
300 struct coda_ctx *ctx = fh_to_ctx(priv);
301 struct coda_dev *dev = ctx->dev;
302 struct coda_fmt *formats = dev->devtype->formats;
303 struct coda_fmt *fmt;
304 int num_formats = dev->devtype->num_formats;
305 int i, num = 0;
306
307 for (i = 0; i < num_formats; i++) {
308 if (formats[i].type == type) {
309 if (num == f->index)
310 break;
311 ++num;
312 }
313 }
314
315 if (i < num_formats) {
316 fmt = &formats[i];
317 strlcpy(f->description, fmt->name, sizeof(f->description));
318 f->pixelformat = fmt->fourcc;
319 return 0;
320 }
321
322 /* Format not found */
323 return -EINVAL;
324}
325
326static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
327 struct v4l2_fmtdesc *f)
328{
329 return enum_fmt(priv, f, CODA_FMT_ENC);
330}
331
332static int vidioc_enum_fmt_vid_out(struct file *file, void *priv,
333 struct v4l2_fmtdesc *f)
334{
335 return enum_fmt(priv, f, CODA_FMT_RAW);
336}
337
338static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
339{
340 struct vb2_queue *vq;
341 struct coda_q_data *q_data;
342 struct coda_ctx *ctx = fh_to_ctx(priv);
343
344 vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
345 if (!vq)
346 return -EINVAL;
347
348 q_data = get_q_data(ctx, f->type);
349
350 f->fmt.pix.field = V4L2_FIELD_NONE;
351 f->fmt.pix.pixelformat = q_data->fmt->fourcc;
352 f->fmt.pix.width = q_data->width;
353 f->fmt.pix.height = q_data->height;
354 if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420)
355 f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 2);
356 else /* encoded formats h.264/mpeg4 */
357 f->fmt.pix.bytesperline = 0;
358
359 f->fmt.pix.sizeimage = q_data->sizeimage;
360 f->fmt.pix.colorspace = ctx->colorspace;
361
362 return 0;
363}
364
365static int vidioc_try_fmt(struct coda_dev *dev, struct v4l2_format *f)
366{
367 enum v4l2_field field;
368
369 field = f->fmt.pix.field;
370 if (field == V4L2_FIELD_ANY)
371 field = V4L2_FIELD_NONE;
372 else if (V4L2_FIELD_NONE != field)
373 return -EINVAL;
374
375 /* V4L2 specification suggests the driver corrects the format struct
376 * if any of the dimensions is unsupported */
377 f->fmt.pix.field = field;
378
379 if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_YUV420) {
380 v4l_bound_align_image(&f->fmt.pix.width, MIN_W, MAX_W,
381 W_ALIGN, &f->fmt.pix.height,
382 MIN_H, MAX_H, H_ALIGN, S_ALIGN);
383 f->fmt.pix.bytesperline = round_up(f->fmt.pix.width, 2);
384 f->fmt.pix.sizeimage = f->fmt.pix.height *
385 f->fmt.pix.bytesperline;
386 } else { /*encoded formats h.264/mpeg4 */
387 f->fmt.pix.bytesperline = 0;
388 f->fmt.pix.sizeimage = CODA_MAX_FRAME_SIZE;
389 }
390
391 return 0;
392}
393
394static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
395 struct v4l2_format *f)
396{
397 int ret;
398 struct coda_fmt *fmt;
399 struct coda_ctx *ctx = fh_to_ctx(priv);
400
401 fmt = find_format(ctx->dev, f);
402 /*
403 * Since decoding support is not implemented yet do not allow
404 * CODA_FMT_RAW formats in the capture interface.
405 */
406 if (!fmt || !(fmt->type == CODA_FMT_ENC))
407 f->fmt.pix.pixelformat = V4L2_PIX_FMT_H264;
408
409 f->fmt.pix.colorspace = ctx->colorspace;
410
411 ret = vidioc_try_fmt(ctx->dev, f);
412 if (ret < 0)
413 return ret;
414
415 return 0;
416}
417
418static int vidioc_try_fmt_vid_out(struct file *file, void *priv,
419 struct v4l2_format *f)
420{
421 struct coda_ctx *ctx = fh_to_ctx(priv);
422 struct coda_fmt *fmt;
423 int ret;
424
425 fmt = find_format(ctx->dev, f);
426 /*
427 * Since decoding support is not implemented yet do not allow
428 * CODA_FMT formats in the capture interface.
429 */
430 if (!fmt || !(fmt->type == CODA_FMT_RAW))
431 f->fmt.pix.pixelformat = V4L2_PIX_FMT_YUV420;
432
433 if (!f->fmt.pix.colorspace)
434 f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709;
435
436 ret = vidioc_try_fmt(ctx->dev, f);
437 if (ret < 0)
438 return ret;
439
440 return 0;
441}
442
443static int vidioc_s_fmt(struct coda_ctx *ctx, struct v4l2_format *f)
444{
445 struct coda_q_data *q_data;
446 struct vb2_queue *vq;
447 int ret;
448
449 vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
450 if (!vq)
451 return -EINVAL;
452
453 q_data = get_q_data(ctx, f->type);
454 if (!q_data)
455 return -EINVAL;
456
457 if (vb2_is_busy(vq)) {
458 v4l2_err(&ctx->dev->v4l2_dev, "%s queue busy\n", __func__);
459 return -EBUSY;
460 }
461
462 ret = vidioc_try_fmt(ctx->dev, f);
463 if (ret)
464 return ret;
465
466 q_data->fmt = find_format(ctx->dev, f);
467 q_data->width = f->fmt.pix.width;
468 q_data->height = f->fmt.pix.height;
469 if (q_data->fmt->fourcc == V4L2_PIX_FMT_YUV420) {
470 q_data->sizeimage = q_data->width * q_data->height * 3 / 2;
471 } else { /* encoded format h.264/mpeg-4 */
472 q_data->sizeimage = CODA_MAX_FRAME_SIZE;
473 }
474
475 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
476 "Setting format for type %d, wxh: %dx%d, fmt: %d\n",
477 f->type, q_data->width, q_data->height, q_data->fmt->fourcc);
478
479 return 0;
480}
481
482static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
483 struct v4l2_format *f)
484{
485 int ret;
486
487 ret = vidioc_try_fmt_vid_cap(file, priv, f);
488 if (ret)
489 return ret;
490
491 return vidioc_s_fmt(fh_to_ctx(priv), f);
492}
493
494static int vidioc_s_fmt_vid_out(struct file *file, void *priv,
495 struct v4l2_format *f)
496{
497 struct coda_ctx *ctx = fh_to_ctx(priv);
498 int ret;
499
500 ret = vidioc_try_fmt_vid_out(file, priv, f);
501 if (ret)
502 return ret;
503
504 ret = vidioc_s_fmt(fh_to_ctx(priv), f);
505 if (ret)
506 ctx->colorspace = f->fmt.pix.colorspace;
507
508 return ret;
509}
510
511static int vidioc_reqbufs(struct file *file, void *priv,
512 struct v4l2_requestbuffers *reqbufs)
513{
514 struct coda_ctx *ctx = fh_to_ctx(priv);
515
516 return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
517}
518
519static int vidioc_querybuf(struct file *file, void *priv,
520 struct v4l2_buffer *buf)
521{
522 struct coda_ctx *ctx = fh_to_ctx(priv);
523
524 return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
525}
526
527static int vidioc_qbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
528{
529 struct coda_ctx *ctx = fh_to_ctx(priv);
530
531 return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
532}
533
534static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *buf)
535{
536 struct coda_ctx *ctx = fh_to_ctx(priv);
537
538 return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
539}
540
541static int vidioc_streamon(struct file *file, void *priv,
542 enum v4l2_buf_type type)
543{
544 struct coda_ctx *ctx = fh_to_ctx(priv);
545
546 return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
547}
548
549static int vidioc_streamoff(struct file *file, void *priv,
550 enum v4l2_buf_type type)
551{
552 struct coda_ctx *ctx = fh_to_ctx(priv);
553
554 return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
555}
556
557static const struct v4l2_ioctl_ops coda_ioctl_ops = {
558 .vidioc_querycap = vidioc_querycap,
559
560 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
561 .vidioc_g_fmt_vid_cap = vidioc_g_fmt,
562 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
563 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
564
565 .vidioc_enum_fmt_vid_out = vidioc_enum_fmt_vid_out,
566 .vidioc_g_fmt_vid_out = vidioc_g_fmt,
567 .vidioc_try_fmt_vid_out = vidioc_try_fmt_vid_out,
568 .vidioc_s_fmt_vid_out = vidioc_s_fmt_vid_out,
569
570 .vidioc_reqbufs = vidioc_reqbufs,
571 .vidioc_querybuf = vidioc_querybuf,
572
573 .vidioc_qbuf = vidioc_qbuf,
574 .vidioc_dqbuf = vidioc_dqbuf,
575
576 .vidioc_streamon = vidioc_streamon,
577 .vidioc_streamoff = vidioc_streamoff,
578};
579
580/*
581 * Mem-to-mem operations.
582 */
583static void coda_device_run(void *m2m_priv)
584{
585 struct coda_ctx *ctx = m2m_priv;
586 struct coda_q_data *q_data_src, *q_data_dst;
587 struct vb2_buffer *src_buf, *dst_buf;
588 struct coda_dev *dev = ctx->dev;
589 int force_ipicture;
590 int quant_param = 0;
591 u32 picture_y, picture_cb, picture_cr;
592 u32 pic_stream_buffer_addr, pic_stream_buffer_size;
593 u32 dst_fourcc;
594
595 src_buf = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
596 dst_buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
597 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
598 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
599 dst_fourcc = q_data_dst->fmt->fourcc;
600
601 src_buf->v4l2_buf.sequence = ctx->isequence;
602 dst_buf->v4l2_buf.sequence = ctx->isequence;
603 ctx->isequence++;
604
605 /*
606 * Workaround coda firmware BUG that only marks the first
607 * frame as IDR. This is a problem for some decoders that can't
608 * recover when a frame is lost.
609 */
610 if (src_buf->v4l2_buf.sequence % ctx->params.gop_size) {
611 src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
612 src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
613 } else {
614 src_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
615 src_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
616 }
617
618 /*
619 * Copy headers at the beginning of the first frame for H.264 only.
620 * In MPEG4 they are already copied by the coda.
621 */
622 if (src_buf->v4l2_buf.sequence == 0) {
623 pic_stream_buffer_addr =
624 vb2_dma_contig_plane_dma_addr(dst_buf, 0) +
625 ctx->vpu_header_size[0] +
626 ctx->vpu_header_size[1] +
627 ctx->vpu_header_size[2];
628 pic_stream_buffer_size = CODA_MAX_FRAME_SIZE -
629 ctx->vpu_header_size[0] -
630 ctx->vpu_header_size[1] -
631 ctx->vpu_header_size[2];
632 memcpy(vb2_plane_vaddr(dst_buf, 0),
633 &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
634 memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0],
635 &ctx->vpu_header[1][0], ctx->vpu_header_size[1]);
636 memcpy(vb2_plane_vaddr(dst_buf, 0) + ctx->vpu_header_size[0] +
637 ctx->vpu_header_size[1], &ctx->vpu_header[2][0],
638 ctx->vpu_header_size[2]);
639 } else {
640 pic_stream_buffer_addr =
641 vb2_dma_contig_plane_dma_addr(dst_buf, 0);
642 pic_stream_buffer_size = CODA_MAX_FRAME_SIZE;
643 }
644
645 if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
646 force_ipicture = 1;
647 switch (dst_fourcc) {
648 case V4L2_PIX_FMT_H264:
649 quant_param = ctx->params.h264_intra_qp;
650 break;
651 case V4L2_PIX_FMT_MPEG4:
652 quant_param = ctx->params.mpeg4_intra_qp;
653 break;
654 default:
655 v4l2_warn(&ctx->dev->v4l2_dev,
656 "cannot set intra qp, fmt not supported\n");
657 break;
658 }
659 } else {
660 force_ipicture = 0;
661 switch (dst_fourcc) {
662 case V4L2_PIX_FMT_H264:
663 quant_param = ctx->params.h264_inter_qp;
664 break;
665 case V4L2_PIX_FMT_MPEG4:
666 quant_param = ctx->params.mpeg4_inter_qp;
667 break;
668 default:
669 v4l2_warn(&ctx->dev->v4l2_dev,
670 "cannot set inter qp, fmt not supported\n");
671 break;
672 }
673 }
674
675 /* submit */
676 coda_write(dev, 0, CODA_CMD_ENC_PIC_ROT_MODE);
677 coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
678
679
680 picture_y = vb2_dma_contig_plane_dma_addr(src_buf, 0);
681 picture_cb = picture_y + q_data_src->width * q_data_src->height;
682 picture_cr = picture_cb + q_data_src->width / 2 *
683 q_data_src->height / 2;
684
685 coda_write(dev, picture_y, CODA_CMD_ENC_PIC_SRC_ADDR_Y);
686 coda_write(dev, picture_cb, CODA_CMD_ENC_PIC_SRC_ADDR_CB);
687 coda_write(dev, picture_cr, CODA_CMD_ENC_PIC_SRC_ADDR_CR);
688 coda_write(dev, force_ipicture << 1 & 0x2,
689 CODA_CMD_ENC_PIC_OPTION);
690
691 coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
692 coda_write(dev, pic_stream_buffer_size / 1024,
693 CODA_CMD_ENC_PIC_BB_SIZE);
694 coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
695}
696
697static int coda_job_ready(void *m2m_priv)
698{
699 struct coda_ctx *ctx = m2m_priv;
700
701 /*
702 * For both 'P' and 'key' frame cases 1 picture
703 * and 1 frame are needed.
704 */
705 if (!v4l2_m2m_num_src_bufs_ready(ctx->m2m_ctx) ||
706 !v4l2_m2m_num_dst_bufs_ready(ctx->m2m_ctx)) {
707 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
708 "not ready: not enough video buffers.\n");
709 return 0;
710 }
711
712 /* For P frames a reference picture is needed too */
713 if ((ctx->gopcounter != (ctx->params.gop_size - 1)) &&
714 !ctx->reference) {
715 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
716 "not ready: reference picture not available.\n");
717 return 0;
718 }
719
720 if (coda_isbusy(ctx->dev)) {
721 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
722 "not ready: coda is still busy.\n");
723 return 0;
724 }
725
726 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
727 "job ready\n");
728 return 1;
729}
730
731static void coda_job_abort(void *priv)
732{
733 struct coda_ctx *ctx = priv;
734 struct coda_dev *dev = ctx->dev;
735
736 ctx->aborting = 1;
737
738 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
739 "Aborting task\n");
740
741 v4l2_m2m_job_finish(dev->m2m_dev, ctx->m2m_ctx);
742}
743
744static void coda_lock(void *m2m_priv)
745{
746 struct coda_ctx *ctx = m2m_priv;
747 struct coda_dev *pcdev = ctx->dev;
748 mutex_lock(&pcdev->dev_mutex);
749}
750
751static void coda_unlock(void *m2m_priv)
752{
753 struct coda_ctx *ctx = m2m_priv;
754 struct coda_dev *pcdev = ctx->dev;
755 mutex_unlock(&pcdev->dev_mutex);
756}
757
758static struct v4l2_m2m_ops coda_m2m_ops = {
759 .device_run = coda_device_run,
760 .job_ready = coda_job_ready,
761 .job_abort = coda_job_abort,
762 .lock = coda_lock,
763 .unlock = coda_unlock,
764};
765
766static void set_default_params(struct coda_ctx *ctx)
767{
768 struct coda_dev *dev = ctx->dev;
769
770 ctx->params.codec_mode = CODA_MODE_INVALID;
771 ctx->colorspace = V4L2_COLORSPACE_REC709;
772 ctx->params.framerate = 30;
773 ctx->reference = NULL;
774 ctx->aborting = 0;
775
776 /* Default formats for output and input queues */
777 ctx->q_data[V4L2_M2M_SRC].fmt = &dev->devtype->formats[0];
778 ctx->q_data[V4L2_M2M_DST].fmt = &dev->devtype->formats[1];
779 ctx->q_data[V4L2_M2M_SRC].width = MAX_W;
780 ctx->q_data[V4L2_M2M_SRC].height = MAX_H;
781 ctx->q_data[V4L2_M2M_SRC].sizeimage = (MAX_W * MAX_H * 3) / 2;
782 ctx->q_data[V4L2_M2M_DST].width = MAX_W;
783 ctx->q_data[V4L2_M2M_DST].height = MAX_H;
784 ctx->q_data[V4L2_M2M_DST].sizeimage = CODA_MAX_FRAME_SIZE;
785}
786
787/*
788 * Queue operations
789 */
790static int coda_queue_setup(struct vb2_queue *vq,
791 const struct v4l2_format *fmt,
792 unsigned int *nbuffers, unsigned int *nplanes,
793 unsigned int sizes[], void *alloc_ctxs[])
794{
795 struct coda_ctx *ctx = vb2_get_drv_priv(vq);
796 unsigned int size;
797
798 if (vq->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
799 *nbuffers = CODA_OUTPUT_BUFS;
800 if (fmt)
801 size = fmt->fmt.pix.width *
802 fmt->fmt.pix.height * 3 / 2;
803 else
804 size = MAX_W *
805 MAX_H * 3 / 2;
806 } else {
807 *nbuffers = CODA_CAPTURE_BUFS;
808 size = CODA_MAX_FRAME_SIZE;
809 }
810
811 *nplanes = 1;
812 sizes[0] = size;
813
814 alloc_ctxs[0] = ctx->dev->alloc_ctx;
815
816 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
817 "get %d buffer(s) of size %d each.\n", *nbuffers, size);
818
819 return 0;
820}
821
822static int coda_buf_prepare(struct vb2_buffer *vb)
823{
824 struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
825 struct coda_q_data *q_data;
826
827 q_data = get_q_data(ctx, vb->vb2_queue->type);
828
829 if (vb2_plane_size(vb, 0) < q_data->sizeimage) {
830 v4l2_warn(&ctx->dev->v4l2_dev,
831 "%s data will not fit into plane (%lu < %lu)\n",
832 __func__, vb2_plane_size(vb, 0),
833 (long)q_data->sizeimage);
834 return -EINVAL;
835 }
836
837 vb2_set_plane_payload(vb, 0, q_data->sizeimage);
838
839 return 0;
840}
841
842static void coda_buf_queue(struct vb2_buffer *vb)
843{
844 struct coda_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
845 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
846}
847
848static void coda_wait_prepare(struct vb2_queue *q)
849{
850 struct coda_ctx *ctx = vb2_get_drv_priv(q);
851 coda_unlock(ctx);
852}
853
854static void coda_wait_finish(struct vb2_queue *q)
855{
856 struct coda_ctx *ctx = vb2_get_drv_priv(q);
857 coda_lock(ctx);
858}
859
860static int coda_start_streaming(struct vb2_queue *q, unsigned int count)
861{
862 struct coda_ctx *ctx = vb2_get_drv_priv(q);
863 struct v4l2_device *v4l2_dev = &ctx->dev->v4l2_dev;
864 u32 bitstream_buf, bitstream_size;
865 struct coda_dev *dev = ctx->dev;
866 struct coda_q_data *q_data_src, *q_data_dst;
867 u32 dst_fourcc;
868 struct vb2_buffer *buf;
869 struct vb2_queue *src_vq;
870 u32 value;
871 int i = 0;
872
873 if (count < 1)
874 return -EINVAL;
875
876 if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
877 ctx->rawstreamon = 1;
878 else
879 ctx->compstreamon = 1;
880
881 /* Don't start the coda unless both queues are on */
882 if (!(ctx->rawstreamon & ctx->compstreamon))
883 return 0;
884
885 ctx->gopcounter = ctx->params.gop_size - 1;
886
887 q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
888 buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
889 bitstream_buf = vb2_dma_contig_plane_dma_addr(buf, 0);
890 q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
891 bitstream_size = q_data_dst->sizeimage;
892 dst_fourcc = q_data_dst->fmt->fourcc;
893
894 /* Find out whether coda must encode or decode */
895 if (q_data_src->fmt->type == CODA_FMT_RAW &&
896 q_data_dst->fmt->type == CODA_FMT_ENC) {
897 ctx->inst_type = CODA_INST_ENCODER;
898 } else if (q_data_src->fmt->type == CODA_FMT_ENC &&
899 q_data_dst->fmt->type == CODA_FMT_RAW) {
900 ctx->inst_type = CODA_INST_DECODER;
901 v4l2_err(v4l2_dev, "decoding not supported.\n");
902 return -EINVAL;
903 } else {
904 v4l2_err(v4l2_dev, "couldn't tell instance type.\n");
905 return -EINVAL;
906 }
907
908 if (!coda_is_initialized(dev)) {
909 v4l2_err(v4l2_dev, "coda is not initialized.\n");
910 return -EFAULT;
911 }
912 coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
913 coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->idx));
914 coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->idx));
915 switch (dev->devtype->product) {
916 case CODA_DX6:
917 coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
918 CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
919 break;
920 default:
921 coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
922 CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
923 }
924
925 /* Configure the coda */
926 coda_write(dev, 0xffff4c00, CODA_REG_BIT_SEARCH_RAM_BASE_ADDR);
927
928 /* Could set rotation here if needed */
929 switch (dev->devtype->product) {
930 case CODA_DX6:
931 value = (q_data_src->width & CODADX6_PICWIDTH_MASK) << CODADX6_PICWIDTH_OFFSET;
932 break;
933 default:
934 value = (q_data_src->width & CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
935 }
936 value |= (q_data_src->height & CODA_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
937 coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
938 coda_write(dev, ctx->params.framerate,
939 CODA_CMD_ENC_SEQ_SRC_F_RATE);
940
941 switch (dst_fourcc) {
942 case V4L2_PIX_FMT_MPEG4:
943 if (dev->devtype->product == CODA_DX6)
944 ctx->params.codec_mode = CODADX6_MODE_ENCODE_MP4;
945 else
946 ctx->params.codec_mode = CODA7_MODE_ENCODE_MP4;
947
948 coda_write(dev, CODA_STD_MPEG4, CODA_CMD_ENC_SEQ_COD_STD);
949 coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
950 break;
951 case V4L2_PIX_FMT_H264:
952 if (dev->devtype->product == CODA_DX6)
953 ctx->params.codec_mode = CODADX6_MODE_ENCODE_H264;
954 else
955 ctx->params.codec_mode = CODA7_MODE_ENCODE_H264;
956
957 coda_write(dev, CODA_STD_H264, CODA_CMD_ENC_SEQ_COD_STD);
958 coda_write(dev, 0, CODA_CMD_ENC_SEQ_264_PARA);
959 break;
960 default:
961 v4l2_err(v4l2_dev,
962 "dst format (0x%08x) invalid.\n", dst_fourcc);
963 return -EINVAL;
964 }
965
966 value = (ctx->params.slice_max_mb & CODA_SLICING_SIZE_MASK) << CODA_SLICING_SIZE_OFFSET;
967 value |= (1 & CODA_SLICING_UNIT_MASK) << CODA_SLICING_UNIT_OFFSET;
968 if (ctx->params.slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB)
969 value |= 1 & CODA_SLICING_MODE_MASK;
970 coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
971 value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
972 coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
973
974 if (ctx->params.bitrate) {
975 /* Rate control enabled */
976 value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK) << CODA_RATECONTROL_BITRATE_OFFSET;
977 value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
978 } else {
979 value = 0;
980 }
981 coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
982
983 coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
984 coda_write(dev, 0, CODA_CMD_ENC_SEQ_INTRA_REFRESH);
985
986 coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
987 coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
988
989 /* set default gamma */
990 value = (CODA_DEFAULT_GAMMA & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET;
991 coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_GAMMA);
992
993 value = (CODA_DEFAULT_GAMMA > 0) << CODA_OPTION_GAMMA_OFFSET;
994 value |= (0 & CODA_OPTION_SLICEREPORT_MASK) << CODA_OPTION_SLICEREPORT_OFFSET;
995 coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
996
997 if (dst_fourcc == V4L2_PIX_FMT_H264) {
998 value = (FMO_SLICE_SAVE_BUF_SIZE << 7);
999 value |= (0 & CODA_FMOPARAM_TYPE_MASK) << CODA_FMOPARAM_TYPE_OFFSET;
1000 value |= 0 & CODA_FMOPARAM_SLICENUM_MASK;
1001 coda_write(dev, value, CODA_CMD_ENC_SEQ_FMO);
1002 }
1003
1004 if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
1005 v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
1006 return -ETIMEDOUT;
1007 }
1008
1009 if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0)
1010 return -EFAULT;
1011
1012 /*
1013 * Walk the src buffer list and let the codec know the
1014 * addresses of the pictures.
1015 */
1016 src_vq = v4l2_m2m_get_vq(ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
1017 for (i = 0; i < src_vq->num_buffers; i++) {
1018 u32 *p;
1019
1020 buf = src_vq->bufs[i];
1021 p = ctx->parabuf.vaddr;
1022
1023 p[i * 3] = vb2_dma_contig_plane_dma_addr(buf, 0);
1024 p[i * 3 + 1] = p[i * 3] + q_data_src->width *
1025 q_data_src->height;
1026 p[i * 3 + 2] = p[i * 3 + 1] + q_data_src->width / 2 *
1027 q_data_src->height / 2;
1028 }
1029
1030 coda_write(dev, src_vq->num_buffers, CODA_CMD_SET_FRAME_BUF_NUM);
1031 coda_write(dev, q_data_src->width, CODA_CMD_SET_FRAME_BUF_STRIDE);
1032 if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
1033 v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
1034 return -ETIMEDOUT;
1035 }
1036
1037 /* Save stream headers */
1038 buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
1039 switch (dst_fourcc) {
1040 case V4L2_PIX_FMT_H264:
1041 /*
1042 * Get SPS in the first frame and copy it to an
1043 * intermediate buffer.
1044 */
1045 coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
1046 coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
1047 coda_write(dev, CODA_HEADER_H264_SPS, CODA_CMD_ENC_HEADER_CODE);
1048 if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
1049 v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
1050 return -ETIMEDOUT;
1051 }
1052 ctx->vpu_header_size[0] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
1053 coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
1054 memcpy(&ctx->vpu_header[0][0], vb2_plane_vaddr(buf, 0),
1055 ctx->vpu_header_size[0]);
1056
1057 /*
1058 * Get PPS in the first frame and copy it to an
1059 * intermediate buffer.
1060 */
1061 coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
1062 coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
1063 coda_write(dev, CODA_HEADER_H264_PPS, CODA_CMD_ENC_HEADER_CODE);
1064 if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
1065 v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
1066 return -ETIMEDOUT;
1067 }
1068 ctx->vpu_header_size[1] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
1069 coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
1070 memcpy(&ctx->vpu_header[1][0], vb2_plane_vaddr(buf, 0),
1071 ctx->vpu_header_size[1]);
1072 ctx->vpu_header_size[2] = 0;
1073 break;
1074 case V4L2_PIX_FMT_MPEG4:
1075 /*
1076 * Get VOS in the first frame and copy it to an
1077 * intermediate buffer
1078 */
1079 coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
1080 coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
1081 coda_write(dev, CODA_HEADER_MP4V_VOS, CODA_CMD_ENC_HEADER_CODE);
1082 if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
1083 v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
1084 return -ETIMEDOUT;
1085 }
1086 ctx->vpu_header_size[0] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
1087 coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
1088 memcpy(&ctx->vpu_header[0][0], vb2_plane_vaddr(buf, 0),
1089 ctx->vpu_header_size[0]);
1090
1091 coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
1092 coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
1093 coda_write(dev, CODA_HEADER_MP4V_VIS, CODA_CMD_ENC_HEADER_CODE);
1094 if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
1095 v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER failed\n");
1096 return -ETIMEDOUT;
1097 }
1098 ctx->vpu_header_size[1] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
1099 coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
1100 memcpy(&ctx->vpu_header[1][0], vb2_plane_vaddr(buf, 0),
1101 ctx->vpu_header_size[1]);
1102
1103 coda_write(dev, vb2_dma_contig_plane_dma_addr(buf, 0), CODA_CMD_ENC_HEADER_BB_START);
1104 coda_write(dev, bitstream_size, CODA_CMD_ENC_HEADER_BB_SIZE);
1105 coda_write(dev, CODA_HEADER_MP4V_VOL, CODA_CMD_ENC_HEADER_CODE);
1106 if (coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER)) {
1107 v4l2_err(v4l2_dev, "CODA_COMMAND_ENCODE_HEADER failed\n");
1108 return -ETIMEDOUT;
1109 }
1110 ctx->vpu_header_size[2] = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx)) -
1111 coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
1112 memcpy(&ctx->vpu_header[2][0], vb2_plane_vaddr(buf, 0),
1113 ctx->vpu_header_size[2]);
1114 break;
1115 default:
1116 /* No more formats need to save headers at the moment */
1117 break;
1118 }
1119
1120 return 0;
1121}
1122
1123static int coda_stop_streaming(struct vb2_queue *q)
1124{
1125 struct coda_ctx *ctx = vb2_get_drv_priv(q);
1126
1127 if (q->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
1128 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1129 "%s: output\n", __func__);
1130 ctx->rawstreamon = 0;
1131 } else {
1132 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1133 "%s: capture\n", __func__);
1134 ctx->compstreamon = 0;
1135 }
1136
1137 if (!ctx->rawstreamon && !ctx->compstreamon) {
1138 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1139 "%s: sent command 'SEQ_END' to coda\n", __func__);
1140 if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
1141 v4l2_err(&ctx->dev->v4l2_dev,
1142 "CODA_COMMAND_SEQ_END failed\n");
1143 return -ETIMEDOUT;
1144 }
1145 }
1146
1147 return 0;
1148}
1149
1150static struct vb2_ops coda_qops = {
1151 .queue_setup = coda_queue_setup,
1152 .buf_prepare = coda_buf_prepare,
1153 .buf_queue = coda_buf_queue,
1154 .wait_prepare = coda_wait_prepare,
1155 .wait_finish = coda_wait_finish,
1156 .start_streaming = coda_start_streaming,
1157 .stop_streaming = coda_stop_streaming,
1158};
1159
1160static int coda_s_ctrl(struct v4l2_ctrl *ctrl)
1161{
1162 struct coda_ctx *ctx =
1163 container_of(ctrl->handler, struct coda_ctx, ctrls);
1164
1165 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1166 "s_ctrl: id = %d, val = %d\n", ctrl->id, ctrl->val);
1167
1168 switch (ctrl->id) {
1169 case V4L2_CID_MPEG_VIDEO_BITRATE:
1170 ctx->params.bitrate = ctrl->val / 1000;
1171 break;
1172 case V4L2_CID_MPEG_VIDEO_GOP_SIZE:
1173 ctx->params.gop_size = ctrl->val;
1174 break;
1175 case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP:
1176 ctx->params.h264_intra_qp = ctrl->val;
1177 break;
1178 case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP:
1179 ctx->params.h264_inter_qp = ctrl->val;
1180 break;
1181 case V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP:
1182 ctx->params.mpeg4_intra_qp = ctrl->val;
1183 break;
1184 case V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP:
1185 ctx->params.mpeg4_inter_qp = ctrl->val;
1186 break;
1187 case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE:
1188 ctx->params.slice_mode = ctrl->val;
1189 break;
1190 case V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB:
1191 ctx->params.slice_max_mb = ctrl->val;
1192 break;
1193 case V4L2_CID_MPEG_VIDEO_HEADER_MODE:
1194 break;
1195 default:
1196 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1197 "Invalid control, id=%d, val=%d\n",
1198 ctrl->id, ctrl->val);
1199 return -EINVAL;
1200 }
1201
1202 return 0;
1203}
1204
1205static struct v4l2_ctrl_ops coda_ctrl_ops = {
1206 .s_ctrl = coda_s_ctrl,
1207};
1208
1209static int coda_ctrls_setup(struct coda_ctx *ctx)
1210{
1211 v4l2_ctrl_handler_init(&ctx->ctrls, 9);
1212
1213 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1214 V4L2_CID_MPEG_VIDEO_BITRATE, 0, 32767000, 1, 0);
1215 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1216 V4L2_CID_MPEG_VIDEO_GOP_SIZE, 1, 60, 1, 16);
1217 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1218 V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP, 1, 51, 1, 25);
1219 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1220 V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP, 1, 51, 1, 25);
1221 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1222 V4L2_CID_MPEG_VIDEO_MPEG4_I_FRAME_QP, 1, 31, 1, 2);
1223 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1224 V4L2_CID_MPEG_VIDEO_MPEG4_P_FRAME_QP, 1, 31, 1, 2);
1225 v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
1226 V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MODE,
1227 V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB, 0,
1228 V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB);
1229 v4l2_ctrl_new_std(&ctx->ctrls, &coda_ctrl_ops,
1230 V4L2_CID_MPEG_VIDEO_MULTI_SLICE_MAX_MB, 1, 0x3fffffff, 1, 1);
1231 v4l2_ctrl_new_std_menu(&ctx->ctrls, &coda_ctrl_ops,
1232 V4L2_CID_MPEG_VIDEO_HEADER_MODE,
1233 V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME,
1234 (1 << V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE),
1235 V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME);
1236
1237 if (ctx->ctrls.error) {
1238 v4l2_err(&ctx->dev->v4l2_dev, "control initialization error (%d)",
1239 ctx->ctrls.error);
1240 return -EINVAL;
1241 }
1242
1243 return v4l2_ctrl_handler_setup(&ctx->ctrls);
1244}
1245
1246static int coda_queue_init(void *priv, struct vb2_queue *src_vq,
1247 struct vb2_queue *dst_vq)
1248{
1249 struct coda_ctx *ctx = priv;
1250 int ret;
1251
1252 memset(src_vq, 0, sizeof(*src_vq));
1253 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
1254 src_vq->io_modes = VB2_MMAP;
1255 src_vq->drv_priv = ctx;
1256 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1257 src_vq->ops = &coda_qops;
1258 src_vq->mem_ops = &vb2_dma_contig_memops;
1259
1260 ret = vb2_queue_init(src_vq);
1261 if (ret)
1262 return ret;
1263
1264 memset(dst_vq, 0, sizeof(*dst_vq));
1265 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1266 dst_vq->io_modes = VB2_MMAP;
1267 dst_vq->drv_priv = ctx;
1268 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1269 dst_vq->ops = &coda_qops;
1270 dst_vq->mem_ops = &vb2_dma_contig_memops;
1271
1272 return vb2_queue_init(dst_vq);
1273}
1274
1275static int coda_open(struct file *file)
1276{
1277 struct coda_dev *dev = video_drvdata(file);
1278 struct coda_ctx *ctx = NULL;
1279 int ret = 0;
1280
1281 if (dev->instances >= CODA_MAX_INSTANCES)
1282 return -EBUSY;
1283
1284 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1285 if (!ctx)
1286 return -ENOMEM;
1287
1288 v4l2_fh_init(&ctx->fh, video_devdata(file));
1289 file->private_data = &ctx->fh;
1290 v4l2_fh_add(&ctx->fh);
1291 ctx->dev = dev;
1292
1293 set_default_params(ctx);
1294 ctx->m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx,
1295 &coda_queue_init);
1296 if (IS_ERR(ctx->m2m_ctx)) {
1297 int ret = PTR_ERR(ctx->m2m_ctx);
1298
1299 v4l2_err(&dev->v4l2_dev, "%s return error (%d)\n",
1300 __func__, ret);
1301 goto err;
1302 }
1303 ret = coda_ctrls_setup(ctx);
1304 if (ret) {
1305 v4l2_err(&dev->v4l2_dev, "failed to setup coda controls\n");
1306 goto err;
1307 }
1308
1309 ctx->fh.ctrl_handler = &ctx->ctrls;
1310
1311 ctx->parabuf.vaddr = dma_alloc_coherent(&dev->plat_dev->dev,
1312 CODA_PARA_BUF_SIZE, &ctx->parabuf.paddr, GFP_KERNEL);
1313 if (!ctx->parabuf.vaddr) {
1314 v4l2_err(&dev->v4l2_dev, "failed to allocate parabuf");
1315 ret = -ENOMEM;
1316 goto err;
1317 }
1318
1319 coda_lock(ctx);
1320 ctx->idx = dev->instances++;
1321 coda_unlock(ctx);
1322
1323 clk_prepare_enable(dev->clk_per);
1324 clk_prepare_enable(dev->clk_ahb);
1325
1326 v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Created instance %d (%p)\n",
1327 ctx->idx, ctx);
1328
1329 return 0;
1330
1331err:
1332 v4l2_fh_del(&ctx->fh);
1333 v4l2_fh_exit(&ctx->fh);
1334 kfree(ctx);
1335 return ret;
1336}
1337
1338static int coda_release(struct file *file)
1339{
1340 struct coda_dev *dev = video_drvdata(file);
1341 struct coda_ctx *ctx = fh_to_ctx(file->private_data);
1342
1343 v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "Releasing instance %p\n",
1344 ctx);
1345
1346 coda_lock(ctx);
1347 dev->instances--;
1348 coda_unlock(ctx);
1349
1350 dma_free_coherent(&dev->plat_dev->dev, CODA_PARA_BUF_SIZE,
1351 ctx->parabuf.vaddr, ctx->parabuf.paddr);
1352 v4l2_m2m_ctx_release(ctx->m2m_ctx);
1353 v4l2_ctrl_handler_free(&ctx->ctrls);
1354 clk_disable_unprepare(dev->clk_per);
1355 clk_disable_unprepare(dev->clk_ahb);
1356 v4l2_fh_del(&ctx->fh);
1357 v4l2_fh_exit(&ctx->fh);
1358 kfree(ctx);
1359
1360 return 0;
1361}
1362
1363static unsigned int coda_poll(struct file *file,
1364 struct poll_table_struct *wait)
1365{
1366 struct coda_ctx *ctx = fh_to_ctx(file->private_data);
1367 int ret;
1368
1369 coda_lock(ctx);
1370 ret = v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1371 coda_unlock(ctx);
1372 return ret;
1373}
1374
1375static int coda_mmap(struct file *file, struct vm_area_struct *vma)
1376{
1377 struct coda_ctx *ctx = fh_to_ctx(file->private_data);
1378
1379 return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1380}
1381
1382static const struct v4l2_file_operations coda_fops = {
1383 .owner = THIS_MODULE,
1384 .open = coda_open,
1385 .release = coda_release,
1386 .poll = coda_poll,
1387 .unlocked_ioctl = video_ioctl2,
1388 .mmap = coda_mmap,
1389};
1390
1391static irqreturn_t coda_irq_handler(int irq, void *data)
1392{
1393 struct vb2_buffer *src_buf, *dst_buf, *tmp_buf;
1394 struct coda_dev *dev = data;
1395 u32 wr_ptr, start_ptr;
1396 struct coda_ctx *ctx;
1397
1398 /* read status register to attend the IRQ */
1399 coda_read(dev, CODA_REG_BIT_INT_STATUS);
1400 coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
1401 CODA_REG_BIT_INT_CLEAR);
1402
1403 ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
1404 if (ctx == NULL) {
1405 v4l2_err(&dev->v4l2_dev, "Instance released before the end of transaction\n");
1406 return IRQ_HANDLED;
1407 }
1408
1409 if (ctx->aborting) {
1410 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1411 "task has been aborted\n");
1412 return IRQ_HANDLED;
1413 }
1414
1415 if (coda_isbusy(ctx->dev)) {
1416 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
1417 "coda is still busy!!!!\n");
1418 return IRQ_NONE;
1419 }
1420
1421 src_buf = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
1422 dst_buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
1423
1424 /* Get results from the coda */
1425 coda_read(dev, CODA_RET_ENC_PIC_TYPE);
1426 start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
1427 wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->idx));
1428 /* Calculate bytesused field */
1429 if (dst_buf->v4l2_buf.sequence == 0) {
1430 dst_buf->v4l2_planes[0].bytesused = (wr_ptr - start_ptr) +
1431 ctx->vpu_header_size[0] +
1432 ctx->vpu_header_size[1] +
1433 ctx->vpu_header_size[2];
1434 } else {
1435 dst_buf->v4l2_planes[0].bytesused = (wr_ptr - start_ptr);
1436 }
1437
1438 v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
1439 wr_ptr - start_ptr);
1440
1441 coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
1442 coda_read(dev, CODA_RET_ENC_PIC_FLAG);
1443
1444 if (src_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) {
1445 dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_KEYFRAME;
1446 dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_PFRAME;
1447 } else {
1448 dst_buf->v4l2_buf.flags |= V4L2_BUF_FLAG_PFRAME;
1449 dst_buf->v4l2_buf.flags &= ~V4L2_BUF_FLAG_KEYFRAME;
1450 }
1451
1452 /* Free previous reference picture if available */
1453 if (ctx->reference) {
1454 v4l2_m2m_buf_done(ctx->reference, VB2_BUF_STATE_DONE);
1455 ctx->reference = NULL;
1456 }
1457
1458 /*
1459 * For the last frame of the gop we don't need to save
1460 * a reference picture.
1461 */
1462 v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
1463 tmp_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
1464 if (ctx->gopcounter == 0)
1465 v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
1466 else
1467 ctx->reference = tmp_buf;
1468
1469 v4l2_m2m_buf_done(dst_buf, VB2_BUF_STATE_DONE);
1470
1471 ctx->gopcounter--;
1472 if (ctx->gopcounter < 0)
1473 ctx->gopcounter = ctx->params.gop_size - 1;
1474
1475 v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
1476 "job finished: encoding frame (%d) (%s)\n",
1477 dst_buf->v4l2_buf.sequence,
1478 (dst_buf->v4l2_buf.flags & V4L2_BUF_FLAG_KEYFRAME) ?
1479 "KEYFRAME" : "PFRAME");
1480
1481 v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->m2m_ctx);
1482
1483 return IRQ_HANDLED;
1484}
1485
1486static u32 coda_supported_firmwares[] = {
1487 CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
1488};
1489
1490static bool coda_firmware_supported(u32 vernum)
1491{
1492 int i;
1493
1494 for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
1495 if (vernum == coda_supported_firmwares[i])
1496 return true;
1497 return false;
1498}
1499
1500static char *coda_product_name(int product)
1501{
1502 static char buf[9];
1503
1504 switch (product) {
1505 case CODA_DX6:
1506 return "CodaDx6";
1507 default:
1508 snprintf(buf, sizeof(buf), "(0x%04x)", product);
1509 return buf;
1510 }
1511}
1512
1513static int coda_hw_init(struct coda_dev *dev, const struct firmware *fw)
1514{
1515 u16 product, major, minor, release;
1516 u32 data;
1517 u16 *p;
1518 int i;
1519
1520 clk_prepare_enable(dev->clk_per);
1521 clk_prepare_enable(dev->clk_ahb);
1522
1523 /* Copy the whole firmware image to the code buffer */
1524 memcpy(dev->codebuf.vaddr, fw->data, fw->size);
1525 /*
1526 * Copy the first CODA_ISRAM_SIZE in the internal SRAM.
1527 * This memory seems to be big-endian here, which is weird, since
1528 * the internal ARM processor of the coda is little endian.
1529 * Data in this SRAM survives a reboot.
1530 */
1531 p = (u16 *)fw->data;
1532 for (i = 0; i < (CODA_ISRAM_SIZE / 2); i++) {
1533 data = CODA_DOWN_ADDRESS_SET(i) |
1534 CODA_DOWN_DATA_SET(p[i ^ 1]);
1535 coda_write(dev, data, CODA_REG_BIT_CODE_DOWN);
1536 }
1537 release_firmware(fw);
1538
1539 /* Tell the BIT where to find everything it needs */
1540 coda_write(dev, dev->workbuf.paddr,
1541 CODA_REG_BIT_WORK_BUF_ADDR);
1542 coda_write(dev, dev->codebuf.paddr,
1543 CODA_REG_BIT_CODE_BUF_ADDR);
1544 coda_write(dev, 0, CODA_REG_BIT_CODE_RUN);
1545
1546 /* Set default values */
1547 switch (dev->devtype->product) {
1548 case CODA_DX6:
1549 coda_write(dev, CODADX6_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
1550 break;
1551 default:
1552 coda_write(dev, CODA7_STREAM_BUF_PIC_FLUSH, CODA_REG_BIT_STREAM_CTRL);
1553 }
1554 coda_write(dev, 0, CODA_REG_BIT_FRAME_MEM_CTRL);
1555 coda_write(dev, CODA_INT_INTERRUPT_ENABLE,
1556 CODA_REG_BIT_INT_ENABLE);
1557
1558 /* Reset VPU and start processor */
1559 data = coda_read(dev, CODA_REG_BIT_CODE_RESET);
1560 data |= CODA_REG_RESET_ENABLE;
1561 coda_write(dev, data, CODA_REG_BIT_CODE_RESET);
1562 udelay(10);
1563 data &= ~CODA_REG_RESET_ENABLE;
1564 coda_write(dev, data, CODA_REG_BIT_CODE_RESET);
1565 coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
1566
1567 /* Load firmware */
1568 coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
1569 coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
1570 coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
1571 coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
1572 coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
1573 if (coda_wait_timeout(dev)) {
1574 clk_disable_unprepare(dev->clk_per);
1575 clk_disable_unprepare(dev->clk_ahb);
1576 v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
1577 return -EIO;
1578 }
1579
1580 /* Check we are compatible with the loaded firmware */
1581 data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
1582 product = CODA_FIRMWARE_PRODUCT(data);
1583 major = CODA_FIRMWARE_MAJOR(data);
1584 minor = CODA_FIRMWARE_MINOR(data);
1585 release = CODA_FIRMWARE_RELEASE(data);
1586
1587 clk_disable_unprepare(dev->clk_per);
1588 clk_disable_unprepare(dev->clk_ahb);
1589
1590 if (product != dev->devtype->product) {
1591 v4l2_err(&dev->v4l2_dev, "Wrong firmware. Hw: %s, Fw: %s,"
1592 " Version: %u.%u.%u\n",
1593 coda_product_name(dev->devtype->product),
1594 coda_product_name(product), major, minor, release);
1595 return -EINVAL;
1596 }
1597
1598 v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
1599 coda_product_name(product));
1600
1601 if (coda_firmware_supported(data)) {
1602 v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
1603 major, minor, release);
1604 } else {
1605 v4l2_warn(&dev->v4l2_dev, "Unsupported firmware version: "
1606 "%u.%u.%u\n", major, minor, release);
1607 }
1608
1609 return 0;
1610}
1611
1612static void coda_fw_callback(const struct firmware *fw, void *context)
1613{
1614 struct coda_dev *dev = context;
1615 struct platform_device *pdev = dev->plat_dev;
1616 int ret;
1617
1618 if (!fw) {
1619 v4l2_err(&dev->v4l2_dev, "firmware request failed\n");
1620 return;
1621 }
1622
1623 /* allocate auxiliary per-device code buffer for the BIT processor */
1624 dev->codebuf.size = fw->size;
1625 dev->codebuf.vaddr = dma_alloc_coherent(&pdev->dev, fw->size,
1626 &dev->codebuf.paddr,
1627 GFP_KERNEL);
1628 if (!dev->codebuf.vaddr) {
1629 dev_err(&pdev->dev, "failed to allocate code buffer\n");
1630 return;
1631 }
1632
1633 ret = coda_hw_init(dev, fw);
1634 if (ret) {
1635 v4l2_err(&dev->v4l2_dev, "HW initialization failed\n");
1636 return;
1637 }
1638
1639 dev->vfd.fops = &coda_fops,
1640 dev->vfd.ioctl_ops = &coda_ioctl_ops;
1641 dev->vfd.release = video_device_release_empty,
1642 dev->vfd.lock = &dev->dev_mutex;
1643 dev->vfd.v4l2_dev = &dev->v4l2_dev;
1644 snprintf(dev->vfd.name, sizeof(dev->vfd.name), "%s", CODA_NAME);
1645 video_set_drvdata(&dev->vfd, dev);
1646
1647 dev->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1648 if (IS_ERR(dev->alloc_ctx)) {
1649 v4l2_err(&dev->v4l2_dev, "Failed to alloc vb2 context\n");
1650 return;
1651 }
1652
1653 dev->m2m_dev = v4l2_m2m_init(&coda_m2m_ops);
1654 if (IS_ERR(dev->m2m_dev)) {
1655 v4l2_err(&dev->v4l2_dev, "Failed to init mem2mem device\n");
1656 goto rel_ctx;
1657 }
1658
1659 ret = video_register_device(&dev->vfd, VFL_TYPE_GRABBER, 0);
1660 if (ret) {
1661 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1662 goto rel_m2m;
1663 }
1664 v4l2_info(&dev->v4l2_dev, "codec registered as /dev/video%d\n",
1665 dev->vfd.num);
1666
1667 return;
1668
1669rel_m2m:
1670 v4l2_m2m_release(dev->m2m_dev);
1671rel_ctx:
1672 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
1673}
1674
1675static int coda_firmware_request(struct coda_dev *dev)
1676{
1677 char *fw = dev->devtype->firmware;
1678
1679 dev_dbg(&dev->plat_dev->dev, "requesting firmware '%s' for %s\n", fw,
1680 coda_product_name(dev->devtype->product));
1681
1682 return request_firmware_nowait(THIS_MODULE, true,
1683 fw, &dev->plat_dev->dev, GFP_KERNEL, dev, coda_fw_callback);
1684}
1685
1686enum coda_platform {
1687 CODA_IMX27,
1688};
1689
1690static struct coda_devtype coda_devdata[] = {
1691 [CODA_IMX27] = {
1692 .firmware = "v4l-codadx6-imx27.bin",
1693 .product = CODA_DX6,
1694 .formats = codadx6_formats,
1695 .num_formats = ARRAY_SIZE(codadx6_formats),
1696 },
1697};
1698
1699static struct platform_device_id coda_platform_ids[] = {
1700 { .name = "coda-imx27", .driver_data = CODA_IMX27 },
1701 { /* sentinel */ }
1702};
1703MODULE_DEVICE_TABLE(platform, coda_platform_ids);
1704
1705#ifdef CONFIG_OF
1706static const struct of_device_id coda_dt_ids[] = {
1707 { .compatible = "fsl,imx27-vpu", .data = &coda_platform_ids[CODA_IMX27] },
1708 { /* sentinel */ }
1709};
1710MODULE_DEVICE_TABLE(of, coda_dt_ids);
1711#endif
1712
1713static int __devinit coda_probe(struct platform_device *pdev)
1714{
1715 const struct of_device_id *of_id =
1716 of_match_device(of_match_ptr(coda_dt_ids), &pdev->dev);
1717 const struct platform_device_id *pdev_id;
1718 struct coda_dev *dev;
1719 struct resource *res;
1720 int ret, irq;
1721
1722 dev = devm_kzalloc(&pdev->dev, sizeof *dev, GFP_KERNEL);
1723 if (!dev) {
1724 dev_err(&pdev->dev, "Not enough memory for %s\n",
1725 CODA_NAME);
1726 return -ENOMEM;
1727 }
1728
1729 spin_lock_init(&dev->irqlock);
1730
1731 dev->plat_dev = pdev;
1732 dev->clk_per = devm_clk_get(&pdev->dev, "per");
1733 if (IS_ERR(dev->clk_per)) {
1734 dev_err(&pdev->dev, "Could not get per clock\n");
1735 return PTR_ERR(dev->clk_per);
1736 }
1737
1738 dev->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
1739 if (IS_ERR(dev->clk_ahb)) {
1740 dev_err(&pdev->dev, "Could not get ahb clock\n");
1741 return PTR_ERR(dev->clk_ahb);
1742 }
1743
1744 /* Get memory for physical registers */
1745 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1746 if (res == NULL) {
1747 dev_err(&pdev->dev, "failed to get memory region resource\n");
1748 return -ENOENT;
1749 }
1750
1751 if (devm_request_mem_region(&pdev->dev, res->start,
1752 resource_size(res), CODA_NAME) == NULL) {
1753 dev_err(&pdev->dev, "failed to request memory region\n");
1754 return -ENOENT;
1755 }
1756 dev->regs_base = devm_ioremap(&pdev->dev, res->start,
1757 resource_size(res));
1758 if (!dev->regs_base) {
1759 dev_err(&pdev->dev, "failed to ioremap address region\n");
1760 return -ENOENT;
1761 }
1762
1763 /* IRQ */
1764 irq = platform_get_irq(pdev, 0);
1765 if (irq < 0) {
1766 dev_err(&pdev->dev, "failed to get irq resource\n");
1767 return -ENOENT;
1768 }
1769
1770 if (devm_request_irq(&pdev->dev, irq, coda_irq_handler,
1771 0, CODA_NAME, dev) < 0) {
1772 dev_err(&pdev->dev, "failed to request irq\n");
1773 return -ENOENT;
1774 }
1775
1776 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1777 if (ret)
1778 return ret;
1779
1780 mutex_init(&dev->dev_mutex);
1781
1782 pdev_id = of_id ? of_id->data : platform_get_device_id(pdev);
1783
1784 if (of_id) {
1785 dev->devtype = of_id->data;
1786 } else if (pdev_id) {
1787 dev->devtype = &coda_devdata[pdev_id->driver_data];
1788 } else {
1789 v4l2_device_unregister(&dev->v4l2_dev);
1790 return -EINVAL;
1791 }
1792
1793 /* allocate auxiliary per-device buffers for the BIT processor */
1794 switch (dev->devtype->product) {
1795 case CODA_DX6:
1796 dev->workbuf.size = CODADX6_WORK_BUF_SIZE;
1797 break;
1798 default:
1799 dev->workbuf.size = CODA7_WORK_BUF_SIZE;
1800 }
1801 dev->workbuf.vaddr = dma_alloc_coherent(&pdev->dev, dev->workbuf.size,
1802 &dev->workbuf.paddr,
1803 GFP_KERNEL);
1804 if (!dev->workbuf.vaddr) {
1805 dev_err(&pdev->dev, "failed to allocate work buffer\n");
1806 v4l2_device_unregister(&dev->v4l2_dev);
1807 return -ENOMEM;
1808 }
1809
1810 platform_set_drvdata(pdev, dev);
1811
1812 return coda_firmware_request(dev);
1813}
1814
1815static int coda_remove(struct platform_device *pdev)
1816{
1817 struct coda_dev *dev = platform_get_drvdata(pdev);
1818
1819 video_unregister_device(&dev->vfd);
1820 if (dev->m2m_dev)
1821 v4l2_m2m_release(dev->m2m_dev);
1822 if (dev->alloc_ctx)
1823 vb2_dma_contig_cleanup_ctx(dev->alloc_ctx);
1824 v4l2_device_unregister(&dev->v4l2_dev);
1825 if (dev->codebuf.vaddr)
1826 dma_free_coherent(&pdev->dev, dev->codebuf.size,
1827 &dev->codebuf.vaddr, dev->codebuf.paddr);
1828 if (dev->workbuf.vaddr)
1829 dma_free_coherent(&pdev->dev, dev->workbuf.size, &dev->workbuf.vaddr,
1830 dev->workbuf.paddr);
1831 return 0;
1832}
1833
1834static struct platform_driver coda_driver = {
1835 .probe = coda_probe,
1836 .remove = __devexit_p(coda_remove),
1837 .driver = {
1838 .name = CODA_NAME,
1839 .owner = THIS_MODULE,
1840 .of_match_table = of_match_ptr(coda_dt_ids),
1841 },
1842 .id_table = coda_platform_ids,
1843};
1844
1845module_platform_driver(coda_driver);
1846
1847MODULE_LICENSE("GPL");
1848MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
1849MODULE_DESCRIPTION("Coda multi-standard codec V4L2 driver");
diff --git a/drivers/media/video/coda.h b/drivers/media/video/coda.h
new file mode 100644
index 000000000000..4cf4a043186f
--- /dev/null
+++ b/drivers/media/video/coda.h
@@ -0,0 +1,216 @@
1/*
2 * linux/drivers/media/video/coda/coda_regs.h
3 *
4 * Copyright (C) 2012 Vista Silicon SL
5 * Javier Martin <javier.martin@vista-silicon.com>
6 * Xavier Duret
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#ifndef _REGS_CODA_H_
15#define _REGS_CODA_H_
16
17/* HW registers */
18#define CODA_REG_BIT_CODE_RUN 0x000
19#define CODA_REG_RUN_ENABLE (1 << 0)
20#define CODA_REG_BIT_CODE_DOWN 0x004
21#define CODA_DOWN_ADDRESS_SET(x) (((x) & 0xffff) << 16)
22#define CODA_DOWN_DATA_SET(x) ((x) & 0xffff)
23#define CODA_REG_BIT_HOST_IN_REQ 0x008
24#define CODA_REG_BIT_INT_CLEAR 0x00c
25#define CODA_REG_BIT_INT_CLEAR_SET 0x1
26#define CODA_REG_BIT_INT_STATUS 0x010
27#define CODA_REG_BIT_CODE_RESET 0x014
28#define CODA_REG_RESET_ENABLE (1 << 0)
29#define CODA_REG_BIT_CUR_PC 0x018
30
31/* Static SW registers */
32#define CODA_REG_BIT_CODE_BUF_ADDR 0x100
33#define CODA_REG_BIT_WORK_BUF_ADDR 0x104
34#define CODA_REG_BIT_PARA_BUF_ADDR 0x108
35#define CODA_REG_BIT_STREAM_CTRL 0x10c
36#define CODA7_STREAM_BUF_PIC_RESET (1 << 4)
37#define CODADX6_STREAM_BUF_PIC_RESET (1 << 3)
38#define CODA7_STREAM_BUF_PIC_FLUSH (1 << 3)
39#define CODADX6_STREAM_BUF_PIC_FLUSH (1 << 2)
40#define CODA7_STREAM_BUF_DYNALLOC_EN (1 << 5)
41#define CODADX6_STREAM_BUF_DYNALLOC_EN (1 << 4)
42#define CODA_STREAM_CHKDIS_OFFSET (1 << 1)
43#define CODA_STREAM_ENDIAN_SELECT (1 << 0)
44#define CODA_REG_BIT_FRAME_MEM_CTRL 0x110
45#define CODA_IMAGE_ENDIAN_SELECT (1 << 0)
46#define CODA_REG_BIT_RD_PTR(x) (0x120 + 8 * (x))
47#define CODA_REG_BIT_WR_PTR(x) (0x124 + 8 * (x))
48#define CODA_REG_BIT_SEARCH_RAM_BASE_ADDR 0x140
49#define CODA_REG_BIT_BUSY 0x160
50#define CODA_REG_BIT_BUSY_FLAG 1
51#define CODA_REG_BIT_RUN_COMMAND 0x164
52#define CODA_COMMAND_SEQ_INIT 1
53#define CODA_COMMAND_SEQ_END 2
54#define CODA_COMMAND_PIC_RUN 3
55#define CODA_COMMAND_SET_FRAME_BUF 4
56#define CODA_COMMAND_ENCODE_HEADER 5
57#define CODA_COMMAND_ENC_PARA_SET 6
58#define CODA_COMMAND_DEC_PARA_SET 7
59#define CODA_COMMAND_DEC_BUF_FLUSH 8
60#define CODA_COMMAND_RC_CHANGE_PARAMETER 9
61#define CODA_COMMAND_FIRMWARE_GET 0xf
62#define CODA_REG_BIT_RUN_INDEX 0x168
63#define CODA_INDEX_SET(x) ((x) & 0x3)
64#define CODA_REG_BIT_RUN_COD_STD 0x16c
65#define CODADX6_MODE_DECODE_MP4 0
66#define CODADX6_MODE_ENCODE_MP4 1
67#define CODADX6_MODE_DECODE_H264 2
68#define CODADX6_MODE_ENCODE_H264 3
69#define CODA7_MODE_DECODE_H264 0
70#define CODA7_MODE_DECODE_VC1 1
71#define CODA7_MODE_DECODE_MP2 2
72#define CODA7_MODE_DECODE_MP4 3
73#define CODA7_MODE_DECODE_DV3 3
74#define CODA7_MODE_DECODE_RV 4
75#define CODA7_MODE_DECODE_MJPG 5
76#define CODA7_MODE_ENCODE_H264 8
77#define CODA7_MODE_ENCODE_MP4 11
78#define CODA7_MODE_ENCODE_MJPG 13
79#define CODA_MODE_INVALID 0xffff
80#define CODA_REG_BIT_INT_ENABLE 0x170
81#define CODA_INT_INTERRUPT_ENABLE (1 << 3)
82
83/*
84 * Commands' mailbox:
85 * registers with offsets in the range 0x180-0x1d0
86 * have different meaning depending on the command being
87 * issued.
88 */
89
90/* Encoder Sequence Initialization */
91#define CODA_CMD_ENC_SEQ_BB_START 0x180
92#define CODA_CMD_ENC_SEQ_BB_SIZE 0x184
93#define CODA_CMD_ENC_SEQ_OPTION 0x188
94#define CODA_OPTION_GAMMA_OFFSET 7
95#define CODA_OPTION_GAMMA_MASK 0x01
96#define CODA_OPTION_LIMITQP_OFFSET 6
97#define CODA_OPTION_LIMITQP_MASK 0x01
98#define CODA_OPTION_RCINTRAQP_OFFSET 5
99#define CODA_OPTION_RCINTRAQP_MASK 0x01
100#define CODA_OPTION_FMO_OFFSET 4
101#define CODA_OPTION_FMO_MASK 0x01
102#define CODA_OPTION_SLICEREPORT_OFFSET 1
103#define CODA_OPTION_SLICEREPORT_MASK 0x01
104#define CODA_CMD_ENC_SEQ_COD_STD 0x18c
105#define CODA_STD_MPEG4 0
106#define CODA_STD_H263 1
107#define CODA_STD_H264 2
108#define CODA_STD_MJPG 3
109#define CODA_CMD_ENC_SEQ_SRC_SIZE 0x190
110#define CODA7_PICWIDTH_OFFSET 16
111#define CODA7_PICWIDTH_MASK 0xffff
112#define CODADX6_PICWIDTH_OFFSET 10
113#define CODADX6_PICWIDTH_MASK 0x3ff
114#define CODA_PICHEIGHT_OFFSET 0
115#define CODA_PICHEIGHT_MASK 0x3ff
116#define CODA_CMD_ENC_SEQ_SRC_F_RATE 0x194
117#define CODA_CMD_ENC_SEQ_MP4_PARA 0x198
118#define CODA_MP4PARAM_VERID_OFFSET 6
119#define CODA_MP4PARAM_VERID_MASK 0x01
120#define CODA_MP4PARAM_INTRADCVLCTHR_OFFSET 2
121#define CODA_MP4PARAM_INTRADCVLCTHR_MASK 0x07
122#define CODA_MP4PARAM_REVERSIBLEVLCENABLE_OFFSET 1
123#define CODA_MP4PARAM_REVERSIBLEVLCENABLE_MASK 0x01
124#define CODA_MP4PARAM_DATAPARTITIONENABLE_OFFSET 0
125#define CODA_MP4PARAM_DATAPARTITIONENABLE_MASK 0x01
126#define CODA_CMD_ENC_SEQ_263_PARA 0x19c
127#define CODA_263PARAM_ANNEXJENABLE_OFFSET 2
128#define CODA_263PARAM_ANNEXJENABLE_MASK 0x01
129#define CODA_263PARAM_ANNEXKENABLE_OFFSET 1
130#define CODA_263PARAM_ANNEXKENABLE_MASK 0x01
131#define CODA_263PARAM_ANNEXTENABLE_OFFSET 0
132#define CODA_263PARAM_ANNEXTENABLE_MASK 0x01
133#define CODA_CMD_ENC_SEQ_264_PARA 0x1a0
134#define CODA_264PARAM_DEBLKFILTEROFFSETBETA_OFFSET 12
135#define CODA_264PARAM_DEBLKFILTEROFFSETBETA_MASK 0x0f
136#define CODA_264PARAM_DEBLKFILTEROFFSETALPHA_OFFSET 8
137#define CODA_264PARAM_DEBLKFILTEROFFSETALPHA_MASK 0x0f
138#define CODA_264PARAM_DISABLEDEBLK_OFFSET 6
139#define CODA_264PARAM_DISABLEDEBLK_MASK 0x01
140#define CODA_264PARAM_CONSTRAINEDINTRAPREDFLAG_OFFSET 5
141#define CODA_264PARAM_CONSTRAINEDINTRAPREDFLAG_MASK 0x01
142#define CODA_264PARAM_CHROMAQPOFFSET_OFFSET 0
143#define CODA_264PARAM_CHROMAQPOFFSET_MASK 0x1f
144#define CODA_CMD_ENC_SEQ_SLICE_MODE 0x1a4
145#define CODA_SLICING_SIZE_OFFSET 2
146#define CODA_SLICING_SIZE_MASK 0x3fffffff
147#define CODA_SLICING_UNIT_OFFSET 1
148#define CODA_SLICING_UNIT_MASK 0x01
149#define CODA_SLICING_MODE_OFFSET 0
150#define CODA_SLICING_MODE_MASK 0x01
151#define CODA_CMD_ENC_SEQ_GOP_SIZE 0x1a8
152#define CODA_GOP_SIZE_OFFSET 0
153#define CODA_GOP_SIZE_MASK 0x3f
154#define CODA_CMD_ENC_SEQ_RC_PARA 0x1ac
155#define CODA_RATECONTROL_AUTOSKIP_OFFSET 31
156#define CODA_RATECONTROL_AUTOSKIP_MASK 0x01
157#define CODA_RATECONTROL_INITIALDELAY_OFFSET 16
158#define CODA_RATECONTROL_INITIALDELAY_MASK 0x7f
159#define CODA_RATECONTROL_BITRATE_OFFSET 1
160#define CODA_RATECONTROL_BITRATE_MASK 0x7f
161#define CODA_RATECONTROL_ENABLE_OFFSET 0
162#define CODA_RATECONTROL_ENABLE_MASK 0x01
163#define CODA_CMD_ENC_SEQ_RC_BUF_SIZE 0x1b0
164#define CODA_CMD_ENC_SEQ_INTRA_REFRESH 0x1b4
165#define CODA_CMD_ENC_SEQ_FMO 0x1b8
166#define CODA_FMOPARAM_TYPE_OFFSET 4
167#define CODA_FMOPARAM_TYPE_MASK 1
168#define CODA_FMOPARAM_SLICENUM_OFFSET 0
169#define CODA_FMOPARAM_SLICENUM_MASK 0x0f
170#define CODA_CMD_ENC_SEQ_RC_QP_MAX 0x1c8
171#define CODA_QPMAX_OFFSET 0
172#define CODA_QPMAX_MASK 0x3f
173#define CODA_CMD_ENC_SEQ_RC_GAMMA 0x1cc
174#define CODA_GAMMA_OFFSET 0
175#define CODA_GAMMA_MASK 0xffff
176#define CODA_RET_ENC_SEQ_SUCCESS 0x1c0
177
178/* Encoder Picture Run */
179#define CODA_CMD_ENC_PIC_SRC_ADDR_Y 0x180
180#define CODA_CMD_ENC_PIC_SRC_ADDR_CB 0x184
181#define CODA_CMD_ENC_PIC_SRC_ADDR_CR 0x188
182#define CODA_CMD_ENC_PIC_QS 0x18c
183#define CODA_CMD_ENC_PIC_ROT_MODE 0x190
184#define CODA_CMD_ENC_PIC_OPTION 0x194
185#define CODA_CMD_ENC_PIC_BB_START 0x198
186#define CODA_CMD_ENC_PIC_BB_SIZE 0x19c
187#define CODA_RET_ENC_PIC_TYPE 0x1c4
188#define CODA_RET_ENC_PIC_SLICE_NUM 0x1cc
189#define CODA_RET_ENC_PIC_FLAG 0x1d0
190
191/* Set Frame Buffer */
192#define CODA_CMD_SET_FRAME_BUF_NUM 0x180
193#define CODA_CMD_SET_FRAME_BUF_STRIDE 0x184
194
195/* Encoder Header */
196#define CODA_CMD_ENC_HEADER_CODE 0x180
197#define CODA_GAMMA_OFFSET 0
198#define CODA_HEADER_H264_SPS 0
199#define CODA_HEADER_H264_PPS 1
200#define CODA_HEADER_MP4V_VOL 0
201#define CODA_HEADER_MP4V_VOS 1
202#define CODA_HEADER_MP4V_VIS 2
203#define CODA_CMD_ENC_HEADER_BB_START 0x184
204#define CODA_CMD_ENC_HEADER_BB_SIZE 0x188
205
206/* Get Version */
207#define CODA_CMD_FIRMWARE_VERNUM 0x1c0
208#define CODA_FIRMWARE_PRODUCT(x) (((x) >> 16) & 0xffff)
209#define CODA_FIRMWARE_MAJOR(x) (((x) >> 12) & 0x0f)
210#define CODA_FIRMWARE_MINOR(x) (((x) >> 8) & 0x0f)
211#define CODA_FIRMWARE_RELEASE(x) ((x) & 0xff)
212#define CODA_FIRMWARE_VERNUM(product, major, minor, release) \
213 ((product) << 16 | ((major) << 12) | \
214 ((minor) << 8) | (release))
215
216#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 16:57:54 -0500