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authorMauro Carvalho Chehab <mchehab@redhat.com>2012-08-14 16:15:52 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2012-08-15 15:42:46 -0400
commit2a2d1cf46500ab7599d0b45ee837f3936763ccac (patch)
treee21c493977601e02e0425a120795218a58e4c88d /drivers/media/video
parentcb7a01ac324bf2ee2c666f37ac867e4135f9785a (diff)
[media] move soc_camera i2c drivers into its own dir
Move all soc_camera i2c drivers into drivers/media/i2c/soc_camera/. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/video')
-rw-r--r--drivers/media/video/Kconfig87
-rw-r--r--drivers/media/video/Makefile16
-rw-r--r--drivers/media/video/imx074.c475
-rw-r--r--drivers/media/video/mt9m001.c737
-rw-r--r--drivers/media/video/mt9m111.c1014
-rw-r--r--drivers/media/video/mt9t031.c857
-rw-r--r--drivers/media/video/mt9t112.c1125
-rw-r--r--drivers/media/video/mt9v022.c879
-rw-r--r--drivers/media/video/ov2640.c1108
-rw-r--r--drivers/media/video/ov5642.c1073
-rw-r--r--drivers/media/video/ov6650.c1053
-rw-r--r--drivers/media/video/ov772x.c1126
-rw-r--r--drivers/media/video/ov9640.c746
-rw-r--r--drivers/media/video/ov9640.h207
-rw-r--r--drivers/media/video/ov9740.c1005
-rw-r--r--drivers/media/video/rj54n1cb0c.c1414
-rw-r--r--drivers/media/video/sh_mobile_csi2.c398
-rw-r--r--drivers/media/video/soc_camera.c1554
-rw-r--r--drivers/media/video/tw9910.c956
19 files changed, 1 insertions, 15829 deletions
diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
index f2171e777dd3..28b25bf35805 100644
--- a/drivers/media/video/Kconfig
+++ b/drivers/media/video/Kconfig
@@ -127,57 +127,6 @@ config SOC_CAMERA
127 over a bus like PCI or USB. For example some i2c camera connected 127 over a bus like PCI or USB. For example some i2c camera connected
128 directly to the data bus of an SoC. 128 directly to the data bus of an SoC.
129 129
130config SOC_CAMERA_IMX074
131 tristate "imx074 support"
132 depends on SOC_CAMERA && I2C
133 help
134 This driver supports IMX074 cameras from Sony
135
136config SOC_CAMERA_MT9M001
137 tristate "mt9m001 support"
138 depends on SOC_CAMERA && I2C
139 select GPIO_PCA953X if MT9M001_PCA9536_SWITCH
140 help
141 This driver supports MT9M001 cameras from Micron, monochrome
142 and colour models.
143
144config SOC_CAMERA_MT9M111
145 tristate "mt9m111, mt9m112 and mt9m131 support"
146 depends on SOC_CAMERA && I2C
147 help
148 This driver supports MT9M111, MT9M112 and MT9M131 cameras from
149 Micron/Aptina
150
151config SOC_CAMERA_MT9T031
152 tristate "mt9t031 support"
153 depends on SOC_CAMERA && I2C
154 help
155 This driver supports MT9T031 cameras from Micron.
156
157config SOC_CAMERA_MT9T112
158 tristate "mt9t112 support"
159 depends on SOC_CAMERA && I2C
160 help
161 This driver supports MT9T112 cameras from Aptina.
162
163config SOC_CAMERA_MT9V022
164 tristate "mt9v022 support"
165 depends on SOC_CAMERA && I2C
166 select GPIO_PCA953X if MT9V022_PCA9536_SWITCH
167 help
168 This driver supports MT9V022 cameras from Micron
169
170config SOC_CAMERA_RJ54N1
171 tristate "rj54n1cb0c support"
172 depends on SOC_CAMERA && I2C
173 help
174 This is a rj54n1cb0c video driver
175
176config SOC_CAMERA_TW9910
177 tristate "tw9910 support"
178 depends on SOC_CAMERA && I2C
179 help
180 This is a tw9910 video driver
181 130
182config SOC_CAMERA_PLATFORM 131config SOC_CAMERA_PLATFORM
183 tristate "platform camera support" 132 tristate "platform camera support"
@@ -185,42 +134,6 @@ config SOC_CAMERA_PLATFORM
185 help 134 help
186 This is a generic SoC camera platform driver, useful for testing 135 This is a generic SoC camera platform driver, useful for testing
187 136
188config SOC_CAMERA_OV2640
189 tristate "ov2640 camera support"
190 depends on SOC_CAMERA && I2C
191 help
192 This is a ov2640 camera driver
193
194config SOC_CAMERA_OV5642
195 tristate "ov5642 camera support"
196 depends on SOC_CAMERA && I2C
197 help
198 This is a V4L2 camera driver for the OmniVision OV5642 sensor
199
200config SOC_CAMERA_OV6650
201 tristate "ov6650 sensor support"
202 depends on SOC_CAMERA && I2C
203 ---help---
204 This is a V4L2 SoC camera driver for the OmniVision OV6650 sensor
205
206config SOC_CAMERA_OV772X
207 tristate "ov772x camera support"
208 depends on SOC_CAMERA && I2C
209 help
210 This is a ov772x camera driver
211
212config SOC_CAMERA_OV9640
213 tristate "ov9640 camera support"
214 depends on SOC_CAMERA && I2C
215 help
216 This is a ov9640 camera driver
217
218config SOC_CAMERA_OV9740
219 tristate "ov9740 camera support"
220 depends on SOC_CAMERA && I2C
221 help
222 This is a ov9740 camera driver
223
224config MX1_VIDEO 137config MX1_VIDEO
225 bool 138 bool
226 139
diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
index 52a04faa60e8..b3effdc65f76 100644
--- a/drivers/media/video/Makefile
+++ b/drivers/media/video/Makefile
@@ -6,21 +6,6 @@ omap2cam-objs := omap24xxcam.o omap24xxcam-dma.o
6 6
7obj-$(CONFIG_VIDEO_VINO) += indycam.o 7obj-$(CONFIG_VIDEO_VINO) += indycam.o
8 8
9obj-$(CONFIG_SOC_CAMERA_IMX074) += imx074.o
10obj-$(CONFIG_SOC_CAMERA_MT9M001) += mt9m001.o
11obj-$(CONFIG_SOC_CAMERA_MT9M111) += mt9m111.o
12obj-$(CONFIG_SOC_CAMERA_MT9T031) += mt9t031.o
13obj-$(CONFIG_SOC_CAMERA_MT9T112) += mt9t112.o
14obj-$(CONFIG_SOC_CAMERA_MT9V022) += mt9v022.o
15obj-$(CONFIG_SOC_CAMERA_OV2640) += ov2640.o
16obj-$(CONFIG_SOC_CAMERA_OV5642) += ov5642.o
17obj-$(CONFIG_SOC_CAMERA_OV6650) += ov6650.o
18obj-$(CONFIG_SOC_CAMERA_OV772X) += ov772x.o
19obj-$(CONFIG_SOC_CAMERA_OV9640) += ov9640.o
20obj-$(CONFIG_SOC_CAMERA_OV9740) += ov9740.o
21obj-$(CONFIG_SOC_CAMERA_RJ54N1) += rj54n1cb0c.o
22obj-$(CONFIG_SOC_CAMERA_TW9910) += tw9910.o
23
24obj-$(CONFIG_VIDEO_VINO) += vino.o 9obj-$(CONFIG_VIDEO_VINO) += vino.o
25obj-$(CONFIG_VIDEO_TIMBERDALE) += timblogiw.o 10obj-$(CONFIG_VIDEO_TIMBERDALE) += timblogiw.o
26 11
@@ -78,3 +63,4 @@ obj-$(CONFIG_ARCH_OMAP) += omap/
78ccflags-y += -I$(srctree)/drivers/media/dvb-core 63ccflags-y += -I$(srctree)/drivers/media/dvb-core
79ccflags-y += -I$(srctree)/drivers/media/dvb-frontends 64ccflags-y += -I$(srctree)/drivers/media/dvb-frontends
80ccflags-y += -I$(srctree)/drivers/media/tuners 65ccflags-y += -I$(srctree)/drivers/media/tuners
66ccflags-y += -I$(srctree)/drivers/media/i2c/soc_camera
diff --git a/drivers/media/video/imx074.c b/drivers/media/video/imx074.c
deleted file mode 100644
index 351e9bafe8fe..000000000000
--- a/drivers/media/video/imx074.c
+++ /dev/null
@@ -1,475 +0,0 @@
1/*
2 * Driver for IMX074 CMOS Image Sensor from Sony
3 *
4 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
5 *
6 * Partially inspired by the IMX074 driver from the Android / MSM tree
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/delay.h>
14#include <linux/i2c.h>
15#include <linux/v4l2-mediabus.h>
16#include <linux/slab.h>
17#include <linux/videodev2.h>
18#include <linux/module.h>
19
20#include <media/soc_camera.h>
21#include <media/v4l2-subdev.h>
22#include <media/v4l2-chip-ident.h>
23
24/* IMX074 registers */
25
26#define MODE_SELECT 0x0100
27#define IMAGE_ORIENTATION 0x0101
28#define GROUPED_PARAMETER_HOLD 0x0104
29
30/* Integration Time */
31#define COARSE_INTEGRATION_TIME_HI 0x0202
32#define COARSE_INTEGRATION_TIME_LO 0x0203
33/* Gain */
34#define ANALOGUE_GAIN_CODE_GLOBAL_HI 0x0204
35#define ANALOGUE_GAIN_CODE_GLOBAL_LO 0x0205
36
37/* PLL registers */
38#define PRE_PLL_CLK_DIV 0x0305
39#define PLL_MULTIPLIER 0x0307
40#define PLSTATIM 0x302b
41#define VNDMY_ABLMGSHLMT 0x300a
42#define Y_OPBADDR_START_DI 0x3014
43/* mode setting */
44#define FRAME_LENGTH_LINES_HI 0x0340
45#define FRAME_LENGTH_LINES_LO 0x0341
46#define LINE_LENGTH_PCK_HI 0x0342
47#define LINE_LENGTH_PCK_LO 0x0343
48#define YADDR_START 0x0347
49#define YADDR_END 0x034b
50#define X_OUTPUT_SIZE_MSB 0x034c
51#define X_OUTPUT_SIZE_LSB 0x034d
52#define Y_OUTPUT_SIZE_MSB 0x034e
53#define Y_OUTPUT_SIZE_LSB 0x034f
54#define X_EVEN_INC 0x0381
55#define X_ODD_INC 0x0383
56#define Y_EVEN_INC 0x0385
57#define Y_ODD_INC 0x0387
58
59#define HMODEADD 0x3001
60#define VMODEADD 0x3016
61#define VAPPLINE_START 0x3069
62#define VAPPLINE_END 0x306b
63#define SHUTTER 0x3086
64#define HADDAVE 0x30e8
65#define LANESEL 0x3301
66
67/* IMX074 supported geometry */
68#define IMX074_WIDTH 1052
69#define IMX074_HEIGHT 780
70
71/* IMX074 has only one fixed colorspace per pixelcode */
72struct imx074_datafmt {
73 enum v4l2_mbus_pixelcode code;
74 enum v4l2_colorspace colorspace;
75};
76
77struct imx074 {
78 struct v4l2_subdev subdev;
79 const struct imx074_datafmt *fmt;
80};
81
82static const struct imx074_datafmt imx074_colour_fmts[] = {
83 {V4L2_MBUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB},
84};
85
86static struct imx074 *to_imx074(const struct i2c_client *client)
87{
88 return container_of(i2c_get_clientdata(client), struct imx074, subdev);
89}
90
91/* Find a data format by a pixel code in an array */
92static const struct imx074_datafmt *imx074_find_datafmt(enum v4l2_mbus_pixelcode code)
93{
94 int i;
95
96 for (i = 0; i < ARRAY_SIZE(imx074_colour_fmts); i++)
97 if (imx074_colour_fmts[i].code == code)
98 return imx074_colour_fmts + i;
99
100 return NULL;
101}
102
103static int reg_write(struct i2c_client *client, const u16 addr, const u8 data)
104{
105 struct i2c_adapter *adap = client->adapter;
106 struct i2c_msg msg;
107 unsigned char tx[3];
108 int ret;
109
110 msg.addr = client->addr;
111 msg.buf = tx;
112 msg.len = 3;
113 msg.flags = 0;
114
115 tx[0] = addr >> 8;
116 tx[1] = addr & 0xff;
117 tx[2] = data;
118
119 ret = i2c_transfer(adap, &msg, 1);
120
121 mdelay(2);
122
123 return ret == 1 ? 0 : -EIO;
124}
125
126static int reg_read(struct i2c_client *client, const u16 addr)
127{
128 u8 buf[2] = {addr >> 8, addr & 0xff};
129 int ret;
130 struct i2c_msg msgs[] = {
131 {
132 .addr = client->addr,
133 .flags = 0,
134 .len = 2,
135 .buf = buf,
136 }, {
137 .addr = client->addr,
138 .flags = I2C_M_RD,
139 .len = 2,
140 .buf = buf,
141 },
142 };
143
144 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
145 if (ret < 0) {
146 dev_warn(&client->dev, "Reading register %x from %x failed\n",
147 addr, client->addr);
148 return ret;
149 }
150
151 return buf[0] & 0xff; /* no sign-extension */
152}
153
154static int imx074_try_fmt(struct v4l2_subdev *sd,
155 struct v4l2_mbus_framefmt *mf)
156{
157 const struct imx074_datafmt *fmt = imx074_find_datafmt(mf->code);
158
159 dev_dbg(sd->v4l2_dev->dev, "%s(%u)\n", __func__, mf->code);
160
161 if (!fmt) {
162 mf->code = imx074_colour_fmts[0].code;
163 mf->colorspace = imx074_colour_fmts[0].colorspace;
164 }
165
166 mf->width = IMX074_WIDTH;
167 mf->height = IMX074_HEIGHT;
168 mf->field = V4L2_FIELD_NONE;
169
170 return 0;
171}
172
173static int imx074_s_fmt(struct v4l2_subdev *sd,
174 struct v4l2_mbus_framefmt *mf)
175{
176 struct i2c_client *client = v4l2_get_subdevdata(sd);
177 struct imx074 *priv = to_imx074(client);
178
179 dev_dbg(sd->v4l2_dev->dev, "%s(%u)\n", __func__, mf->code);
180
181 /* MIPI CSI could have changed the format, double-check */
182 if (!imx074_find_datafmt(mf->code))
183 return -EINVAL;
184
185 imx074_try_fmt(sd, mf);
186
187 priv->fmt = imx074_find_datafmt(mf->code);
188
189 return 0;
190}
191
192static int imx074_g_fmt(struct v4l2_subdev *sd,
193 struct v4l2_mbus_framefmt *mf)
194{
195 struct i2c_client *client = v4l2_get_subdevdata(sd);
196 struct imx074 *priv = to_imx074(client);
197
198 const struct imx074_datafmt *fmt = priv->fmt;
199
200 mf->code = fmt->code;
201 mf->colorspace = fmt->colorspace;
202 mf->width = IMX074_WIDTH;
203 mf->height = IMX074_HEIGHT;
204 mf->field = V4L2_FIELD_NONE;
205
206 return 0;
207}
208
209static int imx074_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
210{
211 struct v4l2_rect *rect = &a->c;
212
213 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
214 rect->top = 0;
215 rect->left = 0;
216 rect->width = IMX074_WIDTH;
217 rect->height = IMX074_HEIGHT;
218
219 return 0;
220}
221
222static int imx074_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
223{
224 a->bounds.left = 0;
225 a->bounds.top = 0;
226 a->bounds.width = IMX074_WIDTH;
227 a->bounds.height = IMX074_HEIGHT;
228 a->defrect = a->bounds;
229 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
230 a->pixelaspect.numerator = 1;
231 a->pixelaspect.denominator = 1;
232
233 return 0;
234}
235
236static int imx074_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
237 enum v4l2_mbus_pixelcode *code)
238{
239 if ((unsigned int)index >= ARRAY_SIZE(imx074_colour_fmts))
240 return -EINVAL;
241
242 *code = imx074_colour_fmts[index].code;
243 return 0;
244}
245
246static int imx074_s_stream(struct v4l2_subdev *sd, int enable)
247{
248 struct i2c_client *client = v4l2_get_subdevdata(sd);
249
250 /* MODE_SELECT: stream or standby */
251 return reg_write(client, MODE_SELECT, !!enable);
252}
253
254static int imx074_g_chip_ident(struct v4l2_subdev *sd,
255 struct v4l2_dbg_chip_ident *id)
256{
257 struct i2c_client *client = v4l2_get_subdevdata(sd);
258
259 if (id->match.type != V4L2_CHIP_MATCH_I2C_ADDR)
260 return -EINVAL;
261
262 if (id->match.addr != client->addr)
263 return -ENODEV;
264
265 id->ident = V4L2_IDENT_IMX074;
266 id->revision = 0;
267
268 return 0;
269}
270
271static int imx074_g_mbus_config(struct v4l2_subdev *sd,
272 struct v4l2_mbus_config *cfg)
273{
274 cfg->type = V4L2_MBUS_CSI2;
275 cfg->flags = V4L2_MBUS_CSI2_2_LANE |
276 V4L2_MBUS_CSI2_CHANNEL_0 |
277 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
278
279 return 0;
280}
281
282static struct v4l2_subdev_video_ops imx074_subdev_video_ops = {
283 .s_stream = imx074_s_stream,
284 .s_mbus_fmt = imx074_s_fmt,
285 .g_mbus_fmt = imx074_g_fmt,
286 .try_mbus_fmt = imx074_try_fmt,
287 .enum_mbus_fmt = imx074_enum_fmt,
288 .g_crop = imx074_g_crop,
289 .cropcap = imx074_cropcap,
290 .g_mbus_config = imx074_g_mbus_config,
291};
292
293static struct v4l2_subdev_core_ops imx074_subdev_core_ops = {
294 .g_chip_ident = imx074_g_chip_ident,
295};
296
297static struct v4l2_subdev_ops imx074_subdev_ops = {
298 .core = &imx074_subdev_core_ops,
299 .video = &imx074_subdev_video_ops,
300};
301
302static int imx074_video_probe(struct i2c_client *client)
303{
304 int ret;
305 u16 id;
306
307 /* Read sensor Model ID */
308 ret = reg_read(client, 0);
309 if (ret < 0)
310 return ret;
311
312 id = ret << 8;
313
314 ret = reg_read(client, 1);
315 if (ret < 0)
316 return ret;
317
318 id |= ret;
319
320 dev_info(&client->dev, "Chip ID 0x%04x detected\n", id);
321
322 if (id != 0x74)
323 return -ENODEV;
324
325 /* PLL Setting EXTCLK=24MHz, 22.5times */
326 reg_write(client, PLL_MULTIPLIER, 0x2D);
327 reg_write(client, PRE_PLL_CLK_DIV, 0x02);
328 reg_write(client, PLSTATIM, 0x4B);
329
330 /* 2-lane mode */
331 reg_write(client, 0x3024, 0x00);
332
333 reg_write(client, IMAGE_ORIENTATION, 0x00);
334
335 /* select RAW mode:
336 * 0x08+0x08 = top 8 bits
337 * 0x0a+0x08 = compressed 8-bits
338 * 0x0a+0x0a = 10 bits
339 */
340 reg_write(client, 0x0112, 0x08);
341 reg_write(client, 0x0113, 0x08);
342
343 /* Base setting for High frame mode */
344 reg_write(client, VNDMY_ABLMGSHLMT, 0x80);
345 reg_write(client, Y_OPBADDR_START_DI, 0x08);
346 reg_write(client, 0x3015, 0x37);
347 reg_write(client, 0x301C, 0x01);
348 reg_write(client, 0x302C, 0x05);
349 reg_write(client, 0x3031, 0x26);
350 reg_write(client, 0x3041, 0x60);
351 reg_write(client, 0x3051, 0x24);
352 reg_write(client, 0x3053, 0x34);
353 reg_write(client, 0x3057, 0xC0);
354 reg_write(client, 0x305C, 0x09);
355 reg_write(client, 0x305D, 0x07);
356 reg_write(client, 0x3060, 0x30);
357 reg_write(client, 0x3065, 0x00);
358 reg_write(client, 0x30AA, 0x08);
359 reg_write(client, 0x30AB, 0x1C);
360 reg_write(client, 0x30B0, 0x32);
361 reg_write(client, 0x30B2, 0x83);
362 reg_write(client, 0x30D3, 0x04);
363 reg_write(client, 0x3106, 0x78);
364 reg_write(client, 0x310C, 0x82);
365 reg_write(client, 0x3304, 0x05);
366 reg_write(client, 0x3305, 0x04);
367 reg_write(client, 0x3306, 0x11);
368 reg_write(client, 0x3307, 0x02);
369 reg_write(client, 0x3308, 0x0C);
370 reg_write(client, 0x3309, 0x06);
371 reg_write(client, 0x330A, 0x08);
372 reg_write(client, 0x330B, 0x04);
373 reg_write(client, 0x330C, 0x08);
374 reg_write(client, 0x330D, 0x06);
375 reg_write(client, 0x330E, 0x01);
376 reg_write(client, 0x3381, 0x00);
377
378 /* V : 1/2V-addition (1,3), H : 1/2H-averaging (1,3) -> Full HD */
379 /* 1608 = 1560 + 48 (black lines) */
380 reg_write(client, FRAME_LENGTH_LINES_HI, 0x06);
381 reg_write(client, FRAME_LENGTH_LINES_LO, 0x48);
382 reg_write(client, YADDR_START, 0x00);
383 reg_write(client, YADDR_END, 0x2F);
384 /* 0x838 == 2104 */
385 reg_write(client, X_OUTPUT_SIZE_MSB, 0x08);
386 reg_write(client, X_OUTPUT_SIZE_LSB, 0x38);
387 /* 0x618 == 1560 */
388 reg_write(client, Y_OUTPUT_SIZE_MSB, 0x06);
389 reg_write(client, Y_OUTPUT_SIZE_LSB, 0x18);
390 reg_write(client, X_EVEN_INC, 0x01);
391 reg_write(client, X_ODD_INC, 0x03);
392 reg_write(client, Y_EVEN_INC, 0x01);
393 reg_write(client, Y_ODD_INC, 0x03);
394 reg_write(client, HMODEADD, 0x00);
395 reg_write(client, VMODEADD, 0x16);
396 reg_write(client, VAPPLINE_START, 0x24);
397 reg_write(client, VAPPLINE_END, 0x53);
398 reg_write(client, SHUTTER, 0x00);
399 reg_write(client, HADDAVE, 0x80);
400
401 reg_write(client, LANESEL, 0x00);
402
403 reg_write(client, GROUPED_PARAMETER_HOLD, 0x00); /* off */
404
405 return 0;
406}
407
408static int imx074_probe(struct i2c_client *client,
409 const struct i2c_device_id *did)
410{
411 struct imx074 *priv;
412 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
413 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
414 int ret;
415
416 if (!icl) {
417 dev_err(&client->dev, "IMX074: missing platform data!\n");
418 return -EINVAL;
419 }
420
421 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
422 dev_warn(&adapter->dev,
423 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_BYTE\n");
424 return -EIO;
425 }
426
427 priv = kzalloc(sizeof(struct imx074), GFP_KERNEL);
428 if (!priv)
429 return -ENOMEM;
430
431 v4l2_i2c_subdev_init(&priv->subdev, client, &imx074_subdev_ops);
432
433 priv->fmt = &imx074_colour_fmts[0];
434
435 ret = imx074_video_probe(client);
436 if (ret < 0) {
437 kfree(priv);
438 return ret;
439 }
440
441 return ret;
442}
443
444static int imx074_remove(struct i2c_client *client)
445{
446 struct imx074 *priv = to_imx074(client);
447 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
448
449 if (icl->free_bus)
450 icl->free_bus(icl);
451 kfree(priv);
452
453 return 0;
454}
455
456static const struct i2c_device_id imx074_id[] = {
457 { "imx074", 0 },
458 { }
459};
460MODULE_DEVICE_TABLE(i2c, imx074_id);
461
462static struct i2c_driver imx074_i2c_driver = {
463 .driver = {
464 .name = "imx074",
465 },
466 .probe = imx074_probe,
467 .remove = imx074_remove,
468 .id_table = imx074_id,
469};
470
471module_i2c_driver(imx074_i2c_driver);
472
473MODULE_DESCRIPTION("Sony IMX074 Camera driver");
474MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
475MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/video/mt9m001.c b/drivers/media/video/mt9m001.c
deleted file mode 100644
index 00583f5fd26b..000000000000
--- a/drivers/media/video/mt9m001.c
+++ /dev/null
@@ -1,737 +0,0 @@
1/*
2 * Driver for MT9M001 CMOS Image Sensor from Micron
3 *
4 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/videodev2.h>
12#include <linux/slab.h>
13#include <linux/i2c.h>
14#include <linux/log2.h>
15#include <linux/module.h>
16
17#include <media/soc_camera.h>
18#include <media/soc_mediabus.h>
19#include <media/v4l2-subdev.h>
20#include <media/v4l2-chip-ident.h>
21#include <media/v4l2-ctrls.h>
22
23/*
24 * mt9m001 i2c address 0x5d
25 * The platform has to define struct i2c_board_info objects and link to them
26 * from struct soc_camera_link
27 */
28
29/* mt9m001 selected register addresses */
30#define MT9M001_CHIP_VERSION 0x00
31#define MT9M001_ROW_START 0x01
32#define MT9M001_COLUMN_START 0x02
33#define MT9M001_WINDOW_HEIGHT 0x03
34#define MT9M001_WINDOW_WIDTH 0x04
35#define MT9M001_HORIZONTAL_BLANKING 0x05
36#define MT9M001_VERTICAL_BLANKING 0x06
37#define MT9M001_OUTPUT_CONTROL 0x07
38#define MT9M001_SHUTTER_WIDTH 0x09
39#define MT9M001_FRAME_RESTART 0x0b
40#define MT9M001_SHUTTER_DELAY 0x0c
41#define MT9M001_RESET 0x0d
42#define MT9M001_READ_OPTIONS1 0x1e
43#define MT9M001_READ_OPTIONS2 0x20
44#define MT9M001_GLOBAL_GAIN 0x35
45#define MT9M001_CHIP_ENABLE 0xF1
46
47#define MT9M001_MAX_WIDTH 1280
48#define MT9M001_MAX_HEIGHT 1024
49#define MT9M001_MIN_WIDTH 48
50#define MT9M001_MIN_HEIGHT 32
51#define MT9M001_COLUMN_SKIP 20
52#define MT9M001_ROW_SKIP 12
53
54/* MT9M001 has only one fixed colorspace per pixelcode */
55struct mt9m001_datafmt {
56 enum v4l2_mbus_pixelcode code;
57 enum v4l2_colorspace colorspace;
58};
59
60/* Find a data format by a pixel code in an array */
61static const struct mt9m001_datafmt *mt9m001_find_datafmt(
62 enum v4l2_mbus_pixelcode code, const struct mt9m001_datafmt *fmt,
63 int n)
64{
65 int i;
66 for (i = 0; i < n; i++)
67 if (fmt[i].code == code)
68 return fmt + i;
69
70 return NULL;
71}
72
73static const struct mt9m001_datafmt mt9m001_colour_fmts[] = {
74 /*
75 * Order important: first natively supported,
76 * second supported with a GPIO extender
77 */
78 {V4L2_MBUS_FMT_SBGGR10_1X10, V4L2_COLORSPACE_SRGB},
79 {V4L2_MBUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB},
80};
81
82static const struct mt9m001_datafmt mt9m001_monochrome_fmts[] = {
83 /* Order important - see above */
84 {V4L2_MBUS_FMT_Y10_1X10, V4L2_COLORSPACE_JPEG},
85 {V4L2_MBUS_FMT_Y8_1X8, V4L2_COLORSPACE_JPEG},
86};
87
88struct mt9m001 {
89 struct v4l2_subdev subdev;
90 struct v4l2_ctrl_handler hdl;
91 struct {
92 /* exposure/auto-exposure cluster */
93 struct v4l2_ctrl *autoexposure;
94 struct v4l2_ctrl *exposure;
95 };
96 struct v4l2_rect rect; /* Sensor window */
97 const struct mt9m001_datafmt *fmt;
98 const struct mt9m001_datafmt *fmts;
99 int num_fmts;
100 int model; /* V4L2_IDENT_MT9M001* codes from v4l2-chip-ident.h */
101 unsigned int total_h;
102 unsigned short y_skip_top; /* Lines to skip at the top */
103};
104
105static struct mt9m001 *to_mt9m001(const struct i2c_client *client)
106{
107 return container_of(i2c_get_clientdata(client), struct mt9m001, subdev);
108}
109
110static int reg_read(struct i2c_client *client, const u8 reg)
111{
112 return i2c_smbus_read_word_swapped(client, reg);
113}
114
115static int reg_write(struct i2c_client *client, const u8 reg,
116 const u16 data)
117{
118 return i2c_smbus_write_word_swapped(client, reg, data);
119}
120
121static int reg_set(struct i2c_client *client, const u8 reg,
122 const u16 data)
123{
124 int ret;
125
126 ret = reg_read(client, reg);
127 if (ret < 0)
128 return ret;
129 return reg_write(client, reg, ret | data);
130}
131
132static int reg_clear(struct i2c_client *client, const u8 reg,
133 const u16 data)
134{
135 int ret;
136
137 ret = reg_read(client, reg);
138 if (ret < 0)
139 return ret;
140 return reg_write(client, reg, ret & ~data);
141}
142
143static int mt9m001_init(struct i2c_client *client)
144{
145 int ret;
146
147 dev_dbg(&client->dev, "%s\n", __func__);
148
149 /*
150 * We don't know, whether platform provides reset, issue a soft reset
151 * too. This returns all registers to their default values.
152 */
153 ret = reg_write(client, MT9M001_RESET, 1);
154 if (!ret)
155 ret = reg_write(client, MT9M001_RESET, 0);
156
157 /* Disable chip, synchronous option update */
158 if (!ret)
159 ret = reg_write(client, MT9M001_OUTPUT_CONTROL, 0);
160
161 return ret;
162}
163
164static int mt9m001_s_stream(struct v4l2_subdev *sd, int enable)
165{
166 struct i2c_client *client = v4l2_get_subdevdata(sd);
167
168 /* Switch to master "normal" mode or stop sensor readout */
169 if (reg_write(client, MT9M001_OUTPUT_CONTROL, enable ? 2 : 0) < 0)
170 return -EIO;
171 return 0;
172}
173
174static int mt9m001_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
175{
176 struct i2c_client *client = v4l2_get_subdevdata(sd);
177 struct mt9m001 *mt9m001 = to_mt9m001(client);
178 struct v4l2_rect rect = a->c;
179 int ret;
180 const u16 hblank = 9, vblank = 25;
181
182 if (mt9m001->fmts == mt9m001_colour_fmts)
183 /*
184 * Bayer format - even number of rows for simplicity,
185 * but let the user play with the top row.
186 */
187 rect.height = ALIGN(rect.height, 2);
188
189 /* Datasheet requirement: see register description */
190 rect.width = ALIGN(rect.width, 2);
191 rect.left = ALIGN(rect.left, 2);
192
193 soc_camera_limit_side(&rect.left, &rect.width,
194 MT9M001_COLUMN_SKIP, MT9M001_MIN_WIDTH, MT9M001_MAX_WIDTH);
195
196 soc_camera_limit_side(&rect.top, &rect.height,
197 MT9M001_ROW_SKIP, MT9M001_MIN_HEIGHT, MT9M001_MAX_HEIGHT);
198
199 mt9m001->total_h = rect.height + mt9m001->y_skip_top + vblank;
200
201 /* Blanking and start values - default... */
202 ret = reg_write(client, MT9M001_HORIZONTAL_BLANKING, hblank);
203 if (!ret)
204 ret = reg_write(client, MT9M001_VERTICAL_BLANKING, vblank);
205
206 /*
207 * The caller provides a supported format, as verified per
208 * call to .try_mbus_fmt()
209 */
210 if (!ret)
211 ret = reg_write(client, MT9M001_COLUMN_START, rect.left);
212 if (!ret)
213 ret = reg_write(client, MT9M001_ROW_START, rect.top);
214 if (!ret)
215 ret = reg_write(client, MT9M001_WINDOW_WIDTH, rect.width - 1);
216 if (!ret)
217 ret = reg_write(client, MT9M001_WINDOW_HEIGHT,
218 rect.height + mt9m001->y_skip_top - 1);
219 if (!ret && v4l2_ctrl_g_ctrl(mt9m001->autoexposure) == V4L2_EXPOSURE_AUTO)
220 ret = reg_write(client, MT9M001_SHUTTER_WIDTH, mt9m001->total_h);
221
222 if (!ret)
223 mt9m001->rect = rect;
224
225 return ret;
226}
227
228static int mt9m001_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
229{
230 struct i2c_client *client = v4l2_get_subdevdata(sd);
231 struct mt9m001 *mt9m001 = to_mt9m001(client);
232
233 a->c = mt9m001->rect;
234 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
235
236 return 0;
237}
238
239static int mt9m001_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
240{
241 a->bounds.left = MT9M001_COLUMN_SKIP;
242 a->bounds.top = MT9M001_ROW_SKIP;
243 a->bounds.width = MT9M001_MAX_WIDTH;
244 a->bounds.height = MT9M001_MAX_HEIGHT;
245 a->defrect = a->bounds;
246 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
247 a->pixelaspect.numerator = 1;
248 a->pixelaspect.denominator = 1;
249
250 return 0;
251}
252
253static int mt9m001_g_fmt(struct v4l2_subdev *sd,
254 struct v4l2_mbus_framefmt *mf)
255{
256 struct i2c_client *client = v4l2_get_subdevdata(sd);
257 struct mt9m001 *mt9m001 = to_mt9m001(client);
258
259 mf->width = mt9m001->rect.width;
260 mf->height = mt9m001->rect.height;
261 mf->code = mt9m001->fmt->code;
262 mf->colorspace = mt9m001->fmt->colorspace;
263 mf->field = V4L2_FIELD_NONE;
264
265 return 0;
266}
267
268static int mt9m001_s_fmt(struct v4l2_subdev *sd,
269 struct v4l2_mbus_framefmt *mf)
270{
271 struct i2c_client *client = v4l2_get_subdevdata(sd);
272 struct mt9m001 *mt9m001 = to_mt9m001(client);
273 struct v4l2_crop a = {
274 .c = {
275 .left = mt9m001->rect.left,
276 .top = mt9m001->rect.top,
277 .width = mf->width,
278 .height = mf->height,
279 },
280 };
281 int ret;
282
283 /* No support for scaling so far, just crop. TODO: use skipping */
284 ret = mt9m001_s_crop(sd, &a);
285 if (!ret) {
286 mf->width = mt9m001->rect.width;
287 mf->height = mt9m001->rect.height;
288 mt9m001->fmt = mt9m001_find_datafmt(mf->code,
289 mt9m001->fmts, mt9m001->num_fmts);
290 mf->colorspace = mt9m001->fmt->colorspace;
291 }
292
293 return ret;
294}
295
296static int mt9m001_try_fmt(struct v4l2_subdev *sd,
297 struct v4l2_mbus_framefmt *mf)
298{
299 struct i2c_client *client = v4l2_get_subdevdata(sd);
300 struct mt9m001 *mt9m001 = to_mt9m001(client);
301 const struct mt9m001_datafmt *fmt;
302
303 v4l_bound_align_image(&mf->width, MT9M001_MIN_WIDTH,
304 MT9M001_MAX_WIDTH, 1,
305 &mf->height, MT9M001_MIN_HEIGHT + mt9m001->y_skip_top,
306 MT9M001_MAX_HEIGHT + mt9m001->y_skip_top, 0, 0);
307
308 if (mt9m001->fmts == mt9m001_colour_fmts)
309 mf->height = ALIGN(mf->height - 1, 2);
310
311 fmt = mt9m001_find_datafmt(mf->code, mt9m001->fmts,
312 mt9m001->num_fmts);
313 if (!fmt) {
314 fmt = mt9m001->fmt;
315 mf->code = fmt->code;
316 }
317
318 mf->colorspace = fmt->colorspace;
319
320 return 0;
321}
322
323static int mt9m001_g_chip_ident(struct v4l2_subdev *sd,
324 struct v4l2_dbg_chip_ident *id)
325{
326 struct i2c_client *client = v4l2_get_subdevdata(sd);
327 struct mt9m001 *mt9m001 = to_mt9m001(client);
328
329 if (id->match.type != V4L2_CHIP_MATCH_I2C_ADDR)
330 return -EINVAL;
331
332 if (id->match.addr != client->addr)
333 return -ENODEV;
334
335 id->ident = mt9m001->model;
336 id->revision = 0;
337
338 return 0;
339}
340
341#ifdef CONFIG_VIDEO_ADV_DEBUG
342static int mt9m001_g_register(struct v4l2_subdev *sd,
343 struct v4l2_dbg_register *reg)
344{
345 struct i2c_client *client = v4l2_get_subdevdata(sd);
346
347 if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0xff)
348 return -EINVAL;
349
350 if (reg->match.addr != client->addr)
351 return -ENODEV;
352
353 reg->size = 2;
354 reg->val = reg_read(client, reg->reg);
355
356 if (reg->val > 0xffff)
357 return -EIO;
358
359 return 0;
360}
361
362static int mt9m001_s_register(struct v4l2_subdev *sd,
363 struct v4l2_dbg_register *reg)
364{
365 struct i2c_client *client = v4l2_get_subdevdata(sd);
366
367 if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0xff)
368 return -EINVAL;
369
370 if (reg->match.addr != client->addr)
371 return -ENODEV;
372
373 if (reg_write(client, reg->reg, reg->val) < 0)
374 return -EIO;
375
376 return 0;
377}
378#endif
379
380static int mt9m001_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
381{
382 struct mt9m001 *mt9m001 = container_of(ctrl->handler,
383 struct mt9m001, hdl);
384 s32 min, max;
385
386 switch (ctrl->id) {
387 case V4L2_CID_EXPOSURE_AUTO:
388 min = mt9m001->exposure->minimum;
389 max = mt9m001->exposure->maximum;
390 mt9m001->exposure->val =
391 (524 + (mt9m001->total_h - 1) * (max - min)) / 1048 + min;
392 break;
393 }
394 return 0;
395}
396
397static int mt9m001_s_ctrl(struct v4l2_ctrl *ctrl)
398{
399 struct mt9m001 *mt9m001 = container_of(ctrl->handler,
400 struct mt9m001, hdl);
401 struct v4l2_subdev *sd = &mt9m001->subdev;
402 struct i2c_client *client = v4l2_get_subdevdata(sd);
403 struct v4l2_ctrl *exp = mt9m001->exposure;
404 int data;
405
406 switch (ctrl->id) {
407 case V4L2_CID_VFLIP:
408 if (ctrl->val)
409 data = reg_set(client, MT9M001_READ_OPTIONS2, 0x8000);
410 else
411 data = reg_clear(client, MT9M001_READ_OPTIONS2, 0x8000);
412 if (data < 0)
413 return -EIO;
414 return 0;
415
416 case V4L2_CID_GAIN:
417 /* See Datasheet Table 7, Gain settings. */
418 if (ctrl->val <= ctrl->default_value) {
419 /* Pack it into 0..1 step 0.125, register values 0..8 */
420 unsigned long range = ctrl->default_value - ctrl->minimum;
421 data = ((ctrl->val - ctrl->minimum) * 8 + range / 2) / range;
422
423 dev_dbg(&client->dev, "Setting gain %d\n", data);
424 data = reg_write(client, MT9M001_GLOBAL_GAIN, data);
425 if (data < 0)
426 return -EIO;
427 } else {
428 /* Pack it into 1.125..15 variable step, register values 9..67 */
429 /* We assume qctrl->maximum - qctrl->default_value - 1 > 0 */
430 unsigned long range = ctrl->maximum - ctrl->default_value - 1;
431 unsigned long gain = ((ctrl->val - ctrl->default_value - 1) *
432 111 + range / 2) / range + 9;
433
434 if (gain <= 32)
435 data = gain;
436 else if (gain <= 64)
437 data = ((gain - 32) * 16 + 16) / 32 + 80;
438 else
439 data = ((gain - 64) * 7 + 28) / 56 + 96;
440
441 dev_dbg(&client->dev, "Setting gain from %d to %d\n",
442 reg_read(client, MT9M001_GLOBAL_GAIN), data);
443 data = reg_write(client, MT9M001_GLOBAL_GAIN, data);
444 if (data < 0)
445 return -EIO;
446 }
447 return 0;
448
449 case V4L2_CID_EXPOSURE_AUTO:
450 if (ctrl->val == V4L2_EXPOSURE_MANUAL) {
451 unsigned long range = exp->maximum - exp->minimum;
452 unsigned long shutter = ((exp->val - exp->minimum) * 1048 +
453 range / 2) / range + 1;
454
455 dev_dbg(&client->dev,
456 "Setting shutter width from %d to %lu\n",
457 reg_read(client, MT9M001_SHUTTER_WIDTH), shutter);
458 if (reg_write(client, MT9M001_SHUTTER_WIDTH, shutter) < 0)
459 return -EIO;
460 } else {
461 const u16 vblank = 25;
462
463 mt9m001->total_h = mt9m001->rect.height +
464 mt9m001->y_skip_top + vblank;
465 if (reg_write(client, MT9M001_SHUTTER_WIDTH, mt9m001->total_h) < 0)
466 return -EIO;
467 }
468 return 0;
469 }
470 return -EINVAL;
471}
472
473/*
474 * Interface active, can use i2c. If it fails, it can indeed mean, that
475 * this wasn't our capture interface, so, we wait for the right one
476 */
477static int mt9m001_video_probe(struct soc_camera_link *icl,
478 struct i2c_client *client)
479{
480 struct mt9m001 *mt9m001 = to_mt9m001(client);
481 s32 data;
482 unsigned long flags;
483 int ret;
484
485 /* Enable the chip */
486 data = reg_write(client, MT9M001_CHIP_ENABLE, 1);
487 dev_dbg(&client->dev, "write: %d\n", data);
488
489 /* Read out the chip version register */
490 data = reg_read(client, MT9M001_CHIP_VERSION);
491
492 /* must be 0x8411 or 0x8421 for colour sensor and 8431 for bw */
493 switch (data) {
494 case 0x8411:
495 case 0x8421:
496 mt9m001->model = V4L2_IDENT_MT9M001C12ST;
497 mt9m001->fmts = mt9m001_colour_fmts;
498 break;
499 case 0x8431:
500 mt9m001->model = V4L2_IDENT_MT9M001C12STM;
501 mt9m001->fmts = mt9m001_monochrome_fmts;
502 break;
503 default:
504 dev_err(&client->dev,
505 "No MT9M001 chip detected, register read %x\n", data);
506 return -ENODEV;
507 }
508
509 mt9m001->num_fmts = 0;
510
511 /*
512 * This is a 10bit sensor, so by default we only allow 10bit.
513 * The platform may support different bus widths due to
514 * different routing of the data lines.
515 */
516 if (icl->query_bus_param)
517 flags = icl->query_bus_param(icl);
518 else
519 flags = SOCAM_DATAWIDTH_10;
520
521 if (flags & SOCAM_DATAWIDTH_10)
522 mt9m001->num_fmts++;
523 else
524 mt9m001->fmts++;
525
526 if (flags & SOCAM_DATAWIDTH_8)
527 mt9m001->num_fmts++;
528
529 mt9m001->fmt = &mt9m001->fmts[0];
530
531 dev_info(&client->dev, "Detected a MT9M001 chip ID %x (%s)\n", data,
532 data == 0x8431 ? "C12STM" : "C12ST");
533
534 ret = mt9m001_init(client);
535 if (ret < 0)
536 dev_err(&client->dev, "Failed to initialise the camera\n");
537
538 /* mt9m001_init() has reset the chip, returning registers to defaults */
539 return v4l2_ctrl_handler_setup(&mt9m001->hdl);
540}
541
542static void mt9m001_video_remove(struct soc_camera_link *icl)
543{
544 if (icl->free_bus)
545 icl->free_bus(icl);
546}
547
548static int mt9m001_g_skip_top_lines(struct v4l2_subdev *sd, u32 *lines)
549{
550 struct i2c_client *client = v4l2_get_subdevdata(sd);
551 struct mt9m001 *mt9m001 = to_mt9m001(client);
552
553 *lines = mt9m001->y_skip_top;
554
555 return 0;
556}
557
558static const struct v4l2_ctrl_ops mt9m001_ctrl_ops = {
559 .g_volatile_ctrl = mt9m001_g_volatile_ctrl,
560 .s_ctrl = mt9m001_s_ctrl,
561};
562
563static struct v4l2_subdev_core_ops mt9m001_subdev_core_ops = {
564 .g_chip_ident = mt9m001_g_chip_ident,
565#ifdef CONFIG_VIDEO_ADV_DEBUG
566 .g_register = mt9m001_g_register,
567 .s_register = mt9m001_s_register,
568#endif
569};
570
571static int mt9m001_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
572 enum v4l2_mbus_pixelcode *code)
573{
574 struct i2c_client *client = v4l2_get_subdevdata(sd);
575 struct mt9m001 *mt9m001 = to_mt9m001(client);
576
577 if (index >= mt9m001->num_fmts)
578 return -EINVAL;
579
580 *code = mt9m001->fmts[index].code;
581 return 0;
582}
583
584static int mt9m001_g_mbus_config(struct v4l2_subdev *sd,
585 struct v4l2_mbus_config *cfg)
586{
587 struct i2c_client *client = v4l2_get_subdevdata(sd);
588 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
589
590 /* MT9M001 has all capture_format parameters fixed */
591 cfg->flags = V4L2_MBUS_PCLK_SAMPLE_FALLING |
592 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_HIGH |
593 V4L2_MBUS_DATA_ACTIVE_HIGH | V4L2_MBUS_MASTER;
594 cfg->type = V4L2_MBUS_PARALLEL;
595 cfg->flags = soc_camera_apply_board_flags(icl, cfg);
596
597 return 0;
598}
599
600static int mt9m001_s_mbus_config(struct v4l2_subdev *sd,
601 const struct v4l2_mbus_config *cfg)
602{
603 const struct i2c_client *client = v4l2_get_subdevdata(sd);
604 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
605 struct mt9m001 *mt9m001 = to_mt9m001(client);
606 unsigned int bps = soc_mbus_get_fmtdesc(mt9m001->fmt->code)->bits_per_sample;
607
608 if (icl->set_bus_param)
609 return icl->set_bus_param(icl, 1 << (bps - 1));
610
611 /*
612 * Without board specific bus width settings we only support the
613 * sensors native bus width
614 */
615 return bps == 10 ? 0 : -EINVAL;
616}
617
618static struct v4l2_subdev_video_ops mt9m001_subdev_video_ops = {
619 .s_stream = mt9m001_s_stream,
620 .s_mbus_fmt = mt9m001_s_fmt,
621 .g_mbus_fmt = mt9m001_g_fmt,
622 .try_mbus_fmt = mt9m001_try_fmt,
623 .s_crop = mt9m001_s_crop,
624 .g_crop = mt9m001_g_crop,
625 .cropcap = mt9m001_cropcap,
626 .enum_mbus_fmt = mt9m001_enum_fmt,
627 .g_mbus_config = mt9m001_g_mbus_config,
628 .s_mbus_config = mt9m001_s_mbus_config,
629};
630
631static struct v4l2_subdev_sensor_ops mt9m001_subdev_sensor_ops = {
632 .g_skip_top_lines = mt9m001_g_skip_top_lines,
633};
634
635static struct v4l2_subdev_ops mt9m001_subdev_ops = {
636 .core = &mt9m001_subdev_core_ops,
637 .video = &mt9m001_subdev_video_ops,
638 .sensor = &mt9m001_subdev_sensor_ops,
639};
640
641static int mt9m001_probe(struct i2c_client *client,
642 const struct i2c_device_id *did)
643{
644 struct mt9m001 *mt9m001;
645 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
646 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
647 int ret;
648
649 if (!icl) {
650 dev_err(&client->dev, "MT9M001 driver needs platform data\n");
651 return -EINVAL;
652 }
653
654 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) {
655 dev_warn(&adapter->dev,
656 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
657 return -EIO;
658 }
659
660 mt9m001 = kzalloc(sizeof(struct mt9m001), GFP_KERNEL);
661 if (!mt9m001)
662 return -ENOMEM;
663
664 v4l2_i2c_subdev_init(&mt9m001->subdev, client, &mt9m001_subdev_ops);
665 v4l2_ctrl_handler_init(&mt9m001->hdl, 4);
666 v4l2_ctrl_new_std(&mt9m001->hdl, &mt9m001_ctrl_ops,
667 V4L2_CID_VFLIP, 0, 1, 1, 0);
668 v4l2_ctrl_new_std(&mt9m001->hdl, &mt9m001_ctrl_ops,
669 V4L2_CID_GAIN, 0, 127, 1, 64);
670 mt9m001->exposure = v4l2_ctrl_new_std(&mt9m001->hdl, &mt9m001_ctrl_ops,
671 V4L2_CID_EXPOSURE, 1, 255, 1, 255);
672 /*
673 * Simulated autoexposure. If enabled, we calculate shutter width
674 * ourselves in the driver based on vertical blanking and frame width
675 */
676 mt9m001->autoexposure = v4l2_ctrl_new_std_menu(&mt9m001->hdl,
677 &mt9m001_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, 1, 0,
678 V4L2_EXPOSURE_AUTO);
679 mt9m001->subdev.ctrl_handler = &mt9m001->hdl;
680 if (mt9m001->hdl.error) {
681 int err = mt9m001->hdl.error;
682
683 kfree(mt9m001);
684 return err;
685 }
686 v4l2_ctrl_auto_cluster(2, &mt9m001->autoexposure,
687 V4L2_EXPOSURE_MANUAL, true);
688
689 /* Second stage probe - when a capture adapter is there */
690 mt9m001->y_skip_top = 0;
691 mt9m001->rect.left = MT9M001_COLUMN_SKIP;
692 mt9m001->rect.top = MT9M001_ROW_SKIP;
693 mt9m001->rect.width = MT9M001_MAX_WIDTH;
694 mt9m001->rect.height = MT9M001_MAX_HEIGHT;
695
696 ret = mt9m001_video_probe(icl, client);
697 if (ret) {
698 v4l2_ctrl_handler_free(&mt9m001->hdl);
699 kfree(mt9m001);
700 }
701
702 return ret;
703}
704
705static int mt9m001_remove(struct i2c_client *client)
706{
707 struct mt9m001 *mt9m001 = to_mt9m001(client);
708 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
709
710 v4l2_device_unregister_subdev(&mt9m001->subdev);
711 v4l2_ctrl_handler_free(&mt9m001->hdl);
712 mt9m001_video_remove(icl);
713 kfree(mt9m001);
714
715 return 0;
716}
717
718static const struct i2c_device_id mt9m001_id[] = {
719 { "mt9m001", 0 },
720 { }
721};
722MODULE_DEVICE_TABLE(i2c, mt9m001_id);
723
724static struct i2c_driver mt9m001_i2c_driver = {
725 .driver = {
726 .name = "mt9m001",
727 },
728 .probe = mt9m001_probe,
729 .remove = mt9m001_remove,
730 .id_table = mt9m001_id,
731};
732
733module_i2c_driver(mt9m001_i2c_driver);
734
735MODULE_DESCRIPTION("Micron MT9M001 Camera driver");
736MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
737MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/mt9m111.c b/drivers/media/video/mt9m111.c
deleted file mode 100644
index 863d722dda06..000000000000
--- a/drivers/media/video/mt9m111.c
+++ /dev/null
@@ -1,1014 +0,0 @@
1/*
2 * Driver for MT9M111/MT9M112/MT9M131 CMOS Image Sensor from Micron/Aptina
3 *
4 * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/videodev2.h>
11#include <linux/slab.h>
12#include <linux/i2c.h>
13#include <linux/log2.h>
14#include <linux/gpio.h>
15#include <linux/delay.h>
16#include <linux/v4l2-mediabus.h>
17#include <linux/module.h>
18
19#include <media/soc_camera.h>
20#include <media/v4l2-common.h>
21#include <media/v4l2-ctrls.h>
22#include <media/v4l2-chip-ident.h>
23
24/*
25 * MT9M111, MT9M112 and MT9M131:
26 * i2c address is 0x48 or 0x5d (depending on SADDR pin)
27 * The platform has to define i2c_board_info and call i2c_register_board_info()
28 */
29
30/*
31 * Sensor core register addresses (0x000..0x0ff)
32 */
33#define MT9M111_CHIP_VERSION 0x000
34#define MT9M111_ROW_START 0x001
35#define MT9M111_COLUMN_START 0x002
36#define MT9M111_WINDOW_HEIGHT 0x003
37#define MT9M111_WINDOW_WIDTH 0x004
38#define MT9M111_HORIZONTAL_BLANKING_B 0x005
39#define MT9M111_VERTICAL_BLANKING_B 0x006
40#define MT9M111_HORIZONTAL_BLANKING_A 0x007
41#define MT9M111_VERTICAL_BLANKING_A 0x008
42#define MT9M111_SHUTTER_WIDTH 0x009
43#define MT9M111_ROW_SPEED 0x00a
44#define MT9M111_EXTRA_DELAY 0x00b
45#define MT9M111_SHUTTER_DELAY 0x00c
46#define MT9M111_RESET 0x00d
47#define MT9M111_READ_MODE_B 0x020
48#define MT9M111_READ_MODE_A 0x021
49#define MT9M111_FLASH_CONTROL 0x023
50#define MT9M111_GREEN1_GAIN 0x02b
51#define MT9M111_BLUE_GAIN 0x02c
52#define MT9M111_RED_GAIN 0x02d
53#define MT9M111_GREEN2_GAIN 0x02e
54#define MT9M111_GLOBAL_GAIN 0x02f
55#define MT9M111_CONTEXT_CONTROL 0x0c8
56#define MT9M111_PAGE_MAP 0x0f0
57#define MT9M111_BYTE_WISE_ADDR 0x0f1
58
59#define MT9M111_RESET_SYNC_CHANGES (1 << 15)
60#define MT9M111_RESET_RESTART_BAD_FRAME (1 << 9)
61#define MT9M111_RESET_SHOW_BAD_FRAMES (1 << 8)
62#define MT9M111_RESET_RESET_SOC (1 << 5)
63#define MT9M111_RESET_OUTPUT_DISABLE (1 << 4)
64#define MT9M111_RESET_CHIP_ENABLE (1 << 3)
65#define MT9M111_RESET_ANALOG_STANDBY (1 << 2)
66#define MT9M111_RESET_RESTART_FRAME (1 << 1)
67#define MT9M111_RESET_RESET_MODE (1 << 0)
68
69#define MT9M111_RM_FULL_POWER_RD (0 << 10)
70#define MT9M111_RM_LOW_POWER_RD (1 << 10)
71#define MT9M111_RM_COL_SKIP_4X (1 << 5)
72#define MT9M111_RM_ROW_SKIP_4X (1 << 4)
73#define MT9M111_RM_COL_SKIP_2X (1 << 3)
74#define MT9M111_RM_ROW_SKIP_2X (1 << 2)
75#define MT9M111_RMB_MIRROR_COLS (1 << 1)
76#define MT9M111_RMB_MIRROR_ROWS (1 << 0)
77#define MT9M111_CTXT_CTRL_RESTART (1 << 15)
78#define MT9M111_CTXT_CTRL_DEFECTCOR_B (1 << 12)
79#define MT9M111_CTXT_CTRL_RESIZE_B (1 << 10)
80#define MT9M111_CTXT_CTRL_CTRL2_B (1 << 9)
81#define MT9M111_CTXT_CTRL_GAMMA_B (1 << 8)
82#define MT9M111_CTXT_CTRL_XENON_EN (1 << 7)
83#define MT9M111_CTXT_CTRL_READ_MODE_B (1 << 3)
84#define MT9M111_CTXT_CTRL_LED_FLASH_EN (1 << 2)
85#define MT9M111_CTXT_CTRL_VBLANK_SEL_B (1 << 1)
86#define MT9M111_CTXT_CTRL_HBLANK_SEL_B (1 << 0)
87
88/*
89 * Colorpipe register addresses (0x100..0x1ff)
90 */
91#define MT9M111_OPER_MODE_CTRL 0x106
92#define MT9M111_OUTPUT_FORMAT_CTRL 0x108
93#define MT9M111_REDUCER_XZOOM_B 0x1a0
94#define MT9M111_REDUCER_XSIZE_B 0x1a1
95#define MT9M111_REDUCER_YZOOM_B 0x1a3
96#define MT9M111_REDUCER_YSIZE_B 0x1a4
97#define MT9M111_REDUCER_XZOOM_A 0x1a6
98#define MT9M111_REDUCER_XSIZE_A 0x1a7
99#define MT9M111_REDUCER_YZOOM_A 0x1a9
100#define MT9M111_REDUCER_YSIZE_A 0x1aa
101
102#define MT9M111_OUTPUT_FORMAT_CTRL2_A 0x13a
103#define MT9M111_OUTPUT_FORMAT_CTRL2_B 0x19b
104
105#define MT9M111_OPMODE_AUTOEXPO_EN (1 << 14)
106#define MT9M111_OPMODE_AUTOWHITEBAL_EN (1 << 1)
107#define MT9M111_OUTFMT_FLIP_BAYER_COL (1 << 9)
108#define MT9M111_OUTFMT_FLIP_BAYER_ROW (1 << 8)
109#define MT9M111_OUTFMT_PROCESSED_BAYER (1 << 14)
110#define MT9M111_OUTFMT_BYPASS_IFP (1 << 10)
111#define MT9M111_OUTFMT_INV_PIX_CLOCK (1 << 9)
112#define MT9M111_OUTFMT_RGB (1 << 8)
113#define MT9M111_OUTFMT_RGB565 (0 << 6)
114#define MT9M111_OUTFMT_RGB555 (1 << 6)
115#define MT9M111_OUTFMT_RGB444x (2 << 6)
116#define MT9M111_OUTFMT_RGBx444 (3 << 6)
117#define MT9M111_OUTFMT_TST_RAMP_OFF (0 << 4)
118#define MT9M111_OUTFMT_TST_RAMP_COL (1 << 4)
119#define MT9M111_OUTFMT_TST_RAMP_ROW (2 << 4)
120#define MT9M111_OUTFMT_TST_RAMP_FRAME (3 << 4)
121#define MT9M111_OUTFMT_SHIFT_3_UP (1 << 3)
122#define MT9M111_OUTFMT_AVG_CHROMA (1 << 2)
123#define MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN (1 << 1)
124#define MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B (1 << 0)
125
126/*
127 * Camera control register addresses (0x200..0x2ff not implemented)
128 */
129
130#define reg_read(reg) mt9m111_reg_read(client, MT9M111_##reg)
131#define reg_write(reg, val) mt9m111_reg_write(client, MT9M111_##reg, (val))
132#define reg_set(reg, val) mt9m111_reg_set(client, MT9M111_##reg, (val))
133#define reg_clear(reg, val) mt9m111_reg_clear(client, MT9M111_##reg, (val))
134#define reg_mask(reg, val, mask) mt9m111_reg_mask(client, MT9M111_##reg, \
135 (val), (mask))
136
137#define MT9M111_MIN_DARK_ROWS 8
138#define MT9M111_MIN_DARK_COLS 26
139#define MT9M111_MAX_HEIGHT 1024
140#define MT9M111_MAX_WIDTH 1280
141
142struct mt9m111_context {
143 u16 read_mode;
144 u16 blanking_h;
145 u16 blanking_v;
146 u16 reducer_xzoom;
147 u16 reducer_yzoom;
148 u16 reducer_xsize;
149 u16 reducer_ysize;
150 u16 output_fmt_ctrl2;
151 u16 control;
152};
153
154static struct mt9m111_context context_a = {
155 .read_mode = MT9M111_READ_MODE_A,
156 .blanking_h = MT9M111_HORIZONTAL_BLANKING_A,
157 .blanking_v = MT9M111_VERTICAL_BLANKING_A,
158 .reducer_xzoom = MT9M111_REDUCER_XZOOM_A,
159 .reducer_yzoom = MT9M111_REDUCER_YZOOM_A,
160 .reducer_xsize = MT9M111_REDUCER_XSIZE_A,
161 .reducer_ysize = MT9M111_REDUCER_YSIZE_A,
162 .output_fmt_ctrl2 = MT9M111_OUTPUT_FORMAT_CTRL2_A,
163 .control = MT9M111_CTXT_CTRL_RESTART,
164};
165
166static struct mt9m111_context context_b = {
167 .read_mode = MT9M111_READ_MODE_B,
168 .blanking_h = MT9M111_HORIZONTAL_BLANKING_B,
169 .blanking_v = MT9M111_VERTICAL_BLANKING_B,
170 .reducer_xzoom = MT9M111_REDUCER_XZOOM_B,
171 .reducer_yzoom = MT9M111_REDUCER_YZOOM_B,
172 .reducer_xsize = MT9M111_REDUCER_XSIZE_B,
173 .reducer_ysize = MT9M111_REDUCER_YSIZE_B,
174 .output_fmt_ctrl2 = MT9M111_OUTPUT_FORMAT_CTRL2_B,
175 .control = MT9M111_CTXT_CTRL_RESTART |
176 MT9M111_CTXT_CTRL_DEFECTCOR_B | MT9M111_CTXT_CTRL_RESIZE_B |
177 MT9M111_CTXT_CTRL_CTRL2_B | MT9M111_CTXT_CTRL_GAMMA_B |
178 MT9M111_CTXT_CTRL_READ_MODE_B | MT9M111_CTXT_CTRL_VBLANK_SEL_B |
179 MT9M111_CTXT_CTRL_HBLANK_SEL_B,
180};
181
182/* MT9M111 has only one fixed colorspace per pixelcode */
183struct mt9m111_datafmt {
184 enum v4l2_mbus_pixelcode code;
185 enum v4l2_colorspace colorspace;
186};
187
188static const struct mt9m111_datafmt mt9m111_colour_fmts[] = {
189 {V4L2_MBUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_JPEG},
190 {V4L2_MBUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_JPEG},
191 {V4L2_MBUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_JPEG},
192 {V4L2_MBUS_FMT_VYUY8_2X8, V4L2_COLORSPACE_JPEG},
193 {V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB},
194 {V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE, V4L2_COLORSPACE_SRGB},
195 {V4L2_MBUS_FMT_RGB565_2X8_LE, V4L2_COLORSPACE_SRGB},
196 {V4L2_MBUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_SRGB},
197 {V4L2_MBUS_FMT_BGR565_2X8_LE, V4L2_COLORSPACE_SRGB},
198 {V4L2_MBUS_FMT_BGR565_2X8_BE, V4L2_COLORSPACE_SRGB},
199 {V4L2_MBUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB},
200 {V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB},
201};
202
203struct mt9m111 {
204 struct v4l2_subdev subdev;
205 struct v4l2_ctrl_handler hdl;
206 struct v4l2_ctrl *gain;
207 int model; /* V4L2_IDENT_MT9M111 or V4L2_IDENT_MT9M112 code
208 * from v4l2-chip-ident.h */
209 struct mt9m111_context *ctx;
210 struct v4l2_rect rect; /* cropping rectangle */
211 int width; /* output */
212 int height; /* sizes */
213 struct mutex power_lock; /* lock to protect power_count */
214 int power_count;
215 const struct mt9m111_datafmt *fmt;
216 int lastpage; /* PageMap cache value */
217};
218
219/* Find a data format by a pixel code */
220static const struct mt9m111_datafmt *mt9m111_find_datafmt(struct mt9m111 *mt9m111,
221 enum v4l2_mbus_pixelcode code)
222{
223 int i;
224 for (i = 0; i < ARRAY_SIZE(mt9m111_colour_fmts); i++)
225 if (mt9m111_colour_fmts[i].code == code)
226 return mt9m111_colour_fmts + i;
227
228 return mt9m111->fmt;
229}
230
231static struct mt9m111 *to_mt9m111(const struct i2c_client *client)
232{
233 return container_of(i2c_get_clientdata(client), struct mt9m111, subdev);
234}
235
236static int reg_page_map_set(struct i2c_client *client, const u16 reg)
237{
238 int ret;
239 u16 page;
240 struct mt9m111 *mt9m111 = to_mt9m111(client);
241
242 page = (reg >> 8);
243 if (page == mt9m111->lastpage)
244 return 0;
245 if (page > 2)
246 return -EINVAL;
247
248 ret = i2c_smbus_write_word_swapped(client, MT9M111_PAGE_MAP, page);
249 if (!ret)
250 mt9m111->lastpage = page;
251 return ret;
252}
253
254static int mt9m111_reg_read(struct i2c_client *client, const u16 reg)
255{
256 int ret;
257
258 ret = reg_page_map_set(client, reg);
259 if (!ret)
260 ret = i2c_smbus_read_word_swapped(client, reg & 0xff);
261
262 dev_dbg(&client->dev, "read reg.%03x -> %04x\n", reg, ret);
263 return ret;
264}
265
266static int mt9m111_reg_write(struct i2c_client *client, const u16 reg,
267 const u16 data)
268{
269 int ret;
270
271 ret = reg_page_map_set(client, reg);
272 if (!ret)
273 ret = i2c_smbus_write_word_swapped(client, reg & 0xff, data);
274 dev_dbg(&client->dev, "write reg.%03x = %04x -> %d\n", reg, data, ret);
275 return ret;
276}
277
278static int mt9m111_reg_set(struct i2c_client *client, const u16 reg,
279 const u16 data)
280{
281 int ret;
282
283 ret = mt9m111_reg_read(client, reg);
284 if (ret >= 0)
285 ret = mt9m111_reg_write(client, reg, ret | data);
286 return ret;
287}
288
289static int mt9m111_reg_clear(struct i2c_client *client, const u16 reg,
290 const u16 data)
291{
292 int ret;
293
294 ret = mt9m111_reg_read(client, reg);
295 if (ret >= 0)
296 ret = mt9m111_reg_write(client, reg, ret & ~data);
297 return ret;
298}
299
300static int mt9m111_reg_mask(struct i2c_client *client, const u16 reg,
301 const u16 data, const u16 mask)
302{
303 int ret;
304
305 ret = mt9m111_reg_read(client, reg);
306 if (ret >= 0)
307 ret = mt9m111_reg_write(client, reg, (ret & ~mask) | data);
308 return ret;
309}
310
311static int mt9m111_set_context(struct mt9m111 *mt9m111,
312 struct mt9m111_context *ctx)
313{
314 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
315 return reg_write(CONTEXT_CONTROL, ctx->control);
316}
317
318static int mt9m111_setup_rect_ctx(struct mt9m111 *mt9m111,
319 struct mt9m111_context *ctx, struct v4l2_rect *rect,
320 unsigned int width, unsigned int height)
321{
322 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
323 int ret = mt9m111_reg_write(client, ctx->reducer_xzoom, rect->width);
324 if (!ret)
325 ret = mt9m111_reg_write(client, ctx->reducer_yzoom, rect->height);
326 if (!ret)
327 ret = mt9m111_reg_write(client, ctx->reducer_xsize, width);
328 if (!ret)
329 ret = mt9m111_reg_write(client, ctx->reducer_ysize, height);
330 return ret;
331}
332
333static int mt9m111_setup_geometry(struct mt9m111 *mt9m111, struct v4l2_rect *rect,
334 int width, int height, enum v4l2_mbus_pixelcode code)
335{
336 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
337 int ret;
338
339 ret = reg_write(COLUMN_START, rect->left);
340 if (!ret)
341 ret = reg_write(ROW_START, rect->top);
342
343 if (!ret)
344 ret = reg_write(WINDOW_WIDTH, rect->width);
345 if (!ret)
346 ret = reg_write(WINDOW_HEIGHT, rect->height);
347
348 if (code != V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE) {
349 /* IFP in use, down-scaling possible */
350 if (!ret)
351 ret = mt9m111_setup_rect_ctx(mt9m111, &context_b,
352 rect, width, height);
353 if (!ret)
354 ret = mt9m111_setup_rect_ctx(mt9m111, &context_a,
355 rect, width, height);
356 }
357
358 dev_dbg(&client->dev, "%s(%x): %ux%u@%u:%u -> %ux%u = %d\n",
359 __func__, code, rect->width, rect->height, rect->left, rect->top,
360 width, height, ret);
361
362 return ret;
363}
364
365static int mt9m111_enable(struct mt9m111 *mt9m111)
366{
367 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
368 return reg_write(RESET, MT9M111_RESET_CHIP_ENABLE);
369}
370
371static int mt9m111_reset(struct mt9m111 *mt9m111)
372{
373 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
374 int ret;
375
376 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE);
377 if (!ret)
378 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC);
379 if (!ret)
380 ret = reg_clear(RESET, MT9M111_RESET_RESET_MODE
381 | MT9M111_RESET_RESET_SOC);
382
383 return ret;
384}
385
386static int mt9m111_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
387{
388 struct v4l2_rect rect = a->c;
389 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
390 int width, height;
391 int ret;
392
393 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
394 return -EINVAL;
395
396 if (mt9m111->fmt->code == V4L2_MBUS_FMT_SBGGR8_1X8 ||
397 mt9m111->fmt->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE) {
398 /* Bayer format - even size lengths */
399 rect.width = ALIGN(rect.width, 2);
400 rect.height = ALIGN(rect.height, 2);
401 /* Let the user play with the starting pixel */
402 }
403
404 /* FIXME: the datasheet doesn't specify minimum sizes */
405 soc_camera_limit_side(&rect.left, &rect.width,
406 MT9M111_MIN_DARK_COLS, 2, MT9M111_MAX_WIDTH);
407
408 soc_camera_limit_side(&rect.top, &rect.height,
409 MT9M111_MIN_DARK_ROWS, 2, MT9M111_MAX_HEIGHT);
410
411 width = min(mt9m111->width, rect.width);
412 height = min(mt9m111->height, rect.height);
413
414 ret = mt9m111_setup_geometry(mt9m111, &rect, width, height, mt9m111->fmt->code);
415 if (!ret) {
416 mt9m111->rect = rect;
417 mt9m111->width = width;
418 mt9m111->height = height;
419 }
420
421 return ret;
422}
423
424static int mt9m111_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
425{
426 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
427
428 a->c = mt9m111->rect;
429 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
430
431 return 0;
432}
433
434static int mt9m111_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
435{
436 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
437 return -EINVAL;
438
439 a->bounds.left = MT9M111_MIN_DARK_COLS;
440 a->bounds.top = MT9M111_MIN_DARK_ROWS;
441 a->bounds.width = MT9M111_MAX_WIDTH;
442 a->bounds.height = MT9M111_MAX_HEIGHT;
443 a->defrect = a->bounds;
444 a->pixelaspect.numerator = 1;
445 a->pixelaspect.denominator = 1;
446
447 return 0;
448}
449
450static int mt9m111_g_fmt(struct v4l2_subdev *sd,
451 struct v4l2_mbus_framefmt *mf)
452{
453 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
454
455 mf->width = mt9m111->width;
456 mf->height = mt9m111->height;
457 mf->code = mt9m111->fmt->code;
458 mf->colorspace = mt9m111->fmt->colorspace;
459 mf->field = V4L2_FIELD_NONE;
460
461 return 0;
462}
463
464static int mt9m111_set_pixfmt(struct mt9m111 *mt9m111,
465 enum v4l2_mbus_pixelcode code)
466{
467 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
468 u16 data_outfmt2, mask_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER |
469 MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB |
470 MT9M111_OUTFMT_RGB565 | MT9M111_OUTFMT_RGB555 |
471 MT9M111_OUTFMT_RGB444x | MT9M111_OUTFMT_RGBx444 |
472 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
473 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
474 int ret;
475
476 switch (code) {
477 case V4L2_MBUS_FMT_SBGGR8_1X8:
478 data_outfmt2 = MT9M111_OUTFMT_PROCESSED_BAYER |
479 MT9M111_OUTFMT_RGB;
480 break;
481 case V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE:
482 data_outfmt2 = MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_RGB;
483 break;
484 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
485 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555 |
486 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
487 break;
488 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE:
489 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB555;
490 break;
491 case V4L2_MBUS_FMT_RGB565_2X8_LE:
492 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
493 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
494 break;
495 case V4L2_MBUS_FMT_RGB565_2X8_BE:
496 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565;
497 break;
498 case V4L2_MBUS_FMT_BGR565_2X8_BE:
499 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
500 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
501 break;
502 case V4L2_MBUS_FMT_BGR565_2X8_LE:
503 data_outfmt2 = MT9M111_OUTFMT_RGB | MT9M111_OUTFMT_RGB565 |
504 MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
505 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
506 break;
507 case V4L2_MBUS_FMT_UYVY8_2X8:
508 data_outfmt2 = 0;
509 break;
510 case V4L2_MBUS_FMT_VYUY8_2X8:
511 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
512 break;
513 case V4L2_MBUS_FMT_YUYV8_2X8:
514 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN;
515 break;
516 case V4L2_MBUS_FMT_YVYU8_2X8:
517 data_outfmt2 = MT9M111_OUTFMT_SWAP_YCbCr_C_Y_RGB_EVEN |
518 MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr_RGB_R_B;
519 break;
520 default:
521 dev_err(&client->dev, "Pixel format not handled: %x\n", code);
522 return -EINVAL;
523 }
524
525 ret = mt9m111_reg_mask(client, context_a.output_fmt_ctrl2,
526 data_outfmt2, mask_outfmt2);
527 if (!ret)
528 ret = mt9m111_reg_mask(client, context_b.output_fmt_ctrl2,
529 data_outfmt2, mask_outfmt2);
530
531 return ret;
532}
533
534static int mt9m111_try_fmt(struct v4l2_subdev *sd,
535 struct v4l2_mbus_framefmt *mf)
536{
537 struct i2c_client *client = v4l2_get_subdevdata(sd);
538 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
539 const struct mt9m111_datafmt *fmt;
540 struct v4l2_rect *rect = &mt9m111->rect;
541 bool bayer;
542
543 fmt = mt9m111_find_datafmt(mt9m111, mf->code);
544
545 bayer = fmt->code == V4L2_MBUS_FMT_SBGGR8_1X8 ||
546 fmt->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE;
547
548 /*
549 * With Bayer format enforce even side lengths, but let the user play
550 * with the starting pixel
551 */
552 if (bayer) {
553 rect->width = ALIGN(rect->width, 2);
554 rect->height = ALIGN(rect->height, 2);
555 }
556
557 if (fmt->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE) {
558 /* IFP bypass mode, no scaling */
559 mf->width = rect->width;
560 mf->height = rect->height;
561 } else {
562 /* No upscaling */
563 if (mf->width > rect->width)
564 mf->width = rect->width;
565 if (mf->height > rect->height)
566 mf->height = rect->height;
567 }
568
569 dev_dbg(&client->dev, "%s(): %ux%u, code=%x\n", __func__,
570 mf->width, mf->height, fmt->code);
571
572 mf->code = fmt->code;
573 mf->colorspace = fmt->colorspace;
574
575 return 0;
576}
577
578static int mt9m111_s_fmt(struct v4l2_subdev *sd,
579 struct v4l2_mbus_framefmt *mf)
580{
581 const struct mt9m111_datafmt *fmt;
582 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
583 struct v4l2_rect *rect = &mt9m111->rect;
584 int ret;
585
586 mt9m111_try_fmt(sd, mf);
587 fmt = mt9m111_find_datafmt(mt9m111, mf->code);
588 /* try_fmt() guarantees fmt != NULL && fmt->code == mf->code */
589
590 ret = mt9m111_setup_geometry(mt9m111, rect, mf->width, mf->height, mf->code);
591 if (!ret)
592 ret = mt9m111_set_pixfmt(mt9m111, mf->code);
593 if (!ret) {
594 mt9m111->width = mf->width;
595 mt9m111->height = mf->height;
596 mt9m111->fmt = fmt;
597 }
598
599 return ret;
600}
601
602static int mt9m111_g_chip_ident(struct v4l2_subdev *sd,
603 struct v4l2_dbg_chip_ident *id)
604{
605 struct i2c_client *client = v4l2_get_subdevdata(sd);
606 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
607
608 if (id->match.type != V4L2_CHIP_MATCH_I2C_ADDR)
609 return -EINVAL;
610
611 if (id->match.addr != client->addr)
612 return -ENODEV;
613
614 id->ident = mt9m111->model;
615 id->revision = 0;
616
617 return 0;
618}
619
620#ifdef CONFIG_VIDEO_ADV_DEBUG
621static int mt9m111_g_register(struct v4l2_subdev *sd,
622 struct v4l2_dbg_register *reg)
623{
624 struct i2c_client *client = v4l2_get_subdevdata(sd);
625 int val;
626
627 if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0x2ff)
628 return -EINVAL;
629 if (reg->match.addr != client->addr)
630 return -ENODEV;
631
632 val = mt9m111_reg_read(client, reg->reg);
633 reg->size = 2;
634 reg->val = (u64)val;
635
636 if (reg->val > 0xffff)
637 return -EIO;
638
639 return 0;
640}
641
642static int mt9m111_s_register(struct v4l2_subdev *sd,
643 struct v4l2_dbg_register *reg)
644{
645 struct i2c_client *client = v4l2_get_subdevdata(sd);
646
647 if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0x2ff)
648 return -EINVAL;
649
650 if (reg->match.addr != client->addr)
651 return -ENODEV;
652
653 if (mt9m111_reg_write(client, reg->reg, reg->val) < 0)
654 return -EIO;
655
656 return 0;
657}
658#endif
659
660static int mt9m111_set_flip(struct mt9m111 *mt9m111, int flip, int mask)
661{
662 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
663 int ret;
664
665 if (flip)
666 ret = mt9m111_reg_set(client, mt9m111->ctx->read_mode, mask);
667 else
668 ret = mt9m111_reg_clear(client, mt9m111->ctx->read_mode, mask);
669
670 return ret;
671}
672
673static int mt9m111_get_global_gain(struct mt9m111 *mt9m111)
674{
675 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
676 int data;
677
678 data = reg_read(GLOBAL_GAIN);
679 if (data >= 0)
680 return (data & 0x2f) * (1 << ((data >> 10) & 1)) *
681 (1 << ((data >> 9) & 1));
682 return data;
683}
684
685static int mt9m111_set_global_gain(struct mt9m111 *mt9m111, int gain)
686{
687 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
688 u16 val;
689
690 if (gain > 63 * 2 * 2)
691 return -EINVAL;
692
693 if ((gain >= 64 * 2) && (gain < 63 * 2 * 2))
694 val = (1 << 10) | (1 << 9) | (gain / 4);
695 else if ((gain >= 64) && (gain < 64 * 2))
696 val = (1 << 9) | (gain / 2);
697 else
698 val = gain;
699
700 return reg_write(GLOBAL_GAIN, val);
701}
702
703static int mt9m111_set_autoexposure(struct mt9m111 *mt9m111, int on)
704{
705 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
706
707 if (on)
708 return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN);
709 return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOEXPO_EN);
710}
711
712static int mt9m111_set_autowhitebalance(struct mt9m111 *mt9m111, int on)
713{
714 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
715
716 if (on)
717 return reg_set(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN);
718 return reg_clear(OPER_MODE_CTRL, MT9M111_OPMODE_AUTOWHITEBAL_EN);
719}
720
721static int mt9m111_s_ctrl(struct v4l2_ctrl *ctrl)
722{
723 struct mt9m111 *mt9m111 = container_of(ctrl->handler,
724 struct mt9m111, hdl);
725
726 switch (ctrl->id) {
727 case V4L2_CID_VFLIP:
728 return mt9m111_set_flip(mt9m111, ctrl->val,
729 MT9M111_RMB_MIRROR_ROWS);
730 case V4L2_CID_HFLIP:
731 return mt9m111_set_flip(mt9m111, ctrl->val,
732 MT9M111_RMB_MIRROR_COLS);
733 case V4L2_CID_GAIN:
734 return mt9m111_set_global_gain(mt9m111, ctrl->val);
735 case V4L2_CID_EXPOSURE_AUTO:
736 return mt9m111_set_autoexposure(mt9m111, ctrl->val);
737 case V4L2_CID_AUTO_WHITE_BALANCE:
738 return mt9m111_set_autowhitebalance(mt9m111, ctrl->val);
739 }
740
741 return -EINVAL;
742}
743
744static int mt9m111_suspend(struct mt9m111 *mt9m111)
745{
746 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
747 int ret;
748
749 v4l2_ctrl_s_ctrl(mt9m111->gain, mt9m111_get_global_gain(mt9m111));
750
751 ret = reg_set(RESET, MT9M111_RESET_RESET_MODE);
752 if (!ret)
753 ret = reg_set(RESET, MT9M111_RESET_RESET_SOC |
754 MT9M111_RESET_OUTPUT_DISABLE |
755 MT9M111_RESET_ANALOG_STANDBY);
756 if (!ret)
757 ret = reg_clear(RESET, MT9M111_RESET_CHIP_ENABLE);
758
759 return ret;
760}
761
762static void mt9m111_restore_state(struct mt9m111 *mt9m111)
763{
764 mt9m111_set_context(mt9m111, mt9m111->ctx);
765 mt9m111_set_pixfmt(mt9m111, mt9m111->fmt->code);
766 mt9m111_setup_geometry(mt9m111, &mt9m111->rect,
767 mt9m111->width, mt9m111->height, mt9m111->fmt->code);
768 v4l2_ctrl_handler_setup(&mt9m111->hdl);
769}
770
771static int mt9m111_resume(struct mt9m111 *mt9m111)
772{
773 int ret = mt9m111_enable(mt9m111);
774 if (!ret)
775 ret = mt9m111_reset(mt9m111);
776 if (!ret)
777 mt9m111_restore_state(mt9m111);
778
779 return ret;
780}
781
782static int mt9m111_init(struct mt9m111 *mt9m111)
783{
784 struct i2c_client *client = v4l2_get_subdevdata(&mt9m111->subdev);
785 int ret;
786
787 /* Default HIGHPOWER context */
788 mt9m111->ctx = &context_b;
789 ret = mt9m111_enable(mt9m111);
790 if (!ret)
791 ret = mt9m111_reset(mt9m111);
792 if (!ret)
793 ret = mt9m111_set_context(mt9m111, mt9m111->ctx);
794 if (ret)
795 dev_err(&client->dev, "mt9m111 init failed: %d\n", ret);
796 return ret;
797}
798
799/*
800 * Interface active, can use i2c. If it fails, it can indeed mean, that
801 * this wasn't our capture interface, so, we wait for the right one
802 */
803static int mt9m111_video_probe(struct i2c_client *client)
804{
805 struct mt9m111 *mt9m111 = to_mt9m111(client);
806 s32 data;
807 int ret;
808
809 data = reg_read(CHIP_VERSION);
810
811 switch (data) {
812 case 0x143a: /* MT9M111 or MT9M131 */
813 mt9m111->model = V4L2_IDENT_MT9M111;
814 dev_info(&client->dev,
815 "Detected a MT9M111/MT9M131 chip ID %x\n", data);
816 break;
817 case 0x148c: /* MT9M112 */
818 mt9m111->model = V4L2_IDENT_MT9M112;
819 dev_info(&client->dev, "Detected a MT9M112 chip ID %x\n", data);
820 break;
821 default:
822 dev_err(&client->dev,
823 "No MT9M111/MT9M112/MT9M131 chip detected register read %x\n",
824 data);
825 return -ENODEV;
826 }
827
828 ret = mt9m111_init(mt9m111);
829 if (ret)
830 return ret;
831 return v4l2_ctrl_handler_setup(&mt9m111->hdl);
832}
833
834static int mt9m111_s_power(struct v4l2_subdev *sd, int on)
835{
836 struct mt9m111 *mt9m111 = container_of(sd, struct mt9m111, subdev);
837 struct i2c_client *client = v4l2_get_subdevdata(sd);
838 int ret = 0;
839
840 mutex_lock(&mt9m111->power_lock);
841
842 /*
843 * If the power count is modified from 0 to != 0 or from != 0 to 0,
844 * update the power state.
845 */
846 if (mt9m111->power_count == !on) {
847 if (on) {
848 ret = mt9m111_resume(mt9m111);
849 if (ret) {
850 dev_err(&client->dev,
851 "Failed to resume the sensor: %d\n", ret);
852 goto out;
853 }
854 } else {
855 mt9m111_suspend(mt9m111);
856 }
857 }
858
859 /* Update the power count. */
860 mt9m111->power_count += on ? 1 : -1;
861 WARN_ON(mt9m111->power_count < 0);
862
863out:
864 mutex_unlock(&mt9m111->power_lock);
865 return ret;
866}
867
868static const struct v4l2_ctrl_ops mt9m111_ctrl_ops = {
869 .s_ctrl = mt9m111_s_ctrl,
870};
871
872static struct v4l2_subdev_core_ops mt9m111_subdev_core_ops = {
873 .g_chip_ident = mt9m111_g_chip_ident,
874 .s_power = mt9m111_s_power,
875#ifdef CONFIG_VIDEO_ADV_DEBUG
876 .g_register = mt9m111_g_register,
877 .s_register = mt9m111_s_register,
878#endif
879};
880
881static int mt9m111_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
882 enum v4l2_mbus_pixelcode *code)
883{
884 if (index >= ARRAY_SIZE(mt9m111_colour_fmts))
885 return -EINVAL;
886
887 *code = mt9m111_colour_fmts[index].code;
888 return 0;
889}
890
891static int mt9m111_g_mbus_config(struct v4l2_subdev *sd,
892 struct v4l2_mbus_config *cfg)
893{
894 struct i2c_client *client = v4l2_get_subdevdata(sd);
895 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
896
897 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |
898 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_HIGH |
899 V4L2_MBUS_DATA_ACTIVE_HIGH;
900 cfg->type = V4L2_MBUS_PARALLEL;
901 cfg->flags = soc_camera_apply_board_flags(icl, cfg);
902
903 return 0;
904}
905
906static struct v4l2_subdev_video_ops mt9m111_subdev_video_ops = {
907 .s_mbus_fmt = mt9m111_s_fmt,
908 .g_mbus_fmt = mt9m111_g_fmt,
909 .try_mbus_fmt = mt9m111_try_fmt,
910 .s_crop = mt9m111_s_crop,
911 .g_crop = mt9m111_g_crop,
912 .cropcap = mt9m111_cropcap,
913 .enum_mbus_fmt = mt9m111_enum_fmt,
914 .g_mbus_config = mt9m111_g_mbus_config,
915};
916
917static struct v4l2_subdev_ops mt9m111_subdev_ops = {
918 .core = &mt9m111_subdev_core_ops,
919 .video = &mt9m111_subdev_video_ops,
920};
921
922static int mt9m111_probe(struct i2c_client *client,
923 const struct i2c_device_id *did)
924{
925 struct mt9m111 *mt9m111;
926 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
927 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
928 int ret;
929
930 if (!icl) {
931 dev_err(&client->dev, "mt9m111: driver needs platform data\n");
932 return -EINVAL;
933 }
934
935 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) {
936 dev_warn(&adapter->dev,
937 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
938 return -EIO;
939 }
940
941 mt9m111 = kzalloc(sizeof(struct mt9m111), GFP_KERNEL);
942 if (!mt9m111)
943 return -ENOMEM;
944
945 v4l2_i2c_subdev_init(&mt9m111->subdev, client, &mt9m111_subdev_ops);
946 v4l2_ctrl_handler_init(&mt9m111->hdl, 5);
947 v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
948 V4L2_CID_VFLIP, 0, 1, 1, 0);
949 v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
950 V4L2_CID_HFLIP, 0, 1, 1, 0);
951 v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
952 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
953 mt9m111->gain = v4l2_ctrl_new_std(&mt9m111->hdl, &mt9m111_ctrl_ops,
954 V4L2_CID_GAIN, 0, 63 * 2 * 2, 1, 32);
955 v4l2_ctrl_new_std_menu(&mt9m111->hdl,
956 &mt9m111_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, 1, 0,
957 V4L2_EXPOSURE_AUTO);
958 mt9m111->subdev.ctrl_handler = &mt9m111->hdl;
959 if (mt9m111->hdl.error) {
960 int err = mt9m111->hdl.error;
961
962 kfree(mt9m111);
963 return err;
964 }
965
966 /* Second stage probe - when a capture adapter is there */
967 mt9m111->rect.left = MT9M111_MIN_DARK_COLS;
968 mt9m111->rect.top = MT9M111_MIN_DARK_ROWS;
969 mt9m111->rect.width = MT9M111_MAX_WIDTH;
970 mt9m111->rect.height = MT9M111_MAX_HEIGHT;
971 mt9m111->fmt = &mt9m111_colour_fmts[0];
972 mt9m111->lastpage = -1;
973 mutex_init(&mt9m111->power_lock);
974
975 ret = mt9m111_video_probe(client);
976 if (ret) {
977 v4l2_ctrl_handler_free(&mt9m111->hdl);
978 kfree(mt9m111);
979 }
980
981 return ret;
982}
983
984static int mt9m111_remove(struct i2c_client *client)
985{
986 struct mt9m111 *mt9m111 = to_mt9m111(client);
987
988 v4l2_device_unregister_subdev(&mt9m111->subdev);
989 v4l2_ctrl_handler_free(&mt9m111->hdl);
990 kfree(mt9m111);
991
992 return 0;
993}
994
995static const struct i2c_device_id mt9m111_id[] = {
996 { "mt9m111", 0 },
997 { }
998};
999MODULE_DEVICE_TABLE(i2c, mt9m111_id);
1000
1001static struct i2c_driver mt9m111_i2c_driver = {
1002 .driver = {
1003 .name = "mt9m111",
1004 },
1005 .probe = mt9m111_probe,
1006 .remove = mt9m111_remove,
1007 .id_table = mt9m111_id,
1008};
1009
1010module_i2c_driver(mt9m111_i2c_driver);
1011
1012MODULE_DESCRIPTION("Micron/Aptina MT9M111/MT9M112/MT9M131 Camera driver");
1013MODULE_AUTHOR("Robert Jarzmik");
1014MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/mt9t031.c b/drivers/media/video/mt9t031.c
deleted file mode 100644
index 1415074138a5..000000000000
--- a/drivers/media/video/mt9t031.c
+++ /dev/null
@@ -1,857 +0,0 @@
1/*
2 * Driver for MT9T031 CMOS Image Sensor from Micron
3 *
4 * Copyright (C) 2008, Guennadi Liakhovetski, DENX Software Engineering <lg@denx.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/device.h>
12#include <linux/i2c.h>
13#include <linux/log2.h>
14#include <linux/pm.h>
15#include <linux/slab.h>
16#include <linux/v4l2-mediabus.h>
17#include <linux/videodev2.h>
18#include <linux/module.h>
19
20#include <media/soc_camera.h>
21#include <media/v4l2-chip-ident.h>
22#include <media/v4l2-subdev.h>
23#include <media/v4l2-ctrls.h>
24
25/*
26 * ATTENTION: this driver still cannot be used outside of the soc-camera
27 * framework because of its PM implementation, using the video_device node.
28 * If hardware becomes available for testing, alternative PM approaches shall
29 * be considered and tested.
30 */
31
32/*
33 * mt9t031 i2c address 0x5d
34 * The platform has to define i2c_board_info and link to it from
35 * struct soc_camera_link
36 */
37
38/* mt9t031 selected register addresses */
39#define MT9T031_CHIP_VERSION 0x00
40#define MT9T031_ROW_START 0x01
41#define MT9T031_COLUMN_START 0x02
42#define MT9T031_WINDOW_HEIGHT 0x03
43#define MT9T031_WINDOW_WIDTH 0x04
44#define MT9T031_HORIZONTAL_BLANKING 0x05
45#define MT9T031_VERTICAL_BLANKING 0x06
46#define MT9T031_OUTPUT_CONTROL 0x07
47#define MT9T031_SHUTTER_WIDTH_UPPER 0x08
48#define MT9T031_SHUTTER_WIDTH 0x09
49#define MT9T031_PIXEL_CLOCK_CONTROL 0x0a
50#define MT9T031_FRAME_RESTART 0x0b
51#define MT9T031_SHUTTER_DELAY 0x0c
52#define MT9T031_RESET 0x0d
53#define MT9T031_READ_MODE_1 0x1e
54#define MT9T031_READ_MODE_2 0x20
55#define MT9T031_READ_MODE_3 0x21
56#define MT9T031_ROW_ADDRESS_MODE 0x22
57#define MT9T031_COLUMN_ADDRESS_MODE 0x23
58#define MT9T031_GLOBAL_GAIN 0x35
59#define MT9T031_CHIP_ENABLE 0xF8
60
61#define MT9T031_MAX_HEIGHT 1536
62#define MT9T031_MAX_WIDTH 2048
63#define MT9T031_MIN_HEIGHT 2
64#define MT9T031_MIN_WIDTH 18
65#define MT9T031_HORIZONTAL_BLANK 142
66#define MT9T031_VERTICAL_BLANK 25
67#define MT9T031_COLUMN_SKIP 32
68#define MT9T031_ROW_SKIP 20
69
70struct mt9t031 {
71 struct v4l2_subdev subdev;
72 struct v4l2_ctrl_handler hdl;
73 struct {
74 /* exposure/auto-exposure cluster */
75 struct v4l2_ctrl *autoexposure;
76 struct v4l2_ctrl *exposure;
77 };
78 struct v4l2_rect rect; /* Sensor window */
79 int model; /* V4L2_IDENT_MT9T031* codes from v4l2-chip-ident.h */
80 u16 xskip;
81 u16 yskip;
82 unsigned int total_h;
83 unsigned short y_skip_top; /* Lines to skip at the top */
84};
85
86static struct mt9t031 *to_mt9t031(const struct i2c_client *client)
87{
88 return container_of(i2c_get_clientdata(client), struct mt9t031, subdev);
89}
90
91static int reg_read(struct i2c_client *client, const u8 reg)
92{
93 return i2c_smbus_read_word_swapped(client, reg);
94}
95
96static int reg_write(struct i2c_client *client, const u8 reg,
97 const u16 data)
98{
99 return i2c_smbus_write_word_swapped(client, reg, data);
100}
101
102static int reg_set(struct i2c_client *client, const u8 reg,
103 const u16 data)
104{
105 int ret;
106
107 ret = reg_read(client, reg);
108 if (ret < 0)
109 return ret;
110 return reg_write(client, reg, ret | data);
111}
112
113static int reg_clear(struct i2c_client *client, const u8 reg,
114 const u16 data)
115{
116 int ret;
117
118 ret = reg_read(client, reg);
119 if (ret < 0)
120 return ret;
121 return reg_write(client, reg, ret & ~data);
122}
123
124static int set_shutter(struct i2c_client *client, const u32 data)
125{
126 int ret;
127
128 ret = reg_write(client, MT9T031_SHUTTER_WIDTH_UPPER, data >> 16);
129
130 if (ret >= 0)
131 ret = reg_write(client, MT9T031_SHUTTER_WIDTH, data & 0xffff);
132
133 return ret;
134}
135
136static int get_shutter(struct i2c_client *client, u32 *data)
137{
138 int ret;
139
140 ret = reg_read(client, MT9T031_SHUTTER_WIDTH_UPPER);
141 *data = ret << 16;
142
143 if (ret >= 0)
144 ret = reg_read(client, MT9T031_SHUTTER_WIDTH);
145 *data |= ret & 0xffff;
146
147 return ret < 0 ? ret : 0;
148}
149
150static int mt9t031_idle(struct i2c_client *client)
151{
152 int ret;
153
154 /* Disable chip output, synchronous option update */
155 ret = reg_write(client, MT9T031_RESET, 1);
156 if (ret >= 0)
157 ret = reg_write(client, MT9T031_RESET, 0);
158 if (ret >= 0)
159 ret = reg_clear(client, MT9T031_OUTPUT_CONTROL, 2);
160
161 return ret >= 0 ? 0 : -EIO;
162}
163
164static int mt9t031_disable(struct i2c_client *client)
165{
166 /* Disable the chip */
167 reg_clear(client, MT9T031_OUTPUT_CONTROL, 2);
168
169 return 0;
170}
171
172static int mt9t031_s_stream(struct v4l2_subdev *sd, int enable)
173{
174 struct i2c_client *client = v4l2_get_subdevdata(sd);
175 int ret;
176
177 if (enable)
178 /* Switch to master "normal" mode */
179 ret = reg_set(client, MT9T031_OUTPUT_CONTROL, 2);
180 else
181 /* Stop sensor readout */
182 ret = reg_clear(client, MT9T031_OUTPUT_CONTROL, 2);
183
184 if (ret < 0)
185 return -EIO;
186
187 return 0;
188}
189
190/* target must be _even_ */
191static u16 mt9t031_skip(s32 *source, s32 target, s32 max)
192{
193 unsigned int skip;
194
195 if (*source < target + target / 2) {
196 *source = target;
197 return 1;
198 }
199
200 skip = min(max, *source + target / 2) / target;
201 if (skip > 8)
202 skip = 8;
203 *source = target * skip;
204
205 return skip;
206}
207
208/* rect is the sensor rectangle, the caller guarantees parameter validity */
209static int mt9t031_set_params(struct i2c_client *client,
210 struct v4l2_rect *rect, u16 xskip, u16 yskip)
211{
212 struct mt9t031 *mt9t031 = to_mt9t031(client);
213 int ret;
214 u16 xbin, ybin;
215 const u16 hblank = MT9T031_HORIZONTAL_BLANK,
216 vblank = MT9T031_VERTICAL_BLANK;
217
218 xbin = min(xskip, (u16)3);
219 ybin = min(yskip, (u16)3);
220
221 /*
222 * Could just do roundup(rect->left, [xy]bin * 2); but this is cheaper.
223 * There is always a valid suitably aligned value. The worst case is
224 * xbin = 3, width = 2048. Then we will start at 36, the last read out
225 * pixel will be 2083, which is < 2085 - first black pixel.
226 *
227 * MT9T031 datasheet imposes window left border alignment, depending on
228 * the selected xskip. Failing to conform to this requirement produces
229 * dark horizontal stripes in the image. However, even obeying to this
230 * requirement doesn't eliminate the stripes in all configurations. They
231 * appear "locally reproducibly," but can differ between tests under
232 * different lighting conditions.
233 */
234 switch (xbin) {
235 case 1:
236 rect->left &= ~1;
237 break;
238 case 2:
239 rect->left &= ~3;
240 break;
241 case 3:
242 rect->left = rect->left > roundup(MT9T031_COLUMN_SKIP, 6) ?
243 (rect->left / 6) * 6 : roundup(MT9T031_COLUMN_SKIP, 6);
244 }
245
246 rect->top &= ~1;
247
248 dev_dbg(&client->dev, "skip %u:%u, rect %ux%u@%u:%u\n",
249 xskip, yskip, rect->width, rect->height, rect->left, rect->top);
250
251 /* Disable register update, reconfigure atomically */
252 ret = reg_set(client, MT9T031_OUTPUT_CONTROL, 1);
253 if (ret < 0)
254 return ret;
255
256 /* Blanking and start values - default... */
257 ret = reg_write(client, MT9T031_HORIZONTAL_BLANKING, hblank);
258 if (ret >= 0)
259 ret = reg_write(client, MT9T031_VERTICAL_BLANKING, vblank);
260
261 if (yskip != mt9t031->yskip || xskip != mt9t031->xskip) {
262 /* Binning, skipping */
263 if (ret >= 0)
264 ret = reg_write(client, MT9T031_COLUMN_ADDRESS_MODE,
265 ((xbin - 1) << 4) | (xskip - 1));
266 if (ret >= 0)
267 ret = reg_write(client, MT9T031_ROW_ADDRESS_MODE,
268 ((ybin - 1) << 4) | (yskip - 1));
269 }
270 dev_dbg(&client->dev, "new physical left %u, top %u\n",
271 rect->left, rect->top);
272
273 /*
274 * The caller provides a supported format, as guaranteed by
275 * .try_mbus_fmt(), soc_camera_s_crop() and soc_camera_cropcap()
276 */
277 if (ret >= 0)
278 ret = reg_write(client, MT9T031_COLUMN_START, rect->left);
279 if (ret >= 0)
280 ret = reg_write(client, MT9T031_ROW_START, rect->top);
281 if (ret >= 0)
282 ret = reg_write(client, MT9T031_WINDOW_WIDTH, rect->width - 1);
283 if (ret >= 0)
284 ret = reg_write(client, MT9T031_WINDOW_HEIGHT,
285 rect->height + mt9t031->y_skip_top - 1);
286 if (ret >= 0 && v4l2_ctrl_g_ctrl(mt9t031->autoexposure) == V4L2_EXPOSURE_AUTO) {
287 mt9t031->total_h = rect->height + mt9t031->y_skip_top + vblank;
288
289 ret = set_shutter(client, mt9t031->total_h);
290 }
291
292 /* Re-enable register update, commit all changes */
293 if (ret >= 0)
294 ret = reg_clear(client, MT9T031_OUTPUT_CONTROL, 1);
295
296 if (ret >= 0) {
297 mt9t031->rect = *rect;
298 mt9t031->xskip = xskip;
299 mt9t031->yskip = yskip;
300 }
301
302 return ret < 0 ? ret : 0;
303}
304
305static int mt9t031_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
306{
307 struct v4l2_rect rect = a->c;
308 struct i2c_client *client = v4l2_get_subdevdata(sd);
309 struct mt9t031 *mt9t031 = to_mt9t031(client);
310
311 rect.width = ALIGN(rect.width, 2);
312 rect.height = ALIGN(rect.height, 2);
313
314 soc_camera_limit_side(&rect.left, &rect.width,
315 MT9T031_COLUMN_SKIP, MT9T031_MIN_WIDTH, MT9T031_MAX_WIDTH);
316
317 soc_camera_limit_side(&rect.top, &rect.height,
318 MT9T031_ROW_SKIP, MT9T031_MIN_HEIGHT, MT9T031_MAX_HEIGHT);
319
320 return mt9t031_set_params(client, &rect, mt9t031->xskip, mt9t031->yskip);
321}
322
323static int mt9t031_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
324{
325 struct i2c_client *client = v4l2_get_subdevdata(sd);
326 struct mt9t031 *mt9t031 = to_mt9t031(client);
327
328 a->c = mt9t031->rect;
329 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
330
331 return 0;
332}
333
334static int mt9t031_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
335{
336 a->bounds.left = MT9T031_COLUMN_SKIP;
337 a->bounds.top = MT9T031_ROW_SKIP;
338 a->bounds.width = MT9T031_MAX_WIDTH;
339 a->bounds.height = MT9T031_MAX_HEIGHT;
340 a->defrect = a->bounds;
341 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
342 a->pixelaspect.numerator = 1;
343 a->pixelaspect.denominator = 1;
344
345 return 0;
346}
347
348static int mt9t031_g_fmt(struct v4l2_subdev *sd,
349 struct v4l2_mbus_framefmt *mf)
350{
351 struct i2c_client *client = v4l2_get_subdevdata(sd);
352 struct mt9t031 *mt9t031 = to_mt9t031(client);
353
354 mf->width = mt9t031->rect.width / mt9t031->xskip;
355 mf->height = mt9t031->rect.height / mt9t031->yskip;
356 mf->code = V4L2_MBUS_FMT_SBGGR10_1X10;
357 mf->colorspace = V4L2_COLORSPACE_SRGB;
358 mf->field = V4L2_FIELD_NONE;
359
360 return 0;
361}
362
363static int mt9t031_s_fmt(struct v4l2_subdev *sd,
364 struct v4l2_mbus_framefmt *mf)
365{
366 struct i2c_client *client = v4l2_get_subdevdata(sd);
367 struct mt9t031 *mt9t031 = to_mt9t031(client);
368 u16 xskip, yskip;
369 struct v4l2_rect rect = mt9t031->rect;
370
371 /*
372 * try_fmt has put width and height within limits.
373 * S_FMT: use binning and skipping for scaling
374 */
375 xskip = mt9t031_skip(&rect.width, mf->width, MT9T031_MAX_WIDTH);
376 yskip = mt9t031_skip(&rect.height, mf->height, MT9T031_MAX_HEIGHT);
377
378 mf->code = V4L2_MBUS_FMT_SBGGR10_1X10;
379 mf->colorspace = V4L2_COLORSPACE_SRGB;
380
381 /* mt9t031_set_params() doesn't change width and height */
382 return mt9t031_set_params(client, &rect, xskip, yskip);
383}
384
385/*
386 * If a user window larger than sensor window is requested, we'll increase the
387 * sensor window.
388 */
389static int mt9t031_try_fmt(struct v4l2_subdev *sd,
390 struct v4l2_mbus_framefmt *mf)
391{
392 v4l_bound_align_image(
393 &mf->width, MT9T031_MIN_WIDTH, MT9T031_MAX_WIDTH, 1,
394 &mf->height, MT9T031_MIN_HEIGHT, MT9T031_MAX_HEIGHT, 1, 0);
395
396 mf->code = V4L2_MBUS_FMT_SBGGR10_1X10;
397 mf->colorspace = V4L2_COLORSPACE_SRGB;
398
399 return 0;
400}
401
402static int mt9t031_g_chip_ident(struct v4l2_subdev *sd,
403 struct v4l2_dbg_chip_ident *id)
404{
405 struct i2c_client *client = v4l2_get_subdevdata(sd);
406 struct mt9t031 *mt9t031 = to_mt9t031(client);
407
408 if (id->match.type != V4L2_CHIP_MATCH_I2C_ADDR)
409 return -EINVAL;
410
411 if (id->match.addr != client->addr)
412 return -ENODEV;
413
414 id->ident = mt9t031->model;
415 id->revision = 0;
416
417 return 0;
418}
419
420#ifdef CONFIG_VIDEO_ADV_DEBUG
421static int mt9t031_g_register(struct v4l2_subdev *sd,
422 struct v4l2_dbg_register *reg)
423{
424 struct i2c_client *client = v4l2_get_subdevdata(sd);
425
426 if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0xff)
427 return -EINVAL;
428
429 if (reg->match.addr != client->addr)
430 return -ENODEV;
431
432 reg->val = reg_read(client, reg->reg);
433
434 if (reg->val > 0xffff)
435 return -EIO;
436
437 return 0;
438}
439
440static int mt9t031_s_register(struct v4l2_subdev *sd,
441 struct v4l2_dbg_register *reg)
442{
443 struct i2c_client *client = v4l2_get_subdevdata(sd);
444
445 if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0xff)
446 return -EINVAL;
447
448 if (reg->match.addr != client->addr)
449 return -ENODEV;
450
451 if (reg_write(client, reg->reg, reg->val) < 0)
452 return -EIO;
453
454 return 0;
455}
456#endif
457
458static int mt9t031_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
459{
460 struct mt9t031 *mt9t031 = container_of(ctrl->handler,
461 struct mt9t031, hdl);
462 const u32 shutter_max = MT9T031_MAX_HEIGHT + MT9T031_VERTICAL_BLANK;
463 s32 min, max;
464
465 switch (ctrl->id) {
466 case V4L2_CID_EXPOSURE_AUTO:
467 min = mt9t031->exposure->minimum;
468 max = mt9t031->exposure->maximum;
469 mt9t031->exposure->val =
470 (shutter_max / 2 + (mt9t031->total_h - 1) * (max - min))
471 / shutter_max + min;
472 break;
473 }
474 return 0;
475}
476
477static int mt9t031_s_ctrl(struct v4l2_ctrl *ctrl)
478{
479 struct mt9t031 *mt9t031 = container_of(ctrl->handler,
480 struct mt9t031, hdl);
481 struct v4l2_subdev *sd = &mt9t031->subdev;
482 struct i2c_client *client = v4l2_get_subdevdata(sd);
483 struct v4l2_ctrl *exp = mt9t031->exposure;
484 int data;
485
486 switch (ctrl->id) {
487 case V4L2_CID_VFLIP:
488 if (ctrl->val)
489 data = reg_set(client, MT9T031_READ_MODE_2, 0x8000);
490 else
491 data = reg_clear(client, MT9T031_READ_MODE_2, 0x8000);
492 if (data < 0)
493 return -EIO;
494 return 0;
495 case V4L2_CID_HFLIP:
496 if (ctrl->val)
497 data = reg_set(client, MT9T031_READ_MODE_2, 0x4000);
498 else
499 data = reg_clear(client, MT9T031_READ_MODE_2, 0x4000);
500 if (data < 0)
501 return -EIO;
502 return 0;
503 case V4L2_CID_GAIN:
504 /* See Datasheet Table 7, Gain settings. */
505 if (ctrl->val <= ctrl->default_value) {
506 /* Pack it into 0..1 step 0.125, register values 0..8 */
507 unsigned long range = ctrl->default_value - ctrl->minimum;
508 data = ((ctrl->val - ctrl->minimum) * 8 + range / 2) / range;
509
510 dev_dbg(&client->dev, "Setting gain %d\n", data);
511 data = reg_write(client, MT9T031_GLOBAL_GAIN, data);
512 if (data < 0)
513 return -EIO;
514 } else {
515 /* Pack it into 1.125..128 variable step, register values 9..0x7860 */
516 /* We assume qctrl->maximum - qctrl->default_value - 1 > 0 */
517 unsigned long range = ctrl->maximum - ctrl->default_value - 1;
518 /* calculated gain: map 65..127 to 9..1024 step 0.125 */
519 unsigned long gain = ((ctrl->val - ctrl->default_value - 1) *
520 1015 + range / 2) / range + 9;
521
522 if (gain <= 32) /* calculated gain 9..32 -> 9..32 */
523 data = gain;
524 else if (gain <= 64) /* calculated gain 33..64 -> 0x51..0x60 */
525 data = ((gain - 32) * 16 + 16) / 32 + 80;
526 else
527 /* calculated gain 65..1024 -> (1..120) << 8 + 0x60 */
528 data = (((gain - 64 + 7) * 32) & 0xff00) | 0x60;
529
530 dev_dbg(&client->dev, "Set gain from 0x%x to 0x%x\n",
531 reg_read(client, MT9T031_GLOBAL_GAIN), data);
532 data = reg_write(client, MT9T031_GLOBAL_GAIN, data);
533 if (data < 0)
534 return -EIO;
535 }
536 return 0;
537
538 case V4L2_CID_EXPOSURE_AUTO:
539 if (ctrl->val == V4L2_EXPOSURE_MANUAL) {
540 unsigned int range = exp->maximum - exp->minimum;
541 unsigned int shutter = ((exp->val - exp->minimum) * 1048 +
542 range / 2) / range + 1;
543 u32 old;
544
545 get_shutter(client, &old);
546 dev_dbg(&client->dev, "Set shutter from %u to %u\n",
547 old, shutter);
548 if (set_shutter(client, shutter) < 0)
549 return -EIO;
550 } else {
551 const u16 vblank = MT9T031_VERTICAL_BLANK;
552 mt9t031->total_h = mt9t031->rect.height +
553 mt9t031->y_skip_top + vblank;
554
555 if (set_shutter(client, mt9t031->total_h) < 0)
556 return -EIO;
557 }
558 return 0;
559 default:
560 return -EINVAL;
561 }
562 return 0;
563}
564
565/*
566 * Power Management:
567 * This function does nothing for now but must be present for pm to work
568 */
569static int mt9t031_runtime_suspend(struct device *dev)
570{
571 return 0;
572}
573
574/*
575 * Power Management:
576 * COLUMN_ADDRESS_MODE and ROW_ADDRESS_MODE are not rewritten if unchanged
577 * they are however changed at reset if the platform hook is present
578 * thus we rewrite them with the values stored by the driver
579 */
580static int mt9t031_runtime_resume(struct device *dev)
581{
582 struct video_device *vdev = to_video_device(dev);
583 struct v4l2_subdev *sd = soc_camera_vdev_to_subdev(vdev);
584 struct i2c_client *client = v4l2_get_subdevdata(sd);
585 struct mt9t031 *mt9t031 = to_mt9t031(client);
586
587 int ret;
588 u16 xbin, ybin;
589
590 xbin = min(mt9t031->xskip, (u16)3);
591 ybin = min(mt9t031->yskip, (u16)3);
592
593 ret = reg_write(client, MT9T031_COLUMN_ADDRESS_MODE,
594 ((xbin - 1) << 4) | (mt9t031->xskip - 1));
595 if (ret < 0)
596 return ret;
597
598 ret = reg_write(client, MT9T031_ROW_ADDRESS_MODE,
599 ((ybin - 1) << 4) | (mt9t031->yskip - 1));
600 if (ret < 0)
601 return ret;
602
603 return 0;
604}
605
606static struct dev_pm_ops mt9t031_dev_pm_ops = {
607 .runtime_suspend = mt9t031_runtime_suspend,
608 .runtime_resume = mt9t031_runtime_resume,
609};
610
611static struct device_type mt9t031_dev_type = {
612 .name = "MT9T031",
613 .pm = &mt9t031_dev_pm_ops,
614};
615
616static int mt9t031_s_power(struct v4l2_subdev *sd, int on)
617{
618 struct i2c_client *client = v4l2_get_subdevdata(sd);
619 struct video_device *vdev = soc_camera_i2c_to_vdev(client);
620
621 if (on)
622 vdev->dev.type = &mt9t031_dev_type;
623 else
624 vdev->dev.type = NULL;
625
626 return 0;
627}
628
629/*
630 * Interface active, can use i2c. If it fails, it can indeed mean, that
631 * this wasn't our capture interface, so, we wait for the right one
632 */
633static int mt9t031_video_probe(struct i2c_client *client)
634{
635 struct mt9t031 *mt9t031 = to_mt9t031(client);
636 s32 data;
637 int ret;
638
639 /* Enable the chip */
640 data = reg_write(client, MT9T031_CHIP_ENABLE, 1);
641 dev_dbg(&client->dev, "write: %d\n", data);
642
643 /* Read out the chip version register */
644 data = reg_read(client, MT9T031_CHIP_VERSION);
645
646 switch (data) {
647 case 0x1621:
648 mt9t031->model = V4L2_IDENT_MT9T031;
649 break;
650 default:
651 dev_err(&client->dev,
652 "No MT9T031 chip detected, register read %x\n", data);
653 return -ENODEV;
654 }
655
656 dev_info(&client->dev, "Detected a MT9T031 chip ID %x\n", data);
657
658 ret = mt9t031_idle(client);
659 if (ret < 0)
660 dev_err(&client->dev, "Failed to initialise the camera\n");
661 else
662 v4l2_ctrl_handler_setup(&mt9t031->hdl);
663
664 return ret;
665}
666
667static int mt9t031_g_skip_top_lines(struct v4l2_subdev *sd, u32 *lines)
668{
669 struct i2c_client *client = v4l2_get_subdevdata(sd);
670 struct mt9t031 *mt9t031 = to_mt9t031(client);
671
672 *lines = mt9t031->y_skip_top;
673
674 return 0;
675}
676
677static const struct v4l2_ctrl_ops mt9t031_ctrl_ops = {
678 .g_volatile_ctrl = mt9t031_g_volatile_ctrl,
679 .s_ctrl = mt9t031_s_ctrl,
680};
681
682static struct v4l2_subdev_core_ops mt9t031_subdev_core_ops = {
683 .g_chip_ident = mt9t031_g_chip_ident,
684 .s_power = mt9t031_s_power,
685#ifdef CONFIG_VIDEO_ADV_DEBUG
686 .g_register = mt9t031_g_register,
687 .s_register = mt9t031_s_register,
688#endif
689};
690
691static int mt9t031_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
692 enum v4l2_mbus_pixelcode *code)
693{
694 if (index)
695 return -EINVAL;
696
697 *code = V4L2_MBUS_FMT_SBGGR10_1X10;
698 return 0;
699}
700
701static int mt9t031_g_mbus_config(struct v4l2_subdev *sd,
702 struct v4l2_mbus_config *cfg)
703{
704 struct i2c_client *client = v4l2_get_subdevdata(sd);
705 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
706
707 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |
708 V4L2_MBUS_PCLK_SAMPLE_FALLING | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
709 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_DATA_ACTIVE_HIGH;
710 cfg->type = V4L2_MBUS_PARALLEL;
711 cfg->flags = soc_camera_apply_board_flags(icl, cfg);
712
713 return 0;
714}
715
716static int mt9t031_s_mbus_config(struct v4l2_subdev *sd,
717 const struct v4l2_mbus_config *cfg)
718{
719 struct i2c_client *client = v4l2_get_subdevdata(sd);
720 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
721
722 if (soc_camera_apply_board_flags(icl, cfg) &
723 V4L2_MBUS_PCLK_SAMPLE_FALLING)
724 return reg_clear(client, MT9T031_PIXEL_CLOCK_CONTROL, 0x8000);
725 else
726 return reg_set(client, MT9T031_PIXEL_CLOCK_CONTROL, 0x8000);
727}
728
729static struct v4l2_subdev_video_ops mt9t031_subdev_video_ops = {
730 .s_stream = mt9t031_s_stream,
731 .s_mbus_fmt = mt9t031_s_fmt,
732 .g_mbus_fmt = mt9t031_g_fmt,
733 .try_mbus_fmt = mt9t031_try_fmt,
734 .s_crop = mt9t031_s_crop,
735 .g_crop = mt9t031_g_crop,
736 .cropcap = mt9t031_cropcap,
737 .enum_mbus_fmt = mt9t031_enum_fmt,
738 .g_mbus_config = mt9t031_g_mbus_config,
739 .s_mbus_config = mt9t031_s_mbus_config,
740};
741
742static struct v4l2_subdev_sensor_ops mt9t031_subdev_sensor_ops = {
743 .g_skip_top_lines = mt9t031_g_skip_top_lines,
744};
745
746static struct v4l2_subdev_ops mt9t031_subdev_ops = {
747 .core = &mt9t031_subdev_core_ops,
748 .video = &mt9t031_subdev_video_ops,
749 .sensor = &mt9t031_subdev_sensor_ops,
750};
751
752static int mt9t031_probe(struct i2c_client *client,
753 const struct i2c_device_id *did)
754{
755 struct mt9t031 *mt9t031;
756 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
757 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
758 int ret;
759
760 if (!icl) {
761 dev_err(&client->dev, "MT9T031 driver needs platform data\n");
762 return -EINVAL;
763 }
764
765 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) {
766 dev_warn(&adapter->dev,
767 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
768 return -EIO;
769 }
770
771 mt9t031 = kzalloc(sizeof(struct mt9t031), GFP_KERNEL);
772 if (!mt9t031)
773 return -ENOMEM;
774
775 v4l2_i2c_subdev_init(&mt9t031->subdev, client, &mt9t031_subdev_ops);
776 v4l2_ctrl_handler_init(&mt9t031->hdl, 5);
777 v4l2_ctrl_new_std(&mt9t031->hdl, &mt9t031_ctrl_ops,
778 V4L2_CID_VFLIP, 0, 1, 1, 0);
779 v4l2_ctrl_new_std(&mt9t031->hdl, &mt9t031_ctrl_ops,
780 V4L2_CID_HFLIP, 0, 1, 1, 0);
781 v4l2_ctrl_new_std(&mt9t031->hdl, &mt9t031_ctrl_ops,
782 V4L2_CID_GAIN, 0, 127, 1, 64);
783
784 /*
785 * Simulated autoexposure. If enabled, we calculate shutter width
786 * ourselves in the driver based on vertical blanking and frame width
787 */
788 mt9t031->autoexposure = v4l2_ctrl_new_std_menu(&mt9t031->hdl,
789 &mt9t031_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, 1, 0,
790 V4L2_EXPOSURE_AUTO);
791 mt9t031->exposure = v4l2_ctrl_new_std(&mt9t031->hdl, &mt9t031_ctrl_ops,
792 V4L2_CID_EXPOSURE, 1, 255, 1, 255);
793
794 mt9t031->subdev.ctrl_handler = &mt9t031->hdl;
795 if (mt9t031->hdl.error) {
796 int err = mt9t031->hdl.error;
797
798 kfree(mt9t031);
799 return err;
800 }
801 v4l2_ctrl_auto_cluster(2, &mt9t031->autoexposure,
802 V4L2_EXPOSURE_MANUAL, true);
803
804 mt9t031->y_skip_top = 0;
805 mt9t031->rect.left = MT9T031_COLUMN_SKIP;
806 mt9t031->rect.top = MT9T031_ROW_SKIP;
807 mt9t031->rect.width = MT9T031_MAX_WIDTH;
808 mt9t031->rect.height = MT9T031_MAX_HEIGHT;
809
810 mt9t031->xskip = 1;
811 mt9t031->yskip = 1;
812
813 mt9t031_idle(client);
814
815 ret = mt9t031_video_probe(client);
816
817 mt9t031_disable(client);
818
819 if (ret) {
820 v4l2_ctrl_handler_free(&mt9t031->hdl);
821 kfree(mt9t031);
822 }
823
824 return ret;
825}
826
827static int mt9t031_remove(struct i2c_client *client)
828{
829 struct mt9t031 *mt9t031 = to_mt9t031(client);
830
831 v4l2_device_unregister_subdev(&mt9t031->subdev);
832 v4l2_ctrl_handler_free(&mt9t031->hdl);
833 kfree(mt9t031);
834
835 return 0;
836}
837
838static const struct i2c_device_id mt9t031_id[] = {
839 { "mt9t031", 0 },
840 { }
841};
842MODULE_DEVICE_TABLE(i2c, mt9t031_id);
843
844static struct i2c_driver mt9t031_i2c_driver = {
845 .driver = {
846 .name = "mt9t031",
847 },
848 .probe = mt9t031_probe,
849 .remove = mt9t031_remove,
850 .id_table = mt9t031_id,
851};
852
853module_i2c_driver(mt9t031_i2c_driver);
854
855MODULE_DESCRIPTION("Micron MT9T031 Camera driver");
856MODULE_AUTHOR("Guennadi Liakhovetski <lg@denx.de>");
857MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/video/mt9t112.c b/drivers/media/video/mt9t112.c
deleted file mode 100644
index e1ae46a7ee96..000000000000
--- a/drivers/media/video/mt9t112.c
+++ /dev/null
@@ -1,1125 +0,0 @@
1/*
2 * mt9t112 Camera Driver
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ov772x driver, mt9m111 driver,
8 *
9 * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
10 * Copyright (C) 2008, Robert Jarzmik <robert.jarzmik@free.fr>
11 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
12 * Copyright (C) 2008 Magnus Damm
13 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/delay.h>
21#include <linux/i2c.h>
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/slab.h>
25#include <linux/v4l2-mediabus.h>
26#include <linux/videodev2.h>
27
28#include <media/mt9t112.h>
29#include <media/soc_camera.h>
30#include <media/v4l2-chip-ident.h>
31#include <media/v4l2-common.h>
32
33/* you can check PLL/clock info */
34/* #define EXT_CLOCK 24000000 */
35
36/************************************************************************
37 macro
38************************************************************************/
39/*
40 * frame size
41 */
42#define MAX_WIDTH 2048
43#define MAX_HEIGHT 1536
44
45#define VGA_WIDTH 640
46#define VGA_HEIGHT 480
47
48/*
49 * macro of read/write
50 */
51#define ECHECKER(ret, x) \
52 do { \
53 (ret) = (x); \
54 if ((ret) < 0) \
55 return (ret); \
56 } while (0)
57
58#define mt9t112_reg_write(ret, client, a, b) \
59 ECHECKER(ret, __mt9t112_reg_write(client, a, b))
60#define mt9t112_mcu_write(ret, client, a, b) \
61 ECHECKER(ret, __mt9t112_mcu_write(client, a, b))
62
63#define mt9t112_reg_mask_set(ret, client, a, b, c) \
64 ECHECKER(ret, __mt9t112_reg_mask_set(client, a, b, c))
65#define mt9t112_mcu_mask_set(ret, client, a, b, c) \
66 ECHECKER(ret, __mt9t112_mcu_mask_set(client, a, b, c))
67
68#define mt9t112_reg_read(ret, client, a) \
69 ECHECKER(ret, __mt9t112_reg_read(client, a))
70
71/*
72 * Logical address
73 */
74#define _VAR(id, offset, base) (base | (id & 0x1f) << 10 | (offset & 0x3ff))
75#define VAR(id, offset) _VAR(id, offset, 0x0000)
76#define VAR8(id, offset) _VAR(id, offset, 0x8000)
77
78/************************************************************************
79 struct
80************************************************************************/
81struct mt9t112_format {
82 enum v4l2_mbus_pixelcode code;
83 enum v4l2_colorspace colorspace;
84 u16 fmt;
85 u16 order;
86};
87
88struct mt9t112_priv {
89 struct v4l2_subdev subdev;
90 struct mt9t112_camera_info *info;
91 struct i2c_client *client;
92 struct v4l2_rect frame;
93 const struct mt9t112_format *format;
94 int model;
95 u32 flags;
96/* for flags */
97#define INIT_DONE (1 << 0)
98#define PCLK_RISING (1 << 1)
99};
100
101/************************************************************************
102 supported format
103************************************************************************/
104
105static const struct mt9t112_format mt9t112_cfmts[] = {
106 {
107 .code = V4L2_MBUS_FMT_UYVY8_2X8,
108 .colorspace = V4L2_COLORSPACE_JPEG,
109 .fmt = 1,
110 .order = 0,
111 }, {
112 .code = V4L2_MBUS_FMT_VYUY8_2X8,
113 .colorspace = V4L2_COLORSPACE_JPEG,
114 .fmt = 1,
115 .order = 1,
116 }, {
117 .code = V4L2_MBUS_FMT_YUYV8_2X8,
118 .colorspace = V4L2_COLORSPACE_JPEG,
119 .fmt = 1,
120 .order = 2,
121 }, {
122 .code = V4L2_MBUS_FMT_YVYU8_2X8,
123 .colorspace = V4L2_COLORSPACE_JPEG,
124 .fmt = 1,
125 .order = 3,
126 }, {
127 .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE,
128 .colorspace = V4L2_COLORSPACE_SRGB,
129 .fmt = 8,
130 .order = 2,
131 }, {
132 .code = V4L2_MBUS_FMT_RGB565_2X8_LE,
133 .colorspace = V4L2_COLORSPACE_SRGB,
134 .fmt = 4,
135 .order = 2,
136 },
137};
138
139/************************************************************************
140 general function
141************************************************************************/
142static struct mt9t112_priv *to_mt9t112(const struct i2c_client *client)
143{
144 return container_of(i2c_get_clientdata(client),
145 struct mt9t112_priv,
146 subdev);
147}
148
149static int __mt9t112_reg_read(const struct i2c_client *client, u16 command)
150{
151 struct i2c_msg msg[2];
152 u8 buf[2];
153 int ret;
154
155 command = swab16(command);
156
157 msg[0].addr = client->addr;
158 msg[0].flags = 0;
159 msg[0].len = 2;
160 msg[0].buf = (u8 *)&command;
161
162 msg[1].addr = client->addr;
163 msg[1].flags = I2C_M_RD;
164 msg[1].len = 2;
165 msg[1].buf = buf;
166
167 /*
168 * if return value of this function is < 0,
169 * it mean error.
170 * else, under 16bit is valid data.
171 */
172 ret = i2c_transfer(client->adapter, msg, 2);
173 if (ret < 0)
174 return ret;
175
176 memcpy(&ret, buf, 2);
177 return swab16(ret);
178}
179
180static int __mt9t112_reg_write(const struct i2c_client *client,
181 u16 command, u16 data)
182{
183 struct i2c_msg msg;
184 u8 buf[4];
185 int ret;
186
187 command = swab16(command);
188 data = swab16(data);
189
190 memcpy(buf + 0, &command, 2);
191 memcpy(buf + 2, &data, 2);
192
193 msg.addr = client->addr;
194 msg.flags = 0;
195 msg.len = 4;
196 msg.buf = buf;
197
198 /*
199 * i2c_transfer return message length,
200 * but this function should return 0 if correct case
201 */
202 ret = i2c_transfer(client->adapter, &msg, 1);
203 if (ret >= 0)
204 ret = 0;
205
206 return ret;
207}
208
209static int __mt9t112_reg_mask_set(const struct i2c_client *client,
210 u16 command,
211 u16 mask,
212 u16 set)
213{
214 int val = __mt9t112_reg_read(client, command);
215 if (val < 0)
216 return val;
217
218 val &= ~mask;
219 val |= set & mask;
220
221 return __mt9t112_reg_write(client, command, val);
222}
223
224/* mcu access */
225static int __mt9t112_mcu_read(const struct i2c_client *client, u16 command)
226{
227 int ret;
228
229 ret = __mt9t112_reg_write(client, 0x098E, command);
230 if (ret < 0)
231 return ret;
232
233 return __mt9t112_reg_read(client, 0x0990);
234}
235
236static int __mt9t112_mcu_write(const struct i2c_client *client,
237 u16 command, u16 data)
238{
239 int ret;
240
241 ret = __mt9t112_reg_write(client, 0x098E, command);
242 if (ret < 0)
243 return ret;
244
245 return __mt9t112_reg_write(client, 0x0990, data);
246}
247
248static int __mt9t112_mcu_mask_set(const struct i2c_client *client,
249 u16 command,
250 u16 mask,
251 u16 set)
252{
253 int val = __mt9t112_mcu_read(client, command);
254 if (val < 0)
255 return val;
256
257 val &= ~mask;
258 val |= set & mask;
259
260 return __mt9t112_mcu_write(client, command, val);
261}
262
263static int mt9t112_reset(const struct i2c_client *client)
264{
265 int ret;
266
267 mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0001);
268 msleep(1);
269 mt9t112_reg_mask_set(ret, client, 0x001a, 0x0001, 0x0000);
270
271 return ret;
272}
273
274#ifndef EXT_CLOCK
275#define CLOCK_INFO(a, b)
276#else
277#define CLOCK_INFO(a, b) mt9t112_clock_info(a, b)
278static int mt9t112_clock_info(const struct i2c_client *client, u32 ext)
279{
280 int m, n, p1, p2, p3, p4, p5, p6, p7;
281 u32 vco, clk;
282 char *enable;
283
284 ext /= 1000; /* kbyte order */
285
286 mt9t112_reg_read(n, client, 0x0012);
287 p1 = n & 0x000f;
288 n = n >> 4;
289 p2 = n & 0x000f;
290 n = n >> 4;
291 p3 = n & 0x000f;
292
293 mt9t112_reg_read(n, client, 0x002a);
294 p4 = n & 0x000f;
295 n = n >> 4;
296 p5 = n & 0x000f;
297 n = n >> 4;
298 p6 = n & 0x000f;
299
300 mt9t112_reg_read(n, client, 0x002c);
301 p7 = n & 0x000f;
302
303 mt9t112_reg_read(n, client, 0x0010);
304 m = n & 0x00ff;
305 n = (n >> 8) & 0x003f;
306
307 enable = ((6000 > ext) || (54000 < ext)) ? "X" : "";
308 dev_dbg(&client->dev, "EXTCLK : %10u K %s\n", ext, enable);
309
310 vco = 2 * m * ext / (n+1);
311 enable = ((384000 > vco) || (768000 < vco)) ? "X" : "";
312 dev_dbg(&client->dev, "VCO : %10u K %s\n", vco, enable);
313
314 clk = vco / (p1+1) / (p2+1);
315 enable = (96000 < clk) ? "X" : "";
316 dev_dbg(&client->dev, "PIXCLK : %10u K %s\n", clk, enable);
317
318 clk = vco / (p3+1);
319 enable = (768000 < clk) ? "X" : "";
320 dev_dbg(&client->dev, "MIPICLK : %10u K %s\n", clk, enable);
321
322 clk = vco / (p6+1);
323 enable = (96000 < clk) ? "X" : "";
324 dev_dbg(&client->dev, "MCU CLK : %10u K %s\n", clk, enable);
325
326 clk = vco / (p5+1);
327 enable = (54000 < clk) ? "X" : "";
328 dev_dbg(&client->dev, "SOC CLK : %10u K %s\n", clk, enable);
329
330 clk = vco / (p4+1);
331 enable = (70000 < clk) ? "X" : "";
332 dev_dbg(&client->dev, "Sensor CLK : %10u K %s\n", clk, enable);
333
334 clk = vco / (p7+1);
335 dev_dbg(&client->dev, "External sensor : %10u K\n", clk);
336
337 clk = ext / (n+1);
338 enable = ((2000 > clk) || (24000 < clk)) ? "X" : "";
339 dev_dbg(&client->dev, "PFD : %10u K %s\n", clk, enable);
340
341 return 0;
342}
343#endif
344
345static void mt9t112_frame_check(u32 *width, u32 *height, u32 *left, u32 *top)
346{
347 soc_camera_limit_side(left, width, 0, 0, MAX_WIDTH);
348 soc_camera_limit_side(top, height, 0, 0, MAX_HEIGHT);
349}
350
351static int mt9t112_set_a_frame_size(const struct i2c_client *client,
352 u16 width,
353 u16 height)
354{
355 int ret;
356 u16 wstart = (MAX_WIDTH - width) / 2;
357 u16 hstart = (MAX_HEIGHT - height) / 2;
358
359 /* (Context A) Image Width/Height */
360 mt9t112_mcu_write(ret, client, VAR(26, 0), width);
361 mt9t112_mcu_write(ret, client, VAR(26, 2), height);
362
363 /* (Context A) Output Width/Height */
364 mt9t112_mcu_write(ret, client, VAR(18, 43), 8 + width);
365 mt9t112_mcu_write(ret, client, VAR(18, 45), 8 + height);
366
367 /* (Context A) Start Row/Column */
368 mt9t112_mcu_write(ret, client, VAR(18, 2), 4 + hstart);
369 mt9t112_mcu_write(ret, client, VAR(18, 4), 4 + wstart);
370
371 /* (Context A) End Row/Column */
372 mt9t112_mcu_write(ret, client, VAR(18, 6), 11 + height + hstart);
373 mt9t112_mcu_write(ret, client, VAR(18, 8), 11 + width + wstart);
374
375 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
376
377 return ret;
378}
379
380static int mt9t112_set_pll_dividers(const struct i2c_client *client,
381 u8 m, u8 n,
382 u8 p1, u8 p2, u8 p3,
383 u8 p4, u8 p5, u8 p6,
384 u8 p7)
385{
386 int ret;
387 u16 val;
388
389 /* N/M */
390 val = (n << 8) |
391 (m << 0);
392 mt9t112_reg_mask_set(ret, client, 0x0010, 0x3fff, val);
393
394 /* P1/P2/P3 */
395 val = ((p3 & 0x0F) << 8) |
396 ((p2 & 0x0F) << 4) |
397 ((p1 & 0x0F) << 0);
398 mt9t112_reg_mask_set(ret, client, 0x0012, 0x0fff, val);
399
400 /* P4/P5/P6 */
401 val = (0x7 << 12) |
402 ((p6 & 0x0F) << 8) |
403 ((p5 & 0x0F) << 4) |
404 ((p4 & 0x0F) << 0);
405 mt9t112_reg_mask_set(ret, client, 0x002A, 0x7fff, val);
406
407 /* P7 */
408 val = (0x1 << 12) |
409 ((p7 & 0x0F) << 0);
410 mt9t112_reg_mask_set(ret, client, 0x002C, 0x100f, val);
411
412 return ret;
413}
414
415static int mt9t112_init_pll(const struct i2c_client *client)
416{
417 struct mt9t112_priv *priv = to_mt9t112(client);
418 int data, i, ret;
419
420 mt9t112_reg_mask_set(ret, client, 0x0014, 0x003, 0x0001);
421
422 /* PLL control: BYPASS PLL = 8517 */
423 mt9t112_reg_write(ret, client, 0x0014, 0x2145);
424
425 /* Replace these registers when new timing parameters are generated */
426 mt9t112_set_pll_dividers(client,
427 priv->info->divider.m,
428 priv->info->divider.n,
429 priv->info->divider.p1,
430 priv->info->divider.p2,
431 priv->info->divider.p3,
432 priv->info->divider.p4,
433 priv->info->divider.p5,
434 priv->info->divider.p6,
435 priv->info->divider.p7);
436
437 /*
438 * TEST_BYPASS on
439 * PLL_ENABLE on
440 * SEL_LOCK_DET on
441 * TEST_BYPASS off
442 */
443 mt9t112_reg_write(ret, client, 0x0014, 0x2525);
444 mt9t112_reg_write(ret, client, 0x0014, 0x2527);
445 mt9t112_reg_write(ret, client, 0x0014, 0x3427);
446 mt9t112_reg_write(ret, client, 0x0014, 0x3027);
447
448 mdelay(10);
449
450 /*
451 * PLL_BYPASS off
452 * Reference clock count
453 * I2C Master Clock Divider
454 */
455 mt9t112_reg_write(ret, client, 0x0014, 0x3046);
456 mt9t112_reg_write(ret, client, 0x0016, 0x0400); /* JPEG initialization workaround */
457 mt9t112_reg_write(ret, client, 0x0022, 0x0190);
458 mt9t112_reg_write(ret, client, 0x3B84, 0x0212);
459
460 /* External sensor clock is PLL bypass */
461 mt9t112_reg_write(ret, client, 0x002E, 0x0500);
462
463 mt9t112_reg_mask_set(ret, client, 0x0018, 0x0002, 0x0002);
464 mt9t112_reg_mask_set(ret, client, 0x3B82, 0x0004, 0x0004);
465
466 /* MCU disabled */
467 mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0x0004);
468
469 /* out of standby */
470 mt9t112_reg_mask_set(ret, client, 0x0018, 0x0001, 0);
471
472 mdelay(50);
473
474 /*
475 * Standby Workaround
476 * Disable Secondary I2C Pads
477 */
478 mt9t112_reg_write(ret, client, 0x0614, 0x0001);
479 mdelay(1);
480 mt9t112_reg_write(ret, client, 0x0614, 0x0001);
481 mdelay(1);
482 mt9t112_reg_write(ret, client, 0x0614, 0x0001);
483 mdelay(1);
484 mt9t112_reg_write(ret, client, 0x0614, 0x0001);
485 mdelay(1);
486 mt9t112_reg_write(ret, client, 0x0614, 0x0001);
487 mdelay(1);
488 mt9t112_reg_write(ret, client, 0x0614, 0x0001);
489 mdelay(1);
490
491 /* poll to verify out of standby. Must Poll this bit */
492 for (i = 0; i < 100; i++) {
493 mt9t112_reg_read(data, client, 0x0018);
494 if (!(0x4000 & data))
495 break;
496
497 mdelay(10);
498 }
499
500 return ret;
501}
502
503static int mt9t112_init_setting(const struct i2c_client *client)
504{
505
506 int ret;
507
508 /* Adaptive Output Clock (A) */
509 mt9t112_mcu_mask_set(ret, client, VAR(26, 160), 0x0040, 0x0000);
510
511 /* Read Mode (A) */
512 mt9t112_mcu_write(ret, client, VAR(18, 12), 0x0024);
513
514 /* Fine Correction (A) */
515 mt9t112_mcu_write(ret, client, VAR(18, 15), 0x00CC);
516
517 /* Fine IT Min (A) */
518 mt9t112_mcu_write(ret, client, VAR(18, 17), 0x01f1);
519
520 /* Fine IT Max Margin (A) */
521 mt9t112_mcu_write(ret, client, VAR(18, 19), 0x00fF);
522
523 /* Base Frame Lines (A) */
524 mt9t112_mcu_write(ret, client, VAR(18, 29), 0x032D);
525
526 /* Min Line Length (A) */
527 mt9t112_mcu_write(ret, client, VAR(18, 31), 0x073a);
528
529 /* Line Length (A) */
530 mt9t112_mcu_write(ret, client, VAR(18, 37), 0x07d0);
531
532 /* Adaptive Output Clock (B) */
533 mt9t112_mcu_mask_set(ret, client, VAR(27, 160), 0x0040, 0x0000);
534
535 /* Row Start (B) */
536 mt9t112_mcu_write(ret, client, VAR(18, 74), 0x004);
537
538 /* Column Start (B) */
539 mt9t112_mcu_write(ret, client, VAR(18, 76), 0x004);
540
541 /* Row End (B) */
542 mt9t112_mcu_write(ret, client, VAR(18, 78), 0x60B);
543
544 /* Column End (B) */
545 mt9t112_mcu_write(ret, client, VAR(18, 80), 0x80B);
546
547 /* Fine Correction (B) */
548 mt9t112_mcu_write(ret, client, VAR(18, 87), 0x008C);
549
550 /* Fine IT Min (B) */
551 mt9t112_mcu_write(ret, client, VAR(18, 89), 0x01F1);
552
553 /* Fine IT Max Margin (B) */
554 mt9t112_mcu_write(ret, client, VAR(18, 91), 0x00FF);
555
556 /* Base Frame Lines (B) */
557 mt9t112_mcu_write(ret, client, VAR(18, 101), 0x0668);
558
559 /* Min Line Length (B) */
560 mt9t112_mcu_write(ret, client, VAR(18, 103), 0x0AF0);
561
562 /* Line Length (B) */
563 mt9t112_mcu_write(ret, client, VAR(18, 109), 0x0AF0);
564
565 /*
566 * Flicker Dectection registers
567 * This section should be replaced whenever new Timing file is generated
568 * All the following registers need to be replaced
569 * Following registers are generated from Register Wizard but user can
570 * modify them. For detail see auto flicker detection tuning
571 */
572
573 /* FD_FDPERIOD_SELECT */
574 mt9t112_mcu_write(ret, client, VAR8(8, 5), 0x01);
575
576 /* PRI_B_CONFIG_FD_ALGO_RUN */
577 mt9t112_mcu_write(ret, client, VAR(27, 17), 0x0003);
578
579 /* PRI_A_CONFIG_FD_ALGO_RUN */
580 mt9t112_mcu_write(ret, client, VAR(26, 17), 0x0003);
581
582 /*
583 * AFD range detection tuning registers
584 */
585
586 /* search_f1_50 */
587 mt9t112_mcu_write(ret, client, VAR8(18, 165), 0x25);
588
589 /* search_f2_50 */
590 mt9t112_mcu_write(ret, client, VAR8(18, 166), 0x28);
591
592 /* search_f1_60 */
593 mt9t112_mcu_write(ret, client, VAR8(18, 167), 0x2C);
594
595 /* search_f2_60 */
596 mt9t112_mcu_write(ret, client, VAR8(18, 168), 0x2F);
597
598 /* period_50Hz (A) */
599 mt9t112_mcu_write(ret, client, VAR8(18, 68), 0xBA);
600
601 /* secret register by aptina */
602 /* period_50Hz (A MSB) */
603 mt9t112_mcu_write(ret, client, VAR8(18, 303), 0x00);
604
605 /* period_60Hz (A) */
606 mt9t112_mcu_write(ret, client, VAR8(18, 69), 0x9B);
607
608 /* secret register by aptina */
609 /* period_60Hz (A MSB) */
610 mt9t112_mcu_write(ret, client, VAR8(18, 301), 0x00);
611
612 /* period_50Hz (B) */
613 mt9t112_mcu_write(ret, client, VAR8(18, 140), 0x82);
614
615 /* secret register by aptina */
616 /* period_50Hz (B) MSB */
617 mt9t112_mcu_write(ret, client, VAR8(18, 304), 0x00);
618
619 /* period_60Hz (B) */
620 mt9t112_mcu_write(ret, client, VAR8(18, 141), 0x6D);
621
622 /* secret register by aptina */
623 /* period_60Hz (B) MSB */
624 mt9t112_mcu_write(ret, client, VAR8(18, 302), 0x00);
625
626 /* FD Mode */
627 mt9t112_mcu_write(ret, client, VAR8(8, 2), 0x10);
628
629 /* Stat_min */
630 mt9t112_mcu_write(ret, client, VAR8(8, 9), 0x02);
631
632 /* Stat_max */
633 mt9t112_mcu_write(ret, client, VAR8(8, 10), 0x03);
634
635 /* Min_amplitude */
636 mt9t112_mcu_write(ret, client, VAR8(8, 12), 0x0A);
637
638 /* RX FIFO Watermark (A) */
639 mt9t112_mcu_write(ret, client, VAR(18, 70), 0x0014);
640
641 /* RX FIFO Watermark (B) */
642 mt9t112_mcu_write(ret, client, VAR(18, 142), 0x0014);
643
644 /* MCLK: 16MHz
645 * PCLK: 73MHz
646 * CorePixCLK: 36.5 MHz
647 */
648 mt9t112_mcu_write(ret, client, VAR8(18, 0x0044), 133);
649 mt9t112_mcu_write(ret, client, VAR8(18, 0x0045), 110);
650 mt9t112_mcu_write(ret, client, VAR8(18, 0x008c), 130);
651 mt9t112_mcu_write(ret, client, VAR8(18, 0x008d), 108);
652
653 mt9t112_mcu_write(ret, client, VAR8(18, 0x00A5), 27);
654 mt9t112_mcu_write(ret, client, VAR8(18, 0x00a6), 30);
655 mt9t112_mcu_write(ret, client, VAR8(18, 0x00a7), 32);
656 mt9t112_mcu_write(ret, client, VAR8(18, 0x00a8), 35);
657
658 return ret;
659}
660
661static int mt9t112_auto_focus_setting(const struct i2c_client *client)
662{
663 int ret;
664
665 mt9t112_mcu_write(ret, client, VAR(12, 13), 0x000F);
666 mt9t112_mcu_write(ret, client, VAR(12, 23), 0x0F0F);
667 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
668
669 mt9t112_reg_write(ret, client, 0x0614, 0x0000);
670
671 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x05);
672 mt9t112_mcu_write(ret, client, VAR8(12, 2), 0x02);
673 mt9t112_mcu_write(ret, client, VAR(12, 3), 0x0002);
674 mt9t112_mcu_write(ret, client, VAR(17, 3), 0x8001);
675 mt9t112_mcu_write(ret, client, VAR(17, 11), 0x0025);
676 mt9t112_mcu_write(ret, client, VAR(17, 13), 0x0193);
677 mt9t112_mcu_write(ret, client, VAR8(17, 33), 0x18);
678 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x05);
679
680 return ret;
681}
682
683static int mt9t112_auto_focus_trigger(const struct i2c_client *client)
684{
685 int ret;
686
687 mt9t112_mcu_write(ret, client, VAR8(12, 25), 0x01);
688
689 return ret;
690}
691
692static int mt9t112_init_camera(const struct i2c_client *client)
693{
694 int ret;
695
696 ECHECKER(ret, mt9t112_reset(client));
697
698 ECHECKER(ret, mt9t112_init_pll(client));
699
700 ECHECKER(ret, mt9t112_init_setting(client));
701
702 ECHECKER(ret, mt9t112_auto_focus_setting(client));
703
704 mt9t112_reg_mask_set(ret, client, 0x0018, 0x0004, 0);
705
706 /* Analog setting B */
707 mt9t112_reg_write(ret, client, 0x3084, 0x2409);
708 mt9t112_reg_write(ret, client, 0x3092, 0x0A49);
709 mt9t112_reg_write(ret, client, 0x3094, 0x4949);
710 mt9t112_reg_write(ret, client, 0x3096, 0x4950);
711
712 /*
713 * Disable adaptive clock
714 * PRI_A_CONFIG_JPEG_OB_TX_CONTROL_VAR
715 * PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR
716 */
717 mt9t112_mcu_write(ret, client, VAR(26, 160), 0x0A2E);
718 mt9t112_mcu_write(ret, client, VAR(27, 160), 0x0A2E);
719
720 /* Configure STatus in Status_before_length Format and enable header */
721 /* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR */
722 mt9t112_mcu_write(ret, client, VAR(27, 144), 0x0CB4);
723
724 /* Enable JPEG in context B */
725 /* PRI_B_CONFIG_JPEG_OB_TX_CONTROL_VAR */
726 mt9t112_mcu_write(ret, client, VAR8(27, 142), 0x01);
727
728 /* Disable Dac_TXLO */
729 mt9t112_reg_write(ret, client, 0x316C, 0x350F);
730
731 /* Set max slew rates */
732 mt9t112_reg_write(ret, client, 0x1E, 0x777);
733
734 return ret;
735}
736
737/************************************************************************
738 v4l2_subdev_core_ops
739************************************************************************/
740static int mt9t112_g_chip_ident(struct v4l2_subdev *sd,
741 struct v4l2_dbg_chip_ident *id)
742{
743 struct i2c_client *client = v4l2_get_subdevdata(sd);
744 struct mt9t112_priv *priv = to_mt9t112(client);
745
746 id->ident = priv->model;
747 id->revision = 0;
748
749 return 0;
750}
751
752#ifdef CONFIG_VIDEO_ADV_DEBUG
753static int mt9t112_g_register(struct v4l2_subdev *sd,
754 struct v4l2_dbg_register *reg)
755{
756 struct i2c_client *client = v4l2_get_subdevdata(sd);
757 int ret;
758
759 reg->size = 2;
760 mt9t112_reg_read(ret, client, reg->reg);
761
762 reg->val = (__u64)ret;
763
764 return 0;
765}
766
767static int mt9t112_s_register(struct v4l2_subdev *sd,
768 struct v4l2_dbg_register *reg)
769{
770 struct i2c_client *client = v4l2_get_subdevdata(sd);
771 int ret;
772
773 mt9t112_reg_write(ret, client, reg->reg, reg->val);
774
775 return ret;
776}
777#endif
778
779static struct v4l2_subdev_core_ops mt9t112_subdev_core_ops = {
780 .g_chip_ident = mt9t112_g_chip_ident,
781#ifdef CONFIG_VIDEO_ADV_DEBUG
782 .g_register = mt9t112_g_register,
783 .s_register = mt9t112_s_register,
784#endif
785};
786
787
788/************************************************************************
789 v4l2_subdev_video_ops
790************************************************************************/
791static int mt9t112_s_stream(struct v4l2_subdev *sd, int enable)
792{
793 struct i2c_client *client = v4l2_get_subdevdata(sd);
794 struct mt9t112_priv *priv = to_mt9t112(client);
795 int ret = 0;
796
797 if (!enable) {
798 /* FIXME
799 *
800 * If user selected large output size,
801 * and used it long time,
802 * mt9t112 camera will be very warm.
803 *
804 * But current driver can not stop mt9t112 camera.
805 * So, set small size here to solve this problem.
806 */
807 mt9t112_set_a_frame_size(client, VGA_WIDTH, VGA_HEIGHT);
808 return ret;
809 }
810
811 if (!(priv->flags & INIT_DONE)) {
812 u16 param = PCLK_RISING & priv->flags ? 0x0001 : 0x0000;
813
814 ECHECKER(ret, mt9t112_init_camera(client));
815
816 /* Invert PCLK (Data sampled on falling edge of pixclk) */
817 mt9t112_reg_write(ret, client, 0x3C20, param);
818
819 mdelay(5);
820
821 priv->flags |= INIT_DONE;
822 }
823
824 mt9t112_mcu_write(ret, client, VAR(26, 7), priv->format->fmt);
825 mt9t112_mcu_write(ret, client, VAR(26, 9), priv->format->order);
826 mt9t112_mcu_write(ret, client, VAR8(1, 0), 0x06);
827
828 mt9t112_set_a_frame_size(client,
829 priv->frame.width,
830 priv->frame.height);
831
832 ECHECKER(ret, mt9t112_auto_focus_trigger(client));
833
834 dev_dbg(&client->dev, "format : %d\n", priv->format->code);
835 dev_dbg(&client->dev, "size : %d x %d\n",
836 priv->frame.width,
837 priv->frame.height);
838
839 CLOCK_INFO(client, EXT_CLOCK);
840
841 return ret;
842}
843
844static int mt9t112_set_params(struct mt9t112_priv *priv,
845 const struct v4l2_rect *rect,
846 enum v4l2_mbus_pixelcode code)
847{
848 int i;
849
850 /*
851 * get color format
852 */
853 for (i = 0; i < ARRAY_SIZE(mt9t112_cfmts); i++)
854 if (mt9t112_cfmts[i].code == code)
855 break;
856
857 if (i == ARRAY_SIZE(mt9t112_cfmts))
858 return -EINVAL;
859
860 priv->frame = *rect;
861
862 /*
863 * frame size check
864 */
865 mt9t112_frame_check(&priv->frame.width, &priv->frame.height,
866 &priv->frame.left, &priv->frame.top);
867
868 priv->format = mt9t112_cfmts + i;
869
870 return 0;
871}
872
873static int mt9t112_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
874{
875 a->bounds.left = 0;
876 a->bounds.top = 0;
877 a->bounds.width = MAX_WIDTH;
878 a->bounds.height = MAX_HEIGHT;
879 a->defrect.left = 0;
880 a->defrect.top = 0;
881 a->defrect.width = VGA_WIDTH;
882 a->defrect.height = VGA_HEIGHT;
883 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
884 a->pixelaspect.numerator = 1;
885 a->pixelaspect.denominator = 1;
886
887 return 0;
888}
889
890static int mt9t112_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
891{
892 struct i2c_client *client = v4l2_get_subdevdata(sd);
893 struct mt9t112_priv *priv = to_mt9t112(client);
894
895 a->c = priv->frame;
896 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
897
898 return 0;
899}
900
901static int mt9t112_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
902{
903 struct i2c_client *client = v4l2_get_subdevdata(sd);
904 struct mt9t112_priv *priv = to_mt9t112(client);
905 struct v4l2_rect *rect = &a->c;
906
907 return mt9t112_set_params(priv, rect, priv->format->code);
908}
909
910static int mt9t112_g_fmt(struct v4l2_subdev *sd,
911 struct v4l2_mbus_framefmt *mf)
912{
913 struct i2c_client *client = v4l2_get_subdevdata(sd);
914 struct mt9t112_priv *priv = to_mt9t112(client);
915
916 mf->width = priv->frame.width;
917 mf->height = priv->frame.height;
918 mf->colorspace = priv->format->colorspace;
919 mf->code = priv->format->code;
920 mf->field = V4L2_FIELD_NONE;
921
922 return 0;
923}
924
925static int mt9t112_s_fmt(struct v4l2_subdev *sd,
926 struct v4l2_mbus_framefmt *mf)
927{
928 struct i2c_client *client = v4l2_get_subdevdata(sd);
929 struct mt9t112_priv *priv = to_mt9t112(client);
930 struct v4l2_rect rect = {
931 .width = mf->width,
932 .height = mf->height,
933 .left = priv->frame.left,
934 .top = priv->frame.top,
935 };
936 int ret;
937
938 ret = mt9t112_set_params(priv, &rect, mf->code);
939
940 if (!ret)
941 mf->colorspace = priv->format->colorspace;
942
943 return ret;
944}
945
946static int mt9t112_try_fmt(struct v4l2_subdev *sd,
947 struct v4l2_mbus_framefmt *mf)
948{
949 unsigned int top, left;
950 int i;
951
952 for (i = 0; i < ARRAY_SIZE(mt9t112_cfmts); i++)
953 if (mt9t112_cfmts[i].code == mf->code)
954 break;
955
956 if (i == ARRAY_SIZE(mt9t112_cfmts)) {
957 mf->code = V4L2_MBUS_FMT_UYVY8_2X8;
958 mf->colorspace = V4L2_COLORSPACE_JPEG;
959 } else {
960 mf->colorspace = mt9t112_cfmts[i].colorspace;
961 }
962
963 mt9t112_frame_check(&mf->width, &mf->height, &left, &top);
964
965 mf->field = V4L2_FIELD_NONE;
966
967 return 0;
968}
969
970static int mt9t112_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
971 enum v4l2_mbus_pixelcode *code)
972{
973 if (index >= ARRAY_SIZE(mt9t112_cfmts))
974 return -EINVAL;
975
976 *code = mt9t112_cfmts[index].code;
977
978 return 0;
979}
980
981static int mt9t112_g_mbus_config(struct v4l2_subdev *sd,
982 struct v4l2_mbus_config *cfg)
983{
984 struct i2c_client *client = v4l2_get_subdevdata(sd);
985 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
986
987 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_VSYNC_ACTIVE_HIGH |
988 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_DATA_ACTIVE_HIGH |
989 V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING;
990 cfg->type = V4L2_MBUS_PARALLEL;
991 cfg->flags = soc_camera_apply_board_flags(icl, cfg);
992
993 return 0;
994}
995
996static int mt9t112_s_mbus_config(struct v4l2_subdev *sd,
997 const struct v4l2_mbus_config *cfg)
998{
999 struct i2c_client *client = v4l2_get_subdevdata(sd);
1000 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
1001 struct mt9t112_priv *priv = to_mt9t112(client);
1002
1003 if (soc_camera_apply_board_flags(icl, cfg) & V4L2_MBUS_PCLK_SAMPLE_RISING)
1004 priv->flags |= PCLK_RISING;
1005
1006 return 0;
1007}
1008
1009static struct v4l2_subdev_video_ops mt9t112_subdev_video_ops = {
1010 .s_stream = mt9t112_s_stream,
1011 .g_mbus_fmt = mt9t112_g_fmt,
1012 .s_mbus_fmt = mt9t112_s_fmt,
1013 .try_mbus_fmt = mt9t112_try_fmt,
1014 .cropcap = mt9t112_cropcap,
1015 .g_crop = mt9t112_g_crop,
1016 .s_crop = mt9t112_s_crop,
1017 .enum_mbus_fmt = mt9t112_enum_fmt,
1018 .g_mbus_config = mt9t112_g_mbus_config,
1019 .s_mbus_config = mt9t112_s_mbus_config,
1020};
1021
1022/************************************************************************
1023 i2c driver
1024************************************************************************/
1025static struct v4l2_subdev_ops mt9t112_subdev_ops = {
1026 .core = &mt9t112_subdev_core_ops,
1027 .video = &mt9t112_subdev_video_ops,
1028};
1029
1030static int mt9t112_camera_probe(struct i2c_client *client)
1031{
1032 struct mt9t112_priv *priv = to_mt9t112(client);
1033 const char *devname;
1034 int chipid;
1035
1036 /*
1037 * check and show chip ID
1038 */
1039 mt9t112_reg_read(chipid, client, 0x0000);
1040
1041 switch (chipid) {
1042 case 0x2680:
1043 devname = "mt9t111";
1044 priv->model = V4L2_IDENT_MT9T111;
1045 break;
1046 case 0x2682:
1047 devname = "mt9t112";
1048 priv->model = V4L2_IDENT_MT9T112;
1049 break;
1050 default:
1051 dev_err(&client->dev, "Product ID error %04x\n", chipid);
1052 return -ENODEV;
1053 }
1054
1055 dev_info(&client->dev, "%s chip ID %04x\n", devname, chipid);
1056
1057 return 0;
1058}
1059
1060static int mt9t112_probe(struct i2c_client *client,
1061 const struct i2c_device_id *did)
1062{
1063 struct mt9t112_priv *priv;
1064 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
1065 struct v4l2_rect rect = {
1066 .width = VGA_WIDTH,
1067 .height = VGA_HEIGHT,
1068 .left = (MAX_WIDTH - VGA_WIDTH) / 2,
1069 .top = (MAX_HEIGHT - VGA_HEIGHT) / 2,
1070 };
1071 int ret;
1072
1073 if (!icl || !icl->priv) {
1074 dev_err(&client->dev, "mt9t112: missing platform data!\n");
1075 return -EINVAL;
1076 }
1077
1078 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1079 if (!priv)
1080 return -ENOMEM;
1081
1082 priv->info = icl->priv;
1083
1084 v4l2_i2c_subdev_init(&priv->subdev, client, &mt9t112_subdev_ops);
1085
1086 ret = mt9t112_camera_probe(client);
1087 if (ret) {
1088 kfree(priv);
1089 return ret;
1090 }
1091
1092 /* Cannot fail: using the default supported pixel code */
1093 mt9t112_set_params(priv, &rect, V4L2_MBUS_FMT_UYVY8_2X8);
1094
1095 return ret;
1096}
1097
1098static int mt9t112_remove(struct i2c_client *client)
1099{
1100 struct mt9t112_priv *priv = to_mt9t112(client);
1101
1102 kfree(priv);
1103 return 0;
1104}
1105
1106static const struct i2c_device_id mt9t112_id[] = {
1107 { "mt9t112", 0 },
1108 { }
1109};
1110MODULE_DEVICE_TABLE(i2c, mt9t112_id);
1111
1112static struct i2c_driver mt9t112_i2c_driver = {
1113 .driver = {
1114 .name = "mt9t112",
1115 },
1116 .probe = mt9t112_probe,
1117 .remove = mt9t112_remove,
1118 .id_table = mt9t112_id,
1119};
1120
1121module_i2c_driver(mt9t112_i2c_driver);
1122
1123MODULE_DESCRIPTION("SoC Camera driver for mt9t112");
1124MODULE_AUTHOR("Kuninori Morimoto");
1125MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/video/mt9v022.c b/drivers/media/video/mt9v022.c
deleted file mode 100644
index 72479247522a..000000000000
--- a/drivers/media/video/mt9v022.c
+++ /dev/null
@@ -1,879 +0,0 @@
1/*
2 * Driver for MT9V022 CMOS Image Sensor from Micron
3 *
4 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/videodev2.h>
12#include <linux/slab.h>
13#include <linux/i2c.h>
14#include <linux/delay.h>
15#include <linux/log2.h>
16#include <linux/module.h>
17
18#include <media/soc_camera.h>
19#include <media/soc_mediabus.h>
20#include <media/v4l2-subdev.h>
21#include <media/v4l2-chip-ident.h>
22#include <media/v4l2-ctrls.h>
23
24/*
25 * mt9v022 i2c address 0x48, 0x4c, 0x58, 0x5c
26 * The platform has to define struct i2c_board_info objects and link to them
27 * from struct soc_camera_link
28 */
29
30static char *sensor_type;
31module_param(sensor_type, charp, S_IRUGO);
32MODULE_PARM_DESC(sensor_type, "Sensor type: \"colour\" or \"monochrome\"");
33
34/* mt9v022 selected register addresses */
35#define MT9V022_CHIP_VERSION 0x00
36#define MT9V022_COLUMN_START 0x01
37#define MT9V022_ROW_START 0x02
38#define MT9V022_WINDOW_HEIGHT 0x03
39#define MT9V022_WINDOW_WIDTH 0x04
40#define MT9V022_HORIZONTAL_BLANKING 0x05
41#define MT9V022_VERTICAL_BLANKING 0x06
42#define MT9V022_CHIP_CONTROL 0x07
43#define MT9V022_SHUTTER_WIDTH1 0x08
44#define MT9V022_SHUTTER_WIDTH2 0x09
45#define MT9V022_SHUTTER_WIDTH_CTRL 0x0a
46#define MT9V022_TOTAL_SHUTTER_WIDTH 0x0b
47#define MT9V022_RESET 0x0c
48#define MT9V022_READ_MODE 0x0d
49#define MT9V022_MONITOR_MODE 0x0e
50#define MT9V022_PIXEL_OPERATION_MODE 0x0f
51#define MT9V022_LED_OUT_CONTROL 0x1b
52#define MT9V022_ADC_MODE_CONTROL 0x1c
53#define MT9V022_ANALOG_GAIN 0x35
54#define MT9V022_BLACK_LEVEL_CALIB_CTRL 0x47
55#define MT9V022_PIXCLK_FV_LV 0x74
56#define MT9V022_DIGITAL_TEST_PATTERN 0x7f
57#define MT9V022_AEC_AGC_ENABLE 0xAF
58#define MT9V022_MAX_TOTAL_SHUTTER_WIDTH 0xBD
59
60/* Progressive scan, master, defaults */
61#define MT9V022_CHIP_CONTROL_DEFAULT 0x188
62
63#define MT9V022_MAX_WIDTH 752
64#define MT9V022_MAX_HEIGHT 480
65#define MT9V022_MIN_WIDTH 48
66#define MT9V022_MIN_HEIGHT 32
67#define MT9V022_COLUMN_SKIP 1
68#define MT9V022_ROW_SKIP 4
69
70/* MT9V022 has only one fixed colorspace per pixelcode */
71struct mt9v022_datafmt {
72 enum v4l2_mbus_pixelcode code;
73 enum v4l2_colorspace colorspace;
74};
75
76/* Find a data format by a pixel code in an array */
77static const struct mt9v022_datafmt *mt9v022_find_datafmt(
78 enum v4l2_mbus_pixelcode code, const struct mt9v022_datafmt *fmt,
79 int n)
80{
81 int i;
82 for (i = 0; i < n; i++)
83 if (fmt[i].code == code)
84 return fmt + i;
85
86 return NULL;
87}
88
89static const struct mt9v022_datafmt mt9v022_colour_fmts[] = {
90 /*
91 * Order important: first natively supported,
92 * second supported with a GPIO extender
93 */
94 {V4L2_MBUS_FMT_SBGGR10_1X10, V4L2_COLORSPACE_SRGB},
95 {V4L2_MBUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB},
96};
97
98static const struct mt9v022_datafmt mt9v022_monochrome_fmts[] = {
99 /* Order important - see above */
100 {V4L2_MBUS_FMT_Y10_1X10, V4L2_COLORSPACE_JPEG},
101 {V4L2_MBUS_FMT_Y8_1X8, V4L2_COLORSPACE_JPEG},
102};
103
104struct mt9v022 {
105 struct v4l2_subdev subdev;
106 struct v4l2_ctrl_handler hdl;
107 struct {
108 /* exposure/auto-exposure cluster */
109 struct v4l2_ctrl *autoexposure;
110 struct v4l2_ctrl *exposure;
111 };
112 struct {
113 /* gain/auto-gain cluster */
114 struct v4l2_ctrl *autogain;
115 struct v4l2_ctrl *gain;
116 };
117 struct v4l2_rect rect; /* Sensor window */
118 const struct mt9v022_datafmt *fmt;
119 const struct mt9v022_datafmt *fmts;
120 int num_fmts;
121 int model; /* V4L2_IDENT_MT9V022* codes from v4l2-chip-ident.h */
122 u16 chip_control;
123 unsigned short y_skip_top; /* Lines to skip at the top */
124};
125
126static struct mt9v022 *to_mt9v022(const struct i2c_client *client)
127{
128 return container_of(i2c_get_clientdata(client), struct mt9v022, subdev);
129}
130
131static int reg_read(struct i2c_client *client, const u8 reg)
132{
133 return i2c_smbus_read_word_swapped(client, reg);
134}
135
136static int reg_write(struct i2c_client *client, const u8 reg,
137 const u16 data)
138{
139 return i2c_smbus_write_word_swapped(client, reg, data);
140}
141
142static int reg_set(struct i2c_client *client, const u8 reg,
143 const u16 data)
144{
145 int ret;
146
147 ret = reg_read(client, reg);
148 if (ret < 0)
149 return ret;
150 return reg_write(client, reg, ret | data);
151}
152
153static int reg_clear(struct i2c_client *client, const u8 reg,
154 const u16 data)
155{
156 int ret;
157
158 ret = reg_read(client, reg);
159 if (ret < 0)
160 return ret;
161 return reg_write(client, reg, ret & ~data);
162}
163
164static int mt9v022_init(struct i2c_client *client)
165{
166 struct mt9v022 *mt9v022 = to_mt9v022(client);
167 int ret;
168
169 /*
170 * Almost the default mode: master, parallel, simultaneous, and an
171 * undocumented bit 0x200, which is present in table 7, but not in 8,
172 * plus snapshot mode to disable scan for now
173 */
174 mt9v022->chip_control |= 0x10;
175 ret = reg_write(client, MT9V022_CHIP_CONTROL, mt9v022->chip_control);
176 if (!ret)
177 ret = reg_write(client, MT9V022_READ_MODE, 0x300);
178
179 /* All defaults */
180 if (!ret)
181 /* AEC, AGC on */
182 ret = reg_set(client, MT9V022_AEC_AGC_ENABLE, 0x3);
183 if (!ret)
184 ret = reg_write(client, MT9V022_ANALOG_GAIN, 16);
185 if (!ret)
186 ret = reg_write(client, MT9V022_TOTAL_SHUTTER_WIDTH, 480);
187 if (!ret)
188 ret = reg_write(client, MT9V022_MAX_TOTAL_SHUTTER_WIDTH, 480);
189 if (!ret)
190 /* default - auto */
191 ret = reg_clear(client, MT9V022_BLACK_LEVEL_CALIB_CTRL, 1);
192 if (!ret)
193 ret = reg_write(client, MT9V022_DIGITAL_TEST_PATTERN, 0);
194 if (!ret)
195 return v4l2_ctrl_handler_setup(&mt9v022->hdl);
196
197 return ret;
198}
199
200static int mt9v022_s_stream(struct v4l2_subdev *sd, int enable)
201{
202 struct i2c_client *client = v4l2_get_subdevdata(sd);
203 struct mt9v022 *mt9v022 = to_mt9v022(client);
204
205 if (enable)
206 /* Switch to master "normal" mode */
207 mt9v022->chip_control &= ~0x10;
208 else
209 /* Switch to snapshot mode */
210 mt9v022->chip_control |= 0x10;
211
212 if (reg_write(client, MT9V022_CHIP_CONTROL, mt9v022->chip_control) < 0)
213 return -EIO;
214 return 0;
215}
216
217static int mt9v022_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
218{
219 struct i2c_client *client = v4l2_get_subdevdata(sd);
220 struct mt9v022 *mt9v022 = to_mt9v022(client);
221 struct v4l2_rect rect = a->c;
222 int ret;
223
224 /* Bayer format - even size lengths */
225 if (mt9v022->fmts == mt9v022_colour_fmts) {
226 rect.width = ALIGN(rect.width, 2);
227 rect.height = ALIGN(rect.height, 2);
228 /* Let the user play with the starting pixel */
229 }
230
231 soc_camera_limit_side(&rect.left, &rect.width,
232 MT9V022_COLUMN_SKIP, MT9V022_MIN_WIDTH, MT9V022_MAX_WIDTH);
233
234 soc_camera_limit_side(&rect.top, &rect.height,
235 MT9V022_ROW_SKIP, MT9V022_MIN_HEIGHT, MT9V022_MAX_HEIGHT);
236
237 /* Like in example app. Contradicts the datasheet though */
238 ret = reg_read(client, MT9V022_AEC_AGC_ENABLE);
239 if (ret >= 0) {
240 if (ret & 1) /* Autoexposure */
241 ret = reg_write(client, MT9V022_MAX_TOTAL_SHUTTER_WIDTH,
242 rect.height + mt9v022->y_skip_top + 43);
243 else
244 ret = reg_write(client, MT9V022_TOTAL_SHUTTER_WIDTH,
245 rect.height + mt9v022->y_skip_top + 43);
246 }
247 /* Setup frame format: defaults apart from width and height */
248 if (!ret)
249 ret = reg_write(client, MT9V022_COLUMN_START, rect.left);
250 if (!ret)
251 ret = reg_write(client, MT9V022_ROW_START, rect.top);
252 if (!ret)
253 /*
254 * Default 94, Phytec driver says:
255 * "width + horizontal blank >= 660"
256 */
257 ret = reg_write(client, MT9V022_HORIZONTAL_BLANKING,
258 rect.width > 660 - 43 ? 43 :
259 660 - rect.width);
260 if (!ret)
261 ret = reg_write(client, MT9V022_VERTICAL_BLANKING, 45);
262 if (!ret)
263 ret = reg_write(client, MT9V022_WINDOW_WIDTH, rect.width);
264 if (!ret)
265 ret = reg_write(client, MT9V022_WINDOW_HEIGHT,
266 rect.height + mt9v022->y_skip_top);
267
268 if (ret < 0)
269 return ret;
270
271 dev_dbg(&client->dev, "Frame %dx%d pixel\n", rect.width, rect.height);
272
273 mt9v022->rect = rect;
274
275 return 0;
276}
277
278static int mt9v022_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
279{
280 struct i2c_client *client = v4l2_get_subdevdata(sd);
281 struct mt9v022 *mt9v022 = to_mt9v022(client);
282
283 a->c = mt9v022->rect;
284 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
285
286 return 0;
287}
288
289static int mt9v022_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
290{
291 a->bounds.left = MT9V022_COLUMN_SKIP;
292 a->bounds.top = MT9V022_ROW_SKIP;
293 a->bounds.width = MT9V022_MAX_WIDTH;
294 a->bounds.height = MT9V022_MAX_HEIGHT;
295 a->defrect = a->bounds;
296 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
297 a->pixelaspect.numerator = 1;
298 a->pixelaspect.denominator = 1;
299
300 return 0;
301}
302
303static int mt9v022_g_fmt(struct v4l2_subdev *sd,
304 struct v4l2_mbus_framefmt *mf)
305{
306 struct i2c_client *client = v4l2_get_subdevdata(sd);
307 struct mt9v022 *mt9v022 = to_mt9v022(client);
308
309 mf->width = mt9v022->rect.width;
310 mf->height = mt9v022->rect.height;
311 mf->code = mt9v022->fmt->code;
312 mf->colorspace = mt9v022->fmt->colorspace;
313 mf->field = V4L2_FIELD_NONE;
314
315 return 0;
316}
317
318static int mt9v022_s_fmt(struct v4l2_subdev *sd,
319 struct v4l2_mbus_framefmt *mf)
320{
321 struct i2c_client *client = v4l2_get_subdevdata(sd);
322 struct mt9v022 *mt9v022 = to_mt9v022(client);
323 struct v4l2_crop a = {
324 .c = {
325 .left = mt9v022->rect.left,
326 .top = mt9v022->rect.top,
327 .width = mf->width,
328 .height = mf->height,
329 },
330 };
331 int ret;
332
333 /*
334 * The caller provides a supported format, as verified per call to
335 * .try_mbus_fmt(), datawidth is from our supported format list
336 */
337 switch (mf->code) {
338 case V4L2_MBUS_FMT_Y8_1X8:
339 case V4L2_MBUS_FMT_Y10_1X10:
340 if (mt9v022->model != V4L2_IDENT_MT9V022IX7ATM)
341 return -EINVAL;
342 break;
343 case V4L2_MBUS_FMT_SBGGR8_1X8:
344 case V4L2_MBUS_FMT_SBGGR10_1X10:
345 if (mt9v022->model != V4L2_IDENT_MT9V022IX7ATC)
346 return -EINVAL;
347 break;
348 default:
349 return -EINVAL;
350 }
351
352 /* No support for scaling on this camera, just crop. */
353 ret = mt9v022_s_crop(sd, &a);
354 if (!ret) {
355 mf->width = mt9v022->rect.width;
356 mf->height = mt9v022->rect.height;
357 mt9v022->fmt = mt9v022_find_datafmt(mf->code,
358 mt9v022->fmts, mt9v022->num_fmts);
359 mf->colorspace = mt9v022->fmt->colorspace;
360 }
361
362 return ret;
363}
364
365static int mt9v022_try_fmt(struct v4l2_subdev *sd,
366 struct v4l2_mbus_framefmt *mf)
367{
368 struct i2c_client *client = v4l2_get_subdevdata(sd);
369 struct mt9v022 *mt9v022 = to_mt9v022(client);
370 const struct mt9v022_datafmt *fmt;
371 int align = mf->code == V4L2_MBUS_FMT_SBGGR8_1X8 ||
372 mf->code == V4L2_MBUS_FMT_SBGGR10_1X10;
373
374 v4l_bound_align_image(&mf->width, MT9V022_MIN_WIDTH,
375 MT9V022_MAX_WIDTH, align,
376 &mf->height, MT9V022_MIN_HEIGHT + mt9v022->y_skip_top,
377 MT9V022_MAX_HEIGHT + mt9v022->y_skip_top, align, 0);
378
379 fmt = mt9v022_find_datafmt(mf->code, mt9v022->fmts,
380 mt9v022->num_fmts);
381 if (!fmt) {
382 fmt = mt9v022->fmt;
383 mf->code = fmt->code;
384 }
385
386 mf->colorspace = fmt->colorspace;
387
388 return 0;
389}
390
391static int mt9v022_g_chip_ident(struct v4l2_subdev *sd,
392 struct v4l2_dbg_chip_ident *id)
393{
394 struct i2c_client *client = v4l2_get_subdevdata(sd);
395 struct mt9v022 *mt9v022 = to_mt9v022(client);
396
397 if (id->match.type != V4L2_CHIP_MATCH_I2C_ADDR)
398 return -EINVAL;
399
400 if (id->match.addr != client->addr)
401 return -ENODEV;
402
403 id->ident = mt9v022->model;
404 id->revision = 0;
405
406 return 0;
407}
408
409#ifdef CONFIG_VIDEO_ADV_DEBUG
410static int mt9v022_g_register(struct v4l2_subdev *sd,
411 struct v4l2_dbg_register *reg)
412{
413 struct i2c_client *client = v4l2_get_subdevdata(sd);
414
415 if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0xff)
416 return -EINVAL;
417
418 if (reg->match.addr != client->addr)
419 return -ENODEV;
420
421 reg->size = 2;
422 reg->val = reg_read(client, reg->reg);
423
424 if (reg->val > 0xffff)
425 return -EIO;
426
427 return 0;
428}
429
430static int mt9v022_s_register(struct v4l2_subdev *sd,
431 struct v4l2_dbg_register *reg)
432{
433 struct i2c_client *client = v4l2_get_subdevdata(sd);
434
435 if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR || reg->reg > 0xff)
436 return -EINVAL;
437
438 if (reg->match.addr != client->addr)
439 return -ENODEV;
440
441 if (reg_write(client, reg->reg, reg->val) < 0)
442 return -EIO;
443
444 return 0;
445}
446#endif
447
448static int mt9v022_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
449{
450 struct mt9v022 *mt9v022 = container_of(ctrl->handler,
451 struct mt9v022, hdl);
452 struct v4l2_subdev *sd = &mt9v022->subdev;
453 struct i2c_client *client = v4l2_get_subdevdata(sd);
454 struct v4l2_ctrl *gain = mt9v022->gain;
455 struct v4l2_ctrl *exp = mt9v022->exposure;
456 unsigned long range;
457 int data;
458
459 switch (ctrl->id) {
460 case V4L2_CID_AUTOGAIN:
461 data = reg_read(client, MT9V022_ANALOG_GAIN);
462 if (data < 0)
463 return -EIO;
464
465 range = gain->maximum - gain->minimum;
466 gain->val = ((data - 16) * range + 24) / 48 + gain->minimum;
467 return 0;
468 case V4L2_CID_EXPOSURE_AUTO:
469 data = reg_read(client, MT9V022_TOTAL_SHUTTER_WIDTH);
470 if (data < 0)
471 return -EIO;
472
473 range = exp->maximum - exp->minimum;
474 exp->val = ((data - 1) * range + 239) / 479 + exp->minimum;
475 return 0;
476 }
477 return -EINVAL;
478}
479
480static int mt9v022_s_ctrl(struct v4l2_ctrl *ctrl)
481{
482 struct mt9v022 *mt9v022 = container_of(ctrl->handler,
483 struct mt9v022, hdl);
484 struct v4l2_subdev *sd = &mt9v022->subdev;
485 struct i2c_client *client = v4l2_get_subdevdata(sd);
486 int data;
487
488 switch (ctrl->id) {
489 case V4L2_CID_VFLIP:
490 if (ctrl->val)
491 data = reg_set(client, MT9V022_READ_MODE, 0x10);
492 else
493 data = reg_clear(client, MT9V022_READ_MODE, 0x10);
494 if (data < 0)
495 return -EIO;
496 return 0;
497 case V4L2_CID_HFLIP:
498 if (ctrl->val)
499 data = reg_set(client, MT9V022_READ_MODE, 0x20);
500 else
501 data = reg_clear(client, MT9V022_READ_MODE, 0x20);
502 if (data < 0)
503 return -EIO;
504 return 0;
505 case V4L2_CID_AUTOGAIN:
506 if (ctrl->val) {
507 if (reg_set(client, MT9V022_AEC_AGC_ENABLE, 0x2) < 0)
508 return -EIO;
509 } else {
510 struct v4l2_ctrl *gain = mt9v022->gain;
511 /* mt9v022 has minimum == default */
512 unsigned long range = gain->maximum - gain->minimum;
513 /* Valid values 16 to 64, 32 to 64 must be even. */
514 unsigned long gain_val = ((gain->val - gain->minimum) *
515 48 + range / 2) / range + 16;
516
517 if (gain_val >= 32)
518 gain_val &= ~1;
519
520 /*
521 * The user wants to set gain manually, hope, she
522 * knows, what she's doing... Switch AGC off.
523 */
524 if (reg_clear(client, MT9V022_AEC_AGC_ENABLE, 0x2) < 0)
525 return -EIO;
526
527 dev_dbg(&client->dev, "Setting gain from %d to %lu\n",
528 reg_read(client, MT9V022_ANALOG_GAIN), gain_val);
529 if (reg_write(client, MT9V022_ANALOG_GAIN, gain_val) < 0)
530 return -EIO;
531 }
532 return 0;
533 case V4L2_CID_EXPOSURE_AUTO:
534 if (ctrl->val == V4L2_EXPOSURE_AUTO) {
535 data = reg_set(client, MT9V022_AEC_AGC_ENABLE, 0x1);
536 } else {
537 struct v4l2_ctrl *exp = mt9v022->exposure;
538 unsigned long range = exp->maximum - exp->minimum;
539 unsigned long shutter = ((exp->val - exp->minimum) *
540 479 + range / 2) / range + 1;
541
542 /*
543 * The user wants to set shutter width manually, hope,
544 * she knows, what she's doing... Switch AEC off.
545 */
546 data = reg_clear(client, MT9V022_AEC_AGC_ENABLE, 0x1);
547 if (data < 0)
548 return -EIO;
549 dev_dbg(&client->dev, "Shutter width from %d to %lu\n",
550 reg_read(client, MT9V022_TOTAL_SHUTTER_WIDTH),
551 shutter);
552 if (reg_write(client, MT9V022_TOTAL_SHUTTER_WIDTH,
553 shutter) < 0)
554 return -EIO;
555 }
556 return 0;
557 }
558 return -EINVAL;
559}
560
561/*
562 * Interface active, can use i2c. If it fails, it can indeed mean, that
563 * this wasn't our capture interface, so, we wait for the right one
564 */
565static int mt9v022_video_probe(struct i2c_client *client)
566{
567 struct mt9v022 *mt9v022 = to_mt9v022(client);
568 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
569 s32 data;
570 int ret;
571 unsigned long flags;
572
573 /* Read out the chip version register */
574 data = reg_read(client, MT9V022_CHIP_VERSION);
575
576 /* must be 0x1311 or 0x1313 */
577 if (data != 0x1311 && data != 0x1313) {
578 ret = -ENODEV;
579 dev_info(&client->dev, "No MT9V022 found, ID register 0x%x\n",
580 data);
581 goto ei2c;
582 }
583
584 /* Soft reset */
585 ret = reg_write(client, MT9V022_RESET, 1);
586 if (ret < 0)
587 goto ei2c;
588 /* 15 clock cycles */
589 udelay(200);
590 if (reg_read(client, MT9V022_RESET)) {
591 dev_err(&client->dev, "Resetting MT9V022 failed!\n");
592 if (ret > 0)
593 ret = -EIO;
594 goto ei2c;
595 }
596
597 /* Set monochrome or colour sensor type */
598 if (sensor_type && (!strcmp("colour", sensor_type) ||
599 !strcmp("color", sensor_type))) {
600 ret = reg_write(client, MT9V022_PIXEL_OPERATION_MODE, 4 | 0x11);
601 mt9v022->model = V4L2_IDENT_MT9V022IX7ATC;
602 mt9v022->fmts = mt9v022_colour_fmts;
603 } else {
604 ret = reg_write(client, MT9V022_PIXEL_OPERATION_MODE, 0x11);
605 mt9v022->model = V4L2_IDENT_MT9V022IX7ATM;
606 mt9v022->fmts = mt9v022_monochrome_fmts;
607 }
608
609 if (ret < 0)
610 goto ei2c;
611
612 mt9v022->num_fmts = 0;
613
614 /*
615 * This is a 10bit sensor, so by default we only allow 10bit.
616 * The platform may support different bus widths due to
617 * different routing of the data lines.
618 */
619 if (icl->query_bus_param)
620 flags = icl->query_bus_param(icl);
621 else
622 flags = SOCAM_DATAWIDTH_10;
623
624 if (flags & SOCAM_DATAWIDTH_10)
625 mt9v022->num_fmts++;
626 else
627 mt9v022->fmts++;
628
629 if (flags & SOCAM_DATAWIDTH_8)
630 mt9v022->num_fmts++;
631
632 mt9v022->fmt = &mt9v022->fmts[0];
633
634 dev_info(&client->dev, "Detected a MT9V022 chip ID %x, %s sensor\n",
635 data, mt9v022->model == V4L2_IDENT_MT9V022IX7ATM ?
636 "monochrome" : "colour");
637
638 ret = mt9v022_init(client);
639 if (ret < 0)
640 dev_err(&client->dev, "Failed to initialise the camera\n");
641
642ei2c:
643 return ret;
644}
645
646static int mt9v022_g_skip_top_lines(struct v4l2_subdev *sd, u32 *lines)
647{
648 struct i2c_client *client = v4l2_get_subdevdata(sd);
649 struct mt9v022 *mt9v022 = to_mt9v022(client);
650
651 *lines = mt9v022->y_skip_top;
652
653 return 0;
654}
655
656static const struct v4l2_ctrl_ops mt9v022_ctrl_ops = {
657 .g_volatile_ctrl = mt9v022_g_volatile_ctrl,
658 .s_ctrl = mt9v022_s_ctrl,
659};
660
661static struct v4l2_subdev_core_ops mt9v022_subdev_core_ops = {
662 .g_chip_ident = mt9v022_g_chip_ident,
663#ifdef CONFIG_VIDEO_ADV_DEBUG
664 .g_register = mt9v022_g_register,
665 .s_register = mt9v022_s_register,
666#endif
667};
668
669static int mt9v022_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
670 enum v4l2_mbus_pixelcode *code)
671{
672 struct i2c_client *client = v4l2_get_subdevdata(sd);
673 struct mt9v022 *mt9v022 = to_mt9v022(client);
674
675 if (index >= mt9v022->num_fmts)
676 return -EINVAL;
677
678 *code = mt9v022->fmts[index].code;
679 return 0;
680}
681
682static int mt9v022_g_mbus_config(struct v4l2_subdev *sd,
683 struct v4l2_mbus_config *cfg)
684{
685 struct i2c_client *client = v4l2_get_subdevdata(sd);
686 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
687
688 cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_SLAVE |
689 V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING |
690 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW |
691 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW |
692 V4L2_MBUS_DATA_ACTIVE_HIGH;
693 cfg->type = V4L2_MBUS_PARALLEL;
694 cfg->flags = soc_camera_apply_board_flags(icl, cfg);
695
696 return 0;
697}
698
699static int mt9v022_s_mbus_config(struct v4l2_subdev *sd,
700 const struct v4l2_mbus_config *cfg)
701{
702 struct i2c_client *client = v4l2_get_subdevdata(sd);
703 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
704 struct mt9v022 *mt9v022 = to_mt9v022(client);
705 unsigned long flags = soc_camera_apply_board_flags(icl, cfg);
706 unsigned int bps = soc_mbus_get_fmtdesc(mt9v022->fmt->code)->bits_per_sample;
707 int ret;
708 u16 pixclk = 0;
709
710 if (icl->set_bus_param) {
711 ret = icl->set_bus_param(icl, 1 << (bps - 1));
712 if (ret)
713 return ret;
714 } else if (bps != 10) {
715 /*
716 * Without board specific bus width settings we only support the
717 * sensors native bus width
718 */
719 return -EINVAL;
720 }
721
722 if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
723 pixclk |= 0x10;
724
725 if (!(flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH))
726 pixclk |= 0x1;
727
728 if (!(flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH))
729 pixclk |= 0x2;
730
731 ret = reg_write(client, MT9V022_PIXCLK_FV_LV, pixclk);
732 if (ret < 0)
733 return ret;
734
735 if (!(flags & V4L2_MBUS_MASTER))
736 mt9v022->chip_control &= ~0x8;
737
738 ret = reg_write(client, MT9V022_CHIP_CONTROL, mt9v022->chip_control);
739 if (ret < 0)
740 return ret;
741
742 dev_dbg(&client->dev, "Calculated pixclk 0x%x, chip control 0x%x\n",
743 pixclk, mt9v022->chip_control);
744
745 return 0;
746}
747
748static struct v4l2_subdev_video_ops mt9v022_subdev_video_ops = {
749 .s_stream = mt9v022_s_stream,
750 .s_mbus_fmt = mt9v022_s_fmt,
751 .g_mbus_fmt = mt9v022_g_fmt,
752 .try_mbus_fmt = mt9v022_try_fmt,
753 .s_crop = mt9v022_s_crop,
754 .g_crop = mt9v022_g_crop,
755 .cropcap = mt9v022_cropcap,
756 .enum_mbus_fmt = mt9v022_enum_fmt,
757 .g_mbus_config = mt9v022_g_mbus_config,
758 .s_mbus_config = mt9v022_s_mbus_config,
759};
760
761static struct v4l2_subdev_sensor_ops mt9v022_subdev_sensor_ops = {
762 .g_skip_top_lines = mt9v022_g_skip_top_lines,
763};
764
765static struct v4l2_subdev_ops mt9v022_subdev_ops = {
766 .core = &mt9v022_subdev_core_ops,
767 .video = &mt9v022_subdev_video_ops,
768 .sensor = &mt9v022_subdev_sensor_ops,
769};
770
771static int mt9v022_probe(struct i2c_client *client,
772 const struct i2c_device_id *did)
773{
774 struct mt9v022 *mt9v022;
775 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
776 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
777 int ret;
778
779 if (!icl) {
780 dev_err(&client->dev, "MT9V022 driver needs platform data\n");
781 return -EINVAL;
782 }
783
784 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_WORD_DATA)) {
785 dev_warn(&adapter->dev,
786 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
787 return -EIO;
788 }
789
790 mt9v022 = kzalloc(sizeof(struct mt9v022), GFP_KERNEL);
791 if (!mt9v022)
792 return -ENOMEM;
793
794 v4l2_i2c_subdev_init(&mt9v022->subdev, client, &mt9v022_subdev_ops);
795 v4l2_ctrl_handler_init(&mt9v022->hdl, 6);
796 v4l2_ctrl_new_std(&mt9v022->hdl, &mt9v022_ctrl_ops,
797 V4L2_CID_VFLIP, 0, 1, 1, 0);
798 v4l2_ctrl_new_std(&mt9v022->hdl, &mt9v022_ctrl_ops,
799 V4L2_CID_HFLIP, 0, 1, 1, 0);
800 mt9v022->autogain = v4l2_ctrl_new_std(&mt9v022->hdl, &mt9v022_ctrl_ops,
801 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
802 mt9v022->gain = v4l2_ctrl_new_std(&mt9v022->hdl, &mt9v022_ctrl_ops,
803 V4L2_CID_GAIN, 0, 127, 1, 64);
804
805 /*
806 * Simulated autoexposure. If enabled, we calculate shutter width
807 * ourselves in the driver based on vertical blanking and frame width
808 */
809 mt9v022->autoexposure = v4l2_ctrl_new_std_menu(&mt9v022->hdl,
810 &mt9v022_ctrl_ops, V4L2_CID_EXPOSURE_AUTO, 1, 0,
811 V4L2_EXPOSURE_AUTO);
812 mt9v022->exposure = v4l2_ctrl_new_std(&mt9v022->hdl, &mt9v022_ctrl_ops,
813 V4L2_CID_EXPOSURE, 1, 255, 1, 255);
814
815 mt9v022->subdev.ctrl_handler = &mt9v022->hdl;
816 if (mt9v022->hdl.error) {
817 int err = mt9v022->hdl.error;
818
819 kfree(mt9v022);
820 return err;
821 }
822 v4l2_ctrl_auto_cluster(2, &mt9v022->autoexposure,
823 V4L2_EXPOSURE_MANUAL, true);
824 v4l2_ctrl_auto_cluster(2, &mt9v022->autogain, 0, true);
825
826 mt9v022->chip_control = MT9V022_CHIP_CONTROL_DEFAULT;
827
828 /*
829 * MT9V022 _really_ corrupts the first read out line.
830 * TODO: verify on i.MX31
831 */
832 mt9v022->y_skip_top = 1;
833 mt9v022->rect.left = MT9V022_COLUMN_SKIP;
834 mt9v022->rect.top = MT9V022_ROW_SKIP;
835 mt9v022->rect.width = MT9V022_MAX_WIDTH;
836 mt9v022->rect.height = MT9V022_MAX_HEIGHT;
837
838 ret = mt9v022_video_probe(client);
839 if (ret) {
840 v4l2_ctrl_handler_free(&mt9v022->hdl);
841 kfree(mt9v022);
842 }
843
844 return ret;
845}
846
847static int mt9v022_remove(struct i2c_client *client)
848{
849 struct mt9v022 *mt9v022 = to_mt9v022(client);
850 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
851
852 v4l2_device_unregister_subdev(&mt9v022->subdev);
853 if (icl->free_bus)
854 icl->free_bus(icl);
855 v4l2_ctrl_handler_free(&mt9v022->hdl);
856 kfree(mt9v022);
857
858 return 0;
859}
860static const struct i2c_device_id mt9v022_id[] = {
861 { "mt9v022", 0 },
862 { }
863};
864MODULE_DEVICE_TABLE(i2c, mt9v022_id);
865
866static struct i2c_driver mt9v022_i2c_driver = {
867 .driver = {
868 .name = "mt9v022",
869 },
870 .probe = mt9v022_probe,
871 .remove = mt9v022_remove,
872 .id_table = mt9v022_id,
873};
874
875module_i2c_driver(mt9v022_i2c_driver);
876
877MODULE_DESCRIPTION("Micron MT9V022 Camera driver");
878MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
879MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/ov2640.c b/drivers/media/video/ov2640.c
deleted file mode 100644
index 7c44d1fe3c87..000000000000
--- a/drivers/media/video/ov2640.c
+++ /dev/null
@@ -1,1108 +0,0 @@
1/*
2 * ov2640 Camera Driver
3 *
4 * Copyright (C) 2010 Alberto Panizzo <maramaopercheseimorto@gmail.com>
5 *
6 * Based on ov772x, ov9640 drivers and previous non merged implementations.
7 *
8 * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
9 * Copyright (C) 2006, OmniVision
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/init.h>
17#include <linux/module.h>
18#include <linux/i2c.h>
19#include <linux/slab.h>
20#include <linux/delay.h>
21#include <linux/v4l2-mediabus.h>
22#include <linux/videodev2.h>
23
24#include <media/soc_camera.h>
25#include <media/v4l2-chip-ident.h>
26#include <media/v4l2-subdev.h>
27#include <media/v4l2-ctrls.h>
28
29#define VAL_SET(x, mask, rshift, lshift) \
30 ((((x) >> rshift) & mask) << lshift)
31/*
32 * DSP registers
33 * register offset for BANK_SEL == BANK_SEL_DSP
34 */
35#define R_BYPASS 0x05 /* Bypass DSP */
36#define R_BYPASS_DSP_BYPAS 0x01 /* Bypass DSP, sensor out directly */
37#define R_BYPASS_USE_DSP 0x00 /* Use the internal DSP */
38#define QS 0x44 /* Quantization Scale Factor */
39#define CTRLI 0x50
40#define CTRLI_LP_DP 0x80
41#define CTRLI_ROUND 0x40
42#define CTRLI_V_DIV_SET(x) VAL_SET(x, 0x3, 0, 3)
43#define CTRLI_H_DIV_SET(x) VAL_SET(x, 0x3, 0, 0)
44#define HSIZE 0x51 /* H_SIZE[7:0] (real/4) */
45#define HSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0)
46#define VSIZE 0x52 /* V_SIZE[7:0] (real/4) */
47#define VSIZE_SET(x) VAL_SET(x, 0xFF, 2, 0)
48#define XOFFL 0x53 /* OFFSET_X[7:0] */
49#define XOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0)
50#define YOFFL 0x54 /* OFFSET_Y[7:0] */
51#define YOFFL_SET(x) VAL_SET(x, 0xFF, 0, 0)
52#define VHYX 0x55 /* Offset and size completion */
53#define VHYX_VSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 7)
54#define VHYX_HSIZE_SET(x) VAL_SET(x, 0x1, (8+2), 3)
55#define VHYX_YOFF_SET(x) VAL_SET(x, 0x3, 8, 4)
56#define VHYX_XOFF_SET(x) VAL_SET(x, 0x3, 8, 0)
57#define DPRP 0x56
58#define TEST 0x57 /* Horizontal size completion */
59#define TEST_HSIZE_SET(x) VAL_SET(x, 0x1, (9+2), 7)
60#define ZMOW 0x5A /* Zoom: Out Width OUTW[7:0] (real/4) */
61#define ZMOW_OUTW_SET(x) VAL_SET(x, 0xFF, 2, 0)
62#define ZMOH 0x5B /* Zoom: Out Height OUTH[7:0] (real/4) */
63#define ZMOH_OUTH_SET(x) VAL_SET(x, 0xFF, 2, 0)
64#define ZMHH 0x5C /* Zoom: Speed and H&W completion */
65#define ZMHH_ZSPEED_SET(x) VAL_SET(x, 0x0F, 0, 4)
66#define ZMHH_OUTH_SET(x) VAL_SET(x, 0x1, (8+2), 2)
67#define ZMHH_OUTW_SET(x) VAL_SET(x, 0x3, (8+2), 0)
68#define BPADDR 0x7C /* SDE Indirect Register Access: Address */
69#define BPDATA 0x7D /* SDE Indirect Register Access: Data */
70#define CTRL2 0x86 /* DSP Module enable 2 */
71#define CTRL2_DCW_EN 0x20
72#define CTRL2_SDE_EN 0x10
73#define CTRL2_UV_ADJ_EN 0x08
74#define CTRL2_UV_AVG_EN 0x04
75#define CTRL2_CMX_EN 0x01
76#define CTRL3 0x87 /* DSP Module enable 3 */
77#define CTRL3_BPC_EN 0x80
78#define CTRL3_WPC_EN 0x40
79#define SIZEL 0x8C /* Image Size Completion */
80#define SIZEL_HSIZE8_11_SET(x) VAL_SET(x, 0x1, 11, 6)
81#define SIZEL_HSIZE8_SET(x) VAL_SET(x, 0x7, 0, 3)
82#define SIZEL_VSIZE8_SET(x) VAL_SET(x, 0x7, 0, 0)
83#define HSIZE8 0xC0 /* Image Horizontal Size HSIZE[10:3] */
84#define HSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0)
85#define VSIZE8 0xC1 /* Image Vertical Size VSIZE[10:3] */
86#define VSIZE8_SET(x) VAL_SET(x, 0xFF, 3, 0)
87#define CTRL0 0xC2 /* DSP Module enable 0 */
88#define CTRL0_AEC_EN 0x80
89#define CTRL0_AEC_SEL 0x40
90#define CTRL0_STAT_SEL 0x20
91#define CTRL0_VFIRST 0x10
92#define CTRL0_YUV422 0x08
93#define CTRL0_YUV_EN 0x04
94#define CTRL0_RGB_EN 0x02
95#define CTRL0_RAW_EN 0x01
96#define CTRL1 0xC3 /* DSP Module enable 1 */
97#define CTRL1_CIP 0x80
98#define CTRL1_DMY 0x40
99#define CTRL1_RAW_GMA 0x20
100#define CTRL1_DG 0x10
101#define CTRL1_AWB 0x08
102#define CTRL1_AWB_GAIN 0x04
103#define CTRL1_LENC 0x02
104#define CTRL1_PRE 0x01
105#define R_DVP_SP 0xD3 /* DVP output speed control */
106#define R_DVP_SP_AUTO_MODE 0x80
107#define R_DVP_SP_DVP_MASK 0x3F /* DVP PCLK = sysclk (48)/[6:0] (YUV0);
108 * = sysclk (48)/(2*[6:0]) (RAW);*/
109#define IMAGE_MODE 0xDA /* Image Output Format Select */
110#define IMAGE_MODE_Y8_DVP_EN 0x40
111#define IMAGE_MODE_JPEG_EN 0x10
112#define IMAGE_MODE_YUV422 0x00
113#define IMAGE_MODE_RAW10 0x04 /* (DVP) */
114#define IMAGE_MODE_RGB565 0x08
115#define IMAGE_MODE_HREF_VSYNC 0x02 /* HREF timing select in DVP JPEG output
116 * mode (0 for HREF is same as sensor) */
117#define IMAGE_MODE_LBYTE_FIRST 0x01 /* Byte swap enable for DVP
118 * 1: Low byte first UYVY (C2[4] =0)
119 * VYUY (C2[4] =1)
120 * 0: High byte first YUYV (C2[4]=0)
121 * YVYU (C2[4] = 1) */
122#define RESET 0xE0 /* Reset */
123#define RESET_MICROC 0x40
124#define RESET_SCCB 0x20
125#define RESET_JPEG 0x10
126#define RESET_DVP 0x04
127#define RESET_IPU 0x02
128#define RESET_CIF 0x01
129#define REGED 0xED /* Register ED */
130#define REGED_CLK_OUT_DIS 0x10
131#define MS_SP 0xF0 /* SCCB Master Speed */
132#define SS_ID 0xF7 /* SCCB Slave ID */
133#define SS_CTRL 0xF8 /* SCCB Slave Control */
134#define SS_CTRL_ADD_AUTO_INC 0x20
135#define SS_CTRL_EN 0x08
136#define SS_CTRL_DELAY_CLK 0x04
137#define SS_CTRL_ACC_EN 0x02
138#define SS_CTRL_SEN_PASS_THR 0x01
139#define MC_BIST 0xF9 /* Microcontroller misc register */
140#define MC_BIST_RESET 0x80 /* Microcontroller Reset */
141#define MC_BIST_BOOT_ROM_SEL 0x40
142#define MC_BIST_12KB_SEL 0x20
143#define MC_BIST_12KB_MASK 0x30
144#define MC_BIST_512KB_SEL 0x08
145#define MC_BIST_512KB_MASK 0x0C
146#define MC_BIST_BUSY_BIT_R 0x02
147#define MC_BIST_MC_RES_ONE_SH_W 0x02
148#define MC_BIST_LAUNCH 0x01
149#define BANK_SEL 0xFF /* Register Bank Select */
150#define BANK_SEL_DSP 0x00
151#define BANK_SEL_SENS 0x01
152
153/*
154 * Sensor registers
155 * register offset for BANK_SEL == BANK_SEL_SENS
156 */
157#define GAIN 0x00 /* AGC - Gain control gain setting */
158#define COM1 0x03 /* Common control 1 */
159#define COM1_1_DUMMY_FR 0x40
160#define COM1_3_DUMMY_FR 0x80
161#define COM1_7_DUMMY_FR 0xC0
162#define COM1_VWIN_LSB_UXGA 0x0F
163#define COM1_VWIN_LSB_SVGA 0x0A
164#define COM1_VWIN_LSB_CIF 0x06
165#define REG04 0x04 /* Register 04 */
166#define REG04_DEF 0x20 /* Always set */
167#define REG04_HFLIP_IMG 0x80 /* Horizontal mirror image ON/OFF */
168#define REG04_VFLIP_IMG 0x40 /* Vertical flip image ON/OFF */
169#define REG04_VREF_EN 0x10
170#define REG04_HREF_EN 0x08
171#define REG04_AEC_SET(x) VAL_SET(x, 0x3, 0, 0)
172#define REG08 0x08 /* Frame Exposure One-pin Control Pre-charge Row Num */
173#define COM2 0x09 /* Common control 2 */
174#define COM2_SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */
175 /* Output drive capability */
176#define COM2_OCAP_Nx_SET(N) (((N) - 1) & 0x03) /* N = [1x .. 4x] */
177#define PID 0x0A /* Product ID Number MSB */
178#define VER 0x0B /* Product ID Number LSB */
179#define COM3 0x0C /* Common control 3 */
180#define COM3_BAND_50H 0x04 /* 0 For Banding at 60H */
181#define COM3_BAND_AUTO 0x02 /* Auto Banding */
182#define COM3_SING_FR_SNAPSH 0x01 /* 0 For enable live video output after the
183 * snapshot sequence*/
184#define AEC 0x10 /* AEC[9:2] Exposure Value */
185#define CLKRC 0x11 /* Internal clock */
186#define CLKRC_EN 0x80
187#define CLKRC_DIV_SET(x) (((x) - 1) & 0x1F) /* CLK = XVCLK/(x) */
188#define COM7 0x12 /* Common control 7 */
189#define COM7_SRST 0x80 /* Initiates system reset. All registers are
190 * set to factory default values after which
191 * the chip resumes normal operation */
192#define COM7_RES_UXGA 0x00 /* Resolution selectors for UXGA */
193#define COM7_RES_SVGA 0x40 /* SVGA */
194#define COM7_RES_CIF 0x20 /* CIF */
195#define COM7_ZOOM_EN 0x04 /* Enable Zoom mode */
196#define COM7_COLOR_BAR_TEST 0x02 /* Enable Color Bar Test Pattern */
197#define COM8 0x13 /* Common control 8 */
198#define COM8_DEF 0xC0 /* Banding filter ON/OFF */
199#define COM8_BNDF_EN 0x20 /* Banding filter ON/OFF */
200#define COM8_AGC_EN 0x04 /* AGC Auto/Manual control selection */
201#define COM8_AEC_EN 0x01 /* Auto/Manual Exposure control */
202#define COM9 0x14 /* Common control 9
203 * Automatic gain ceiling - maximum AGC value [7:5]*/
204#define COM9_AGC_GAIN_2x 0x00 /* 000 : 2x */
205#define COM9_AGC_GAIN_4x 0x20 /* 001 : 4x */
206#define COM9_AGC_GAIN_8x 0x40 /* 010 : 8x */
207#define COM9_AGC_GAIN_16x 0x60 /* 011 : 16x */
208#define COM9_AGC_GAIN_32x 0x80 /* 100 : 32x */
209#define COM9_AGC_GAIN_64x 0xA0 /* 101 : 64x */
210#define COM9_AGC_GAIN_128x 0xC0 /* 110 : 128x */
211#define COM10 0x15 /* Common control 10 */
212#define COM10_PCLK_HREF 0x20 /* PCLK output qualified by HREF */
213#define COM10_PCLK_RISE 0x10 /* Data is updated at the rising edge of
214 * PCLK (user can latch data at the next
215 * falling edge of PCLK).
216 * 0 otherwise. */
217#define COM10_HREF_INV 0x08 /* Invert HREF polarity:
218 * HREF negative for valid data*/
219#define COM10_VSINC_INV 0x02 /* Invert VSYNC polarity */
220#define HSTART 0x17 /* Horizontal Window start MSB 8 bit */
221#define HEND 0x18 /* Horizontal Window end MSB 8 bit */
222#define VSTART 0x19 /* Vertical Window start MSB 8 bit */
223#define VEND 0x1A /* Vertical Window end MSB 8 bit */
224#define MIDH 0x1C /* Manufacturer ID byte - high */
225#define MIDL 0x1D /* Manufacturer ID byte - low */
226#define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */
227#define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */
228#define VV 0x26 /* AGC/AEC Fast mode operating region */
229#define VV_HIGH_TH_SET(x) VAL_SET(x, 0xF, 0, 4)
230#define VV_LOW_TH_SET(x) VAL_SET(x, 0xF, 0, 0)
231#define REG2A 0x2A /* Dummy pixel insert MSB */
232#define FRARL 0x2B /* Dummy pixel insert LSB */
233#define ADDVFL 0x2D /* LSB of insert dummy lines in Vertical direction */
234#define ADDVFH 0x2E /* MSB of insert dummy lines in Vertical direction */
235#define YAVG 0x2F /* Y/G Channel Average value */
236#define REG32 0x32 /* Common Control 32 */
237#define REG32_PCLK_DIV_2 0x80 /* PCLK freq divided by 2 */
238#define REG32_PCLK_DIV_4 0xC0 /* PCLK freq divided by 4 */
239#define ARCOM2 0x34 /* Zoom: Horizontal start point */
240#define REG45 0x45 /* Register 45 */
241#define FLL 0x46 /* Frame Length Adjustment LSBs */
242#define FLH 0x47 /* Frame Length Adjustment MSBs */
243#define COM19 0x48 /* Zoom: Vertical start point */
244#define ZOOMS 0x49 /* Zoom: Vertical start point */
245#define COM22 0x4B /* Flash light control */
246#define COM25 0x4E /* For Banding operations */
247#define BD50 0x4F /* 50Hz Banding AEC 8 LSBs */
248#define BD60 0x50 /* 60Hz Banding AEC 8 LSBs */
249#define REG5D 0x5D /* AVGsel[7:0], 16-zone average weight option */
250#define REG5E 0x5E /* AVGsel[15:8], 16-zone average weight option */
251#define REG5F 0x5F /* AVGsel[23:16], 16-zone average weight option */
252#define REG60 0x60 /* AVGsel[31:24], 16-zone average weight option */
253#define HISTO_LOW 0x61 /* Histogram Algorithm Low Level */
254#define HISTO_HIGH 0x62 /* Histogram Algorithm High Level */
255
256/*
257 * ID
258 */
259#define MANUFACTURER_ID 0x7FA2
260#define PID_OV2640 0x2642
261#define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF))
262
263/*
264 * Struct
265 */
266struct regval_list {
267 u8 reg_num;
268 u8 value;
269};
270
271/* Supported resolutions */
272enum ov2640_width {
273 W_QCIF = 176,
274 W_QVGA = 320,
275 W_CIF = 352,
276 W_VGA = 640,
277 W_SVGA = 800,
278 W_XGA = 1024,
279 W_SXGA = 1280,
280 W_UXGA = 1600,
281};
282
283enum ov2640_height {
284 H_QCIF = 144,
285 H_QVGA = 240,
286 H_CIF = 288,
287 H_VGA = 480,
288 H_SVGA = 600,
289 H_XGA = 768,
290 H_SXGA = 1024,
291 H_UXGA = 1200,
292};
293
294struct ov2640_win_size {
295 char *name;
296 enum ov2640_width width;
297 enum ov2640_height height;
298 const struct regval_list *regs;
299};
300
301
302struct ov2640_priv {
303 struct v4l2_subdev subdev;
304 struct v4l2_ctrl_handler hdl;
305 enum v4l2_mbus_pixelcode cfmt_code;
306 const struct ov2640_win_size *win;
307 int model;
308};
309
310/*
311 * Registers settings
312 */
313
314#define ENDMARKER { 0xff, 0xff }
315
316static const struct regval_list ov2640_init_regs[] = {
317 { BANK_SEL, BANK_SEL_DSP },
318 { 0x2c, 0xff },
319 { 0x2e, 0xdf },
320 { BANK_SEL, BANK_SEL_SENS },
321 { 0x3c, 0x32 },
322 { CLKRC, CLKRC_DIV_SET(1) },
323 { COM2, COM2_OCAP_Nx_SET(3) },
324 { REG04, REG04_DEF | REG04_HREF_EN },
325 { COM8, COM8_DEF | COM8_BNDF_EN | COM8_AGC_EN | COM8_AEC_EN },
326 { COM9, COM9_AGC_GAIN_8x | 0x08},
327 { 0x2c, 0x0c },
328 { 0x33, 0x78 },
329 { 0x3a, 0x33 },
330 { 0x3b, 0xfb },
331 { 0x3e, 0x00 },
332 { 0x43, 0x11 },
333 { 0x16, 0x10 },
334 { 0x39, 0x02 },
335 { 0x35, 0x88 },
336 { 0x22, 0x0a },
337 { 0x37, 0x40 },
338 { 0x23, 0x00 },
339 { ARCOM2, 0xa0 },
340 { 0x06, 0x02 },
341 { 0x06, 0x88 },
342 { 0x07, 0xc0 },
343 { 0x0d, 0xb7 },
344 { 0x0e, 0x01 },
345 { 0x4c, 0x00 },
346 { 0x4a, 0x81 },
347 { 0x21, 0x99 },
348 { AEW, 0x40 },
349 { AEB, 0x38 },
350 { VV, VV_HIGH_TH_SET(0x08) | VV_LOW_TH_SET(0x02) },
351 { 0x5c, 0x00 },
352 { 0x63, 0x00 },
353 { FLL, 0x22 },
354 { COM3, 0x38 | COM3_BAND_AUTO },
355 { REG5D, 0x55 },
356 { REG5E, 0x7d },
357 { REG5F, 0x7d },
358 { REG60, 0x55 },
359 { HISTO_LOW, 0x70 },
360 { HISTO_HIGH, 0x80 },
361 { 0x7c, 0x05 },
362 { 0x20, 0x80 },
363 { 0x28, 0x30 },
364 { 0x6c, 0x00 },
365 { 0x6d, 0x80 },
366 { 0x6e, 0x00 },
367 { 0x70, 0x02 },
368 { 0x71, 0x94 },
369 { 0x73, 0xc1 },
370 { 0x3d, 0x34 },
371 { COM7, COM7_RES_UXGA | COM7_ZOOM_EN },
372 { 0x5a, 0x57 },
373 { BD50, 0xbb },
374 { BD60, 0x9c },
375 { BANK_SEL, BANK_SEL_DSP },
376 { 0xe5, 0x7f },
377 { MC_BIST, MC_BIST_RESET | MC_BIST_BOOT_ROM_SEL },
378 { 0x41, 0x24 },
379 { RESET, RESET_JPEG | RESET_DVP },
380 { 0x76, 0xff },
381 { 0x33, 0xa0 },
382 { 0x42, 0x20 },
383 { 0x43, 0x18 },
384 { 0x4c, 0x00 },
385 { CTRL3, CTRL3_BPC_EN | CTRL3_WPC_EN | 0x10 },
386 { 0x88, 0x3f },
387 { 0xd7, 0x03 },
388 { 0xd9, 0x10 },
389 { R_DVP_SP , R_DVP_SP_AUTO_MODE | 0x2 },
390 { 0xc8, 0x08 },
391 { 0xc9, 0x80 },
392 { BPADDR, 0x00 },
393 { BPDATA, 0x00 },
394 { BPADDR, 0x03 },
395 { BPDATA, 0x48 },
396 { BPDATA, 0x48 },
397 { BPADDR, 0x08 },
398 { BPDATA, 0x20 },
399 { BPDATA, 0x10 },
400 { BPDATA, 0x0e },
401 { 0x90, 0x00 },
402 { 0x91, 0x0e },
403 { 0x91, 0x1a },
404 { 0x91, 0x31 },
405 { 0x91, 0x5a },
406 { 0x91, 0x69 },
407 { 0x91, 0x75 },
408 { 0x91, 0x7e },
409 { 0x91, 0x88 },
410 { 0x91, 0x8f },
411 { 0x91, 0x96 },
412 { 0x91, 0xa3 },
413 { 0x91, 0xaf },
414 { 0x91, 0xc4 },
415 { 0x91, 0xd7 },
416 { 0x91, 0xe8 },
417 { 0x91, 0x20 },
418 { 0x92, 0x00 },
419 { 0x93, 0x06 },
420 { 0x93, 0xe3 },
421 { 0x93, 0x03 },
422 { 0x93, 0x03 },
423 { 0x93, 0x00 },
424 { 0x93, 0x02 },
425 { 0x93, 0x00 },
426 { 0x93, 0x00 },
427 { 0x93, 0x00 },
428 { 0x93, 0x00 },
429 { 0x93, 0x00 },
430 { 0x93, 0x00 },
431 { 0x93, 0x00 },
432 { 0x96, 0x00 },
433 { 0x97, 0x08 },
434 { 0x97, 0x19 },
435 { 0x97, 0x02 },
436 { 0x97, 0x0c },
437 { 0x97, 0x24 },
438 { 0x97, 0x30 },
439 { 0x97, 0x28 },
440 { 0x97, 0x26 },
441 { 0x97, 0x02 },
442 { 0x97, 0x98 },
443 { 0x97, 0x80 },
444 { 0x97, 0x00 },
445 { 0x97, 0x00 },
446 { 0xa4, 0x00 },
447 { 0xa8, 0x00 },
448 { 0xc5, 0x11 },
449 { 0xc6, 0x51 },
450 { 0xbf, 0x80 },
451 { 0xc7, 0x10 },
452 { 0xb6, 0x66 },
453 { 0xb8, 0xA5 },
454 { 0xb7, 0x64 },
455 { 0xb9, 0x7C },
456 { 0xb3, 0xaf },
457 { 0xb4, 0x97 },
458 { 0xb5, 0xFF },
459 { 0xb0, 0xC5 },
460 { 0xb1, 0x94 },
461 { 0xb2, 0x0f },
462 { 0xc4, 0x5c },
463 { 0xa6, 0x00 },
464 { 0xa7, 0x20 },
465 { 0xa7, 0xd8 },
466 { 0xa7, 0x1b },
467 { 0xa7, 0x31 },
468 { 0xa7, 0x00 },
469 { 0xa7, 0x18 },
470 { 0xa7, 0x20 },
471 { 0xa7, 0xd8 },
472 { 0xa7, 0x19 },
473 { 0xa7, 0x31 },
474 { 0xa7, 0x00 },
475 { 0xa7, 0x18 },
476 { 0xa7, 0x20 },
477 { 0xa7, 0xd8 },
478 { 0xa7, 0x19 },
479 { 0xa7, 0x31 },
480 { 0xa7, 0x00 },
481 { 0xa7, 0x18 },
482 { 0x7f, 0x00 },
483 { 0xe5, 0x1f },
484 { 0xe1, 0x77 },
485 { 0xdd, 0x7f },
486 { CTRL0, CTRL0_YUV422 | CTRL0_YUV_EN | CTRL0_RGB_EN },
487 ENDMARKER,
488};
489
490/*
491 * Register settings for window size
492 * The preamble, setup the internal DSP to input an UXGA (1600x1200) image.
493 * Then the different zooming configurations will setup the output image size.
494 */
495static const struct regval_list ov2640_size_change_preamble_regs[] = {
496 { BANK_SEL, BANK_SEL_DSP },
497 { RESET, RESET_DVP },
498 { HSIZE8, HSIZE8_SET(W_UXGA) },
499 { VSIZE8, VSIZE8_SET(H_UXGA) },
500 { CTRL2, CTRL2_DCW_EN | CTRL2_SDE_EN |
501 CTRL2_UV_AVG_EN | CTRL2_CMX_EN | CTRL2_UV_ADJ_EN },
502 { HSIZE, HSIZE_SET(W_UXGA) },
503 { VSIZE, VSIZE_SET(H_UXGA) },
504 { XOFFL, XOFFL_SET(0) },
505 { YOFFL, YOFFL_SET(0) },
506 { VHYX, VHYX_HSIZE_SET(W_UXGA) | VHYX_VSIZE_SET(H_UXGA) |
507 VHYX_XOFF_SET(0) | VHYX_YOFF_SET(0)},
508 { TEST, TEST_HSIZE_SET(W_UXGA) },
509 ENDMARKER,
510};
511
512#define PER_SIZE_REG_SEQ(x, y, v_div, h_div, pclk_div) \
513 { CTRLI, CTRLI_LP_DP | CTRLI_V_DIV_SET(v_div) | \
514 CTRLI_H_DIV_SET(h_div)}, \
515 { ZMOW, ZMOW_OUTW_SET(x) }, \
516 { ZMOH, ZMOH_OUTH_SET(y) }, \
517 { ZMHH, ZMHH_OUTW_SET(x) | ZMHH_OUTH_SET(y) }, \
518 { R_DVP_SP, pclk_div }, \
519 { RESET, 0x00}
520
521static const struct regval_list ov2640_qcif_regs[] = {
522 PER_SIZE_REG_SEQ(W_QCIF, H_QCIF, 3, 3, 4),
523 ENDMARKER,
524};
525
526static const struct regval_list ov2640_qvga_regs[] = {
527 PER_SIZE_REG_SEQ(W_QVGA, H_QVGA, 2, 2, 4),
528 ENDMARKER,
529};
530
531static const struct regval_list ov2640_cif_regs[] = {
532 PER_SIZE_REG_SEQ(W_CIF, H_CIF, 2, 2, 8),
533 ENDMARKER,
534};
535
536static const struct regval_list ov2640_vga_regs[] = {
537 PER_SIZE_REG_SEQ(W_VGA, H_VGA, 0, 0, 2),
538 ENDMARKER,
539};
540
541static const struct regval_list ov2640_svga_regs[] = {
542 PER_SIZE_REG_SEQ(W_SVGA, H_SVGA, 1, 1, 2),
543 ENDMARKER,
544};
545
546static const struct regval_list ov2640_xga_regs[] = {
547 PER_SIZE_REG_SEQ(W_XGA, H_XGA, 0, 0, 2),
548 { CTRLI, 0x00},
549 ENDMARKER,
550};
551
552static const struct regval_list ov2640_sxga_regs[] = {
553 PER_SIZE_REG_SEQ(W_SXGA, H_SXGA, 0, 0, 2),
554 { CTRLI, 0x00},
555 { R_DVP_SP, 2 | R_DVP_SP_AUTO_MODE },
556 ENDMARKER,
557};
558
559static const struct regval_list ov2640_uxga_regs[] = {
560 PER_SIZE_REG_SEQ(W_UXGA, H_UXGA, 0, 0, 0),
561 { CTRLI, 0x00},
562 { R_DVP_SP, 0 | R_DVP_SP_AUTO_MODE },
563 ENDMARKER,
564};
565
566#define OV2640_SIZE(n, w, h, r) \
567 {.name = n, .width = w , .height = h, .regs = r }
568
569static const struct ov2640_win_size ov2640_supported_win_sizes[] = {
570 OV2640_SIZE("QCIF", W_QCIF, H_QCIF, ov2640_qcif_regs),
571 OV2640_SIZE("QVGA", W_QVGA, H_QVGA, ov2640_qvga_regs),
572 OV2640_SIZE("CIF", W_CIF, H_CIF, ov2640_cif_regs),
573 OV2640_SIZE("VGA", W_VGA, H_VGA, ov2640_vga_regs),
574 OV2640_SIZE("SVGA", W_SVGA, H_SVGA, ov2640_svga_regs),
575 OV2640_SIZE("XGA", W_XGA, H_XGA, ov2640_xga_regs),
576 OV2640_SIZE("SXGA", W_SXGA, H_SXGA, ov2640_sxga_regs),
577 OV2640_SIZE("UXGA", W_UXGA, H_UXGA, ov2640_uxga_regs),
578};
579
580/*
581 * Register settings for pixel formats
582 */
583static const struct regval_list ov2640_format_change_preamble_regs[] = {
584 { BANK_SEL, BANK_SEL_DSP },
585 { R_BYPASS, R_BYPASS_USE_DSP },
586 ENDMARKER,
587};
588
589static const struct regval_list ov2640_yuv422_regs[] = {
590 { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_YUV422 },
591 { 0xD7, 0x01 },
592 { 0x33, 0xa0 },
593 { 0xe1, 0x67 },
594 { RESET, 0x00 },
595 { R_BYPASS, R_BYPASS_USE_DSP },
596 ENDMARKER,
597};
598
599static const struct regval_list ov2640_rgb565_regs[] = {
600 { IMAGE_MODE, IMAGE_MODE_LBYTE_FIRST | IMAGE_MODE_RGB565 },
601 { 0xd7, 0x03 },
602 { RESET, 0x00 },
603 { R_BYPASS, R_BYPASS_USE_DSP },
604 ENDMARKER,
605};
606
607static enum v4l2_mbus_pixelcode ov2640_codes[] = {
608 V4L2_MBUS_FMT_UYVY8_2X8,
609 V4L2_MBUS_FMT_RGB565_2X8_LE,
610};
611
612/*
613 * General functions
614 */
615static struct ov2640_priv *to_ov2640(const struct i2c_client *client)
616{
617 return container_of(i2c_get_clientdata(client), struct ov2640_priv,
618 subdev);
619}
620
621static int ov2640_write_array(struct i2c_client *client,
622 const struct regval_list *vals)
623{
624 int ret;
625
626 while ((vals->reg_num != 0xff) || (vals->value != 0xff)) {
627 ret = i2c_smbus_write_byte_data(client,
628 vals->reg_num, vals->value);
629 dev_vdbg(&client->dev, "array: 0x%02x, 0x%02x",
630 vals->reg_num, vals->value);
631
632 if (ret < 0)
633 return ret;
634 vals++;
635 }
636 return 0;
637}
638
639static int ov2640_mask_set(struct i2c_client *client,
640 u8 reg, u8 mask, u8 set)
641{
642 s32 val = i2c_smbus_read_byte_data(client, reg);
643 if (val < 0)
644 return val;
645
646 val &= ~mask;
647 val |= set & mask;
648
649 dev_vdbg(&client->dev, "masks: 0x%02x, 0x%02x", reg, val);
650
651 return i2c_smbus_write_byte_data(client, reg, val);
652}
653
654static int ov2640_reset(struct i2c_client *client)
655{
656 int ret;
657 const struct regval_list reset_seq[] = {
658 {BANK_SEL, BANK_SEL_SENS},
659 {COM7, COM7_SRST},
660 ENDMARKER,
661 };
662
663 ret = ov2640_write_array(client, reset_seq);
664 if (ret)
665 goto err;
666
667 msleep(5);
668err:
669 dev_dbg(&client->dev, "%s: (ret %d)", __func__, ret);
670 return ret;
671}
672
673/*
674 * soc_camera_ops functions
675 */
676static int ov2640_s_stream(struct v4l2_subdev *sd, int enable)
677{
678 return 0;
679}
680
681static int ov2640_s_ctrl(struct v4l2_ctrl *ctrl)
682{
683 struct v4l2_subdev *sd =
684 &container_of(ctrl->handler, struct ov2640_priv, hdl)->subdev;
685 struct i2c_client *client = v4l2_get_subdevdata(sd);
686 u8 val;
687
688 switch (ctrl->id) {
689 case V4L2_CID_VFLIP:
690 val = ctrl->val ? REG04_VFLIP_IMG : 0x00;
691 return ov2640_mask_set(client, REG04, REG04_VFLIP_IMG, val);
692 case V4L2_CID_HFLIP:
693 val = ctrl->val ? REG04_HFLIP_IMG : 0x00;
694 return ov2640_mask_set(client, REG04, REG04_HFLIP_IMG, val);
695 }
696
697 return -EINVAL;
698}
699
700static int ov2640_g_chip_ident(struct v4l2_subdev *sd,
701 struct v4l2_dbg_chip_ident *id)
702{
703 struct i2c_client *client = v4l2_get_subdevdata(sd);
704 struct ov2640_priv *priv = to_ov2640(client);
705
706 id->ident = priv->model;
707 id->revision = 0;
708
709 return 0;
710}
711
712#ifdef CONFIG_VIDEO_ADV_DEBUG
713static int ov2640_g_register(struct v4l2_subdev *sd,
714 struct v4l2_dbg_register *reg)
715{
716 struct i2c_client *client = v4l2_get_subdevdata(sd);
717 int ret;
718
719 reg->size = 1;
720 if (reg->reg > 0xff)
721 return -EINVAL;
722
723 ret = i2c_smbus_read_byte_data(client, reg->reg);
724 if (ret < 0)
725 return ret;
726
727 reg->val = ret;
728
729 return 0;
730}
731
732static int ov2640_s_register(struct v4l2_subdev *sd,
733 struct v4l2_dbg_register *reg)
734{
735 struct i2c_client *client = v4l2_get_subdevdata(sd);
736
737 if (reg->reg > 0xff ||
738 reg->val > 0xff)
739 return -EINVAL;
740
741 return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
742}
743#endif
744
745/* Select the nearest higher resolution for capture */
746static const struct ov2640_win_size *ov2640_select_win(u32 *width, u32 *height)
747{
748 int i, default_size = ARRAY_SIZE(ov2640_supported_win_sizes) - 1;
749
750 for (i = 0; i < ARRAY_SIZE(ov2640_supported_win_sizes); i++) {
751 if (ov2640_supported_win_sizes[i].width >= *width &&
752 ov2640_supported_win_sizes[i].height >= *height) {
753 *width = ov2640_supported_win_sizes[i].width;
754 *height = ov2640_supported_win_sizes[i].height;
755 return &ov2640_supported_win_sizes[i];
756 }
757 }
758
759 *width = ov2640_supported_win_sizes[default_size].width;
760 *height = ov2640_supported_win_sizes[default_size].height;
761 return &ov2640_supported_win_sizes[default_size];
762}
763
764static int ov2640_set_params(struct i2c_client *client, u32 *width, u32 *height,
765 enum v4l2_mbus_pixelcode code)
766{
767 struct ov2640_priv *priv = to_ov2640(client);
768 const struct regval_list *selected_cfmt_regs;
769 int ret;
770
771 /* select win */
772 priv->win = ov2640_select_win(width, height);
773
774 /* select format */
775 priv->cfmt_code = 0;
776 switch (code) {
777 case V4L2_MBUS_FMT_RGB565_2X8_LE:
778 dev_dbg(&client->dev, "%s: Selected cfmt RGB565", __func__);
779 selected_cfmt_regs = ov2640_rgb565_regs;
780 break;
781 default:
782 case V4L2_MBUS_FMT_UYVY8_2X8:
783 dev_dbg(&client->dev, "%s: Selected cfmt YUV422", __func__);
784 selected_cfmt_regs = ov2640_yuv422_regs;
785 }
786
787 /* reset hardware */
788 ov2640_reset(client);
789
790 /* initialize the sensor with default data */
791 dev_dbg(&client->dev, "%s: Init default", __func__);
792 ret = ov2640_write_array(client, ov2640_init_regs);
793 if (ret < 0)
794 goto err;
795
796 /* select preamble */
797 dev_dbg(&client->dev, "%s: Set size to %s", __func__, priv->win->name);
798 ret = ov2640_write_array(client, ov2640_size_change_preamble_regs);
799 if (ret < 0)
800 goto err;
801
802 /* set size win */
803 ret = ov2640_write_array(client, priv->win->regs);
804 if (ret < 0)
805 goto err;
806
807 /* cfmt preamble */
808 dev_dbg(&client->dev, "%s: Set cfmt", __func__);
809 ret = ov2640_write_array(client, ov2640_format_change_preamble_regs);
810 if (ret < 0)
811 goto err;
812
813 /* set cfmt */
814 ret = ov2640_write_array(client, selected_cfmt_regs);
815 if (ret < 0)
816 goto err;
817
818 priv->cfmt_code = code;
819 *width = priv->win->width;
820 *height = priv->win->height;
821
822 return 0;
823
824err:
825 dev_err(&client->dev, "%s: Error %d", __func__, ret);
826 ov2640_reset(client);
827 priv->win = NULL;
828
829 return ret;
830}
831
832static int ov2640_g_fmt(struct v4l2_subdev *sd,
833 struct v4l2_mbus_framefmt *mf)
834{
835 struct i2c_client *client = v4l2_get_subdevdata(sd);
836 struct ov2640_priv *priv = to_ov2640(client);
837
838 if (!priv->win) {
839 u32 width = W_SVGA, height = H_SVGA;
840 priv->win = ov2640_select_win(&width, &height);
841 priv->cfmt_code = V4L2_MBUS_FMT_UYVY8_2X8;
842 }
843
844 mf->width = priv->win->width;
845 mf->height = priv->win->height;
846 mf->code = priv->cfmt_code;
847
848 switch (mf->code) {
849 case V4L2_MBUS_FMT_RGB565_2X8_LE:
850 mf->colorspace = V4L2_COLORSPACE_SRGB;
851 break;
852 default:
853 case V4L2_MBUS_FMT_UYVY8_2X8:
854 mf->colorspace = V4L2_COLORSPACE_JPEG;
855 }
856 mf->field = V4L2_FIELD_NONE;
857
858 return 0;
859}
860
861static int ov2640_s_fmt(struct v4l2_subdev *sd,
862 struct v4l2_mbus_framefmt *mf)
863{
864 struct i2c_client *client = v4l2_get_subdevdata(sd);
865 int ret;
866
867
868 switch (mf->code) {
869 case V4L2_MBUS_FMT_RGB565_2X8_LE:
870 mf->colorspace = V4L2_COLORSPACE_SRGB;
871 break;
872 default:
873 mf->code = V4L2_MBUS_FMT_UYVY8_2X8;
874 case V4L2_MBUS_FMT_UYVY8_2X8:
875 mf->colorspace = V4L2_COLORSPACE_JPEG;
876 }
877
878 ret = ov2640_set_params(client, &mf->width, &mf->height, mf->code);
879
880 return ret;
881}
882
883static int ov2640_try_fmt(struct v4l2_subdev *sd,
884 struct v4l2_mbus_framefmt *mf)
885{
886 const struct ov2640_win_size *win;
887
888 /*
889 * select suitable win
890 */
891 win = ov2640_select_win(&mf->width, &mf->height);
892
893 mf->field = V4L2_FIELD_NONE;
894
895 switch (mf->code) {
896 case V4L2_MBUS_FMT_RGB565_2X8_LE:
897 mf->colorspace = V4L2_COLORSPACE_SRGB;
898 break;
899 default:
900 mf->code = V4L2_MBUS_FMT_UYVY8_2X8;
901 case V4L2_MBUS_FMT_UYVY8_2X8:
902 mf->colorspace = V4L2_COLORSPACE_JPEG;
903 }
904
905 return 0;
906}
907
908static int ov2640_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
909 enum v4l2_mbus_pixelcode *code)
910{
911 if (index >= ARRAY_SIZE(ov2640_codes))
912 return -EINVAL;
913
914 *code = ov2640_codes[index];
915 return 0;
916}
917
918static int ov2640_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
919{
920 a->c.left = 0;
921 a->c.top = 0;
922 a->c.width = W_UXGA;
923 a->c.height = H_UXGA;
924 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
925
926 return 0;
927}
928
929static int ov2640_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
930{
931 a->bounds.left = 0;
932 a->bounds.top = 0;
933 a->bounds.width = W_UXGA;
934 a->bounds.height = H_UXGA;
935 a->defrect = a->bounds;
936 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
937 a->pixelaspect.numerator = 1;
938 a->pixelaspect.denominator = 1;
939
940 return 0;
941}
942
943static int ov2640_video_probe(struct i2c_client *client)
944{
945 struct ov2640_priv *priv = to_ov2640(client);
946 u8 pid, ver, midh, midl;
947 const char *devname;
948 int ret;
949
950 /*
951 * check and show product ID and manufacturer ID
952 */
953 i2c_smbus_write_byte_data(client, BANK_SEL, BANK_SEL_SENS);
954 pid = i2c_smbus_read_byte_data(client, PID);
955 ver = i2c_smbus_read_byte_data(client, VER);
956 midh = i2c_smbus_read_byte_data(client, MIDH);
957 midl = i2c_smbus_read_byte_data(client, MIDL);
958
959 switch (VERSION(pid, ver)) {
960 case PID_OV2640:
961 devname = "ov2640";
962 priv->model = V4L2_IDENT_OV2640;
963 break;
964 default:
965 dev_err(&client->dev,
966 "Product ID error %x:%x\n", pid, ver);
967 ret = -ENODEV;
968 goto err;
969 }
970
971 dev_info(&client->dev,
972 "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
973 devname, pid, ver, midh, midl);
974
975 return v4l2_ctrl_handler_setup(&priv->hdl);
976
977err:
978 return ret;
979}
980
981static const struct v4l2_ctrl_ops ov2640_ctrl_ops = {
982 .s_ctrl = ov2640_s_ctrl,
983};
984
985static struct v4l2_subdev_core_ops ov2640_subdev_core_ops = {
986 .g_chip_ident = ov2640_g_chip_ident,
987#ifdef CONFIG_VIDEO_ADV_DEBUG
988 .g_register = ov2640_g_register,
989 .s_register = ov2640_s_register,
990#endif
991};
992
993static int ov2640_g_mbus_config(struct v4l2_subdev *sd,
994 struct v4l2_mbus_config *cfg)
995{
996 struct i2c_client *client = v4l2_get_subdevdata(sd);
997 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
998
999 cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
1000 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1001 V4L2_MBUS_DATA_ACTIVE_HIGH;
1002 cfg->type = V4L2_MBUS_PARALLEL;
1003 cfg->flags = soc_camera_apply_board_flags(icl, cfg);
1004
1005 return 0;
1006}
1007
1008static struct v4l2_subdev_video_ops ov2640_subdev_video_ops = {
1009 .s_stream = ov2640_s_stream,
1010 .g_mbus_fmt = ov2640_g_fmt,
1011 .s_mbus_fmt = ov2640_s_fmt,
1012 .try_mbus_fmt = ov2640_try_fmt,
1013 .cropcap = ov2640_cropcap,
1014 .g_crop = ov2640_g_crop,
1015 .enum_mbus_fmt = ov2640_enum_fmt,
1016 .g_mbus_config = ov2640_g_mbus_config,
1017};
1018
1019static struct v4l2_subdev_ops ov2640_subdev_ops = {
1020 .core = &ov2640_subdev_core_ops,
1021 .video = &ov2640_subdev_video_ops,
1022};
1023
1024/*
1025 * i2c_driver functions
1026 */
1027static int ov2640_probe(struct i2c_client *client,
1028 const struct i2c_device_id *did)
1029{
1030 struct ov2640_priv *priv;
1031 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
1032 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
1033 int ret;
1034
1035 if (!icl) {
1036 dev_err(&adapter->dev,
1037 "OV2640: Missing platform_data for driver\n");
1038 return -EINVAL;
1039 }
1040
1041 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
1042 dev_err(&adapter->dev,
1043 "OV2640: I2C-Adapter doesn't support SMBUS\n");
1044 return -EIO;
1045 }
1046
1047 priv = kzalloc(sizeof(struct ov2640_priv), GFP_KERNEL);
1048 if (!priv) {
1049 dev_err(&adapter->dev,
1050 "Failed to allocate memory for private data!\n");
1051 return -ENOMEM;
1052 }
1053
1054 v4l2_i2c_subdev_init(&priv->subdev, client, &ov2640_subdev_ops);
1055 v4l2_ctrl_handler_init(&priv->hdl, 2);
1056 v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops,
1057 V4L2_CID_VFLIP, 0, 1, 1, 0);
1058 v4l2_ctrl_new_std(&priv->hdl, &ov2640_ctrl_ops,
1059 V4L2_CID_HFLIP, 0, 1, 1, 0);
1060 priv->subdev.ctrl_handler = &priv->hdl;
1061 if (priv->hdl.error) {
1062 int err = priv->hdl.error;
1063
1064 kfree(priv);
1065 return err;
1066 }
1067
1068 ret = ov2640_video_probe(client);
1069 if (ret) {
1070 v4l2_ctrl_handler_free(&priv->hdl);
1071 kfree(priv);
1072 } else {
1073 dev_info(&adapter->dev, "OV2640 Probed\n");
1074 }
1075
1076 return ret;
1077}
1078
1079static int ov2640_remove(struct i2c_client *client)
1080{
1081 struct ov2640_priv *priv = to_ov2640(client);
1082
1083 v4l2_device_unregister_subdev(&priv->subdev);
1084 v4l2_ctrl_handler_free(&priv->hdl);
1085 kfree(priv);
1086 return 0;
1087}
1088
1089static const struct i2c_device_id ov2640_id[] = {
1090 { "ov2640", 0 },
1091 { }
1092};
1093MODULE_DEVICE_TABLE(i2c, ov2640_id);
1094
1095static struct i2c_driver ov2640_i2c_driver = {
1096 .driver = {
1097 .name = "ov2640",
1098 },
1099 .probe = ov2640_probe,
1100 .remove = ov2640_remove,
1101 .id_table = ov2640_id,
1102};
1103
1104module_i2c_driver(ov2640_i2c_driver);
1105
1106MODULE_DESCRIPTION("SoC Camera driver for Omni Vision 2640 sensor");
1107MODULE_AUTHOR("Alberto Panizzo");
1108MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/video/ov5642.c b/drivers/media/video/ov5642.c
deleted file mode 100644
index 0bc93313d37a..000000000000
--- a/drivers/media/video/ov5642.c
+++ /dev/null
@@ -1,1073 +0,0 @@
1/*
2 * Driver for OV5642 CMOS Image Sensor from Omnivision
3 *
4 * Copyright (C) 2011, Bastian Hecht <hechtb@gmail.com>
5 *
6 * Based on Sony IMX074 Camera Driver
7 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
8 *
9 * Based on Omnivision OV7670 Camera Driver
10 * Copyright (C) 2006-7 Jonathan Corbet <corbet@lwn.net>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/bitops.h>
18#include <linux/delay.h>
19#include <linux/i2c.h>
20#include <linux/kernel.h>
21#include <linux/slab.h>
22#include <linux/videodev2.h>
23#include <linux/module.h>
24#include <linux/v4l2-mediabus.h>
25
26#include <media/soc_camera.h>
27#include <media/v4l2-chip-ident.h>
28#include <media/v4l2-subdev.h>
29
30/* OV5642 registers */
31#define REG_CHIP_ID_HIGH 0x300a
32#define REG_CHIP_ID_LOW 0x300b
33
34#define REG_WINDOW_START_X_HIGH 0x3800
35#define REG_WINDOW_START_X_LOW 0x3801
36#define REG_WINDOW_START_Y_HIGH 0x3802
37#define REG_WINDOW_START_Y_LOW 0x3803
38#define REG_WINDOW_WIDTH_HIGH 0x3804
39#define REG_WINDOW_WIDTH_LOW 0x3805
40#define REG_WINDOW_HEIGHT_HIGH 0x3806
41#define REG_WINDOW_HEIGHT_LOW 0x3807
42#define REG_OUT_WIDTH_HIGH 0x3808
43#define REG_OUT_WIDTH_LOW 0x3809
44#define REG_OUT_HEIGHT_HIGH 0x380a
45#define REG_OUT_HEIGHT_LOW 0x380b
46#define REG_OUT_TOTAL_WIDTH_HIGH 0x380c
47#define REG_OUT_TOTAL_WIDTH_LOW 0x380d
48#define REG_OUT_TOTAL_HEIGHT_HIGH 0x380e
49#define REG_OUT_TOTAL_HEIGHT_LOW 0x380f
50#define REG_OUTPUT_FORMAT 0x4300
51#define REG_ISP_CTRL_01 0x5001
52#define REG_AVG_WINDOW_END_X_HIGH 0x5682
53#define REG_AVG_WINDOW_END_X_LOW 0x5683
54#define REG_AVG_WINDOW_END_Y_HIGH 0x5686
55#define REG_AVG_WINDOW_END_Y_LOW 0x5687
56
57/* active pixel array size */
58#define OV5642_SENSOR_SIZE_X 2592
59#define OV5642_SENSOR_SIZE_Y 1944
60
61/*
62 * About OV5642 resolution, cropping and binning:
63 * This sensor supports it all, at least in the feature description.
64 * Unfortunately, no combination of appropriate registers settings could make
65 * the chip work the intended way. As it works with predefined register lists,
66 * some undocumented registers are presumably changed there to achieve their
67 * goals.
68 * This driver currently only works for resolutions up to 720 lines with a
69 * 1:1 scale. Hopefully these restrictions will be removed in the future.
70 */
71#define OV5642_MAX_WIDTH OV5642_SENSOR_SIZE_X
72#define OV5642_MAX_HEIGHT 720
73
74/* default sizes */
75#define OV5642_DEFAULT_WIDTH 1280
76#define OV5642_DEFAULT_HEIGHT OV5642_MAX_HEIGHT
77
78/* minimum extra blanking */
79#define BLANKING_EXTRA_WIDTH 500
80#define BLANKING_EXTRA_HEIGHT 20
81
82/*
83 * the sensor's autoexposure is buggy when setting total_height low.
84 * It tries to expose longer than 1 frame period without taking care of it
85 * and this leads to weird output. So we set 1000 lines as minimum.
86 */
87#define BLANKING_MIN_HEIGHT 1000
88
89struct regval_list {
90 u16 reg_num;
91 u8 value;
92};
93
94static struct regval_list ov5642_default_regs_init[] = {
95 { 0x3103, 0x93 },
96 { 0x3008, 0x82 },
97 { 0x3017, 0x7f },
98 { 0x3018, 0xfc },
99 { 0x3810, 0xc2 },
100 { 0x3615, 0xf0 },
101 { 0x3000, 0x0 },
102 { 0x3001, 0x0 },
103 { 0x3002, 0x0 },
104 { 0x3003, 0x0 },
105 { 0x3004, 0xff },
106 { 0x3030, 0x2b },
107 { 0x3011, 0x8 },
108 { 0x3010, 0x10 },
109 { 0x3604, 0x60 },
110 { 0x3622, 0x60 },
111 { 0x3621, 0x9 },
112 { 0x3709, 0x0 },
113 { 0x4000, 0x21 },
114 { 0x401d, 0x22 },
115 { 0x3600, 0x54 },
116 { 0x3605, 0x4 },
117 { 0x3606, 0x3f },
118 { 0x3c01, 0x80 },
119 { 0x300d, 0x22 },
120 { 0x3623, 0x22 },
121 { 0x5000, 0x4f },
122 { 0x5020, 0x4 },
123 { 0x5181, 0x79 },
124 { 0x5182, 0x0 },
125 { 0x5185, 0x22 },
126 { 0x5197, 0x1 },
127 { 0x5500, 0xa },
128 { 0x5504, 0x0 },
129 { 0x5505, 0x7f },
130 { 0x5080, 0x8 },
131 { 0x300e, 0x18 },
132 { 0x4610, 0x0 },
133 { 0x471d, 0x5 },
134 { 0x4708, 0x6 },
135 { 0x370c, 0xa0 },
136 { 0x5687, 0x94 },
137 { 0x501f, 0x0 },
138 { 0x5000, 0x4f },
139 { 0x5001, 0xcf },
140 { 0x4300, 0x30 },
141 { 0x4300, 0x30 },
142 { 0x460b, 0x35 },
143 { 0x471d, 0x0 },
144 { 0x3002, 0xc },
145 { 0x3002, 0x0 },
146 { 0x4713, 0x3 },
147 { 0x471c, 0x50 },
148 { 0x4721, 0x2 },
149 { 0x4402, 0x90 },
150 { 0x460c, 0x22 },
151 { 0x3815, 0x44 },
152 { 0x3503, 0x7 },
153 { 0x3501, 0x73 },
154 { 0x3502, 0x80 },
155 { 0x350b, 0x0 },
156 { 0x3818, 0xc8 },
157 { 0x3824, 0x11 },
158 { 0x3a00, 0x78 },
159 { 0x3a1a, 0x4 },
160 { 0x3a13, 0x30 },
161 { 0x3a18, 0x0 },
162 { 0x3a19, 0x7c },
163 { 0x3a08, 0x12 },
164 { 0x3a09, 0xc0 },
165 { 0x3a0a, 0xf },
166 { 0x3a0b, 0xa0 },
167 { 0x350c, 0x7 },
168 { 0x350d, 0xd0 },
169 { 0x3a0d, 0x8 },
170 { 0x3a0e, 0x6 },
171 { 0x3500, 0x0 },
172 { 0x3501, 0x0 },
173 { 0x3502, 0x0 },
174 { 0x350a, 0x0 },
175 { 0x350b, 0x0 },
176 { 0x3503, 0x0 },
177 { 0x3a0f, 0x3c },
178 { 0x3a10, 0x32 },
179 { 0x3a1b, 0x3c },
180 { 0x3a1e, 0x32 },
181 { 0x3a11, 0x80 },
182 { 0x3a1f, 0x20 },
183 { 0x3030, 0x2b },
184 { 0x3a02, 0x0 },
185 { 0x3a03, 0x7d },
186 { 0x3a04, 0x0 },
187 { 0x3a14, 0x0 },
188 { 0x3a15, 0x7d },
189 { 0x3a16, 0x0 },
190 { 0x3a00, 0x78 },
191 { 0x3a08, 0x9 },
192 { 0x3a09, 0x60 },
193 { 0x3a0a, 0x7 },
194 { 0x3a0b, 0xd0 },
195 { 0x3a0d, 0x10 },
196 { 0x3a0e, 0xd },
197 { 0x4407, 0x4 },
198 { 0x5193, 0x70 },
199 { 0x589b, 0x0 },
200 { 0x589a, 0xc0 },
201 { 0x401e, 0x20 },
202 { 0x4001, 0x42 },
203 { 0x401c, 0x6 },
204 { 0x3825, 0xac },
205 { 0x3827, 0xc },
206 { 0x528a, 0x1 },
207 { 0x528b, 0x4 },
208 { 0x528c, 0x8 },
209 { 0x528d, 0x10 },
210 { 0x528e, 0x20 },
211 { 0x528f, 0x28 },
212 { 0x5290, 0x30 },
213 { 0x5292, 0x0 },
214 { 0x5293, 0x1 },
215 { 0x5294, 0x0 },
216 { 0x5295, 0x4 },
217 { 0x5296, 0x0 },
218 { 0x5297, 0x8 },
219 { 0x5298, 0x0 },
220 { 0x5299, 0x10 },
221 { 0x529a, 0x0 },
222 { 0x529b, 0x20 },
223 { 0x529c, 0x0 },
224 { 0x529d, 0x28 },
225 { 0x529e, 0x0 },
226 { 0x529f, 0x30 },
227 { 0x5282, 0x0 },
228 { 0x5300, 0x0 },
229 { 0x5301, 0x20 },
230 { 0x5302, 0x0 },
231 { 0x5303, 0x7c },
232 { 0x530c, 0x0 },
233 { 0x530d, 0xc },
234 { 0x530e, 0x20 },
235 { 0x530f, 0x80 },
236 { 0x5310, 0x20 },
237 { 0x5311, 0x80 },
238 { 0x5308, 0x20 },
239 { 0x5309, 0x40 },
240 { 0x5304, 0x0 },
241 { 0x5305, 0x30 },
242 { 0x5306, 0x0 },
243 { 0x5307, 0x80 },
244 { 0x5314, 0x8 },
245 { 0x5315, 0x20 },
246 { 0x5319, 0x30 },
247 { 0x5316, 0x10 },
248 { 0x5317, 0x0 },
249 { 0x5318, 0x2 },
250 { 0x5380, 0x1 },
251 { 0x5381, 0x0 },
252 { 0x5382, 0x0 },
253 { 0x5383, 0x4e },
254 { 0x5384, 0x0 },
255 { 0x5385, 0xf },
256 { 0x5386, 0x0 },
257 { 0x5387, 0x0 },
258 { 0x5388, 0x1 },
259 { 0x5389, 0x15 },
260 { 0x538a, 0x0 },
261 { 0x538b, 0x31 },
262 { 0x538c, 0x0 },
263 { 0x538d, 0x0 },
264 { 0x538e, 0x0 },
265 { 0x538f, 0xf },
266 { 0x5390, 0x0 },
267 { 0x5391, 0xab },
268 { 0x5392, 0x0 },
269 { 0x5393, 0xa2 },
270 { 0x5394, 0x8 },
271 { 0x5480, 0x14 },
272 { 0x5481, 0x21 },
273 { 0x5482, 0x36 },
274 { 0x5483, 0x57 },
275 { 0x5484, 0x65 },
276 { 0x5485, 0x71 },
277 { 0x5486, 0x7d },
278 { 0x5487, 0x87 },
279 { 0x5488, 0x91 },
280 { 0x5489, 0x9a },
281 { 0x548a, 0xaa },
282 { 0x548b, 0xb8 },
283 { 0x548c, 0xcd },
284 { 0x548d, 0xdd },
285 { 0x548e, 0xea },
286 { 0x548f, 0x1d },
287 { 0x5490, 0x5 },
288 { 0x5491, 0x0 },
289 { 0x5492, 0x4 },
290 { 0x5493, 0x20 },
291 { 0x5494, 0x3 },
292 { 0x5495, 0x60 },
293 { 0x5496, 0x2 },
294 { 0x5497, 0xb8 },
295 { 0x5498, 0x2 },
296 { 0x5499, 0x86 },
297 { 0x549a, 0x2 },
298 { 0x549b, 0x5b },
299 { 0x549c, 0x2 },
300 { 0x549d, 0x3b },
301 { 0x549e, 0x2 },
302 { 0x549f, 0x1c },
303 { 0x54a0, 0x2 },
304 { 0x54a1, 0x4 },
305 { 0x54a2, 0x1 },
306 { 0x54a3, 0xed },
307 { 0x54a4, 0x1 },
308 { 0x54a5, 0xc5 },
309 { 0x54a6, 0x1 },
310 { 0x54a7, 0xa5 },
311 { 0x54a8, 0x1 },
312 { 0x54a9, 0x6c },
313 { 0x54aa, 0x1 },
314 { 0x54ab, 0x41 },
315 { 0x54ac, 0x1 },
316 { 0x54ad, 0x20 },
317 { 0x54ae, 0x0 },
318 { 0x54af, 0x16 },
319 { 0x54b0, 0x1 },
320 { 0x54b1, 0x20 },
321 { 0x54b2, 0x0 },
322 { 0x54b3, 0x10 },
323 { 0x54b4, 0x0 },
324 { 0x54b5, 0xf0 },
325 { 0x54b6, 0x0 },
326 { 0x54b7, 0xdf },
327 { 0x5402, 0x3f },
328 { 0x5403, 0x0 },
329 { 0x3406, 0x0 },
330 { 0x5180, 0xff },
331 { 0x5181, 0x52 },
332 { 0x5182, 0x11 },
333 { 0x5183, 0x14 },
334 { 0x5184, 0x25 },
335 { 0x5185, 0x24 },
336 { 0x5186, 0x6 },
337 { 0x5187, 0x8 },
338 { 0x5188, 0x8 },
339 { 0x5189, 0x7c },
340 { 0x518a, 0x60 },
341 { 0x518b, 0xb2 },
342 { 0x518c, 0xb2 },
343 { 0x518d, 0x44 },
344 { 0x518e, 0x3d },
345 { 0x518f, 0x58 },
346 { 0x5190, 0x46 },
347 { 0x5191, 0xf8 },
348 { 0x5192, 0x4 },
349 { 0x5193, 0x70 },
350 { 0x5194, 0xf0 },
351 { 0x5195, 0xf0 },
352 { 0x5196, 0x3 },
353 { 0x5197, 0x1 },
354 { 0x5198, 0x4 },
355 { 0x5199, 0x12 },
356 { 0x519a, 0x4 },
357 { 0x519b, 0x0 },
358 { 0x519c, 0x6 },
359 { 0x519d, 0x82 },
360 { 0x519e, 0x0 },
361 { 0x5025, 0x80 },
362 { 0x3a0f, 0x38 },
363 { 0x3a10, 0x30 },
364 { 0x3a1b, 0x3a },
365 { 0x3a1e, 0x2e },
366 { 0x3a11, 0x60 },
367 { 0x3a1f, 0x10 },
368 { 0x5688, 0xa6 },
369 { 0x5689, 0x6a },
370 { 0x568a, 0xea },
371 { 0x568b, 0xae },
372 { 0x568c, 0xa6 },
373 { 0x568d, 0x6a },
374 { 0x568e, 0x62 },
375 { 0x568f, 0x26 },
376 { 0x5583, 0x40 },
377 { 0x5584, 0x40 },
378 { 0x5580, 0x2 },
379 { 0x5000, 0xcf },
380 { 0x5800, 0x27 },
381 { 0x5801, 0x19 },
382 { 0x5802, 0x12 },
383 { 0x5803, 0xf },
384 { 0x5804, 0x10 },
385 { 0x5805, 0x15 },
386 { 0x5806, 0x1e },
387 { 0x5807, 0x2f },
388 { 0x5808, 0x15 },
389 { 0x5809, 0xd },
390 { 0x580a, 0xa },
391 { 0x580b, 0x9 },
392 { 0x580c, 0xa },
393 { 0x580d, 0xc },
394 { 0x580e, 0x12 },
395 { 0x580f, 0x19 },
396 { 0x5810, 0xb },
397 { 0x5811, 0x7 },
398 { 0x5812, 0x4 },
399 { 0x5813, 0x3 },
400 { 0x5814, 0x3 },
401 { 0x5815, 0x6 },
402 { 0x5816, 0xa },
403 { 0x5817, 0xf },
404 { 0x5818, 0xa },
405 { 0x5819, 0x5 },
406 { 0x581a, 0x1 },
407 { 0x581b, 0x0 },
408 { 0x581c, 0x0 },
409 { 0x581d, 0x3 },
410 { 0x581e, 0x8 },
411 { 0x581f, 0xc },
412 { 0x5820, 0xa },
413 { 0x5821, 0x5 },
414 { 0x5822, 0x1 },
415 { 0x5823, 0x0 },
416 { 0x5824, 0x0 },
417 { 0x5825, 0x3 },
418 { 0x5826, 0x8 },
419 { 0x5827, 0xc },
420 { 0x5828, 0xe },
421 { 0x5829, 0x8 },
422 { 0x582a, 0x6 },
423 { 0x582b, 0x4 },
424 { 0x582c, 0x5 },
425 { 0x582d, 0x7 },
426 { 0x582e, 0xb },
427 { 0x582f, 0x12 },
428 { 0x5830, 0x18 },
429 { 0x5831, 0x10 },
430 { 0x5832, 0xc },
431 { 0x5833, 0xa },
432 { 0x5834, 0xb },
433 { 0x5835, 0xe },
434 { 0x5836, 0x15 },
435 { 0x5837, 0x19 },
436 { 0x5838, 0x32 },
437 { 0x5839, 0x1f },
438 { 0x583a, 0x18 },
439 { 0x583b, 0x16 },
440 { 0x583c, 0x17 },
441 { 0x583d, 0x1e },
442 { 0x583e, 0x26 },
443 { 0x583f, 0x53 },
444 { 0x5840, 0x10 },
445 { 0x5841, 0xf },
446 { 0x5842, 0xd },
447 { 0x5843, 0xc },
448 { 0x5844, 0xe },
449 { 0x5845, 0x9 },
450 { 0x5846, 0x11 },
451 { 0x5847, 0x10 },
452 { 0x5848, 0x10 },
453 { 0x5849, 0x10 },
454 { 0x584a, 0x10 },
455 { 0x584b, 0xe },
456 { 0x584c, 0x10 },
457 { 0x584d, 0x10 },
458 { 0x584e, 0x11 },
459 { 0x584f, 0x10 },
460 { 0x5850, 0xf },
461 { 0x5851, 0xc },
462 { 0x5852, 0xf },
463 { 0x5853, 0x10 },
464 { 0x5854, 0x10 },
465 { 0x5855, 0xf },
466 { 0x5856, 0xe },
467 { 0x5857, 0xb },
468 { 0x5858, 0x10 },
469 { 0x5859, 0xd },
470 { 0x585a, 0xd },
471 { 0x585b, 0xc },
472 { 0x585c, 0xc },
473 { 0x585d, 0xc },
474 { 0x585e, 0xb },
475 { 0x585f, 0xc },
476 { 0x5860, 0xc },
477 { 0x5861, 0xc },
478 { 0x5862, 0xd },
479 { 0x5863, 0x8 },
480 { 0x5864, 0x11 },
481 { 0x5865, 0x18 },
482 { 0x5866, 0x18 },
483 { 0x5867, 0x19 },
484 { 0x5868, 0x17 },
485 { 0x5869, 0x19 },
486 { 0x586a, 0x16 },
487 { 0x586b, 0x13 },
488 { 0x586c, 0x13 },
489 { 0x586d, 0x12 },
490 { 0x586e, 0x13 },
491 { 0x586f, 0x16 },
492 { 0x5870, 0x14 },
493 { 0x5871, 0x12 },
494 { 0x5872, 0x10 },
495 { 0x5873, 0x11 },
496 { 0x5874, 0x11 },
497 { 0x5875, 0x16 },
498 { 0x5876, 0x14 },
499 { 0x5877, 0x11 },
500 { 0x5878, 0x10 },
501 { 0x5879, 0xf },
502 { 0x587a, 0x10 },
503 { 0x587b, 0x14 },
504 { 0x587c, 0x13 },
505 { 0x587d, 0x12 },
506 { 0x587e, 0x11 },
507 { 0x587f, 0x11 },
508 { 0x5880, 0x12 },
509 { 0x5881, 0x15 },
510 { 0x5882, 0x14 },
511 { 0x5883, 0x15 },
512 { 0x5884, 0x15 },
513 { 0x5885, 0x15 },
514 { 0x5886, 0x13 },
515 { 0x5887, 0x17 },
516 { 0x3710, 0x10 },
517 { 0x3632, 0x51 },
518 { 0x3702, 0x10 },
519 { 0x3703, 0xb2 },
520 { 0x3704, 0x18 },
521 { 0x370b, 0x40 },
522 { 0x370d, 0x3 },
523 { 0x3631, 0x1 },
524 { 0x3632, 0x52 },
525 { 0x3606, 0x24 },
526 { 0x3620, 0x96 },
527 { 0x5785, 0x7 },
528 { 0x3a13, 0x30 },
529 { 0x3600, 0x52 },
530 { 0x3604, 0x48 },
531 { 0x3606, 0x1b },
532 { 0x370d, 0xb },
533 { 0x370f, 0xc0 },
534 { 0x3709, 0x1 },
535 { 0x3823, 0x0 },
536 { 0x5007, 0x0 },
537 { 0x5009, 0x0 },
538 { 0x5011, 0x0 },
539 { 0x5013, 0x0 },
540 { 0x519e, 0x0 },
541 { 0x5086, 0x0 },
542 { 0x5087, 0x0 },
543 { 0x5088, 0x0 },
544 { 0x5089, 0x0 },
545 { 0x302b, 0x0 },
546 { 0x3503, 0x7 },
547 { 0x3011, 0x8 },
548 { 0x350c, 0x2 },
549 { 0x350d, 0xe4 },
550 { 0x3621, 0xc9 },
551 { 0x370a, 0x81 },
552 { 0xffff, 0xff },
553};
554
555static struct regval_list ov5642_default_regs_finalise[] = {
556 { 0x3810, 0xc2 },
557 { 0x3818, 0xc9 },
558 { 0x381c, 0x10 },
559 { 0x381d, 0xa0 },
560 { 0x381e, 0x5 },
561 { 0x381f, 0xb0 },
562 { 0x3820, 0x0 },
563 { 0x3821, 0x0 },
564 { 0x3824, 0x11 },
565 { 0x3a08, 0x1b },
566 { 0x3a09, 0xc0 },
567 { 0x3a0a, 0x17 },
568 { 0x3a0b, 0x20 },
569 { 0x3a0d, 0x2 },
570 { 0x3a0e, 0x1 },
571 { 0x401c, 0x4 },
572 { 0x5682, 0x5 },
573 { 0x5683, 0x0 },
574 { 0x5686, 0x2 },
575 { 0x5687, 0xcc },
576 { 0x5001, 0x4f },
577 { 0x589b, 0x6 },
578 { 0x589a, 0xc5 },
579 { 0x3503, 0x0 },
580 { 0x460c, 0x20 },
581 { 0x460b, 0x37 },
582 { 0x471c, 0xd0 },
583 { 0x471d, 0x5 },
584 { 0x3815, 0x1 },
585 { 0x3818, 0xc1 },
586 { 0x501f, 0x0 },
587 { 0x5002, 0xe0 },
588 { 0x4300, 0x32 }, /* UYVY */
589 { 0x3002, 0x1c },
590 { 0x4800, 0x14 },
591 { 0x4801, 0xf },
592 { 0x3007, 0x3b },
593 { 0x300e, 0x4 },
594 { 0x4803, 0x50 },
595 { 0x3815, 0x1 },
596 { 0x4713, 0x2 },
597 { 0x4842, 0x1 },
598 { 0x300f, 0xe },
599 { 0x3003, 0x3 },
600 { 0x3003, 0x1 },
601 { 0xffff, 0xff },
602};
603
604struct ov5642_datafmt {
605 enum v4l2_mbus_pixelcode code;
606 enum v4l2_colorspace colorspace;
607};
608
609struct ov5642 {
610 struct v4l2_subdev subdev;
611 const struct ov5642_datafmt *fmt;
612 struct v4l2_rect crop_rect;
613
614 /* blanking information */
615 int total_width;
616 int total_height;
617};
618
619static const struct ov5642_datafmt ov5642_colour_fmts[] = {
620 {V4L2_MBUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_JPEG},
621};
622
623static struct ov5642 *to_ov5642(const struct i2c_client *client)
624{
625 return container_of(i2c_get_clientdata(client), struct ov5642, subdev);
626}
627
628/* Find a data format by a pixel code in an array */
629static const struct ov5642_datafmt
630 *ov5642_find_datafmt(enum v4l2_mbus_pixelcode code)
631{
632 int i;
633
634 for (i = 0; i < ARRAY_SIZE(ov5642_colour_fmts); i++)
635 if (ov5642_colour_fmts[i].code == code)
636 return ov5642_colour_fmts + i;
637
638 return NULL;
639}
640
641static int reg_read(struct i2c_client *client, u16 reg, u8 *val)
642{
643 int ret;
644 /* We have 16-bit i2c addresses - care for endianess */
645 unsigned char data[2] = { reg >> 8, reg & 0xff };
646
647 ret = i2c_master_send(client, data, 2);
648 if (ret < 2) {
649 dev_err(&client->dev, "%s: i2c read error, reg: %x\n",
650 __func__, reg);
651 return ret < 0 ? ret : -EIO;
652 }
653
654 ret = i2c_master_recv(client, val, 1);
655 if (ret < 1) {
656 dev_err(&client->dev, "%s: i2c read error, reg: %x\n",
657 __func__, reg);
658 return ret < 0 ? ret : -EIO;
659 }
660 return 0;
661}
662
663static int reg_write(struct i2c_client *client, u16 reg, u8 val)
664{
665 int ret;
666 unsigned char data[3] = { reg >> 8, reg & 0xff, val };
667
668 ret = i2c_master_send(client, data, 3);
669 if (ret < 3) {
670 dev_err(&client->dev, "%s: i2c write error, reg: %x\n",
671 __func__, reg);
672 return ret < 0 ? ret : -EIO;
673 }
674
675 return 0;
676}
677
678/*
679 * convenience function to write 16 bit register values that are split up
680 * into two consecutive high and low parts
681 */
682static int reg_write16(struct i2c_client *client, u16 reg, u16 val16)
683{
684 int ret;
685
686 ret = reg_write(client, reg, val16 >> 8);
687 if (ret)
688 return ret;
689 return reg_write(client, reg + 1, val16 & 0x00ff);
690}
691
692#ifdef CONFIG_VIDEO_ADV_DEBUG
693static int ov5642_get_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
694{
695 struct i2c_client *client = v4l2_get_subdevdata(sd);
696 int ret;
697 u8 val;
698
699 if (reg->reg & ~0xffff)
700 return -EINVAL;
701
702 reg->size = 1;
703
704 ret = reg_read(client, reg->reg, &val);
705 if (!ret)
706 reg->val = (__u64)val;
707
708 return ret;
709}
710
711static int ov5642_set_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
712{
713 struct i2c_client *client = v4l2_get_subdevdata(sd);
714
715 if (reg->reg & ~0xffff || reg->val & ~0xff)
716 return -EINVAL;
717
718 return reg_write(client, reg->reg, reg->val);
719}
720#endif
721
722static int ov5642_write_array(struct i2c_client *client,
723 struct regval_list *vals)
724{
725 while (vals->reg_num != 0xffff || vals->value != 0xff) {
726 int ret = reg_write(client, vals->reg_num, vals->value);
727 if (ret < 0)
728 return ret;
729 vals++;
730 }
731 dev_dbg(&client->dev, "Register list loaded\n");
732 return 0;
733}
734
735static int ov5642_set_resolution(struct v4l2_subdev *sd)
736{
737 struct i2c_client *client = v4l2_get_subdevdata(sd);
738 struct ov5642 *priv = to_ov5642(client);
739 int width = priv->crop_rect.width;
740 int height = priv->crop_rect.height;
741 int total_width = priv->total_width;
742 int total_height = priv->total_height;
743 int start_x = (OV5642_SENSOR_SIZE_X - width) / 2;
744 int start_y = (OV5642_SENSOR_SIZE_Y - height) / 2;
745 int ret;
746
747 /*
748 * This should set the starting point for cropping.
749 * Doesn't work so far.
750 */
751 ret = reg_write16(client, REG_WINDOW_START_X_HIGH, start_x);
752 if (!ret)
753 ret = reg_write16(client, REG_WINDOW_START_Y_HIGH, start_y);
754 if (!ret) {
755 priv->crop_rect.left = start_x;
756 priv->crop_rect.top = start_y;
757 }
758
759 if (!ret)
760 ret = reg_write16(client, REG_WINDOW_WIDTH_HIGH, width);
761 if (!ret)
762 ret = reg_write16(client, REG_WINDOW_HEIGHT_HIGH, height);
763 if (ret)
764 return ret;
765 priv->crop_rect.width = width;
766 priv->crop_rect.height = height;
767
768 /* Set the output window size. Only 1:1 scale is supported so far. */
769 ret = reg_write16(client, REG_OUT_WIDTH_HIGH, width);
770 if (!ret)
771 ret = reg_write16(client, REG_OUT_HEIGHT_HIGH, height);
772
773 /* Total width = output size + blanking */
774 if (!ret)
775 ret = reg_write16(client, REG_OUT_TOTAL_WIDTH_HIGH, total_width);
776 if (!ret)
777 ret = reg_write16(client, REG_OUT_TOTAL_HEIGHT_HIGH, total_height);
778
779 /* Sets the window for AWB calculations */
780 if (!ret)
781 ret = reg_write16(client, REG_AVG_WINDOW_END_X_HIGH, width);
782 if (!ret)
783 ret = reg_write16(client, REG_AVG_WINDOW_END_Y_HIGH, height);
784
785 return ret;
786}
787
788static int ov5642_try_fmt(struct v4l2_subdev *sd,
789 struct v4l2_mbus_framefmt *mf)
790{
791 struct i2c_client *client = v4l2_get_subdevdata(sd);
792 struct ov5642 *priv = to_ov5642(client);
793 const struct ov5642_datafmt *fmt = ov5642_find_datafmt(mf->code);
794
795 mf->width = priv->crop_rect.width;
796 mf->height = priv->crop_rect.height;
797
798 if (!fmt) {
799 mf->code = ov5642_colour_fmts[0].code;
800 mf->colorspace = ov5642_colour_fmts[0].colorspace;
801 }
802
803 mf->field = V4L2_FIELD_NONE;
804
805 return 0;
806}
807
808static int ov5642_s_fmt(struct v4l2_subdev *sd,
809 struct v4l2_mbus_framefmt *mf)
810{
811 struct i2c_client *client = v4l2_get_subdevdata(sd);
812 struct ov5642 *priv = to_ov5642(client);
813
814 /* MIPI CSI could have changed the format, double-check */
815 if (!ov5642_find_datafmt(mf->code))
816 return -EINVAL;
817
818 ov5642_try_fmt(sd, mf);
819 priv->fmt = ov5642_find_datafmt(mf->code);
820
821 return 0;
822}
823
824static int ov5642_g_fmt(struct v4l2_subdev *sd,
825 struct v4l2_mbus_framefmt *mf)
826{
827 struct i2c_client *client = v4l2_get_subdevdata(sd);
828 struct ov5642 *priv = to_ov5642(client);
829
830 const struct ov5642_datafmt *fmt = priv->fmt;
831
832 mf->code = fmt->code;
833 mf->colorspace = fmt->colorspace;
834 mf->width = priv->crop_rect.width;
835 mf->height = priv->crop_rect.height;
836 mf->field = V4L2_FIELD_NONE;
837
838 return 0;
839}
840
841static int ov5642_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
842 enum v4l2_mbus_pixelcode *code)
843{
844 if (index >= ARRAY_SIZE(ov5642_colour_fmts))
845 return -EINVAL;
846
847 *code = ov5642_colour_fmts[index].code;
848 return 0;
849}
850
851static int ov5642_g_chip_ident(struct v4l2_subdev *sd,
852 struct v4l2_dbg_chip_ident *id)
853{
854 struct i2c_client *client = v4l2_get_subdevdata(sd);
855
856 if (id->match.type != V4L2_CHIP_MATCH_I2C_ADDR)
857 return -EINVAL;
858
859 if (id->match.addr != client->addr)
860 return -ENODEV;
861
862 id->ident = V4L2_IDENT_OV5642;
863 id->revision = 0;
864
865 return 0;
866}
867
868static int ov5642_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
869{
870 struct i2c_client *client = v4l2_get_subdevdata(sd);
871 struct ov5642 *priv = to_ov5642(client);
872 struct v4l2_rect *rect = &a->c;
873 int ret;
874
875 v4l_bound_align_image(&rect->width, 48, OV5642_MAX_WIDTH, 1,
876 &rect->height, 32, OV5642_MAX_HEIGHT, 1, 0);
877
878 priv->crop_rect.width = rect->width;
879 priv->crop_rect.height = rect->height;
880 priv->total_width = rect->width + BLANKING_EXTRA_WIDTH;
881 priv->total_height = max_t(int, rect->height +
882 BLANKING_EXTRA_HEIGHT,
883 BLANKING_MIN_HEIGHT);
884 priv->crop_rect.width = rect->width;
885 priv->crop_rect.height = rect->height;
886
887 ret = ov5642_write_array(client, ov5642_default_regs_init);
888 if (!ret)
889 ret = ov5642_set_resolution(sd);
890 if (!ret)
891 ret = ov5642_write_array(client, ov5642_default_regs_finalise);
892
893 return ret;
894}
895
896static int ov5642_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
897{
898 struct i2c_client *client = v4l2_get_subdevdata(sd);
899 struct ov5642 *priv = to_ov5642(client);
900 struct v4l2_rect *rect = &a->c;
901
902 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
903 return -EINVAL;
904
905 *rect = priv->crop_rect;
906
907 return 0;
908}
909
910static int ov5642_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
911{
912 a->bounds.left = 0;
913 a->bounds.top = 0;
914 a->bounds.width = OV5642_MAX_WIDTH;
915 a->bounds.height = OV5642_MAX_HEIGHT;
916 a->defrect = a->bounds;
917 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
918 a->pixelaspect.numerator = 1;
919 a->pixelaspect.denominator = 1;
920
921 return 0;
922}
923
924static int ov5642_g_mbus_config(struct v4l2_subdev *sd,
925 struct v4l2_mbus_config *cfg)
926{
927 cfg->type = V4L2_MBUS_CSI2;
928 cfg->flags = V4L2_MBUS_CSI2_2_LANE | V4L2_MBUS_CSI2_CHANNEL_0 |
929 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
930
931 return 0;
932}
933
934static int ov5642_s_power(struct v4l2_subdev *sd, int on)
935{
936 struct i2c_client *client;
937 int ret;
938
939 if (!on)
940 return 0;
941
942 client = v4l2_get_subdevdata(sd);
943 ret = ov5642_write_array(client, ov5642_default_regs_init);
944 if (!ret)
945 ret = ov5642_set_resolution(sd);
946 if (!ret)
947 ret = ov5642_write_array(client, ov5642_default_regs_finalise);
948
949 return ret;
950}
951
952static struct v4l2_subdev_video_ops ov5642_subdev_video_ops = {
953 .s_mbus_fmt = ov5642_s_fmt,
954 .g_mbus_fmt = ov5642_g_fmt,
955 .try_mbus_fmt = ov5642_try_fmt,
956 .enum_mbus_fmt = ov5642_enum_fmt,
957 .s_crop = ov5642_s_crop,
958 .g_crop = ov5642_g_crop,
959 .cropcap = ov5642_cropcap,
960 .g_mbus_config = ov5642_g_mbus_config,
961};
962
963static struct v4l2_subdev_core_ops ov5642_subdev_core_ops = {
964 .s_power = ov5642_s_power,
965 .g_chip_ident = ov5642_g_chip_ident,
966#ifdef CONFIG_VIDEO_ADV_DEBUG
967 .g_register = ov5642_get_register,
968 .s_register = ov5642_set_register,
969#endif
970};
971
972static struct v4l2_subdev_ops ov5642_subdev_ops = {
973 .core = &ov5642_subdev_core_ops,
974 .video = &ov5642_subdev_video_ops,
975};
976
977static int ov5642_video_probe(struct i2c_client *client)
978{
979 int ret;
980 u8 id_high, id_low;
981 u16 id;
982
983 /* Read sensor Model ID */
984 ret = reg_read(client, REG_CHIP_ID_HIGH, &id_high);
985 if (ret < 0)
986 return ret;
987
988 id = id_high << 8;
989
990 ret = reg_read(client, REG_CHIP_ID_LOW, &id_low);
991 if (ret < 0)
992 return ret;
993
994 id |= id_low;
995
996 dev_info(&client->dev, "Chip ID 0x%04x detected\n", id);
997
998 if (id != 0x5642)
999 return -ENODEV;
1000
1001 return 0;
1002}
1003
1004static int ov5642_probe(struct i2c_client *client,
1005 const struct i2c_device_id *did)
1006{
1007 struct ov5642 *priv;
1008 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
1009 int ret;
1010
1011 if (!icl) {
1012 dev_err(&client->dev, "OV5642: missing platform data!\n");
1013 return -EINVAL;
1014 }
1015
1016 priv = kzalloc(sizeof(struct ov5642), GFP_KERNEL);
1017 if (!priv)
1018 return -ENOMEM;
1019
1020 v4l2_i2c_subdev_init(&priv->subdev, client, &ov5642_subdev_ops);
1021
1022 priv->fmt = &ov5642_colour_fmts[0];
1023
1024 priv->crop_rect.width = OV5642_DEFAULT_WIDTH;
1025 priv->crop_rect.height = OV5642_DEFAULT_HEIGHT;
1026 priv->crop_rect.left = (OV5642_MAX_WIDTH - OV5642_DEFAULT_WIDTH) / 2;
1027 priv->crop_rect.top = (OV5642_MAX_HEIGHT - OV5642_DEFAULT_HEIGHT) / 2;
1028 priv->total_width = OV5642_DEFAULT_WIDTH + BLANKING_EXTRA_WIDTH;
1029 priv->total_height = BLANKING_MIN_HEIGHT;
1030
1031 ret = ov5642_video_probe(client);
1032 if (ret < 0)
1033 goto error;
1034
1035 return 0;
1036
1037error:
1038 kfree(priv);
1039 return ret;
1040}
1041
1042static int ov5642_remove(struct i2c_client *client)
1043{
1044 struct ov5642 *priv = to_ov5642(client);
1045 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
1046
1047 if (icl->free_bus)
1048 icl->free_bus(icl);
1049 kfree(priv);
1050
1051 return 0;
1052}
1053
1054static const struct i2c_device_id ov5642_id[] = {
1055 { "ov5642", 0 },
1056 { }
1057};
1058MODULE_DEVICE_TABLE(i2c, ov5642_id);
1059
1060static struct i2c_driver ov5642_i2c_driver = {
1061 .driver = {
1062 .name = "ov5642",
1063 },
1064 .probe = ov5642_probe,
1065 .remove = ov5642_remove,
1066 .id_table = ov5642_id,
1067};
1068
1069module_i2c_driver(ov5642_i2c_driver);
1070
1071MODULE_DESCRIPTION("Omnivision OV5642 Camera driver");
1072MODULE_AUTHOR("Bastian Hecht <hechtb@gmail.com>");
1073MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/video/ov6650.c b/drivers/media/video/ov6650.c
deleted file mode 100644
index 3e028b1970dd..000000000000
--- a/drivers/media/video/ov6650.c
+++ /dev/null
@@ -1,1053 +0,0 @@
1/*
2 * V4L2 SoC Camera driver for OmniVision OV6650 Camera Sensor
3 *
4 * Copyright (C) 2010 Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
5 *
6 * Based on OmniVision OV96xx Camera Driver
7 * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
8 *
9 * Based on ov772x camera driver:
10 * Copyright (C) 2008 Renesas Solutions Corp.
11 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
12 *
13 * Based on ov7670 and soc_camera_platform driver,
14 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
15 * Copyright (C) 2008 Magnus Damm
16 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
17 *
18 * Hardware specific bits initialy based on former work by Matt Callow
19 * drivers/media/video/omap/sensor_ov6650.c
20 * Copyright (C) 2006 Matt Callow
21 *
22 * This program is free software; you can redistribute it and/or modify
23 * it under the terms of the GNU General Public License version 2 as
24 * published by the Free Software Foundation.
25 */
26
27#include <linux/bitops.h>
28#include <linux/delay.h>
29#include <linux/i2c.h>
30#include <linux/slab.h>
31#include <linux/v4l2-mediabus.h>
32#include <linux/module.h>
33
34#include <media/soc_camera.h>
35#include <media/v4l2-chip-ident.h>
36#include <media/v4l2-ctrls.h>
37
38/* Register definitions */
39#define REG_GAIN 0x00 /* range 00 - 3F */
40#define REG_BLUE 0x01
41#define REG_RED 0x02
42#define REG_SAT 0x03 /* [7:4] saturation [0:3] reserved */
43#define REG_HUE 0x04 /* [7:6] rsrvd [5] hue en [4:0] hue */
44
45#define REG_BRT 0x06
46
47#define REG_PIDH 0x0a
48#define REG_PIDL 0x0b
49
50#define REG_AECH 0x10
51#define REG_CLKRC 0x11 /* Data Format and Internal Clock */
52 /* [7:6] Input system clock (MHz)*/
53 /* 00=8, 01=12, 10=16, 11=24 */
54 /* [5:0]: Internal Clock Pre-Scaler */
55#define REG_COMA 0x12 /* [7] Reset */
56#define REG_COMB 0x13
57#define REG_COMC 0x14
58#define REG_COMD 0x15
59#define REG_COML 0x16
60#define REG_HSTRT 0x17
61#define REG_HSTOP 0x18
62#define REG_VSTRT 0x19
63#define REG_VSTOP 0x1a
64#define REG_PSHFT 0x1b
65#define REG_MIDH 0x1c
66#define REG_MIDL 0x1d
67#define REG_HSYNS 0x1e
68#define REG_HSYNE 0x1f
69#define REG_COME 0x20
70#define REG_YOFF 0x21
71#define REG_UOFF 0x22
72#define REG_VOFF 0x23
73#define REG_AEW 0x24
74#define REG_AEB 0x25
75#define REG_COMF 0x26
76#define REG_COMG 0x27
77#define REG_COMH 0x28
78#define REG_COMI 0x29
79
80#define REG_FRARL 0x2b
81#define REG_COMJ 0x2c
82#define REG_COMK 0x2d
83#define REG_AVGY 0x2e
84#define REG_REF0 0x2f
85#define REG_REF1 0x30
86#define REG_REF2 0x31
87#define REG_FRAJH 0x32
88#define REG_FRAJL 0x33
89#define REG_FACT 0x34
90#define REG_L1AEC 0x35
91#define REG_AVGU 0x36
92#define REG_AVGV 0x37
93
94#define REG_SPCB 0x60
95#define REG_SPCC 0x61
96#define REG_GAM1 0x62
97#define REG_GAM2 0x63
98#define REG_GAM3 0x64
99#define REG_SPCD 0x65
100
101#define REG_SPCE 0x68
102#define REG_ADCL 0x69
103
104#define REG_RMCO 0x6c
105#define REG_GMCO 0x6d
106#define REG_BMCO 0x6e
107
108
109/* Register bits, values, etc. */
110#define OV6650_PIDH 0x66 /* high byte of product ID number */
111#define OV6650_PIDL 0x50 /* low byte of product ID number */
112#define OV6650_MIDH 0x7F /* high byte of mfg ID */
113#define OV6650_MIDL 0xA2 /* low byte of mfg ID */
114
115#define DEF_GAIN 0x00
116#define DEF_BLUE 0x80
117#define DEF_RED 0x80
118
119#define SAT_SHIFT 4
120#define SAT_MASK (0xf << SAT_SHIFT)
121#define SET_SAT(x) (((x) << SAT_SHIFT) & SAT_MASK)
122
123#define HUE_EN BIT(5)
124#define HUE_MASK 0x1f
125#define DEF_HUE 0x10
126#define SET_HUE(x) (HUE_EN | ((x) & HUE_MASK))
127
128#define DEF_AECH 0x4D
129
130#define CLKRC_6MHz 0x00
131#define CLKRC_12MHz 0x40
132#define CLKRC_16MHz 0x80
133#define CLKRC_24MHz 0xc0
134#define CLKRC_DIV_MASK 0x3f
135#define GET_CLKRC_DIV(x) (((x) & CLKRC_DIV_MASK) + 1)
136
137#define COMA_RESET BIT(7)
138#define COMA_QCIF BIT(5)
139#define COMA_RAW_RGB BIT(4)
140#define COMA_RGB BIT(3)
141#define COMA_BW BIT(2)
142#define COMA_WORD_SWAP BIT(1)
143#define COMA_BYTE_SWAP BIT(0)
144#define DEF_COMA 0x00
145
146#define COMB_FLIP_V BIT(7)
147#define COMB_FLIP_H BIT(5)
148#define COMB_BAND_FILTER BIT(4)
149#define COMB_AWB BIT(2)
150#define COMB_AGC BIT(1)
151#define COMB_AEC BIT(0)
152#define DEF_COMB 0x5f
153
154#define COML_ONE_CHANNEL BIT(7)
155
156#define DEF_HSTRT 0x24
157#define DEF_HSTOP 0xd4
158#define DEF_VSTRT 0x04
159#define DEF_VSTOP 0x94
160
161#define COMF_HREF_LOW BIT(4)
162
163#define COMJ_PCLK_RISING BIT(4)
164#define COMJ_VSYNC_HIGH BIT(0)
165
166/* supported resolutions */
167#define W_QCIF (DEF_HSTOP - DEF_HSTRT)
168#define W_CIF (W_QCIF << 1)
169#define H_QCIF (DEF_VSTOP - DEF_VSTRT)
170#define H_CIF (H_QCIF << 1)
171
172#define FRAME_RATE_MAX 30
173
174
175struct ov6650_reg {
176 u8 reg;
177 u8 val;
178};
179
180struct ov6650 {
181 struct v4l2_subdev subdev;
182 struct v4l2_ctrl_handler hdl;
183 struct {
184 /* exposure/autoexposure cluster */
185 struct v4l2_ctrl *autoexposure;
186 struct v4l2_ctrl *exposure;
187 };
188 struct {
189 /* gain/autogain cluster */
190 struct v4l2_ctrl *autogain;
191 struct v4l2_ctrl *gain;
192 };
193 struct {
194 /* blue/red/autowhitebalance cluster */
195 struct v4l2_ctrl *autowb;
196 struct v4l2_ctrl *blue;
197 struct v4l2_ctrl *red;
198 };
199 bool half_scale; /* scale down output by 2 */
200 struct v4l2_rect rect; /* sensor cropping window */
201 unsigned long pclk_limit; /* from host */
202 unsigned long pclk_max; /* from resolution and format */
203 struct v4l2_fract tpf; /* as requested with s_parm */
204 enum v4l2_mbus_pixelcode code;
205 enum v4l2_colorspace colorspace;
206};
207
208
209static enum v4l2_mbus_pixelcode ov6650_codes[] = {
210 V4L2_MBUS_FMT_YUYV8_2X8,
211 V4L2_MBUS_FMT_UYVY8_2X8,
212 V4L2_MBUS_FMT_YVYU8_2X8,
213 V4L2_MBUS_FMT_VYUY8_2X8,
214 V4L2_MBUS_FMT_SBGGR8_1X8,
215 V4L2_MBUS_FMT_Y8_1X8,
216};
217
218/* read a register */
219static int ov6650_reg_read(struct i2c_client *client, u8 reg, u8 *val)
220{
221 int ret;
222 u8 data = reg;
223 struct i2c_msg msg = {
224 .addr = client->addr,
225 .flags = 0,
226 .len = 1,
227 .buf = &data,
228 };
229
230 ret = i2c_transfer(client->adapter, &msg, 1);
231 if (ret < 0)
232 goto err;
233
234 msg.flags = I2C_M_RD;
235 ret = i2c_transfer(client->adapter, &msg, 1);
236 if (ret < 0)
237 goto err;
238
239 *val = data;
240 return 0;
241
242err:
243 dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
244 return ret;
245}
246
247/* write a register */
248static int ov6650_reg_write(struct i2c_client *client, u8 reg, u8 val)
249{
250 int ret;
251 unsigned char data[2] = { reg, val };
252 struct i2c_msg msg = {
253 .addr = client->addr,
254 .flags = 0,
255 .len = 2,
256 .buf = data,
257 };
258
259 ret = i2c_transfer(client->adapter, &msg, 1);
260 udelay(100);
261
262 if (ret < 0) {
263 dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
264 return ret;
265 }
266 return 0;
267}
268
269
270/* Read a register, alter its bits, write it back */
271static int ov6650_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 mask)
272{
273 u8 val;
274 int ret;
275
276 ret = ov6650_reg_read(client, reg, &val);
277 if (ret) {
278 dev_err(&client->dev,
279 "[Read]-Modify-Write of register 0x%02x failed!\n",
280 reg);
281 return ret;
282 }
283
284 val &= ~mask;
285 val |= set;
286
287 ret = ov6650_reg_write(client, reg, val);
288 if (ret)
289 dev_err(&client->dev,
290 "Read-Modify-[Write] of register 0x%02x failed!\n",
291 reg);
292
293 return ret;
294}
295
296static struct ov6650 *to_ov6650(const struct i2c_client *client)
297{
298 return container_of(i2c_get_clientdata(client), struct ov6650, subdev);
299}
300
301/* Start/Stop streaming from the device */
302static int ov6650_s_stream(struct v4l2_subdev *sd, int enable)
303{
304 return 0;
305}
306
307/* Get status of additional camera capabilities */
308static int ov6550_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
309{
310 struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
311 struct v4l2_subdev *sd = &priv->subdev;
312 struct i2c_client *client = v4l2_get_subdevdata(sd);
313 uint8_t reg, reg2;
314 int ret;
315
316 switch (ctrl->id) {
317 case V4L2_CID_AUTOGAIN:
318 ret = ov6650_reg_read(client, REG_GAIN, &reg);
319 if (!ret)
320 priv->gain->val = reg;
321 return ret;
322 case V4L2_CID_AUTO_WHITE_BALANCE:
323 ret = ov6650_reg_read(client, REG_BLUE, &reg);
324 if (!ret)
325 ret = ov6650_reg_read(client, REG_RED, &reg2);
326 if (!ret) {
327 priv->blue->val = reg;
328 priv->red->val = reg2;
329 }
330 return ret;
331 case V4L2_CID_EXPOSURE_AUTO:
332 ret = ov6650_reg_read(client, REG_AECH, &reg);
333 if (!ret)
334 priv->exposure->val = reg;
335 return ret;
336 }
337 return -EINVAL;
338}
339
340/* Set status of additional camera capabilities */
341static int ov6550_s_ctrl(struct v4l2_ctrl *ctrl)
342{
343 struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
344 struct v4l2_subdev *sd = &priv->subdev;
345 struct i2c_client *client = v4l2_get_subdevdata(sd);
346 int ret;
347
348 switch (ctrl->id) {
349 case V4L2_CID_AUTOGAIN:
350 ret = ov6650_reg_rmw(client, REG_COMB,
351 ctrl->val ? COMB_AGC : 0, COMB_AGC);
352 if (!ret && !ctrl->val)
353 ret = ov6650_reg_write(client, REG_GAIN, priv->gain->val);
354 return ret;
355 case V4L2_CID_AUTO_WHITE_BALANCE:
356 ret = ov6650_reg_rmw(client, REG_COMB,
357 ctrl->val ? COMB_AWB : 0, COMB_AWB);
358 if (!ret && !ctrl->val) {
359 ret = ov6650_reg_write(client, REG_BLUE, priv->blue->val);
360 if (!ret)
361 ret = ov6650_reg_write(client, REG_RED,
362 priv->red->val);
363 }
364 return ret;
365 case V4L2_CID_SATURATION:
366 return ov6650_reg_rmw(client, REG_SAT, SET_SAT(ctrl->val),
367 SAT_MASK);
368 case V4L2_CID_HUE:
369 return ov6650_reg_rmw(client, REG_HUE, SET_HUE(ctrl->val),
370 HUE_MASK);
371 case V4L2_CID_BRIGHTNESS:
372 return ov6650_reg_write(client, REG_BRT, ctrl->val);
373 case V4L2_CID_EXPOSURE_AUTO:
374 ret = ov6650_reg_rmw(client, REG_COMB, ctrl->val ==
375 V4L2_EXPOSURE_AUTO ? COMB_AEC : 0, COMB_AEC);
376 if (!ret && ctrl->val == V4L2_EXPOSURE_MANUAL)
377 ret = ov6650_reg_write(client, REG_AECH,
378 priv->exposure->val);
379 return ret;
380 case V4L2_CID_GAMMA:
381 return ov6650_reg_write(client, REG_GAM1, ctrl->val);
382 case V4L2_CID_VFLIP:
383 return ov6650_reg_rmw(client, REG_COMB,
384 ctrl->val ? COMB_FLIP_V : 0, COMB_FLIP_V);
385 case V4L2_CID_HFLIP:
386 return ov6650_reg_rmw(client, REG_COMB,
387 ctrl->val ? COMB_FLIP_H : 0, COMB_FLIP_H);
388 }
389
390 return -EINVAL;
391}
392
393/* Get chip identification */
394static int ov6650_g_chip_ident(struct v4l2_subdev *sd,
395 struct v4l2_dbg_chip_ident *id)
396{
397 id->ident = V4L2_IDENT_OV6650;
398 id->revision = 0;
399
400 return 0;
401}
402
403#ifdef CONFIG_VIDEO_ADV_DEBUG
404static int ov6650_get_register(struct v4l2_subdev *sd,
405 struct v4l2_dbg_register *reg)
406{
407 struct i2c_client *client = v4l2_get_subdevdata(sd);
408 int ret;
409 u8 val;
410
411 if (reg->reg & ~0xff)
412 return -EINVAL;
413
414 reg->size = 1;
415
416 ret = ov6650_reg_read(client, reg->reg, &val);
417 if (!ret)
418 reg->val = (__u64)val;
419
420 return ret;
421}
422
423static int ov6650_set_register(struct v4l2_subdev *sd,
424 struct v4l2_dbg_register *reg)
425{
426 struct i2c_client *client = v4l2_get_subdevdata(sd);
427
428 if (reg->reg & ~0xff || reg->val & ~0xff)
429 return -EINVAL;
430
431 return ov6650_reg_write(client, reg->reg, reg->val);
432}
433#endif
434
435static int ov6650_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
436{
437 struct i2c_client *client = v4l2_get_subdevdata(sd);
438 struct ov6650 *priv = to_ov6650(client);
439
440 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
441 a->c = priv->rect;
442
443 return 0;
444}
445
446static int ov6650_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
447{
448 struct i2c_client *client = v4l2_get_subdevdata(sd);
449 struct ov6650 *priv = to_ov6650(client);
450 struct v4l2_rect *rect = &a->c;
451 int ret;
452
453 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
454 return -EINVAL;
455
456 rect->left = ALIGN(rect->left, 2);
457 rect->width = ALIGN(rect->width, 2);
458 rect->top = ALIGN(rect->top, 2);
459 rect->height = ALIGN(rect->height, 2);
460 soc_camera_limit_side(&rect->left, &rect->width,
461 DEF_HSTRT << 1, 2, W_CIF);
462 soc_camera_limit_side(&rect->top, &rect->height,
463 DEF_VSTRT << 1, 2, H_CIF);
464
465 ret = ov6650_reg_write(client, REG_HSTRT, rect->left >> 1);
466 if (!ret) {
467 priv->rect.left = rect->left;
468 ret = ov6650_reg_write(client, REG_HSTOP,
469 (rect->left + rect->width) >> 1);
470 }
471 if (!ret) {
472 priv->rect.width = rect->width;
473 ret = ov6650_reg_write(client, REG_VSTRT, rect->top >> 1);
474 }
475 if (!ret) {
476 priv->rect.top = rect->top;
477 ret = ov6650_reg_write(client, REG_VSTOP,
478 (rect->top + rect->height) >> 1);
479 }
480 if (!ret)
481 priv->rect.height = rect->height;
482
483 return ret;
484}
485
486static int ov6650_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
487{
488 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
489 return -EINVAL;
490
491 a->bounds.left = DEF_HSTRT << 1;
492 a->bounds.top = DEF_VSTRT << 1;
493 a->bounds.width = W_CIF;
494 a->bounds.height = H_CIF;
495 a->defrect = a->bounds;
496 a->pixelaspect.numerator = 1;
497 a->pixelaspect.denominator = 1;
498
499 return 0;
500}
501
502static int ov6650_g_fmt(struct v4l2_subdev *sd,
503 struct v4l2_mbus_framefmt *mf)
504{
505 struct i2c_client *client = v4l2_get_subdevdata(sd);
506 struct ov6650 *priv = to_ov6650(client);
507
508 mf->width = priv->rect.width >> priv->half_scale;
509 mf->height = priv->rect.height >> priv->half_scale;
510 mf->code = priv->code;
511 mf->colorspace = priv->colorspace;
512 mf->field = V4L2_FIELD_NONE;
513
514 return 0;
515}
516
517static bool is_unscaled_ok(int width, int height, struct v4l2_rect *rect)
518{
519 return width > rect->width >> 1 || height > rect->height >> 1;
520}
521
522static u8 to_clkrc(struct v4l2_fract *timeperframe,
523 unsigned long pclk_limit, unsigned long pclk_max)
524{
525 unsigned long pclk;
526
527 if (timeperframe->numerator && timeperframe->denominator)
528 pclk = pclk_max * timeperframe->denominator /
529 (FRAME_RATE_MAX * timeperframe->numerator);
530 else
531 pclk = pclk_max;
532
533 if (pclk_limit && pclk_limit < pclk)
534 pclk = pclk_limit;
535
536 return (pclk_max - 1) / pclk;
537}
538
539/* set the format we will capture in */
540static int ov6650_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
541{
542 struct i2c_client *client = v4l2_get_subdevdata(sd);
543 struct soc_camera_device *icd = v4l2_get_subdev_hostdata(sd);
544 struct soc_camera_sense *sense = icd->sense;
545 struct ov6650 *priv = to_ov6650(client);
546 bool half_scale = !is_unscaled_ok(mf->width, mf->height, &priv->rect);
547 struct v4l2_crop a = {
548 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
549 .c = {
550 .left = priv->rect.left + (priv->rect.width >> 1) -
551 (mf->width >> (1 - half_scale)),
552 .top = priv->rect.top + (priv->rect.height >> 1) -
553 (mf->height >> (1 - half_scale)),
554 .width = mf->width << half_scale,
555 .height = mf->height << half_scale,
556 },
557 };
558 enum v4l2_mbus_pixelcode code = mf->code;
559 unsigned long mclk, pclk;
560 u8 coma_set = 0, coma_mask = 0, coml_set, coml_mask, clkrc;
561 int ret;
562
563 /* select color matrix configuration for given color encoding */
564 switch (code) {
565 case V4L2_MBUS_FMT_Y8_1X8:
566 dev_dbg(&client->dev, "pixel format GREY8_1X8\n");
567 coma_mask |= COMA_RGB | COMA_WORD_SWAP | COMA_BYTE_SWAP;
568 coma_set |= COMA_BW;
569 break;
570 case V4L2_MBUS_FMT_YUYV8_2X8:
571 dev_dbg(&client->dev, "pixel format YUYV8_2X8_LE\n");
572 coma_mask |= COMA_RGB | COMA_BW | COMA_BYTE_SWAP;
573 coma_set |= COMA_WORD_SWAP;
574 break;
575 case V4L2_MBUS_FMT_YVYU8_2X8:
576 dev_dbg(&client->dev, "pixel format YVYU8_2X8_LE (untested)\n");
577 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP |
578 COMA_BYTE_SWAP;
579 break;
580 case V4L2_MBUS_FMT_UYVY8_2X8:
581 dev_dbg(&client->dev, "pixel format YUYV8_2X8_BE\n");
582 if (half_scale) {
583 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
584 coma_set |= COMA_BYTE_SWAP;
585 } else {
586 coma_mask |= COMA_RGB | COMA_BW;
587 coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
588 }
589 break;
590 case V4L2_MBUS_FMT_VYUY8_2X8:
591 dev_dbg(&client->dev, "pixel format YVYU8_2X8_BE (untested)\n");
592 if (half_scale) {
593 coma_mask |= COMA_RGB | COMA_BW;
594 coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
595 } else {
596 coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
597 coma_set |= COMA_BYTE_SWAP;
598 }
599 break;
600 case V4L2_MBUS_FMT_SBGGR8_1X8:
601 dev_dbg(&client->dev, "pixel format SBGGR8_1X8 (untested)\n");
602 coma_mask |= COMA_BW | COMA_BYTE_SWAP | COMA_WORD_SWAP;
603 coma_set |= COMA_RAW_RGB | COMA_RGB;
604 break;
605 default:
606 dev_err(&client->dev, "Pixel format not handled: 0x%x\n", code);
607 return -EINVAL;
608 }
609 priv->code = code;
610
611 if (code == V4L2_MBUS_FMT_Y8_1X8 ||
612 code == V4L2_MBUS_FMT_SBGGR8_1X8) {
613 coml_mask = COML_ONE_CHANNEL;
614 coml_set = 0;
615 priv->pclk_max = 4000000;
616 } else {
617 coml_mask = 0;
618 coml_set = COML_ONE_CHANNEL;
619 priv->pclk_max = 8000000;
620 }
621
622 if (code == V4L2_MBUS_FMT_SBGGR8_1X8)
623 priv->colorspace = V4L2_COLORSPACE_SRGB;
624 else if (code != 0)
625 priv->colorspace = V4L2_COLORSPACE_JPEG;
626
627 if (half_scale) {
628 dev_dbg(&client->dev, "max resolution: QCIF\n");
629 coma_set |= COMA_QCIF;
630 priv->pclk_max /= 2;
631 } else {
632 dev_dbg(&client->dev, "max resolution: CIF\n");
633 coma_mask |= COMA_QCIF;
634 }
635 priv->half_scale = half_scale;
636
637 if (sense) {
638 if (sense->master_clock == 8000000) {
639 dev_dbg(&client->dev, "8MHz input clock\n");
640 clkrc = CLKRC_6MHz;
641 } else if (sense->master_clock == 12000000) {
642 dev_dbg(&client->dev, "12MHz input clock\n");
643 clkrc = CLKRC_12MHz;
644 } else if (sense->master_clock == 16000000) {
645 dev_dbg(&client->dev, "16MHz input clock\n");
646 clkrc = CLKRC_16MHz;
647 } else if (sense->master_clock == 24000000) {
648 dev_dbg(&client->dev, "24MHz input clock\n");
649 clkrc = CLKRC_24MHz;
650 } else {
651 dev_err(&client->dev,
652 "unsupported input clock, check platform data\n");
653 return -EINVAL;
654 }
655 mclk = sense->master_clock;
656 priv->pclk_limit = sense->pixel_clock_max;
657 } else {
658 clkrc = CLKRC_24MHz;
659 mclk = 24000000;
660 priv->pclk_limit = 0;
661 dev_dbg(&client->dev, "using default 24MHz input clock\n");
662 }
663
664 clkrc |= to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max);
665
666 pclk = priv->pclk_max / GET_CLKRC_DIV(clkrc);
667 dev_dbg(&client->dev, "pixel clock divider: %ld.%ld\n",
668 mclk / pclk, 10 * mclk % pclk / pclk);
669
670 ret = ov6650_s_crop(sd, &a);
671 if (!ret)
672 ret = ov6650_reg_rmw(client, REG_COMA, coma_set, coma_mask);
673 if (!ret)
674 ret = ov6650_reg_write(client, REG_CLKRC, clkrc);
675 if (!ret)
676 ret = ov6650_reg_rmw(client, REG_COML, coml_set, coml_mask);
677
678 if (!ret) {
679 mf->colorspace = priv->colorspace;
680 mf->width = priv->rect.width >> half_scale;
681 mf->height = priv->rect.height >> half_scale;
682 }
683
684 return ret;
685}
686
687static int ov6650_try_fmt(struct v4l2_subdev *sd,
688 struct v4l2_mbus_framefmt *mf)
689{
690 struct i2c_client *client = v4l2_get_subdevdata(sd);
691 struct ov6650 *priv = to_ov6650(client);
692
693 if (is_unscaled_ok(mf->width, mf->height, &priv->rect))
694 v4l_bound_align_image(&mf->width, 2, W_CIF, 1,
695 &mf->height, 2, H_CIF, 1, 0);
696
697 mf->field = V4L2_FIELD_NONE;
698
699 switch (mf->code) {
700 case V4L2_MBUS_FMT_Y10_1X10:
701 mf->code = V4L2_MBUS_FMT_Y8_1X8;
702 case V4L2_MBUS_FMT_Y8_1X8:
703 case V4L2_MBUS_FMT_YVYU8_2X8:
704 case V4L2_MBUS_FMT_YUYV8_2X8:
705 case V4L2_MBUS_FMT_VYUY8_2X8:
706 case V4L2_MBUS_FMT_UYVY8_2X8:
707 mf->colorspace = V4L2_COLORSPACE_JPEG;
708 break;
709 default:
710 mf->code = V4L2_MBUS_FMT_SBGGR8_1X8;
711 case V4L2_MBUS_FMT_SBGGR8_1X8:
712 mf->colorspace = V4L2_COLORSPACE_SRGB;
713 break;
714 }
715
716 return 0;
717}
718
719static int ov6650_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
720 enum v4l2_mbus_pixelcode *code)
721{
722 if (index >= ARRAY_SIZE(ov6650_codes))
723 return -EINVAL;
724
725 *code = ov6650_codes[index];
726 return 0;
727}
728
729static int ov6650_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
730{
731 struct i2c_client *client = v4l2_get_subdevdata(sd);
732 struct ov6650 *priv = to_ov6650(client);
733 struct v4l2_captureparm *cp = &parms->parm.capture;
734
735 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
736 return -EINVAL;
737
738 memset(cp, 0, sizeof(*cp));
739 cp->capability = V4L2_CAP_TIMEPERFRAME;
740 cp->timeperframe.numerator = GET_CLKRC_DIV(to_clkrc(&priv->tpf,
741 priv->pclk_limit, priv->pclk_max));
742 cp->timeperframe.denominator = FRAME_RATE_MAX;
743
744 dev_dbg(&client->dev, "Frame interval: %u/%u s\n",
745 cp->timeperframe.numerator, cp->timeperframe.denominator);
746
747 return 0;
748}
749
750static int ov6650_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
751{
752 struct i2c_client *client = v4l2_get_subdevdata(sd);
753 struct ov6650 *priv = to_ov6650(client);
754 struct v4l2_captureparm *cp = &parms->parm.capture;
755 struct v4l2_fract *tpf = &cp->timeperframe;
756 int div, ret;
757 u8 clkrc;
758
759 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
760 return -EINVAL;
761
762 if (cp->extendedmode != 0)
763 return -EINVAL;
764
765 if (tpf->numerator == 0 || tpf->denominator == 0)
766 div = 1; /* Reset to full rate */
767 else
768 div = (tpf->numerator * FRAME_RATE_MAX) / tpf->denominator;
769
770 if (div == 0)
771 div = 1;
772 else if (div > GET_CLKRC_DIV(CLKRC_DIV_MASK))
773 div = GET_CLKRC_DIV(CLKRC_DIV_MASK);
774
775 /*
776 * Keep result to be used as tpf limit
777 * for subseqent clock divider calculations
778 */
779 priv->tpf.numerator = div;
780 priv->tpf.denominator = FRAME_RATE_MAX;
781
782 clkrc = to_clkrc(&priv->tpf, priv->pclk_limit, priv->pclk_max);
783
784 ret = ov6650_reg_rmw(client, REG_CLKRC, clkrc, CLKRC_DIV_MASK);
785 if (!ret) {
786 tpf->numerator = GET_CLKRC_DIV(clkrc);
787 tpf->denominator = FRAME_RATE_MAX;
788 }
789
790 return ret;
791}
792
793/* Soft reset the camera. This has nothing to do with the RESET pin! */
794static int ov6650_reset(struct i2c_client *client)
795{
796 int ret;
797
798 dev_dbg(&client->dev, "reset\n");
799
800 ret = ov6650_reg_rmw(client, REG_COMA, COMA_RESET, 0);
801 if (ret)
802 dev_err(&client->dev,
803 "An error occurred while entering soft reset!\n");
804
805 return ret;
806}
807
808/* program default register values */
809static int ov6650_prog_dflt(struct i2c_client *client)
810{
811 int ret;
812
813 dev_dbg(&client->dev, "initializing\n");
814
815 ret = ov6650_reg_write(client, REG_COMA, 0); /* ~COMA_RESET */
816 if (!ret)
817 ret = ov6650_reg_rmw(client, REG_COMB, 0, COMB_BAND_FILTER);
818
819 return ret;
820}
821
822static int ov6650_video_probe(struct i2c_client *client)
823{
824 u8 pidh, pidl, midh, midl;
825 int ret = 0;
826
827 /*
828 * check and show product ID and manufacturer ID
829 */
830 ret = ov6650_reg_read(client, REG_PIDH, &pidh);
831 if (!ret)
832 ret = ov6650_reg_read(client, REG_PIDL, &pidl);
833 if (!ret)
834 ret = ov6650_reg_read(client, REG_MIDH, &midh);
835 if (!ret)
836 ret = ov6650_reg_read(client, REG_MIDL, &midl);
837
838 if (ret)
839 return ret;
840
841 if ((pidh != OV6650_PIDH) || (pidl != OV6650_PIDL)) {
842 dev_err(&client->dev, "Product ID error 0x%02x:0x%02x\n",
843 pidh, pidl);
844 return -ENODEV;
845 }
846
847 dev_info(&client->dev,
848 "ov6650 Product ID 0x%02x:0x%02x Manufacturer ID 0x%02x:0x%02x\n",
849 pidh, pidl, midh, midl);
850
851 ret = ov6650_reset(client);
852 if (!ret)
853 ret = ov6650_prog_dflt(client);
854
855 return ret;
856}
857
858static const struct v4l2_ctrl_ops ov6550_ctrl_ops = {
859 .g_volatile_ctrl = ov6550_g_volatile_ctrl,
860 .s_ctrl = ov6550_s_ctrl,
861};
862
863static struct v4l2_subdev_core_ops ov6650_core_ops = {
864 .g_chip_ident = ov6650_g_chip_ident,
865#ifdef CONFIG_VIDEO_ADV_DEBUG
866 .g_register = ov6650_get_register,
867 .s_register = ov6650_set_register,
868#endif
869};
870
871/* Request bus settings on camera side */
872static int ov6650_g_mbus_config(struct v4l2_subdev *sd,
873 struct v4l2_mbus_config *cfg)
874{
875 struct i2c_client *client = v4l2_get_subdevdata(sd);
876 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
877
878 cfg->flags = V4L2_MBUS_MASTER |
879 V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING |
880 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW |
881 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW |
882 V4L2_MBUS_DATA_ACTIVE_HIGH;
883 cfg->type = V4L2_MBUS_PARALLEL;
884 cfg->flags = soc_camera_apply_board_flags(icl, cfg);
885
886 return 0;
887}
888
889/* Alter bus settings on camera side */
890static int ov6650_s_mbus_config(struct v4l2_subdev *sd,
891 const struct v4l2_mbus_config *cfg)
892{
893 struct i2c_client *client = v4l2_get_subdevdata(sd);
894 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
895 unsigned long flags = soc_camera_apply_board_flags(icl, cfg);
896 int ret;
897
898 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
899 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_PCLK_RISING, 0);
900 else
901 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_PCLK_RISING);
902 if (ret)
903 return ret;
904
905 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
906 ret = ov6650_reg_rmw(client, REG_COMF, COMF_HREF_LOW, 0);
907 else
908 ret = ov6650_reg_rmw(client, REG_COMF, 0, COMF_HREF_LOW);
909 if (ret)
910 return ret;
911
912 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
913 ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_VSYNC_HIGH, 0);
914 else
915 ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_VSYNC_HIGH);
916
917 return ret;
918}
919
920static struct v4l2_subdev_video_ops ov6650_video_ops = {
921 .s_stream = ov6650_s_stream,
922 .g_mbus_fmt = ov6650_g_fmt,
923 .s_mbus_fmt = ov6650_s_fmt,
924 .try_mbus_fmt = ov6650_try_fmt,
925 .enum_mbus_fmt = ov6650_enum_fmt,
926 .cropcap = ov6650_cropcap,
927 .g_crop = ov6650_g_crop,
928 .s_crop = ov6650_s_crop,
929 .g_parm = ov6650_g_parm,
930 .s_parm = ov6650_s_parm,
931 .g_mbus_config = ov6650_g_mbus_config,
932 .s_mbus_config = ov6650_s_mbus_config,
933};
934
935static struct v4l2_subdev_ops ov6650_subdev_ops = {
936 .core = &ov6650_core_ops,
937 .video = &ov6650_video_ops,
938};
939
940/*
941 * i2c_driver function
942 */
943static int ov6650_probe(struct i2c_client *client,
944 const struct i2c_device_id *did)
945{
946 struct ov6650 *priv;
947 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
948 int ret;
949
950 if (!icl) {
951 dev_err(&client->dev, "Missing platform_data for driver\n");
952 return -EINVAL;
953 }
954
955 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
956 if (!priv) {
957 dev_err(&client->dev,
958 "Failed to allocate memory for private data!\n");
959 return -ENOMEM;
960 }
961
962 v4l2_i2c_subdev_init(&priv->subdev, client, &ov6650_subdev_ops);
963 v4l2_ctrl_handler_init(&priv->hdl, 13);
964 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
965 V4L2_CID_VFLIP, 0, 1, 1, 0);
966 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
967 V4L2_CID_HFLIP, 0, 1, 1, 0);
968 priv->autogain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
969 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
970 priv->gain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
971 V4L2_CID_GAIN, 0, 0x3f, 1, DEF_GAIN);
972 priv->autowb = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
973 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
974 priv->blue = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
975 V4L2_CID_BLUE_BALANCE, 0, 0xff, 1, DEF_BLUE);
976 priv->red = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
977 V4L2_CID_RED_BALANCE, 0, 0xff, 1, DEF_RED);
978 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
979 V4L2_CID_SATURATION, 0, 0xf, 1, 0x8);
980 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
981 V4L2_CID_HUE, 0, HUE_MASK, 1, DEF_HUE);
982 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
983 V4L2_CID_BRIGHTNESS, 0, 0xff, 1, 0x80);
984 priv->autoexposure = v4l2_ctrl_new_std_menu(&priv->hdl,
985 &ov6550_ctrl_ops, V4L2_CID_EXPOSURE_AUTO,
986 V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO);
987 priv->exposure = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
988 V4L2_CID_EXPOSURE, 0, 0xff, 1, DEF_AECH);
989 v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
990 V4L2_CID_GAMMA, 0, 0xff, 1, 0x12);
991
992 priv->subdev.ctrl_handler = &priv->hdl;
993 if (priv->hdl.error) {
994 int err = priv->hdl.error;
995
996 kfree(priv);
997 return err;
998 }
999 v4l2_ctrl_auto_cluster(2, &priv->autogain, 0, true);
1000 v4l2_ctrl_auto_cluster(3, &priv->autowb, 0, true);
1001 v4l2_ctrl_auto_cluster(2, &priv->autoexposure,
1002 V4L2_EXPOSURE_MANUAL, true);
1003
1004 priv->rect.left = DEF_HSTRT << 1;
1005 priv->rect.top = DEF_VSTRT << 1;
1006 priv->rect.width = W_CIF;
1007 priv->rect.height = H_CIF;
1008 priv->half_scale = false;
1009 priv->code = V4L2_MBUS_FMT_YUYV8_2X8;
1010 priv->colorspace = V4L2_COLORSPACE_JPEG;
1011
1012 ret = ov6650_video_probe(client);
1013 if (!ret)
1014 ret = v4l2_ctrl_handler_setup(&priv->hdl);
1015
1016 if (ret) {
1017 v4l2_ctrl_handler_free(&priv->hdl);
1018 kfree(priv);
1019 }
1020
1021 return ret;
1022}
1023
1024static int ov6650_remove(struct i2c_client *client)
1025{
1026 struct ov6650 *priv = to_ov6650(client);
1027
1028 v4l2_device_unregister_subdev(&priv->subdev);
1029 v4l2_ctrl_handler_free(&priv->hdl);
1030 kfree(priv);
1031 return 0;
1032}
1033
1034static const struct i2c_device_id ov6650_id[] = {
1035 { "ov6650", 0 },
1036 { }
1037};
1038MODULE_DEVICE_TABLE(i2c, ov6650_id);
1039
1040static struct i2c_driver ov6650_i2c_driver = {
1041 .driver = {
1042 .name = "ov6650",
1043 },
1044 .probe = ov6650_probe,
1045 .remove = ov6650_remove,
1046 .id_table = ov6650_id,
1047};
1048
1049module_i2c_driver(ov6650_i2c_driver);
1050
1051MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV6650");
1052MODULE_AUTHOR("Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>");
1053MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/video/ov772x.c b/drivers/media/video/ov772x.c
deleted file mode 100644
index 6d79b89b8603..000000000000
--- a/drivers/media/video/ov772x.c
+++ /dev/null
@@ -1,1126 +0,0 @@
1/*
2 * ov772x Camera Driver
3 *
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ov7670 and soc_camera_platform driver,
8 *
9 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
10 * Copyright (C) 2008 Magnus Damm
11 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/i2c.h>
21#include <linux/slab.h>
22#include <linux/delay.h>
23#include <linux/v4l2-mediabus.h>
24#include <linux/videodev2.h>
25
26#include <media/ov772x.h>
27#include <media/soc_camera.h>
28#include <media/v4l2-ctrls.h>
29#include <media/v4l2-chip-ident.h>
30#include <media/v4l2-subdev.h>
31
32/*
33 * register offset
34 */
35#define GAIN 0x00 /* AGC - Gain control gain setting */
36#define BLUE 0x01 /* AWB - Blue channel gain setting */
37#define RED 0x02 /* AWB - Red channel gain setting */
38#define GREEN 0x03 /* AWB - Green channel gain setting */
39#define COM1 0x04 /* Common control 1 */
40#define BAVG 0x05 /* U/B Average Level */
41#define GAVG 0x06 /* Y/Gb Average Level */
42#define RAVG 0x07 /* V/R Average Level */
43#define AECH 0x08 /* Exposure Value - AEC MSBs */
44#define COM2 0x09 /* Common control 2 */
45#define PID 0x0A /* Product ID Number MSB */
46#define VER 0x0B /* Product ID Number LSB */
47#define COM3 0x0C /* Common control 3 */
48#define COM4 0x0D /* Common control 4 */
49#define COM5 0x0E /* Common control 5 */
50#define COM6 0x0F /* Common control 6 */
51#define AEC 0x10 /* Exposure Value */
52#define CLKRC 0x11 /* Internal clock */
53#define COM7 0x12 /* Common control 7 */
54#define COM8 0x13 /* Common control 8 */
55#define COM9 0x14 /* Common control 9 */
56#define COM10 0x15 /* Common control 10 */
57#define REG16 0x16 /* Register 16 */
58#define HSTART 0x17 /* Horizontal sensor size */
59#define HSIZE 0x18 /* Horizontal frame (HREF column) end high 8-bit */
60#define VSTART 0x19 /* Vertical frame (row) start high 8-bit */
61#define VSIZE 0x1A /* Vertical sensor size */
62#define PSHFT 0x1B /* Data format - pixel delay select */
63#define MIDH 0x1C /* Manufacturer ID byte - high */
64#define MIDL 0x1D /* Manufacturer ID byte - low */
65#define LAEC 0x1F /* Fine AEC value */
66#define COM11 0x20 /* Common control 11 */
67#define BDBASE 0x22 /* Banding filter Minimum AEC value */
68#define DBSTEP 0x23 /* Banding filter Maximum Setp */
69#define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */
70#define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */
71#define VPT 0x26 /* AGC/AEC Fast mode operating region */
72#define REG28 0x28 /* Register 28 */
73#define HOUTSIZE 0x29 /* Horizontal data output size MSBs */
74#define EXHCH 0x2A /* Dummy pixel insert MSB */
75#define EXHCL 0x2B /* Dummy pixel insert LSB */
76#define VOUTSIZE 0x2C /* Vertical data output size MSBs */
77#define ADVFL 0x2D /* LSB of insert dummy lines in Vertical direction */
78#define ADVFH 0x2E /* MSG of insert dummy lines in Vertical direction */
79#define YAVE 0x2F /* Y/G Channel Average value */
80#define LUMHTH 0x30 /* Histogram AEC/AGC Luminance high level threshold */
81#define LUMLTH 0x31 /* Histogram AEC/AGC Luminance low level threshold */
82#define HREF 0x32 /* Image start and size control */
83#define DM_LNL 0x33 /* Dummy line low 8 bits */
84#define DM_LNH 0x34 /* Dummy line high 8 bits */
85#define ADOFF_B 0x35 /* AD offset compensation value for B channel */
86#define ADOFF_R 0x36 /* AD offset compensation value for R channel */
87#define ADOFF_GB 0x37 /* AD offset compensation value for Gb channel */
88#define ADOFF_GR 0x38 /* AD offset compensation value for Gr channel */
89#define OFF_B 0x39 /* Analog process B channel offset value */
90#define OFF_R 0x3A /* Analog process R channel offset value */
91#define OFF_GB 0x3B /* Analog process Gb channel offset value */
92#define OFF_GR 0x3C /* Analog process Gr channel offset value */
93#define COM12 0x3D /* Common control 12 */
94#define COM13 0x3E /* Common control 13 */
95#define COM14 0x3F /* Common control 14 */
96#define COM15 0x40 /* Common control 15*/
97#define COM16 0x41 /* Common control 16 */
98#define TGT_B 0x42 /* BLC blue channel target value */
99#define TGT_R 0x43 /* BLC red channel target value */
100#define TGT_GB 0x44 /* BLC Gb channel target value */
101#define TGT_GR 0x45 /* BLC Gr channel target value */
102/* for ov7720 */
103#define LCC0 0x46 /* Lens correction control 0 */
104#define LCC1 0x47 /* Lens correction option 1 - X coordinate */
105#define LCC2 0x48 /* Lens correction option 2 - Y coordinate */
106#define LCC3 0x49 /* Lens correction option 3 */
107#define LCC4 0x4A /* Lens correction option 4 - radius of the circular */
108#define LCC5 0x4B /* Lens correction option 5 */
109#define LCC6 0x4C /* Lens correction option 6 */
110/* for ov7725 */
111#define LC_CTR 0x46 /* Lens correction control */
112#define LC_XC 0x47 /* X coordinate of lens correction center relative */
113#define LC_YC 0x48 /* Y coordinate of lens correction center relative */
114#define LC_COEF 0x49 /* Lens correction coefficient */
115#define LC_RADI 0x4A /* Lens correction radius */
116#define LC_COEFB 0x4B /* Lens B channel compensation coefficient */
117#define LC_COEFR 0x4C /* Lens R channel compensation coefficient */
118
119#define FIXGAIN 0x4D /* Analog fix gain amplifer */
120#define AREF0 0x4E /* Sensor reference control */
121#define AREF1 0x4F /* Sensor reference current control */
122#define AREF2 0x50 /* Analog reference control */
123#define AREF3 0x51 /* ADC reference control */
124#define AREF4 0x52 /* ADC reference control */
125#define AREF5 0x53 /* ADC reference control */
126#define AREF6 0x54 /* Analog reference control */
127#define AREF7 0x55 /* Analog reference control */
128#define UFIX 0x60 /* U channel fixed value output */
129#define VFIX 0x61 /* V channel fixed value output */
130#define AWBB_BLK 0x62 /* AWB option for advanced AWB */
131#define AWB_CTRL0 0x63 /* AWB control byte 0 */
132#define DSP_CTRL1 0x64 /* DSP control byte 1 */
133#define DSP_CTRL2 0x65 /* DSP control byte 2 */
134#define DSP_CTRL3 0x66 /* DSP control byte 3 */
135#define DSP_CTRL4 0x67 /* DSP control byte 4 */
136#define AWB_BIAS 0x68 /* AWB BLC level clip */
137#define AWB_CTRL1 0x69 /* AWB control 1 */
138#define AWB_CTRL2 0x6A /* AWB control 2 */
139#define AWB_CTRL3 0x6B /* AWB control 3 */
140#define AWB_CTRL4 0x6C /* AWB control 4 */
141#define AWB_CTRL5 0x6D /* AWB control 5 */
142#define AWB_CTRL6 0x6E /* AWB control 6 */
143#define AWB_CTRL7 0x6F /* AWB control 7 */
144#define AWB_CTRL8 0x70 /* AWB control 8 */
145#define AWB_CTRL9 0x71 /* AWB control 9 */
146#define AWB_CTRL10 0x72 /* AWB control 10 */
147#define AWB_CTRL11 0x73 /* AWB control 11 */
148#define AWB_CTRL12 0x74 /* AWB control 12 */
149#define AWB_CTRL13 0x75 /* AWB control 13 */
150#define AWB_CTRL14 0x76 /* AWB control 14 */
151#define AWB_CTRL15 0x77 /* AWB control 15 */
152#define AWB_CTRL16 0x78 /* AWB control 16 */
153#define AWB_CTRL17 0x79 /* AWB control 17 */
154#define AWB_CTRL18 0x7A /* AWB control 18 */
155#define AWB_CTRL19 0x7B /* AWB control 19 */
156#define AWB_CTRL20 0x7C /* AWB control 20 */
157#define AWB_CTRL21 0x7D /* AWB control 21 */
158#define GAM1 0x7E /* Gamma Curve 1st segment input end point */
159#define GAM2 0x7F /* Gamma Curve 2nd segment input end point */
160#define GAM3 0x80 /* Gamma Curve 3rd segment input end point */
161#define GAM4 0x81 /* Gamma Curve 4th segment input end point */
162#define GAM5 0x82 /* Gamma Curve 5th segment input end point */
163#define GAM6 0x83 /* Gamma Curve 6th segment input end point */
164#define GAM7 0x84 /* Gamma Curve 7th segment input end point */
165#define GAM8 0x85 /* Gamma Curve 8th segment input end point */
166#define GAM9 0x86 /* Gamma Curve 9th segment input end point */
167#define GAM10 0x87 /* Gamma Curve 10th segment input end point */
168#define GAM11 0x88 /* Gamma Curve 11th segment input end point */
169#define GAM12 0x89 /* Gamma Curve 12th segment input end point */
170#define GAM13 0x8A /* Gamma Curve 13th segment input end point */
171#define GAM14 0x8B /* Gamma Curve 14th segment input end point */
172#define GAM15 0x8C /* Gamma Curve 15th segment input end point */
173#define SLOP 0x8D /* Gamma curve highest segment slope */
174#define DNSTH 0x8E /* De-noise threshold */
175#define EDGE_STRNGT 0x8F /* Edge strength control when manual mode */
176#define EDGE_TRSHLD 0x90 /* Edge threshold control when manual mode */
177#define DNSOFF 0x91 /* Auto De-noise threshold control */
178#define EDGE_UPPER 0x92 /* Edge strength upper limit when Auto mode */
179#define EDGE_LOWER 0x93 /* Edge strength lower limit when Auto mode */
180#define MTX1 0x94 /* Matrix coefficient 1 */
181#define MTX2 0x95 /* Matrix coefficient 2 */
182#define MTX3 0x96 /* Matrix coefficient 3 */
183#define MTX4 0x97 /* Matrix coefficient 4 */
184#define MTX5 0x98 /* Matrix coefficient 5 */
185#define MTX6 0x99 /* Matrix coefficient 6 */
186#define MTX_CTRL 0x9A /* Matrix control */
187#define BRIGHT 0x9B /* Brightness control */
188#define CNTRST 0x9C /* Contrast contrast */
189#define CNTRST_CTRL 0x9D /* Contrast contrast center */
190#define UVAD_J0 0x9E /* Auto UV adjust contrast 0 */
191#define UVAD_J1 0x9F /* Auto UV adjust contrast 1 */
192#define SCAL0 0xA0 /* Scaling control 0 */
193#define SCAL1 0xA1 /* Scaling control 1 */
194#define SCAL2 0xA2 /* Scaling control 2 */
195#define FIFODLYM 0xA3 /* FIFO manual mode delay control */
196#define FIFODLYA 0xA4 /* FIFO auto mode delay control */
197#define SDE 0xA6 /* Special digital effect control */
198#define USAT 0xA7 /* U component saturation control */
199#define VSAT 0xA8 /* V component saturation control */
200/* for ov7720 */
201#define HUE0 0xA9 /* Hue control 0 */
202#define HUE1 0xAA /* Hue control 1 */
203/* for ov7725 */
204#define HUECOS 0xA9 /* Cosine value */
205#define HUESIN 0xAA /* Sine value */
206
207#define SIGN 0xAB /* Sign bit for Hue and contrast */
208#define DSPAUTO 0xAC /* DSP auto function ON/OFF control */
209
210/*
211 * register detail
212 */
213
214/* COM2 */
215#define SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */
216 /* Output drive capability */
217#define OCAP_1x 0x00 /* 1x */
218#define OCAP_2x 0x01 /* 2x */
219#define OCAP_3x 0x02 /* 3x */
220#define OCAP_4x 0x03 /* 4x */
221
222/* COM3 */
223#define SWAP_MASK (SWAP_RGB | SWAP_YUV | SWAP_ML)
224#define IMG_MASK (VFLIP_IMG | HFLIP_IMG)
225
226#define VFLIP_IMG 0x80 /* Vertical flip image ON/OFF selection */
227#define HFLIP_IMG 0x40 /* Horizontal mirror image ON/OFF selection */
228#define SWAP_RGB 0x20 /* Swap B/R output sequence in RGB mode */
229#define SWAP_YUV 0x10 /* Swap Y/UV output sequence in YUV mode */
230#define SWAP_ML 0x08 /* Swap output MSB/LSB */
231 /* Tri-state option for output clock */
232#define NOTRI_CLOCK 0x04 /* 0: Tri-state at this period */
233 /* 1: No tri-state at this period */
234 /* Tri-state option for output data */
235#define NOTRI_DATA 0x02 /* 0: Tri-state at this period */
236 /* 1: No tri-state at this period */
237#define SCOLOR_TEST 0x01 /* Sensor color bar test pattern */
238
239/* COM4 */
240 /* PLL frequency control */
241#define PLL_BYPASS 0x00 /* 00: Bypass PLL */
242#define PLL_4x 0x40 /* 01: PLL 4x */
243#define PLL_6x 0x80 /* 10: PLL 6x */
244#define PLL_8x 0xc0 /* 11: PLL 8x */
245 /* AEC evaluate window */
246#define AEC_FULL 0x00 /* 00: Full window */
247#define AEC_1p2 0x10 /* 01: 1/2 window */
248#define AEC_1p4 0x20 /* 10: 1/4 window */
249#define AEC_2p3 0x30 /* 11: Low 2/3 window */
250
251/* COM5 */
252#define AFR_ON_OFF 0x80 /* Auto frame rate control ON/OFF selection */
253#define AFR_SPPED 0x40 /* Auto frame rate control speed selection */
254 /* Auto frame rate max rate control */
255#define AFR_NO_RATE 0x00 /* No reduction of frame rate */
256#define AFR_1p2 0x10 /* Max reduction to 1/2 frame rate */
257#define AFR_1p4 0x20 /* Max reduction to 1/4 frame rate */
258#define AFR_1p8 0x30 /* Max reduction to 1/8 frame rate */
259 /* Auto frame rate active point control */
260#define AF_2x 0x00 /* Add frame when AGC reaches 2x gain */
261#define AF_4x 0x04 /* Add frame when AGC reaches 4x gain */
262#define AF_8x 0x08 /* Add frame when AGC reaches 8x gain */
263#define AF_16x 0x0c /* Add frame when AGC reaches 16x gain */
264 /* AEC max step control */
265#define AEC_NO_LIMIT 0x01 /* 0 : AEC incease step has limit */
266 /* 1 : No limit to AEC increase step */
267
268/* COM7 */
269 /* SCCB Register Reset */
270#define SCCB_RESET 0x80 /* 0 : No change */
271 /* 1 : Resets all registers to default */
272 /* Resolution selection */
273#define SLCT_MASK 0x40 /* Mask of VGA or QVGA */
274#define SLCT_VGA 0x00 /* 0 : VGA */
275#define SLCT_QVGA 0x40 /* 1 : QVGA */
276#define ITU656_ON_OFF 0x20 /* ITU656 protocol ON/OFF selection */
277 /* RGB output format control */
278#define FMT_MASK 0x0c /* Mask of color format */
279#define FMT_GBR422 0x00 /* 00 : GBR 4:2:2 */
280#define FMT_RGB565 0x04 /* 01 : RGB 565 */
281#define FMT_RGB555 0x08 /* 10 : RGB 555 */
282#define FMT_RGB444 0x0c /* 11 : RGB 444 */
283 /* Output format control */
284#define OFMT_MASK 0x03 /* Mask of output format */
285#define OFMT_YUV 0x00 /* 00 : YUV */
286#define OFMT_P_BRAW 0x01 /* 01 : Processed Bayer RAW */
287#define OFMT_RGB 0x02 /* 10 : RGB */
288#define OFMT_BRAW 0x03 /* 11 : Bayer RAW */
289
290/* COM8 */
291#define FAST_ALGO 0x80 /* Enable fast AGC/AEC algorithm */
292 /* AEC Setp size limit */
293#define UNLMT_STEP 0x40 /* 0 : Step size is limited */
294 /* 1 : Unlimited step size */
295#define BNDF_ON_OFF 0x20 /* Banding filter ON/OFF */
296#define AEC_BND 0x10 /* Enable AEC below banding value */
297#define AEC_ON_OFF 0x08 /* Fine AEC ON/OFF control */
298#define AGC_ON 0x04 /* AGC Enable */
299#define AWB_ON 0x02 /* AWB Enable */
300#define AEC_ON 0x01 /* AEC Enable */
301
302/* COM9 */
303#define BASE_AECAGC 0x80 /* Histogram or average based AEC/AGC */
304 /* Automatic gain ceiling - maximum AGC value */
305#define GAIN_2x 0x00 /* 000 : 2x */
306#define GAIN_4x 0x10 /* 001 : 4x */
307#define GAIN_8x 0x20 /* 010 : 8x */
308#define GAIN_16x 0x30 /* 011 : 16x */
309#define GAIN_32x 0x40 /* 100 : 32x */
310#define GAIN_64x 0x50 /* 101 : 64x */
311#define GAIN_128x 0x60 /* 110 : 128x */
312#define DROP_VSYNC 0x04 /* Drop VSYNC output of corrupt frame */
313#define DROP_HREF 0x02 /* Drop HREF output of corrupt frame */
314
315/* COM11 */
316#define SGLF_ON_OFF 0x02 /* Single frame ON/OFF selection */
317#define SGLF_TRIG 0x01 /* Single frame transfer trigger */
318
319/* EXHCH */
320#define VSIZE_LSB 0x04 /* Vertical data output size LSB */
321
322/* DSP_CTRL1 */
323#define FIFO_ON 0x80 /* FIFO enable/disable selection */
324#define UV_ON_OFF 0x40 /* UV adjust function ON/OFF selection */
325#define YUV444_2_422 0x20 /* YUV444 to 422 UV channel option selection */
326#define CLR_MTRX_ON_OFF 0x10 /* Color matrix ON/OFF selection */
327#define INTPLT_ON_OFF 0x08 /* Interpolation ON/OFF selection */
328#define GMM_ON_OFF 0x04 /* Gamma function ON/OFF selection */
329#define AUTO_BLK_ON_OFF 0x02 /* Black defect auto correction ON/OFF */
330#define AUTO_WHT_ON_OFF 0x01 /* White define auto correction ON/OFF */
331
332/* DSP_CTRL3 */
333#define UV_MASK 0x80 /* UV output sequence option */
334#define UV_ON 0x80 /* ON */
335#define UV_OFF 0x00 /* OFF */
336#define CBAR_MASK 0x20 /* DSP Color bar mask */
337#define CBAR_ON 0x20 /* ON */
338#define CBAR_OFF 0x00 /* OFF */
339
340/* HSTART */
341#define HST_VGA 0x23
342#define HST_QVGA 0x3F
343
344/* HSIZE */
345#define HSZ_VGA 0xA0
346#define HSZ_QVGA 0x50
347
348/* VSTART */
349#define VST_VGA 0x07
350#define VST_QVGA 0x03
351
352/* VSIZE */
353#define VSZ_VGA 0xF0
354#define VSZ_QVGA 0x78
355
356/* HOUTSIZE */
357#define HOSZ_VGA 0xA0
358#define HOSZ_QVGA 0x50
359
360/* VOUTSIZE */
361#define VOSZ_VGA 0xF0
362#define VOSZ_QVGA 0x78
363
364/* DSPAUTO (DSP Auto Function ON/OFF Control) */
365#define AWB_ACTRL 0x80 /* AWB auto threshold control */
366#define DENOISE_ACTRL 0x40 /* De-noise auto threshold control */
367#define EDGE_ACTRL 0x20 /* Edge enhancement auto strength control */
368#define UV_ACTRL 0x10 /* UV adjust auto slope control */
369#define SCAL0_ACTRL 0x08 /* Auto scaling factor control */
370#define SCAL1_2_ACTRL 0x04 /* Auto scaling factor control */
371
372/*
373 * ID
374 */
375#define OV7720 0x7720
376#define OV7725 0x7721
377#define VERSION(pid, ver) ((pid<<8)|(ver&0xFF))
378
379/*
380 * struct
381 */
382struct regval_list {
383 unsigned char reg_num;
384 unsigned char value;
385};
386
387struct ov772x_color_format {
388 enum v4l2_mbus_pixelcode code;
389 enum v4l2_colorspace colorspace;
390 u8 dsp3;
391 u8 com3;
392 u8 com7;
393};
394
395struct ov772x_win_size {
396 char *name;
397 __u32 width;
398 __u32 height;
399 unsigned char com7_bit;
400 const struct regval_list *regs;
401};
402
403struct ov772x_priv {
404 struct v4l2_subdev subdev;
405 struct v4l2_ctrl_handler hdl;
406 struct ov772x_camera_info *info;
407 const struct ov772x_color_format *cfmt;
408 const struct ov772x_win_size *win;
409 int model;
410 unsigned short flag_vflip:1;
411 unsigned short flag_hflip:1;
412 /* band_filter = COM8[5] ? 256 - BDBASE : 0 */
413 unsigned short band_filter;
414};
415
416#define ENDMARKER { 0xff, 0xff }
417
418/*
419 * register setting for window size
420 */
421static const struct regval_list ov772x_qvga_regs[] = {
422 { HSTART, HST_QVGA },
423 { HSIZE, HSZ_QVGA },
424 { VSTART, VST_QVGA },
425 { VSIZE, VSZ_QVGA },
426 { HOUTSIZE, HOSZ_QVGA },
427 { VOUTSIZE, VOSZ_QVGA },
428 ENDMARKER,
429};
430
431static const struct regval_list ov772x_vga_regs[] = {
432 { HSTART, HST_VGA },
433 { HSIZE, HSZ_VGA },
434 { VSTART, VST_VGA },
435 { VSIZE, VSZ_VGA },
436 { HOUTSIZE, HOSZ_VGA },
437 { VOUTSIZE, VOSZ_VGA },
438 ENDMARKER,
439};
440
441/*
442 * supported color format list
443 */
444static const struct ov772x_color_format ov772x_cfmts[] = {
445 {
446 .code = V4L2_MBUS_FMT_YUYV8_2X8,
447 .colorspace = V4L2_COLORSPACE_JPEG,
448 .dsp3 = 0x0,
449 .com3 = SWAP_YUV,
450 .com7 = OFMT_YUV,
451 },
452 {
453 .code = V4L2_MBUS_FMT_YVYU8_2X8,
454 .colorspace = V4L2_COLORSPACE_JPEG,
455 .dsp3 = UV_ON,
456 .com3 = SWAP_YUV,
457 .com7 = OFMT_YUV,
458 },
459 {
460 .code = V4L2_MBUS_FMT_UYVY8_2X8,
461 .colorspace = V4L2_COLORSPACE_JPEG,
462 .dsp3 = 0x0,
463 .com3 = 0x0,
464 .com7 = OFMT_YUV,
465 },
466 {
467 .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE,
468 .colorspace = V4L2_COLORSPACE_SRGB,
469 .dsp3 = 0x0,
470 .com3 = SWAP_RGB,
471 .com7 = FMT_RGB555 | OFMT_RGB,
472 },
473 {
474 .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE,
475 .colorspace = V4L2_COLORSPACE_SRGB,
476 .dsp3 = 0x0,
477 .com3 = 0x0,
478 .com7 = FMT_RGB555 | OFMT_RGB,
479 },
480 {
481 .code = V4L2_MBUS_FMT_RGB565_2X8_LE,
482 .colorspace = V4L2_COLORSPACE_SRGB,
483 .dsp3 = 0x0,
484 .com3 = SWAP_RGB,
485 .com7 = FMT_RGB565 | OFMT_RGB,
486 },
487 {
488 .code = V4L2_MBUS_FMT_RGB565_2X8_BE,
489 .colorspace = V4L2_COLORSPACE_SRGB,
490 .dsp3 = 0x0,
491 .com3 = 0x0,
492 .com7 = FMT_RGB565 | OFMT_RGB,
493 },
494};
495
496
497/*
498 * window size list
499 */
500#define VGA_WIDTH 640
501#define VGA_HEIGHT 480
502#define QVGA_WIDTH 320
503#define QVGA_HEIGHT 240
504#define MAX_WIDTH VGA_WIDTH
505#define MAX_HEIGHT VGA_HEIGHT
506
507static const struct ov772x_win_size ov772x_win_vga = {
508 .name = "VGA",
509 .width = VGA_WIDTH,
510 .height = VGA_HEIGHT,
511 .com7_bit = SLCT_VGA,
512 .regs = ov772x_vga_regs,
513};
514
515static const struct ov772x_win_size ov772x_win_qvga = {
516 .name = "QVGA",
517 .width = QVGA_WIDTH,
518 .height = QVGA_HEIGHT,
519 .com7_bit = SLCT_QVGA,
520 .regs = ov772x_qvga_regs,
521};
522
523/*
524 * general function
525 */
526
527static struct ov772x_priv *to_ov772x(const struct i2c_client *client)
528{
529 return container_of(i2c_get_clientdata(client), struct ov772x_priv,
530 subdev);
531}
532
533static int ov772x_write_array(struct i2c_client *client,
534 const struct regval_list *vals)
535{
536 while (vals->reg_num != 0xff) {
537 int ret = i2c_smbus_write_byte_data(client,
538 vals->reg_num,
539 vals->value);
540 if (ret < 0)
541 return ret;
542 vals++;
543 }
544 return 0;
545}
546
547static int ov772x_mask_set(struct i2c_client *client,
548 u8 command,
549 u8 mask,
550 u8 set)
551{
552 s32 val = i2c_smbus_read_byte_data(client, command);
553 if (val < 0)
554 return val;
555
556 val &= ~mask;
557 val |= set & mask;
558
559 return i2c_smbus_write_byte_data(client, command, val);
560}
561
562static int ov772x_reset(struct i2c_client *client)
563{
564 int ret = i2c_smbus_write_byte_data(client, COM7, SCCB_RESET);
565 msleep(1);
566 return ret;
567}
568
569/*
570 * soc_camera_ops function
571 */
572
573static int ov772x_s_stream(struct v4l2_subdev *sd, int enable)
574{
575 struct i2c_client *client = v4l2_get_subdevdata(sd);
576 struct ov772x_priv *priv = container_of(sd, struct ov772x_priv, subdev);
577
578 if (!enable) {
579 ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, SOFT_SLEEP_MODE);
580 return 0;
581 }
582
583 if (!priv->win || !priv->cfmt) {
584 dev_err(&client->dev, "norm or win select error\n");
585 return -EPERM;
586 }
587
588 ov772x_mask_set(client, COM2, SOFT_SLEEP_MODE, 0);
589
590 dev_dbg(&client->dev, "format %d, win %s\n",
591 priv->cfmt->code, priv->win->name);
592
593 return 0;
594}
595
596static int ov772x_s_ctrl(struct v4l2_ctrl *ctrl)
597{
598 struct ov772x_priv *priv = container_of(ctrl->handler,
599 struct ov772x_priv, hdl);
600 struct v4l2_subdev *sd = &priv->subdev;
601 struct i2c_client *client = v4l2_get_subdevdata(sd);
602 int ret = 0;
603 u8 val;
604
605 switch (ctrl->id) {
606 case V4L2_CID_VFLIP:
607 val = ctrl->val ? VFLIP_IMG : 0x00;
608 priv->flag_vflip = ctrl->val;
609 if (priv->info->flags & OV772X_FLAG_VFLIP)
610 val ^= VFLIP_IMG;
611 return ov772x_mask_set(client, COM3, VFLIP_IMG, val);
612 case V4L2_CID_HFLIP:
613 val = ctrl->val ? HFLIP_IMG : 0x00;
614 priv->flag_hflip = ctrl->val;
615 if (priv->info->flags & OV772X_FLAG_HFLIP)
616 val ^= HFLIP_IMG;
617 return ov772x_mask_set(client, COM3, HFLIP_IMG, val);
618 case V4L2_CID_BAND_STOP_FILTER:
619 if (!ctrl->val) {
620 /* Switch the filter off, it is on now */
621 ret = ov772x_mask_set(client, BDBASE, 0xff, 0xff);
622 if (!ret)
623 ret = ov772x_mask_set(client, COM8,
624 BNDF_ON_OFF, 0);
625 } else {
626 /* Switch the filter on, set AEC low limit */
627 val = 256 - ctrl->val;
628 ret = ov772x_mask_set(client, COM8,
629 BNDF_ON_OFF, BNDF_ON_OFF);
630 if (!ret)
631 ret = ov772x_mask_set(client, BDBASE,
632 0xff, val);
633 }
634 if (!ret)
635 priv->band_filter = ctrl->val;
636 return ret;
637 }
638
639 return -EINVAL;
640}
641
642static int ov772x_g_chip_ident(struct v4l2_subdev *sd,
643 struct v4l2_dbg_chip_ident *id)
644{
645 struct ov772x_priv *priv = container_of(sd, struct ov772x_priv, subdev);
646
647 id->ident = priv->model;
648 id->revision = 0;
649
650 return 0;
651}
652
653#ifdef CONFIG_VIDEO_ADV_DEBUG
654static int ov772x_g_register(struct v4l2_subdev *sd,
655 struct v4l2_dbg_register *reg)
656{
657 struct i2c_client *client = v4l2_get_subdevdata(sd);
658 int ret;
659
660 reg->size = 1;
661 if (reg->reg > 0xff)
662 return -EINVAL;
663
664 ret = i2c_smbus_read_byte_data(client, reg->reg);
665 if (ret < 0)
666 return ret;
667
668 reg->val = (__u64)ret;
669
670 return 0;
671}
672
673static int ov772x_s_register(struct v4l2_subdev *sd,
674 struct v4l2_dbg_register *reg)
675{
676 struct i2c_client *client = v4l2_get_subdevdata(sd);
677
678 if (reg->reg > 0xff ||
679 reg->val > 0xff)
680 return -EINVAL;
681
682 return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
683}
684#endif
685
686static const struct ov772x_win_size *ov772x_select_win(u32 width, u32 height)
687{
688 __u32 diff;
689 const struct ov772x_win_size *win;
690
691 /* default is QVGA */
692 diff = abs(width - ov772x_win_qvga.width) +
693 abs(height - ov772x_win_qvga.height);
694 win = &ov772x_win_qvga;
695
696 /* VGA */
697 if (diff >
698 abs(width - ov772x_win_vga.width) +
699 abs(height - ov772x_win_vga.height))
700 win = &ov772x_win_vga;
701
702 return win;
703}
704
705static int ov772x_set_params(struct i2c_client *client, u32 *width, u32 *height,
706 enum v4l2_mbus_pixelcode code)
707{
708 struct ov772x_priv *priv = to_ov772x(client);
709 int ret = -EINVAL;
710 u8 val;
711 int i;
712
713 /*
714 * select format
715 */
716 priv->cfmt = NULL;
717 for (i = 0; i < ARRAY_SIZE(ov772x_cfmts); i++) {
718 if (code == ov772x_cfmts[i].code) {
719 priv->cfmt = ov772x_cfmts + i;
720 break;
721 }
722 }
723 if (!priv->cfmt)
724 goto ov772x_set_fmt_error;
725
726 /*
727 * select win
728 */
729 priv->win = ov772x_select_win(*width, *height);
730
731 /*
732 * reset hardware
733 */
734 ov772x_reset(client);
735
736 /*
737 * Edge Ctrl
738 */
739 if (priv->info->edgectrl.strength & OV772X_MANUAL_EDGE_CTRL) {
740
741 /*
742 * Manual Edge Control Mode
743 *
744 * Edge auto strength bit is set by default.
745 * Remove it when manual mode.
746 */
747
748 ret = ov772x_mask_set(client, DSPAUTO, EDGE_ACTRL, 0x00);
749 if (ret < 0)
750 goto ov772x_set_fmt_error;
751
752 ret = ov772x_mask_set(client,
753 EDGE_TRSHLD, OV772X_EDGE_THRESHOLD_MASK,
754 priv->info->edgectrl.threshold);
755 if (ret < 0)
756 goto ov772x_set_fmt_error;
757
758 ret = ov772x_mask_set(client,
759 EDGE_STRNGT, OV772X_EDGE_STRENGTH_MASK,
760 priv->info->edgectrl.strength);
761 if (ret < 0)
762 goto ov772x_set_fmt_error;
763
764 } else if (priv->info->edgectrl.upper > priv->info->edgectrl.lower) {
765 /*
766 * Auto Edge Control Mode
767 *
768 * set upper and lower limit
769 */
770 ret = ov772x_mask_set(client,
771 EDGE_UPPER, OV772X_EDGE_UPPER_MASK,
772 priv->info->edgectrl.upper);
773 if (ret < 0)
774 goto ov772x_set_fmt_error;
775
776 ret = ov772x_mask_set(client,
777 EDGE_LOWER, OV772X_EDGE_LOWER_MASK,
778 priv->info->edgectrl.lower);
779 if (ret < 0)
780 goto ov772x_set_fmt_error;
781 }
782
783 /*
784 * set size format
785 */
786 ret = ov772x_write_array(client, priv->win->regs);
787 if (ret < 0)
788 goto ov772x_set_fmt_error;
789
790 /*
791 * set DSP_CTRL3
792 */
793 val = priv->cfmt->dsp3;
794 if (val) {
795 ret = ov772x_mask_set(client,
796 DSP_CTRL3, UV_MASK, val);
797 if (ret < 0)
798 goto ov772x_set_fmt_error;
799 }
800
801 /*
802 * set COM3
803 */
804 val = priv->cfmt->com3;
805 if (priv->info->flags & OV772X_FLAG_VFLIP)
806 val |= VFLIP_IMG;
807 if (priv->info->flags & OV772X_FLAG_HFLIP)
808 val |= HFLIP_IMG;
809 if (priv->flag_vflip)
810 val ^= VFLIP_IMG;
811 if (priv->flag_hflip)
812 val ^= HFLIP_IMG;
813
814 ret = ov772x_mask_set(client,
815 COM3, SWAP_MASK | IMG_MASK, val);
816 if (ret < 0)
817 goto ov772x_set_fmt_error;
818
819 /*
820 * set COM7
821 */
822 val = priv->win->com7_bit | priv->cfmt->com7;
823 ret = ov772x_mask_set(client,
824 COM7, SLCT_MASK | FMT_MASK | OFMT_MASK,
825 val);
826 if (ret < 0)
827 goto ov772x_set_fmt_error;
828
829 /*
830 * set COM8
831 */
832 if (priv->band_filter) {
833 ret = ov772x_mask_set(client, COM8, BNDF_ON_OFF, 1);
834 if (!ret)
835 ret = ov772x_mask_set(client, BDBASE,
836 0xff, 256 - priv->band_filter);
837 if (ret < 0)
838 goto ov772x_set_fmt_error;
839 }
840
841 *width = priv->win->width;
842 *height = priv->win->height;
843
844 return ret;
845
846ov772x_set_fmt_error:
847
848 ov772x_reset(client);
849 priv->win = NULL;
850 priv->cfmt = NULL;
851
852 return ret;
853}
854
855static int ov772x_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
856{
857 a->c.left = 0;
858 a->c.top = 0;
859 a->c.width = VGA_WIDTH;
860 a->c.height = VGA_HEIGHT;
861 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
862
863 return 0;
864}
865
866static int ov772x_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
867{
868 a->bounds.left = 0;
869 a->bounds.top = 0;
870 a->bounds.width = VGA_WIDTH;
871 a->bounds.height = VGA_HEIGHT;
872 a->defrect = a->bounds;
873 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
874 a->pixelaspect.numerator = 1;
875 a->pixelaspect.denominator = 1;
876
877 return 0;
878}
879
880static int ov772x_g_fmt(struct v4l2_subdev *sd,
881 struct v4l2_mbus_framefmt *mf)
882{
883 struct ov772x_priv *priv = container_of(sd, struct ov772x_priv, subdev);
884
885 if (!priv->win || !priv->cfmt) {
886 priv->cfmt = &ov772x_cfmts[0];
887 priv->win = ov772x_select_win(VGA_WIDTH, VGA_HEIGHT);
888 }
889
890 mf->width = priv->win->width;
891 mf->height = priv->win->height;
892 mf->code = priv->cfmt->code;
893 mf->colorspace = priv->cfmt->colorspace;
894 mf->field = V4L2_FIELD_NONE;
895
896 return 0;
897}
898
899static int ov772x_s_fmt(struct v4l2_subdev *sd,
900 struct v4l2_mbus_framefmt *mf)
901{
902 struct i2c_client *client = v4l2_get_subdevdata(sd);
903 struct ov772x_priv *priv = container_of(sd, struct ov772x_priv, subdev);
904 int ret = ov772x_set_params(client, &mf->width, &mf->height,
905 mf->code);
906
907 if (!ret)
908 mf->colorspace = priv->cfmt->colorspace;
909
910 return ret;
911}
912
913static int ov772x_try_fmt(struct v4l2_subdev *sd,
914 struct v4l2_mbus_framefmt *mf)
915{
916 struct ov772x_priv *priv = container_of(sd, struct ov772x_priv, subdev);
917 const struct ov772x_win_size *win;
918 int i;
919
920 /*
921 * select suitable win
922 */
923 win = ov772x_select_win(mf->width, mf->height);
924
925 mf->width = win->width;
926 mf->height = win->height;
927 mf->field = V4L2_FIELD_NONE;
928
929 for (i = 0; i < ARRAY_SIZE(ov772x_cfmts); i++)
930 if (mf->code == ov772x_cfmts[i].code)
931 break;
932
933 if (i == ARRAY_SIZE(ov772x_cfmts)) {
934 /* Unsupported format requested. Propose either */
935 if (priv->cfmt) {
936 /* the current one or */
937 mf->colorspace = priv->cfmt->colorspace;
938 mf->code = priv->cfmt->code;
939 } else {
940 /* the default one */
941 mf->colorspace = ov772x_cfmts[0].colorspace;
942 mf->code = ov772x_cfmts[0].code;
943 }
944 } else {
945 /* Also return the colorspace */
946 mf->colorspace = ov772x_cfmts[i].colorspace;
947 }
948
949 return 0;
950}
951
952static int ov772x_video_probe(struct i2c_client *client)
953{
954 struct ov772x_priv *priv = to_ov772x(client);
955 u8 pid, ver;
956 const char *devname;
957
958 /*
959 * check and show product ID and manufacturer ID
960 */
961 pid = i2c_smbus_read_byte_data(client, PID);
962 ver = i2c_smbus_read_byte_data(client, VER);
963
964 switch (VERSION(pid, ver)) {
965 case OV7720:
966 devname = "ov7720";
967 priv->model = V4L2_IDENT_OV7720;
968 break;
969 case OV7725:
970 devname = "ov7725";
971 priv->model = V4L2_IDENT_OV7725;
972 break;
973 default:
974 dev_err(&client->dev,
975 "Product ID error %x:%x\n", pid, ver);
976 return -ENODEV;
977 }
978
979 dev_info(&client->dev,
980 "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
981 devname,
982 pid,
983 ver,
984 i2c_smbus_read_byte_data(client, MIDH),
985 i2c_smbus_read_byte_data(client, MIDL));
986 return v4l2_ctrl_handler_setup(&priv->hdl);
987}
988
989static const struct v4l2_ctrl_ops ov772x_ctrl_ops = {
990 .s_ctrl = ov772x_s_ctrl,
991};
992
993static struct v4l2_subdev_core_ops ov772x_subdev_core_ops = {
994 .g_chip_ident = ov772x_g_chip_ident,
995#ifdef CONFIG_VIDEO_ADV_DEBUG
996 .g_register = ov772x_g_register,
997 .s_register = ov772x_s_register,
998#endif
999};
1000
1001static int ov772x_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
1002 enum v4l2_mbus_pixelcode *code)
1003{
1004 if (index >= ARRAY_SIZE(ov772x_cfmts))
1005 return -EINVAL;
1006
1007 *code = ov772x_cfmts[index].code;
1008 return 0;
1009}
1010
1011static int ov772x_g_mbus_config(struct v4l2_subdev *sd,
1012 struct v4l2_mbus_config *cfg)
1013{
1014 struct i2c_client *client = v4l2_get_subdevdata(sd);
1015 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
1016
1017 cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
1018 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1019 V4L2_MBUS_DATA_ACTIVE_HIGH;
1020 cfg->type = V4L2_MBUS_PARALLEL;
1021 cfg->flags = soc_camera_apply_board_flags(icl, cfg);
1022
1023 return 0;
1024}
1025
1026static struct v4l2_subdev_video_ops ov772x_subdev_video_ops = {
1027 .s_stream = ov772x_s_stream,
1028 .g_mbus_fmt = ov772x_g_fmt,
1029 .s_mbus_fmt = ov772x_s_fmt,
1030 .try_mbus_fmt = ov772x_try_fmt,
1031 .cropcap = ov772x_cropcap,
1032 .g_crop = ov772x_g_crop,
1033 .enum_mbus_fmt = ov772x_enum_fmt,
1034 .g_mbus_config = ov772x_g_mbus_config,
1035};
1036
1037static struct v4l2_subdev_ops ov772x_subdev_ops = {
1038 .core = &ov772x_subdev_core_ops,
1039 .video = &ov772x_subdev_video_ops,
1040};
1041
1042/*
1043 * i2c_driver function
1044 */
1045
1046static int ov772x_probe(struct i2c_client *client,
1047 const struct i2c_device_id *did)
1048{
1049 struct ov772x_priv *priv;
1050 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
1051 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
1052 int ret;
1053
1054 if (!icl || !icl->priv) {
1055 dev_err(&client->dev, "OV772X: missing platform data!\n");
1056 return -EINVAL;
1057 }
1058
1059 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
1060 dev_err(&adapter->dev,
1061 "I2C-Adapter doesn't support "
1062 "I2C_FUNC_SMBUS_BYTE_DATA\n");
1063 return -EIO;
1064 }
1065
1066 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
1067 if (!priv)
1068 return -ENOMEM;
1069
1070 priv->info = icl->priv;
1071
1072 v4l2_i2c_subdev_init(&priv->subdev, client, &ov772x_subdev_ops);
1073 v4l2_ctrl_handler_init(&priv->hdl, 3);
1074 v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
1075 V4L2_CID_VFLIP, 0, 1, 1, 0);
1076 v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
1077 V4L2_CID_HFLIP, 0, 1, 1, 0);
1078 v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
1079 V4L2_CID_BAND_STOP_FILTER, 0, 256, 1, 0);
1080 priv->subdev.ctrl_handler = &priv->hdl;
1081 if (priv->hdl.error) {
1082 int err = priv->hdl.error;
1083
1084 kfree(priv);
1085 return err;
1086 }
1087
1088 ret = ov772x_video_probe(client);
1089 if (ret) {
1090 v4l2_ctrl_handler_free(&priv->hdl);
1091 kfree(priv);
1092 }
1093
1094 return ret;
1095}
1096
1097static int ov772x_remove(struct i2c_client *client)
1098{
1099 struct ov772x_priv *priv = to_ov772x(client);
1100
1101 v4l2_device_unregister_subdev(&priv->subdev);
1102 v4l2_ctrl_handler_free(&priv->hdl);
1103 kfree(priv);
1104 return 0;
1105}
1106
1107static const struct i2c_device_id ov772x_id[] = {
1108 { "ov772x", 0 },
1109 { }
1110};
1111MODULE_DEVICE_TABLE(i2c, ov772x_id);
1112
1113static struct i2c_driver ov772x_i2c_driver = {
1114 .driver = {
1115 .name = "ov772x",
1116 },
1117 .probe = ov772x_probe,
1118 .remove = ov772x_remove,
1119 .id_table = ov772x_id,
1120};
1121
1122module_i2c_driver(ov772x_i2c_driver);
1123
1124MODULE_DESCRIPTION("SoC Camera driver for ov772x");
1125MODULE_AUTHOR("Kuninori Morimoto");
1126MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/video/ov9640.c b/drivers/media/video/ov9640.c
deleted file mode 100644
index 9ed4ba4236c4..000000000000
--- a/drivers/media/video/ov9640.c
+++ /dev/null
@@ -1,746 +0,0 @@
1/*
2 * OmniVision OV96xx Camera Driver
3 *
4 * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
5 *
6 * Based on ov772x camera driver:
7 *
8 * Copyright (C) 2008 Renesas Solutions Corp.
9 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
10 *
11 * Based on ov7670 and soc_camera_platform driver,
12 *
13 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
14 * Copyright (C) 2008 Magnus Damm
15 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/i2c.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
27#include <linux/v4l2-mediabus.h>
28#include <linux/videodev2.h>
29
30#include <media/soc_camera.h>
31#include <media/v4l2-chip-ident.h>
32#include <media/v4l2-common.h>
33#include <media/v4l2-ctrls.h>
34
35#include "ov9640.h"
36
37#define to_ov9640_sensor(sd) container_of(sd, struct ov9640_priv, subdev)
38
39/* default register setup */
40static const struct ov9640_reg ov9640_regs_dflt[] = {
41 { OV9640_COM5, OV9640_COM5_SYSCLK | OV9640_COM5_LONGEXP },
42 { OV9640_COM6, OV9640_COM6_OPT_BLC | OV9640_COM6_ADBLC_BIAS |
43 OV9640_COM6_FMT_RST | OV9640_COM6_ADBLC_OPTEN },
44 { OV9640_PSHFT, OV9640_PSHFT_VAL(0x01) },
45 { OV9640_ACOM, OV9640_ACOM_2X_ANALOG | OV9640_ACOM_RSVD },
46 { OV9640_TSLB, OV9640_TSLB_YUYV_UYVY },
47 { OV9640_COM16, OV9640_COM16_RB_AVG },
48
49 /* Gamma curve P */
50 { 0x6c, 0x40 }, { 0x6d, 0x30 }, { 0x6e, 0x4b }, { 0x6f, 0x60 },
51 { 0x70, 0x70 }, { 0x71, 0x70 }, { 0x72, 0x70 }, { 0x73, 0x70 },
52 { 0x74, 0x60 }, { 0x75, 0x60 }, { 0x76, 0x50 }, { 0x77, 0x48 },
53 { 0x78, 0x3a }, { 0x79, 0x2e }, { 0x7a, 0x28 }, { 0x7b, 0x22 },
54
55 /* Gamma curve T */
56 { 0x7c, 0x04 }, { 0x7d, 0x07 }, { 0x7e, 0x10 }, { 0x7f, 0x28 },
57 { 0x80, 0x36 }, { 0x81, 0x44 }, { 0x82, 0x52 }, { 0x83, 0x60 },
58 { 0x84, 0x6c }, { 0x85, 0x78 }, { 0x86, 0x8c }, { 0x87, 0x9e },
59 { 0x88, 0xbb }, { 0x89, 0xd2 }, { 0x8a, 0xe6 },
60};
61
62/* Configurations
63 * NOTE: for YUV, alter the following registers:
64 * COM12 |= OV9640_COM12_YUV_AVG
65 *
66 * for RGB, alter the following registers:
67 * COM7 |= OV9640_COM7_RGB
68 * COM13 |= OV9640_COM13_RGB_AVG
69 * COM15 |= proper RGB color encoding mode
70 */
71static const struct ov9640_reg ov9640_regs_qqcif[] = {
72 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x0f) },
73 { OV9640_COM1, OV9640_COM1_QQFMT | OV9640_COM1_HREF_2SKIP },
74 { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
75 { OV9640_COM7, OV9640_COM7_QCIF },
76 { OV9640_COM12, OV9640_COM12_RSVD },
77 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
78 { OV9640_COM15, OV9640_COM15_OR_10F0 },
79};
80
81static const struct ov9640_reg ov9640_regs_qqvga[] = {
82 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x07) },
83 { OV9640_COM1, OV9640_COM1_QQFMT | OV9640_COM1_HREF_2SKIP },
84 { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
85 { OV9640_COM7, OV9640_COM7_QVGA },
86 { OV9640_COM12, OV9640_COM12_RSVD },
87 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
88 { OV9640_COM15, OV9640_COM15_OR_10F0 },
89};
90
91static const struct ov9640_reg ov9640_regs_qcif[] = {
92 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x07) },
93 { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
94 { OV9640_COM7, OV9640_COM7_QCIF },
95 { OV9640_COM12, OV9640_COM12_RSVD },
96 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
97 { OV9640_COM15, OV9640_COM15_OR_10F0 },
98};
99
100static const struct ov9640_reg ov9640_regs_qvga[] = {
101 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x03) },
102 { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
103 { OV9640_COM7, OV9640_COM7_QVGA },
104 { OV9640_COM12, OV9640_COM12_RSVD },
105 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
106 { OV9640_COM15, OV9640_COM15_OR_10F0 },
107};
108
109static const struct ov9640_reg ov9640_regs_cif[] = {
110 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x03) },
111 { OV9640_COM3, OV9640_COM3_VP },
112 { OV9640_COM7, OV9640_COM7_CIF },
113 { OV9640_COM12, OV9640_COM12_RSVD },
114 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
115 { OV9640_COM15, OV9640_COM15_OR_10F0 },
116};
117
118static const struct ov9640_reg ov9640_regs_vga[] = {
119 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x01) },
120 { OV9640_COM3, OV9640_COM3_VP },
121 { OV9640_COM7, OV9640_COM7_VGA },
122 { OV9640_COM12, OV9640_COM12_RSVD },
123 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
124 { OV9640_COM15, OV9640_COM15_OR_10F0 },
125};
126
127static const struct ov9640_reg ov9640_regs_sxga[] = {
128 { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x01) },
129 { OV9640_COM3, OV9640_COM3_VP },
130 { OV9640_COM7, 0 },
131 { OV9640_COM12, OV9640_COM12_RSVD },
132 { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
133 { OV9640_COM15, OV9640_COM15_OR_10F0 },
134};
135
136static const struct ov9640_reg ov9640_regs_yuv[] = {
137 { OV9640_MTX1, 0x58 },
138 { OV9640_MTX2, 0x48 },
139 { OV9640_MTX3, 0x10 },
140 { OV9640_MTX4, 0x28 },
141 { OV9640_MTX5, 0x48 },
142 { OV9640_MTX6, 0x70 },
143 { OV9640_MTX7, 0x40 },
144 { OV9640_MTX8, 0x40 },
145 { OV9640_MTX9, 0x40 },
146 { OV9640_MTXS, 0x0f },
147};
148
149static const struct ov9640_reg ov9640_regs_rgb[] = {
150 { OV9640_MTX1, 0x71 },
151 { OV9640_MTX2, 0x3e },
152 { OV9640_MTX3, 0x0c },
153 { OV9640_MTX4, 0x33 },
154 { OV9640_MTX5, 0x72 },
155 { OV9640_MTX6, 0x00 },
156 { OV9640_MTX7, 0x2b },
157 { OV9640_MTX8, 0x66 },
158 { OV9640_MTX9, 0xd2 },
159 { OV9640_MTXS, 0x65 },
160};
161
162static enum v4l2_mbus_pixelcode ov9640_codes[] = {
163 V4L2_MBUS_FMT_UYVY8_2X8,
164 V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE,
165 V4L2_MBUS_FMT_RGB565_2X8_LE,
166};
167
168/* read a register */
169static int ov9640_reg_read(struct i2c_client *client, u8 reg, u8 *val)
170{
171 int ret;
172 u8 data = reg;
173 struct i2c_msg msg = {
174 .addr = client->addr,
175 .flags = 0,
176 .len = 1,
177 .buf = &data,
178 };
179
180 ret = i2c_transfer(client->adapter, &msg, 1);
181 if (ret < 0)
182 goto err;
183
184 msg.flags = I2C_M_RD;
185 ret = i2c_transfer(client->adapter, &msg, 1);
186 if (ret < 0)
187 goto err;
188
189 *val = data;
190 return 0;
191
192err:
193 dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
194 return ret;
195}
196
197/* write a register */
198static int ov9640_reg_write(struct i2c_client *client, u8 reg, u8 val)
199{
200 int ret;
201 u8 _val;
202 unsigned char data[2] = { reg, val };
203 struct i2c_msg msg = {
204 .addr = client->addr,
205 .flags = 0,
206 .len = 2,
207 .buf = data,
208 };
209
210 ret = i2c_transfer(client->adapter, &msg, 1);
211 if (ret < 0) {
212 dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
213 return ret;
214 }
215
216 /* we have to read the register back ... no idea why, maybe HW bug */
217 ret = ov9640_reg_read(client, reg, &_val);
218 if (ret)
219 dev_err(&client->dev,
220 "Failed reading back register 0x%02x!\n", reg);
221
222 return 0;
223}
224
225
226/* Read a register, alter its bits, write it back */
227static int ov9640_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 unset)
228{
229 u8 val;
230 int ret;
231
232 ret = ov9640_reg_read(client, reg, &val);
233 if (ret) {
234 dev_err(&client->dev,
235 "[Read]-Modify-Write of register %02x failed!\n", reg);
236 return val;
237 }
238
239 val |= set;
240 val &= ~unset;
241
242 ret = ov9640_reg_write(client, reg, val);
243 if (ret)
244 dev_err(&client->dev,
245 "Read-Modify-[Write] of register %02x failed!\n", reg);
246
247 return ret;
248}
249
250/* Soft reset the camera. This has nothing to do with the RESET pin! */
251static int ov9640_reset(struct i2c_client *client)
252{
253 int ret;
254
255 ret = ov9640_reg_write(client, OV9640_COM7, OV9640_COM7_SCCB_RESET);
256 if (ret)
257 dev_err(&client->dev,
258 "An error occurred while entering soft reset!\n");
259
260 return ret;
261}
262
263/* Start/Stop streaming from the device */
264static int ov9640_s_stream(struct v4l2_subdev *sd, int enable)
265{
266 return 0;
267}
268
269/* Set status of additional camera capabilities */
270static int ov9640_s_ctrl(struct v4l2_ctrl *ctrl)
271{
272 struct ov9640_priv *priv = container_of(ctrl->handler, struct ov9640_priv, hdl);
273 struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev);
274
275 switch (ctrl->id) {
276 case V4L2_CID_VFLIP:
277 if (ctrl->val)
278 return ov9640_reg_rmw(client, OV9640_MVFP,
279 OV9640_MVFP_V, 0);
280 return ov9640_reg_rmw(client, OV9640_MVFP, 0, OV9640_MVFP_V);
281 case V4L2_CID_HFLIP:
282 if (ctrl->val)
283 return ov9640_reg_rmw(client, OV9640_MVFP,
284 OV9640_MVFP_H, 0);
285 return ov9640_reg_rmw(client, OV9640_MVFP, 0, OV9640_MVFP_H);
286 }
287 return -EINVAL;
288}
289
290/* Get chip identification */
291static int ov9640_g_chip_ident(struct v4l2_subdev *sd,
292 struct v4l2_dbg_chip_ident *id)
293{
294 struct ov9640_priv *priv = to_ov9640_sensor(sd);
295
296 id->ident = priv->model;
297 id->revision = priv->revision;
298
299 return 0;
300}
301
302#ifdef CONFIG_VIDEO_ADV_DEBUG
303static int ov9640_get_register(struct v4l2_subdev *sd,
304 struct v4l2_dbg_register *reg)
305{
306 struct i2c_client *client = v4l2_get_subdevdata(sd);
307 int ret;
308 u8 val;
309
310 if (reg->reg & ~0xff)
311 return -EINVAL;
312
313 reg->size = 1;
314
315 ret = ov9640_reg_read(client, reg->reg, &val);
316 if (ret)
317 return ret;
318
319 reg->val = (__u64)val;
320
321 return 0;
322}
323
324static int ov9640_set_register(struct v4l2_subdev *sd,
325 struct v4l2_dbg_register *reg)
326{
327 struct i2c_client *client = v4l2_get_subdevdata(sd);
328
329 if (reg->reg & ~0xff || reg->val & ~0xff)
330 return -EINVAL;
331
332 return ov9640_reg_write(client, reg->reg, reg->val);
333}
334#endif
335
336/* select nearest higher resolution for capture */
337static void ov9640_res_roundup(u32 *width, u32 *height)
338{
339 int i;
340 enum { QQCIF, QQVGA, QCIF, QVGA, CIF, VGA, SXGA };
341 int res_x[] = { 88, 160, 176, 320, 352, 640, 1280 };
342 int res_y[] = { 72, 120, 144, 240, 288, 480, 960 };
343
344 for (i = 0; i < ARRAY_SIZE(res_x); i++) {
345 if (res_x[i] >= *width && res_y[i] >= *height) {
346 *width = res_x[i];
347 *height = res_y[i];
348 return;
349 }
350 }
351
352 *width = res_x[SXGA];
353 *height = res_y[SXGA];
354}
355
356/* Prepare necessary register changes depending on color encoding */
357static void ov9640_alter_regs(enum v4l2_mbus_pixelcode code,
358 struct ov9640_reg_alt *alt)
359{
360 switch (code) {
361 default:
362 case V4L2_MBUS_FMT_UYVY8_2X8:
363 alt->com12 = OV9640_COM12_YUV_AVG;
364 alt->com13 = OV9640_COM13_Y_DELAY_EN |
365 OV9640_COM13_YUV_DLY(0x01);
366 break;
367 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
368 alt->com7 = OV9640_COM7_RGB;
369 alt->com13 = OV9640_COM13_RGB_AVG;
370 alt->com15 = OV9640_COM15_RGB_555;
371 break;
372 case V4L2_MBUS_FMT_RGB565_2X8_LE:
373 alt->com7 = OV9640_COM7_RGB;
374 alt->com13 = OV9640_COM13_RGB_AVG;
375 alt->com15 = OV9640_COM15_RGB_565;
376 break;
377 };
378}
379
380/* Setup registers according to resolution and color encoding */
381static int ov9640_write_regs(struct i2c_client *client, u32 width,
382 enum v4l2_mbus_pixelcode code, struct ov9640_reg_alt *alts)
383{
384 const struct ov9640_reg *ov9640_regs, *matrix_regs;
385 int ov9640_regs_len, matrix_regs_len;
386 int i, ret;
387 u8 val;
388
389 /* select register configuration for given resolution */
390 switch (width) {
391 case W_QQCIF:
392 ov9640_regs = ov9640_regs_qqcif;
393 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qqcif);
394 break;
395 case W_QQVGA:
396 ov9640_regs = ov9640_regs_qqvga;
397 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qqvga);
398 break;
399 case W_QCIF:
400 ov9640_regs = ov9640_regs_qcif;
401 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qcif);
402 break;
403 case W_QVGA:
404 ov9640_regs = ov9640_regs_qvga;
405 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qvga);
406 break;
407 case W_CIF:
408 ov9640_regs = ov9640_regs_cif;
409 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_cif);
410 break;
411 case W_VGA:
412 ov9640_regs = ov9640_regs_vga;
413 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_vga);
414 break;
415 case W_SXGA:
416 ov9640_regs = ov9640_regs_sxga;
417 ov9640_regs_len = ARRAY_SIZE(ov9640_regs_sxga);
418 break;
419 default:
420 dev_err(&client->dev, "Failed to select resolution!\n");
421 return -EINVAL;
422 }
423
424 /* select color matrix configuration for given color encoding */
425 if (code == V4L2_MBUS_FMT_UYVY8_2X8) {
426 matrix_regs = ov9640_regs_yuv;
427 matrix_regs_len = ARRAY_SIZE(ov9640_regs_yuv);
428 } else {
429 matrix_regs = ov9640_regs_rgb;
430 matrix_regs_len = ARRAY_SIZE(ov9640_regs_rgb);
431 }
432
433 /* write register settings into the module */
434 for (i = 0; i < ov9640_regs_len; i++) {
435 val = ov9640_regs[i].val;
436
437 switch (ov9640_regs[i].reg) {
438 case OV9640_COM7:
439 val |= alts->com7;
440 break;
441 case OV9640_COM12:
442 val |= alts->com12;
443 break;
444 case OV9640_COM13:
445 val |= alts->com13;
446 break;
447 case OV9640_COM15:
448 val |= alts->com15;
449 break;
450 }
451
452 ret = ov9640_reg_write(client, ov9640_regs[i].reg, val);
453 if (ret)
454 return ret;
455 }
456
457 /* write color matrix configuration into the module */
458 for (i = 0; i < matrix_regs_len; i++) {
459 ret = ov9640_reg_write(client, matrix_regs[i].reg,
460 matrix_regs[i].val);
461 if (ret)
462 return ret;
463 }
464
465 return 0;
466}
467
468/* program default register values */
469static int ov9640_prog_dflt(struct i2c_client *client)
470{
471 int i, ret;
472
473 for (i = 0; i < ARRAY_SIZE(ov9640_regs_dflt); i++) {
474 ret = ov9640_reg_write(client, ov9640_regs_dflt[i].reg,
475 ov9640_regs_dflt[i].val);
476 if (ret)
477 return ret;
478 }
479
480 /* wait for the changes to actually happen, 140ms are not enough yet */
481 mdelay(150);
482
483 return 0;
484}
485
486/* set the format we will capture in */
487static int ov9640_s_fmt(struct v4l2_subdev *sd,
488 struct v4l2_mbus_framefmt *mf)
489{
490 struct i2c_client *client = v4l2_get_subdevdata(sd);
491 struct ov9640_reg_alt alts = {0};
492 enum v4l2_colorspace cspace;
493 enum v4l2_mbus_pixelcode code = mf->code;
494 int ret;
495
496 ov9640_res_roundup(&mf->width, &mf->height);
497 ov9640_alter_regs(mf->code, &alts);
498
499 ov9640_reset(client);
500
501 ret = ov9640_prog_dflt(client);
502 if (ret)
503 return ret;
504
505 switch (code) {
506 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
507 case V4L2_MBUS_FMT_RGB565_2X8_LE:
508 cspace = V4L2_COLORSPACE_SRGB;
509 break;
510 default:
511 code = V4L2_MBUS_FMT_UYVY8_2X8;
512 case V4L2_MBUS_FMT_UYVY8_2X8:
513 cspace = V4L2_COLORSPACE_JPEG;
514 }
515
516 ret = ov9640_write_regs(client, mf->width, code, &alts);
517 if (!ret) {
518 mf->code = code;
519 mf->colorspace = cspace;
520 }
521
522 return ret;
523}
524
525static int ov9640_try_fmt(struct v4l2_subdev *sd,
526 struct v4l2_mbus_framefmt *mf)
527{
528 ov9640_res_roundup(&mf->width, &mf->height);
529
530 mf->field = V4L2_FIELD_NONE;
531
532 switch (mf->code) {
533 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
534 case V4L2_MBUS_FMT_RGB565_2X8_LE:
535 mf->colorspace = V4L2_COLORSPACE_SRGB;
536 break;
537 default:
538 mf->code = V4L2_MBUS_FMT_UYVY8_2X8;
539 case V4L2_MBUS_FMT_UYVY8_2X8:
540 mf->colorspace = V4L2_COLORSPACE_JPEG;
541 }
542
543 return 0;
544}
545
546static int ov9640_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
547 enum v4l2_mbus_pixelcode *code)
548{
549 if (index >= ARRAY_SIZE(ov9640_codes))
550 return -EINVAL;
551
552 *code = ov9640_codes[index];
553 return 0;
554}
555
556static int ov9640_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
557{
558 a->c.left = 0;
559 a->c.top = 0;
560 a->c.width = W_SXGA;
561 a->c.height = H_SXGA;
562 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
563
564 return 0;
565}
566
567static int ov9640_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
568{
569 a->bounds.left = 0;
570 a->bounds.top = 0;
571 a->bounds.width = W_SXGA;
572 a->bounds.height = H_SXGA;
573 a->defrect = a->bounds;
574 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
575 a->pixelaspect.numerator = 1;
576 a->pixelaspect.denominator = 1;
577
578 return 0;
579}
580
581static int ov9640_video_probe(struct i2c_client *client)
582{
583 struct v4l2_subdev *sd = i2c_get_clientdata(client);
584 struct ov9640_priv *priv = to_ov9640_sensor(sd);
585 u8 pid, ver, midh, midl;
586 const char *devname;
587 int ret = 0;
588
589 /*
590 * check and show product ID and manufacturer ID
591 */
592
593 ret = ov9640_reg_read(client, OV9640_PID, &pid);
594 if (!ret)
595 ret = ov9640_reg_read(client, OV9640_VER, &ver);
596 if (!ret)
597 ret = ov9640_reg_read(client, OV9640_MIDH, &midh);
598 if (!ret)
599 ret = ov9640_reg_read(client, OV9640_MIDL, &midl);
600 if (ret)
601 return ret;
602
603 switch (VERSION(pid, ver)) {
604 case OV9640_V2:
605 devname = "ov9640";
606 priv->model = V4L2_IDENT_OV9640;
607 priv->revision = 2;
608 break;
609 case OV9640_V3:
610 devname = "ov9640";
611 priv->model = V4L2_IDENT_OV9640;
612 priv->revision = 3;
613 break;
614 default:
615 dev_err(&client->dev, "Product ID error %x:%x\n", pid, ver);
616 return -ENODEV;
617 }
618
619 dev_info(&client->dev, "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
620 devname, pid, ver, midh, midl);
621
622 return v4l2_ctrl_handler_setup(&priv->hdl);
623}
624
625static const struct v4l2_ctrl_ops ov9640_ctrl_ops = {
626 .s_ctrl = ov9640_s_ctrl,
627};
628
629static struct v4l2_subdev_core_ops ov9640_core_ops = {
630 .g_chip_ident = ov9640_g_chip_ident,
631#ifdef CONFIG_VIDEO_ADV_DEBUG
632 .g_register = ov9640_get_register,
633 .s_register = ov9640_set_register,
634#endif
635
636};
637
638/* Request bus settings on camera side */
639static int ov9640_g_mbus_config(struct v4l2_subdev *sd,
640 struct v4l2_mbus_config *cfg)
641{
642 struct i2c_client *client = v4l2_get_subdevdata(sd);
643 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
644
645 cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
646 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
647 V4L2_MBUS_DATA_ACTIVE_HIGH;
648 cfg->type = V4L2_MBUS_PARALLEL;
649 cfg->flags = soc_camera_apply_board_flags(icl, cfg);
650
651 return 0;
652}
653
654static struct v4l2_subdev_video_ops ov9640_video_ops = {
655 .s_stream = ov9640_s_stream,
656 .s_mbus_fmt = ov9640_s_fmt,
657 .try_mbus_fmt = ov9640_try_fmt,
658 .enum_mbus_fmt = ov9640_enum_fmt,
659 .cropcap = ov9640_cropcap,
660 .g_crop = ov9640_g_crop,
661 .g_mbus_config = ov9640_g_mbus_config,
662};
663
664static struct v4l2_subdev_ops ov9640_subdev_ops = {
665 .core = &ov9640_core_ops,
666 .video = &ov9640_video_ops,
667};
668
669/*
670 * i2c_driver function
671 */
672static int ov9640_probe(struct i2c_client *client,
673 const struct i2c_device_id *did)
674{
675 struct ov9640_priv *priv;
676 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
677 int ret;
678
679 if (!icl) {
680 dev_err(&client->dev, "Missing platform_data for driver\n");
681 return -EINVAL;
682 }
683
684 priv = kzalloc(sizeof(struct ov9640_priv), GFP_KERNEL);
685 if (!priv) {
686 dev_err(&client->dev,
687 "Failed to allocate memory for private data!\n");
688 return -ENOMEM;
689 }
690
691 v4l2_i2c_subdev_init(&priv->subdev, client, &ov9640_subdev_ops);
692
693 v4l2_ctrl_handler_init(&priv->hdl, 2);
694 v4l2_ctrl_new_std(&priv->hdl, &ov9640_ctrl_ops,
695 V4L2_CID_VFLIP, 0, 1, 1, 0);
696 v4l2_ctrl_new_std(&priv->hdl, &ov9640_ctrl_ops,
697 V4L2_CID_HFLIP, 0, 1, 1, 0);
698 priv->subdev.ctrl_handler = &priv->hdl;
699 if (priv->hdl.error) {
700 int err = priv->hdl.error;
701
702 kfree(priv);
703 return err;
704 }
705
706 ret = ov9640_video_probe(client);
707
708 if (ret) {
709 v4l2_ctrl_handler_free(&priv->hdl);
710 kfree(priv);
711 }
712
713 return ret;
714}
715
716static int ov9640_remove(struct i2c_client *client)
717{
718 struct v4l2_subdev *sd = i2c_get_clientdata(client);
719 struct ov9640_priv *priv = to_ov9640_sensor(sd);
720
721 v4l2_device_unregister_subdev(&priv->subdev);
722 v4l2_ctrl_handler_free(&priv->hdl);
723 kfree(priv);
724 return 0;
725}
726
727static const struct i2c_device_id ov9640_id[] = {
728 { "ov9640", 0 },
729 { }
730};
731MODULE_DEVICE_TABLE(i2c, ov9640_id);
732
733static struct i2c_driver ov9640_i2c_driver = {
734 .driver = {
735 .name = "ov9640",
736 },
737 .probe = ov9640_probe,
738 .remove = ov9640_remove,
739 .id_table = ov9640_id,
740};
741
742module_i2c_driver(ov9640_i2c_driver);
743
744MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV96xx");
745MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
746MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/video/ov9640.h b/drivers/media/video/ov9640.h
deleted file mode 100644
index 6b33a972c83c..000000000000
--- a/drivers/media/video/ov9640.h
+++ /dev/null
@@ -1,207 +0,0 @@
1/*
2 * OmniVision OV96xx Camera Header File
3 *
4 * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __DRIVERS_MEDIA_VIDEO_OV9640_H__
12#define __DRIVERS_MEDIA_VIDEO_OV9640_H__
13
14/* Register definitions */
15#define OV9640_GAIN 0x00
16#define OV9640_BLUE 0x01
17#define OV9640_RED 0x02
18#define OV9640_VFER 0x03
19#define OV9640_COM1 0x04
20#define OV9640_BAVE 0x05
21#define OV9640_GEAVE 0x06
22#define OV9640_RSID 0x07
23#define OV9640_RAVE 0x08
24#define OV9640_COM2 0x09
25#define OV9640_PID 0x0a
26#define OV9640_VER 0x0b
27#define OV9640_COM3 0x0c
28#define OV9640_COM4 0x0d
29#define OV9640_COM5 0x0e
30#define OV9640_COM6 0x0f
31#define OV9640_AECH 0x10
32#define OV9640_CLKRC 0x11
33#define OV9640_COM7 0x12
34#define OV9640_COM8 0x13
35#define OV9640_COM9 0x14
36#define OV9640_COM10 0x15
37/* 0x16 - RESERVED */
38#define OV9640_HSTART 0x17
39#define OV9640_HSTOP 0x18
40#define OV9640_VSTART 0x19
41#define OV9640_VSTOP 0x1a
42#define OV9640_PSHFT 0x1b
43#define OV9640_MIDH 0x1c
44#define OV9640_MIDL 0x1d
45#define OV9640_MVFP 0x1e
46#define OV9640_LAEC 0x1f
47#define OV9640_BOS 0x20
48#define OV9640_GBOS 0x21
49#define OV9640_GROS 0x22
50#define OV9640_ROS 0x23
51#define OV9640_AEW 0x24
52#define OV9640_AEB 0x25
53#define OV9640_VPT 0x26
54#define OV9640_BBIAS 0x27
55#define OV9640_GBBIAS 0x28
56/* 0x29 - RESERVED */
57#define OV9640_EXHCH 0x2a
58#define OV9640_EXHCL 0x2b
59#define OV9640_RBIAS 0x2c
60#define OV9640_ADVFL 0x2d
61#define OV9640_ADVFH 0x2e
62#define OV9640_YAVE 0x2f
63#define OV9640_HSYST 0x30
64#define OV9640_HSYEN 0x31
65#define OV9640_HREF 0x32
66#define OV9640_CHLF 0x33
67#define OV9640_ARBLM 0x34
68/* 0x35..0x36 - RESERVED */
69#define OV9640_ADC 0x37
70#define OV9640_ACOM 0x38
71#define OV9640_OFON 0x39
72#define OV9640_TSLB 0x3a
73#define OV9640_COM11 0x3b
74#define OV9640_COM12 0x3c
75#define OV9640_COM13 0x3d
76#define OV9640_COM14 0x3e
77#define OV9640_EDGE 0x3f
78#define OV9640_COM15 0x40
79#define OV9640_COM16 0x41
80#define OV9640_COM17 0x42
81/* 0x43..0x4e - RESERVED */
82#define OV9640_MTX1 0x4f
83#define OV9640_MTX2 0x50
84#define OV9640_MTX3 0x51
85#define OV9640_MTX4 0x52
86#define OV9640_MTX5 0x53
87#define OV9640_MTX6 0x54
88#define OV9640_MTX7 0x55
89#define OV9640_MTX8 0x56
90#define OV9640_MTX9 0x57
91#define OV9640_MTXS 0x58
92/* 0x59..0x61 - RESERVED */
93#define OV9640_LCC1 0x62
94#define OV9640_LCC2 0x63
95#define OV9640_LCC3 0x64
96#define OV9640_LCC4 0x65
97#define OV9640_LCC5 0x66
98#define OV9640_MANU 0x67
99#define OV9640_MANV 0x68
100#define OV9640_HV 0x69
101#define OV9640_MBD 0x6a
102#define OV9640_DBLV 0x6b
103#define OV9640_GSP 0x6c /* ... till 0x7b */
104#define OV9640_GST 0x7c /* ... till 0x8a */
105
106#define OV9640_CLKRC_DPLL_EN 0x80
107#define OV9640_CLKRC_DIRECT 0x40
108#define OV9640_CLKRC_DIV(x) ((x) & 0x3f)
109
110#define OV9640_PSHFT_VAL(x) ((x) & 0xff)
111
112#define OV9640_ACOM_2X_ANALOG 0x80
113#define OV9640_ACOM_RSVD 0x12
114
115#define OV9640_MVFP_V 0x10
116#define OV9640_MVFP_H 0x20
117
118#define OV9640_COM1_HREF_NOSKIP 0x00
119#define OV9640_COM1_HREF_2SKIP 0x04
120#define OV9640_COM1_HREF_3SKIP 0x08
121#define OV9640_COM1_QQFMT 0x20
122
123#define OV9640_COM2_SSM 0x10
124
125#define OV9640_COM3_VP 0x04
126
127#define OV9640_COM4_QQ_VP 0x80
128#define OV9640_COM4_RSVD 0x40
129
130#define OV9640_COM5_SYSCLK 0x80
131#define OV9640_COM5_LONGEXP 0x01
132
133#define OV9640_COM6_OPT_BLC 0x40
134#define OV9640_COM6_ADBLC_BIAS 0x08
135#define OV9640_COM6_FMT_RST 0x82
136#define OV9640_COM6_ADBLC_OPTEN 0x01
137
138#define OV9640_COM7_RAW_RGB 0x01
139#define OV9640_COM7_RGB 0x04
140#define OV9640_COM7_QCIF 0x08
141#define OV9640_COM7_QVGA 0x10
142#define OV9640_COM7_CIF 0x20
143#define OV9640_COM7_VGA 0x40
144#define OV9640_COM7_SCCB_RESET 0x80
145
146#define OV9640_TSLB_YVYU_YUYV 0x04
147#define OV9640_TSLB_YUYV_UYVY 0x08
148
149#define OV9640_COM12_YUV_AVG 0x04
150#define OV9640_COM12_RSVD 0x40
151
152#define OV9640_COM13_GAMMA_NONE 0x00
153#define OV9640_COM13_GAMMA_Y 0x40
154#define OV9640_COM13_GAMMA_RAW 0x80
155#define OV9640_COM13_RGB_AVG 0x20
156#define OV9640_COM13_MATRIX_EN 0x10
157#define OV9640_COM13_Y_DELAY_EN 0x08
158#define OV9640_COM13_YUV_DLY(x) ((x) & 0x07)
159
160#define OV9640_COM15_OR_00FF 0x00
161#define OV9640_COM15_OR_01FE 0x40
162#define OV9640_COM15_OR_10F0 0xc0
163#define OV9640_COM15_RGB_NORM 0x00
164#define OV9640_COM15_RGB_565 0x10
165#define OV9640_COM15_RGB_555 0x30
166
167#define OV9640_COM16_RB_AVG 0x01
168
169/* IDs */
170#define OV9640_V2 0x9648
171#define OV9640_V3 0x9649
172#define VERSION(pid, ver) (((pid) << 8) | ((ver) & 0xFF))
173
174/* supported resolutions */
175enum {
176 W_QQCIF = 88,
177 W_QQVGA = 160,
178 W_QCIF = 176,
179 W_QVGA = 320,
180 W_CIF = 352,
181 W_VGA = 640,
182 W_SXGA = 1280
183};
184#define H_SXGA 960
185
186/* Misc. structures */
187struct ov9640_reg_alt {
188 u8 com7;
189 u8 com12;
190 u8 com13;
191 u8 com15;
192};
193
194struct ov9640_reg {
195 u8 reg;
196 u8 val;
197};
198
199struct ov9640_priv {
200 struct v4l2_subdev subdev;
201 struct v4l2_ctrl_handler hdl;
202
203 int model;
204 int revision;
205};
206
207#endif /* __DRIVERS_MEDIA_VIDEO_OV9640_H__ */
diff --git a/drivers/media/video/ov9740.c b/drivers/media/video/ov9740.c
deleted file mode 100644
index 3eb07c22516e..000000000000
--- a/drivers/media/video/ov9740.c
+++ /dev/null
@@ -1,1005 +0,0 @@
1/*
2 * OmniVision OV9740 Camera Driver
3 *
4 * Copyright (C) 2011 NVIDIA Corporation
5 *
6 * Based on ov9640 camera driver.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/i2c.h>
16#include <linux/slab.h>
17#include <linux/v4l2-mediabus.h>
18
19#include <media/soc_camera.h>
20#include <media/v4l2-chip-ident.h>
21#include <media/v4l2-ctrls.h>
22
23#define to_ov9740(sd) container_of(sd, struct ov9740_priv, subdev)
24
25/* General Status Registers */
26#define OV9740_MODEL_ID_HI 0x0000
27#define OV9740_MODEL_ID_LO 0x0001
28#define OV9740_REVISION_NUMBER 0x0002
29#define OV9740_MANUFACTURER_ID 0x0003
30#define OV9740_SMIA_VERSION 0x0004
31
32/* General Setup Registers */
33#define OV9740_MODE_SELECT 0x0100
34#define OV9740_IMAGE_ORT 0x0101
35#define OV9740_SOFTWARE_RESET 0x0103
36#define OV9740_GRP_PARAM_HOLD 0x0104
37#define OV9740_MSK_CORRUP_FM 0x0105
38
39/* Timing Setting */
40#define OV9740_FRM_LENGTH_LN_HI 0x0340 /* VTS */
41#define OV9740_FRM_LENGTH_LN_LO 0x0341 /* VTS */
42#define OV9740_LN_LENGTH_PCK_HI 0x0342 /* HTS */
43#define OV9740_LN_LENGTH_PCK_LO 0x0343 /* HTS */
44#define OV9740_X_ADDR_START_HI 0x0344
45#define OV9740_X_ADDR_START_LO 0x0345
46#define OV9740_Y_ADDR_START_HI 0x0346
47#define OV9740_Y_ADDR_START_LO 0x0347
48#define OV9740_X_ADDR_END_HI 0x0348
49#define OV9740_X_ADDR_END_LO 0x0349
50#define OV9740_Y_ADDR_END_HI 0x034a
51#define OV9740_Y_ADDR_END_LO 0x034b
52#define OV9740_X_OUTPUT_SIZE_HI 0x034c
53#define OV9740_X_OUTPUT_SIZE_LO 0x034d
54#define OV9740_Y_OUTPUT_SIZE_HI 0x034e
55#define OV9740_Y_OUTPUT_SIZE_LO 0x034f
56
57/* IO Control Registers */
58#define OV9740_IO_CREL00 0x3002
59#define OV9740_IO_CREL01 0x3004
60#define OV9740_IO_CREL02 0x3005
61#define OV9740_IO_OUTPUT_SEL01 0x3026
62#define OV9740_IO_OUTPUT_SEL02 0x3027
63
64/* AWB Registers */
65#define OV9740_AWB_MANUAL_CTRL 0x3406
66
67/* Analog Control Registers */
68#define OV9740_ANALOG_CTRL01 0x3601
69#define OV9740_ANALOG_CTRL02 0x3602
70#define OV9740_ANALOG_CTRL03 0x3603
71#define OV9740_ANALOG_CTRL04 0x3604
72#define OV9740_ANALOG_CTRL10 0x3610
73#define OV9740_ANALOG_CTRL12 0x3612
74#define OV9740_ANALOG_CTRL15 0x3615
75#define OV9740_ANALOG_CTRL20 0x3620
76#define OV9740_ANALOG_CTRL21 0x3621
77#define OV9740_ANALOG_CTRL22 0x3622
78#define OV9740_ANALOG_CTRL30 0x3630
79#define OV9740_ANALOG_CTRL31 0x3631
80#define OV9740_ANALOG_CTRL32 0x3632
81#define OV9740_ANALOG_CTRL33 0x3633
82
83/* Sensor Control */
84#define OV9740_SENSOR_CTRL03 0x3703
85#define OV9740_SENSOR_CTRL04 0x3704
86#define OV9740_SENSOR_CTRL05 0x3705
87#define OV9740_SENSOR_CTRL07 0x3707
88
89/* Timing Control */
90#define OV9740_TIMING_CTRL17 0x3817
91#define OV9740_TIMING_CTRL19 0x3819
92#define OV9740_TIMING_CTRL33 0x3833
93#define OV9740_TIMING_CTRL35 0x3835
94
95/* Banding Filter */
96#define OV9740_AEC_MAXEXPO_60_H 0x3a02
97#define OV9740_AEC_MAXEXPO_60_L 0x3a03
98#define OV9740_AEC_B50_STEP_HI 0x3a08
99#define OV9740_AEC_B50_STEP_LO 0x3a09
100#define OV9740_AEC_B60_STEP_HI 0x3a0a
101#define OV9740_AEC_B60_STEP_LO 0x3a0b
102#define OV9740_AEC_CTRL0D 0x3a0d
103#define OV9740_AEC_CTRL0E 0x3a0e
104#define OV9740_AEC_MAXEXPO_50_H 0x3a14
105#define OV9740_AEC_MAXEXPO_50_L 0x3a15
106
107/* AEC/AGC Control */
108#define OV9740_AEC_ENABLE 0x3503
109#define OV9740_GAIN_CEILING_01 0x3a18
110#define OV9740_GAIN_CEILING_02 0x3a19
111#define OV9740_AEC_HI_THRESHOLD 0x3a11
112#define OV9740_AEC_3A1A 0x3a1a
113#define OV9740_AEC_CTRL1B_WPT2 0x3a1b
114#define OV9740_AEC_CTRL0F_WPT 0x3a0f
115#define OV9740_AEC_CTRL10_BPT 0x3a10
116#define OV9740_AEC_CTRL1E_BPT2 0x3a1e
117#define OV9740_AEC_LO_THRESHOLD 0x3a1f
118
119/* BLC Control */
120#define OV9740_BLC_AUTO_ENABLE 0x4002
121#define OV9740_BLC_MODE 0x4005
122
123/* VFIFO */
124#define OV9740_VFIFO_READ_START_HI 0x4608
125#define OV9740_VFIFO_READ_START_LO 0x4609
126
127/* DVP Control */
128#define OV9740_DVP_VSYNC_CTRL02 0x4702
129#define OV9740_DVP_VSYNC_MODE 0x4704
130#define OV9740_DVP_VSYNC_CTRL06 0x4706
131
132/* PLL Setting */
133#define OV9740_PLL_MODE_CTRL01 0x3104
134#define OV9740_PRE_PLL_CLK_DIV 0x0305
135#define OV9740_PLL_MULTIPLIER 0x0307
136#define OV9740_VT_SYS_CLK_DIV 0x0303
137#define OV9740_VT_PIX_CLK_DIV 0x0301
138#define OV9740_PLL_CTRL3010 0x3010
139#define OV9740_VFIFO_CTRL00 0x460e
140
141/* ISP Control */
142#define OV9740_ISP_CTRL00 0x5000
143#define OV9740_ISP_CTRL01 0x5001
144#define OV9740_ISP_CTRL03 0x5003
145#define OV9740_ISP_CTRL05 0x5005
146#define OV9740_ISP_CTRL12 0x5012
147#define OV9740_ISP_CTRL19 0x5019
148#define OV9740_ISP_CTRL1A 0x501a
149#define OV9740_ISP_CTRL1E 0x501e
150#define OV9740_ISP_CTRL1F 0x501f
151#define OV9740_ISP_CTRL20 0x5020
152#define OV9740_ISP_CTRL21 0x5021
153
154/* AWB */
155#define OV9740_AWB_CTRL00 0x5180
156#define OV9740_AWB_CTRL01 0x5181
157#define OV9740_AWB_CTRL02 0x5182
158#define OV9740_AWB_CTRL03 0x5183
159#define OV9740_AWB_ADV_CTRL01 0x5184
160#define OV9740_AWB_ADV_CTRL02 0x5185
161#define OV9740_AWB_ADV_CTRL03 0x5186
162#define OV9740_AWB_ADV_CTRL04 0x5187
163#define OV9740_AWB_ADV_CTRL05 0x5188
164#define OV9740_AWB_ADV_CTRL06 0x5189
165#define OV9740_AWB_ADV_CTRL07 0x518a
166#define OV9740_AWB_ADV_CTRL08 0x518b
167#define OV9740_AWB_ADV_CTRL09 0x518c
168#define OV9740_AWB_ADV_CTRL10 0x518d
169#define OV9740_AWB_ADV_CTRL11 0x518e
170#define OV9740_AWB_CTRL0F 0x518f
171#define OV9740_AWB_CTRL10 0x5190
172#define OV9740_AWB_CTRL11 0x5191
173#define OV9740_AWB_CTRL12 0x5192
174#define OV9740_AWB_CTRL13 0x5193
175#define OV9740_AWB_CTRL14 0x5194
176
177/* MIPI Control */
178#define OV9740_MIPI_CTRL00 0x4800
179#define OV9740_MIPI_3837 0x3837
180#define OV9740_MIPI_CTRL01 0x4801
181#define OV9740_MIPI_CTRL03 0x4803
182#define OV9740_MIPI_CTRL05 0x4805
183#define OV9740_VFIFO_RD_CTRL 0x4601
184#define OV9740_MIPI_CTRL_3012 0x3012
185#define OV9740_SC_CMMM_MIPI_CTR 0x3014
186
187#define OV9740_MAX_WIDTH 1280
188#define OV9740_MAX_HEIGHT 720
189
190/* Misc. structures */
191struct ov9740_reg {
192 u16 reg;
193 u8 val;
194};
195
196struct ov9740_priv {
197 struct v4l2_subdev subdev;
198 struct v4l2_ctrl_handler hdl;
199
200 int ident;
201 u16 model;
202 u8 revision;
203 u8 manid;
204 u8 smiaver;
205
206 bool flag_vflip;
207 bool flag_hflip;
208
209 /* For suspend/resume. */
210 struct v4l2_mbus_framefmt current_mf;
211 bool current_enable;
212};
213
214static const struct ov9740_reg ov9740_defaults[] = {
215 /* Software Reset */
216 { OV9740_SOFTWARE_RESET, 0x01 },
217
218 /* Banding Filter */
219 { OV9740_AEC_B50_STEP_HI, 0x00 },
220 { OV9740_AEC_B50_STEP_LO, 0xe8 },
221 { OV9740_AEC_CTRL0E, 0x03 },
222 { OV9740_AEC_MAXEXPO_50_H, 0x15 },
223 { OV9740_AEC_MAXEXPO_50_L, 0xc6 },
224 { OV9740_AEC_B60_STEP_HI, 0x00 },
225 { OV9740_AEC_B60_STEP_LO, 0xc0 },
226 { OV9740_AEC_CTRL0D, 0x04 },
227 { OV9740_AEC_MAXEXPO_60_H, 0x18 },
228 { OV9740_AEC_MAXEXPO_60_L, 0x20 },
229
230 /* LC */
231 { 0x5842, 0x02 }, { 0x5843, 0x5e }, { 0x5844, 0x04 }, { 0x5845, 0x32 },
232 { 0x5846, 0x03 }, { 0x5847, 0x29 }, { 0x5848, 0x02 }, { 0x5849, 0xcc },
233
234 /* Un-documented OV9740 registers */
235 { 0x5800, 0x29 }, { 0x5801, 0x25 }, { 0x5802, 0x20 }, { 0x5803, 0x21 },
236 { 0x5804, 0x26 }, { 0x5805, 0x2e }, { 0x5806, 0x11 }, { 0x5807, 0x0c },
237 { 0x5808, 0x09 }, { 0x5809, 0x0a }, { 0x580a, 0x0e }, { 0x580b, 0x16 },
238 { 0x580c, 0x06 }, { 0x580d, 0x02 }, { 0x580e, 0x00 }, { 0x580f, 0x00 },
239 { 0x5810, 0x04 }, { 0x5811, 0x0a }, { 0x5812, 0x05 }, { 0x5813, 0x02 },
240 { 0x5814, 0x00 }, { 0x5815, 0x00 }, { 0x5816, 0x03 }, { 0x5817, 0x09 },
241 { 0x5818, 0x0f }, { 0x5819, 0x0a }, { 0x581a, 0x07 }, { 0x581b, 0x08 },
242 { 0x581c, 0x0b }, { 0x581d, 0x14 }, { 0x581e, 0x28 }, { 0x581f, 0x23 },
243 { 0x5820, 0x1d }, { 0x5821, 0x1e }, { 0x5822, 0x24 }, { 0x5823, 0x2a },
244 { 0x5824, 0x4f }, { 0x5825, 0x6f }, { 0x5826, 0x5f }, { 0x5827, 0x7f },
245 { 0x5828, 0x9f }, { 0x5829, 0x5f }, { 0x582a, 0x8f }, { 0x582b, 0x9e },
246 { 0x582c, 0x8f }, { 0x582d, 0x9f }, { 0x582e, 0x4f }, { 0x582f, 0x87 },
247 { 0x5830, 0x86 }, { 0x5831, 0x97 }, { 0x5832, 0xae }, { 0x5833, 0x3f },
248 { 0x5834, 0x8e }, { 0x5835, 0x7c }, { 0x5836, 0x7e }, { 0x5837, 0xaf },
249 { 0x5838, 0x8f }, { 0x5839, 0x8f }, { 0x583a, 0x9f }, { 0x583b, 0x7f },
250 { 0x583c, 0x5f },
251
252 /* Y Gamma */
253 { 0x5480, 0x07 }, { 0x5481, 0x18 }, { 0x5482, 0x2c }, { 0x5483, 0x4e },
254 { 0x5484, 0x5e }, { 0x5485, 0x6b }, { 0x5486, 0x77 }, { 0x5487, 0x82 },
255 { 0x5488, 0x8c }, { 0x5489, 0x95 }, { 0x548a, 0xa4 }, { 0x548b, 0xb1 },
256 { 0x548c, 0xc6 }, { 0x548d, 0xd8 }, { 0x548e, 0xe9 },
257
258 /* UV Gamma */
259 { 0x5490, 0x0f }, { 0x5491, 0xff }, { 0x5492, 0x0d }, { 0x5493, 0x05 },
260 { 0x5494, 0x07 }, { 0x5495, 0x1a }, { 0x5496, 0x04 }, { 0x5497, 0x01 },
261 { 0x5498, 0x03 }, { 0x5499, 0x53 }, { 0x549a, 0x02 }, { 0x549b, 0xeb },
262 { 0x549c, 0x02 }, { 0x549d, 0xa0 }, { 0x549e, 0x02 }, { 0x549f, 0x67 },
263 { 0x54a0, 0x02 }, { 0x54a1, 0x3b }, { 0x54a2, 0x02 }, { 0x54a3, 0x18 },
264 { 0x54a4, 0x01 }, { 0x54a5, 0xe7 }, { 0x54a6, 0x01 }, { 0x54a7, 0xc3 },
265 { 0x54a8, 0x01 }, { 0x54a9, 0x94 }, { 0x54aa, 0x01 }, { 0x54ab, 0x72 },
266 { 0x54ac, 0x01 }, { 0x54ad, 0x57 },
267
268 /* AWB */
269 { OV9740_AWB_CTRL00, 0xf0 },
270 { OV9740_AWB_CTRL01, 0x00 },
271 { OV9740_AWB_CTRL02, 0x41 },
272 { OV9740_AWB_CTRL03, 0x42 },
273 { OV9740_AWB_ADV_CTRL01, 0x8a },
274 { OV9740_AWB_ADV_CTRL02, 0x61 },
275 { OV9740_AWB_ADV_CTRL03, 0xce },
276 { OV9740_AWB_ADV_CTRL04, 0xa8 },
277 { OV9740_AWB_ADV_CTRL05, 0x17 },
278 { OV9740_AWB_ADV_CTRL06, 0x1f },
279 { OV9740_AWB_ADV_CTRL07, 0x27 },
280 { OV9740_AWB_ADV_CTRL08, 0x41 },
281 { OV9740_AWB_ADV_CTRL09, 0x34 },
282 { OV9740_AWB_ADV_CTRL10, 0xf0 },
283 { OV9740_AWB_ADV_CTRL11, 0x10 },
284 { OV9740_AWB_CTRL0F, 0xff },
285 { OV9740_AWB_CTRL10, 0x00 },
286 { OV9740_AWB_CTRL11, 0xff },
287 { OV9740_AWB_CTRL12, 0x00 },
288 { OV9740_AWB_CTRL13, 0xff },
289 { OV9740_AWB_CTRL14, 0x00 },
290
291 /* CIP */
292 { 0x530d, 0x12 },
293
294 /* CMX */
295 { 0x5380, 0x01 }, { 0x5381, 0x00 }, { 0x5382, 0x00 }, { 0x5383, 0x17 },
296 { 0x5384, 0x00 }, { 0x5385, 0x01 }, { 0x5386, 0x00 }, { 0x5387, 0x00 },
297 { 0x5388, 0x00 }, { 0x5389, 0xe0 }, { 0x538a, 0x00 }, { 0x538b, 0x20 },
298 { 0x538c, 0x00 }, { 0x538d, 0x00 }, { 0x538e, 0x00 }, { 0x538f, 0x16 },
299 { 0x5390, 0x00 }, { 0x5391, 0x9c }, { 0x5392, 0x00 }, { 0x5393, 0xa0 },
300 { 0x5394, 0x18 },
301
302 /* 50/60 Detection */
303 { 0x3c0a, 0x9c }, { 0x3c0b, 0x3f },
304
305 /* Output Select */
306 { OV9740_IO_OUTPUT_SEL01, 0x00 },
307 { OV9740_IO_OUTPUT_SEL02, 0x00 },
308 { OV9740_IO_CREL00, 0x00 },
309 { OV9740_IO_CREL01, 0x00 },
310 { OV9740_IO_CREL02, 0x00 },
311
312 /* AWB Control */
313 { OV9740_AWB_MANUAL_CTRL, 0x00 },
314
315 /* Analog Control */
316 { OV9740_ANALOG_CTRL03, 0xaa },
317 { OV9740_ANALOG_CTRL32, 0x2f },
318 { OV9740_ANALOG_CTRL20, 0x66 },
319 { OV9740_ANALOG_CTRL21, 0xc0 },
320 { OV9740_ANALOG_CTRL31, 0x52 },
321 { OV9740_ANALOG_CTRL33, 0x50 },
322 { OV9740_ANALOG_CTRL30, 0xca },
323 { OV9740_ANALOG_CTRL04, 0x0c },
324 { OV9740_ANALOG_CTRL01, 0x40 },
325 { OV9740_ANALOG_CTRL02, 0x16 },
326 { OV9740_ANALOG_CTRL10, 0xa1 },
327 { OV9740_ANALOG_CTRL12, 0x24 },
328 { OV9740_ANALOG_CTRL22, 0x9f },
329 { OV9740_ANALOG_CTRL15, 0xf0 },
330
331 /* Sensor Control */
332 { OV9740_SENSOR_CTRL03, 0x42 },
333 { OV9740_SENSOR_CTRL04, 0x10 },
334 { OV9740_SENSOR_CTRL05, 0x45 },
335 { OV9740_SENSOR_CTRL07, 0x14 },
336
337 /* Timing Control */
338 { OV9740_TIMING_CTRL33, 0x04 },
339 { OV9740_TIMING_CTRL35, 0x02 },
340 { OV9740_TIMING_CTRL19, 0x6e },
341 { OV9740_TIMING_CTRL17, 0x94 },
342
343 /* AEC/AGC Control */
344 { OV9740_AEC_ENABLE, 0x10 },
345 { OV9740_GAIN_CEILING_01, 0x00 },
346 { OV9740_GAIN_CEILING_02, 0x7f },
347 { OV9740_AEC_HI_THRESHOLD, 0xa0 },
348 { OV9740_AEC_3A1A, 0x05 },
349 { OV9740_AEC_CTRL1B_WPT2, 0x50 },
350 { OV9740_AEC_CTRL0F_WPT, 0x50 },
351 { OV9740_AEC_CTRL10_BPT, 0x4c },
352 { OV9740_AEC_CTRL1E_BPT2, 0x4c },
353 { OV9740_AEC_LO_THRESHOLD, 0x26 },
354
355 /* BLC Control */
356 { OV9740_BLC_AUTO_ENABLE, 0x45 },
357 { OV9740_BLC_MODE, 0x18 },
358
359 /* DVP Control */
360 { OV9740_DVP_VSYNC_CTRL02, 0x04 },
361 { OV9740_DVP_VSYNC_MODE, 0x00 },
362 { OV9740_DVP_VSYNC_CTRL06, 0x08 },
363
364 /* PLL Setting */
365 { OV9740_PLL_MODE_CTRL01, 0x20 },
366 { OV9740_PRE_PLL_CLK_DIV, 0x03 },
367 { OV9740_PLL_MULTIPLIER, 0x4c },
368 { OV9740_VT_SYS_CLK_DIV, 0x01 },
369 { OV9740_VT_PIX_CLK_DIV, 0x08 },
370 { OV9740_PLL_CTRL3010, 0x01 },
371 { OV9740_VFIFO_CTRL00, 0x82 },
372
373 /* Timing Setting */
374 /* VTS */
375 { OV9740_FRM_LENGTH_LN_HI, 0x03 },
376 { OV9740_FRM_LENGTH_LN_LO, 0x07 },
377 /* HTS */
378 { OV9740_LN_LENGTH_PCK_HI, 0x06 },
379 { OV9740_LN_LENGTH_PCK_LO, 0x62 },
380
381 /* MIPI Control */
382 { OV9740_MIPI_CTRL00, 0x44 }, /* 0x64 for discontinuous clk */
383 { OV9740_MIPI_3837, 0x01 },
384 { OV9740_MIPI_CTRL01, 0x0f },
385 { OV9740_MIPI_CTRL03, 0x05 },
386 { OV9740_MIPI_CTRL05, 0x10 },
387 { OV9740_VFIFO_RD_CTRL, 0x16 },
388 { OV9740_MIPI_CTRL_3012, 0x70 },
389 { OV9740_SC_CMMM_MIPI_CTR, 0x01 },
390
391 /* YUYV order */
392 { OV9740_ISP_CTRL19, 0x02 },
393};
394
395static enum v4l2_mbus_pixelcode ov9740_codes[] = {
396 V4L2_MBUS_FMT_YUYV8_2X8,
397};
398
399/* read a register */
400static int ov9740_reg_read(struct i2c_client *client, u16 reg, u8 *val)
401{
402 int ret;
403 struct i2c_msg msg[] = {
404 {
405 .addr = client->addr,
406 .flags = 0,
407 .len = 2,
408 .buf = (u8 *)&reg,
409 },
410 {
411 .addr = client->addr,
412 .flags = I2C_M_RD,
413 .len = 1,
414 .buf = val,
415 },
416 };
417
418 reg = swab16(reg);
419
420 ret = i2c_transfer(client->adapter, msg, 2);
421 if (ret < 0) {
422 dev_err(&client->dev, "Failed reading register 0x%04x!\n", reg);
423 return ret;
424 }
425
426 return 0;
427}
428
429/* write a register */
430static int ov9740_reg_write(struct i2c_client *client, u16 reg, u8 val)
431{
432 struct i2c_msg msg;
433 struct {
434 u16 reg;
435 u8 val;
436 } __packed buf;
437 int ret;
438
439 reg = swab16(reg);
440
441 buf.reg = reg;
442 buf.val = val;
443
444 msg.addr = client->addr;
445 msg.flags = 0;
446 msg.len = 3;
447 msg.buf = (u8 *)&buf;
448
449 ret = i2c_transfer(client->adapter, &msg, 1);
450 if (ret < 0) {
451 dev_err(&client->dev, "Failed writing register 0x%04x!\n", reg);
452 return ret;
453 }
454
455 return 0;
456}
457
458
459/* Read a register, alter its bits, write it back */
460static int ov9740_reg_rmw(struct i2c_client *client, u16 reg, u8 set, u8 unset)
461{
462 u8 val;
463 int ret;
464
465 ret = ov9740_reg_read(client, reg, &val);
466 if (ret < 0) {
467 dev_err(&client->dev,
468 "[Read]-Modify-Write of register 0x%04x failed!\n",
469 reg);
470 return ret;
471 }
472
473 val |= set;
474 val &= ~unset;
475
476 ret = ov9740_reg_write(client, reg, val);
477 if (ret < 0) {
478 dev_err(&client->dev,
479 "Read-Modify-[Write] of register 0x%04x failed!\n",
480 reg);
481 return ret;
482 }
483
484 return 0;
485}
486
487static int ov9740_reg_write_array(struct i2c_client *client,
488 const struct ov9740_reg *regarray,
489 int regarraylen)
490{
491 int i;
492 int ret;
493
494 for (i = 0; i < regarraylen; i++) {
495 ret = ov9740_reg_write(client,
496 regarray[i].reg, regarray[i].val);
497 if (ret < 0)
498 return ret;
499 }
500
501 return 0;
502}
503
504/* Start/Stop streaming from the device */
505static int ov9740_s_stream(struct v4l2_subdev *sd, int enable)
506{
507 struct i2c_client *client = v4l2_get_subdevdata(sd);
508 struct ov9740_priv *priv = to_ov9740(sd);
509 int ret;
510
511 /* Program orientation register. */
512 if (priv->flag_vflip)
513 ret = ov9740_reg_rmw(client, OV9740_IMAGE_ORT, 0x2, 0);
514 else
515 ret = ov9740_reg_rmw(client, OV9740_IMAGE_ORT, 0, 0x2);
516 if (ret < 0)
517 return ret;
518
519 if (priv->flag_hflip)
520 ret = ov9740_reg_rmw(client, OV9740_IMAGE_ORT, 0x1, 0);
521 else
522 ret = ov9740_reg_rmw(client, OV9740_IMAGE_ORT, 0, 0x1);
523 if (ret < 0)
524 return ret;
525
526 if (enable) {
527 dev_dbg(&client->dev, "Enabling Streaming\n");
528 /* Start Streaming */
529 ret = ov9740_reg_write(client, OV9740_MODE_SELECT, 0x01);
530
531 } else {
532 dev_dbg(&client->dev, "Disabling Streaming\n");
533 /* Software Reset */
534 ret = ov9740_reg_write(client, OV9740_SOFTWARE_RESET, 0x01);
535 if (!ret)
536 /* Setting Streaming to Standby */
537 ret = ov9740_reg_write(client, OV9740_MODE_SELECT,
538 0x00);
539 }
540
541 priv->current_enable = enable;
542
543 return ret;
544}
545
546/* select nearest higher resolution for capture */
547static void ov9740_res_roundup(u32 *width, u32 *height)
548{
549 /* Width must be a multiple of 4 pixels. */
550 *width = ALIGN(*width, 4);
551
552 /* Max resolution is 1280x720 (720p). */
553 if (*width > OV9740_MAX_WIDTH)
554 *width = OV9740_MAX_WIDTH;
555
556 if (*height > OV9740_MAX_HEIGHT)
557 *height = OV9740_MAX_HEIGHT;
558}
559
560/* Setup registers according to resolution and color encoding */
561static int ov9740_set_res(struct i2c_client *client, u32 width, u32 height)
562{
563 u32 x_start;
564 u32 y_start;
565 u32 x_end;
566 u32 y_end;
567 bool scaling = 0;
568 u32 scale_input_x;
569 u32 scale_input_y;
570 int ret;
571
572 if ((width != OV9740_MAX_WIDTH) || (height != OV9740_MAX_HEIGHT))
573 scaling = 1;
574
575 /*
576 * Try to use as much of the sensor area as possible when supporting
577 * smaller resolutions. Depending on the aspect ratio of the
578 * chosen resolution, we can either use the full width of the sensor,
579 * or the full height of the sensor (or both if the aspect ratio is
580 * the same as 1280x720.
581 */
582 if ((OV9740_MAX_WIDTH * height) > (OV9740_MAX_HEIGHT * width)) {
583 scale_input_x = (OV9740_MAX_HEIGHT * width) / height;
584 scale_input_y = OV9740_MAX_HEIGHT;
585 } else {
586 scale_input_x = OV9740_MAX_WIDTH;
587 scale_input_y = (OV9740_MAX_WIDTH * height) / width;
588 }
589
590 /* These describe the area of the sensor to use. */
591 x_start = (OV9740_MAX_WIDTH - scale_input_x) / 2;
592 y_start = (OV9740_MAX_HEIGHT - scale_input_y) / 2;
593 x_end = x_start + scale_input_x - 1;
594 y_end = y_start + scale_input_y - 1;
595
596 ret = ov9740_reg_write(client, OV9740_X_ADDR_START_HI, x_start >> 8);
597 if (ret)
598 goto done;
599 ret = ov9740_reg_write(client, OV9740_X_ADDR_START_LO, x_start & 0xff);
600 if (ret)
601 goto done;
602 ret = ov9740_reg_write(client, OV9740_Y_ADDR_START_HI, y_start >> 8);
603 if (ret)
604 goto done;
605 ret = ov9740_reg_write(client, OV9740_Y_ADDR_START_LO, y_start & 0xff);
606 if (ret)
607 goto done;
608
609 ret = ov9740_reg_write(client, OV9740_X_ADDR_END_HI, x_end >> 8);
610 if (ret)
611 goto done;
612 ret = ov9740_reg_write(client, OV9740_X_ADDR_END_LO, x_end & 0xff);
613 if (ret)
614 goto done;
615 ret = ov9740_reg_write(client, OV9740_Y_ADDR_END_HI, y_end >> 8);
616 if (ret)
617 goto done;
618 ret = ov9740_reg_write(client, OV9740_Y_ADDR_END_LO, y_end & 0xff);
619 if (ret)
620 goto done;
621
622 ret = ov9740_reg_write(client, OV9740_X_OUTPUT_SIZE_HI, width >> 8);
623 if (ret)
624 goto done;
625 ret = ov9740_reg_write(client, OV9740_X_OUTPUT_SIZE_LO, width & 0xff);
626 if (ret)
627 goto done;
628 ret = ov9740_reg_write(client, OV9740_Y_OUTPUT_SIZE_HI, height >> 8);
629 if (ret)
630 goto done;
631 ret = ov9740_reg_write(client, OV9740_Y_OUTPUT_SIZE_LO, height & 0xff);
632 if (ret)
633 goto done;
634
635 ret = ov9740_reg_write(client, OV9740_ISP_CTRL1E, scale_input_x >> 8);
636 if (ret)
637 goto done;
638 ret = ov9740_reg_write(client, OV9740_ISP_CTRL1F, scale_input_x & 0xff);
639 if (ret)
640 goto done;
641 ret = ov9740_reg_write(client, OV9740_ISP_CTRL20, scale_input_y >> 8);
642 if (ret)
643 goto done;
644 ret = ov9740_reg_write(client, OV9740_ISP_CTRL21, scale_input_y & 0xff);
645 if (ret)
646 goto done;
647
648 ret = ov9740_reg_write(client, OV9740_VFIFO_READ_START_HI,
649 (scale_input_x - width) >> 8);
650 if (ret)
651 goto done;
652 ret = ov9740_reg_write(client, OV9740_VFIFO_READ_START_LO,
653 (scale_input_x - width) & 0xff);
654 if (ret)
655 goto done;
656
657 ret = ov9740_reg_write(client, OV9740_ISP_CTRL00, 0xff);
658 if (ret)
659 goto done;
660 ret = ov9740_reg_write(client, OV9740_ISP_CTRL01, 0xef |
661 (scaling << 4));
662 if (ret)
663 goto done;
664 ret = ov9740_reg_write(client, OV9740_ISP_CTRL03, 0xff);
665
666done:
667 return ret;
668}
669
670/* set the format we will capture in */
671static int ov9740_s_fmt(struct v4l2_subdev *sd,
672 struct v4l2_mbus_framefmt *mf)
673{
674 struct i2c_client *client = v4l2_get_subdevdata(sd);
675 struct ov9740_priv *priv = to_ov9740(sd);
676 enum v4l2_colorspace cspace;
677 enum v4l2_mbus_pixelcode code = mf->code;
678 int ret;
679
680 ov9740_res_roundup(&mf->width, &mf->height);
681
682 switch (code) {
683 case V4L2_MBUS_FMT_YUYV8_2X8:
684 cspace = V4L2_COLORSPACE_SRGB;
685 break;
686 default:
687 return -EINVAL;
688 }
689
690 ret = ov9740_reg_write_array(client, ov9740_defaults,
691 ARRAY_SIZE(ov9740_defaults));
692 if (ret < 0)
693 return ret;
694
695 ret = ov9740_set_res(client, mf->width, mf->height);
696 if (ret < 0)
697 return ret;
698
699 mf->code = code;
700 mf->colorspace = cspace;
701
702 memcpy(&priv->current_mf, mf, sizeof(struct v4l2_mbus_framefmt));
703
704 return ret;
705}
706
707static int ov9740_try_fmt(struct v4l2_subdev *sd,
708 struct v4l2_mbus_framefmt *mf)
709{
710 ov9740_res_roundup(&mf->width, &mf->height);
711
712 mf->field = V4L2_FIELD_NONE;
713 mf->code = V4L2_MBUS_FMT_YUYV8_2X8;
714 mf->colorspace = V4L2_COLORSPACE_SRGB;
715
716 return 0;
717}
718
719static int ov9740_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
720 enum v4l2_mbus_pixelcode *code)
721{
722 if (index >= ARRAY_SIZE(ov9740_codes))
723 return -EINVAL;
724
725 *code = ov9740_codes[index];
726
727 return 0;
728}
729
730static int ov9740_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
731{
732 a->bounds.left = 0;
733 a->bounds.top = 0;
734 a->bounds.width = OV9740_MAX_WIDTH;
735 a->bounds.height = OV9740_MAX_HEIGHT;
736 a->defrect = a->bounds;
737 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
738 a->pixelaspect.numerator = 1;
739 a->pixelaspect.denominator = 1;
740
741 return 0;
742}
743
744static int ov9740_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
745{
746 a->c.left = 0;
747 a->c.top = 0;
748 a->c.width = OV9740_MAX_WIDTH;
749 a->c.height = OV9740_MAX_HEIGHT;
750 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
751
752 return 0;
753}
754
755/* Set status of additional camera capabilities */
756static int ov9740_s_ctrl(struct v4l2_ctrl *ctrl)
757{
758 struct ov9740_priv *priv =
759 container_of(ctrl->handler, struct ov9740_priv, hdl);
760
761 switch (ctrl->id) {
762 case V4L2_CID_VFLIP:
763 priv->flag_vflip = ctrl->val;
764 break;
765 case V4L2_CID_HFLIP:
766 priv->flag_hflip = ctrl->val;
767 break;
768 default:
769 return -EINVAL;
770 }
771
772 return 0;
773}
774
775/* Get chip identification */
776static int ov9740_g_chip_ident(struct v4l2_subdev *sd,
777 struct v4l2_dbg_chip_ident *id)
778{
779 struct ov9740_priv *priv = to_ov9740(sd);
780
781 id->ident = priv->ident;
782 id->revision = priv->revision;
783
784 return 0;
785}
786
787static int ov9740_s_power(struct v4l2_subdev *sd, int on)
788{
789 struct ov9740_priv *priv = to_ov9740(sd);
790
791 if (!priv->current_enable)
792 return 0;
793
794 if (on) {
795 ov9740_s_fmt(sd, &priv->current_mf);
796 ov9740_s_stream(sd, priv->current_enable);
797 } else {
798 ov9740_s_stream(sd, 0);
799 priv->current_enable = true;
800 }
801
802 return 0;
803}
804
805#ifdef CONFIG_VIDEO_ADV_DEBUG
806static int ov9740_get_register(struct v4l2_subdev *sd,
807 struct v4l2_dbg_register *reg)
808{
809 struct i2c_client *client = v4l2_get_subdevdata(sd);
810 int ret;
811 u8 val;
812
813 if (reg->reg & ~0xffff)
814 return -EINVAL;
815
816 reg->size = 2;
817
818 ret = ov9740_reg_read(client, reg->reg, &val);
819 if (ret)
820 return ret;
821
822 reg->val = (__u64)val;
823
824 return ret;
825}
826
827static int ov9740_set_register(struct v4l2_subdev *sd,
828 struct v4l2_dbg_register *reg)
829{
830 struct i2c_client *client = v4l2_get_subdevdata(sd);
831
832 if (reg->reg & ~0xffff || reg->val & ~0xff)
833 return -EINVAL;
834
835 return ov9740_reg_write(client, reg->reg, reg->val);
836}
837#endif
838
839static int ov9740_video_probe(struct i2c_client *client)
840{
841 struct v4l2_subdev *sd = i2c_get_clientdata(client);
842 struct ov9740_priv *priv = to_ov9740(sd);
843 u8 modelhi, modello;
844 int ret;
845
846 /*
847 * check and show product ID and manufacturer ID
848 */
849 ret = ov9740_reg_read(client, OV9740_MODEL_ID_HI, &modelhi);
850 if (ret < 0)
851 goto err;
852
853 ret = ov9740_reg_read(client, OV9740_MODEL_ID_LO, &modello);
854 if (ret < 0)
855 goto err;
856
857 priv->model = (modelhi << 8) | modello;
858
859 ret = ov9740_reg_read(client, OV9740_REVISION_NUMBER, &priv->revision);
860 if (ret < 0)
861 goto err;
862
863 ret = ov9740_reg_read(client, OV9740_MANUFACTURER_ID, &priv->manid);
864 if (ret < 0)
865 goto err;
866
867 ret = ov9740_reg_read(client, OV9740_SMIA_VERSION, &priv->smiaver);
868 if (ret < 0)
869 goto err;
870
871 if (priv->model != 0x9740) {
872 ret = -ENODEV;
873 goto err;
874 }
875
876 priv->ident = V4L2_IDENT_OV9740;
877
878 dev_info(&client->dev, "ov9740 Model ID 0x%04x, Revision 0x%02x, "
879 "Manufacturer 0x%02x, SMIA Version 0x%02x\n",
880 priv->model, priv->revision, priv->manid, priv->smiaver);
881
882err:
883 return ret;
884}
885
886/* Request bus settings on camera side */
887static int ov9740_g_mbus_config(struct v4l2_subdev *sd,
888 struct v4l2_mbus_config *cfg)
889{
890 struct i2c_client *client = v4l2_get_subdevdata(sd);
891 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
892
893 cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
894 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
895 V4L2_MBUS_DATA_ACTIVE_HIGH;
896 cfg->type = V4L2_MBUS_PARALLEL;
897 cfg->flags = soc_camera_apply_board_flags(icl, cfg);
898
899 return 0;
900}
901
902static struct v4l2_subdev_video_ops ov9740_video_ops = {
903 .s_stream = ov9740_s_stream,
904 .s_mbus_fmt = ov9740_s_fmt,
905 .try_mbus_fmt = ov9740_try_fmt,
906 .enum_mbus_fmt = ov9740_enum_fmt,
907 .cropcap = ov9740_cropcap,
908 .g_crop = ov9740_g_crop,
909 .g_mbus_config = ov9740_g_mbus_config,
910};
911
912static struct v4l2_subdev_core_ops ov9740_core_ops = {
913 .g_chip_ident = ov9740_g_chip_ident,
914 .s_power = ov9740_s_power,
915#ifdef CONFIG_VIDEO_ADV_DEBUG
916 .g_register = ov9740_get_register,
917 .s_register = ov9740_set_register,
918#endif
919};
920
921static struct v4l2_subdev_ops ov9740_subdev_ops = {
922 .core = &ov9740_core_ops,
923 .video = &ov9740_video_ops,
924};
925
926static const struct v4l2_ctrl_ops ov9740_ctrl_ops = {
927 .s_ctrl = ov9740_s_ctrl,
928};
929
930/*
931 * i2c_driver function
932 */
933static int ov9740_probe(struct i2c_client *client,
934 const struct i2c_device_id *did)
935{
936 struct ov9740_priv *priv;
937 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
938 int ret;
939
940 if (!icl) {
941 dev_err(&client->dev, "Missing platform_data for driver\n");
942 return -EINVAL;
943 }
944
945 priv = kzalloc(sizeof(struct ov9740_priv), GFP_KERNEL);
946 if (!priv) {
947 dev_err(&client->dev, "Failed to allocate private data!\n");
948 return -ENOMEM;
949 }
950
951 v4l2_i2c_subdev_init(&priv->subdev, client, &ov9740_subdev_ops);
952 v4l2_ctrl_handler_init(&priv->hdl, 13);
953 v4l2_ctrl_new_std(&priv->hdl, &ov9740_ctrl_ops,
954 V4L2_CID_VFLIP, 0, 1, 1, 0);
955 v4l2_ctrl_new_std(&priv->hdl, &ov9740_ctrl_ops,
956 V4L2_CID_HFLIP, 0, 1, 1, 0);
957 priv->subdev.ctrl_handler = &priv->hdl;
958 if (priv->hdl.error) {
959 int err = priv->hdl.error;
960
961 kfree(priv);
962 return err;
963 }
964
965 ret = ov9740_video_probe(client);
966 if (!ret)
967 ret = v4l2_ctrl_handler_setup(&priv->hdl);
968 if (ret < 0) {
969 v4l2_ctrl_handler_free(&priv->hdl);
970 kfree(priv);
971 }
972
973 return ret;
974}
975
976static int ov9740_remove(struct i2c_client *client)
977{
978 struct ov9740_priv *priv = i2c_get_clientdata(client);
979
980 v4l2_device_unregister_subdev(&priv->subdev);
981 v4l2_ctrl_handler_free(&priv->hdl);
982 kfree(priv);
983 return 0;
984}
985
986static const struct i2c_device_id ov9740_id[] = {
987 { "ov9740", 0 },
988 { }
989};
990MODULE_DEVICE_TABLE(i2c, ov9740_id);
991
992static struct i2c_driver ov9740_i2c_driver = {
993 .driver = {
994 .name = "ov9740",
995 },
996 .probe = ov9740_probe,
997 .remove = ov9740_remove,
998 .id_table = ov9740_id,
999};
1000
1001module_i2c_driver(ov9740_i2c_driver);
1002
1003MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV9740");
1004MODULE_AUTHOR("Andrew Chew <achew@nvidia.com>");
1005MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/video/rj54n1cb0c.c b/drivers/media/video/rj54n1cb0c.c
deleted file mode 100644
index f6419b22c258..000000000000
--- a/drivers/media/video/rj54n1cb0c.c
+++ /dev/null
@@ -1,1414 +0,0 @@
1/*
2 * Driver for RJ54N1CB0C CMOS Image Sensor from Sharp
3 *
4 * Copyright (C) 2009, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/delay.h>
12#include <linux/i2c.h>
13#include <linux/slab.h>
14#include <linux/v4l2-mediabus.h>
15#include <linux/videodev2.h>
16#include <linux/module.h>
17
18#include <media/rj54n1cb0c.h>
19#include <media/soc_camera.h>
20#include <media/v4l2-subdev.h>
21#include <media/v4l2-chip-ident.h>
22#include <media/v4l2-ctrls.h>
23
24#define RJ54N1_DEV_CODE 0x0400
25#define RJ54N1_DEV_CODE2 0x0401
26#define RJ54N1_OUT_SEL 0x0403
27#define RJ54N1_XY_OUTPUT_SIZE_S_H 0x0404
28#define RJ54N1_X_OUTPUT_SIZE_S_L 0x0405
29#define RJ54N1_Y_OUTPUT_SIZE_S_L 0x0406
30#define RJ54N1_XY_OUTPUT_SIZE_P_H 0x0407
31#define RJ54N1_X_OUTPUT_SIZE_P_L 0x0408
32#define RJ54N1_Y_OUTPUT_SIZE_P_L 0x0409
33#define RJ54N1_LINE_LENGTH_PCK_S_H 0x040a
34#define RJ54N1_LINE_LENGTH_PCK_S_L 0x040b
35#define RJ54N1_LINE_LENGTH_PCK_P_H 0x040c
36#define RJ54N1_LINE_LENGTH_PCK_P_L 0x040d
37#define RJ54N1_RESIZE_N 0x040e
38#define RJ54N1_RESIZE_N_STEP 0x040f
39#define RJ54N1_RESIZE_STEP 0x0410
40#define RJ54N1_RESIZE_HOLD_H 0x0411
41#define RJ54N1_RESIZE_HOLD_L 0x0412
42#define RJ54N1_H_OBEN_OFS 0x0413
43#define RJ54N1_V_OBEN_OFS 0x0414
44#define RJ54N1_RESIZE_CONTROL 0x0415
45#define RJ54N1_STILL_CONTROL 0x0417
46#define RJ54N1_INC_USE_SEL_H 0x0425
47#define RJ54N1_INC_USE_SEL_L 0x0426
48#define RJ54N1_MIRROR_STILL_MODE 0x0427
49#define RJ54N1_INIT_START 0x0428
50#define RJ54N1_SCALE_1_2_LEV 0x0429
51#define RJ54N1_SCALE_4_LEV 0x042a
52#define RJ54N1_Y_GAIN 0x04d8
53#define RJ54N1_APT_GAIN_UP 0x04fa
54#define RJ54N1_RA_SEL_UL 0x0530
55#define RJ54N1_BYTE_SWAP 0x0531
56#define RJ54N1_OUT_SIGPO 0x053b
57#define RJ54N1_WB_SEL_WEIGHT_I 0x054e
58#define RJ54N1_BIT8_WB 0x0569
59#define RJ54N1_HCAPS_WB 0x056a
60#define RJ54N1_VCAPS_WB 0x056b
61#define RJ54N1_HCAPE_WB 0x056c
62#define RJ54N1_VCAPE_WB 0x056d
63#define RJ54N1_EXPOSURE_CONTROL 0x058c
64#define RJ54N1_FRAME_LENGTH_S_H 0x0595
65#define RJ54N1_FRAME_LENGTH_S_L 0x0596
66#define RJ54N1_FRAME_LENGTH_P_H 0x0597
67#define RJ54N1_FRAME_LENGTH_P_L 0x0598
68#define RJ54N1_PEAK_H 0x05b7
69#define RJ54N1_PEAK_50 0x05b8
70#define RJ54N1_PEAK_60 0x05b9
71#define RJ54N1_PEAK_DIFF 0x05ba
72#define RJ54N1_IOC 0x05ef
73#define RJ54N1_TG_BYPASS 0x0700
74#define RJ54N1_PLL_L 0x0701
75#define RJ54N1_PLL_N 0x0702
76#define RJ54N1_PLL_EN 0x0704
77#define RJ54N1_RATIO_TG 0x0706
78#define RJ54N1_RATIO_T 0x0707
79#define RJ54N1_RATIO_R 0x0708
80#define RJ54N1_RAMP_TGCLK_EN 0x0709
81#define RJ54N1_OCLK_DSP 0x0710
82#define RJ54N1_RATIO_OP 0x0711
83#define RJ54N1_RATIO_O 0x0712
84#define RJ54N1_OCLK_SEL_EN 0x0713
85#define RJ54N1_CLK_RST 0x0717
86#define RJ54N1_RESET_STANDBY 0x0718
87#define RJ54N1_FWFLG 0x07fe
88
89#define E_EXCLK (1 << 7)
90#define SOFT_STDBY (1 << 4)
91#define SEN_RSTX (1 << 2)
92#define TG_RSTX (1 << 1)
93#define DSP_RSTX (1 << 0)
94
95#define RESIZE_HOLD_SEL (1 << 2)
96#define RESIZE_GO (1 << 1)
97
98/*
99 * When cropping, the camera automatically centers the cropped region, there
100 * doesn't seem to be a way to specify an explicit location of the rectangle.
101 */
102#define RJ54N1_COLUMN_SKIP 0
103#define RJ54N1_ROW_SKIP 0
104#define RJ54N1_MAX_WIDTH 1600
105#define RJ54N1_MAX_HEIGHT 1200
106
107#define PLL_L 2
108#define PLL_N 0x31
109
110/* I2C addresses: 0x50, 0x51, 0x60, 0x61 */
111
112/* RJ54N1CB0C has only one fixed colorspace per pixelcode */
113struct rj54n1_datafmt {
114 enum v4l2_mbus_pixelcode code;
115 enum v4l2_colorspace colorspace;
116};
117
118/* Find a data format by a pixel code in an array */
119static const struct rj54n1_datafmt *rj54n1_find_datafmt(
120 enum v4l2_mbus_pixelcode code, const struct rj54n1_datafmt *fmt,
121 int n)
122{
123 int i;
124 for (i = 0; i < n; i++)
125 if (fmt[i].code == code)
126 return fmt + i;
127
128 return NULL;
129}
130
131static const struct rj54n1_datafmt rj54n1_colour_fmts[] = {
132 {V4L2_MBUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_JPEG},
133 {V4L2_MBUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_JPEG},
134 {V4L2_MBUS_FMT_RGB565_2X8_LE, V4L2_COLORSPACE_SRGB},
135 {V4L2_MBUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_SRGB},
136 {V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE, V4L2_COLORSPACE_SRGB},
137 {V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_LE, V4L2_COLORSPACE_SRGB},
138 {V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_BE, V4L2_COLORSPACE_SRGB},
139 {V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_BE, V4L2_COLORSPACE_SRGB},
140 {V4L2_MBUS_FMT_SBGGR10_1X10, V4L2_COLORSPACE_SRGB},
141};
142
143struct rj54n1_clock_div {
144 u8 ratio_tg; /* can be 0 or an odd number */
145 u8 ratio_t;
146 u8 ratio_r;
147 u8 ratio_op;
148 u8 ratio_o;
149};
150
151struct rj54n1 {
152 struct v4l2_subdev subdev;
153 struct v4l2_ctrl_handler hdl;
154 struct rj54n1_clock_div clk_div;
155 const struct rj54n1_datafmt *fmt;
156 struct v4l2_rect rect; /* Sensor window */
157 unsigned int tgclk_mhz;
158 bool auto_wb;
159 unsigned short width; /* Output window */
160 unsigned short height;
161 unsigned short resize; /* Sensor * 1024 / resize = Output */
162 unsigned short scale;
163 u8 bank;
164};
165
166struct rj54n1_reg_val {
167 u16 reg;
168 u8 val;
169};
170
171static const struct rj54n1_reg_val bank_4[] = {
172 {0x417, 0},
173 {0x42c, 0},
174 {0x42d, 0xf0},
175 {0x42e, 0},
176 {0x42f, 0x50},
177 {0x430, 0xf5},
178 {0x431, 0x16},
179 {0x432, 0x20},
180 {0x433, 0},
181 {0x434, 0xc8},
182 {0x43c, 8},
183 {0x43e, 0x90},
184 {0x445, 0x83},
185 {0x4ba, 0x58},
186 {0x4bb, 4},
187 {0x4bc, 0x20},
188 {0x4db, 4},
189 {0x4fe, 2},
190};
191
192static const struct rj54n1_reg_val bank_5[] = {
193 {0x514, 0},
194 {0x516, 0},
195 {0x518, 0},
196 {0x51a, 0},
197 {0x51d, 0xff},
198 {0x56f, 0x28},
199 {0x575, 0x40},
200 {0x5bc, 0x48},
201 {0x5c1, 6},
202 {0x5e5, 0x11},
203 {0x5e6, 0x43},
204 {0x5e7, 0x33},
205 {0x5e8, 0x21},
206 {0x5e9, 0x30},
207 {0x5ea, 0x0},
208 {0x5eb, 0xa5},
209 {0x5ec, 0xff},
210 {0x5fe, 2},
211};
212
213static const struct rj54n1_reg_val bank_7[] = {
214 {0x70a, 0},
215 {0x714, 0xff},
216 {0x715, 0xff},
217 {0x716, 0x1f},
218 {0x7FE, 2},
219};
220
221static const struct rj54n1_reg_val bank_8[] = {
222 {0x800, 0x00},
223 {0x801, 0x01},
224 {0x802, 0x61},
225 {0x805, 0x00},
226 {0x806, 0x00},
227 {0x807, 0x00},
228 {0x808, 0x00},
229 {0x809, 0x01},
230 {0x80A, 0x61},
231 {0x80B, 0x00},
232 {0x80C, 0x01},
233 {0x80D, 0x00},
234 {0x80E, 0x00},
235 {0x80F, 0x00},
236 {0x810, 0x00},
237 {0x811, 0x01},
238 {0x812, 0x61},
239 {0x813, 0x00},
240 {0x814, 0x11},
241 {0x815, 0x00},
242 {0x816, 0x41},
243 {0x817, 0x00},
244 {0x818, 0x51},
245 {0x819, 0x01},
246 {0x81A, 0x1F},
247 {0x81B, 0x00},
248 {0x81C, 0x01},
249 {0x81D, 0x00},
250 {0x81E, 0x11},
251 {0x81F, 0x00},
252 {0x820, 0x41},
253 {0x821, 0x00},
254 {0x822, 0x51},
255 {0x823, 0x00},
256 {0x824, 0x00},
257 {0x825, 0x00},
258 {0x826, 0x47},
259 {0x827, 0x01},
260 {0x828, 0x4F},
261 {0x829, 0x00},
262 {0x82A, 0x00},
263 {0x82B, 0x00},
264 {0x82C, 0x30},
265 {0x82D, 0x00},
266 {0x82E, 0x40},
267 {0x82F, 0x00},
268 {0x830, 0xB3},
269 {0x831, 0x00},
270 {0x832, 0xE3},
271 {0x833, 0x00},
272 {0x834, 0x00},
273 {0x835, 0x00},
274 {0x836, 0x00},
275 {0x837, 0x00},
276 {0x838, 0x00},
277 {0x839, 0x01},
278 {0x83A, 0x61},
279 {0x83B, 0x00},
280 {0x83C, 0x01},
281 {0x83D, 0x00},
282 {0x83E, 0x00},
283 {0x83F, 0x00},
284 {0x840, 0x00},
285 {0x841, 0x01},
286 {0x842, 0x61},
287 {0x843, 0x00},
288 {0x844, 0x1D},
289 {0x845, 0x00},
290 {0x846, 0x00},
291 {0x847, 0x00},
292 {0x848, 0x00},
293 {0x849, 0x01},
294 {0x84A, 0x1F},
295 {0x84B, 0x00},
296 {0x84C, 0x05},
297 {0x84D, 0x00},
298 {0x84E, 0x19},
299 {0x84F, 0x01},
300 {0x850, 0x21},
301 {0x851, 0x01},
302 {0x852, 0x5D},
303 {0x853, 0x00},
304 {0x854, 0x00},
305 {0x855, 0x00},
306 {0x856, 0x19},
307 {0x857, 0x01},
308 {0x858, 0x21},
309 {0x859, 0x00},
310 {0x85A, 0x00},
311 {0x85B, 0x00},
312 {0x85C, 0x00},
313 {0x85D, 0x00},
314 {0x85E, 0x00},
315 {0x85F, 0x00},
316 {0x860, 0xB3},
317 {0x861, 0x00},
318 {0x862, 0xE3},
319 {0x863, 0x00},
320 {0x864, 0x00},
321 {0x865, 0x00},
322 {0x866, 0x00},
323 {0x867, 0x00},
324 {0x868, 0x00},
325 {0x869, 0xE2},
326 {0x86A, 0x00},
327 {0x86B, 0x01},
328 {0x86C, 0x06},
329 {0x86D, 0x00},
330 {0x86E, 0x00},
331 {0x86F, 0x00},
332 {0x870, 0x60},
333 {0x871, 0x8C},
334 {0x872, 0x10},
335 {0x873, 0x00},
336 {0x874, 0xE0},
337 {0x875, 0x00},
338 {0x876, 0x27},
339 {0x877, 0x01},
340 {0x878, 0x00},
341 {0x879, 0x00},
342 {0x87A, 0x00},
343 {0x87B, 0x03},
344 {0x87C, 0x00},
345 {0x87D, 0x00},
346 {0x87E, 0x00},
347 {0x87F, 0x00},
348 {0x880, 0x00},
349 {0x881, 0x00},
350 {0x882, 0x00},
351 {0x883, 0x00},
352 {0x884, 0x00},
353 {0x885, 0x00},
354 {0x886, 0xF8},
355 {0x887, 0x00},
356 {0x888, 0x03},
357 {0x889, 0x00},
358 {0x88A, 0x64},
359 {0x88B, 0x00},
360 {0x88C, 0x03},
361 {0x88D, 0x00},
362 {0x88E, 0xB1},
363 {0x88F, 0x00},
364 {0x890, 0x03},
365 {0x891, 0x01},
366 {0x892, 0x1D},
367 {0x893, 0x00},
368 {0x894, 0x03},
369 {0x895, 0x01},
370 {0x896, 0x4B},
371 {0x897, 0x00},
372 {0x898, 0xE5},
373 {0x899, 0x00},
374 {0x89A, 0x01},
375 {0x89B, 0x00},
376 {0x89C, 0x01},
377 {0x89D, 0x04},
378 {0x89E, 0xC8},
379 {0x89F, 0x00},
380 {0x8A0, 0x01},
381 {0x8A1, 0x01},
382 {0x8A2, 0x61},
383 {0x8A3, 0x00},
384 {0x8A4, 0x01},
385 {0x8A5, 0x00},
386 {0x8A6, 0x00},
387 {0x8A7, 0x00},
388 {0x8A8, 0x00},
389 {0x8A9, 0x00},
390 {0x8AA, 0x7F},
391 {0x8AB, 0x03},
392 {0x8AC, 0x00},
393 {0x8AD, 0x00},
394 {0x8AE, 0x00},
395 {0x8AF, 0x00},
396 {0x8B0, 0x00},
397 {0x8B1, 0x00},
398 {0x8B6, 0x00},
399 {0x8B7, 0x01},
400 {0x8B8, 0x00},
401 {0x8B9, 0x00},
402 {0x8BA, 0x02},
403 {0x8BB, 0x00},
404 {0x8BC, 0xFF},
405 {0x8BD, 0x00},
406 {0x8FE, 2},
407};
408
409static const struct rj54n1_reg_val bank_10[] = {
410 {0x10bf, 0x69}
411};
412
413/* Clock dividers - these are default register values, divider = register + 1 */
414static const struct rj54n1_clock_div clk_div = {
415 .ratio_tg = 3 /* default: 5 */,
416 .ratio_t = 4 /* default: 1 */,
417 .ratio_r = 4 /* default: 0 */,
418 .ratio_op = 1 /* default: 5 */,
419 .ratio_o = 9 /* default: 0 */,
420};
421
422static struct rj54n1 *to_rj54n1(const struct i2c_client *client)
423{
424 return container_of(i2c_get_clientdata(client), struct rj54n1, subdev);
425}
426
427static int reg_read(struct i2c_client *client, const u16 reg)
428{
429 struct rj54n1 *rj54n1 = to_rj54n1(client);
430 int ret;
431
432 /* set bank */
433 if (rj54n1->bank != reg >> 8) {
434 dev_dbg(&client->dev, "[0x%x] = 0x%x\n", 0xff, reg >> 8);
435 ret = i2c_smbus_write_byte_data(client, 0xff, reg >> 8);
436 if (ret < 0)
437 return ret;
438 rj54n1->bank = reg >> 8;
439 }
440 return i2c_smbus_read_byte_data(client, reg & 0xff);
441}
442
443static int reg_write(struct i2c_client *client, const u16 reg,
444 const u8 data)
445{
446 struct rj54n1 *rj54n1 = to_rj54n1(client);
447 int ret;
448
449 /* set bank */
450 if (rj54n1->bank != reg >> 8) {
451 dev_dbg(&client->dev, "[0x%x] = 0x%x\n", 0xff, reg >> 8);
452 ret = i2c_smbus_write_byte_data(client, 0xff, reg >> 8);
453 if (ret < 0)
454 return ret;
455 rj54n1->bank = reg >> 8;
456 }
457 dev_dbg(&client->dev, "[0x%x] = 0x%x\n", reg & 0xff, data);
458 return i2c_smbus_write_byte_data(client, reg & 0xff, data);
459}
460
461static int reg_set(struct i2c_client *client, const u16 reg,
462 const u8 data, const u8 mask)
463{
464 int ret;
465
466 ret = reg_read(client, reg);
467 if (ret < 0)
468 return ret;
469 return reg_write(client, reg, (ret & ~mask) | (data & mask));
470}
471
472static int reg_write_multiple(struct i2c_client *client,
473 const struct rj54n1_reg_val *rv, const int n)
474{
475 int i, ret;
476
477 for (i = 0; i < n; i++) {
478 ret = reg_write(client, rv->reg, rv->val);
479 if (ret < 0)
480 return ret;
481 rv++;
482 }
483
484 return 0;
485}
486
487static int rj54n1_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
488 enum v4l2_mbus_pixelcode *code)
489{
490 if (index >= ARRAY_SIZE(rj54n1_colour_fmts))
491 return -EINVAL;
492
493 *code = rj54n1_colour_fmts[index].code;
494 return 0;
495}
496
497static int rj54n1_s_stream(struct v4l2_subdev *sd, int enable)
498{
499 struct i2c_client *client = v4l2_get_subdevdata(sd);
500
501 /* Switch between preview and still shot modes */
502 return reg_set(client, RJ54N1_STILL_CONTROL, (!enable) << 7, 0x80);
503}
504
505static int rj54n1_set_rect(struct i2c_client *client,
506 u16 reg_x, u16 reg_y, u16 reg_xy,
507 u32 width, u32 height)
508{
509 int ret;
510
511 ret = reg_write(client, reg_xy,
512 ((width >> 4) & 0x70) |
513 ((height >> 8) & 7));
514
515 if (!ret)
516 ret = reg_write(client, reg_x, width & 0xff);
517 if (!ret)
518 ret = reg_write(client, reg_y, height & 0xff);
519
520 return ret;
521}
522
523/*
524 * Some commands, specifically certain initialisation sequences, require
525 * a commit operation.
526 */
527static int rj54n1_commit(struct i2c_client *client)
528{
529 int ret = reg_write(client, RJ54N1_INIT_START, 1);
530 msleep(10);
531 if (!ret)
532 ret = reg_write(client, RJ54N1_INIT_START, 0);
533 return ret;
534}
535
536static int rj54n1_sensor_scale(struct v4l2_subdev *sd, s32 *in_w, s32 *in_h,
537 s32 *out_w, s32 *out_h);
538
539static int rj54n1_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
540{
541 struct i2c_client *client = v4l2_get_subdevdata(sd);
542 struct rj54n1 *rj54n1 = to_rj54n1(client);
543 struct v4l2_rect *rect = &a->c;
544 int dummy = 0, output_w, output_h,
545 input_w = rect->width, input_h = rect->height;
546 int ret;
547
548 /* arbitrary minimum width and height, edges unimportant */
549 soc_camera_limit_side(&dummy, &input_w,
550 RJ54N1_COLUMN_SKIP, 8, RJ54N1_MAX_WIDTH);
551
552 soc_camera_limit_side(&dummy, &input_h,
553 RJ54N1_ROW_SKIP, 8, RJ54N1_MAX_HEIGHT);
554
555 output_w = (input_w * 1024 + rj54n1->resize / 2) / rj54n1->resize;
556 output_h = (input_h * 1024 + rj54n1->resize / 2) / rj54n1->resize;
557
558 dev_dbg(&client->dev, "Scaling for %dx%d : %u = %dx%d\n",
559 input_w, input_h, rj54n1->resize, output_w, output_h);
560
561 ret = rj54n1_sensor_scale(sd, &input_w, &input_h, &output_w, &output_h);
562 if (ret < 0)
563 return ret;
564
565 rj54n1->width = output_w;
566 rj54n1->height = output_h;
567 rj54n1->resize = ret;
568 rj54n1->rect.width = input_w;
569 rj54n1->rect.height = input_h;
570
571 return 0;
572}
573
574static int rj54n1_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
575{
576 struct i2c_client *client = v4l2_get_subdevdata(sd);
577 struct rj54n1 *rj54n1 = to_rj54n1(client);
578
579 a->c = rj54n1->rect;
580 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
581
582 return 0;
583}
584
585static int rj54n1_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
586{
587 a->bounds.left = RJ54N1_COLUMN_SKIP;
588 a->bounds.top = RJ54N1_ROW_SKIP;
589 a->bounds.width = RJ54N1_MAX_WIDTH;
590 a->bounds.height = RJ54N1_MAX_HEIGHT;
591 a->defrect = a->bounds;
592 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
593 a->pixelaspect.numerator = 1;
594 a->pixelaspect.denominator = 1;
595
596 return 0;
597}
598
599static int rj54n1_g_fmt(struct v4l2_subdev *sd,
600 struct v4l2_mbus_framefmt *mf)
601{
602 struct i2c_client *client = v4l2_get_subdevdata(sd);
603 struct rj54n1 *rj54n1 = to_rj54n1(client);
604
605 mf->code = rj54n1->fmt->code;
606 mf->colorspace = rj54n1->fmt->colorspace;
607 mf->field = V4L2_FIELD_NONE;
608 mf->width = rj54n1->width;
609 mf->height = rj54n1->height;
610
611 return 0;
612}
613
614/*
615 * The actual geometry configuration routine. It scales the input window into
616 * the output one, updates the window sizes and returns an error or the resize
617 * coefficient on success. Note: we only use the "Fixed Scaling" on this camera.
618 */
619static int rj54n1_sensor_scale(struct v4l2_subdev *sd, s32 *in_w, s32 *in_h,
620 s32 *out_w, s32 *out_h)
621{
622 struct i2c_client *client = v4l2_get_subdevdata(sd);
623 struct rj54n1 *rj54n1 = to_rj54n1(client);
624 unsigned int skip, resize, input_w = *in_w, input_h = *in_h,
625 output_w = *out_w, output_h = *out_h;
626 u16 inc_sel, wb_bit8, wb_left, wb_right, wb_top, wb_bottom;
627 unsigned int peak, peak_50, peak_60;
628 int ret;
629
630 /*
631 * We have a problem with crops, where the window is larger than 512x384
632 * and output window is larger than a half of the input one. In this
633 * case we have to either reduce the input window to equal or below
634 * 512x384 or the output window to equal or below 1/2 of the input.
635 */
636 if (output_w > max(512U, input_w / 2)) {
637 if (2 * output_w > RJ54N1_MAX_WIDTH) {
638 input_w = RJ54N1_MAX_WIDTH;
639 output_w = RJ54N1_MAX_WIDTH / 2;
640 } else {
641 input_w = output_w * 2;
642 }
643
644 dev_dbg(&client->dev, "Adjusted output width: in %u, out %u\n",
645 input_w, output_w);
646 }
647
648 if (output_h > max(384U, input_h / 2)) {
649 if (2 * output_h > RJ54N1_MAX_HEIGHT) {
650 input_h = RJ54N1_MAX_HEIGHT;
651 output_h = RJ54N1_MAX_HEIGHT / 2;
652 } else {
653 input_h = output_h * 2;
654 }
655
656 dev_dbg(&client->dev, "Adjusted output height: in %u, out %u\n",
657 input_h, output_h);
658 }
659
660 /* Idea: use the read mode for snapshots, handle separate geometries */
661 ret = rj54n1_set_rect(client, RJ54N1_X_OUTPUT_SIZE_S_L,
662 RJ54N1_Y_OUTPUT_SIZE_S_L,
663 RJ54N1_XY_OUTPUT_SIZE_S_H, output_w, output_h);
664 if (!ret)
665 ret = rj54n1_set_rect(client, RJ54N1_X_OUTPUT_SIZE_P_L,
666 RJ54N1_Y_OUTPUT_SIZE_P_L,
667 RJ54N1_XY_OUTPUT_SIZE_P_H, output_w, output_h);
668
669 if (ret < 0)
670 return ret;
671
672 if (output_w > input_w && output_h > input_h) {
673 input_w = output_w;
674 input_h = output_h;
675
676 resize = 1024;
677 } else {
678 unsigned int resize_x, resize_y;
679 resize_x = (input_w * 1024 + output_w / 2) / output_w;
680 resize_y = (input_h * 1024 + output_h / 2) / output_h;
681
682 /* We want max(resize_x, resize_y), check if it still fits */
683 if (resize_x > resize_y &&
684 (output_h * resize_x + 512) / 1024 > RJ54N1_MAX_HEIGHT)
685 resize = (RJ54N1_MAX_HEIGHT * 1024 + output_h / 2) /
686 output_h;
687 else if (resize_y > resize_x &&
688 (output_w * resize_y + 512) / 1024 > RJ54N1_MAX_WIDTH)
689 resize = (RJ54N1_MAX_WIDTH * 1024 + output_w / 2) /
690 output_w;
691 else
692 resize = max(resize_x, resize_y);
693
694 /* Prohibited value ranges */
695 switch (resize) {
696 case 2040 ... 2047:
697 resize = 2039;
698 break;
699 case 4080 ... 4095:
700 resize = 4079;
701 break;
702 case 8160 ... 8191:
703 resize = 8159;
704 break;
705 case 16320 ... 16384:
706 resize = 16319;
707 }
708 }
709
710 /* Set scaling */
711 ret = reg_write(client, RJ54N1_RESIZE_HOLD_L, resize & 0xff);
712 if (!ret)
713 ret = reg_write(client, RJ54N1_RESIZE_HOLD_H, resize >> 8);
714
715 if (ret < 0)
716 return ret;
717
718 /*
719 * Configure a skipping bitmask. The sensor will select a skipping value
720 * among set bits automatically. This is very unclear in the datasheet
721 * too. I was told, in this register one enables all skipping values,
722 * that are required for a specific resize, and the camera selects
723 * automatically, which ones to use. But it is unclear how to identify,
724 * which cropping values are needed. Secondly, why don't we just set all
725 * bits and let the camera choose? Would it increase processing time and
726 * reduce the framerate? Using 0xfffc for INC_USE_SEL doesn't seem to
727 * improve the image quality or stability for larger frames (see comment
728 * above), but I didn't check the framerate.
729 */
730 skip = min(resize / 1024, 15U);
731
732 inc_sel = 1 << skip;
733
734 if (inc_sel <= 2)
735 inc_sel = 0xc;
736 else if (resize & 1023 && skip < 15)
737 inc_sel |= 1 << (skip + 1);
738
739 ret = reg_write(client, RJ54N1_INC_USE_SEL_L, inc_sel & 0xfc);
740 if (!ret)
741 ret = reg_write(client, RJ54N1_INC_USE_SEL_H, inc_sel >> 8);
742
743 if (!rj54n1->auto_wb) {
744 /* Auto white balance window */
745 wb_left = output_w / 16;
746 wb_right = (3 * output_w / 4 - 3) / 4;
747 wb_top = output_h / 16;
748 wb_bottom = (3 * output_h / 4 - 3) / 4;
749 wb_bit8 = ((wb_left >> 2) & 0x40) | ((wb_top >> 4) & 0x10) |
750 ((wb_right >> 6) & 4) | ((wb_bottom >> 8) & 1);
751
752 if (!ret)
753 ret = reg_write(client, RJ54N1_BIT8_WB, wb_bit8);
754 if (!ret)
755 ret = reg_write(client, RJ54N1_HCAPS_WB, wb_left);
756 if (!ret)
757 ret = reg_write(client, RJ54N1_VCAPS_WB, wb_top);
758 if (!ret)
759 ret = reg_write(client, RJ54N1_HCAPE_WB, wb_right);
760 if (!ret)
761 ret = reg_write(client, RJ54N1_VCAPE_WB, wb_bottom);
762 }
763
764 /* Antiflicker */
765 peak = 12 * RJ54N1_MAX_WIDTH * (1 << 14) * resize / rj54n1->tgclk_mhz /
766 10000;
767 peak_50 = peak / 6;
768 peak_60 = peak / 5;
769
770 if (!ret)
771 ret = reg_write(client, RJ54N1_PEAK_H,
772 ((peak_50 >> 4) & 0xf0) | (peak_60 >> 8));
773 if (!ret)
774 ret = reg_write(client, RJ54N1_PEAK_50, peak_50);
775 if (!ret)
776 ret = reg_write(client, RJ54N1_PEAK_60, peak_60);
777 if (!ret)
778 ret = reg_write(client, RJ54N1_PEAK_DIFF, peak / 150);
779
780 /* Start resizing */
781 if (!ret)
782 ret = reg_write(client, RJ54N1_RESIZE_CONTROL,
783 RESIZE_HOLD_SEL | RESIZE_GO | 1);
784
785 if (ret < 0)
786 return ret;
787
788 /* Constant taken from manufacturer's example */
789 msleep(230);
790
791 ret = reg_write(client, RJ54N1_RESIZE_CONTROL, RESIZE_HOLD_SEL | 1);
792 if (ret < 0)
793 return ret;
794
795 *in_w = (output_w * resize + 512) / 1024;
796 *in_h = (output_h * resize + 512) / 1024;
797 *out_w = output_w;
798 *out_h = output_h;
799
800 dev_dbg(&client->dev, "Scaled for %dx%d : %u = %ux%u, skip %u\n",
801 *in_w, *in_h, resize, output_w, output_h, skip);
802
803 return resize;
804}
805
806static int rj54n1_set_clock(struct i2c_client *client)
807{
808 struct rj54n1 *rj54n1 = to_rj54n1(client);
809 int ret;
810
811 /* Enable external clock */
812 ret = reg_write(client, RJ54N1_RESET_STANDBY, E_EXCLK | SOFT_STDBY);
813 /* Leave stand-by. Note: use this when implementing suspend / resume */
814 if (!ret)
815 ret = reg_write(client, RJ54N1_RESET_STANDBY, E_EXCLK);
816
817 if (!ret)
818 ret = reg_write(client, RJ54N1_PLL_L, PLL_L);
819 if (!ret)
820 ret = reg_write(client, RJ54N1_PLL_N, PLL_N);
821
822 /* TGCLK dividers */
823 if (!ret)
824 ret = reg_write(client, RJ54N1_RATIO_TG,
825 rj54n1->clk_div.ratio_tg);
826 if (!ret)
827 ret = reg_write(client, RJ54N1_RATIO_T,
828 rj54n1->clk_div.ratio_t);
829 if (!ret)
830 ret = reg_write(client, RJ54N1_RATIO_R,
831 rj54n1->clk_div.ratio_r);
832
833 /* Enable TGCLK & RAMP */
834 if (!ret)
835 ret = reg_write(client, RJ54N1_RAMP_TGCLK_EN, 3);
836
837 /* Disable clock output */
838 if (!ret)
839 ret = reg_write(client, RJ54N1_OCLK_DSP, 0);
840
841 /* Set divisors */
842 if (!ret)
843 ret = reg_write(client, RJ54N1_RATIO_OP,
844 rj54n1->clk_div.ratio_op);
845 if (!ret)
846 ret = reg_write(client, RJ54N1_RATIO_O,
847 rj54n1->clk_div.ratio_o);
848
849 /* Enable OCLK */
850 if (!ret)
851 ret = reg_write(client, RJ54N1_OCLK_SEL_EN, 1);
852
853 /* Use PLL for Timing Generator, write 2 to reserved bits */
854 if (!ret)
855 ret = reg_write(client, RJ54N1_TG_BYPASS, 2);
856
857 /* Take sensor out of reset */
858 if (!ret)
859 ret = reg_write(client, RJ54N1_RESET_STANDBY,
860 E_EXCLK | SEN_RSTX);
861 /* Enable PLL */
862 if (!ret)
863 ret = reg_write(client, RJ54N1_PLL_EN, 1);
864
865 /* Wait for PLL to stabilise */
866 msleep(10);
867
868 /* Enable clock to frequency divider */
869 if (!ret)
870 ret = reg_write(client, RJ54N1_CLK_RST, 1);
871
872 if (!ret)
873 ret = reg_read(client, RJ54N1_CLK_RST);
874 if (ret != 1) {
875 dev_err(&client->dev,
876 "Resetting RJ54N1CB0C clock failed: %d!\n", ret);
877 return -EIO;
878 }
879
880 /* Start the PLL */
881 ret = reg_set(client, RJ54N1_OCLK_DSP, 1, 1);
882
883 /* Enable OCLK */
884 if (!ret)
885 ret = reg_write(client, RJ54N1_OCLK_SEL_EN, 1);
886
887 return ret;
888}
889
890static int rj54n1_reg_init(struct i2c_client *client)
891{
892 struct rj54n1 *rj54n1 = to_rj54n1(client);
893 int ret = rj54n1_set_clock(client);
894
895 if (!ret)
896 ret = reg_write_multiple(client, bank_7, ARRAY_SIZE(bank_7));
897 if (!ret)
898 ret = reg_write_multiple(client, bank_10, ARRAY_SIZE(bank_10));
899
900 /* Set binning divisors */
901 if (!ret)
902 ret = reg_write(client, RJ54N1_SCALE_1_2_LEV, 3 | (7 << 4));
903 if (!ret)
904 ret = reg_write(client, RJ54N1_SCALE_4_LEV, 0xf);
905
906 /* Switch to fixed resize mode */
907 if (!ret)
908 ret = reg_write(client, RJ54N1_RESIZE_CONTROL,
909 RESIZE_HOLD_SEL | 1);
910
911 /* Set gain */
912 if (!ret)
913 ret = reg_write(client, RJ54N1_Y_GAIN, 0x84);
914
915 /*
916 * Mirror the image back: default is upside down and left-to-right...
917 * Set manual preview / still shot switching
918 */
919 if (!ret)
920 ret = reg_write(client, RJ54N1_MIRROR_STILL_MODE, 0x27);
921
922 if (!ret)
923 ret = reg_write_multiple(client, bank_4, ARRAY_SIZE(bank_4));
924
925 /* Auto exposure area */
926 if (!ret)
927 ret = reg_write(client, RJ54N1_EXPOSURE_CONTROL, 0x80);
928 /* Check current auto WB config */
929 if (!ret)
930 ret = reg_read(client, RJ54N1_WB_SEL_WEIGHT_I);
931 if (ret >= 0) {
932 rj54n1->auto_wb = ret & 0x80;
933 ret = reg_write_multiple(client, bank_5, ARRAY_SIZE(bank_5));
934 }
935 if (!ret)
936 ret = reg_write_multiple(client, bank_8, ARRAY_SIZE(bank_8));
937
938 if (!ret)
939 ret = reg_write(client, RJ54N1_RESET_STANDBY,
940 E_EXCLK | DSP_RSTX | SEN_RSTX);
941
942 /* Commit init */
943 if (!ret)
944 ret = rj54n1_commit(client);
945
946 /* Take DSP, TG, sensor out of reset */
947 if (!ret)
948 ret = reg_write(client, RJ54N1_RESET_STANDBY,
949 E_EXCLK | DSP_RSTX | TG_RSTX | SEN_RSTX);
950
951 /* Start register update? Same register as 0x?FE in many bank_* sets */
952 if (!ret)
953 ret = reg_write(client, RJ54N1_FWFLG, 2);
954
955 /* Constant taken from manufacturer's example */
956 msleep(700);
957
958 return ret;
959}
960
961static int rj54n1_try_fmt(struct v4l2_subdev *sd,
962 struct v4l2_mbus_framefmt *mf)
963{
964 struct i2c_client *client = v4l2_get_subdevdata(sd);
965 struct rj54n1 *rj54n1 = to_rj54n1(client);
966 const struct rj54n1_datafmt *fmt;
967 int align = mf->code == V4L2_MBUS_FMT_SBGGR10_1X10 ||
968 mf->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_BE ||
969 mf->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_BE ||
970 mf->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE ||
971 mf->code == V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_LE;
972
973 dev_dbg(&client->dev, "%s: code = %d, width = %u, height = %u\n",
974 __func__, mf->code, mf->width, mf->height);
975
976 fmt = rj54n1_find_datafmt(mf->code, rj54n1_colour_fmts,
977 ARRAY_SIZE(rj54n1_colour_fmts));
978 if (!fmt) {
979 fmt = rj54n1->fmt;
980 mf->code = fmt->code;
981 }
982
983 mf->field = V4L2_FIELD_NONE;
984 mf->colorspace = fmt->colorspace;
985
986 v4l_bound_align_image(&mf->width, 112, RJ54N1_MAX_WIDTH, align,
987 &mf->height, 84, RJ54N1_MAX_HEIGHT, align, 0);
988
989 return 0;
990}
991
992static int rj54n1_s_fmt(struct v4l2_subdev *sd,
993 struct v4l2_mbus_framefmt *mf)
994{
995 struct i2c_client *client = v4l2_get_subdevdata(sd);
996 struct rj54n1 *rj54n1 = to_rj54n1(client);
997 const struct rj54n1_datafmt *fmt;
998 int output_w, output_h, max_w, max_h,
999 input_w = rj54n1->rect.width, input_h = rj54n1->rect.height;
1000 int ret;
1001
1002 /*
1003 * The host driver can call us without .try_fmt(), so, we have to take
1004 * care ourseleves
1005 */
1006 rj54n1_try_fmt(sd, mf);
1007
1008 /*
1009 * Verify if the sensor has just been powered on. TODO: replace this
1010 * with proper PM, when a suitable API is available.
1011 */
1012 ret = reg_read(client, RJ54N1_RESET_STANDBY);
1013 if (ret < 0)
1014 return ret;
1015
1016 if (!(ret & E_EXCLK)) {
1017 ret = rj54n1_reg_init(client);
1018 if (ret < 0)
1019 return ret;
1020 }
1021
1022 dev_dbg(&client->dev, "%s: code = %d, width = %u, height = %u\n",
1023 __func__, mf->code, mf->width, mf->height);
1024
1025 /* RA_SEL_UL is only relevant for raw modes, ignored otherwise. */
1026 switch (mf->code) {
1027 case V4L2_MBUS_FMT_YUYV8_2X8:
1028 ret = reg_write(client, RJ54N1_OUT_SEL, 0);
1029 if (!ret)
1030 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8);
1031 break;
1032 case V4L2_MBUS_FMT_YVYU8_2X8:
1033 ret = reg_write(client, RJ54N1_OUT_SEL, 0);
1034 if (!ret)
1035 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8);
1036 break;
1037 case V4L2_MBUS_FMT_RGB565_2X8_LE:
1038 ret = reg_write(client, RJ54N1_OUT_SEL, 0x11);
1039 if (!ret)
1040 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8);
1041 break;
1042 case V4L2_MBUS_FMT_RGB565_2X8_BE:
1043 ret = reg_write(client, RJ54N1_OUT_SEL, 0x11);
1044 if (!ret)
1045 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8);
1046 break;
1047 case V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_LE:
1048 ret = reg_write(client, RJ54N1_OUT_SEL, 4);
1049 if (!ret)
1050 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8);
1051 if (!ret)
1052 ret = reg_write(client, RJ54N1_RA_SEL_UL, 0);
1053 break;
1054 case V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE:
1055 ret = reg_write(client, RJ54N1_OUT_SEL, 4);
1056 if (!ret)
1057 ret = reg_set(client, RJ54N1_BYTE_SWAP, 8, 8);
1058 if (!ret)
1059 ret = reg_write(client, RJ54N1_RA_SEL_UL, 8);
1060 break;
1061 case V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_BE:
1062 ret = reg_write(client, RJ54N1_OUT_SEL, 4);
1063 if (!ret)
1064 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8);
1065 if (!ret)
1066 ret = reg_write(client, RJ54N1_RA_SEL_UL, 0);
1067 break;
1068 case V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_BE:
1069 ret = reg_write(client, RJ54N1_OUT_SEL, 4);
1070 if (!ret)
1071 ret = reg_set(client, RJ54N1_BYTE_SWAP, 0, 8);
1072 if (!ret)
1073 ret = reg_write(client, RJ54N1_RA_SEL_UL, 8);
1074 break;
1075 case V4L2_MBUS_FMT_SBGGR10_1X10:
1076 ret = reg_write(client, RJ54N1_OUT_SEL, 5);
1077 break;
1078 default:
1079 ret = -EINVAL;
1080 }
1081
1082 /* Special case: a raw mode with 10 bits of data per clock tick */
1083 if (!ret)
1084 ret = reg_set(client, RJ54N1_OCLK_SEL_EN,
1085 (mf->code == V4L2_MBUS_FMT_SBGGR10_1X10) << 1, 2);
1086
1087 if (ret < 0)
1088 return ret;
1089
1090 /* Supported scales 1:1 >= scale > 1:16 */
1091 max_w = mf->width * (16 * 1024 - 1) / 1024;
1092 if (input_w > max_w)
1093 input_w = max_w;
1094 max_h = mf->height * (16 * 1024 - 1) / 1024;
1095 if (input_h > max_h)
1096 input_h = max_h;
1097
1098 output_w = mf->width;
1099 output_h = mf->height;
1100
1101 ret = rj54n1_sensor_scale(sd, &input_w, &input_h, &output_w, &output_h);
1102 if (ret < 0)
1103 return ret;
1104
1105 fmt = rj54n1_find_datafmt(mf->code, rj54n1_colour_fmts,
1106 ARRAY_SIZE(rj54n1_colour_fmts));
1107
1108 rj54n1->fmt = fmt;
1109 rj54n1->resize = ret;
1110 rj54n1->rect.width = input_w;
1111 rj54n1->rect.height = input_h;
1112 rj54n1->width = output_w;
1113 rj54n1->height = output_h;
1114
1115 mf->width = output_w;
1116 mf->height = output_h;
1117 mf->field = V4L2_FIELD_NONE;
1118 mf->colorspace = fmt->colorspace;
1119
1120 return 0;
1121}
1122
1123static int rj54n1_g_chip_ident(struct v4l2_subdev *sd,
1124 struct v4l2_dbg_chip_ident *id)
1125{
1126 struct i2c_client *client = v4l2_get_subdevdata(sd);
1127
1128 if (id->match.type != V4L2_CHIP_MATCH_I2C_ADDR)
1129 return -EINVAL;
1130
1131 if (id->match.addr != client->addr)
1132 return -ENODEV;
1133
1134 id->ident = V4L2_IDENT_RJ54N1CB0C;
1135 id->revision = 0;
1136
1137 return 0;
1138}
1139
1140#ifdef CONFIG_VIDEO_ADV_DEBUG
1141static int rj54n1_g_register(struct v4l2_subdev *sd,
1142 struct v4l2_dbg_register *reg)
1143{
1144 struct i2c_client *client = v4l2_get_subdevdata(sd);
1145
1146 if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR ||
1147 reg->reg < 0x400 || reg->reg > 0x1fff)
1148 /* Registers > 0x0800 are only available from Sharp support */
1149 return -EINVAL;
1150
1151 if (reg->match.addr != client->addr)
1152 return -ENODEV;
1153
1154 reg->size = 1;
1155 reg->val = reg_read(client, reg->reg);
1156
1157 if (reg->val > 0xff)
1158 return -EIO;
1159
1160 return 0;
1161}
1162
1163static int rj54n1_s_register(struct v4l2_subdev *sd,
1164 struct v4l2_dbg_register *reg)
1165{
1166 struct i2c_client *client = v4l2_get_subdevdata(sd);
1167
1168 if (reg->match.type != V4L2_CHIP_MATCH_I2C_ADDR ||
1169 reg->reg < 0x400 || reg->reg > 0x1fff)
1170 /* Registers >= 0x0800 are only available from Sharp support */
1171 return -EINVAL;
1172
1173 if (reg->match.addr != client->addr)
1174 return -ENODEV;
1175
1176 if (reg_write(client, reg->reg, reg->val) < 0)
1177 return -EIO;
1178
1179 return 0;
1180}
1181#endif
1182
1183static int rj54n1_s_ctrl(struct v4l2_ctrl *ctrl)
1184{
1185 struct rj54n1 *rj54n1 = container_of(ctrl->handler, struct rj54n1, hdl);
1186 struct v4l2_subdev *sd = &rj54n1->subdev;
1187 struct i2c_client *client = v4l2_get_subdevdata(sd);
1188 int data;
1189
1190 switch (ctrl->id) {
1191 case V4L2_CID_VFLIP:
1192 if (ctrl->val)
1193 data = reg_set(client, RJ54N1_MIRROR_STILL_MODE, 0, 1);
1194 else
1195 data = reg_set(client, RJ54N1_MIRROR_STILL_MODE, 1, 1);
1196 if (data < 0)
1197 return -EIO;
1198 return 0;
1199 case V4L2_CID_HFLIP:
1200 if (ctrl->val)
1201 data = reg_set(client, RJ54N1_MIRROR_STILL_MODE, 0, 2);
1202 else
1203 data = reg_set(client, RJ54N1_MIRROR_STILL_MODE, 2, 2);
1204 if (data < 0)
1205 return -EIO;
1206 return 0;
1207 case V4L2_CID_GAIN:
1208 if (reg_write(client, RJ54N1_Y_GAIN, ctrl->val * 2) < 0)
1209 return -EIO;
1210 return 0;
1211 case V4L2_CID_AUTO_WHITE_BALANCE:
1212 /* Auto WB area - whole image */
1213 if (reg_set(client, RJ54N1_WB_SEL_WEIGHT_I, ctrl->val << 7,
1214 0x80) < 0)
1215 return -EIO;
1216 rj54n1->auto_wb = ctrl->val;
1217 return 0;
1218 }
1219
1220 return -EINVAL;
1221}
1222
1223static const struct v4l2_ctrl_ops rj54n1_ctrl_ops = {
1224 .s_ctrl = rj54n1_s_ctrl,
1225};
1226
1227static struct v4l2_subdev_core_ops rj54n1_subdev_core_ops = {
1228 .g_chip_ident = rj54n1_g_chip_ident,
1229#ifdef CONFIG_VIDEO_ADV_DEBUG
1230 .g_register = rj54n1_g_register,
1231 .s_register = rj54n1_s_register,
1232#endif
1233};
1234
1235static int rj54n1_g_mbus_config(struct v4l2_subdev *sd,
1236 struct v4l2_mbus_config *cfg)
1237{
1238 struct i2c_client *client = v4l2_get_subdevdata(sd);
1239 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
1240
1241 cfg->flags =
1242 V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING |
1243 V4L2_MBUS_MASTER | V4L2_MBUS_DATA_ACTIVE_HIGH |
1244 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1245 cfg->type = V4L2_MBUS_PARALLEL;
1246 cfg->flags = soc_camera_apply_board_flags(icl, cfg);
1247
1248 return 0;
1249}
1250
1251static int rj54n1_s_mbus_config(struct v4l2_subdev *sd,
1252 const struct v4l2_mbus_config *cfg)
1253{
1254 struct i2c_client *client = v4l2_get_subdevdata(sd);
1255 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
1256
1257 /* Figures 2.5-1 to 2.5-3 - default falling pixclk edge */
1258 if (soc_camera_apply_board_flags(icl, cfg) &
1259 V4L2_MBUS_PCLK_SAMPLE_RISING)
1260 return reg_write(client, RJ54N1_OUT_SIGPO, 1 << 4);
1261 else
1262 return reg_write(client, RJ54N1_OUT_SIGPO, 0);
1263}
1264
1265static struct v4l2_subdev_video_ops rj54n1_subdev_video_ops = {
1266 .s_stream = rj54n1_s_stream,
1267 .s_mbus_fmt = rj54n1_s_fmt,
1268 .g_mbus_fmt = rj54n1_g_fmt,
1269 .try_mbus_fmt = rj54n1_try_fmt,
1270 .enum_mbus_fmt = rj54n1_enum_fmt,
1271 .g_crop = rj54n1_g_crop,
1272 .s_crop = rj54n1_s_crop,
1273 .cropcap = rj54n1_cropcap,
1274 .g_mbus_config = rj54n1_g_mbus_config,
1275 .s_mbus_config = rj54n1_s_mbus_config,
1276};
1277
1278static struct v4l2_subdev_ops rj54n1_subdev_ops = {
1279 .core = &rj54n1_subdev_core_ops,
1280 .video = &rj54n1_subdev_video_ops,
1281};
1282
1283/*
1284 * Interface active, can use i2c. If it fails, it can indeed mean, that
1285 * this wasn't our capture interface, so, we wait for the right one
1286 */
1287static int rj54n1_video_probe(struct i2c_client *client,
1288 struct rj54n1_pdata *priv)
1289{
1290 int data1, data2;
1291 int ret;
1292
1293 /* Read out the chip version register */
1294 data1 = reg_read(client, RJ54N1_DEV_CODE);
1295 data2 = reg_read(client, RJ54N1_DEV_CODE2);
1296
1297 if (data1 != 0x51 || data2 != 0x10) {
1298 ret = -ENODEV;
1299 dev_info(&client->dev, "No RJ54N1CB0C found, read 0x%x:0x%x\n",
1300 data1, data2);
1301 goto ei2c;
1302 }
1303
1304 /* Configure IOCTL polarity from the platform data: 0 or 1 << 7. */
1305 ret = reg_write(client, RJ54N1_IOC, priv->ioctl_high << 7);
1306 if (ret < 0)
1307 goto ei2c;
1308
1309 dev_info(&client->dev, "Detected a RJ54N1CB0C chip ID 0x%x:0x%x\n",
1310 data1, data2);
1311
1312ei2c:
1313 return ret;
1314}
1315
1316static int rj54n1_probe(struct i2c_client *client,
1317 const struct i2c_device_id *did)
1318{
1319 struct rj54n1 *rj54n1;
1320 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
1321 struct i2c_adapter *adapter = to_i2c_adapter(client->dev.parent);
1322 struct rj54n1_pdata *rj54n1_priv;
1323 int ret;
1324
1325 if (!icl || !icl->priv) {
1326 dev_err(&client->dev, "RJ54N1CB0C: missing platform data!\n");
1327 return -EINVAL;
1328 }
1329
1330 rj54n1_priv = icl->priv;
1331
1332 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
1333 dev_warn(&adapter->dev,
1334 "I2C-Adapter doesn't support I2C_FUNC_SMBUS_BYTE\n");
1335 return -EIO;
1336 }
1337
1338 rj54n1 = kzalloc(sizeof(struct rj54n1), GFP_KERNEL);
1339 if (!rj54n1)
1340 return -ENOMEM;
1341
1342 v4l2_i2c_subdev_init(&rj54n1->subdev, client, &rj54n1_subdev_ops);
1343 v4l2_ctrl_handler_init(&rj54n1->hdl, 4);
1344 v4l2_ctrl_new_std(&rj54n1->hdl, &rj54n1_ctrl_ops,
1345 V4L2_CID_VFLIP, 0, 1, 1, 0);
1346 v4l2_ctrl_new_std(&rj54n1->hdl, &rj54n1_ctrl_ops,
1347 V4L2_CID_HFLIP, 0, 1, 1, 0);
1348 v4l2_ctrl_new_std(&rj54n1->hdl, &rj54n1_ctrl_ops,
1349 V4L2_CID_GAIN, 0, 127, 1, 66);
1350 v4l2_ctrl_new_std(&rj54n1->hdl, &rj54n1_ctrl_ops,
1351 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
1352 rj54n1->subdev.ctrl_handler = &rj54n1->hdl;
1353 if (rj54n1->hdl.error) {
1354 int err = rj54n1->hdl.error;
1355
1356 kfree(rj54n1);
1357 return err;
1358 }
1359
1360 rj54n1->clk_div = clk_div;
1361 rj54n1->rect.left = RJ54N1_COLUMN_SKIP;
1362 rj54n1->rect.top = RJ54N1_ROW_SKIP;
1363 rj54n1->rect.width = RJ54N1_MAX_WIDTH;
1364 rj54n1->rect.height = RJ54N1_MAX_HEIGHT;
1365 rj54n1->width = RJ54N1_MAX_WIDTH;
1366 rj54n1->height = RJ54N1_MAX_HEIGHT;
1367 rj54n1->fmt = &rj54n1_colour_fmts[0];
1368 rj54n1->resize = 1024;
1369 rj54n1->tgclk_mhz = (rj54n1_priv->mclk_freq / PLL_L * PLL_N) /
1370 (clk_div.ratio_tg + 1) / (clk_div.ratio_t + 1);
1371
1372 ret = rj54n1_video_probe(client, rj54n1_priv);
1373 if (ret < 0) {
1374 v4l2_ctrl_handler_free(&rj54n1->hdl);
1375 kfree(rj54n1);
1376 return ret;
1377 }
1378 return v4l2_ctrl_handler_setup(&rj54n1->hdl);
1379}
1380
1381static int rj54n1_remove(struct i2c_client *client)
1382{
1383 struct rj54n1 *rj54n1 = to_rj54n1(client);
1384 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
1385
1386 v4l2_device_unregister_subdev(&rj54n1->subdev);
1387 if (icl->free_bus)
1388 icl->free_bus(icl);
1389 v4l2_ctrl_handler_free(&rj54n1->hdl);
1390 kfree(rj54n1);
1391
1392 return 0;
1393}
1394
1395static const struct i2c_device_id rj54n1_id[] = {
1396 { "rj54n1cb0c", 0 },
1397 { }
1398};
1399MODULE_DEVICE_TABLE(i2c, rj54n1_id);
1400
1401static struct i2c_driver rj54n1_i2c_driver = {
1402 .driver = {
1403 .name = "rj54n1cb0c",
1404 },
1405 .probe = rj54n1_probe,
1406 .remove = rj54n1_remove,
1407 .id_table = rj54n1_id,
1408};
1409
1410module_i2c_driver(rj54n1_i2c_driver);
1411
1412MODULE_DESCRIPTION("Sharp RJ54N1CB0C Camera driver");
1413MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1414MODULE_LICENSE("GPL v2");
diff --git a/drivers/media/video/sh_mobile_csi2.c b/drivers/media/video/sh_mobile_csi2.c
deleted file mode 100644
index 05286500b4d4..000000000000
--- a/drivers/media/video/sh_mobile_csi2.c
+++ /dev/null
@@ -1,398 +0,0 @@
1/*
2 * Driver for the SH-Mobile MIPI CSI-2 unit
3 *
4 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/delay.h>
12#include <linux/i2c.h>
13#include <linux/io.h>
14#include <linux/platform_device.h>
15#include <linux/pm_runtime.h>
16#include <linux/slab.h>
17#include <linux/videodev2.h>
18#include <linux/module.h>
19
20#include <media/sh_mobile_ceu.h>
21#include <media/sh_mobile_csi2.h>
22#include <media/soc_camera.h>
23#include <media/soc_mediabus.h>
24#include <media/v4l2-common.h>
25#include <media/v4l2-dev.h>
26#include <media/v4l2-device.h>
27#include <media/v4l2-mediabus.h>
28#include <media/v4l2-subdev.h>
29
30#define SH_CSI2_TREF 0x00
31#define SH_CSI2_SRST 0x04
32#define SH_CSI2_PHYCNT 0x08
33#define SH_CSI2_CHKSUM 0x0C
34#define SH_CSI2_VCDT 0x10
35
36struct sh_csi2 {
37 struct v4l2_subdev subdev;
38 struct list_head list;
39 unsigned int irq;
40 unsigned long mipi_flags;
41 void __iomem *base;
42 struct platform_device *pdev;
43 struct sh_csi2_client_config *client;
44};
45
46static int sh_csi2_try_fmt(struct v4l2_subdev *sd,
47 struct v4l2_mbus_framefmt *mf)
48{
49 struct sh_csi2 *priv = container_of(sd, struct sh_csi2, subdev);
50 struct sh_csi2_pdata *pdata = priv->pdev->dev.platform_data;
51
52 if (mf->width > 8188)
53 mf->width = 8188;
54 else if (mf->width & 1)
55 mf->width &= ~1;
56
57 switch (pdata->type) {
58 case SH_CSI2C:
59 switch (mf->code) {
60 case V4L2_MBUS_FMT_UYVY8_2X8: /* YUV422 */
61 case V4L2_MBUS_FMT_YUYV8_1_5X8: /* YUV420 */
62 case V4L2_MBUS_FMT_Y8_1X8: /* RAW8 */
63 case V4L2_MBUS_FMT_SBGGR8_1X8:
64 case V4L2_MBUS_FMT_SGRBG8_1X8:
65 break;
66 default:
67 /* All MIPI CSI-2 devices must support one of primary formats */
68 mf->code = V4L2_MBUS_FMT_YUYV8_2X8;
69 }
70 break;
71 case SH_CSI2I:
72 switch (mf->code) {
73 case V4L2_MBUS_FMT_Y8_1X8: /* RAW8 */
74 case V4L2_MBUS_FMT_SBGGR8_1X8:
75 case V4L2_MBUS_FMT_SGRBG8_1X8:
76 case V4L2_MBUS_FMT_SBGGR10_1X10: /* RAW10 */
77 case V4L2_MBUS_FMT_SBGGR12_1X12: /* RAW12 */
78 break;
79 default:
80 /* All MIPI CSI-2 devices must support one of primary formats */
81 mf->code = V4L2_MBUS_FMT_SBGGR8_1X8;
82 }
83 break;
84 }
85
86 return 0;
87}
88
89/*
90 * We have done our best in try_fmt to try and tell the sensor, which formats
91 * we support. If now the configuration is unsuitable for us we can only
92 * error out.
93 */
94static int sh_csi2_s_fmt(struct v4l2_subdev *sd,
95 struct v4l2_mbus_framefmt *mf)
96{
97 struct sh_csi2 *priv = container_of(sd, struct sh_csi2, subdev);
98 u32 tmp = (priv->client->channel & 3) << 8;
99
100 dev_dbg(sd->v4l2_dev->dev, "%s(%u)\n", __func__, mf->code);
101 if (mf->width > 8188 || mf->width & 1)
102 return -EINVAL;
103
104 switch (mf->code) {
105 case V4L2_MBUS_FMT_UYVY8_2X8:
106 tmp |= 0x1e; /* YUV422 8 bit */
107 break;
108 case V4L2_MBUS_FMT_YUYV8_1_5X8:
109 tmp |= 0x18; /* YUV420 8 bit */
110 break;
111 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE:
112 tmp |= 0x21; /* RGB555 */
113 break;
114 case V4L2_MBUS_FMT_RGB565_2X8_BE:
115 tmp |= 0x22; /* RGB565 */
116 break;
117 case V4L2_MBUS_FMT_Y8_1X8:
118 case V4L2_MBUS_FMT_SBGGR8_1X8:
119 case V4L2_MBUS_FMT_SGRBG8_1X8:
120 tmp |= 0x2a; /* RAW8 */
121 break;
122 default:
123 return -EINVAL;
124 }
125
126 iowrite32(tmp, priv->base + SH_CSI2_VCDT);
127
128 return 0;
129}
130
131static int sh_csi2_g_mbus_config(struct v4l2_subdev *sd,
132 struct v4l2_mbus_config *cfg)
133{
134 cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING |
135 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_HIGH |
136 V4L2_MBUS_MASTER | V4L2_MBUS_DATA_ACTIVE_HIGH;
137 cfg->type = V4L2_MBUS_PARALLEL;
138
139 return 0;
140}
141
142static int sh_csi2_s_mbus_config(struct v4l2_subdev *sd,
143 const struct v4l2_mbus_config *cfg)
144{
145 struct sh_csi2 *priv = container_of(sd, struct sh_csi2, subdev);
146 struct soc_camera_device *icd = v4l2_get_subdev_hostdata(sd);
147 struct v4l2_subdev *client_sd = soc_camera_to_subdev(icd);
148 struct v4l2_mbus_config client_cfg = {.type = V4L2_MBUS_CSI2,
149 .flags = priv->mipi_flags};
150
151 return v4l2_subdev_call(client_sd, video, s_mbus_config, &client_cfg);
152}
153
154static struct v4l2_subdev_video_ops sh_csi2_subdev_video_ops = {
155 .s_mbus_fmt = sh_csi2_s_fmt,
156 .try_mbus_fmt = sh_csi2_try_fmt,
157 .g_mbus_config = sh_csi2_g_mbus_config,
158 .s_mbus_config = sh_csi2_s_mbus_config,
159};
160
161static void sh_csi2_hwinit(struct sh_csi2 *priv)
162{
163 struct sh_csi2_pdata *pdata = priv->pdev->dev.platform_data;
164 __u32 tmp = 0x10; /* Enable MIPI CSI clock lane */
165
166 /* Reflect registers immediately */
167 iowrite32(0x00000001, priv->base + SH_CSI2_TREF);
168 /* reset CSI2 harware */
169 iowrite32(0x00000001, priv->base + SH_CSI2_SRST);
170 udelay(5);
171 iowrite32(0x00000000, priv->base + SH_CSI2_SRST);
172
173 switch (pdata->type) {
174 case SH_CSI2C:
175 if (priv->client->lanes == 1)
176 tmp |= 1;
177 else
178 /* Default - both lanes */
179 tmp |= 3;
180 break;
181 case SH_CSI2I:
182 if (!priv->client->lanes || priv->client->lanes > 4)
183 /* Default - all 4 lanes */
184 tmp |= 0xf;
185 else
186 tmp |= (1 << priv->client->lanes) - 1;
187 }
188
189 if (priv->client->phy == SH_CSI2_PHY_MAIN)
190 tmp |= 0x8000;
191
192 iowrite32(tmp, priv->base + SH_CSI2_PHYCNT);
193
194 tmp = 0;
195 if (pdata->flags & SH_CSI2_ECC)
196 tmp |= 2;
197 if (pdata->flags & SH_CSI2_CRC)
198 tmp |= 1;
199 iowrite32(tmp, priv->base + SH_CSI2_CHKSUM);
200}
201
202static int sh_csi2_client_connect(struct sh_csi2 *priv)
203{
204 struct sh_csi2_pdata *pdata = priv->pdev->dev.platform_data;
205 struct soc_camera_device *icd = v4l2_get_subdev_hostdata(&priv->subdev);
206 struct v4l2_subdev *client_sd = soc_camera_to_subdev(icd);
207 struct device *dev = v4l2_get_subdevdata(&priv->subdev);
208 struct v4l2_mbus_config cfg;
209 unsigned long common_flags, csi2_flags;
210 int i, ret;
211
212 if (priv->client)
213 return -EBUSY;
214
215 for (i = 0; i < pdata->num_clients; i++)
216 if (&pdata->clients[i].pdev->dev == icd->pdev)
217 break;
218
219 dev_dbg(dev, "%s(%p): found #%d\n", __func__, dev, i);
220
221 if (i == pdata->num_clients)
222 return -ENODEV;
223
224 /* Check if we can support this camera */
225 csi2_flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK | V4L2_MBUS_CSI2_1_LANE;
226
227 switch (pdata->type) {
228 case SH_CSI2C:
229 if (pdata->clients[i].lanes != 1)
230 csi2_flags |= V4L2_MBUS_CSI2_2_LANE;
231 break;
232 case SH_CSI2I:
233 switch (pdata->clients[i].lanes) {
234 default:
235 csi2_flags |= V4L2_MBUS_CSI2_4_LANE;
236 case 3:
237 csi2_flags |= V4L2_MBUS_CSI2_3_LANE;
238 case 2:
239 csi2_flags |= V4L2_MBUS_CSI2_2_LANE;
240 }
241 }
242
243 cfg.type = V4L2_MBUS_CSI2;
244 ret = v4l2_subdev_call(client_sd, video, g_mbus_config, &cfg);
245 if (ret == -ENOIOCTLCMD)
246 common_flags = csi2_flags;
247 else if (!ret)
248 common_flags = soc_mbus_config_compatible(&cfg,
249 csi2_flags);
250 else
251 common_flags = 0;
252
253 if (!common_flags)
254 return -EINVAL;
255
256 /* All good: camera MIPI configuration supported */
257 priv->mipi_flags = common_flags;
258 priv->client = pdata->clients + i;
259
260 pm_runtime_get_sync(dev);
261
262 sh_csi2_hwinit(priv);
263
264 return 0;
265}
266
267static void sh_csi2_client_disconnect(struct sh_csi2 *priv)
268{
269 if (!priv->client)
270 return;
271
272 priv->client = NULL;
273
274 pm_runtime_put(v4l2_get_subdevdata(&priv->subdev));
275}
276
277static int sh_csi2_s_power(struct v4l2_subdev *sd, int on)
278{
279 struct sh_csi2 *priv = container_of(sd, struct sh_csi2, subdev);
280
281 if (on)
282 return sh_csi2_client_connect(priv);
283
284 sh_csi2_client_disconnect(priv);
285 return 0;
286}
287
288static struct v4l2_subdev_core_ops sh_csi2_subdev_core_ops = {
289 .s_power = sh_csi2_s_power,
290};
291
292static struct v4l2_subdev_ops sh_csi2_subdev_ops = {
293 .core = &sh_csi2_subdev_core_ops,
294 .video = &sh_csi2_subdev_video_ops,
295};
296
297static __devinit int sh_csi2_probe(struct platform_device *pdev)
298{
299 struct resource *res;
300 unsigned int irq;
301 int ret;
302 struct sh_csi2 *priv;
303 /* Platform data specify the PHY, lanes, ECC, CRC */
304 struct sh_csi2_pdata *pdata = pdev->dev.platform_data;
305
306 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
307 /* Interrupt unused so far */
308 irq = platform_get_irq(pdev, 0);
309
310 if (!res || (int)irq <= 0 || !pdata) {
311 dev_err(&pdev->dev, "Not enough CSI2 platform resources.\n");
312 return -ENODEV;
313 }
314
315 /* TODO: Add support for CSI2I. Careful: different register layout! */
316 if (pdata->type != SH_CSI2C) {
317 dev_err(&pdev->dev, "Only CSI2C supported ATM.\n");
318 return -EINVAL;
319 }
320
321 priv = kzalloc(sizeof(struct sh_csi2), GFP_KERNEL);
322 if (!priv)
323 return -ENOMEM;
324
325 priv->irq = irq;
326
327 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
328 dev_err(&pdev->dev, "CSI2 register region already claimed\n");
329 ret = -EBUSY;
330 goto ereqreg;
331 }
332
333 priv->base = ioremap(res->start, resource_size(res));
334 if (!priv->base) {
335 ret = -ENXIO;
336 dev_err(&pdev->dev, "Unable to ioremap CSI2 registers.\n");
337 goto eremap;
338 }
339
340 priv->pdev = pdev;
341 platform_set_drvdata(pdev, priv);
342
343 v4l2_subdev_init(&priv->subdev, &sh_csi2_subdev_ops);
344 v4l2_set_subdevdata(&priv->subdev, &pdev->dev);
345
346 snprintf(priv->subdev.name, V4L2_SUBDEV_NAME_SIZE, "%s.mipi-csi",
347 dev_name(pdata->v4l2_dev->dev));
348 ret = v4l2_device_register_subdev(pdata->v4l2_dev, &priv->subdev);
349 dev_dbg(&pdev->dev, "%s(%p): ret(register_subdev) = %d\n", __func__, priv, ret);
350 if (ret < 0)
351 goto esdreg;
352
353 pm_runtime_enable(&pdev->dev);
354
355 dev_dbg(&pdev->dev, "CSI2 probed.\n");
356
357 return 0;
358
359esdreg:
360 iounmap(priv->base);
361eremap:
362 release_mem_region(res->start, resource_size(res));
363ereqreg:
364 kfree(priv);
365
366 return ret;
367}
368
369static __devexit int sh_csi2_remove(struct platform_device *pdev)
370{
371 struct sh_csi2 *priv = platform_get_drvdata(pdev);
372 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
373
374 v4l2_device_unregister_subdev(&priv->subdev);
375 pm_runtime_disable(&pdev->dev);
376 iounmap(priv->base);
377 release_mem_region(res->start, resource_size(res));
378 platform_set_drvdata(pdev, NULL);
379 kfree(priv);
380
381 return 0;
382}
383
384static struct platform_driver __refdata sh_csi2_pdrv = {
385 .remove = __devexit_p(sh_csi2_remove),
386 .probe = sh_csi2_probe,
387 .driver = {
388 .name = "sh-mobile-csi2",
389 .owner = THIS_MODULE,
390 },
391};
392
393module_platform_driver(sh_csi2_pdrv);
394
395MODULE_DESCRIPTION("SH-Mobile MIPI CSI-2 driver");
396MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
397MODULE_LICENSE("GPL v2");
398MODULE_ALIAS("platform:sh-mobile-csi2");
diff --git a/drivers/media/video/soc_camera.c b/drivers/media/video/soc_camera.c
deleted file mode 100644
index 9758217470f0..000000000000
--- a/drivers/media/video/soc_camera.c
+++ /dev/null
@@ -1,1554 +0,0 @@
1/*
2 * camera image capture (abstract) bus driver
3 *
4 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
5 *
6 * This driver provides an interface between platform-specific camera
7 * busses and camera devices. It should be used if the camera is
8 * connected not over a "proper" bus like PCI or USB, but over a
9 * special bus, like, for example, the Quick Capture interface on PXA270
10 * SoCs. Later it should also be used for i.MX31 SoCs from Freescale.
11 * It can handle multiple cameras and / or multiple busses, which can
12 * be used, e.g., in stereo-vision applications.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/device.h>
20#include <linux/err.h>
21#include <linux/i2c.h>
22#include <linux/init.h>
23#include <linux/list.h>
24#include <linux/mutex.h>
25#include <linux/module.h>
26#include <linux/platform_device.h>
27#include <linux/regulator/consumer.h>
28#include <linux/slab.h>
29#include <linux/pm_runtime.h>
30#include <linux/vmalloc.h>
31
32#include <media/soc_camera.h>
33#include <media/v4l2-common.h>
34#include <media/v4l2-ioctl.h>
35#include <media/v4l2-dev.h>
36#include <media/videobuf-core.h>
37#include <media/videobuf2-core.h>
38#include <media/soc_mediabus.h>
39
40/* Default to VGA resolution */
41#define DEFAULT_WIDTH 640
42#define DEFAULT_HEIGHT 480
43
44#define is_streaming(ici, icd) \
45 (((ici)->ops->init_videobuf) ? \
46 (icd)->vb_vidq.streaming : \
47 vb2_is_streaming(&(icd)->vb2_vidq))
48
49static LIST_HEAD(hosts);
50static LIST_HEAD(devices);
51static DEFINE_MUTEX(list_lock); /* Protects the list of hosts */
52
53static int soc_camera_power_on(struct soc_camera_device *icd,
54 struct soc_camera_link *icl)
55{
56 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
57 int ret = regulator_bulk_enable(icl->num_regulators,
58 icl->regulators);
59 if (ret < 0) {
60 dev_err(icd->pdev, "Cannot enable regulators\n");
61 return ret;
62 }
63
64 if (icl->power) {
65 ret = icl->power(icd->control, 1);
66 if (ret < 0) {
67 dev_err(icd->pdev,
68 "Platform failed to power-on the camera.\n");
69 goto elinkpwr;
70 }
71 }
72
73 ret = v4l2_subdev_call(sd, core, s_power, 1);
74 if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV)
75 goto esdpwr;
76
77 return 0;
78
79esdpwr:
80 if (icl->power)
81 icl->power(icd->control, 0);
82elinkpwr:
83 regulator_bulk_disable(icl->num_regulators,
84 icl->regulators);
85 return ret;
86}
87
88static int soc_camera_power_off(struct soc_camera_device *icd,
89 struct soc_camera_link *icl)
90{
91 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
92 int ret = v4l2_subdev_call(sd, core, s_power, 0);
93
94 if (ret < 0 && ret != -ENOIOCTLCMD && ret != -ENODEV)
95 return ret;
96
97 if (icl->power) {
98 ret = icl->power(icd->control, 0);
99 if (ret < 0) {
100 dev_err(icd->pdev,
101 "Platform failed to power-off the camera.\n");
102 return ret;
103 }
104 }
105
106 ret = regulator_bulk_disable(icl->num_regulators,
107 icl->regulators);
108 if (ret < 0)
109 dev_err(icd->pdev, "Cannot disable regulators\n");
110
111 return ret;
112}
113
114const struct soc_camera_format_xlate *soc_camera_xlate_by_fourcc(
115 struct soc_camera_device *icd, unsigned int fourcc)
116{
117 unsigned int i;
118
119 for (i = 0; i < icd->num_user_formats; i++)
120 if (icd->user_formats[i].host_fmt->fourcc == fourcc)
121 return icd->user_formats + i;
122 return NULL;
123}
124EXPORT_SYMBOL(soc_camera_xlate_by_fourcc);
125
126/**
127 * soc_camera_apply_board_flags() - apply platform SOCAM_SENSOR_INVERT_* flags
128 * @icl: camera platform parameters
129 * @cfg: media bus configuration
130 * @return: resulting flags
131 */
132unsigned long soc_camera_apply_board_flags(struct soc_camera_link *icl,
133 const struct v4l2_mbus_config *cfg)
134{
135 unsigned long f, flags = cfg->flags;
136
137 /* If only one of the two polarities is supported, switch to the opposite */
138 if (icl->flags & SOCAM_SENSOR_INVERT_HSYNC) {
139 f = flags & (V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW);
140 if (f == V4L2_MBUS_HSYNC_ACTIVE_HIGH || f == V4L2_MBUS_HSYNC_ACTIVE_LOW)
141 flags ^= V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW;
142 }
143
144 if (icl->flags & SOCAM_SENSOR_INVERT_VSYNC) {
145 f = flags & (V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW);
146 if (f == V4L2_MBUS_VSYNC_ACTIVE_HIGH || f == V4L2_MBUS_VSYNC_ACTIVE_LOW)
147 flags ^= V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW;
148 }
149
150 if (icl->flags & SOCAM_SENSOR_INVERT_PCLK) {
151 f = flags & (V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING);
152 if (f == V4L2_MBUS_PCLK_SAMPLE_RISING || f == V4L2_MBUS_PCLK_SAMPLE_FALLING)
153 flags ^= V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_PCLK_SAMPLE_FALLING;
154 }
155
156 return flags;
157}
158EXPORT_SYMBOL(soc_camera_apply_board_flags);
159
160#define pixfmtstr(x) (x) & 0xff, ((x) >> 8) & 0xff, ((x) >> 16) & 0xff, \
161 ((x) >> 24) & 0xff
162
163static int soc_camera_try_fmt(struct soc_camera_device *icd,
164 struct v4l2_format *f)
165{
166 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
167 const struct soc_camera_format_xlate *xlate;
168 struct v4l2_pix_format *pix = &f->fmt.pix;
169 int ret;
170
171 dev_dbg(icd->pdev, "TRY_FMT(%c%c%c%c, %ux%u)\n",
172 pixfmtstr(pix->pixelformat), pix->width, pix->height);
173
174 if (!(ici->capabilities & SOCAM_HOST_CAP_STRIDE)) {
175 pix->bytesperline = 0;
176 pix->sizeimage = 0;
177 }
178
179 ret = ici->ops->try_fmt(icd, f);
180 if (ret < 0)
181 return ret;
182
183 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
184 if (!xlate)
185 return -EINVAL;
186
187 ret = soc_mbus_bytes_per_line(pix->width, xlate->host_fmt);
188 if (ret < 0)
189 return ret;
190
191 pix->bytesperline = max_t(u32, pix->bytesperline, ret);
192
193 ret = soc_mbus_image_size(xlate->host_fmt, pix->bytesperline,
194 pix->height);
195 if (ret < 0)
196 return ret;
197
198 pix->sizeimage = max_t(u32, pix->sizeimage, ret);
199
200 return 0;
201}
202
203static int soc_camera_try_fmt_vid_cap(struct file *file, void *priv,
204 struct v4l2_format *f)
205{
206 struct soc_camera_device *icd = file->private_data;
207
208 WARN_ON(priv != file->private_data);
209
210 /* Only single-plane capture is supported so far */
211 if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
212 return -EINVAL;
213
214 /* limit format to hardware capabilities */
215 return soc_camera_try_fmt(icd, f);
216}
217
218static int soc_camera_enum_input(struct file *file, void *priv,
219 struct v4l2_input *inp)
220{
221 if (inp->index != 0)
222 return -EINVAL;
223
224 /* default is camera */
225 inp->type = V4L2_INPUT_TYPE_CAMERA;
226 inp->std = V4L2_STD_UNKNOWN;
227 strcpy(inp->name, "Camera");
228
229 return 0;
230}
231
232static int soc_camera_g_input(struct file *file, void *priv, unsigned int *i)
233{
234 *i = 0;
235
236 return 0;
237}
238
239static int soc_camera_s_input(struct file *file, void *priv, unsigned int i)
240{
241 if (i > 0)
242 return -EINVAL;
243
244 return 0;
245}
246
247static int soc_camera_s_std(struct file *file, void *priv, v4l2_std_id *a)
248{
249 struct soc_camera_device *icd = file->private_data;
250 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
251
252 return v4l2_subdev_call(sd, core, s_std, *a);
253}
254
255static int soc_camera_g_std(struct file *file, void *priv, v4l2_std_id *a)
256{
257 struct soc_camera_device *icd = file->private_data;
258 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
259
260 return v4l2_subdev_call(sd, core, g_std, a);
261}
262
263static int soc_camera_enum_framesizes(struct file *file, void *fh,
264 struct v4l2_frmsizeenum *fsize)
265{
266 struct soc_camera_device *icd = file->private_data;
267 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
268
269 return ici->ops->enum_framesizes(icd, fsize);
270}
271
272static int soc_camera_reqbufs(struct file *file, void *priv,
273 struct v4l2_requestbuffers *p)
274{
275 int ret;
276 struct soc_camera_device *icd = file->private_data;
277 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
278
279 WARN_ON(priv != file->private_data);
280
281 if (icd->streamer && icd->streamer != file)
282 return -EBUSY;
283
284 if (ici->ops->init_videobuf) {
285 ret = videobuf_reqbufs(&icd->vb_vidq, p);
286 if (ret < 0)
287 return ret;
288
289 ret = ici->ops->reqbufs(icd, p);
290 } else {
291 ret = vb2_reqbufs(&icd->vb2_vidq, p);
292 }
293
294 if (!ret && !icd->streamer)
295 icd->streamer = file;
296
297 return ret;
298}
299
300static int soc_camera_querybuf(struct file *file, void *priv,
301 struct v4l2_buffer *p)
302{
303 struct soc_camera_device *icd = file->private_data;
304 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
305
306 WARN_ON(priv != file->private_data);
307
308 if (ici->ops->init_videobuf)
309 return videobuf_querybuf(&icd->vb_vidq, p);
310 else
311 return vb2_querybuf(&icd->vb2_vidq, p);
312}
313
314static int soc_camera_qbuf(struct file *file, void *priv,
315 struct v4l2_buffer *p)
316{
317 struct soc_camera_device *icd = file->private_data;
318 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
319
320 WARN_ON(priv != file->private_data);
321
322 if (icd->streamer != file)
323 return -EBUSY;
324
325 if (ici->ops->init_videobuf)
326 return videobuf_qbuf(&icd->vb_vidq, p);
327 else
328 return vb2_qbuf(&icd->vb2_vidq, p);
329}
330
331static int soc_camera_dqbuf(struct file *file, void *priv,
332 struct v4l2_buffer *p)
333{
334 struct soc_camera_device *icd = file->private_data;
335 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
336
337 WARN_ON(priv != file->private_data);
338
339 if (icd->streamer != file)
340 return -EBUSY;
341
342 if (ici->ops->init_videobuf)
343 return videobuf_dqbuf(&icd->vb_vidq, p, file->f_flags & O_NONBLOCK);
344 else
345 return vb2_dqbuf(&icd->vb2_vidq, p, file->f_flags & O_NONBLOCK);
346}
347
348static int soc_camera_create_bufs(struct file *file, void *priv,
349 struct v4l2_create_buffers *create)
350{
351 struct soc_camera_device *icd = file->private_data;
352 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
353
354 /* videobuf2 only */
355 if (ici->ops->init_videobuf)
356 return -EINVAL;
357 else
358 return vb2_create_bufs(&icd->vb2_vidq, create);
359}
360
361static int soc_camera_prepare_buf(struct file *file, void *priv,
362 struct v4l2_buffer *b)
363{
364 struct soc_camera_device *icd = file->private_data;
365 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
366
367 /* videobuf2 only */
368 if (ici->ops->init_videobuf)
369 return -EINVAL;
370 else
371 return vb2_prepare_buf(&icd->vb2_vidq, b);
372}
373
374/* Always entered with .video_lock held */
375static int soc_camera_init_user_formats(struct soc_camera_device *icd)
376{
377 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
378 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
379 unsigned int i, fmts = 0, raw_fmts = 0;
380 int ret;
381 enum v4l2_mbus_pixelcode code;
382
383 while (!v4l2_subdev_call(sd, video, enum_mbus_fmt, raw_fmts, &code))
384 raw_fmts++;
385
386 if (!ici->ops->get_formats)
387 /*
388 * Fallback mode - the host will have to serve all
389 * sensor-provided formats one-to-one to the user
390 */
391 fmts = raw_fmts;
392 else
393 /*
394 * First pass - only count formats this host-sensor
395 * configuration can provide
396 */
397 for (i = 0; i < raw_fmts; i++) {
398 ret = ici->ops->get_formats(icd, i, NULL);
399 if (ret < 0)
400 return ret;
401 fmts += ret;
402 }
403
404 if (!fmts)
405 return -ENXIO;
406
407 icd->user_formats =
408 vmalloc(fmts * sizeof(struct soc_camera_format_xlate));
409 if (!icd->user_formats)
410 return -ENOMEM;
411
412 dev_dbg(icd->pdev, "Found %d supported formats.\n", fmts);
413
414 /* Second pass - actually fill data formats */
415 fmts = 0;
416 for (i = 0; i < raw_fmts; i++)
417 if (!ici->ops->get_formats) {
418 v4l2_subdev_call(sd, video, enum_mbus_fmt, i, &code);
419 icd->user_formats[fmts].host_fmt =
420 soc_mbus_get_fmtdesc(code);
421 if (icd->user_formats[fmts].host_fmt)
422 icd->user_formats[fmts++].code = code;
423 } else {
424 ret = ici->ops->get_formats(icd, i,
425 &icd->user_formats[fmts]);
426 if (ret < 0)
427 goto egfmt;
428 fmts += ret;
429 }
430
431 icd->num_user_formats = fmts;
432 icd->current_fmt = &icd->user_formats[0];
433
434 return 0;
435
436egfmt:
437 vfree(icd->user_formats);
438 return ret;
439}
440
441/* Always entered with .video_lock held */
442static void soc_camera_free_user_formats(struct soc_camera_device *icd)
443{
444 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
445
446 if (ici->ops->put_formats)
447 ici->ops->put_formats(icd);
448 icd->current_fmt = NULL;
449 icd->num_user_formats = 0;
450 vfree(icd->user_formats);
451 icd->user_formats = NULL;
452}
453
454/* Called with .vb_lock held, or from the first open(2), see comment there */
455static int soc_camera_set_fmt(struct soc_camera_device *icd,
456 struct v4l2_format *f)
457{
458 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
459 struct v4l2_pix_format *pix = &f->fmt.pix;
460 int ret;
461
462 dev_dbg(icd->pdev, "S_FMT(%c%c%c%c, %ux%u)\n",
463 pixfmtstr(pix->pixelformat), pix->width, pix->height);
464
465 /* We always call try_fmt() before set_fmt() or set_crop() */
466 ret = soc_camera_try_fmt(icd, f);
467 if (ret < 0)
468 return ret;
469
470 ret = ici->ops->set_fmt(icd, f);
471 if (ret < 0) {
472 return ret;
473 } else if (!icd->current_fmt ||
474 icd->current_fmt->host_fmt->fourcc != pix->pixelformat) {
475 dev_err(icd->pdev,
476 "Host driver hasn't set up current format correctly!\n");
477 return -EINVAL;
478 }
479
480 icd->user_width = pix->width;
481 icd->user_height = pix->height;
482 icd->bytesperline = pix->bytesperline;
483 icd->sizeimage = pix->sizeimage;
484 icd->colorspace = pix->colorspace;
485 icd->field = pix->field;
486 if (ici->ops->init_videobuf)
487 icd->vb_vidq.field = pix->field;
488
489 dev_dbg(icd->pdev, "set width: %d height: %d\n",
490 icd->user_width, icd->user_height);
491
492 /* set physical bus parameters */
493 return ici->ops->set_bus_param(icd);
494}
495
496static int soc_camera_open(struct file *file)
497{
498 struct video_device *vdev = video_devdata(file);
499 struct soc_camera_device *icd = dev_get_drvdata(vdev->parent);
500 struct soc_camera_link *icl = to_soc_camera_link(icd);
501 struct soc_camera_host *ici;
502 int ret;
503
504 if (!to_soc_camera_control(icd))
505 /* No device driver attached */
506 return -ENODEV;
507
508 ici = to_soc_camera_host(icd->parent);
509
510 if (mutex_lock_interruptible(&icd->video_lock))
511 return -ERESTARTSYS;
512 if (!try_module_get(ici->ops->owner)) {
513 dev_err(icd->pdev, "Couldn't lock capture bus driver.\n");
514 ret = -EINVAL;
515 goto emodule;
516 }
517
518 icd->use_count++;
519
520 /* Now we really have to activate the camera */
521 if (icd->use_count == 1) {
522 /* Restore parameters before the last close() per V4L2 API */
523 struct v4l2_format f = {
524 .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
525 .fmt.pix = {
526 .width = icd->user_width,
527 .height = icd->user_height,
528 .field = icd->field,
529 .colorspace = icd->colorspace,
530 .pixelformat =
531 icd->current_fmt->host_fmt->fourcc,
532 },
533 };
534
535 /* The camera could have been already on, try to reset */
536 if (icl->reset)
537 icl->reset(icd->pdev);
538
539 /* Don't mess with the host during probe */
540 mutex_lock(&ici->host_lock);
541 ret = ici->ops->add(icd);
542 mutex_unlock(&ici->host_lock);
543 if (ret < 0) {
544 dev_err(icd->pdev, "Couldn't activate the camera: %d\n", ret);
545 goto eiciadd;
546 }
547
548 ret = soc_camera_power_on(icd, icl);
549 if (ret < 0)
550 goto epower;
551
552 pm_runtime_enable(&icd->vdev->dev);
553 ret = pm_runtime_resume(&icd->vdev->dev);
554 if (ret < 0 && ret != -ENOSYS)
555 goto eresume;
556
557 /*
558 * Try to configure with default parameters. Notice: this is the
559 * very first open, so, we cannot race against other calls,
560 * apart from someone else calling open() simultaneously, but
561 * .video_lock is protecting us against it.
562 */
563 ret = soc_camera_set_fmt(icd, &f);
564 if (ret < 0)
565 goto esfmt;
566
567 if (ici->ops->init_videobuf) {
568 ici->ops->init_videobuf(&icd->vb_vidq, icd);
569 } else {
570 ret = ici->ops->init_videobuf2(&icd->vb2_vidq, icd);
571 if (ret < 0)
572 goto einitvb;
573 }
574 v4l2_ctrl_handler_setup(&icd->ctrl_handler);
575 }
576 mutex_unlock(&icd->video_lock);
577
578 file->private_data = icd;
579 dev_dbg(icd->pdev, "camera device open\n");
580
581 return 0;
582
583 /*
584 * First four errors are entered with the .video_lock held
585 * and use_count == 1
586 */
587einitvb:
588esfmt:
589 pm_runtime_disable(&icd->vdev->dev);
590eresume:
591 soc_camera_power_off(icd, icl);
592epower:
593 ici->ops->remove(icd);
594eiciadd:
595 icd->use_count--;
596 module_put(ici->ops->owner);
597emodule:
598 mutex_unlock(&icd->video_lock);
599
600 return ret;
601}
602
603static int soc_camera_close(struct file *file)
604{
605 struct soc_camera_device *icd = file->private_data;
606 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
607
608 mutex_lock(&icd->video_lock);
609 icd->use_count--;
610 if (!icd->use_count) {
611 struct soc_camera_link *icl = to_soc_camera_link(icd);
612
613 pm_runtime_suspend(&icd->vdev->dev);
614 pm_runtime_disable(&icd->vdev->dev);
615
616 if (ici->ops->init_videobuf2)
617 vb2_queue_release(&icd->vb2_vidq);
618 ici->ops->remove(icd);
619
620 soc_camera_power_off(icd, icl);
621 }
622
623 if (icd->streamer == file)
624 icd->streamer = NULL;
625 mutex_unlock(&icd->video_lock);
626
627 module_put(ici->ops->owner);
628
629 dev_dbg(icd->pdev, "camera device close\n");
630
631 return 0;
632}
633
634static ssize_t soc_camera_read(struct file *file, char __user *buf,
635 size_t count, loff_t *ppos)
636{
637 struct soc_camera_device *icd = file->private_data;
638 int err = -EINVAL;
639
640 dev_err(icd->pdev, "camera device read not implemented\n");
641
642 return err;
643}
644
645static int soc_camera_mmap(struct file *file, struct vm_area_struct *vma)
646{
647 struct soc_camera_device *icd = file->private_data;
648 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
649 int err;
650
651 dev_dbg(icd->pdev, "mmap called, vma=0x%08lx\n", (unsigned long)vma);
652
653 if (icd->streamer != file)
654 return -EBUSY;
655
656 if (mutex_lock_interruptible(&icd->video_lock))
657 return -ERESTARTSYS;
658 if (ici->ops->init_videobuf)
659 err = videobuf_mmap_mapper(&icd->vb_vidq, vma);
660 else
661 err = vb2_mmap(&icd->vb2_vidq, vma);
662 mutex_unlock(&icd->video_lock);
663
664 dev_dbg(icd->pdev, "vma start=0x%08lx, size=%ld, ret=%d\n",
665 (unsigned long)vma->vm_start,
666 (unsigned long)vma->vm_end - (unsigned long)vma->vm_start,
667 err);
668
669 return err;
670}
671
672static unsigned int soc_camera_poll(struct file *file, poll_table *pt)
673{
674 struct soc_camera_device *icd = file->private_data;
675 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
676 unsigned res = POLLERR;
677
678 if (icd->streamer != file)
679 return POLLERR;
680
681 mutex_lock(&icd->video_lock);
682 if (ici->ops->init_videobuf && list_empty(&icd->vb_vidq.stream))
683 dev_err(icd->pdev, "Trying to poll with no queued buffers!\n");
684 else
685 res = ici->ops->poll(file, pt);
686 mutex_unlock(&icd->video_lock);
687 return res;
688}
689
690void soc_camera_lock(struct vb2_queue *vq)
691{
692 struct soc_camera_device *icd = vb2_get_drv_priv(vq);
693 mutex_lock(&icd->video_lock);
694}
695EXPORT_SYMBOL(soc_camera_lock);
696
697void soc_camera_unlock(struct vb2_queue *vq)
698{
699 struct soc_camera_device *icd = vb2_get_drv_priv(vq);
700 mutex_unlock(&icd->video_lock);
701}
702EXPORT_SYMBOL(soc_camera_unlock);
703
704static struct v4l2_file_operations soc_camera_fops = {
705 .owner = THIS_MODULE,
706 .open = soc_camera_open,
707 .release = soc_camera_close,
708 .unlocked_ioctl = video_ioctl2,
709 .read = soc_camera_read,
710 .mmap = soc_camera_mmap,
711 .poll = soc_camera_poll,
712};
713
714static int soc_camera_s_fmt_vid_cap(struct file *file, void *priv,
715 struct v4l2_format *f)
716{
717 struct soc_camera_device *icd = file->private_data;
718 int ret;
719
720 WARN_ON(priv != file->private_data);
721
722 if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) {
723 dev_warn(icd->pdev, "Wrong buf-type %d\n", f->type);
724 return -EINVAL;
725 }
726
727 if (icd->streamer && icd->streamer != file)
728 return -EBUSY;
729
730 if (is_streaming(to_soc_camera_host(icd->parent), icd)) {
731 dev_err(icd->pdev, "S_FMT denied: queue initialised\n");
732 return -EBUSY;
733 }
734
735 ret = soc_camera_set_fmt(icd, f);
736
737 if (!ret && !icd->streamer)
738 icd->streamer = file;
739
740 return ret;
741}
742
743static int soc_camera_enum_fmt_vid_cap(struct file *file, void *priv,
744 struct v4l2_fmtdesc *f)
745{
746 struct soc_camera_device *icd = file->private_data;
747 const struct soc_mbus_pixelfmt *format;
748
749 WARN_ON(priv != file->private_data);
750
751 if (f->index >= icd->num_user_formats)
752 return -EINVAL;
753
754 format = icd->user_formats[f->index].host_fmt;
755
756 if (format->name)
757 strlcpy(f->description, format->name, sizeof(f->description));
758 f->pixelformat = format->fourcc;
759 return 0;
760}
761
762static int soc_camera_g_fmt_vid_cap(struct file *file, void *priv,
763 struct v4l2_format *f)
764{
765 struct soc_camera_device *icd = file->private_data;
766 struct v4l2_pix_format *pix = &f->fmt.pix;
767
768 WARN_ON(priv != file->private_data);
769
770 if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
771 return -EINVAL;
772
773 pix->width = icd->user_width;
774 pix->height = icd->user_height;
775 pix->bytesperline = icd->bytesperline;
776 pix->sizeimage = icd->sizeimage;
777 pix->field = icd->field;
778 pix->pixelformat = icd->current_fmt->host_fmt->fourcc;
779 pix->colorspace = icd->colorspace;
780 dev_dbg(icd->pdev, "current_fmt->fourcc: 0x%08x\n",
781 icd->current_fmt->host_fmt->fourcc);
782 return 0;
783}
784
785static int soc_camera_querycap(struct file *file, void *priv,
786 struct v4l2_capability *cap)
787{
788 struct soc_camera_device *icd = file->private_data;
789 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
790
791 WARN_ON(priv != file->private_data);
792
793 strlcpy(cap->driver, ici->drv_name, sizeof(cap->driver));
794 return ici->ops->querycap(ici, cap);
795}
796
797static int soc_camera_streamon(struct file *file, void *priv,
798 enum v4l2_buf_type i)
799{
800 struct soc_camera_device *icd = file->private_data;
801 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
802 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
803 int ret;
804
805 WARN_ON(priv != file->private_data);
806
807 if (i != V4L2_BUF_TYPE_VIDEO_CAPTURE)
808 return -EINVAL;
809
810 if (icd->streamer != file)
811 return -EBUSY;
812
813 /* This calls buf_queue from host driver's videobuf_queue_ops */
814 if (ici->ops->init_videobuf)
815 ret = videobuf_streamon(&icd->vb_vidq);
816 else
817 ret = vb2_streamon(&icd->vb2_vidq, i);
818
819 if (!ret)
820 v4l2_subdev_call(sd, video, s_stream, 1);
821
822 return ret;
823}
824
825static int soc_camera_streamoff(struct file *file, void *priv,
826 enum v4l2_buf_type i)
827{
828 struct soc_camera_device *icd = file->private_data;
829 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
830 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
831
832 WARN_ON(priv != file->private_data);
833
834 if (i != V4L2_BUF_TYPE_VIDEO_CAPTURE)
835 return -EINVAL;
836
837 if (icd->streamer != file)
838 return -EBUSY;
839
840 /*
841 * This calls buf_release from host driver's videobuf_queue_ops for all
842 * remaining buffers. When the last buffer is freed, stop capture
843 */
844 if (ici->ops->init_videobuf)
845 videobuf_streamoff(&icd->vb_vidq);
846 else
847 vb2_streamoff(&icd->vb2_vidq, i);
848
849 v4l2_subdev_call(sd, video, s_stream, 0);
850
851 return 0;
852}
853
854static int soc_camera_cropcap(struct file *file, void *fh,
855 struct v4l2_cropcap *a)
856{
857 struct soc_camera_device *icd = file->private_data;
858 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
859
860 return ici->ops->cropcap(icd, a);
861}
862
863static int soc_camera_g_crop(struct file *file, void *fh,
864 struct v4l2_crop *a)
865{
866 struct soc_camera_device *icd = file->private_data;
867 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
868 int ret;
869
870 ret = ici->ops->get_crop(icd, a);
871
872 return ret;
873}
874
875/*
876 * According to the V4L2 API, drivers shall not update the struct v4l2_crop
877 * argument with the actual geometry, instead, the user shall use G_CROP to
878 * retrieve it.
879 */
880static int soc_camera_s_crop(struct file *file, void *fh,
881 struct v4l2_crop *a)
882{
883 struct soc_camera_device *icd = file->private_data;
884 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
885 struct v4l2_rect *rect = &a->c;
886 struct v4l2_crop current_crop;
887 int ret;
888
889 if (a->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
890 return -EINVAL;
891
892 dev_dbg(icd->pdev, "S_CROP(%ux%u@%u:%u)\n",
893 rect->width, rect->height, rect->left, rect->top);
894
895 /* If get_crop fails, we'll let host and / or client drivers decide */
896 ret = ici->ops->get_crop(icd, &current_crop);
897
898 /* Prohibit window size change with initialised buffers */
899 if (ret < 0) {
900 dev_err(icd->pdev,
901 "S_CROP denied: getting current crop failed\n");
902 } else if ((a->c.width == current_crop.c.width &&
903 a->c.height == current_crop.c.height) ||
904 !is_streaming(ici, icd)) {
905 /* same size or not streaming - use .set_crop() */
906 ret = ici->ops->set_crop(icd, a);
907 } else if (ici->ops->set_livecrop) {
908 ret = ici->ops->set_livecrop(icd, a);
909 } else {
910 dev_err(icd->pdev,
911 "S_CROP denied: queue initialised and sizes differ\n");
912 ret = -EBUSY;
913 }
914
915 return ret;
916}
917
918static int soc_camera_g_parm(struct file *file, void *fh,
919 struct v4l2_streamparm *a)
920{
921 struct soc_camera_device *icd = file->private_data;
922 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
923
924 if (ici->ops->get_parm)
925 return ici->ops->get_parm(icd, a);
926
927 return -ENOIOCTLCMD;
928}
929
930static int soc_camera_s_parm(struct file *file, void *fh,
931 struct v4l2_streamparm *a)
932{
933 struct soc_camera_device *icd = file->private_data;
934 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
935
936 if (ici->ops->set_parm)
937 return ici->ops->set_parm(icd, a);
938
939 return -ENOIOCTLCMD;
940}
941
942static int soc_camera_g_chip_ident(struct file *file, void *fh,
943 struct v4l2_dbg_chip_ident *id)
944{
945 struct soc_camera_device *icd = file->private_data;
946 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
947
948 return v4l2_subdev_call(sd, core, g_chip_ident, id);
949}
950
951#ifdef CONFIG_VIDEO_ADV_DEBUG
952static int soc_camera_g_register(struct file *file, void *fh,
953 struct v4l2_dbg_register *reg)
954{
955 struct soc_camera_device *icd = file->private_data;
956 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
957
958 return v4l2_subdev_call(sd, core, g_register, reg);
959}
960
961static int soc_camera_s_register(struct file *file, void *fh,
962 struct v4l2_dbg_register *reg)
963{
964 struct soc_camera_device *icd = file->private_data;
965 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
966
967 return v4l2_subdev_call(sd, core, s_register, reg);
968}
969#endif
970
971static int soc_camera_probe(struct soc_camera_device *icd);
972
973/* So far this function cannot fail */
974static void scan_add_host(struct soc_camera_host *ici)
975{
976 struct soc_camera_device *icd;
977
978 mutex_lock(&ici->host_lock);
979
980 list_for_each_entry(icd, &devices, list) {
981 if (icd->iface == ici->nr) {
982 int ret;
983
984 icd->parent = ici->v4l2_dev.dev;
985 ret = soc_camera_probe(icd);
986 }
987 }
988
989 mutex_unlock(&ici->host_lock);
990}
991
992#ifdef CONFIG_I2C_BOARDINFO
993static int soc_camera_init_i2c(struct soc_camera_device *icd,
994 struct soc_camera_link *icl)
995{
996 struct i2c_client *client;
997 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
998 struct i2c_adapter *adap = i2c_get_adapter(icl->i2c_adapter_id);
999 struct v4l2_subdev *subdev;
1000
1001 if (!adap) {
1002 dev_err(icd->pdev, "Cannot get I2C adapter #%d. No driver?\n",
1003 icl->i2c_adapter_id);
1004 goto ei2cga;
1005 }
1006
1007 icl->board_info->platform_data = icl;
1008
1009 subdev = v4l2_i2c_new_subdev_board(&ici->v4l2_dev, adap,
1010 icl->board_info, NULL);
1011 if (!subdev)
1012 goto ei2cnd;
1013
1014 client = v4l2_get_subdevdata(subdev);
1015
1016 /* Use to_i2c_client(dev) to recover the i2c client */
1017 icd->control = &client->dev;
1018
1019 return 0;
1020ei2cnd:
1021 i2c_put_adapter(adap);
1022ei2cga:
1023 return -ENODEV;
1024}
1025
1026static void soc_camera_free_i2c(struct soc_camera_device *icd)
1027{
1028 struct i2c_client *client =
1029 to_i2c_client(to_soc_camera_control(icd));
1030 struct i2c_adapter *adap = client->adapter;
1031
1032 icd->control = NULL;
1033 v4l2_device_unregister_subdev(i2c_get_clientdata(client));
1034 i2c_unregister_device(client);
1035 i2c_put_adapter(adap);
1036}
1037#else
1038#define soc_camera_init_i2c(icd, icl) (-ENODEV)
1039#define soc_camera_free_i2c(icd) do {} while (0)
1040#endif
1041
1042static int soc_camera_video_start(struct soc_camera_device *icd);
1043static int video_dev_create(struct soc_camera_device *icd);
1044/* Called during host-driver probe */
1045static int soc_camera_probe(struct soc_camera_device *icd)
1046{
1047 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1048 struct soc_camera_link *icl = to_soc_camera_link(icd);
1049 struct device *control = NULL;
1050 struct v4l2_subdev *sd;
1051 struct v4l2_mbus_framefmt mf;
1052 int ret;
1053
1054 dev_info(icd->pdev, "Probing %s\n", dev_name(icd->pdev));
1055
1056 /*
1057 * Currently the subdev with the largest number of controls (13) is
1058 * ov6550. So let's pick 16 as a hint for the control handler. Note
1059 * that this is a hint only: too large and you waste some memory, too
1060 * small and there is a (very) small performance hit when looking up
1061 * controls in the internal hash.
1062 */
1063 ret = v4l2_ctrl_handler_init(&icd->ctrl_handler, 16);
1064 if (ret < 0)
1065 return ret;
1066
1067 ret = regulator_bulk_get(icd->pdev, icl->num_regulators,
1068 icl->regulators);
1069 if (ret < 0)
1070 goto ereg;
1071
1072 /* The camera could have been already on, try to reset */
1073 if (icl->reset)
1074 icl->reset(icd->pdev);
1075
1076 ret = ici->ops->add(icd);
1077 if (ret < 0)
1078 goto eadd;
1079
1080 /*
1081 * This will not yet call v4l2_subdev_core_ops::s_power(1), because the
1082 * subdevice has not been initialised yet. We'll have to call it once
1083 * again after initialisation, even though it shouldn't be needed, we
1084 * don't do any IO here.
1085 */
1086 ret = soc_camera_power_on(icd, icl);
1087 if (ret < 0)
1088 goto epower;
1089
1090 /* Must have icd->vdev before registering the device */
1091 ret = video_dev_create(icd);
1092 if (ret < 0)
1093 goto evdc;
1094
1095 /* Non-i2c cameras, e.g., soc_camera_platform, have no board_info */
1096 if (icl->board_info) {
1097 ret = soc_camera_init_i2c(icd, icl);
1098 if (ret < 0)
1099 goto eadddev;
1100 } else if (!icl->add_device || !icl->del_device) {
1101 ret = -EINVAL;
1102 goto eadddev;
1103 } else {
1104 if (icl->module_name)
1105 ret = request_module(icl->module_name);
1106
1107 ret = icl->add_device(icd);
1108 if (ret < 0)
1109 goto eadddev;
1110
1111 /*
1112 * FIXME: this is racy, have to use driver-binding notification,
1113 * when it is available
1114 */
1115 control = to_soc_camera_control(icd);
1116 if (!control || !control->driver || !dev_get_drvdata(control) ||
1117 !try_module_get(control->driver->owner)) {
1118 icl->del_device(icd);
1119 ret = -ENODEV;
1120 goto enodrv;
1121 }
1122 }
1123
1124 sd = soc_camera_to_subdev(icd);
1125 sd->grp_id = soc_camera_grp_id(icd);
1126 v4l2_set_subdev_hostdata(sd, icd);
1127
1128 if (v4l2_ctrl_add_handler(&icd->ctrl_handler, sd->ctrl_handler))
1129 goto ectrl;
1130
1131 /* At this point client .probe() should have run already */
1132 ret = soc_camera_init_user_formats(icd);
1133 if (ret < 0)
1134 goto eiufmt;
1135
1136 icd->field = V4L2_FIELD_ANY;
1137
1138 /*
1139 * ..._video_start() will create a device node, video_register_device()
1140 * itself is protected against concurrent open() calls, but we also have
1141 * to protect our data.
1142 */
1143 mutex_lock(&icd->video_lock);
1144
1145 ret = soc_camera_video_start(icd);
1146 if (ret < 0)
1147 goto evidstart;
1148
1149 ret = v4l2_subdev_call(sd, core, s_power, 1);
1150 if (ret < 0 && ret != -ENOIOCTLCMD)
1151 goto esdpwr;
1152
1153 /* Try to improve our guess of a reasonable window format */
1154 if (!v4l2_subdev_call(sd, video, g_mbus_fmt, &mf)) {
1155 icd->user_width = mf.width;
1156 icd->user_height = mf.height;
1157 icd->colorspace = mf.colorspace;
1158 icd->field = mf.field;
1159 }
1160
1161 ici->ops->remove(icd);
1162
1163 soc_camera_power_off(icd, icl);
1164
1165 mutex_unlock(&icd->video_lock);
1166
1167 return 0;
1168
1169esdpwr:
1170 video_unregister_device(icd->vdev);
1171evidstart:
1172 mutex_unlock(&icd->video_lock);
1173 soc_camera_free_user_formats(icd);
1174eiufmt:
1175ectrl:
1176 if (icl->board_info) {
1177 soc_camera_free_i2c(icd);
1178 } else {
1179 icl->del_device(icd);
1180 module_put(control->driver->owner);
1181 }
1182enodrv:
1183eadddev:
1184 video_device_release(icd->vdev);
1185 icd->vdev = NULL;
1186evdc:
1187 soc_camera_power_off(icd, icl);
1188epower:
1189 ici->ops->remove(icd);
1190eadd:
1191 regulator_bulk_free(icl->num_regulators, icl->regulators);
1192ereg:
1193 v4l2_ctrl_handler_free(&icd->ctrl_handler);
1194 return ret;
1195}
1196
1197/*
1198 * This is called on device_unregister, which only means we have to disconnect
1199 * from the host, but not remove ourselves from the device list
1200 */
1201static int soc_camera_remove(struct soc_camera_device *icd)
1202{
1203 struct soc_camera_link *icl = to_soc_camera_link(icd);
1204 struct video_device *vdev = icd->vdev;
1205
1206 BUG_ON(!icd->parent);
1207
1208 v4l2_ctrl_handler_free(&icd->ctrl_handler);
1209 if (vdev) {
1210 video_unregister_device(vdev);
1211 icd->vdev = NULL;
1212 }
1213
1214 if (icl->board_info) {
1215 soc_camera_free_i2c(icd);
1216 } else {
1217 struct device_driver *drv = to_soc_camera_control(icd)->driver;
1218 if (drv) {
1219 icl->del_device(icd);
1220 module_put(drv->owner);
1221 }
1222 }
1223 soc_camera_free_user_formats(icd);
1224
1225 regulator_bulk_free(icl->num_regulators, icl->regulators);
1226
1227 return 0;
1228}
1229
1230static int default_cropcap(struct soc_camera_device *icd,
1231 struct v4l2_cropcap *a)
1232{
1233 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1234 return v4l2_subdev_call(sd, video, cropcap, a);
1235}
1236
1237static int default_g_crop(struct soc_camera_device *icd, struct v4l2_crop *a)
1238{
1239 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1240 return v4l2_subdev_call(sd, video, g_crop, a);
1241}
1242
1243static int default_s_crop(struct soc_camera_device *icd, struct v4l2_crop *a)
1244{
1245 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1246 return v4l2_subdev_call(sd, video, s_crop, a);
1247}
1248
1249static int default_g_parm(struct soc_camera_device *icd,
1250 struct v4l2_streamparm *parm)
1251{
1252 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1253 return v4l2_subdev_call(sd, video, g_parm, parm);
1254}
1255
1256static int default_s_parm(struct soc_camera_device *icd,
1257 struct v4l2_streamparm *parm)
1258{
1259 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1260 return v4l2_subdev_call(sd, video, s_parm, parm);
1261}
1262
1263static int default_enum_framesizes(struct soc_camera_device *icd,
1264 struct v4l2_frmsizeenum *fsize)
1265{
1266 int ret;
1267 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1268 const struct soc_camera_format_xlate *xlate;
1269 __u32 pixfmt = fsize->pixel_format;
1270 struct v4l2_frmsizeenum fsize_mbus = *fsize;
1271
1272 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1273 if (!xlate)
1274 return -EINVAL;
1275 /* map xlate-code to pixel_format, sensor only handle xlate-code*/
1276 fsize_mbus.pixel_format = xlate->code;
1277
1278 ret = v4l2_subdev_call(sd, video, enum_framesizes, &fsize_mbus);
1279 if (ret < 0)
1280 return ret;
1281
1282 *fsize = fsize_mbus;
1283 fsize->pixel_format = pixfmt;
1284
1285 return 0;
1286}
1287
1288int soc_camera_host_register(struct soc_camera_host *ici)
1289{
1290 struct soc_camera_host *ix;
1291 int ret;
1292
1293 if (!ici || !ici->ops ||
1294 !ici->ops->try_fmt ||
1295 !ici->ops->set_fmt ||
1296 !ici->ops->set_bus_param ||
1297 !ici->ops->querycap ||
1298 ((!ici->ops->init_videobuf ||
1299 !ici->ops->reqbufs) &&
1300 !ici->ops->init_videobuf2) ||
1301 !ici->ops->add ||
1302 !ici->ops->remove ||
1303 !ici->ops->poll ||
1304 !ici->v4l2_dev.dev)
1305 return -EINVAL;
1306
1307 if (!ici->ops->set_crop)
1308 ici->ops->set_crop = default_s_crop;
1309 if (!ici->ops->get_crop)
1310 ici->ops->get_crop = default_g_crop;
1311 if (!ici->ops->cropcap)
1312 ici->ops->cropcap = default_cropcap;
1313 if (!ici->ops->set_parm)
1314 ici->ops->set_parm = default_s_parm;
1315 if (!ici->ops->get_parm)
1316 ici->ops->get_parm = default_g_parm;
1317 if (!ici->ops->enum_framesizes)
1318 ici->ops->enum_framesizes = default_enum_framesizes;
1319
1320 mutex_lock(&list_lock);
1321 list_for_each_entry(ix, &hosts, list) {
1322 if (ix->nr == ici->nr) {
1323 ret = -EBUSY;
1324 goto edevreg;
1325 }
1326 }
1327
1328 ret = v4l2_device_register(ici->v4l2_dev.dev, &ici->v4l2_dev);
1329 if (ret < 0)
1330 goto edevreg;
1331
1332 list_add_tail(&ici->list, &hosts);
1333 mutex_unlock(&list_lock);
1334
1335 mutex_init(&ici->host_lock);
1336 scan_add_host(ici);
1337
1338 return 0;
1339
1340edevreg:
1341 mutex_unlock(&list_lock);
1342 return ret;
1343}
1344EXPORT_SYMBOL(soc_camera_host_register);
1345
1346/* Unregister all clients! */
1347void soc_camera_host_unregister(struct soc_camera_host *ici)
1348{
1349 struct soc_camera_device *icd;
1350
1351 mutex_lock(&list_lock);
1352
1353 list_del(&ici->list);
1354 list_for_each_entry(icd, &devices, list)
1355 if (icd->iface == ici->nr && to_soc_camera_control(icd))
1356 soc_camera_remove(icd);
1357
1358 mutex_unlock(&list_lock);
1359
1360 v4l2_device_unregister(&ici->v4l2_dev);
1361}
1362EXPORT_SYMBOL(soc_camera_host_unregister);
1363
1364/* Image capture device */
1365static int soc_camera_device_register(struct soc_camera_device *icd)
1366{
1367 struct soc_camera_device *ix;
1368 int num = -1, i;
1369
1370 for (i = 0; i < 256 && num < 0; i++) {
1371 num = i;
1372 /* Check if this index is available on this interface */
1373 list_for_each_entry(ix, &devices, list) {
1374 if (ix->iface == icd->iface && ix->devnum == i) {
1375 num = -1;
1376 break;
1377 }
1378 }
1379 }
1380
1381 if (num < 0)
1382 /*
1383 * ok, we have 256 cameras on this host...
1384 * man, stay reasonable...
1385 */
1386 return -ENOMEM;
1387
1388 icd->devnum = num;
1389 icd->use_count = 0;
1390 icd->host_priv = NULL;
1391 mutex_init(&icd->video_lock);
1392
1393 list_add_tail(&icd->list, &devices);
1394
1395 return 0;
1396}
1397
1398static const struct v4l2_ioctl_ops soc_camera_ioctl_ops = {
1399 .vidioc_querycap = soc_camera_querycap,
1400 .vidioc_try_fmt_vid_cap = soc_camera_try_fmt_vid_cap,
1401 .vidioc_g_fmt_vid_cap = soc_camera_g_fmt_vid_cap,
1402 .vidioc_s_fmt_vid_cap = soc_camera_s_fmt_vid_cap,
1403 .vidioc_enum_fmt_vid_cap = soc_camera_enum_fmt_vid_cap,
1404 .vidioc_enum_input = soc_camera_enum_input,
1405 .vidioc_g_input = soc_camera_g_input,
1406 .vidioc_s_input = soc_camera_s_input,
1407 .vidioc_s_std = soc_camera_s_std,
1408 .vidioc_g_std = soc_camera_g_std,
1409 .vidioc_enum_framesizes = soc_camera_enum_framesizes,
1410 .vidioc_reqbufs = soc_camera_reqbufs,
1411 .vidioc_querybuf = soc_camera_querybuf,
1412 .vidioc_qbuf = soc_camera_qbuf,
1413 .vidioc_dqbuf = soc_camera_dqbuf,
1414 .vidioc_create_bufs = soc_camera_create_bufs,
1415 .vidioc_prepare_buf = soc_camera_prepare_buf,
1416 .vidioc_streamon = soc_camera_streamon,
1417 .vidioc_streamoff = soc_camera_streamoff,
1418 .vidioc_cropcap = soc_camera_cropcap,
1419 .vidioc_g_crop = soc_camera_g_crop,
1420 .vidioc_s_crop = soc_camera_s_crop,
1421 .vidioc_g_parm = soc_camera_g_parm,
1422 .vidioc_s_parm = soc_camera_s_parm,
1423 .vidioc_g_chip_ident = soc_camera_g_chip_ident,
1424#ifdef CONFIG_VIDEO_ADV_DEBUG
1425 .vidioc_g_register = soc_camera_g_register,
1426 .vidioc_s_register = soc_camera_s_register,
1427#endif
1428};
1429
1430static int video_dev_create(struct soc_camera_device *icd)
1431{
1432 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1433 struct video_device *vdev = video_device_alloc();
1434
1435 if (!vdev)
1436 return -ENOMEM;
1437
1438 strlcpy(vdev->name, ici->drv_name, sizeof(vdev->name));
1439
1440 vdev->parent = icd->pdev;
1441 vdev->current_norm = V4L2_STD_UNKNOWN;
1442 vdev->fops = &soc_camera_fops;
1443 vdev->ioctl_ops = &soc_camera_ioctl_ops;
1444 vdev->release = video_device_release;
1445 vdev->tvnorms = V4L2_STD_UNKNOWN;
1446 vdev->ctrl_handler = &icd->ctrl_handler;
1447 vdev->lock = &icd->video_lock;
1448
1449 icd->vdev = vdev;
1450
1451 return 0;
1452}
1453
1454/*
1455 * Called from soc_camera_probe() above (with .video_lock held???)
1456 */
1457static int soc_camera_video_start(struct soc_camera_device *icd)
1458{
1459 const struct device_type *type = icd->vdev->dev.type;
1460 int ret;
1461
1462 if (!icd->parent)
1463 return -ENODEV;
1464
1465 ret = video_register_device(icd->vdev, VFL_TYPE_GRABBER, -1);
1466 if (ret < 0) {
1467 dev_err(icd->pdev, "video_register_device failed: %d\n", ret);
1468 return ret;
1469 }
1470
1471 /* Restore device type, possibly set by the subdevice driver */
1472 icd->vdev->dev.type = type;
1473
1474 return 0;
1475}
1476
1477static int __devinit soc_camera_pdrv_probe(struct platform_device *pdev)
1478{
1479 struct soc_camera_link *icl = pdev->dev.platform_data;
1480 struct soc_camera_device *icd;
1481 int ret;
1482
1483 if (!icl)
1484 return -EINVAL;
1485
1486 icd = kzalloc(sizeof(*icd), GFP_KERNEL);
1487 if (!icd)
1488 return -ENOMEM;
1489
1490 icd->iface = icl->bus_id;
1491 icd->link = icl;
1492 icd->pdev = &pdev->dev;
1493 platform_set_drvdata(pdev, icd);
1494
1495 ret = soc_camera_device_register(icd);
1496 if (ret < 0)
1497 goto escdevreg;
1498
1499 icd->user_width = DEFAULT_WIDTH;
1500 icd->user_height = DEFAULT_HEIGHT;
1501
1502 return 0;
1503
1504escdevreg:
1505 kfree(icd);
1506
1507 return ret;
1508}
1509
1510/*
1511 * Only called on rmmod for each platform device, since they are not
1512 * hot-pluggable. Now we know, that all our users - hosts and devices have
1513 * been unloaded already
1514 */
1515static int __devexit soc_camera_pdrv_remove(struct platform_device *pdev)
1516{
1517 struct soc_camera_device *icd = platform_get_drvdata(pdev);
1518
1519 if (!icd)
1520 return -EINVAL;
1521
1522 list_del(&icd->list);
1523
1524 kfree(icd);
1525
1526 return 0;
1527}
1528
1529static struct platform_driver __refdata soc_camera_pdrv = {
1530 .probe = soc_camera_pdrv_probe,
1531 .remove = __devexit_p(soc_camera_pdrv_remove),
1532 .driver = {
1533 .name = "soc-camera-pdrv",
1534 .owner = THIS_MODULE,
1535 },
1536};
1537
1538static int __init soc_camera_init(void)
1539{
1540 return platform_driver_register(&soc_camera_pdrv);
1541}
1542
1543static void __exit soc_camera_exit(void)
1544{
1545 platform_driver_unregister(&soc_camera_pdrv);
1546}
1547
1548module_init(soc_camera_init);
1549module_exit(soc_camera_exit);
1550
1551MODULE_DESCRIPTION("Image capture bus driver");
1552MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1553MODULE_LICENSE("GPL");
1554MODULE_ALIAS("platform:soc-camera-pdrv");
diff --git a/drivers/media/video/tw9910.c b/drivers/media/video/tw9910.c
deleted file mode 100644
index 9f53eacb66e3..000000000000
--- a/drivers/media/video/tw9910.c
+++ /dev/null
@@ -1,956 +0,0 @@
1/*
2 * tw9910 Video Driver
3 *
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 *
7 * Based on ov772x driver,
8 *
9 * Copyright (C) 2008 Kuninori Morimoto <morimoto.kuninori@renesas.com>
10 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
11 * Copyright (C) 2008 Magnus Damm
12 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18
19#include <linux/init.h>
20#include <linux/module.h>
21#include <linux/i2c.h>
22#include <linux/slab.h>
23#include <linux/kernel.h>
24#include <linux/delay.h>
25#include <linux/v4l2-mediabus.h>
26#include <linux/videodev2.h>
27
28#include <media/soc_camera.h>
29#include <media/tw9910.h>
30#include <media/v4l2-chip-ident.h>
31#include <media/v4l2-subdev.h>
32
33#define GET_ID(val) ((val & 0xF8) >> 3)
34#define GET_REV(val) (val & 0x07)
35
36/*
37 * register offset
38 */
39#define ID 0x00 /* Product ID Code Register */
40#define STATUS1 0x01 /* Chip Status Register I */
41#define INFORM 0x02 /* Input Format */
42#define OPFORM 0x03 /* Output Format Control Register */
43#define DLYCTR 0x04 /* Hysteresis and HSYNC Delay Control */
44#define OUTCTR1 0x05 /* Output Control I */
45#define ACNTL1 0x06 /* Analog Control Register 1 */
46#define CROP_HI 0x07 /* Cropping Register, High */
47#define VDELAY_LO 0x08 /* Vertical Delay Register, Low */
48#define VACTIVE_LO 0x09 /* Vertical Active Register, Low */
49#define HDELAY_LO 0x0A /* Horizontal Delay Register, Low */
50#define HACTIVE_LO 0x0B /* Horizontal Active Register, Low */
51#define CNTRL1 0x0C /* Control Register I */
52#define VSCALE_LO 0x0D /* Vertical Scaling Register, Low */
53#define SCALE_HI 0x0E /* Scaling Register, High */
54#define HSCALE_LO 0x0F /* Horizontal Scaling Register, Low */
55#define BRIGHT 0x10 /* BRIGHTNESS Control Register */
56#define CONTRAST 0x11 /* CONTRAST Control Register */
57#define SHARPNESS 0x12 /* SHARPNESS Control Register I */
58#define SAT_U 0x13 /* Chroma (U) Gain Register */
59#define SAT_V 0x14 /* Chroma (V) Gain Register */
60#define HUE 0x15 /* Hue Control Register */
61#define CORING1 0x17
62#define CORING2 0x18 /* Coring and IF compensation */
63#define VBICNTL 0x19 /* VBI Control Register */
64#define ACNTL2 0x1A /* Analog Control 2 */
65#define OUTCTR2 0x1B /* Output Control 2 */
66#define SDT 0x1C /* Standard Selection */
67#define SDTR 0x1D /* Standard Recognition */
68#define TEST 0x1F /* Test Control Register */
69#define CLMPG 0x20 /* Clamping Gain */
70#define IAGC 0x21 /* Individual AGC Gain */
71#define AGCGAIN 0x22 /* AGC Gain */
72#define PEAKWT 0x23 /* White Peak Threshold */
73#define CLMPL 0x24 /* Clamp level */
74#define SYNCT 0x25 /* Sync Amplitude */
75#define MISSCNT 0x26 /* Sync Miss Count Register */
76#define PCLAMP 0x27 /* Clamp Position Register */
77#define VCNTL1 0x28 /* Vertical Control I */
78#define VCNTL2 0x29 /* Vertical Control II */
79#define CKILL 0x2A /* Color Killer Level Control */
80#define COMB 0x2B /* Comb Filter Control */
81#define LDLY 0x2C /* Luma Delay and H Filter Control */
82#define MISC1 0x2D /* Miscellaneous Control I */
83#define LOOP 0x2E /* LOOP Control Register */
84#define MISC2 0x2F /* Miscellaneous Control II */
85#define MVSN 0x30 /* Macrovision Detection */
86#define STATUS2 0x31 /* Chip STATUS II */
87#define HFREF 0x32 /* H monitor */
88#define CLMD 0x33 /* CLAMP MODE */
89#define IDCNTL 0x34 /* ID Detection Control */
90#define CLCNTL1 0x35 /* Clamp Control I */
91#define ANAPLLCTL 0x4C
92#define VBIMIN 0x4D
93#define HSLOWCTL 0x4E
94#define WSS3 0x4F
95#define FILLDATA 0x50
96#define SDID 0x51
97#define DID 0x52
98#define WSS1 0x53
99#define WSS2 0x54
100#define VVBI 0x55
101#define LCTL6 0x56
102#define LCTL7 0x57
103#define LCTL8 0x58
104#define LCTL9 0x59
105#define LCTL10 0x5A
106#define LCTL11 0x5B
107#define LCTL12 0x5C
108#define LCTL13 0x5D
109#define LCTL14 0x5E
110#define LCTL15 0x5F
111#define LCTL16 0x60
112#define LCTL17 0x61
113#define LCTL18 0x62
114#define LCTL19 0x63
115#define LCTL20 0x64
116#define LCTL21 0x65
117#define LCTL22 0x66
118#define LCTL23 0x67
119#define LCTL24 0x68
120#define LCTL25 0x69
121#define LCTL26 0x6A
122#define HSBEGIN 0x6B
123#define HSEND 0x6C
124#define OVSDLY 0x6D
125#define OVSEND 0x6E
126#define VBIDELAY 0x6F
127
128/*
129 * register detail
130 */
131
132/* INFORM */
133#define FC27_ON 0x40 /* 1 : Input crystal clock frequency is 27MHz */
134#define FC27_FF 0x00 /* 0 : Square pixel mode. */
135 /* Must use 24.54MHz for 60Hz field rate */
136 /* source or 29.5MHz for 50Hz field rate */
137#define IFSEL_S 0x10 /* 01 : S-video decoding */
138#define IFSEL_C 0x00 /* 00 : Composite video decoding */
139 /* Y input video selection */
140#define YSEL_M0 0x00 /* 00 : Mux0 selected */
141#define YSEL_M1 0x04 /* 01 : Mux1 selected */
142#define YSEL_M2 0x08 /* 10 : Mux2 selected */
143#define YSEL_M3 0x10 /* 11 : Mux3 selected */
144
145/* OPFORM */
146#define MODE 0x80 /* 0 : CCIR601 compatible YCrCb 4:2:2 format */
147 /* 1 : ITU-R-656 compatible data sequence format */
148#define LEN 0x40 /* 0 : 8-bit YCrCb 4:2:2 output format */
149 /* 1 : 16-bit YCrCb 4:2:2 output format.*/
150#define LLCMODE 0x20 /* 1 : LLC output mode. */
151 /* 0 : free-run output mode */
152#define AINC 0x10 /* Serial interface auto-indexing control */
153 /* 0 : auto-increment */
154 /* 1 : non-auto */
155#define VSCTL 0x08 /* 1 : Vertical out ctrl by DVALID */
156 /* 0 : Vertical out ctrl by HACTIVE and DVALID */
157#define OEN_TRI_SEL_MASK 0x07
158#define OEN_TRI_SEL_ALL_ON 0x00 /* Enable output for Rev0/Rev1 */
159#define OEN_TRI_SEL_ALL_OFF_r0 0x06 /* All tri-stated for Rev0 */
160#define OEN_TRI_SEL_ALL_OFF_r1 0x07 /* All tri-stated for Rev1 */
161
162/* OUTCTR1 */
163#define VSP_LO 0x00 /* 0 : VS pin output polarity is active low */
164#define VSP_HI 0x80 /* 1 : VS pin output polarity is active high. */
165 /* VS pin output control */
166#define VSSL_VSYNC 0x00 /* 0 : VSYNC */
167#define VSSL_VACT 0x10 /* 1 : VACT */
168#define VSSL_FIELD 0x20 /* 2 : FIELD */
169#define VSSL_VVALID 0x30 /* 3 : VVALID */
170#define VSSL_ZERO 0x70 /* 7 : 0 */
171#define HSP_LOW 0x00 /* 0 : HS pin output polarity is active low */
172#define HSP_HI 0x08 /* 1 : HS pin output polarity is active high.*/
173 /* HS pin output control */
174#define HSSL_HACT 0x00 /* 0 : HACT */
175#define HSSL_HSYNC 0x01 /* 1 : HSYNC */
176#define HSSL_DVALID 0x02 /* 2 : DVALID */
177#define HSSL_HLOCK 0x03 /* 3 : HLOCK */
178#define HSSL_ASYNCW 0x04 /* 4 : ASYNCW */
179#define HSSL_ZERO 0x07 /* 7 : 0 */
180
181/* ACNTL1 */
182#define SRESET 0x80 /* resets the device to its default state
183 * but all register content remain unchanged.
184 * This bit is self-resetting.
185 */
186#define ACNTL1_PDN_MASK 0x0e
187#define CLK_PDN 0x08 /* system clock power down */
188#define Y_PDN 0x04 /* Luma ADC power down */
189#define C_PDN 0x02 /* Chroma ADC power down */
190
191/* ACNTL2 */
192#define ACNTL2_PDN_MASK 0x40
193#define PLL_PDN 0x40 /* PLL power down */
194
195/* VBICNTL */
196
197/* RTSEL : control the real time signal output from the MPOUT pin */
198#define RTSEL_MASK 0x07
199#define RTSEL_VLOSS 0x00 /* 0000 = Video loss */
200#define RTSEL_HLOCK 0x01 /* 0001 = H-lock */
201#define RTSEL_SLOCK 0x02 /* 0010 = S-lock */
202#define RTSEL_VLOCK 0x03 /* 0011 = V-lock */
203#define RTSEL_MONO 0x04 /* 0100 = MONO */
204#define RTSEL_DET50 0x05 /* 0101 = DET50 */
205#define RTSEL_FIELD 0x06 /* 0110 = FIELD */
206#define RTSEL_RTCO 0x07 /* 0111 = RTCO ( Real Time Control ) */
207
208/* HSYNC start and end are constant for now */
209#define HSYNC_START 0x0260
210#define HSYNC_END 0x0300
211
212/*
213 * structure
214 */
215
216struct regval_list {
217 unsigned char reg_num;
218 unsigned char value;
219};
220
221struct tw9910_scale_ctrl {
222 char *name;
223 unsigned short width;
224 unsigned short height;
225 u16 hscale;
226 u16 vscale;
227};
228
229struct tw9910_priv {
230 struct v4l2_subdev subdev;
231 struct tw9910_video_info *info;
232 const struct tw9910_scale_ctrl *scale;
233 v4l2_std_id norm;
234 u32 revision;
235};
236
237static const struct tw9910_scale_ctrl tw9910_ntsc_scales[] = {
238 {
239 .name = "NTSC SQ",
240 .width = 640,
241 .height = 480,
242 .hscale = 0x0100,
243 .vscale = 0x0100,
244 },
245 {
246 .name = "NTSC CCIR601",
247 .width = 720,
248 .height = 480,
249 .hscale = 0x0100,
250 .vscale = 0x0100,
251 },
252 {
253 .name = "NTSC SQ (CIF)",
254 .width = 320,
255 .height = 240,
256 .hscale = 0x0200,
257 .vscale = 0x0200,
258 },
259 {
260 .name = "NTSC CCIR601 (CIF)",
261 .width = 360,
262 .height = 240,
263 .hscale = 0x0200,
264 .vscale = 0x0200,
265 },
266 {
267 .name = "NTSC SQ (QCIF)",
268 .width = 160,
269 .height = 120,
270 .hscale = 0x0400,
271 .vscale = 0x0400,
272 },
273 {
274 .name = "NTSC CCIR601 (QCIF)",
275 .width = 180,
276 .height = 120,
277 .hscale = 0x0400,
278 .vscale = 0x0400,
279 },
280};
281
282static const struct tw9910_scale_ctrl tw9910_pal_scales[] = {
283 {
284 .name = "PAL SQ",
285 .width = 768,
286 .height = 576,
287 .hscale = 0x0100,
288 .vscale = 0x0100,
289 },
290 {
291 .name = "PAL CCIR601",
292 .width = 720,
293 .height = 576,
294 .hscale = 0x0100,
295 .vscale = 0x0100,
296 },
297 {
298 .name = "PAL SQ (CIF)",
299 .width = 384,
300 .height = 288,
301 .hscale = 0x0200,
302 .vscale = 0x0200,
303 },
304 {
305 .name = "PAL CCIR601 (CIF)",
306 .width = 360,
307 .height = 288,
308 .hscale = 0x0200,
309 .vscale = 0x0200,
310 },
311 {
312 .name = "PAL SQ (QCIF)",
313 .width = 192,
314 .height = 144,
315 .hscale = 0x0400,
316 .vscale = 0x0400,
317 },
318 {
319 .name = "PAL CCIR601 (QCIF)",
320 .width = 180,
321 .height = 144,
322 .hscale = 0x0400,
323 .vscale = 0x0400,
324 },
325};
326
327/*
328 * general function
329 */
330static struct tw9910_priv *to_tw9910(const struct i2c_client *client)
331{
332 return container_of(i2c_get_clientdata(client), struct tw9910_priv,
333 subdev);
334}
335
336static int tw9910_mask_set(struct i2c_client *client, u8 command,
337 u8 mask, u8 set)
338{
339 s32 val = i2c_smbus_read_byte_data(client, command);
340 if (val < 0)
341 return val;
342
343 val &= ~mask;
344 val |= set & mask;
345
346 return i2c_smbus_write_byte_data(client, command, val);
347}
348
349static int tw9910_set_scale(struct i2c_client *client,
350 const struct tw9910_scale_ctrl *scale)
351{
352 int ret;
353
354 ret = i2c_smbus_write_byte_data(client, SCALE_HI,
355 (scale->vscale & 0x0F00) >> 4 |
356 (scale->hscale & 0x0F00) >> 8);
357 if (ret < 0)
358 return ret;
359
360 ret = i2c_smbus_write_byte_data(client, HSCALE_LO,
361 scale->hscale & 0x00FF);
362 if (ret < 0)
363 return ret;
364
365 ret = i2c_smbus_write_byte_data(client, VSCALE_LO,
366 scale->vscale & 0x00FF);
367
368 return ret;
369}
370
371static int tw9910_set_hsync(struct i2c_client *client)
372{
373 struct tw9910_priv *priv = to_tw9910(client);
374 int ret;
375
376 /* bit 10 - 3 */
377 ret = i2c_smbus_write_byte_data(client, HSBEGIN,
378 (HSYNC_START & 0x07F8) >> 3);
379 if (ret < 0)
380 return ret;
381
382 /* bit 10 - 3 */
383 ret = i2c_smbus_write_byte_data(client, HSEND,
384 (HSYNC_END & 0x07F8) >> 3);
385 if (ret < 0)
386 return ret;
387
388 /* So far only revisions 0 and 1 have been seen */
389 /* bit 2 - 0 */
390 if (1 == priv->revision)
391 ret = tw9910_mask_set(client, HSLOWCTL, 0x77,
392 (HSYNC_START & 0x0007) << 4 |
393 (HSYNC_END & 0x0007));
394
395 return ret;
396}
397
398static void tw9910_reset(struct i2c_client *client)
399{
400 tw9910_mask_set(client, ACNTL1, SRESET, SRESET);
401 msleep(1);
402}
403
404static int tw9910_power(struct i2c_client *client, int enable)
405{
406 int ret;
407 u8 acntl1;
408 u8 acntl2;
409
410 if (enable) {
411 acntl1 = 0;
412 acntl2 = 0;
413 } else {
414 acntl1 = CLK_PDN | Y_PDN | C_PDN;
415 acntl2 = PLL_PDN;
416 }
417
418 ret = tw9910_mask_set(client, ACNTL1, ACNTL1_PDN_MASK, acntl1);
419 if (ret < 0)
420 return ret;
421
422 return tw9910_mask_set(client, ACNTL2, ACNTL2_PDN_MASK, acntl2);
423}
424
425static const struct tw9910_scale_ctrl *tw9910_select_norm(v4l2_std_id norm,
426 u32 width, u32 height)
427{
428 const struct tw9910_scale_ctrl *scale;
429 const struct tw9910_scale_ctrl *ret = NULL;
430 __u32 diff = 0xffffffff, tmp;
431 int size, i;
432
433 if (norm & V4L2_STD_NTSC) {
434 scale = tw9910_ntsc_scales;
435 size = ARRAY_SIZE(tw9910_ntsc_scales);
436 } else if (norm & V4L2_STD_PAL) {
437 scale = tw9910_pal_scales;
438 size = ARRAY_SIZE(tw9910_pal_scales);
439 } else {
440 return NULL;
441 }
442
443 for (i = 0; i < size; i++) {
444 tmp = abs(width - scale[i].width) +
445 abs(height - scale[i].height);
446 if (tmp < diff) {
447 diff = tmp;
448 ret = scale + i;
449 }
450 }
451
452 return ret;
453}
454
455/*
456 * subdevice operations
457 */
458static int tw9910_s_stream(struct v4l2_subdev *sd, int enable)
459{
460 struct i2c_client *client = v4l2_get_subdevdata(sd);
461 struct tw9910_priv *priv = to_tw9910(client);
462 u8 val;
463 int ret;
464
465 if (!enable) {
466 switch (priv->revision) {
467 case 0:
468 val = OEN_TRI_SEL_ALL_OFF_r0;
469 break;
470 case 1:
471 val = OEN_TRI_SEL_ALL_OFF_r1;
472 break;
473 default:
474 dev_err(&client->dev, "un-supported revision\n");
475 return -EINVAL;
476 }
477 } else {
478 val = OEN_TRI_SEL_ALL_ON;
479
480 if (!priv->scale) {
481 dev_err(&client->dev, "norm select error\n");
482 return -EPERM;
483 }
484
485 dev_dbg(&client->dev, "%s %dx%d\n",
486 priv->scale->name,
487 priv->scale->width,
488 priv->scale->height);
489 }
490
491 ret = tw9910_mask_set(client, OPFORM, OEN_TRI_SEL_MASK, val);
492 if (ret < 0)
493 return ret;
494
495 return tw9910_power(client, enable);
496}
497
498static int tw9910_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
499{
500 struct i2c_client *client = v4l2_get_subdevdata(sd);
501 struct tw9910_priv *priv = to_tw9910(client);
502
503 *norm = priv->norm;
504
505 return 0;
506}
507
508static int tw9910_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)
509{
510 struct i2c_client *client = v4l2_get_subdevdata(sd);
511 struct tw9910_priv *priv = to_tw9910(client);
512
513 if (!(norm & (V4L2_STD_NTSC | V4L2_STD_PAL)))
514 return -EINVAL;
515
516 priv->norm = norm;
517
518 return 0;
519}
520
521static int tw9910_g_chip_ident(struct v4l2_subdev *sd,
522 struct v4l2_dbg_chip_ident *id)
523{
524 struct i2c_client *client = v4l2_get_subdevdata(sd);
525 struct tw9910_priv *priv = to_tw9910(client);
526
527 id->ident = V4L2_IDENT_TW9910;
528 id->revision = priv->revision;
529
530 return 0;
531}
532
533#ifdef CONFIG_VIDEO_ADV_DEBUG
534static int tw9910_g_register(struct v4l2_subdev *sd,
535 struct v4l2_dbg_register *reg)
536{
537 struct i2c_client *client = v4l2_get_subdevdata(sd);
538 int ret;
539
540 if (reg->reg > 0xff)
541 return -EINVAL;
542
543 ret = i2c_smbus_read_byte_data(client, reg->reg);
544 if (ret < 0)
545 return ret;
546
547 /*
548 * ret = int
549 * reg->val = __u64
550 */
551 reg->val = (__u64)ret;
552
553 return 0;
554}
555
556static int tw9910_s_register(struct v4l2_subdev *sd,
557 struct v4l2_dbg_register *reg)
558{
559 struct i2c_client *client = v4l2_get_subdevdata(sd);
560
561 if (reg->reg > 0xff ||
562 reg->val > 0xff)
563 return -EINVAL;
564
565 return i2c_smbus_write_byte_data(client, reg->reg, reg->val);
566}
567#endif
568
569static int tw9910_set_frame(struct v4l2_subdev *sd, u32 *width, u32 *height)
570{
571 struct i2c_client *client = v4l2_get_subdevdata(sd);
572 struct tw9910_priv *priv = to_tw9910(client);
573 int ret = -EINVAL;
574 u8 val;
575
576 /*
577 * select suitable norm
578 */
579 priv->scale = tw9910_select_norm(priv->norm, *width, *height);
580 if (!priv->scale)
581 goto tw9910_set_fmt_error;
582
583 /*
584 * reset hardware
585 */
586 tw9910_reset(client);
587
588 /*
589 * set bus width
590 */
591 val = 0x00;
592 if (SOCAM_DATAWIDTH_16 == priv->info->buswidth)
593 val = LEN;
594
595 ret = tw9910_mask_set(client, OPFORM, LEN, val);
596 if (ret < 0)
597 goto tw9910_set_fmt_error;
598
599 /*
600 * select MPOUT behavior
601 */
602 switch (priv->info->mpout) {
603 case TW9910_MPO_VLOSS:
604 val = RTSEL_VLOSS; break;
605 case TW9910_MPO_HLOCK:
606 val = RTSEL_HLOCK; break;
607 case TW9910_MPO_SLOCK:
608 val = RTSEL_SLOCK; break;
609 case TW9910_MPO_VLOCK:
610 val = RTSEL_VLOCK; break;
611 case TW9910_MPO_MONO:
612 val = RTSEL_MONO; break;
613 case TW9910_MPO_DET50:
614 val = RTSEL_DET50; break;
615 case TW9910_MPO_FIELD:
616 val = RTSEL_FIELD; break;
617 case TW9910_MPO_RTCO:
618 val = RTSEL_RTCO; break;
619 default:
620 val = 0;
621 }
622
623 ret = tw9910_mask_set(client, VBICNTL, RTSEL_MASK, val);
624 if (ret < 0)
625 goto tw9910_set_fmt_error;
626
627 /*
628 * set scale
629 */
630 ret = tw9910_set_scale(client, priv->scale);
631 if (ret < 0)
632 goto tw9910_set_fmt_error;
633
634 /*
635 * set hsync
636 */
637 ret = tw9910_set_hsync(client);
638 if (ret < 0)
639 goto tw9910_set_fmt_error;
640
641 *width = priv->scale->width;
642 *height = priv->scale->height;
643
644 return ret;
645
646tw9910_set_fmt_error:
647
648 tw9910_reset(client);
649 priv->scale = NULL;
650
651 return ret;
652}
653
654static int tw9910_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *a)
655{
656 struct i2c_client *client = v4l2_get_subdevdata(sd);
657 struct tw9910_priv *priv = to_tw9910(client);
658
659 a->c.left = 0;
660 a->c.top = 0;
661 if (priv->norm & V4L2_STD_NTSC) {
662 a->c.width = 640;
663 a->c.height = 480;
664 } else {
665 a->c.width = 768;
666 a->c.height = 576;
667 }
668 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
669
670 return 0;
671}
672
673static int tw9910_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *a)
674{
675 struct i2c_client *client = v4l2_get_subdevdata(sd);
676 struct tw9910_priv *priv = to_tw9910(client);
677
678 a->bounds.left = 0;
679 a->bounds.top = 0;
680 if (priv->norm & V4L2_STD_NTSC) {
681 a->bounds.width = 640;
682 a->bounds.height = 480;
683 } else {
684 a->bounds.width = 768;
685 a->bounds.height = 576;
686 }
687 a->defrect = a->bounds;
688 a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
689 a->pixelaspect.numerator = 1;
690 a->pixelaspect.denominator = 1;
691
692 return 0;
693}
694
695static int tw9910_g_fmt(struct v4l2_subdev *sd,
696 struct v4l2_mbus_framefmt *mf)
697{
698 struct i2c_client *client = v4l2_get_subdevdata(sd);
699 struct tw9910_priv *priv = to_tw9910(client);
700
701 if (!priv->scale) {
702 priv->scale = tw9910_select_norm(priv->norm, 640, 480);
703 if (!priv->scale)
704 return -EINVAL;
705 }
706
707 mf->width = priv->scale->width;
708 mf->height = priv->scale->height;
709 mf->code = V4L2_MBUS_FMT_UYVY8_2X8;
710 mf->colorspace = V4L2_COLORSPACE_JPEG;
711 mf->field = V4L2_FIELD_INTERLACED_BT;
712
713 return 0;
714}
715
716static int tw9910_s_fmt(struct v4l2_subdev *sd,
717 struct v4l2_mbus_framefmt *mf)
718{
719 u32 width = mf->width, height = mf->height;
720 int ret;
721
722 WARN_ON(mf->field != V4L2_FIELD_ANY &&
723 mf->field != V4L2_FIELD_INTERLACED_BT);
724
725 /*
726 * check color format
727 */
728 if (mf->code != V4L2_MBUS_FMT_UYVY8_2X8)
729 return -EINVAL;
730
731 mf->colorspace = V4L2_COLORSPACE_JPEG;
732
733 ret = tw9910_set_frame(sd, &width, &height);
734 if (!ret) {
735 mf->width = width;
736 mf->height = height;
737 }
738 return ret;
739}
740
741static int tw9910_try_fmt(struct v4l2_subdev *sd,
742 struct v4l2_mbus_framefmt *mf)
743{
744 struct i2c_client *client = v4l2_get_subdevdata(sd);
745 struct tw9910_priv *priv = to_tw9910(client);
746 const struct tw9910_scale_ctrl *scale;
747
748 if (V4L2_FIELD_ANY == mf->field) {
749 mf->field = V4L2_FIELD_INTERLACED_BT;
750 } else if (V4L2_FIELD_INTERLACED_BT != mf->field) {
751 dev_err(&client->dev, "Field type %d invalid.\n", mf->field);
752 return -EINVAL;
753 }
754
755 mf->code = V4L2_MBUS_FMT_UYVY8_2X8;
756 mf->colorspace = V4L2_COLORSPACE_JPEG;
757
758 /*
759 * select suitable norm
760 */
761 scale = tw9910_select_norm(priv->norm, mf->width, mf->height);
762 if (!scale)
763 return -EINVAL;
764
765 mf->width = scale->width;
766 mf->height = scale->height;
767
768 return 0;
769}
770
771static int tw9910_video_probe(struct i2c_client *client)
772{
773 struct tw9910_priv *priv = to_tw9910(client);
774 s32 id;
775
776 /*
777 * tw9910 only use 8 or 16 bit bus width
778 */
779 if (SOCAM_DATAWIDTH_16 != priv->info->buswidth &&
780 SOCAM_DATAWIDTH_8 != priv->info->buswidth) {
781 dev_err(&client->dev, "bus width error\n");
782 return -ENODEV;
783 }
784
785 /*
786 * check and show Product ID
787 * So far only revisions 0 and 1 have been seen
788 */
789 id = i2c_smbus_read_byte_data(client, ID);
790 priv->revision = GET_REV(id);
791 id = GET_ID(id);
792
793 if (0x0B != id ||
794 0x01 < priv->revision) {
795 dev_err(&client->dev,
796 "Product ID error %x:%x\n",
797 id, priv->revision);
798 return -ENODEV;
799 }
800
801 dev_info(&client->dev,
802 "tw9910 Product ID %0x:%0x\n", id, priv->revision);
803
804 priv->norm = V4L2_STD_NTSC;
805
806 return 0;
807}
808
809static struct v4l2_subdev_core_ops tw9910_subdev_core_ops = {
810 .g_chip_ident = tw9910_g_chip_ident,
811 .s_std = tw9910_s_std,
812 .g_std = tw9910_g_std,
813#ifdef CONFIG_VIDEO_ADV_DEBUG
814 .g_register = tw9910_g_register,
815 .s_register = tw9910_s_register,
816#endif
817};
818
819static int tw9910_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
820 enum v4l2_mbus_pixelcode *code)
821{
822 if (index)
823 return -EINVAL;
824
825 *code = V4L2_MBUS_FMT_UYVY8_2X8;
826 return 0;
827}
828
829static int tw9910_g_mbus_config(struct v4l2_subdev *sd,
830 struct v4l2_mbus_config *cfg)
831{
832 struct i2c_client *client = v4l2_get_subdevdata(sd);
833 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
834
835 cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
836 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_VSYNC_ACTIVE_LOW |
837 V4L2_MBUS_HSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_LOW |
838 V4L2_MBUS_DATA_ACTIVE_HIGH;
839 cfg->type = V4L2_MBUS_PARALLEL;
840 cfg->flags = soc_camera_apply_board_flags(icl, cfg);
841
842 return 0;
843}
844
845static int tw9910_s_mbus_config(struct v4l2_subdev *sd,
846 const struct v4l2_mbus_config *cfg)
847{
848 struct i2c_client *client = v4l2_get_subdevdata(sd);
849 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
850 u8 val = VSSL_VVALID | HSSL_DVALID;
851 unsigned long flags = soc_camera_apply_board_flags(icl, cfg);
852
853 /*
854 * set OUTCTR1
855 *
856 * We use VVALID and DVALID signals to control VSYNC and HSYNC
857 * outputs, in this mode their polarity is inverted.
858 */
859 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
860 val |= HSP_HI;
861
862 if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
863 val |= VSP_HI;
864
865 return i2c_smbus_write_byte_data(client, OUTCTR1, val);
866}
867
868static struct v4l2_subdev_video_ops tw9910_subdev_video_ops = {
869 .s_stream = tw9910_s_stream,
870 .g_mbus_fmt = tw9910_g_fmt,
871 .s_mbus_fmt = tw9910_s_fmt,
872 .try_mbus_fmt = tw9910_try_fmt,
873 .cropcap = tw9910_cropcap,
874 .g_crop = tw9910_g_crop,
875 .enum_mbus_fmt = tw9910_enum_fmt,
876 .g_mbus_config = tw9910_g_mbus_config,
877 .s_mbus_config = tw9910_s_mbus_config,
878};
879
880static struct v4l2_subdev_ops tw9910_subdev_ops = {
881 .core = &tw9910_subdev_core_ops,
882 .video = &tw9910_subdev_video_ops,
883};
884
885/*
886 * i2c_driver function
887 */
888
889static int tw9910_probe(struct i2c_client *client,
890 const struct i2c_device_id *did)
891
892{
893 struct tw9910_priv *priv;
894 struct tw9910_video_info *info;
895 struct i2c_adapter *adapter =
896 to_i2c_adapter(client->dev.parent);
897 struct soc_camera_link *icl = soc_camera_i2c_to_link(client);
898 int ret;
899
900 if (!icl || !icl->priv) {
901 dev_err(&client->dev, "TW9910: missing platform data!\n");
902 return -EINVAL;
903 }
904
905 info = icl->priv;
906
907 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
908 dev_err(&client->dev,
909 "I2C-Adapter doesn't support "
910 "I2C_FUNC_SMBUS_BYTE_DATA\n");
911 return -EIO;
912 }
913
914 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
915 if (!priv)
916 return -ENOMEM;
917
918 priv->info = info;
919
920 v4l2_i2c_subdev_init(&priv->subdev, client, &tw9910_subdev_ops);
921
922 ret = tw9910_video_probe(client);
923 if (ret)
924 kfree(priv);
925
926 return ret;
927}
928
929static int tw9910_remove(struct i2c_client *client)
930{
931 struct tw9910_priv *priv = to_tw9910(client);
932
933 kfree(priv);
934 return 0;
935}
936
937static const struct i2c_device_id tw9910_id[] = {
938 { "tw9910", 0 },
939 { }
940};
941MODULE_DEVICE_TABLE(i2c, tw9910_id);
942
943static struct i2c_driver tw9910_i2c_driver = {
944 .driver = {
945 .name = "tw9910",
946 },
947 .probe = tw9910_probe,
948 .remove = tw9910_remove,
949 .id_table = tw9910_id,
950};
951
952module_i2c_driver(tw9910_i2c_driver);
953
954MODULE_DESCRIPTION("SoC Camera driver for tw9910");
955MODULE_AUTHOR("Kuninori Morimoto");
956MODULE_LICENSE("GPL v2");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-13 05:22:44 -0500