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authorSri Deevi <srinivasa.deevi@conexant.com>2009-03-10 20:16:26 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2009-04-06 20:44:04 -0400
commit6e4f574ba43511ac1cb860027275e08529c5a28f (patch)
tree6e710a1f93e12c001b2d8634d1a344690586a6ac /drivers/media/video
parentb9255176453086b2531c5559350bd5c92b771cc5 (diff)
V4L/DVB (10958): cx231xx: some additional CodingStyle and minor fixes
changed the pcb-config.c/h to pcb-cfg.c/h for short names. Signed-off-by: Srinivasa Deevi <srinivasa.deevi@conexant.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/video')
-rw-r--r--drivers/media/video/Kconfig2
-rw-r--r--drivers/media/video/cx231xx/Kconfig50
-rw-r--r--drivers/media/video/cx231xx/Makefile7
-rw-r--r--drivers/media/video/cx231xx/cx231xx-audio.c14
-rw-r--r--drivers/media/video/cx231xx/cx231xx-avcore.c305
-rw-r--r--drivers/media/video/cx231xx/cx231xx-cards.c248
-rw-r--r--drivers/media/video/cx231xx/cx231xx-conf-reg.h299
-rw-r--r--drivers/media/video/cx231xx/cx231xx-core.c13
-rw-r--r--drivers/media/video/cx231xx/cx231xx-i2c.c12
-rw-r--r--drivers/media/video/cx231xx/cx231xx-pcb-cfg.c793
-rw-r--r--drivers/media/video/cx231xx/cx231xx-pcb-cfg.h235
-rw-r--r--drivers/media/video/cx231xx/cx231xx-reg.h934
-rw-r--r--drivers/media/video/cx231xx/cx231xx-video.c8
-rw-r--r--drivers/media/video/cx231xx/cx231xx.h14
14 files changed, 1963 insertions, 971 deletions
diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
index 159229fc838d..9d48da2fb013 100644
--- a/drivers/media/video/Kconfig
+++ b/drivers/media/video/Kconfig
@@ -807,6 +807,8 @@ source "drivers/media/video/hdpvr/Kconfig"
807 807
808source "drivers/media/video/em28xx/Kconfig" 808source "drivers/media/video/em28xx/Kconfig"
809 809
810source "drivers/media/video/cx231xx/Kconfig"
811
810source "drivers/media/video/usbvision/Kconfig" 812source "drivers/media/video/usbvision/Kconfig"
811 813
812source "drivers/media/video/usbvideo/Kconfig" 814source "drivers/media/video/usbvideo/Kconfig"
diff --git a/drivers/media/video/cx231xx/Kconfig b/drivers/media/video/cx231xx/Kconfig
index 0f0e2b9d9853..7a6700fb0376 100644
--- a/drivers/media/video/cx231xx/Kconfig
+++ b/drivers/media/video/cx231xx/Kconfig
@@ -1,35 +1,35 @@
1config VIDEO_CX231XX 1config VIDEO_CX231XX
2 tristate "Conexant cx231xx USB video capture support" 2 tristate "Conexant cx231xx USB video capture support"
3 depends on VIDEO_DEV && I2C && INPUT 3 depends on VIDEO_DEV && I2C && INPUT
4 select VIDEO_TUNER 4 select VIDEO_TUNER
5 select VIDEO_TVEEPROM 5 select VIDEO_TVEEPROM
6 select VIDEO_IR 6 select VIDEO_IR
7 select VIDEOBUF_VMALLOC 7 select VIDEOBUF_VMALLOC
8 select VIDEO_CX25840 8 select VIDEO_CX25840
9 select VIDEO_CX231XX_ALSA 9 select VIDEO_CX231XX_ALSA
10 10
11 ---help--- 11 ---help---
12 This is a video4linux driver for Conexant 231xx USB based TV cards. 12 This is a video4linux driver for Conexant 231xx USB based TV cards.
13 13
14 To compile this driver as a module, choose M here: the 14 To compile this driver as a module, choose M here: the
15 module will be called cx231xx 15 module will be called cx231xx
16 16
17config VIDEO_CX231XX_ALSA 17config VIDEO_CX231XX_ALSA
18 tristate "Conexant Cx231xx ALSA audio module" 18 tristate "Conexant Cx231xx ALSA audio module"
19 depends on VIDEO_CX231XX && SND 19 depends on VIDEO_CX231XX && SND
20 select SND_PCM 20 select SND_PCM
21 21
22 ---help--- 22 ---help---
23 This is an ALSA driver for Cx231xx USB based TV cards. 23 This is an ALSA driver for Cx231xx USB based TV cards.
24 24
25 To compile this driver as a module, choose M here: the 25 To compile this driver as a module, choose M here: the
26 module will be called cx231xx-alsa 26 module will be called cx231xx-alsa
27 27
28config VIDEO_CX231XX_DVB 28config VIDEO_CX231XX_DVB
29 tristate "DVB/ATSC Support for Cx231xx based TV cards" 29 tristate "DVB/ATSC Support for Cx231xx based TV cards"
30 depends on VIDEO_CX231XX && DVB_CORE 30 depends on VIDEO_CX231XX && DVB_CORE
31 select VIDEOBUF_DVB 31 select VIDEOBUF_DVB
32 select MEDIA_TUNER_XC5000 if !DVB_FE_CUSTOMIZE 32 select MEDIA_TUNER_XC5000 if !DVB_FE_CUSTOMISE
33 ---help--- 33 ---help---
34 This adds support for DVB cards based on the 34 This adds support for DVB cards based on the
35 Conexant cx231xx chips. 35 Conexant cx231xx chips.
diff --git a/drivers/media/video/cx231xx/Makefile b/drivers/media/video/cx231xx/Makefile
index 2590a09f3442..1dad93619934 100644
--- a/drivers/media/video/cx231xx/Makefile
+++ b/drivers/media/video/cx231xx/Makefile
@@ -1,11 +1,8 @@
1cx231xx-objs := cx231xx-video.o cx231xx-i2c.o cx231xx-cards.o cx231xx-core.o \ 1cx231xx-objs := cx231xx-video.o cx231xx-i2c.o cx231xx-cards.o cx231xx-core.o \
2 cx231xx-avcore.o cx231xx-pcb-config.o cx231xx-vbi.o 2 cx231xx-avcore.o cx231xx-pcb-cfg.o cx231xx-vbi.o
3
4cx231xx-alsa-objs := cx231xx-audio.o
5
6 3
7obj-$(CONFIG_VIDEO_CX231XX) += cx231xx.o 4obj-$(CONFIG_VIDEO_CX231XX) += cx231xx.o
8obj-$(CONFIG_VIDEO_CX231XX_ALSA) += cx231xx-alsa.o 5obj-$(CONFIG_VIDEO_CX231XX_ALSA) += cx231xx-audio.o
9obj-$(CONFIG_VIDEO_CX231XX_DVB) += cx231xx-dvb.o 6obj-$(CONFIG_VIDEO_CX231XX_DVB) += cx231xx-dvb.o
10 7
11EXTRA_CFLAGS += -Idrivers/media/video 8EXTRA_CFLAGS += -Idrivers/media/video
diff --git a/drivers/media/video/cx231xx/cx231xx-audio.c b/drivers/media/video/cx231xx/cx231xx-audio.c
index 044edbc2d844..0027b906f614 100644
--- a/drivers/media/video/cx231xx/cx231xx-audio.c
+++ b/drivers/media/video/cx231xx/cx231xx-audio.c
@@ -38,16 +38,15 @@
38#include <sound/control.h> 38#include <sound/control.h>
39#include <media/v4l2-common.h> 39#include <media/v4l2-common.h>
40#include "cx231xx.h" 40#include "cx231xx.h"
41#include "cx231xx-pcb-config.h"
42 41
43static int debug; 42static int debug;
44module_param(debug, int, 0644); 43module_param(debug, int, 0644);
45MODULE_PARM_DESC(debug, "activates debug info"); 44MODULE_PARM_DESC(debug, "activates debug info");
46 45
47#define dprintk(fmt, arg...) do { \ 46#define dprintk(fmt, arg...) do { \
48 if (debug) \ 47 if (debug) \
49 printk(KERN_INFO "cx231xx-audio %s: " fmt, \ 48 printk(KERN_INFO "cx231xx-audio %s: " fmt, \
50 __func__, ##arg); \ 49 __func__, ##arg); \
51 } while (0) 50 } while (0)
52 51
53static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 52static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
@@ -262,9 +261,10 @@ static int snd_pcm_alloc_vmalloc_buffer(struct snd_pcm_substream *subs,
262} 261}
263 262
264static struct snd_pcm_hardware snd_cx231xx_hw_capture = { 263static struct snd_pcm_hardware snd_cx231xx_hw_capture = {
265 .info = SNDRV_PCM_INFO_BLOCK_TRANSFER | 264 .info = SNDRV_PCM_INFO_BLOCK_TRANSFER |
266 SNDRV_PCM_INFO_MMAP | 265 SNDRV_PCM_INFO_MMAP |
267 SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP_VALID, 266 SNDRV_PCM_INFO_INTERLEAVED |
267 SNDRV_PCM_INFO_MMAP_VALID,
268 268
269 .formats = SNDRV_PCM_FMTBIT_S16_LE, 269 .formats = SNDRV_PCM_FMTBIT_S16_LE,
270 270
diff --git a/drivers/media/video/cx231xx/cx231xx-avcore.c b/drivers/media/video/cx231xx/cx231xx-avcore.c
index 8bbe518f4837..226299d62d7e 100644
--- a/drivers/media/video/cx231xx/cx231xx-avcore.c
+++ b/drivers/media/video/cx231xx/cx231xx-avcore.c
@@ -41,7 +41,7 @@
41 41
42/****************************************************************************** 42/******************************************************************************
43 * C O L I B R I - B L O C K C O N T R O L functions * 43 * C O L I B R I - B L O C K C O N T R O L functions *
44 ********************************************************************* ********/ 44 ******************************************************************************/
45int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count) 45int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count)
46{ 46{
47 int status = 0; 47 int status = 0;
@@ -53,29 +53,44 @@ int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count)
53 temp = (u8) (ref_count & 0xff); 53 temp = (u8) (ref_count & 0xff);
54 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 54 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
55 SUP_BLK_TUNE2, 2, temp, 1); 55 SUP_BLK_TUNE2, 2, temp, 1);
56 if (status < 0)
57 return status;
56 58
57 status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, 59 status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
58 SUP_BLK_TUNE2, 2, 60 SUP_BLK_TUNE2, 2,
59 &colibri_power_status, 1); 61 &colibri_power_status, 1);
62 if (status < 0)
63 return status;
60 64
61 temp = (u8) ((ref_count & 0x300) >> 8); 65 temp = (u8) ((ref_count & 0x300) >> 8);
62 temp |= 0x40; 66 temp |= 0x40;
63 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 67 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
64 SUP_BLK_TUNE1, 2, temp, 1); 68 SUP_BLK_TUNE1, 2, temp, 1);
69 if (status < 0)
70 return status;
71
65 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 72 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
66 SUP_BLK_PLL2, 2, 0x0f, 1); 73 SUP_BLK_PLL2, 2, 0x0f, 1);
74 if (status < 0)
75 return status;
67 76
68 /* enable pll */ 77 /* enable pll */
69 while (colibri_power_status != 0x18) { 78 while (colibri_power_status != 0x18) {
70 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 79 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
71 SUP_BLK_PWRDN, 2, 0x18, 1); 80 SUP_BLK_PWRDN, 2, 0x18, 1);
81 if (status < 0) {
82 cx231xx_info(
83 ": Init Super Block failed in send cmd\n");
84 break;
85 }
86
72 status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS, 87 status = cx231xx_read_i2c_data(dev, Colibri_DEVICE_ADDRESS,
73 SUP_BLK_PWRDN, 2, 88 SUP_BLK_PWRDN, 2,
74 &colibri_power_status, 1); 89 &colibri_power_status, 1);
75 colibri_power_status &= 0xff; 90 colibri_power_status &= 0xff;
76 if (status < 0) { 91 if (status < 0) {
77 cx231xx_info( 92 cx231xx_info(
78 ": Init Super Block failed in send/receive cmds\n"); 93 ": Init Super Block failed in receive cmd\n");
79 break; 94 break;
80 } 95 }
81 i++; 96 i++;
@@ -93,6 +108,9 @@ int cx231xx_colibri_init_super_block(struct cx231xx *dev, u32 ref_count)
93 /* start tuning filter */ 108 /* start tuning filter */
94 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS, 109 status = cx231xx_write_i2c_data(dev, Colibri_DEVICE_ADDRESS,
95 SUP_BLK_TUNE3, 2, 0x40, 1); 110 SUP_BLK_TUNE3, 2, 0x40, 1);
111 if (status < 0)
112 return status;
113
96 msleep(5); 114 msleep(5);
97 115
98 /* exit tuning */ 116 /* exit tuning */
@@ -188,7 +206,10 @@ int cx231xx_colibri_setup_AFE_for_baseband(struct cx231xx *dev)
188} 206}
189 207
190/* 208/*
191 we have 3 channel 209 The Analog Front End in Cx231xx has 3 channels. These
210 channels are used to share between different inputs
211 like tuner, s-video and composite inputs.
212
192 channel 1 ----- pin 1 to pin4(in reg is 1-4) 213 channel 1 ----- pin 1 to pin4(in reg is 1-4)
193 channel 2 ----- pin 5 to pin8(in reg is 5-8) 214 channel 2 ----- pin 5 to pin8(in reg is 5-8)
194 channel 3 ----- pin 9 to pin 12(in reg is 9-11) 215 channel 3 ----- pin 9 to pin 12(in reg is 9-11)
@@ -242,6 +263,11 @@ int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
242{ 263{
243 int status = 0; 264 int status = 0;
244 265
266 /*
267 * FIXME: We need to implement the AFE code for LOW IF and for HI IF.
268 * Currently, only baseband works.
269 */
270
245 switch (mode) { 271 switch (mode) {
246 case AFE_MODE_LOW_IF: 272 case AFE_MODE_LOW_IF:
247 /* SetupAFEforLowIF(); */ 273 /* SetupAFEforLowIF(); */
@@ -270,8 +296,8 @@ int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode)
270 return status; 296 return status;
271} 297}
272 298
273/* For power saving in the EVK */ 299int cx231xx_colibri_update_power_control(struct cx231xx *dev,
274int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode) 300 enum AV_MODE avmode)
275{ 301{
276 u32 colibri_power_status = 0; 302 u32 colibri_power_status = 0;
277 int status = 0; 303 int status = 0;
@@ -279,14 +305,16 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode)
279 switch (dev->model) { 305 switch (dev->model) {
280 case CX231XX_BOARD_CNXT_RDE_250: 306 case CX231XX_BOARD_CNXT_RDE_250:
281 case CX231XX_BOARD_CNXT_RDU_250: 307 case CX231XX_BOARD_CNXT_RDU_250:
282
283 if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 308 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
284 while (colibri_power_status != 0x18) { 309 while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS |
310 FLD_PWRDN_ENABLE_PLL)) {
285 status = cx231xx_write_i2c_data(dev, 311 status = cx231xx_write_i2c_data(dev,
286 Colibri_DEVICE_ADDRESS, 312 Colibri_DEVICE_ADDRESS,
287 SUP_BLK_PWRDN, 2, 313 SUP_BLK_PWRDN, 2,
288 0x18, 1); 314 FLD_PWRDN_TUNING_BIAS |
289 status = cx231xx_read_i2c_data(dev, 315 FLD_PWRDN_ENABLE_PLL,
316 1);
317 status |= cx231xx_read_i2c_data(dev,
290 Colibri_DEVICE_ADDRESS, 318 Colibri_DEVICE_ADDRESS,
291 SUP_BLK_PWRDN, 2, 319 SUP_BLK_PWRDN, 2,
292 &colibri_power_status, 320 &colibri_power_status,
@@ -299,11 +327,11 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode)
299 Colibri_DEVICE_ADDRESS, 327 Colibri_DEVICE_ADDRESS,
300 ADC_PWRDN_CLAMP_CH1, 2, 0x00, 328 ADC_PWRDN_CLAMP_CH1, 2, 0x00,
301 1); 329 1);
302 status = cx231xx_write_i2c_data(dev, 330 status |= cx231xx_write_i2c_data(dev,
303 Colibri_DEVICE_ADDRESS, 331 Colibri_DEVICE_ADDRESS,
304 ADC_PWRDN_CLAMP_CH2, 2, 0x00, 332 ADC_PWRDN_CLAMP_CH2, 2, 0x00,
305 1); 333 1);
306 status = cx231xx_write_i2c_data(dev, 334 status |= cx231xx_write_i2c_data(dev,
307 Colibri_DEVICE_ADDRESS, 335 Colibri_DEVICE_ADDRESS,
308 ADC_PWRDN_CLAMP_CH3, 2, 0x00, 336 ADC_PWRDN_CLAMP_CH3, 2, 0x00,
309 1); 337 1);
@@ -312,32 +340,36 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode)
312 Colibri_DEVICE_ADDRESS, 340 Colibri_DEVICE_ADDRESS,
313 ADC_PWRDN_CLAMP_CH1, 2, 0x70, 341 ADC_PWRDN_CLAMP_CH1, 2, 0x70,
314 1); 342 1);
315 status = cx231xx_write_i2c_data(dev, 343 status |= cx231xx_write_i2c_data(dev,
316 Colibri_DEVICE_ADDRESS, 344 Colibri_DEVICE_ADDRESS,
317 ADC_PWRDN_CLAMP_CH2, 2, 0x70, 345 ADC_PWRDN_CLAMP_CH2, 2, 0x70,
318 1); 346 1);
319 status = cx231xx_write_i2c_data(dev, 347 status |= cx231xx_write_i2c_data(dev,
320 Colibri_DEVICE_ADDRESS, 348 Colibri_DEVICE_ADDRESS,
321 ADC_PWRDN_CLAMP_CH3, 2, 0x70, 349 ADC_PWRDN_CLAMP_CH3, 2, 0x70,
322 1); 350 1);
323 351
324 status = cx231xx_read_i2c_data(dev, 352 status |= cx231xx_read_i2c_data(dev,
325 Colibri_DEVICE_ADDRESS, 353 Colibri_DEVICE_ADDRESS,
326 SUP_BLK_PWRDN, 2, 354 SUP_BLK_PWRDN, 2,
327 &colibri_power_status, 1); 355 &colibri_power_status, 1);
328 colibri_power_status |= 0x07; 356 colibri_power_status |= FLD_PWRDN_PD_BANDGAP |
329 status = cx231xx_write_i2c_data(dev, 357 FLD_PWRDN_PD_BIAS |
358 FLD_PWRDN_PD_TUNECK;
359 status |= cx231xx_write_i2c_data(dev,
330 Colibri_DEVICE_ADDRESS, 360 Colibri_DEVICE_ADDRESS,
331 SUP_BLK_PWRDN, 2, 361 SUP_BLK_PWRDN, 2,
332 colibri_power_status, 1); 362 colibri_power_status, 1);
333 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 363 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
334 364 while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS |
335 while (colibri_power_status != 0x18) { 365 FLD_PWRDN_ENABLE_PLL)) {
336 status = cx231xx_write_i2c_data(dev, 366 status = cx231xx_write_i2c_data(dev,
337 Colibri_DEVICE_ADDRESS, 367 Colibri_DEVICE_ADDRESS,
338 SUP_BLK_PWRDN, 2, 368 SUP_BLK_PWRDN, 2,
339 0x18, 1); 369 FLD_PWRDN_TUNING_BIAS |
340 status = cx231xx_read_i2c_data(dev, 370 FLD_PWRDN_ENABLE_PLL,
371 1);
372 status |= cx231xx_read_i2c_data(dev,
341 Colibri_DEVICE_ADDRESS, 373 Colibri_DEVICE_ADDRESS,
342 SUP_BLK_PWRDN, 2, 374 SUP_BLK_PWRDN, 2,
343 &colibri_power_status, 375 &colibri_power_status,
@@ -346,15 +378,15 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode)
346 break; 378 break;
347 } 379 }
348 380
349 status = cx231xx_write_i2c_data(dev, 381 status |= cx231xx_write_i2c_data(dev,
350 Colibri_DEVICE_ADDRESS, 382 Colibri_DEVICE_ADDRESS,
351 ADC_PWRDN_CLAMP_CH1, 2, 0x00, 383 ADC_PWRDN_CLAMP_CH1, 2, 0x00,
352 1); 384 1);
353 status = cx231xx_write_i2c_data(dev, 385 status |= cx231xx_write_i2c_data(dev,
354 Colibri_DEVICE_ADDRESS, 386 Colibri_DEVICE_ADDRESS,
355 ADC_PWRDN_CLAMP_CH2, 2, 0x00, 387 ADC_PWRDN_CLAMP_CH2, 2, 0x00,
356 1); 388 1);
357 status = cx231xx_write_i2c_data(dev, 389 status |= cx231xx_write_i2c_data(dev,
358 Colibri_DEVICE_ADDRESS, 390 Colibri_DEVICE_ADDRESS,
359 ADC_PWRDN_CLAMP_CH3, 2, 0x00, 391 ADC_PWRDN_CLAMP_CH3, 2, 0x00,
360 1); 392 1);
@@ -365,12 +397,15 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode)
365 break; 397 break;
366 default: 398 default:
367 if (avmode == POLARIS_AVMODE_ANALOGT_TV) { 399 if (avmode == POLARIS_AVMODE_ANALOGT_TV) {
368 while (colibri_power_status != 0x18) { 400 while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS |
401 FLD_PWRDN_ENABLE_PLL)) {
369 status = cx231xx_write_i2c_data(dev, 402 status = cx231xx_write_i2c_data(dev,
370 Colibri_DEVICE_ADDRESS, 403 Colibri_DEVICE_ADDRESS,
371 SUP_BLK_PWRDN, 2, 404 SUP_BLK_PWRDN, 2,
372 0x18, 1); 405 FLD_PWRDN_TUNING_BIAS |
373 status = cx231xx_read_i2c_data(dev, 406 FLD_PWRDN_ENABLE_PLL,
407 1);
408 status |= cx231xx_read_i2c_data(dev,
374 Colibri_DEVICE_ADDRESS, 409 Colibri_DEVICE_ADDRESS,
375 SUP_BLK_PWRDN, 2, 410 SUP_BLK_PWRDN, 2,
376 &colibri_power_status, 411 &colibri_power_status,
@@ -379,15 +414,15 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode)
379 break; 414 break;
380 } 415 }
381 416
382 status = cx231xx_write_i2c_data(dev, 417 status |= cx231xx_write_i2c_data(dev,
383 Colibri_DEVICE_ADDRESS, 418 Colibri_DEVICE_ADDRESS,
384 ADC_PWRDN_CLAMP_CH1, 2, 419 ADC_PWRDN_CLAMP_CH1, 2,
385 0x40, 1); 420 0x40, 1);
386 status = cx231xx_write_i2c_data(dev, 421 status |= cx231xx_write_i2c_data(dev,
387 Colibri_DEVICE_ADDRESS, 422 Colibri_DEVICE_ADDRESS,
388 ADC_PWRDN_CLAMP_CH2, 2, 423 ADC_PWRDN_CLAMP_CH2, 2,
389 0x40, 1); 424 0x40, 1);
390 status = cx231xx_write_i2c_data(dev, 425 status |= cx231xx_write_i2c_data(dev,
391 Colibri_DEVICE_ADDRESS, 426 Colibri_DEVICE_ADDRESS,
392 ADC_PWRDN_CLAMP_CH3, 2, 427 ADC_PWRDN_CLAMP_CH3, 2,
393 0x00, 1); 428 0x00, 1);
@@ -396,33 +431,38 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode)
396 Colibri_DEVICE_ADDRESS, 431 Colibri_DEVICE_ADDRESS,
397 ADC_PWRDN_CLAMP_CH1, 2, 432 ADC_PWRDN_CLAMP_CH1, 2,
398 0x70, 1); 433 0x70, 1);
399 status = cx231xx_write_i2c_data(dev, 434 status |= cx231xx_write_i2c_data(dev,
400 Colibri_DEVICE_ADDRESS, 435 Colibri_DEVICE_ADDRESS,
401 ADC_PWRDN_CLAMP_CH2, 2, 436 ADC_PWRDN_CLAMP_CH2, 2,
402 0x70, 1); 437 0x70, 1);
403 status = cx231xx_write_i2c_data(dev, 438 status |= cx231xx_write_i2c_data(dev,
404 Colibri_DEVICE_ADDRESS, 439 Colibri_DEVICE_ADDRESS,
405 ADC_PWRDN_CLAMP_CH3, 2, 440 ADC_PWRDN_CLAMP_CH3, 2,
406 0x70, 1); 441 0x70, 1);
407 442
408 status = cx231xx_read_i2c_data(dev, 443 status |= cx231xx_read_i2c_data(dev,
409 Colibri_DEVICE_ADDRESS, 444 Colibri_DEVICE_ADDRESS,
410 SUP_BLK_PWRDN, 2, 445 SUP_BLK_PWRDN, 2,
411 &colibri_power_status, 446 &colibri_power_status,
412 1); 447 1);
413 colibri_power_status |= 0x07; 448 colibri_power_status |= FLD_PWRDN_PD_BANDGAP |
414 status = cx231xx_write_i2c_data(dev, 449 FLD_PWRDN_PD_BIAS |
450 FLD_PWRDN_PD_TUNECK;
451 status |= cx231xx_write_i2c_data(dev,
415 Colibri_DEVICE_ADDRESS, 452 Colibri_DEVICE_ADDRESS,
416 SUP_BLK_PWRDN, 2, 453 SUP_BLK_PWRDN, 2,
417 colibri_power_status, 454 colibri_power_status,
418 1); 455 1);
419 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) { 456 } else if (avmode == POLARIS_AVMODE_ENXTERNAL_AV) {
420 while (colibri_power_status != 0x18) { 457 while (colibri_power_status != (FLD_PWRDN_TUNING_BIAS |
458 FLD_PWRDN_ENABLE_PLL)) {
421 status = cx231xx_write_i2c_data(dev, 459 status = cx231xx_write_i2c_data(dev,
422 Colibri_DEVICE_ADDRESS, 460 Colibri_DEVICE_ADDRESS,
423 SUP_BLK_PWRDN, 2, 461 SUP_BLK_PWRDN, 2,
424 0x18, 1); 462 FLD_PWRDN_TUNING_BIAS |
425 status = cx231xx_read_i2c_data(dev, 463 FLD_PWRDN_ENABLE_PLL,
464 1);
465 status |= cx231xx_read_i2c_data(dev,
426 Colibri_DEVICE_ADDRESS, 466 Colibri_DEVICE_ADDRESS,
427 SUP_BLK_PWRDN, 2, 467 SUP_BLK_PWRDN, 2,
428 &colibri_power_status, 468 &colibri_power_status,
@@ -431,15 +471,15 @@ int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode)
431 break; 471 break;
432 } 472 }
433 473
434 status = cx231xx_write_i2c_data(dev, 474 status |= cx231xx_write_i2c_data(dev,
435 Colibri_DEVICE_ADDRESS, 475 Colibri_DEVICE_ADDRESS,
436 ADC_PWRDN_CLAMP_CH1, 2, 476 ADC_PWRDN_CLAMP_CH1, 2,
437 0x00, 1); 477 0x00, 1);
438 status = cx231xx_write_i2c_data(dev, 478 status |= cx231xx_write_i2c_data(dev,
439 Colibri_DEVICE_ADDRESS, 479 Colibri_DEVICE_ADDRESS,
440 ADC_PWRDN_CLAMP_CH2, 2, 480 ADC_PWRDN_CLAMP_CH2, 2,
441 0x00, 1); 481 0x00, 1);
442 status = cx231xx_write_i2c_data(dev, 482 status |= cx231xx_write_i2c_data(dev,
443 Colibri_DEVICE_ADDRESS, 483 Colibri_DEVICE_ADDRESS,
444 ADC_PWRDN_CLAMP_CH3, 2, 484 ADC_PWRDN_CLAMP_CH3, 2,
445 0x40, 1); 485 0x40, 1);
@@ -500,7 +540,7 @@ int cx231xx_colibri_adjust_ref_count(struct cx231xx *dev, u32 video_input)
500 540
501/****************************************************************************** 541/******************************************************************************
502 * V I D E O / A U D I O D E C O D E R C O N T R O L functions * 542 * V I D E O / A U D I O D E C O D E R C O N T R O L functions *
503 ******************************************++**********************************/ 543 ******************************************************************************/
504int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input) 544int cx231xx_set_video_input_mux(struct cx231xx *dev, u8 input)
505{ 545{
506 int status = 0; 546 int status = 0;
@@ -839,7 +879,7 @@ int cx231xx_set_decoder_video_input(struct cx231xx *dev,
839 DFE_CTRL1, 2, 879 DFE_CTRL1, 2,
840 value, 4); 880 value, 4);
841 881
842 /* Wait 15 ms */ 882 /* Wait until AGC locks up */
843 msleep(1); 883 msleep(1);
844 884
845 /* Disable the auto-VGA enable AGC */ 885 /* Disable the auto-VGA enable AGC */
@@ -940,8 +980,7 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
940 DFE_CTRL3, 2, 980 DFE_CTRL3, 2,
941 0xCD3F0280, 4); 981 0xCD3F0280, 4);
942 982
943 if (dev->norm & (V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | 983 if (dev->norm & (V4L2_STD_NTSC | V4L2_STD_PAL_M)) {
944 V4L2_STD_PAL_M)) {
945 cx231xx_info("do_mode_ctrl_overrides NTSC\n"); 984 cx231xx_info("do_mode_ctrl_overrides NTSC\n");
946 985
947 /* Move the close caption lines out of active video, 986 /* Move the close caption lines out of active video,
@@ -967,11 +1006,9 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
967 FLD_HBLANK_CNT, 1006 FLD_HBLANK_CNT,
968 cx231xx_set_field 1007 cx231xx_set_field
969 (FLD_HBLANK_CNT, 0x79)); 1008 (FLD_HBLANK_CNT, 0x79));
970 } else if (dev->norm & (V4L2_STD_PAL_B | V4L2_STD_PAL_G | 1009 } else if (dev->norm & V4L2_STD_SECAM) {
971 V4L2_STD_PAL_D | V4L2_STD_PAL_I | 1010 cx231xx_info("do_mode_ctrl_overrides SECAM\n");
972 V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { 1011 status = cx231xx_read_modify_write_i2c_dword(dev,
973 cx231xx_info("do_mode_ctrl_overrides PAL\n");
974 status = cx231xx_read_modify_write_i2c_dword(dev,
975 HAMMERHEAD_I2C_ADDRESS, 1012 HAMMERHEAD_I2C_ADDRESS,
976 VERT_TIM_CTRL, 1013 VERT_TIM_CTRL,
977 FLD_VBLANK_CNT, 0x24); 1014 FLD_VBLANK_CNT, 0x24);
@@ -982,12 +1019,9 @@ int cx231xx_do_mode_ctrl_overrides(struct cx231xx *dev)
982 FLD_HBLANK_CNT, 1019 FLD_HBLANK_CNT,
983 cx231xx_set_field 1020 cx231xx_set_field
984 (FLD_HBLANK_CNT, 0x85)); 1021 (FLD_HBLANK_CNT, 0x85));
985 } else if (dev->norm & (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | 1022 } else {
986 V4L2_STD_SECAM_G | V4L2_STD_SECAM_K | 1023 cx231xx_info("do_mode_ctrl_overrides PAL\n");
987 V4L2_STD_SECAM_K1 | V4L2_STD_SECAM_L | 1024 status = cx231xx_read_modify_write_i2c_dword(dev,
988 V4L2_STD_SECAM_LC)) {
989 cx231xx_info("do_mode_ctrl_overrides SECAM\n");
990 status = cx231xx_read_modify_write_i2c_dword(dev,
991 HAMMERHEAD_I2C_ADDRESS, 1025 HAMMERHEAD_I2C_ADDRESS,
992 VERT_TIM_CTRL, 1026 VERT_TIM_CTRL,
993 FLD_VBLANK_CNT, 0x24); 1027 FLD_VBLANK_CNT, 0x24);
@@ -1276,13 +1310,8 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1276 status = cx231xx_reg_mask_write(dev, 1310 status = cx231xx_reg_mask_write(dev,
1277 HAMMERHEAD_I2C_ADDRESS, 32, 1311 HAMMERHEAD_I2C_ADDRESS, 32,
1278 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1312 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1279 } else { 1313 } else if (standard != DIF_USE_BASEBAND) {
1280 switch (standard) { 1314 if (standard & V4L2_STD_MN) {
1281 case V4L2_STD_NTSC_M: /* 75 IRE Setup */
1282 case V4L2_STD_NTSC_M_JP:/* Japan, 0 IRE Setup */
1283 case V4L2_STD_PAL_M:
1284 case V4L2_STD_PAL_N:
1285 case V4L2_STD_PAL_Nc:
1286 /* lo if big signal */ 1315 /* lo if big signal */
1287 status = cx231xx_reg_mask_write(dev, 1316 status = cx231xx_reg_mask_write(dev,
1288 HAMMERHEAD_I2C_ADDRESS, 32, 1317 HAMMERHEAD_I2C_ADDRESS, 32,
@@ -1304,10 +1333,8 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1304 status = cx231xx_reg_mask_write(dev, 1333 status = cx231xx_reg_mask_write(dev,
1305 HAMMERHEAD_I2C_ADDRESS, 32, 1334 HAMMERHEAD_I2C_ADDRESS, 32,
1306 AUD_IO_CTRL, 0, 31, 0x00000003); 1335 AUD_IO_CTRL, 0, 31, 0x00000003);
1307 break; 1336 } else if ((standard == V4L2_STD_PAL_I) |
1308 1337 (standard & V4L2_STD_SECAM)) {
1309 case V4L2_STD_PAL_B:
1310 case V4L2_STD_PAL_G:
1311 /* C2HH setup */ 1338 /* C2HH setup */
1312 /* lo if big signal */ 1339 /* lo if big signal */
1313 status = cx231xx_reg_mask_write(dev, 1340 status = cx231xx_reg_mask_write(dev,
@@ -1321,22 +1348,13 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1321 /* IF_MODE */ 1348 /* IF_MODE */
1322 status = cx231xx_reg_mask_write(dev, 1349 status = cx231xx_reg_mask_write(dev,
1323 HAMMERHEAD_I2C_ADDRESS, 32, 1350 HAMMERHEAD_I2C_ADDRESS, 32,
1324 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE); 1351 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF);
1325 /* no inv */ 1352 /* no inv */
1326 status = cx231xx_reg_mask_write(dev, 1353 status = cx231xx_reg_mask_write(dev,
1327 HAMMERHEAD_I2C_ADDRESS, 32, 1354 HAMMERHEAD_I2C_ADDRESS, 32,
1328 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1355 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1329 break; 1356 } else {
1330 1357 /* default PAL BG */
1331 case V4L2_STD_PAL_D:
1332 case V4L2_STD_PAL_I:
1333 case V4L2_STD_SECAM_L:
1334 case V4L2_STD_SECAM_LC:
1335 case V4L2_STD_SECAM_B:
1336 case V4L2_STD_SECAM_D:
1337 case V4L2_STD_SECAM_G:
1338 case V4L2_STD_SECAM_K:
1339 case V4L2_STD_SECAM_K1:
1340 /* C2HH setup */ 1358 /* C2HH setup */
1341 /* lo if big signal */ 1359 /* lo if big signal */
1342 status = cx231xx_reg_mask_write(dev, 1360 status = cx231xx_reg_mask_write(dev,
@@ -1350,17 +1368,11 @@ int cx231xx_dif_configure_C2HH_for_low_IF(struct cx231xx *dev, u32 mode,
1350 /* IF_MODE */ 1368 /* IF_MODE */
1351 status = cx231xx_reg_mask_write(dev, 1369 status = cx231xx_reg_mask_write(dev,
1352 HAMMERHEAD_I2C_ADDRESS, 32, 1370 HAMMERHEAD_I2C_ADDRESS, 32,
1353 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xF); 1371 AFE_CTRL_C2HH_SRC_CTRL, 15, 22, 0xE);
1354 /* no inv */ 1372 /* no inv */
1355 status = cx231xx_reg_mask_write(dev, 1373 status = cx231xx_reg_mask_write(dev,
1356 HAMMERHEAD_I2C_ADDRESS, 32, 1374 HAMMERHEAD_I2C_ADDRESS, 32,
1357 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1); 1375 AFE_CTRL_C2HH_SRC_CTRL, 9, 9, 0x1);
1358 break;
1359
1360 case DIF_USE_BASEBAND:
1361 default:
1362 /* do nothing to config C2HH for baseband */
1363 break;
1364 } 1376 }
1365 } 1377 }
1366 1378
@@ -1406,54 +1418,6 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1406 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1418 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1407 DIF_MISC_CTRL, 2, 1419 DIF_MISC_CTRL, 2,
1408 dif_misc_ctrl_value, 4); 1420 dif_misc_ctrl_value, 4);
1409
1410 } else if (standard & (V4L2_STD_PAL_B | V4L2_STD_PAL_G)) {
1411
1412 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1413 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1414 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1415 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1416 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1417 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1418 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1419 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1420 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1421 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1422 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1423 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1424 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1425 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1426 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1427 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1428 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1429 DIF_AGC_IF_INT_CURRENT, 0, 31,
1430 0x26001700);
1431 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1432 DIF_AGC_RF_CURRENT, 0, 31,
1433 0x00002660);
1434 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1435 DIF_VIDEO_AGC_CTRL, 0, 31,
1436 0x72500800);
1437 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1438 DIF_VID_AUD_OVERRIDE, 0, 31,
1439 0x27000100);
1440 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1441 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
1442 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1443 DIF_COMP_FLT_CTRL, 0, 31,
1444 0x00A653A8);
1445 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1446 DIF_SRC_PHASE_INC, 0, 31,
1447 0x1befbf06);
1448 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1449 DIF_SRC_GAIN_CONTROL, 0, 31,
1450 0x000035e8);
1451 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1452 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1453 /* Save the Spec Inversion value */
1454 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1455 dif_misc_ctrl_value |= 0x3a013F11;
1456
1457 } else if (standard & V4L2_STD_PAL_D) { 1421 } else if (standard & V4L2_STD_PAL_D) {
1458 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1422 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1459 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1423 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
@@ -1499,9 +1463,7 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1499 /* Save the Spec Inversion value */ 1463 /* Save the Spec Inversion value */
1500 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1464 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1501 dif_misc_ctrl_value |= 0x3a023F11; 1465 dif_misc_ctrl_value |= 0x3a023F11;
1502
1503 } else if (standard & V4L2_STD_PAL_I) { 1466 } else if (standard & V4L2_STD_PAL_I) {
1504
1505 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1467 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1506 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1468 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1507 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1469 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
@@ -1546,7 +1508,6 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1546 /* Save the Spec Inversion value */ 1508 /* Save the Spec Inversion value */
1547 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1509 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1548 dif_misc_ctrl_value |= 0x3a033F11; 1510 dif_misc_ctrl_value |= 0x3a033F11;
1549
1550 } else if (standard & V4L2_STD_PAL_M) { 1511 } else if (standard & V4L2_STD_PAL_M) {
1551 /* improved Low Frequency Phase Noise */ 1512 /* improved Low Frequency Phase Noise */
1552 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1513 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
@@ -1584,13 +1545,10 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1584 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1545 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1585 DIF_SOFT_RST_CTRL_REVB, 2, 1546 DIF_SOFT_RST_CTRL_REVB, 2,
1586 0x00000000, 4); 1547 0x00000000, 4);
1587
1588 /* Save the Spec Inversion value */ 1548 /* Save the Spec Inversion value */
1589 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1549 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1590 dif_misc_ctrl_value |= 0x3A0A3F10; 1550 dif_misc_ctrl_value |= 0x3A0A3F10;
1591
1592 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) { 1551 } else if (standard & (V4L2_STD_PAL_N | V4L2_STD_PAL_Nc)) {
1593
1594 /* improved Low Frequency Phase Noise */ 1552 /* improved Low Frequency Phase Noise */
1595 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1553 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1596 DIF_PLL_CTRL, 2, 0xFF01FF0C, 4); 1554 DIF_PLL_CTRL, 2, 0xFF01FF0C, 4);
@@ -1626,14 +1584,12 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1626 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1584 status = cx231xx_write_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1627 DIF_SOFT_RST_CTRL_REVB, 2, 1585 DIF_SOFT_RST_CTRL_REVB, 2,
1628 0x00000000, 4); 1586 0x00000000, 4);
1629
1630 /* Save the Spec Inversion value */ 1587 /* Save the Spec Inversion value */
1631 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1588 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1632 dif_misc_ctrl_value = 0x3A093F10; 1589 dif_misc_ctrl_value = 0x3A093F10;
1633
1634 } else if (standard & 1590 } else if (standard &
1635 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G | 1591 (V4L2_STD_SECAM_B | V4L2_STD_SECAM_D | V4L2_STD_SECAM_G |
1636 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) { 1592 V4L2_STD_SECAM_K | V4L2_STD_SECAM_K1)) {
1637 1593
1638 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1594 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1639 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1595 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
@@ -1680,9 +1636,7 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1680 /* Save the Spec Inversion value */ 1636 /* Save the Spec Inversion value */
1681 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1637 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1682 dif_misc_ctrl_value |= 0x3a023F11; 1638 dif_misc_ctrl_value |= 0x3a023F11;
1683
1684 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) { 1639 } else if (standard & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC)) {
1685
1686 /* Is it SECAM_L1? */ 1640 /* Is it SECAM_L1? */
1687 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32, 1641 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1688 DIF_PLL_CTRL, 0, 31, 0x6503bc0c); 1642 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
@@ -1730,7 +1684,7 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1730 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1684 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1731 dif_misc_ctrl_value |= 0x3a023F11; 1685 dif_misc_ctrl_value |= 0x3a023F11;
1732 1686
1733 } else { 1687 } else if (standard & V4L2_STD_NTSC_M) {
1734 /* V4L2_STD_NTSC_M (75 IRE Setup) Or 1688 /* V4L2_STD_NTSC_M (75 IRE Setup) Or
1735 V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */ 1689 V4L2_STD_NTSC_M_JP (Japan, 0 IRE Setup) */
1736 1690
@@ -1783,7 +1737,52 @@ int cx231xx_dif_set_standard(struct cx231xx *dev, u32 standard)
1783 /* Save the Spec Inversion value */ 1737 /* Save the Spec Inversion value */
1784 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV; 1738 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1785 dif_misc_ctrl_value |= 0x3a003F10; 1739 dif_misc_ctrl_value |= 0x3a003F10;
1786 1740 } else {
1741 /* default PAL BG */
1742 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1743 DIF_PLL_CTRL, 0, 31, 0x6503bc0c);
1744 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1745 DIF_PLL_CTRL1, 0, 31, 0xbd038c85);
1746 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1747 DIF_PLL_CTRL2, 0, 31, 0x1db4640a);
1748 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1749 DIF_PLL_CTRL3, 0, 31, 0x00008800);
1750 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1751 DIF_AGC_IF_REF, 0, 31, 0x444C1380);
1752 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1753 DIF_AGC_CTRL_IF, 0, 31, 0xDA302600);
1754 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1755 DIF_AGC_CTRL_INT, 0, 31, 0xDA261700);
1756 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1757 DIF_AGC_CTRL_RF, 0, 31, 0xDA262600);
1758 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1759 DIF_AGC_IF_INT_CURRENT, 0, 31,
1760 0x26001700);
1761 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1762 DIF_AGC_RF_CURRENT, 0, 31,
1763 0x00002660);
1764 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1765 DIF_VIDEO_AGC_CTRL, 0, 31,
1766 0x72500800);
1767 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1768 DIF_VID_AUD_OVERRIDE, 0, 31,
1769 0x27000100);
1770 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1771 DIF_AV_SEP_CTRL, 0, 31, 0x3F3530EC);
1772 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1773 DIF_COMP_FLT_CTRL, 0, 31,
1774 0x00A653A8);
1775 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1776 DIF_SRC_PHASE_INC, 0, 31,
1777 0x1befbf06);
1778 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1779 DIF_SRC_GAIN_CONTROL, 0, 31,
1780 0x000035e8);
1781 status = cx231xx_reg_mask_write(dev, HAMMERHEAD_I2C_ADDRESS, 32,
1782 DIF_RPT_VARIANCE, 0, 31, 0x00000000);
1783 /* Save the Spec Inversion value */
1784 dif_misc_ctrl_value &= FLD_DIF_SPEC_INV;
1785 dif_misc_ctrl_value |= 0x3a013F11;
1787 } 1786 }
1788 1787
1789 /* The AGC values should be the same for all standards, 1788 /* The AGC values should be the same for all standards,
@@ -1826,7 +1825,8 @@ int cx231xx_tuner_post_channel_change(struct cx231xx *dev)
1826 int status = 0; 1825 int status = 0;
1827 u32 dwval; 1826 u32 dwval;
1828 1827
1829 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for SECAM */ 1828 /* Set the RF and IF k_agc values to 4 for PAL/NTSC and 8 for
1829 * SECAM L/B/D standards */
1830 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS, 1830 status = cx231xx_read_i2c_data(dev, HAMMERHEAD_I2C_ADDRESS,
1831 DIF_AGC_IF_REF, 2, &dwval, 4); 1831 DIF_AGC_IF_REF, 2, &dwval, 4);
1832 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF); 1832 dwval &= ~(FLD_DIF_K_AGC_RF | FLD_DIF_K_AGC_IF);
@@ -1864,7 +1864,8 @@ int cx231xx_flatiron_initialize(struct cx231xx *dev)
1864 return status; 1864 return status;
1865} 1865}
1866 1866
1867int cx231xx_flatiron_update_power_control(struct cx231xx *dev, AV_MODE avmode) 1867int cx231xx_flatiron_update_power_control(struct cx231xx *dev,
1868 enum AV_MODE avmode)
1868{ 1869{
1869 int status = 0; 1870 int status = 0;
1870 u32 value = 0; 1871 u32 value = 0;
@@ -1908,7 +1909,7 @@ int cx231xx_flatiron_set_audio_input(struct cx231xx *dev, u8 audio_input)
1908/****************************************************************************** 1909/******************************************************************************
1909 * P O W E R C O N T R O L functions * 1910 * P O W E R C O N T R O L functions *
1910 ******************************************************************************/ 1911 ******************************************************************************/
1911int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode) 1912int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode)
1912{ 1913{
1913 u8 value[4] = { 0, 0, 0, 0 }; 1914 u8 value[4] = { 0, 0, 0, 0 };
1914 u32 tmp = 0; 1915 u32 tmp = 0;
@@ -2211,7 +2212,7 @@ int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type)
2211 2212
2212 if (dev->udev->speed == USB_SPEED_HIGH) { 2213 if (dev->udev->speed == USB_SPEED_HIGH) {
2213 switch (media_type) { 2214 switch (media_type) {
2214 case 81: /* audio */ 2215 case 81: /* audio */
2215 cx231xx_info("%s: Audio enter HANC\n", __func__); 2216 cx231xx_info("%s: Audio enter HANC\n", __func__);
2216 status = 2217 status =
2217 cx231xx_mode_register(dev, TS_MODE_REG, 0x9300); 2218 cx231xx_mode_register(dev, TS_MODE_REG, 0x9300);
@@ -2390,7 +2391,7 @@ int cx231xx_set_gpio_direction(struct cx231xx *dev,
2390} 2391}
2391 2392
2392/* 2393/*
2393* SetGpioPinLogicValue 2394* cx231xx_set_gpio_value
2394* Sets the value of the GPIO pin to Logic high or low. The Pin under 2395* Sets the value of the GPIO pin to Logic high or low. The Pin under
2395* reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!! 2396* reference should ALREADY BE SET IN OUTPUT MODE !!!!!!!!!
2396* 2397*
diff --git a/drivers/media/video/cx231xx/cx231xx-cards.c b/drivers/media/video/cx231xx/cx231xx-cards.c
index f18d0c11de7d..c12bb62021a9 100644
--- a/drivers/media/video/cx231xx/cx231xx-cards.c
+++ b/drivers/media/video/cx231xx/cx231xx-cards.c
@@ -61,127 +61,108 @@ static struct cx231xx_reg_seq RDE250_XCV_TUNER[] = {
61 * Board definitions 61 * Board definitions
62 */ 62 */
63struct cx231xx_board cx231xx_boards[] = { 63struct cx231xx_board cx231xx_boards[] = {
64
65 [CX231XX_BOARD_UNKNOWN] = { 64 [CX231XX_BOARD_UNKNOWN] = {
66 .name = "Unknown CX231xx video grabber", 65 .name = "Unknown CX231xx video grabber",
67 .tuner_type = TUNER_ABSENT, 66 .tuner_type = TUNER_ABSENT,
68 .input = {{ 67 .input = {{
69 .type = CX231XX_VMUX_TELEVISION, 68 .type = CX231XX_VMUX_TELEVISION,
70 .vmux = CX231XX_VIN_3_1, 69 .vmux = CX231XX_VIN_3_1,
71 .amux = CX231XX_AMUX_VIDEO, 70 .amux = CX231XX_AMUX_VIDEO,
72 .gpio = 0, 71 .gpio = 0,
73 }, { 72 }, {
74 .type = 73 .type = CX231XX_VMUX_COMPOSITE1,
75 CX231XX_VMUX_COMPOSITE1, 74 .vmux = CX231XX_VIN_2_1,
76 .vmux = CX231XX_VIN_2_1, 75 .amux = CX231XX_AMUX_LINE_IN,
77 .amux = CX231XX_AMUX_LINE_IN, 76 .gpio = 0,
78 .gpio = 0, 77 }, {
79 }, { 78 .type = CX231XX_VMUX_SVIDEO,
80 .type = 79 .vmux = CX231XX_VIN_1_1 |
81 CX231XX_VMUX_SVIDEO, 80 (CX231XX_VIN_1_2 << 8) |
82 .vmux = 81 CX25840_SVIDEO_ON,
83 CX231XX_VIN_1_1 | 82 .amux = CX231XX_AMUX_LINE_IN,
84 (CX231XX_VIN_1_2 << 8) | 83 .gpio = 0,
85 CX25840_SVIDEO_ON, 84 }
86 .amux = 85 },
87 CX231XX_AMUX_LINE_IN, 86 },
88 .gpio = 0,
89 } },
90 },
91
92 [CX231XX_BOARD_CNXT_RDE_250] = { 87 [CX231XX_BOARD_CNXT_RDE_250] = {
93 .name = "Conexant Hybrid TV - RDE250", 88 .name = "Conexant Hybrid TV - RDE250",
94 .valid = CX231XX_BOARD_VALIDATED, 89 .tuner_type = TUNER_XC5000,
95 .tuner_type = TUNER_XC5000, 90 .tuner_addr = 0x61,
96 .tuner_addr = 0x61, 91 .tuner_gpio = RDE250_XCV_TUNER,
97 .tuner_gpio = RDE250_XCV_TUNER, 92 .tuner_sif_gpio = 0x05,
98 .tuner_sif_gpio = 0x05, 93 .tuner_scl_gpio = 0x1a,
99 .tuner_scl_gpio = 0x1a, 94 .tuner_sda_gpio = 0x1b,
100 .tuner_sda_gpio = 0x1b, 95 .decoder = CX231XX_AVDECODER,
101 .decoder = CX231XX_AVDECODER, 96 .demod_xfer_mode = 0,
102 .demod_xfer_mode = 0, 97 .ctl_pin_status_mask = 0xFFFFFFC4,
103 .ctl_pin_status_mask = 0xFFFFFFC4, 98 .agc_analog_digital_select_gpio = 0x0c,
104 .agc_analog_digital_select_gpio = 0x0c, 99 .gpio_pin_status_mask = 0x4001000,
105 .gpio_pin_status_mask = 0x4001000, 100 .tuner_i2c_master = 1,
106 .tuner_i2c_master = 1, 101 .demod_i2c_master = 2,
107 .demod_i2c_master = 2, 102 .has_dvb = 1,
108 .has_dvb = 1, 103 .demod_addr = 0x02,
109 .demod_addr = 0x02, 104 .norm = V4L2_STD_PAL,
110 .norm = V4L2_STD_PAL, 105
111 106 .input = {{
112 .input = {{ 107 .type = CX231XX_VMUX_TELEVISION,
113 .type = 108 .vmux = CX231XX_VIN_3_1,
114 CX231XX_VMUX_TELEVISION, 109 .amux = CX231XX_AMUX_VIDEO,
115 .vmux = CX231XX_VIN_3_1, 110 .gpio = 0,
116 .amux = CX231XX_AMUX_VIDEO, 111 }, {
117 .gpio = 0, 112 .type = CX231XX_VMUX_COMPOSITE1,
118 }, { 113 .vmux = CX231XX_VIN_2_1,
119 .type = 114 .amux = CX231XX_AMUX_LINE_IN,
120 CX231XX_VMUX_COMPOSITE1, 115 .gpio = 0,
121 .vmux = CX231XX_VIN_2_1, 116 }, {
122 .amux = 117 .type = CX231XX_VMUX_SVIDEO,
123 CX231XX_AMUX_LINE_IN, 118 .vmux = CX231XX_VIN_1_1 |
124 .gpio = 0, 119 (CX231XX_VIN_1_2 << 8) |
125 }, { 120 CX25840_SVIDEO_ON,
126 .type = 121 .amux = CX231XX_AMUX_LINE_IN,
127 CX231XX_VMUX_SVIDEO, 122 .gpio = 0,
128 .vmux = 123 }
129 CX231XX_VIN_1_1 | 124 },
130 (CX231XX_VIN_1_2 << 125 },
131 8) |
132 CX25840_SVIDEO_ON,
133 .amux =
134 CX231XX_AMUX_LINE_IN,
135 .gpio = 0,
136 } },
137 },
138 126
139 [CX231XX_BOARD_CNXT_RDU_250] = { 127 [CX231XX_BOARD_CNXT_RDU_250] = {
140 .name = "Conexant Hybrid TV - RDU250", 128 .name = "Conexant Hybrid TV - RDU250",
141 .valid = CX231XX_BOARD_VALIDATED, 129 .tuner_type = TUNER_XC5000,
142 .tuner_type = TUNER_XC5000, 130 .tuner_addr = 0x61,
143 .tuner_addr = 0x61, 131 .tuner_gpio = RDE250_XCV_TUNER,
144 .tuner_gpio = RDE250_XCV_TUNER, 132 .tuner_sif_gpio = 0x05,
145 .tuner_sif_gpio = 0x05, 133 .tuner_scl_gpio = 0x1a,
146 .tuner_scl_gpio = 0x1a, 134 .tuner_sda_gpio = 0x1b,
147 .tuner_sda_gpio = 0x1b, 135 .decoder = CX231XX_AVDECODER,
148 .decoder = CX231XX_AVDECODER, 136 .demod_xfer_mode = 0,
149 .demod_xfer_mode = 0, 137 .ctl_pin_status_mask = 0xFFFFFFC4,
150 .ctl_pin_status_mask = 0xFFFFFFC4, 138 .agc_analog_digital_select_gpio = 0x0c,
151 .agc_analog_digital_select_gpio = 0x0c, 139 .gpio_pin_status_mask = 0x4001000,
152 .gpio_pin_status_mask = 0x4001000, 140 .tuner_i2c_master = 1,
153 .tuner_i2c_master = 1, 141 .demod_i2c_master = 2,
154 .demod_i2c_master = 2, 142 .has_dvb = 1,
155 .has_dvb = 1, 143 .demod_addr = 0x32,
156 .demod_addr = 0x32, 144 .norm = V4L2_STD_NTSC,
157 .norm = V4L2_STD_NTSC, 145
158 146 .input = {{
159 .input = {{ 147 .type = CX231XX_VMUX_TELEVISION,
160 .type = 148 .vmux = CX231XX_VIN_3_1,
161 CX231XX_VMUX_TELEVISION, 149 .amux = CX231XX_AMUX_VIDEO,
162 .vmux = CX231XX_VIN_3_1, 150 .gpio = 0,
163 .amux = CX231XX_AMUX_VIDEO, 151 }, {
164 .gpio = 0, 152 .type = CX231XX_VMUX_COMPOSITE1,
165 }, { 153 .vmux = CX231XX_VIN_2_1,
166 .type = 154 .amux = CX231XX_AMUX_LINE_IN,
167 CX231XX_VMUX_COMPOSITE1, 155 .gpio = 0,
168 .vmux = CX231XX_VIN_2_1, 156 }, {
169 .amux = 157 .type = CX231XX_VMUX_SVIDEO,
170 CX231XX_AMUX_LINE_IN, 158 .vmux = CX231XX_VIN_1_1 |
171 .gpio = 0, 159 (CX231XX_VIN_1_2 << 8) |
172 }, { 160 CX25840_SVIDEO_ON,
173 .type = 161 .amux = CX231XX_AMUX_LINE_IN,
174 CX231XX_VMUX_SVIDEO, 162 .gpio = 0,
175 .vmux = 163 }
176 CX231XX_VIN_1_1 | 164 },
177 (CX231XX_VIN_1_2 << 165 },
178 8) |
179 CX25840_SVIDEO_ON,
180 .amux =
181 CX231XX_AMUX_LINE_IN,
182 .gpio = 0,
183 } },
184 },
185}; 166};
186const unsigned int cx231xx_bcount = ARRAY_SIZE(cx231xx_boards); 167const unsigned int cx231xx_bcount = ARRAY_SIZE(cx231xx_boards);
187 168
@@ -243,25 +224,11 @@ void cx231xx_pre_card_setup(struct cx231xx *dev)
243 cx231xx_info("Identified as %s (card=%d)\n", 224 cx231xx_info("Identified as %s (card=%d)\n",
244 dev->board.name, dev->model); 225 dev->board.name, dev->model);
245 226
246 /* Do card specific if any */ 227 cx231xx_info("Precard: Board is %s\n", dev->board.name);
247 switch (dev->model) { 228 /* set the direction for GPIO pins */
248 case CX231XX_BOARD_CNXT_RDE_250: 229 cx231xx_set_gpio_direction(dev, dev->board.tuner_gpio->bit, 1);
249 /* do card specific GPIO settings if required */ 230 cx231xx_set_gpio_value(dev, dev->board.tuner_gpio->bit, 1);
250 cx231xx_info("Precard: Board is Conexnat RDE 250\n"); 231 cx231xx_set_gpio_direction(dev, dev->board.tuner_sif_gpio, 1);
251 /* set the direction for GPIO pins */
252 cx231xx_set_gpio_direction(dev, dev->board.tuner_gpio->bit, 1);
253 cx231xx_set_gpio_value(dev, dev->board.tuner_gpio->bit, 1);
254 cx231xx_set_gpio_direction(dev, dev->board.tuner_sif_gpio, 1);
255 break;
256 case CX231XX_BOARD_CNXT_RDU_250:
257 /* do card specific GPIO settings if required */
258 cx231xx_info("Precard: Board is Conexnat RDU 250\n");
259 /* set the direction for GPIO pins */
260 cx231xx_set_gpio_direction(dev, dev->board.tuner_gpio->bit, 1);
261 cx231xx_set_gpio_value(dev, dev->board.tuner_gpio->bit, 1);
262 cx231xx_set_gpio_direction(dev, dev->board.tuner_sif_gpio, 1);
263 break;
264 }
265 232
266 /* request some modules if any required */ 233 /* request some modules if any required */
267 234
@@ -362,15 +329,6 @@ void cx231xx_card_setup(struct cx231xx *dev)
362 break; 329 break;
363 } 330 }
364 331
365 if (dev->board.valid == CX231XX_BOARD_NOT_VALIDATED) {
366 cx231xx_errdev("\n\n");
367 cx231xx_errdev("The support for this board weren't "
368 "valid yet.\n");
369 cx231xx_errdev("Please send a report of having this working\n");
370 cx231xx_errdev("not to V4L mailing list (and/or to other "
371 "addresses)\n\n");
372 }
373
374 /* request some modules */ 332 /* request some modules */
375 if (dev->board.decoder == CX231XX_AVDECODER) { 333 if (dev->board.decoder == CX231XX_AVDECODER) {
376 cx231xx_info(": Requesting cx25840 module\n"); 334 cx231xx_info(": Requesting cx25840 module\n");
diff --git a/drivers/media/video/cx231xx/cx231xx-conf-reg.h b/drivers/media/video/cx231xx/cx231xx-conf-reg.h
index a65f99ba109b..a6f398a175c5 100644
--- a/drivers/media/video/cx231xx/cx231xx-conf-reg.h
+++ b/drivers/media/video/cx231xx/cx231xx-conf-reg.h
@@ -42,30 +42,30 @@
42#define PWR_CTL_EN 0x74 42#define PWR_CTL_EN 0x74
43 43
44/* Polaris Endpoints capture mask for register EP_MODE_SET */ 44/* Polaris Endpoints capture mask for register EP_MODE_SET */
45#define ENABLE_EP1 0x01 /* Bit[0]=1 */ 45#define ENABLE_EP1 0x01 /* Bit[0]=1 */
46#define ENABLE_EP2 0x02 /* Bit[1]=1 */ 46#define ENABLE_EP2 0x02 /* Bit[1]=1 */
47#define ENABLE_EP3 0x04 /* Bit[2]=1 */ 47#define ENABLE_EP3 0x04 /* Bit[2]=1 */
48#define ENABLE_EP4 0x08 /* Bit[3]=1 */ 48#define ENABLE_EP4 0x08 /* Bit[3]=1 */
49#define ENABLE_EP5 0x10 /* Bit[4]=1 */ 49#define ENABLE_EP5 0x10 /* Bit[4]=1 */
50#define ENABLE_EP6 0x20 /* Bit[5]=1 */ 50#define ENABLE_EP6 0x20 /* Bit[5]=1 */
51 51
52/* Bit definition for register PWR_CTL_EN */ 52/* Bit definition for register PWR_CTL_EN */
53#define PWR_MODE_MASK 0x17f 53#define PWR_MODE_MASK 0x17f
54#define PWR_AV_EN 0x08 /* bit3 */ 54#define PWR_AV_EN 0x08 /* bit3 */
55#define PWR_ISO_EN 0x40 /* bit6 */ 55#define PWR_ISO_EN 0x40 /* bit6 */
56#define PWR_AV_MODE 0x30 /* bit4,5 */ 56#define PWR_AV_MODE 0x30 /* bit4,5 */
57#define PWR_TUNER_EN 0x04 /* bit2 */ 57#define PWR_TUNER_EN 0x04 /* bit2 */
58#define PWR_DEMOD_EN 0x02 /* bit1 */ 58#define PWR_DEMOD_EN 0x02 /* bit1 */
59#define I2C_DEMOD_EN 0x01 /* bit0 */ 59#define I2C_DEMOD_EN 0x01 /* bit0 */
60#define PWR_RESETOUT_EN 0x100 /* bit8 */ 60#define PWR_RESETOUT_EN 0x100 /* bit8 */
61 61
62typedef enum { 62enum AV_MODE{
63 POLARIS_AVMODE_DEFAULT = 0, 63 POLARIS_AVMODE_DEFAULT = 0,
64 POLARIS_AVMODE_DIGITAL = 0x10, 64 POLARIS_AVMODE_DIGITAL = 0x10,
65 POLARIS_AVMODE_ANALOGT_TV = 0x20, 65 POLARIS_AVMODE_ANALOGT_TV = 0x20,
66 POLARIS_AVMODE_ENXTERNAL_AV = 0x30, 66 POLARIS_AVMODE_ENXTERNAL_AV = 0x30,
67 67
68} AV_MODE; 68};
69 69
70/* Colibri Registers */ 70/* Colibri Registers */
71 71
@@ -91,6 +91,13 @@ typedef enum {
91#define ADC_COM_BIAS3 0x0e 91#define ADC_COM_BIAS3 0x0e
92#define TESTBUS_CTRL 0x12 92#define TESTBUS_CTRL 0x12
93 93
94#define FLD_PWRDN_TUNING_BIAS 0x10
95#define FLD_PWRDN_ENABLE_PLL 0x08
96#define FLD_PWRDN_PD_BANDGAP 0x04
97#define FLD_PWRDN_PD_BIAS 0x02
98#define FLD_PWRDN_PD_TUNECK 0x01
99
100
94#define ADC_STATUS_CH1 0x20 101#define ADC_STATUS_CH1 0x20
95#define ADC_STATUS_CH2 0x40 102#define ADC_STATUS_CH2 0x40
96#define ADC_STATUS_CH3 0x60 103#define ADC_STATUS_CH3 0x60
@@ -126,7 +133,7 @@ typedef enum {
126#define ADC_INPUT_CH1 0x28 133#define ADC_INPUT_CH1 0x28
127#define ADC_INPUT_CH2 0x48 134#define ADC_INPUT_CH2 0x48
128#define ADC_INPUT_CH3 0x68 135#define ADC_INPUT_CH3 0x68
129#define INPUT_SEL_MASK 0x30 /* [5:4] in_sel */ 136#define INPUT_SEL_MASK 0x30 /* [5:4] in_sel */
130 137
131#define ADC_NTF_PRECLMP_EN_CH1 0x29 138#define ADC_NTF_PRECLMP_EN_CH1 0x29
132#define ADC_NTF_PRECLMP_EN_CH2 0x49 139#define ADC_NTF_PRECLMP_EN_CH2 0x49
@@ -150,128 +157,128 @@ typedef enum {
150#define DIRECT_IF_REVB_BASE 0x00300 157#define DIRECT_IF_REVB_BASE 0x00300
151 158
152/*****************************************************************************/ 159/*****************************************************************************/
153#define DIF_PLL_FREQ_WORD (DIRECT_IF_REVB_BASE + 0x00000000) /* Reg Size 32 */ 160#define DIF_PLL_FREQ_WORD (DIRECT_IF_REVB_BASE + 0x00000000)
154/*****************************************************************************/ 161/*****************************************************************************/
155#define FLD_DIF_PLL_LOCK 0x80000000 162#define FLD_DIF_PLL_LOCK 0x80000000
156/* Reserved [30:29] */ 163/* Reserved [30:29] */
157#define FLD_DIF_PLL_FREE_RUN 0x10000000 164#define FLD_DIF_PLL_FREE_RUN 0x10000000
158#define FLD_DIF_PLL_FREQ 0x0FFFFFFF 165#define FLD_DIF_PLL_FREQ 0x0fffffff
159 166
160/*****************************************************************************/ 167/*****************************************************************************/
161#define DIF_PLL_CTRL (DIRECT_IF_REVB_BASE + 0x00000004) /* Reg Size 32 */ 168#define DIF_PLL_CTRL (DIRECT_IF_REVB_BASE + 0x00000004)
162/*****************************************************************************/ 169/*****************************************************************************/
163#define FLD_DIF_KD_PD 0xFF000000 170#define FLD_DIF_KD_PD 0xff000000
164/* Reserved [23:20] */ 171/* Reserved [23:20] */
165#define FLD_DIF_KDS_PD 0x000F0000 172#define FLD_DIF_KDS_PD 0x000f0000
166#define FLD_DIF_KI_PD 0x0000FF00 173#define FLD_DIF_KI_PD 0x0000ff00
167/* Reserved [7:4] */ 174/* Reserved [7:4] */
168#define FLD_DIF_KIS_PD 0x0000000F 175#define FLD_DIF_KIS_PD 0x0000000f
169 176
170/*****************************************************************************/ 177/*****************************************************************************/
171#define DIF_PLL_CTRL1 (DIRECT_IF_REVB_BASE + 0x00000008) /* Reg Size 32 */ 178#define DIF_PLL_CTRL1 (DIRECT_IF_REVB_BASE + 0x00000008)
172/*****************************************************************************/ 179/*****************************************************************************/
173#define FLD_DIF_KD_FD 0xFF000000 180#define FLD_DIF_KD_FD 0xff000000
174/* Reserved [23:20] */ 181/* Reserved [23:20] */
175#define FLD_DIF_KDS_FD 0x000F0000 182#define FLD_DIF_KDS_FD 0x000f0000
176#define FLD_DIF_KI_FD 0x0000FF00 183#define FLD_DIF_KI_FD 0x0000ff00
177#define FLD_DIF_SIG_PROP_SZ 0x000000F0 184#define FLD_DIF_SIG_PROP_SZ 0x000000f0
178#define FLD_DIF_KIS_FD 0x0000000F 185#define FLD_DIF_KIS_FD 0x0000000f
179 186
180/*****************************************************************************/ 187/*****************************************************************************/
181#define DIF_PLL_CTRL2 (DIRECT_IF_REVB_BASE + 0x0000000C) /* Reg Size 32 */ 188#define DIF_PLL_CTRL2 (DIRECT_IF_REVB_BASE + 0x0000000c)
182/*****************************************************************************/ 189/*****************************************************************************/
183#define FLD_DIF_PLL_AGC_REF 0xFFF00000 190#define FLD_DIF_PLL_AGC_REF 0xfff00000
184#define FLD_DIF_PLL_AGC_KI 0x000F0000 191#define FLD_DIF_PLL_AGC_KI 0x000f0000
185/* Reserved [15] */ 192/* Reserved [15] */
186#define FLD_DIF_FREQ_LIMIT 0x00007000 193#define FLD_DIF_FREQ_LIMIT 0x00007000
187#define FLD_DIF_K_FD 0x00000F00 194#define FLD_DIF_K_FD 0x00000f00
188#define FLD_DIF_DOWNSMPL_FD 0x000000FF 195#define FLD_DIF_DOWNSMPL_FD 0x000000ff
189 196
190/*****************************************************************************/ 197/*****************************************************************************/
191#define DIF_PLL_CTRL3 (DIRECT_IF_REVB_BASE + 0x00000010) /* Reg Size 32 */ 198#define DIF_PLL_CTRL3 (DIRECT_IF_REVB_BASE + 0x00000010)
192/*****************************************************************************/ 199/*****************************************************************************/
193/* Reserved [31:16] */ 200/* Reserved [31:16] */
194#define FLD_DIF_PLL_AGC_EN 0x00008000 201#define FLD_DIF_PLL_AGC_EN 0x00008000
195/* Reserved [14:12] */ 202/* Reserved [14:12] */
196#define FLD_DIF_PLL_MAN_GAIN 0x00000FFF 203#define FLD_DIF_PLL_MAN_GAIN 0x00000fff
197 204
198/*****************************************************************************/ 205/*****************************************************************************/
199#define DIF_AGC_IF_REF (DIRECT_IF_REVB_BASE + 0x00000014) /* Reg Size 32 */ 206#define DIF_AGC_IF_REF (DIRECT_IF_REVB_BASE + 0x00000014)
200/*****************************************************************************/ 207/*****************************************************************************/
201#define FLD_DIF_K_AGC_RF 0xF0000000 208#define FLD_DIF_K_AGC_RF 0xf0000000
202#define FLD_DIF_K_AGC_IF 0x0F000000 209#define FLD_DIF_K_AGC_IF 0x0f000000
203#define FLD_DIF_K_AGC_INT 0x00F00000 210#define FLD_DIF_K_AGC_INT 0x00f00000
204/* Reserved [19:12] */ 211/* Reserved [19:12] */
205#define FLD_DIF_IF_REF 0x00000FFF 212#define FLD_DIF_IF_REF 0x00000fff
206 213
207/*****************************************************************************/ 214/*****************************************************************************/
208#define DIF_AGC_CTRL_IF (DIRECT_IF_REVB_BASE + 0x00000018) /* Reg Size 32 */ 215#define DIF_AGC_CTRL_IF (DIRECT_IF_REVB_BASE + 0x00000018)
209/*****************************************************************************/ 216/*****************************************************************************/
210#define FLD_DIF_IF_MAX 0xFF000000 217#define FLD_DIF_IF_MAX 0xff000000
211#define FLD_DIF_IF_MIN 0x00FF0000 218#define FLD_DIF_IF_MIN 0x00ff0000
212#define FLD_DIF_IF_AGC 0x0000FFFF 219#define FLD_DIF_IF_AGC 0x0000ffff
213 220
214/*****************************************************************************/ 221/*****************************************************************************/
215#define DIF_AGC_CTRL_INT (DIRECT_IF_REVB_BASE + 0x0000001C) /* Reg Size 32 */ 222#define DIF_AGC_CTRL_INT (DIRECT_IF_REVB_BASE + 0x0000001c)
216/*****************************************************************************/ 223/*****************************************************************************/
217#define FLD_DIF_INT_MAX 0xFF000000 224#define FLD_DIF_INT_MAX 0xff000000
218#define FLD_DIF_INT_MIN 0x00FF0000 225#define FLD_DIF_INT_MIN 0x00ff0000
219#define FLD_DIF_INT_AGC 0x0000FFFF 226#define FLD_DIF_INT_AGC 0x0000ffff
220 227
221/*****************************************************************************/ 228/*****************************************************************************/
222#define DIF_AGC_CTRL_RF (DIRECT_IF_REVB_BASE + 0x00000020) /* Reg Size 32 */ 229#define DIF_AGC_CTRL_RF (DIRECT_IF_REVB_BASE + 0x00000020)
223/*****************************************************************************/ 230/*****************************************************************************/
224#define FLD_DIF_RF_MAX 0xFF000000 231#define FLD_DIF_RF_MAX 0xff000000
225#define FLD_DIF_RF_MIN 0x00FF0000 232#define FLD_DIF_RF_MIN 0x00ff0000
226#define FLD_DIF_RF_AGC 0x0000FFFF 233#define FLD_DIF_RF_AGC 0x0000ffff
227 234
228/*****************************************************************************/ 235/*****************************************************************************/
229#define DIF_AGC_IF_INT_CURRENT (DIRECT_IF_REVB_BASE + 0x00000024) /* Reg Size 32 */ 236#define DIF_AGC_IF_INT_CURRENT (DIRECT_IF_REVB_BASE + 0x00000024)
230/*****************************************************************************/ 237/*****************************************************************************/
231#define FLD_DIF_IF_AGC_IN 0xFFFF0000 238#define FLD_DIF_IF_AGC_IN 0xffff0000
232#define FLD_DIF_INT_AGC_IN 0x0000FFFF 239#define FLD_DIF_INT_AGC_IN 0x0000ffff
233 240
234/*****************************************************************************/ 241/*****************************************************************************/
235#define DIF_AGC_RF_CURRENT (DIRECT_IF_REVB_BASE + 0x00000028) /* Reg Size 32 */ 242#define DIF_AGC_RF_CURRENT (DIRECT_IF_REVB_BASE + 0x00000028)
236/*****************************************************************************/ 243/*****************************************************************************/
237/* Reserved [31:16] */ 244/* Reserved [31:16] */
238#define FLD_DIF_RF_AGC_IN 0x0000FFFF 245#define FLD_DIF_RF_AGC_IN 0x0000ffff
239 246
240/*****************************************************************************/ 247/*****************************************************************************/
241#define DIF_VIDEO_AGC_CTRL (DIRECT_IF_REVB_BASE + 0x0000002C) /* Reg Size 32 */ 248#define DIF_VIDEO_AGC_CTRL (DIRECT_IF_REVB_BASE + 0x0000002c)
242/*****************************************************************************/ 249/*****************************************************************************/
243#define FLD_DIF_AFD 0xC0000000 250#define FLD_DIF_AFD 0xc0000000
244#define FLD_DIF_K_VID_AGC 0x30000000 251#define FLD_DIF_K_VID_AGC 0x30000000
245#define FLD_DIF_LINE_LENGTH 0x0FFF0000 252#define FLD_DIF_LINE_LENGTH 0x0fff0000
246#define FLD_DIF_AGC_GAIN 0x0000FFFF 253#define FLD_DIF_AGC_GAIN 0x0000ffff
247 254
248/*****************************************************************************/ 255/*****************************************************************************/
249#define DIF_VID_AUD_OVERRIDE (DIRECT_IF_REVB_BASE + 0x00000030) /* Reg Size 32 */ 256#define DIF_VID_AUD_OVERRIDE (DIRECT_IF_REVB_BASE + 0x00000030)
250/*****************************************************************************/ 257/*****************************************************************************/
251#define FLD_DIF_AUDIO_AGC_OVERRIDE 0x80000000 258#define FLD_DIF_AUDIO_AGC_OVERRIDE 0x80000000
252/* Reserved [30:30] */ 259/* Reserved [30:30] */
253#define FLD_DIF_AUDIO_MAN_GAIN 0x3F000000 260#define FLD_DIF_AUDIO_MAN_GAIN 0x3f000000
254/* Reserved [23:17] */ 261/* Reserved [23:17] */
255#define FLD_DIF_VID_AGC_OVERRIDE 0x00010000 262#define FLD_DIF_VID_AGC_OVERRIDE 0x00010000
256#define FLD_DIF_VID_MAN_GAIN 0x0000FFFF 263#define FLD_DIF_VID_MAN_GAIN 0x0000ffff
257 264
258/*****************************************************************************/ 265/*****************************************************************************/
259#define DIF_AV_SEP_CTRL (DIRECT_IF_REVB_BASE + 0x00000034) /* Reg Size 32 */ 266#define DIF_AV_SEP_CTRL (DIRECT_IF_REVB_BASE + 0x00000034)
260/*****************************************************************************/ 267/*****************************************************************************/
261#define FLD_DIF_LPF_FREQ 0xC0000000 268#define FLD_DIF_LPF_FREQ 0xc0000000
262#define FLD_DIF_AV_PHASE_INC 0x3F000000 269#define FLD_DIF_AV_PHASE_INC 0x3f000000
263#define FLD_DIF_AUDIO_FREQ 0x00FFFFFF 270#define FLD_DIF_AUDIO_FREQ 0x00ffffff
264 271
265/*****************************************************************************/ 272/*****************************************************************************/
266#define DIF_COMP_FLT_CTRL (DIRECT_IF_REVB_BASE + 0x00000038) /* Reg Size 32 */ 273#define DIF_COMP_FLT_CTRL (DIRECT_IF_REVB_BASE + 0x00000038)
267/*****************************************************************************/ 274/*****************************************************************************/
268/* Reserved [31:24] */ 275/* Reserved [31:24] */
269#define FLD_DIF_IIR23_R2 0x00FF0000 276#define FLD_DIF_IIR23_R2 0x00ff0000
270#define FLD_DIF_IIR23_R1 0x0000FF00 277#define FLD_DIF_IIR23_R1 0x0000ff00
271#define FLD_DIF_IIR1_R1 0x000000FF 278#define FLD_DIF_IIR1_R1 0x000000ff
272 279
273/*****************************************************************************/ 280/*****************************************************************************/
274#define DIF_MISC_CTRL (DIRECT_IF_REVB_BASE + 0x0000003C) /* Reg Size 32 */ 281#define DIF_MISC_CTRL (DIRECT_IF_REVB_BASE + 0x0000003c)
275/*****************************************************************************/ 282/*****************************************************************************/
276#define FLD_DIF_DIF_BYPASS 0x80000000 283#define FLD_DIF_DIF_BYPASS 0x80000000
277#define FLD_DIF_FM_NYQ_GAIN 0x40000000 284#define FLD_DIF_FM_NYQ_GAIN 0x40000000
@@ -289,184 +296,184 @@ typedef enum {
289/* Reserved [18] */ 296/* Reserved [18] */
290#define FLD_DIF_IF_FREQ 0x00030000 297#define FLD_DIF_IF_FREQ 0x00030000
291/* Reserved [15:14] */ 298/* Reserved [15:14] */
292#define FLD_DIF_TIP_OFFSET 0x00003F00 299#define FLD_DIF_TIP_OFFSET 0x00003f00
293/* Reserved [7:5] */ 300/* Reserved [7:5] */
294#define FLD_DIF_DITHER_ENA 0x00000010 301#define FLD_DIF_DITHER_ENA 0x00000010
295/* Reserved [3:1] */ 302/* Reserved [3:1] */
296#define FLD_DIF_RF_IF_LOCK 0x00000001 303#define FLD_DIF_RF_IF_LOCK 0x00000001
297 304
298/*****************************************************************************/ 305/*****************************************************************************/
299#define DIF_SRC_PHASE_INC (DIRECT_IF_REVB_BASE + 0x00000040) /* Reg Size 32 */ 306#define DIF_SRC_PHASE_INC (DIRECT_IF_REVB_BASE + 0x00000040)
300/*****************************************************************************/ 307/*****************************************************************************/
301/* Reserved [31:29] */ 308/* Reserved [31:29] */
302#define FLD_DIF_PHASE_INC 0x1FFFFFFF 309#define FLD_DIF_PHASE_INC 0x1fffffff
303 310
304/*****************************************************************************/ 311/*****************************************************************************/
305#define DIF_SRC_GAIN_CONTROL (DIRECT_IF_REVB_BASE + 0x00000044) /* Reg Size 32 */ 312#define DIF_SRC_GAIN_CONTROL (DIRECT_IF_REVB_BASE + 0x00000044)
306/*****************************************************************************/ 313/*****************************************************************************/
307/* Reserved [31:16] */ 314/* Reserved [31:16] */
308#define FLD_DIF_SRC_KI 0x0000FF00 315#define FLD_DIF_SRC_KI 0x0000ff00
309#define FLD_DIF_SRC_KD 0x000000FF 316#define FLD_DIF_SRC_KD 0x000000ff
310 317
311/*****************************************************************************/ 318/*****************************************************************************/
312#define DIF_BPF_COEFF01 (DIRECT_IF_REVB_BASE + 0x00000048) /* Reg Size 32 */ 319#define DIF_BPF_COEFF01 (DIRECT_IF_REVB_BASE + 0x00000048)
313/*****************************************************************************/ 320/*****************************************************************************/
314/* Reserved [31:19] */ 321/* Reserved [31:19] */
315#define FLD_DIF_BPF_COEFF_0 0x00070000 322#define FLD_DIF_BPF_COEFF_0 0x00070000
316/* Reserved [15:4] */ 323/* Reserved [15:4] */
317#define FLD_DIF_BPF_COEFF_1 0x0000000F 324#define FLD_DIF_BPF_COEFF_1 0x0000000f
318 325
319/*****************************************************************************/ 326/*****************************************************************************/
320#define DIF_BPF_COEFF23 (DIRECT_IF_REVB_BASE + 0x0000004c) /* Reg Size 32 */ 327#define DIF_BPF_COEFF23 (DIRECT_IF_REVB_BASE + 0x0000004c)
321/*****************************************************************************/ 328/*****************************************************************************/
322/* Reserved [31:22] */ 329/* Reserved [31:22] */
323#define FLD_DIF_BPF_COEFF_2 0x003F0000 330#define FLD_DIF_BPF_COEFF_2 0x003f0000
324/* Reserved [15:7] */ 331/* Reserved [15:7] */
325#define FLD_DIF_BPF_COEFF_3 0x0000007F 332#define FLD_DIF_BPF_COEFF_3 0x0000007f
326 333
327/*****************************************************************************/ 334/*****************************************************************************/
328#define DIF_BPF_COEFF45 (DIRECT_IF_REVB_BASE + 0x00000050) /* Reg Size 32 */ 335#define DIF_BPF_COEFF45 (DIRECT_IF_REVB_BASE + 0x00000050)
329/*****************************************************************************/ 336/*****************************************************************************/
330/* Reserved [31:24] */ 337/* Reserved [31:24] */
331#define FLD_DIF_BPF_COEFF_4 0x00FF0000 338#define FLD_DIF_BPF_COEFF_4 0x00ff0000
332/* Reserved [15:8] */ 339/* Reserved [15:8] */
333#define FLD_DIF_BPF_COEFF_5 0x000000FF 340#define FLD_DIF_BPF_COEFF_5 0x000000ff
334 341
335/*****************************************************************************/ 342/*****************************************************************************/
336#define DIF_BPF_COEFF67 (DIRECT_IF_REVB_BASE + 0x00000054) /* Reg Size 32 */ 343#define DIF_BPF_COEFF67 (DIRECT_IF_REVB_BASE + 0x00000054)
337/*****************************************************************************/ 344/*****************************************************************************/
338/* Reserved [31:25] */ 345/* Reserved [31:25] */
339#define FLD_DIF_BPF_COEFF_6 0x01FF0000 346#define FLD_DIF_BPF_COEFF_6 0x01ff0000
340/* Reserved [15:9] */ 347/* Reserved [15:9] */
341#define FLD_DIF_BPF_COEFF_7 0x000001FF 348#define FLD_DIF_BPF_COEFF_7 0x000001ff
342 349
343/*****************************************************************************/ 350/*****************************************************************************/
344#define DIF_BPF_COEFF89 (DIRECT_IF_REVB_BASE + 0x00000058) /* Reg Size 32 */ 351#define DIF_BPF_COEFF89 (DIRECT_IF_REVB_BASE + 0x00000058)
345/*****************************************************************************/ 352/*****************************************************************************/
346/* Reserved [31:26] */ 353/* Reserved [31:26] */
347#define FLD_DIF_BPF_COEFF_8 0x03FF0000 354#define FLD_DIF_BPF_COEFF_8 0x03ff0000
348/* Reserved [15:10] */ 355/* Reserved [15:10] */
349#define FLD_DIF_BPF_COEFF_9 0x000003FF 356#define FLD_DIF_BPF_COEFF_9 0x000003ff
350 357
351/*****************************************************************************/ 358/*****************************************************************************/
352#define DIF_BPF_COEFF1011 (DIRECT_IF_REVB_BASE + 0x0000005C) /* Reg Size 32 */ 359#define DIF_BPF_COEFF1011 (DIRECT_IF_REVB_BASE + 0x0000005c)
353/*****************************************************************************/ 360/*****************************************************************************/
354/* Reserved [31:27] */ 361/* Reserved [31:27] */
355#define FLD_DIF_BPF_COEFF_10 0x07FF0000 362#define FLD_DIF_BPF_COEFF_10 0x07ff0000
356/* Reserved [15:11] */ 363/* Reserved [15:11] */
357#define FLD_DIF_BPF_COEFF_11 0x000007FF 364#define FLD_DIF_BPF_COEFF_11 0x000007ff
358 365
359/*****************************************************************************/ 366/*****************************************************************************/
360#define DIF_BPF_COEFF1213 (DIRECT_IF_REVB_BASE + 0x00000060) /* Reg Size 32 */ 367#define DIF_BPF_COEFF1213 (DIRECT_IF_REVB_BASE + 0x00000060)
361/*****************************************************************************/ 368/*****************************************************************************/
362/* Reserved [31:27] */ 369/* Reserved [31:27] */
363#define FLD_DIF_BPF_COEFF_12 0x07FF0000 370#define FLD_DIF_BPF_COEFF_12 0x07ff0000
364/* Reserved [15:12] */ 371/* Reserved [15:12] */
365#define FLD_DIF_BPF_COEFF_13 0x00000FFF 372#define FLD_DIF_BPF_COEFF_13 0x00000fff
366 373
367/*****************************************************************************/ 374/*****************************************************************************/
368#define DIF_BPF_COEFF1415 (DIRECT_IF_REVB_BASE + 0x00000064) /* Reg Size 32 */ 375#define DIF_BPF_COEFF1415 (DIRECT_IF_REVB_BASE + 0x00000064)
369/*****************************************************************************/ 376/*****************************************************************************/
370/* Reserved [31:28] */ 377/* Reserved [31:28] */
371#define FLD_DIF_BPF_COEFF_14 0x0FFF0000 378#define FLD_DIF_BPF_COEFF_14 0x0fff0000
372/* Reserved [15:12] */ 379/* Reserved [15:12] */
373#define FLD_DIF_BPF_COEFF_15 0x00000FFF 380#define FLD_DIF_BPF_COEFF_15 0x00000fff
374 381
375/*****************************************************************************/ 382/*****************************************************************************/
376#define DIF_BPF_COEFF1617 (DIRECT_IF_REVB_BASE + 0x00000068) /* Reg Size 32 */ 383#define DIF_BPF_COEFF1617 (DIRECT_IF_REVB_BASE + 0x00000068)
377/*****************************************************************************/ 384/*****************************************************************************/
378/* Reserved [31:29] */ 385/* Reserved [31:29] */
379#define FLD_DIF_BPF_COEFF_16 0x1FFF0000 386#define FLD_DIF_BPF_COEFF_16 0x1fff0000
380/* Reserved [15:13] */ 387/* Reserved [15:13] */
381#define FLD_DIF_BPF_COEFF_17 0x00001FFF 388#define FLD_DIF_BPF_COEFF_17 0x00001fff
382 389
383/*****************************************************************************/ 390/*****************************************************************************/
384#define DIF_BPF_COEFF1819 (DIRECT_IF_REVB_BASE + 0x0000006C) /* Reg Size 32 */ 391#define DIF_BPF_COEFF1819 (DIRECT_IF_REVB_BASE + 0x0000006c)
385/*****************************************************************************/ 392/*****************************************************************************/
386/* Reserved [31:29] */ 393/* Reserved [31:29] */
387#define FLD_DIF_BPF_COEFF_18 0x1FFF0000 394#define FLD_DIF_BPF_COEFF_18 0x1fff0000
388/* Reserved [15:13] */ 395/* Reserved [15:13] */
389#define FLD_DIF_BPF_COEFF_19 0x00001FFF 396#define FLD_DIF_BPF_COEFF_19 0x00001fff
390 397
391/*****************************************************************************/ 398/*****************************************************************************/
392#define DIF_BPF_COEFF2021 (DIRECT_IF_REVB_BASE + 0x00000070) /* Reg Size 32 */ 399#define DIF_BPF_COEFF2021 (DIRECT_IF_REVB_BASE + 0x00000070)
393/*****************************************************************************/ 400/*****************************************************************************/
394/* Reserved [31:29] */ 401/* Reserved [31:29] */
395#define FLD_DIF_BPF_COEFF_20 0x1FFF0000 402#define FLD_DIF_BPF_COEFF_20 0x1fff0000
396/* Reserved [15:14] */ 403/* Reserved [15:14] */
397#define FLD_DIF_BPF_COEFF_21 0x00003FFF 404#define FLD_DIF_BPF_COEFF_21 0x00003fff
398 405
399/*****************************************************************************/ 406/*****************************************************************************/
400#define DIF_BPF_COEFF2223 (DIRECT_IF_REVB_BASE + 0x00000074) /* Reg Size 32 */ 407#define DIF_BPF_COEFF2223 (DIRECT_IF_REVB_BASE + 0x00000074)
401/*****************************************************************************/ 408/*****************************************************************************/
402/* Reserved [31:30] */ 409/* Reserved [31:30] */
403#define FLD_DIF_BPF_COEFF_22 0x3FFF0000 410#define FLD_DIF_BPF_COEFF_22 0x3fff0000
404/* Reserved [15:14] */ 411/* Reserved [15:14] */
405#define FLD_DIF_BPF_COEFF_23 0x00003FFF 412#define FLD_DIF_BPF_COEFF_23 0x00003fff
406 413
407/*****************************************************************************/ 414/*****************************************************************************/
408#define DIF_BPF_COEFF2425 (DIRECT_IF_REVB_BASE + 0x00000078) /* Reg Size 32 */ 415#define DIF_BPF_COEFF2425 (DIRECT_IF_REVB_BASE + 0x00000078)
409/*****************************************************************************/ 416/*****************************************************************************/
410/* Reserved [31:30] */ 417/* Reserved [31:30] */
411#define FLD_DIF_BPF_COEFF_24 0x3FFF0000 418#define FLD_DIF_BPF_COEFF_24 0x3fff0000
412/* Reserved [15:14] */ 419/* Reserved [15:14] */
413#define FLD_DIF_BPF_COEFF_25 0x00003FFF 420#define FLD_DIF_BPF_COEFF_25 0x00003fff
414 421
415/*****************************************************************************/ 422/*****************************************************************************/
416#define DIF_BPF_COEFF2627 (DIRECT_IF_REVB_BASE + 0x0000007C) /* Reg Size 32 */ 423#define DIF_BPF_COEFF2627 (DIRECT_IF_REVB_BASE + 0x0000007c)
417/*****************************************************************************/ 424/*****************************************************************************/
418/* Reserved [31:30] */ 425/* Reserved [31:30] */
419#define FLD_DIF_BPF_COEFF_26 0x3FFF0000 426#define FLD_DIF_BPF_COEFF_26 0x3fff0000
420/* Reserved [15:14] */ 427/* Reserved [15:14] */
421#define FLD_DIF_BPF_COEFF_27 0x00003FFF 428#define FLD_DIF_BPF_COEFF_27 0x00003fff
422 429
423/*****************************************************************************/ 430/*****************************************************************************/
424#define DIF_BPF_COEFF2829 (DIRECT_IF_REVB_BASE + 0x00000080) /* Reg Size 32 */ 431#define DIF_BPF_COEFF2829 (DIRECT_IF_REVB_BASE + 0x00000080)
425/*****************************************************************************/ 432/*****************************************************************************/
426/* Reserved [31:30] */ 433/* Reserved [31:30] */
427#define FLD_DIF_BPF_COEFF_28 0x3FFF0000 434#define FLD_DIF_BPF_COEFF_28 0x3fff0000
428/* Reserved [15:14] */ 435/* Reserved [15:14] */
429#define FLD_DIF_BPF_COEFF_29 0x00003FFF 436#define FLD_DIF_BPF_COEFF_29 0x00003fff
430 437
431/*****************************************************************************/ 438/*****************************************************************************/
432#define DIF_BPF_COEFF3031 (DIRECT_IF_REVB_BASE + 0x00000084) /* Reg Size 32 */ 439#define DIF_BPF_COEFF3031 (DIRECT_IF_REVB_BASE + 0x00000084)
433/*****************************************************************************/ 440/*****************************************************************************/
434/* Reserved [31:30] */ 441/* Reserved [31:30] */
435#define FLD_DIF_BPF_COEFF_30 0x3FFF0000 442#define FLD_DIF_BPF_COEFF_30 0x3fff0000
436/* Reserved [15:14] */ 443/* Reserved [15:14] */
437#define FLD_DIF_BPF_COEFF_31 0x00003FFF 444#define FLD_DIF_BPF_COEFF_31 0x00003fff
438 445
439/*****************************************************************************/ 446/*****************************************************************************/
440#define DIF_BPF_COEFF3233 (DIRECT_IF_REVB_BASE + 0x00000088) /* Reg Size 32 */ 447#define DIF_BPF_COEFF3233 (DIRECT_IF_REVB_BASE + 0x00000088)
441/*****************************************************************************/ 448/*****************************************************************************/
442/* Reserved [31:30] */ 449/* Reserved [31:30] */
443#define FLD_DIF_BPF_COEFF_32 0x3FFF0000 450#define FLD_DIF_BPF_COEFF_32 0x3fff0000
444/* Reserved [15:14] */ 451/* Reserved [15:14] */
445#define FLD_DIF_BPF_COEFF_33 0x00003FFF 452#define FLD_DIF_BPF_COEFF_33 0x00003fff
446 453
447/*****************************************************************************/ 454/*****************************************************************************/
448#define DIF_BPF_COEFF3435 (DIRECT_IF_REVB_BASE + 0x0000008C) /* Reg Size 32 */ 455#define DIF_BPF_COEFF3435 (DIRECT_IF_REVB_BASE + 0x0000008c)
449/*****************************************************************************/ 456/*****************************************************************************/
450/* Reserved [31:30] */ 457/* Reserved [31:30] */
451#define FLD_DIF_BPF_COEFF_34 0x3FFF0000 458#define FLD_DIF_BPF_COEFF_34 0x3fff0000
452/* Reserved [15:14] */ 459/* Reserved [15:14] */
453#define FLD_DIF_BPF_COEFF_35 0x00003FFF 460#define FLD_DIF_BPF_COEFF_35 0x00003fff
454 461
455/*****************************************************************************/ 462/*****************************************************************************/
456#define DIF_BPF_COEFF36 (DIRECT_IF_REVB_BASE + 0x00000090) /* Reg Size 32 */ 463#define DIF_BPF_COEFF36 (DIRECT_IF_REVB_BASE + 0x00000090)
457/*****************************************************************************/ 464/*****************************************************************************/
458/* Reserved [31:30] */ 465/* Reserved [31:30] */
459#define FLD_DIF_BPF_COEFF_36 0x3FFF0000 466#define FLD_DIF_BPF_COEFF_36 0x3fff0000
460/* Reserved [15:0] */ 467/* Reserved [15:0] */
461 468
462/*****************************************************************************/ 469/*****************************************************************************/
463#define DIF_RPT_VARIANCE (DIRECT_IF_REVB_BASE + 0x00000094) /* Reg Size 32 */ 470#define DIF_RPT_VARIANCE (DIRECT_IF_REVB_BASE + 0x00000094)
464/*****************************************************************************/ 471/*****************************************************************************/
465/* Reserved [31:20] */ 472/* Reserved [31:20] */
466#define FLD_DIF_RPT_VARIANCE 0x000FFFFF 473#define FLD_DIF_RPT_VARIANCE 0x000fffff
467 474
468/*****************************************************************************/ 475/*****************************************************************************/
469#define DIF_SOFT_RST_CTRL_REVB (DIRECT_IF_REVB_BASE + 0x00000098) /* Reg Size 32 */ 476#define DIF_SOFT_RST_CTRL_REVB (DIRECT_IF_REVB_BASE + 0x00000098)
470/*****************************************************************************/ 477/*****************************************************************************/
471/* Reserved [31:8] */ 478/* Reserved [31:8] */
472#define FLD_DIF_DIF_SOFT_RST 0x00000080 479#define FLD_DIF_DIF_SOFT_RST 0x00000080
@@ -479,9 +486,9 @@ typedef enum {
479#define FLD_DIF_PLL_RST_MSK 0x00000001 486#define FLD_DIF_PLL_RST_MSK 0x00000001
480 487
481/*****************************************************************************/ 488/*****************************************************************************/
482#define DIF_PLL_FREQ_ERR (DIRECT_IF_REVB_BASE + 0x0000009C) /* Reg Size 32 */ 489#define DIF_PLL_FREQ_ERR (DIRECT_IF_REVB_BASE + 0x0000009c)
483/*****************************************************************************/ 490/*****************************************************************************/
484/* Reserved [31:25] */ 491/* Reserved [31:25] */
485#define FLD_DIF_CTL_IP 0x01FFFFFF 492#define FLD_DIF_CTL_IP 0x01ffffff
486 493
487#endif 494#endif
diff --git a/drivers/media/video/cx231xx/cx231xx-core.c b/drivers/media/video/cx231xx/cx231xx-core.c
index 2dda863dd3c4..80deffee984a 100644
--- a/drivers/media/video/cx231xx/cx231xx-core.c
+++ b/drivers/media/video/cx231xx/cx231xx-core.c
@@ -54,7 +54,6 @@ static int alt = CX231XX_PINOUT;
54module_param(alt, int, 0644); 54module_param(alt, int, 0644);
55MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint"); 55MODULE_PARM_DESC(alt, "alternate setting to use for video endpoint");
56 56
57/* FIXME */
58#define cx231xx_isocdbg(fmt, arg...) do {\ 57#define cx231xx_isocdbg(fmt, arg...) do {\
59 if (core_debug) \ 58 if (core_debug) \
60 printk(KERN_INFO "%s %s :"fmt, \ 59 printk(KERN_INFO "%s %s :"fmt, \
@@ -308,7 +307,7 @@ int cx231xx_read_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg,
308 reg & 0xff, reg >> 8, len & 0xff, len >> 8); 307 reg & 0xff, reg >> 8, len & 0xff, len >> 8);
309 } 308 }
310 309
311 /* mutex_lock(&dev->ctrl_urb_lock); */ 310 mutex_lock(&dev->ctrl_urb_lock);
312 ret = usb_control_msg(dev->udev, pipe, req, 311 ret = usb_control_msg(dev->udev, pipe, req,
313 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 312 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
314 val, reg, dev->urb_buf, len, HZ); 313 val, reg, dev->urb_buf, len, HZ);
@@ -321,7 +320,7 @@ int cx231xx_read_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg,
321 if (len) 320 if (len)
322 memcpy(buf, dev->urb_buf, len); 321 memcpy(buf, dev->urb_buf, len);
323 322
324 /* mutex_unlock(&dev->ctrl_urb_lock); */ 323 mutex_unlock(&dev->ctrl_urb_lock);
325 324
326 if (reg_debug) { 325 if (reg_debug) {
327 int byte; 326 int byte;
@@ -369,13 +368,13 @@ int cx231xx_send_vendor_cmd(struct cx231xx *dev,
369 cx231xx_isocdbg("\n"); 368 cx231xx_isocdbg("\n");
370 } 369 }
371 370
372 /* mutex_lock(&dev->ctrl_urb_lock); */ 371 mutex_lock(&dev->ctrl_urb_lock);
373 ret = usb_control_msg(dev->udev, pipe, ven_req->bRequest, 372 ret = usb_control_msg(dev->udev, pipe, ven_req->bRequest,
374 ven_req-> 373 ven_req->
375 direction | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 374 direction | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
376 ven_req->wValue, ven_req->wIndex, ven_req->pBuff, 375 ven_req->wValue, ven_req->wIndex, ven_req->pBuff,
377 ven_req->wLength, HZ); 376 ven_req->wLength, HZ);
378 /* mutex_unlock(&dev->ctrl_urb_lock); */ 377 mutex_unlock(&dev->ctrl_urb_lock);
379 378
380 return ret; 379 return ret;
381} 380}
@@ -432,12 +431,12 @@ int cx231xx_write_ctrl_reg(struct cx231xx *dev, u8 req, u16 reg, char *buf,
432 cx231xx_isocdbg("\n"); 431 cx231xx_isocdbg("\n");
433 } 432 }
434 433
435 /* mutex_lock(&dev->ctrl_urb_lock); */ 434 mutex_lock(&dev->ctrl_urb_lock);
436 memcpy(dev->urb_buf, buf, len); 435 memcpy(dev->urb_buf, buf, len);
437 ret = usb_control_msg(dev->udev, pipe, req, 436 ret = usb_control_msg(dev->udev, pipe, req,
438 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 437 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
439 val, reg, dev->urb_buf, len, HZ); 438 val, reg, dev->urb_buf, len, HZ);
440 /* mutex_unlock(&dev->ctrl_urb_lock); */ 439 mutex_unlock(&dev->ctrl_urb_lock);
441 440
442 return ret; 441 return ret;
443} 442}
diff --git a/drivers/media/video/cx231xx/cx231xx-i2c.c b/drivers/media/video/cx231xx/cx231xx-i2c.c
index 1af87579ab49..4489126c48c1 100644
--- a/drivers/media/video/cx231xx/cx231xx-i2c.c
+++ b/drivers/media/video/cx231xx/cx231xx-i2c.c
@@ -42,8 +42,8 @@ MODULE_PARM_DESC(i2c_debug, "enable debug messages [i2c]");
42#define dprintk1(lvl, fmt, args...) \ 42#define dprintk1(lvl, fmt, args...) \
43do { \ 43do { \
44 if (i2c_debug >= lvl) { \ 44 if (i2c_debug >= lvl) { \
45 printk(fmt, ##args); \ 45 printk(fmt, ##args); \
46 } \ 46 } \
47} while (0) 47} while (0)
48 48
49#define dprintk2(lvl, fmt, args...) \ 49#define dprintk2(lvl, fmt, args...) \
@@ -77,13 +77,10 @@ int cx231xx_i2c_send_bytes(struct i2c_adapter *i2c_adap,
77 size = msg->len; 77 size = msg->len;
78 78
79 if (size == 2) { /* register write sub addr */ 79 if (size == 2) { /* register write sub addr */
80 80 /* Just writing sub address will cause problem
81 /* Just writing sub address will cause problem to XC5000 81 * to XC5000. So ignore the request */
82 So ignore the request */
83 return 0; 82 return 0;
84
85 } else if (size == 4) { /* register write with sub addr */ 83 } else if (size == 4) { /* register write with sub addr */
86
87 if (msg->len >= 2) 84 if (msg->len >= 2)
88 saddr = msg->buf[0] << 8 | msg->buf[1]; 85 saddr = msg->buf[0] << 8 | msg->buf[1];
89 else if (msg->len == 1) 86 else if (msg->len == 1)
@@ -117,7 +114,6 @@ int cx231xx_i2c_send_bytes(struct i2c_adapter *i2c_adap,
117 msg->buf, 114 msg->buf,
118 msg->len); 115 msg->len);
119 } 116 }
120
121 } 117 }
122 118
123 /* special case for Xc5000 tuner case */ 119 /* special case for Xc5000 tuner case */
diff --git a/drivers/media/video/cx231xx/cx231xx-pcb-cfg.c b/drivers/media/video/cx231xx/cx231xx-pcb-cfg.c
new file mode 100644
index 000000000000..c00f51eae0ac
--- /dev/null
+++ b/drivers/media/video/cx231xx/cx231xx-pcb-cfg.c
@@ -0,0 +1,793 @@
1/*
2 cx231xx-pcb-config.c - driver for Conexant
3 Cx23100/101/102 USB video capture devices
4
5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#include "cx231xx.h"
23#include "cx231xx-conf-reg.h"
24
25/******************************************************************************/
26
27struct pcb_config cx231xx_Scenario[] = {
28 {
29 INDEX_SELFPOWER_DIGITAL_ONLY, /* index */
30 USB_SELF_POWER, /* power_type */
31 0, /* speed , not decide yet */
32 MOD_DIGITAL, /* mode */
33 SOURCE_TS_BDA, /* ts1_source, digital tv only */
34 NOT_SUPPORTED, /* ts2_source */
35 NOT_SUPPORTED, /* analog source */
36
37 0, /* digital_index */
38 0, /* analog index */
39 0, /* dif_index */
40 0, /* external_index */
41
42 1, /* only one configuration */
43 {
44 {
45 0, /* config index */
46 {
47 0, /* interrupt ep index */
48 1, /* ts1 index */
49 NOT_SUPPORTED, /* TS2 index */
50 NOT_SUPPORTED, /* AUDIO */
51 NOT_SUPPORTED, /* VIDEO */
52 NOT_SUPPORTED, /* VANC */
53 NOT_SUPPORTED, /* HANC */
54 NOT_SUPPORTED /* ir_index */
55 }
56 ,
57 }
58 ,
59 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
60 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
61 NOT_SUPPORTED}
62 }
63 ,
64 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
65 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
66 NOT_SUPPORTED}
67 }
68 }
69 ,
70 /* full-speed config */
71 {
72 {
73 0, /* config index */
74 {
75 0, /* interrupt ep index */
76 1, /* ts1 index */
77 NOT_SUPPORTED, /* TS2 index */
78 NOT_SUPPORTED, /* AUDIO */
79 NOT_SUPPORTED, /* VIDEO */
80 NOT_SUPPORTED, /* VANC */
81 NOT_SUPPORTED, /* HANC */
82 NOT_SUPPORTED /* ir_index */
83 }
84 }
85 ,
86 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
87 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
88 NOT_SUPPORTED}
89 }
90 ,
91 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
92 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
93 NOT_SUPPORTED}
94 }
95 }
96 }
97 ,
98
99 {
100 INDEX_SELFPOWER_DUAL_DIGITAL, /* index */
101 USB_SELF_POWER, /* power_type */
102 0, /* speed , not decide yet */
103 MOD_DIGITAL, /* mode */
104 SOURCE_TS_BDA, /* ts1_source, digital tv only */
105 0, /* ts2_source,need update from register */
106 NOT_SUPPORTED, /* analog source */
107 0, /* digital_index */
108 0, /* analog index */
109 0, /* dif_index */
110 0, /* external_index */
111
112 1, /* only one configuration */
113 {
114 {
115 0, /* config index */
116 {
117 0, /* interrupt ep index */
118 1, /* ts1 index */
119 2, /* TS2 index */
120 NOT_SUPPORTED, /* AUDIO */
121 NOT_SUPPORTED, /* VIDEO */
122 NOT_SUPPORTED, /* VANC */
123 NOT_SUPPORTED, /* HANC */
124 NOT_SUPPORTED /* ir_index */
125 }
126 }
127 ,
128 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
129 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
130 NOT_SUPPORTED}
131 }
132 ,
133 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
134 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
135 NOT_SUPPORTED}
136 }
137 }
138 ,
139 /* full-speed */
140 {
141 {
142 0, /* config index */
143 {
144 0, /* interrupt ep index */
145 1, /* ts1 index */
146 2, /* TS2 index */
147 NOT_SUPPORTED, /* AUDIO */
148 NOT_SUPPORTED, /* VIDEO */
149 NOT_SUPPORTED, /* VANC */
150 NOT_SUPPORTED, /* HANC */
151 NOT_SUPPORTED /* ir_index */
152 }
153 }
154 ,
155 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
156 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
157 NOT_SUPPORTED}
158 }
159 ,
160 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
161 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
162 NOT_SUPPORTED}
163 }
164 }
165 }
166 ,
167
168 {
169 INDEX_SELFPOWER_ANALOG_ONLY, /* index */
170 USB_SELF_POWER, /* power_type */
171 0, /* speed , not decide yet */
172 MOD_ANALOG | MOD_DIF | MOD_EXTERNAL, /* mode ,analog tv only */
173 NOT_SUPPORTED, /* ts1_source, NOT SUPPORT */
174 NOT_SUPPORTED, /* ts2_source,NOT SUPPORT */
175 0, /* analog source, need update */
176
177 0, /* digital_index */
178 0, /* analog index */
179 0, /* dif_index */
180 0, /* external_index */
181
182 1, /* only one configuration */
183 {
184 {
185 0, /* config index */
186 {
187 0, /* interrupt ep index */
188 NOT_SUPPORTED, /* ts1 index */
189 NOT_SUPPORTED, /* TS2 index */
190 1, /* AUDIO */
191 2, /* VIDEO */
192 3, /* VANC */
193 4, /* HANC */
194 NOT_SUPPORTED /* ir_index */
195 }
196 }
197 ,
198 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
199 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
200 NOT_SUPPORTED}
201 }
202 ,
203 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
204 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
205 NOT_SUPPORTED}
206 }
207 }
208 ,
209 /* full-speed */
210 {
211 {
212 0, /* config index */
213 {
214 0, /* interrupt ep index */
215 NOT_SUPPORTED, /* ts1 index */
216 NOT_SUPPORTED, /* TS2 index */
217 1, /* AUDIO */
218 2, /* VIDEO */
219 NOT_SUPPORTED, /* VANC */
220 NOT_SUPPORTED, /* HANC */
221 NOT_SUPPORTED /* ir_index */
222 }
223 }
224 ,
225 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
226 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
227 NOT_SUPPORTED}
228 }
229 ,
230 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
231 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
232 NOT_SUPPORTED}
233 }
234 }
235 }
236 ,
237
238 {
239 INDEX_SELFPOWER_DUAL, /* index */
240 USB_SELF_POWER, /* power_type */
241 0, /* speed , not decide yet */
242 /* mode ,analog tv and digital path */
243 MOD_ANALOG | MOD_DIF | MOD_DIGITAL | MOD_EXTERNAL,
244 0, /* ts1_source,will update in register */
245 NOT_SUPPORTED, /* ts2_source,NOT SUPPORT */
246 0, /* analog source need update */
247 0, /* digital_index */
248 0, /* analog index */
249 0, /* dif_index */
250 0, /* external_index */
251 1, /* only one configuration */
252 {
253 {
254 0, /* config index */
255 {
256 0, /* interrupt ep index */
257 1, /* ts1 index */
258 NOT_SUPPORTED, /* TS2 index */
259 2, /* AUDIO */
260 3, /* VIDEO */
261 4, /* VANC */
262 5, /* HANC */
263 NOT_SUPPORTED /* ir_index */
264 }
265 }
266 ,
267 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
268 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
269 NOT_SUPPORTED}
270 }
271 ,
272 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
273 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
274 NOT_SUPPORTED}
275 }
276 }
277 ,
278 /* full-speed */
279 {
280 {
281 0, /* config index */
282 {
283 0, /* interrupt ep index */
284 1, /* ts1 index */
285 NOT_SUPPORTED, /* TS2 index */
286 2, /* AUDIO */
287 3, /* VIDEO */
288 NOT_SUPPORTED, /* VANC */
289 NOT_SUPPORTED, /* HANC */
290 NOT_SUPPORTED /* ir_index */
291 }
292 }
293 ,
294 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
295 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
296 NOT_SUPPORTED}
297 }
298 ,
299 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
300 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
301 NOT_SUPPORTED}
302 }
303 }
304 }
305 ,
306
307 {
308 INDEX_SELFPOWER_TRIPLE, /* index */
309 USB_SELF_POWER, /* power_type */
310 0, /* speed , not decide yet */
311 /* mode ,analog tv and digital path */
312 MOD_ANALOG | MOD_DIF | MOD_DIGITAL | MOD_EXTERNAL,
313 0, /* ts1_source, update in register */
314 0, /* ts2_source,update in register */
315 0, /* analog source, need update */
316
317 0, /* digital_index */
318 0, /* analog index */
319 0, /* dif_index */
320 0, /* external_index */
321 1, /* only one configuration */
322 {
323 {
324 0, /* config index */
325 {
326 0, /* interrupt ep index */
327 1, /* ts1 index */
328 2, /* TS2 index */
329 3, /* AUDIO */
330 4, /* VIDEO */
331 5, /* VANC */
332 6, /* HANC */
333 NOT_SUPPORTED /* ir_index */
334 }
335 }
336 ,
337 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
338 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
339 NOT_SUPPORTED}
340 }
341 ,
342 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
343 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
344 NOT_SUPPORTED}
345 }
346 }
347 ,
348 /* full-speed */
349 {
350 {
351 0, /* config index */
352 {
353 0, /* interrupt ep index */
354 1, /* ts1 index */
355 2, /* TS2 index */
356 3, /* AUDIO */
357 4, /* VIDEO */
358 NOT_SUPPORTED, /* VANC */
359 NOT_SUPPORTED, /* HANC */
360 NOT_SUPPORTED /* ir_index */
361 }
362 }
363 ,
364 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
365 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
366 NOT_SUPPORTED}
367 }
368 ,
369 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
370 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
371 NOT_SUPPORTED}
372 }
373 }
374 }
375 ,
376
377 {
378 INDEX_SELFPOWER_COMPRESSOR, /* index */
379 USB_SELF_POWER, /* power_type */
380 0, /* speed , not decide yet */
381 /* mode ,analog tv AND DIGITAL path */
382 MOD_ANALOG | MOD_DIF | MOD_DIGITAL | MOD_EXTERNAL,
383 NOT_SUPPORTED, /* ts1_source, disable */
384 SOURCE_TS_BDA, /* ts2_source */
385 0, /* analog source,need update */
386 0, /* digital_index */
387 0, /* analog index */
388 0, /* dif_index */
389 0, /* external_index */
390 1, /* only one configuration */
391 {
392 {
393 0, /* config index */
394 {
395 0, /* interrupt ep index */
396 NOT_SUPPORTED, /* ts1 index */
397 1, /* TS2 index */
398 2, /* AUDIO */
399 3, /* VIDEO */
400 4, /* VANC */
401 5, /* HANC */
402 NOT_SUPPORTED /* ir_index */
403 }
404 }
405 ,
406 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
407 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
408 NOT_SUPPORTED}
409 }
410 ,
411 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
412 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
413 NOT_SUPPORTED}
414 }
415 }
416 ,
417 /* full-speed */
418 {
419 {
420 0, /* config index */
421 {
422 0, /* interrupt ep index */
423 NOT_SUPPORTED, /* ts1 index */
424 1, /* TS2 index */
425 2, /* AUDIO */
426 3, /* VIDEO */
427 NOT_SUPPORTED, /* VANC */
428 NOT_SUPPORTED, /* HANC */
429 NOT_SUPPORTED /* ir_index */
430 }
431 }
432 ,
433 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
434 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
435 NOT_SUPPORTED}
436 }
437 ,
438 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
439 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
440 NOT_SUPPORTED}
441 }
442 }
443 }
444 ,
445
446 {
447 INDEX_BUSPOWER_DIGITAL_ONLY, /* index */
448 USB_BUS_POWER, /* power_type */
449 0, /* speed , not decide yet */
450 MOD_DIGITAL, /* mode ,analog tv AND DIGITAL path */
451 SOURCE_TS_BDA, /* ts1_source, disable */
452 NOT_SUPPORTED, /* ts2_source */
453 NOT_SUPPORTED, /* analog source */
454
455 0, /* digital_index */
456 0, /* analog index */
457 0, /* dif_index */
458 0, /* external_index */
459
460 1, /* only one configuration */
461 {
462 {
463 0, /* config index */
464 {
465 0, /* interrupt ep index = 2 */
466 1, /* ts1 index */
467 NOT_SUPPORTED, /* TS2 index */
468 NOT_SUPPORTED, /* AUDIO */
469 NOT_SUPPORTED, /* VIDEO */
470 NOT_SUPPORTED, /* VANC */
471 NOT_SUPPORTED, /* HANC */
472 NOT_SUPPORTED /* ir_index */
473 }
474 }
475 ,
476 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
477 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
478 NOT_SUPPORTED}
479 }
480 ,
481 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
482 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
483 NOT_SUPPORTED}
484 }
485 }
486 ,
487 /* full-speed */
488 {
489 {
490 0, /* config index */
491 {
492 0, /* interrupt ep index = 2 */
493 1, /* ts1 index */
494 NOT_SUPPORTED, /* TS2 index */
495 NOT_SUPPORTED, /* AUDIO */
496 NOT_SUPPORTED, /* VIDEO */
497 NOT_SUPPORTED, /* VANC */
498 NOT_SUPPORTED, /* HANC */
499 NOT_SUPPORTED /* ir_index */
500 }
501 }
502 ,
503 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
504 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
505 NOT_SUPPORTED}
506 }
507 ,
508 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
509 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
510 NOT_SUPPORTED}
511 }
512 }
513 }
514 ,
515 {
516 INDEX_BUSPOWER_ANALOG_ONLY, /* index */
517 USB_BUS_POWER, /* power_type */
518 0, /* speed , not decide yet */
519 MOD_ANALOG, /* mode ,analog tv AND DIGITAL path */
520 NOT_SUPPORTED, /* ts1_source, disable */
521 NOT_SUPPORTED, /* ts2_source */
522 SOURCE_ANALOG, /* analog source--analog */
523 0, /* digital_index */
524 0, /* analog index */
525 0, /* dif_index */
526 0, /* external_index */
527 1, /* only one configuration */
528 {
529 {
530 0, /* config index */
531 {
532 0, /* interrupt ep index */
533 NOT_SUPPORTED, /* ts1 index */
534 NOT_SUPPORTED, /* TS2 index */
535 1, /* AUDIO */
536 2, /* VIDEO */
537 3, /* VANC */
538 4, /* HANC */
539 NOT_SUPPORTED /* ir_index */
540 }
541 }
542 ,
543 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
544 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
545 NOT_SUPPORTED}
546 }
547 ,
548 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
549 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
550 NOT_SUPPORTED}
551 }
552 }
553 ,
554 { /* full-speed */
555 {
556 0, /* config index */
557 {
558 0, /* interrupt ep index */
559 NOT_SUPPORTED, /* ts1 index */
560 NOT_SUPPORTED, /* TS2 index */
561 1, /* AUDIO */
562 2, /* VIDEO */
563 NOT_SUPPORTED, /* VANC */
564 NOT_SUPPORTED, /* HANC */
565 NOT_SUPPORTED /* ir_index */
566 }
567 }
568 ,
569 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
570 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
571 NOT_SUPPORTED}
572 }
573 ,
574 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
575 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
576 NOT_SUPPORTED}
577 }
578 }
579 }
580 ,
581 {
582 INDEX_BUSPOWER_DIF_ONLY, /* index */
583 USB_BUS_POWER, /* power_type */
584 0, /* speed , not decide yet */
585 /* mode ,analog tv AND DIGITAL path */
586 MOD_DIF | MOD_ANALOG | MOD_DIGITAL | MOD_EXTERNAL,
587 SOURCE_TS_BDA, /* ts1_source, disable */
588 NOT_SUPPORTED, /* ts2_source */
589 SOURCE_DIF | SOURCE_ANALOG | SOURCE_EXTERNAL, /* analog source, dif */
590 0, /* digital_index */
591 0, /* analog index */
592 0, /* dif_index */
593 0, /* external_index */
594 1, /* only one configuration */
595 {
596 {
597 0, /* config index */
598 {
599 0, /* interrupt ep index */
600 1, /* ts1 index */
601 NOT_SUPPORTED, /* TS2 index */
602 2, /* AUDIO */
603 3, /* VIDEO */
604 4, /* VANC */
605 5, /* HANC */
606 NOT_SUPPORTED /* ir_index */
607 }
608 }
609 ,
610 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
611 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
612 NOT_SUPPORTED}
613 }
614 ,
615 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
616 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
617 NOT_SUPPORTED}
618 }
619 }
620 ,
621 { /* full speed */
622 {
623 0, /* config index */
624 {
625 0, /* interrupt ep index */
626 1, /* ts1 index */
627 NOT_SUPPORTED, /* TS2 index */
628 2, /* AUDIO */
629 3, /* VIDEO */
630 NOT_SUPPORTED, /* VANC */
631 NOT_SUPPORTED, /* HANC */
632 NOT_SUPPORTED /* ir_index */
633 }
634 }
635 ,
636 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
637 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
638 NOT_SUPPORTED}
639 }
640 ,
641 {NOT_SUPPORTED, {NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
642 NOT_SUPPORTED, NOT_SUPPORTED, NOT_SUPPORTED,
643 NOT_SUPPORTED}
644 }
645 }
646 }
647 ,
648
649};
650
651/*****************************************************************/
652
653u32 initialize_cx231xx(struct cx231xx *dev)
654{
655 u32 config_info = 0;
656 struct pcb_config *p_pcb_info;
657 u8 usb_speed = 1; /* from register,1--HS, 0--FS */
658 u8 data[4] = { 0, 0, 0, 0 };
659 u32 ts1_source = 0;
660 u32 ts2_source = 0;
661 u32 analog_source = 0;
662 u8 tmp = 0;
663 u8 _current_scenario_idx = 0xff;
664
665 cx231xx_info("PcbConfig::initialize \n");
666
667 ts1_source = SOURCE_TS_BDA;
668 ts2_source = SOURCE_TS_BDA;
669
670 /* read board config register to find out which
671 pcb config it is related to */
672 cx231xx_read_ctrl_reg(dev, VRT_GET_REGISTER, BOARD_CFG_STAT, data, 4);
673
674 config_info = *((u32 *) data);
675 cx231xx_info("SC(0x00) register = 0x%x\n", config_info);
676 usb_speed = (u8) (config_info & 0x1);
677
678 /* Verify this device belongs to Bus power or Self power device */
679 if (config_info & BUS_POWER) { /* bus-power */
680 switch (config_info & BUSPOWER_MASK) {
681 case TS1_PORT | BUS_POWER:
682 cx231xx_Scenario[INDEX_BUSPOWER_DIGITAL_ONLY].speed =
683 usb_speed;
684 p_pcb_info =
685 &cx231xx_Scenario[INDEX_BUSPOWER_DIGITAL_ONLY];
686 _current_scenario_idx = INDEX_BUSPOWER_DIGITAL_ONLY;
687 break;
688 case AVDEC_ENABLE | BUS_POWER:
689 cx231xx_Scenario[INDEX_BUSPOWER_ANALOG_ONLY].speed =
690 usb_speed;
691 p_pcb_info =
692 &cx231xx_Scenario[INDEX_BUSPOWER_ANALOG_ONLY];
693 _current_scenario_idx = INDEX_BUSPOWER_ANALOG_ONLY;
694 break;
695 case AVDEC_ENABLE | BUS_POWER | TS1_PORT:
696 cx231xx_Scenario[INDEX_BUSPOWER_DIF_ONLY].speed =
697 usb_speed;
698 p_pcb_info = &cx231xx_Scenario[INDEX_BUSPOWER_DIF_ONLY];
699 _current_scenario_idx = INDEX_BUSPOWER_DIF_ONLY;
700 break;
701 default:
702 cx231xx_info("bad config in buspower!!!!\n");
703 cx231xx_info("config_info=%x\n",
704 (config_info & BUSPOWER_MASK));
705 return 1;
706 }
707 } else { /* self-power */
708
709 switch (config_info & SELFPOWER_MASK) {
710 case TS1_PORT | SELF_POWER:
711 cx231xx_Scenario[INDEX_SELFPOWER_DIGITAL_ONLY].speed =
712 usb_speed;
713 p_pcb_info =
714 &cx231xx_Scenario[INDEX_SELFPOWER_DIGITAL_ONLY];
715 _current_scenario_idx = INDEX_SELFPOWER_DIGITAL_ONLY;
716 break;
717 case TS1_TS2_PORT | SELF_POWER:
718 cx231xx_Scenario[INDEX_SELFPOWER_DUAL_DIGITAL].speed =
719 usb_speed;
720 cx231xx_Scenario[INDEX_SELFPOWER_DUAL_DIGITAL].
721 ts2_source = ts2_source;
722 p_pcb_info =
723 &cx231xx_Scenario[INDEX_SELFPOWER_DUAL_DIGITAL];
724 _current_scenario_idx = INDEX_SELFPOWER_DUAL_DIGITAL;
725 break;
726 case AVDEC_ENABLE | SELF_POWER:
727 cx231xx_Scenario[INDEX_SELFPOWER_ANALOG_ONLY].speed =
728 usb_speed;
729 cx231xx_Scenario[INDEX_SELFPOWER_ANALOG_ONLY].
730 analog_source = analog_source;
731 p_pcb_info =
732 &cx231xx_Scenario[INDEX_SELFPOWER_ANALOG_ONLY];
733 _current_scenario_idx = INDEX_SELFPOWER_ANALOG_ONLY;
734 break;
735 case AVDEC_ENABLE | TS1_PORT | SELF_POWER:
736 cx231xx_Scenario[INDEX_SELFPOWER_DUAL].speed =
737 usb_speed;
738 cx231xx_Scenario[INDEX_SELFPOWER_DUAL].ts1_source =
739 ts1_source;
740 cx231xx_Scenario[INDEX_SELFPOWER_DUAL].analog_source =
741 analog_source;
742 p_pcb_info = &cx231xx_Scenario[INDEX_SELFPOWER_DUAL];
743 _current_scenario_idx = INDEX_SELFPOWER_DUAL;
744 break;
745 case AVDEC_ENABLE | TS1_TS2_PORT | SELF_POWER:
746 cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE].speed =
747 usb_speed;
748 cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE].ts1_source =
749 ts1_source;
750 cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE].ts2_source =
751 ts2_source;
752 cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE].analog_source =
753 analog_source;
754 p_pcb_info = &cx231xx_Scenario[INDEX_SELFPOWER_TRIPLE];
755 _current_scenario_idx = INDEX_SELFPOWER_TRIPLE;
756 break;
757 case AVDEC_ENABLE | TS1VIP_TS2_PORT | SELF_POWER:
758 cx231xx_Scenario[INDEX_SELFPOWER_COMPRESSOR].speed =
759 usb_speed;
760 cx231xx_Scenario[INDEX_SELFPOWER_COMPRESSOR].
761 analog_source = analog_source;
762 p_pcb_info =
763 &cx231xx_Scenario[INDEX_SELFPOWER_COMPRESSOR];
764 _current_scenario_idx = INDEX_SELFPOWER_COMPRESSOR;
765 break;
766 default:
767 cx231xx_info("bad senario!!!!!\n");
768 cx231xx_info("config_info=%x\n",
769 (config_info & SELFPOWER_MASK));
770 return 1;
771 }
772 }
773
774 dev->current_scenario_idx = _current_scenario_idx;
775
776 memcpy(&dev->current_pcb_config, p_pcb_info,
777 sizeof(struct pcb_config));
778
779 /*******************************************************************/
780 tmp = (dev->current_pcb_config.index) + 1;
781
782 cx231xx_info("scenario %d\n", tmp);
783 cx231xx_info("type=%x\n", dev->current_pcb_config.type);
784 cx231xx_info("mode=%x\n", dev->current_pcb_config.mode);
785 cx231xx_info("speed=%x\n", dev->current_pcb_config.speed);
786 cx231xx_info("ts1_source=%x\n", dev->current_pcb_config.ts1_source);
787 cx231xx_info("ts2_source=%x\n", dev->current_pcb_config.ts2_source);
788 cx231xx_info("analog_source=%x\n",
789 dev->current_pcb_config.analog_source);
790 /*******************************************************************/
791
792 return 0;
793}
diff --git a/drivers/media/video/cx231xx/cx231xx-pcb-cfg.h b/drivers/media/video/cx231xx/cx231xx-pcb-cfg.h
new file mode 100644
index 000000000000..86fec113f5c5
--- /dev/null
+++ b/drivers/media/video/cx231xx/cx231xx-pcb-cfg.h
@@ -0,0 +1,235 @@
1/*
2 cx231xx-pcb-cfg.h - driver for Conexant
3 Cx23100/101/102 USB video capture devices
4
5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#ifndef _PCB_CONFIG_H_
23#define _PCB_CONFIG_H_
24
25#include <linux/init.h>
26#include <linux/module.h>
27
28/***************************************************************************
29 * Class Information *
30***************************************************************************/
31#define CLASS_DEFAULT 0xFF
32
33enum VENDOR_REQUEST_TYPE {
34 /* Set/Get I2C */
35 VRT_SET_I2C0 = 0x0,
36 VRT_SET_I2C1 = 0x1,
37 VRT_SET_I2C2 = 0x2,
38 VRT_GET_I2C0 = 0x4,
39 VRT_GET_I2C1 = 0x5,
40 VRT_GET_I2C2 = 0x6,
41
42 /* Set/Get GPIO */
43 VRT_SET_GPIO = 0x8,
44 VRT_GET_GPIO = 0x9,
45
46 /* Set/Get GPIE */
47 VRT_SET_GPIE = 0xA,
48 VRT_GET_GPIE = 0xB,
49
50 /* Set/Get Register Control/Status */
51 VRT_SET_REGISTER = 0xC,
52 VRT_GET_REGISTER = 0xD,
53
54 /* Get Extended Compat ID Descriptor */
55 VRT_GET_EXTCID_DESC = 0xFF,
56};
57
58enum BYTE_ENABLE_MASK {
59 ENABLE_ONE_BYTE = 0x1,
60 ENABLE_TWE_BYTE = 0x3,
61 ENABLE_THREE_BYTE = 0x7,
62 ENABLE_FOUR_BYTE = 0xF,
63};
64
65#define SPEED_MASK 0x1
66enum USB_SPEED{
67 FULL_SPEED = 0x0, /* 0: full speed */
68 HIGH_SPEED = 0x1 /* 1: high speed */
69};
70
71enum _true_false{
72 FALSE = 0,
73 TRUE = 1
74};
75
76#define TS_MASK 0x6
77enum TS_PORT{
78 NO_TS_PORT = 0x0, /* 2'b00: Neither port used. PCB not a Hybrid,
79 only offers Analog TV or Video */
80 TS1_PORT = 0x4, /* 2'b10: TS1 Input (Hybrid mode :
81 Digital or External Analog/Compressed source) */
82 TS1_TS2_PORT = 0x6, /* 2'b11: TS1 & TS2 Inputs
83 (Dual inputs from Digital and/or
84 External Analog/Compressed sources) */
85 TS1_EXT_CLOCK = 0x6, /* 2'b11: TS1 & TS2 as selector
86 to external clock */
87 TS1VIP_TS2_PORT = 0x2 /* 2'b01: TS1 used as 656/VIP Output,
88 TS2 Input (from Compressor) */
89};
90
91#define EAVP_MASK 0x8
92enum EAV_PRESENT{
93 NO_EXTERNAL_AV = 0x0, /* 0: No External A/V inputs
94 (no need for Flatiron),
95 Analog Tuner must be present */
96 EXTERNAL_AV = 0x8 /* 1: External A/V inputs
97 present (requires Flatiron) */
98};
99
100#define ATM_MASK 0x30
101enum AT_MODE{
102 DIF_TUNER = 0x30, /* 2'b11: IF Tuner (requires use of DIF) */
103 BASEBAND_SOUND = 0x20, /* 2'b10: Baseband Composite &
104 Sound-IF Signals present */
105 NO_TUNER = 0x10 /* 2'b0x: No Analog Tuner present */
106};
107
108#define PWR_SEL_MASK 0x40
109enum POWE_TYPE{
110 SELF_POWER = 0x0, /* 0: self power */
111 BUS_POWER = 0x40 /* 1: bus power */
112};
113
114enum USB_POWE_TYPE{
115 USB_SELF_POWER = 0,
116 USB_BUS_POWER
117};
118
119#define BO_0_MASK 0x80
120enum AVDEC_STATUS{
121 AVDEC_DISABLE = 0x0, /* 0: A/V Decoder Disabled */
122 AVDEC_ENABLE = 0x80 /* 1: A/V Decoder Enabled */
123};
124
125#define BO_1_MASK 0x100
126enum HAMMERHEAD__STATUS{
127 HAMMERHEAD_ONLY = 0x0, /* 0:Hammerhead Only */
128 HAMMERHEAD_SC = 0x100 /* 1:Hammerhead and SC */
129};
130
131#define BUSPOWER_MASK 0xC4 /* for Polaris spec 0.8 */
132#define SELFPOWER_MASK 0x86
133
134/***************************************************************************/
135#define NOT_DECIDE_YET 0xFE
136#define NOT_SUPPORTED 0xFF
137
138/***************************************************************************
139 * for mod field use *
140***************************************************************************/
141#define MOD_DIGITAL 0x1
142#define MOD_ANALOG 0x2
143#define MOD_DIF 0x4
144#define MOD_EXTERNAL 0x8
145#define CAP_ALL_MOD 0x0f
146
147/***************************************************************************
148 * source define *
149***************************************************************************/
150#define SOURCE_DIGITAL 0x1
151#define SOURCE_ANALOG 0x2
152#define SOURCE_DIF 0x4
153#define SOURCE_EXTERNAL 0x8
154#define SOURCE_TS_BDA 0x10
155#define SOURCE_TS_ENCODE 0x20
156#define SOURCE_TS_EXTERNAL 0x40
157
158/***************************************************************************
159 * interface information define *
160***************************************************************************/
161struct INTERFACE_INFO {
162 u8 interrupt_index;
163 u8 ts1_index;
164 u8 ts2_index;
165 u8 audio_index;
166 u8 video_index;
167 u8 vanc_index; /* VBI */
168 u8 hanc_index; /* Sliced CC */
169 u8 ir_index;
170};
171
172enum INDEX_INTERFACE_INFO{
173 INDEX_INTERRUPT = 0x0,
174 INDEX_TS1,
175 INDEX_TS2,
176 INDEX_AUDIO,
177 INDEX_VIDEO,
178 INDEX_VANC,
179 INDEX_HANC,
180 INDEX_IR,
181};
182
183/***************************************************************************
184 * configuration information define *
185***************************************************************************/
186struct CONFIG_INFO {
187 u8 config_index;
188 struct INTERFACE_INFO interface_info;
189};
190
191struct pcb_config {
192 u8 index;
193 u8 type; /* bus power or self power,
194 self power--0, bus_power--1 */
195 u8 speed; /* usb speed, 2.0--1, 1.1--0 */
196 u8 mode; /* digital , anlog, dif or external A/V */
197 u32 ts1_source; /* three source -- BDA,External,encode */
198 u32 ts2_source;
199 u32 analog_source;
200 u8 digital_index; /* bus-power used */
201 u8 analog_index; /* bus-power used */
202 u8 dif_index; /* bus-power used */
203 u8 external_index; /* bus-power used */
204 u8 config_num; /* current config num, 0,1,2,
205 for self-power, always 0 */
206 struct CONFIG_INFO hs_config_info[3];
207 struct CONFIG_INFO fs_config_info[3];
208};
209
210enum INDEX_PCB_CONFIG{
211 INDEX_SELFPOWER_DIGITAL_ONLY = 0x0,
212 INDEX_SELFPOWER_DUAL_DIGITAL,
213 INDEX_SELFPOWER_ANALOG_ONLY,
214 INDEX_SELFPOWER_DUAL,
215 INDEX_SELFPOWER_TRIPLE,
216 INDEX_SELFPOWER_COMPRESSOR,
217 INDEX_BUSPOWER_DIGITAL_ONLY,
218 INDEX_BUSPOWER_ANALOG_ONLY,
219 INDEX_BUSPOWER_DIF_ONLY,
220 INDEX_BUSPOWER_EXTERNAL_ONLY,
221 INDEX_BUSPOWER_EXTERNAL_ANALOG,
222 INDEX_BUSPOWER_EXTERNAL_DIF,
223 INDEX_BUSPOWER_EXTERNAL_DIGITAL,
224 INDEX_BUSPOWER_DIGITAL_ANALOG,
225 INDEX_BUSPOWER_DIGITAL_DIF,
226 INDEX_BUSPOWER_DIGITAL_ANALOG_EXTERNAL,
227 INDEX_BUSPOWER_DIGITAL_DIF_EXTERNAL,
228};
229
230/***************************************************************************/
231struct cx231xx;
232
233u32 initialize_cx231xx(struct cx231xx *p_dev);
234
235#endif
diff --git a/drivers/media/video/cx231xx/cx231xx-reg.h b/drivers/media/video/cx231xx/cx231xx-reg.h
index d2d325b21d4f..750c5d37d569 100644
--- a/drivers/media/video/cx231xx/cx231xx-reg.h
+++ b/drivers/media/video/cx231xx/cx231xx-reg.h
@@ -1,6 +1,6 @@
1/* 1/*
2 cx231xx-reg.h - driver for Conexant Cx23100/101/102 2 cx231xx-reg.h - driver for Conexant Cx23100/101/102
3 USB video capture devices 3 USB video capture devices
4 4
5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com> 5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
6 6
@@ -23,31 +23,31 @@
23#define _CX231XX_REG_H 23#define _CX231XX_REG_H
24 24
25/***************************************************************************** 25/*****************************************************************************
26 * VBI codes * 26 * VBI codes *
27*****************************************************************************/ 27*****************************************************************************/
28 28
29#define SAV_ACTIVE_VIDEO_FIELD1 0x80 29#define SAV_ACTIVE_VIDEO_FIELD1 0x80
30#define EAV_ACTIVE_VIDEO_FIELD1 0x90 30#define EAV_ACTIVE_VIDEO_FIELD1 0x90
31 31
32#define SAV_ACTIVE_VIDEO_FIELD2 0xC0 32#define SAV_ACTIVE_VIDEO_FIELD2 0xc0
33#define EAV_ACTIVE_VIDEO_FIELD2 0xD0 33#define EAV_ACTIVE_VIDEO_FIELD2 0xd0
34 34
35#define SAV_VBLANK_FIELD1 0xA0 35#define SAV_VBLANK_FIELD1 0xa0
36#define EAV_VBLANK_FIELD1 0xB0 36#define EAV_VBLANK_FIELD1 0xb0
37 37
38#define SAV_VBLANK_FIELD2 0xE0 38#define SAV_VBLANK_FIELD2 0xe0
39#define EAV_VBLANK_FIELD2 0xF0 39#define EAV_VBLANK_FIELD2 0xf0
40 40
41#define SAV_VBI_FIELD1 0x20 41#define SAV_VBI_FIELD1 0x20
42#define EAV_VBI_FIELD1 0x30 42#define EAV_VBI_FIELD1 0x30
43 43
44#define SAV_VBI_FIELD2 0x60 44#define SAV_VBI_FIELD2 0x60
45#define EAV_VBI_FIELD2 0x70 45#define EAV_VBI_FIELD2 0x70
46 46
47/*****************************************************************************/ 47/*****************************************************************************/
48/* Audio ADC Registers */ 48/* Audio ADC Registers */
49#define CH_PWR_CTRL1 0x0000000E 49#define CH_PWR_CTRL1 0x0000000e
50#define CH_PWR_CTRL2 0x0000000F 50#define CH_PWR_CTRL2 0x0000000f
51/*****************************************************************************/ 51/*****************************************************************************/
52 52
53#define HOST_REG1 0x000 53#define HOST_REG1 0x000
@@ -74,11 +74,11 @@
74#define TS1_PIN_CTL1 0x8 74#define TS1_PIN_CTL1 0x8
75/*****************************************************************************/ 75/*****************************************************************************/
76 76
77#define FLD_CLK_IN_EN 0x80 77#define FLD_CLK_IN_EN 0x80
78#define FLD_XTAL_CTRL 0x70 78#define FLD_XTAL_CTRL 0x70
79#define FLD_BB_CLK_MODE 0x0C 79#define FLD_BB_CLK_MODE 0x0C
80#define FLD_REF_DIV_PLL 0x02 80#define FLD_REF_DIV_PLL 0x02
81#define FLD_REF_SEL_PLL1 0x01 81#define FLD_REF_SEL_PLL1 0x01
82 82
83/*****************************************************************************/ 83/*****************************************************************************/
84#define CHIP_CTRL 0x100 84#define CHIP_CTRL 0x100
@@ -89,16 +89,16 @@
89#define FLD_DUAL_MODE_ADC2 0x00040000 89#define FLD_DUAL_MODE_ADC2 0x00040000
90#define FLD_SIF_EN 0x00020000 90#define FLD_SIF_EN 0x00020000
91#define FLD_SOFT_RST 0x00010000 91#define FLD_SOFT_RST 0x00010000
92#define FLD_DEVICE_ID 0x0000FFFF 92#define FLD_DEVICE_ID 0x0000ffff
93 93
94/*****************************************************************************/ 94/*****************************************************************************/
95#define AFE_CTRL 0x104 95#define AFE_CTRL 0x104
96#define AFE_CTRL_C2HH_SRC_CTRL 0x104 96#define AFE_CTRL_C2HH_SRC_CTRL 0x104
97#define FLD_DIF_OUT_SEL 0xC0000000 97#define FLD_DIF_OUT_SEL 0xc0000000
98#define FLD_AUX_PLL_CLK_ALT_SEL 0x3C000000 98#define FLD_AUX_PLL_CLK_ALT_SEL 0x3c000000
99#define FLD_UV_ORDER_MODE 0x02000000 99#define FLD_UV_ORDER_MODE 0x02000000
100#define FLD_FUNC_MODE 0x01800000 100#define FLD_FUNC_MODE 0x01800000
101#define FLD_ROT1_PHASE_CTL 0x007F8000 101#define FLD_ROT1_PHASE_CTL 0x007f8000
102#define FLD_AUD_IN_SEL 0x00004000 102#define FLD_AUD_IN_SEL 0x00004000
103#define FLD_LUMA_IN_SEL 0x00002000 103#define FLD_LUMA_IN_SEL 0x00002000
104#define FLD_CHROMA_IN_SEL 0x00001000 104#define FLD_CHROMA_IN_SEL 0x00001000
@@ -118,16 +118,16 @@
118/*****************************************************************************/ 118/*****************************************************************************/
119#define DC_CTRL1 0x108 119#define DC_CTRL1 0x108
120/* reserve [31:30] */ 120/* reserve [31:30] */
121#define FLD_CLAMP_LVL_CH1 0x3FFF8000 121#define FLD_CLAMP_LVL_CH1 0x3fff8000
122#define FLD_CLAMP_LVL_CH2 0x00007FFF 122#define FLD_CLAMP_LVL_CH2 0x00007fff
123/*****************************************************************************/ 123/*****************************************************************************/
124 124
125/*****************************************************************************/ 125/*****************************************************************************/
126#define DC_CTRL2 0x10c 126#define DC_CTRL2 0x10c
127/* reserve [31:28] */ 127/* reserve [31:28] */
128#define FLD_CLAMP_LVL_CH3 0x00FFFE00 128#define FLD_CLAMP_LVL_CH3 0x00fffe00
129#define FLD_CLAMP_WIND_LENTH 0x000001E0 129#define FLD_CLAMP_WIND_LENTH 0x000001e0
130#define FLD_C2HH_SAT_MIN 0x0000001E 130#define FLD_C2HH_SAT_MIN 0x0000001e
131#define FLD_FLT_BYP_SEL 0x00000001 131#define FLD_FLT_BYP_SEL 0x00000001
132/*****************************************************************************/ 132/*****************************************************************************/
133 133
@@ -135,25 +135,25 @@
135#define DC_CTRL3 0x110 135#define DC_CTRL3 0x110
136/* reserve [31:16] */ 136/* reserve [31:16] */
137#define FLD_ERR_GAIN_CTL 0x00070000 137#define FLD_ERR_GAIN_CTL 0x00070000
138#define FLD_LPF_MIN 0x0000FFFF 138#define FLD_LPF_MIN 0x0000ffff
139/*****************************************************************************/ 139/*****************************************************************************/
140 140
141/*****************************************************************************/ 141/*****************************************************************************/
142#define DC_CTRL4 0x114 142#define DC_CTRL4 0x114
143/* reserve [31:31] */ 143/* reserve [31:31] */
144#define FLD_INTG_CH1 0x7FFFFFFF 144#define FLD_INTG_CH1 0x7fffffff
145/*****************************************************************************/ 145/*****************************************************************************/
146 146
147/*****************************************************************************/ 147/*****************************************************************************/
148#define DC_CTRL5 0x118 148#define DC_CTRL5 0x118
149/* reserve [31:31] */ 149/* reserve [31:31] */
150#define FLD_INTG_CH2 0x7FFFFFFF 150#define FLD_INTG_CH2 0x7fffffff
151/*****************************************************************************/ 151/*****************************************************************************/
152 152
153/*****************************************************************************/ 153/*****************************************************************************/
154#define DC_CTRL6 0x11c 154#define DC_CTRL6 0x11c
155/* reserve [31:31] */ 155/* reserve [31:31] */
156#define FLD_INTG_CH3 0x7FFFFFFF 156#define FLD_INTG_CH3 0x7fffffff
157/*****************************************************************************/ 157/*****************************************************************************/
158 158
159/*****************************************************************************/ 159/*****************************************************************************/
@@ -182,30 +182,30 @@
182#define FLD_I2S_PORT_DIR 0x00000080 182#define FLD_I2S_PORT_DIR 0x00000080
183#define FLD_I2S_OUT_SRC 0x00000040 183#define FLD_I2S_OUT_SRC 0x00000040
184#define FLD_AUD_CHAN3_SRC 0x00000030 184#define FLD_AUD_CHAN3_SRC 0x00000030
185#define FLD_AUD_CHAN2_SRC 0x0000000C 185#define FLD_AUD_CHAN2_SRC 0x0000000c
186#define FLD_AUD_CHAN1_SRC 0x00000003 186#define FLD_AUD_CHAN1_SRC 0x00000003
187 187
188/*****************************************************************************/ 188/*****************************************************************************/
189#define AUD_LOCK1 0x128 189#define AUD_LOCK1 0x128
190#define FLD_AUD_LOCK_KI_SHIFT 0xC0000000 190#define FLD_AUD_LOCK_KI_SHIFT 0xc0000000
191#define FLD_AUD_LOCK_KD_SHIFT 0x30000000 191#define FLD_AUD_LOCK_KD_SHIFT 0x30000000
192/* Reserved [27:25] */ 192/* Reserved [27:25] */
193#define FLD_EN_AV_LOCK 0x01000000 193#define FLD_EN_AV_LOCK 0x01000000
194#define FLD_VID_COUNT 0x00FFFFFF 194#define FLD_VID_COUNT 0x00ffffff
195 195
196/*****************************************************************************/ 196/*****************************************************************************/
197#define AUD_LOCK2 0x12C 197#define AUD_LOCK2 0x12c
198#define FLD_AUD_LOCK_KI_MULT 0xF0000000 198#define FLD_AUD_LOCK_KI_MULT 0xf0000000
199#define FLD_AUD_LOCK_KD_MULT 0x0F000000 199#define FLD_AUD_LOCK_KD_MULT 0x0F000000
200/* Reserved [23:22] */ 200/* Reserved [23:22] */
201#define FLD_AUD_LOCK_FREQ_SHIFT 0x00300000 201#define FLD_AUD_LOCK_FREQ_SHIFT 0x00300000
202#define FLD_AUD_COUNT 0x000FFFFF 202#define FLD_AUD_COUNT 0x000fffff
203 203
204/*****************************************************************************/ 204/*****************************************************************************/
205#define AFE_DIAG_CTRL1 0x134 205#define AFE_DIAG_CTRL1 0x134
206/* Reserved [31:16] */ 206/* Reserved [31:16] */
207#define FLD_CUV_DLY_LENGTH 0x0000FF00 207#define FLD_CUV_DLY_LENGTH 0x0000ff00
208#define FLD_YC_DLY_LENGTH 0x000000FF 208#define FLD_YC_DLY_LENGTH 0x000000ff
209 209
210/*****************************************************************************/ 210/*****************************************************************************/
211/* Poalris redefine */ 211/* Poalris redefine */
@@ -218,18 +218,18 @@
218#define FLD_COL_CLAMP_DIS_CH2 0x00200000 218#define FLD_COL_CLAMP_DIS_CH2 0x00200000
219#define FLD_COL_CLAMP_DIS_CH3 0x00100000 219#define FLD_COL_CLAMP_DIS_CH3 0x00100000
220 220
221#define TEST_CTRL1 0x144 221#define TEST_CTRL1 0x144
222/* Reserved [31:29] */ 222/* Reserved [31:29] */
223#define FLD_LBIST_EN 0x10000000 223#define FLD_LBIST_EN 0x10000000
224/* Reserved [27:10] */ 224/* Reserved [27:10] */
225#define FLD_FI_BIST_INTR_R 0x0000200 225#define FLD_FI_BIST_INTR_R 0x0000200
226#define FLD_FI_BIST_INTR_L 0x0000100 226#define FLD_FI_BIST_INTR_L 0x0000100
227#define FLD_BIST_FAIL_AUD_PLL 0x0000080 227#define FLD_BIST_FAIL_AUD_PLL 0x0000080
228#define FLD_BIST_INTR_AUD_PLL 0x0000040 228#define FLD_BIST_INTR_AUD_PLL 0x0000040
229#define FLD_BIST_FAIL_VID_PLL 0x0000020 229#define FLD_BIST_FAIL_VID_PLL 0x0000020
230#define FLD_BIST_INTR_VID_PLL 0x0000010 230#define FLD_BIST_INTR_VID_PLL 0x0000010
231/* Reserved [3:1] */ 231/* Reserved [3:1] */
232#define FLD_CIR_TEST_DIS 0x00000001 232#define FLD_CIR_TEST_DIS 0x00000001
233 233
234/*****************************************************************************/ 234/*****************************************************************************/
235#define TEST_CTRL2 0x148 235#define TEST_CTRL2 0x148
@@ -237,7 +237,7 @@
237#define FLD_ISO_CTL_SEL 0x40000000 237#define FLD_ISO_CTL_SEL 0x40000000
238#define FLD_ISO_CTL_EN 0x20000000 238#define FLD_ISO_CTL_EN 0x20000000
239#define FLD_BIST_DEBUGZ 0x10000000 239#define FLD_BIST_DEBUGZ 0x10000000
240#define FLD_AUD_BIST_TEST_H 0x0F000000 240#define FLD_AUD_BIST_TEST_H 0x0f000000
241/* Reserved [23:22] */ 241/* Reserved [23:22] */
242#define FLD_FLTRN_BIST_TEST_H 0x00020000 242#define FLD_FLTRN_BIST_TEST_H 0x00020000
243#define FLD_VID_BIST_TEST_H 0x00010000 243#define FLD_VID_BIST_TEST_H 0x00010000
@@ -248,11 +248,11 @@
248/* Reserved [11:0] */ 248/* Reserved [11:0] */
249 249
250/*****************************************************************************/ 250/*****************************************************************************/
251#define BIST_STAT 0x14C 251#define BIST_STAT 0x14c
252#define FLD_AUD_BIST_FAIL_H 0xFFF00000 252#define FLD_AUD_BIST_FAIL_H 0xfff00000
253#define FLD_FLTRN_BIST_FAIL_H 0x00180000 253#define FLD_FLTRN_BIST_FAIL_H 0x00180000
254#define FLD_VID_BIST_FAIL_H 0x00070000 254#define FLD_VID_BIST_FAIL_H 0x00070000
255#define FLD_AUD_BIST_TST_DONE 0x0000FFF0 255#define FLD_AUD_BIST_TST_DONE 0x0000fff0
256#define FLD_FLTRN_BIST_TST_DONE 0x00000008 256#define FLD_FLTRN_BIST_TST_DONE 0x00000008
257#define FLD_VID_BIST_TST_DONE 0x00000007 257#define FLD_VID_BIST_TST_DONE 0x00000007
258 258
@@ -266,7 +266,7 @@
266#define FLD_AFD_FORCE_PAL 0x04000000 266#define FLD_AFD_FORCE_PAL 0x04000000
267#define FLD_AFD_PALM_SEL 0x03000000 267#define FLD_AFD_PALM_SEL 0x03000000
268#define FLD_CKILL_MODE 0x00300000 268#define FLD_CKILL_MODE 0x00300000
269#define FLD_COMB_NOTCH_MODE 0x00c00000 /* bit[19:18] */ 269#define FLD_COMB_NOTCH_MODE 0x00c00000 /* bit[19:18] */
270#define FLD_CLR_LOCK_STAT 0x00020000 270#define FLD_CLR_LOCK_STAT 0x00020000
271#define FLD_FAST_LOCK_MD 0x00010000 271#define FLD_FAST_LOCK_MD 0x00010000
272#define FLD_WCEN 0x00008000 272#define FLD_WCEN 0x00008000
@@ -280,11 +280,11 @@
280#define FLD_AFD_PAL_SEL 0x00000040 280#define FLD_AFD_PAL_SEL 0x00000040
281#define FLD_ACFG_DIS 0x00000020 281#define FLD_ACFG_DIS 0x00000020
282#define FLD_SQ_PIXEL 0x00000010 282#define FLD_SQ_PIXEL 0x00000010
283#define FLD_VID_FMT_SEL 0x0000000F 283#define FLD_VID_FMT_SEL 0x0000000f
284 284
285/*****************************************************************************/ 285/*****************************************************************************/
286#define OUT_CTRL1 0x404 286#define OUT_CTRL1 0x404
287#define FLD_POLAR 0x7F000000 287#define FLD_POLAR 0x7f000000
288/* Reserved [23] */ 288/* Reserved [23] */
289#define FLD_RND_MODE 0x00600000 289#define FLD_RND_MODE 0x00600000
290#define FLD_VIPCLAMP_EN 0x00100000 290#define FLD_VIPCLAMP_EN 0x00100000
@@ -292,7 +292,7 @@
292#define FLD_VIP_OPT_AL 0x00040000 292#define FLD_VIP_OPT_AL 0x00040000
293#define FLD_IDID0_SOURCE 0x00020000 293#define FLD_IDID0_SOURCE 0x00020000
294#define FLD_DCMODE 0x00010000 294#define FLD_DCMODE 0x00010000
295#define FLD_CLK_GATING 0x0000C000 295#define FLD_CLK_GATING 0x0000c000
296#define FLD_CLK_INVERT 0x00002000 296#define FLD_CLK_INVERT 0x00002000
297#define FLD_HSFMT 0x00001000 297#define FLD_HSFMT 0x00001000
298#define FLD_VALIDFMT 0x00000800 298#define FLD_VALIDFMT 0x00000800
@@ -309,20 +309,20 @@
309 309
310/*****************************************************************************/ 310/*****************************************************************************/
311#define OUT_CTRL2 0x408 311#define OUT_CTRL2 0x408
312#define FLD_AUD_GRP 0xC0000000 312#define FLD_AUD_GRP 0xc0000000
313#define FLD_SAMPLE_RATE 0x30000000 313#define FLD_SAMPLE_RATE 0x30000000
314#define FLD_AUD_ANC_EN 0x08000000 314#define FLD_AUD_ANC_EN 0x08000000
315#define FLD_EN_C 0x04000000 315#define FLD_EN_C 0x04000000
316#define FLD_EN_B 0x02000000 316#define FLD_EN_B 0x02000000
317#define FLD_EN_A 0x01000000 317#define FLD_EN_A 0x01000000
318/* Reserved [23:20] */ 318/* Reserved [23:20] */
319#define FLD_IDID1_LSB 0x000C0000 319#define FLD_IDID1_LSB 0x000c0000
320#define FLD_IDID0_LSB 0x00030000 320#define FLD_IDID0_LSB 0x00030000
321#define FLD_IDID1_MSB 0x0000FF00 321#define FLD_IDID1_MSB 0x0000ff00
322#define FLD_IDID0_MSB 0x000000FF 322#define FLD_IDID0_MSB 0x000000ff
323 323
324/*****************************************************************************/ 324/*****************************************************************************/
325#define GEN_STAT 0x40C 325#define GEN_STAT 0x40c
326#define FLD_VCR_DETECT 0x00800000 326#define FLD_VCR_DETECT 0x00800000
327#define FLD_SPECIAL_PLAY_N 0x00400000 327#define FLD_SPECIAL_PLAY_N 0x00400000
328#define FLD_VPRES 0x00200000 328#define FLD_VPRES 0x00200000
@@ -335,7 +335,7 @@
335#define FLD_SRC_FIFO_UFLOW 0x00004000 335#define FLD_SRC_FIFO_UFLOW 0x00004000
336#define FLD_SRC_FIFO_OFLOW 0x00002000 336#define FLD_SRC_FIFO_OFLOW 0x00002000
337#define FLD_FIELD 0x00001000 337#define FLD_FIELD 0x00001000
338#define FLD_AFD_FMT_STAT 0x00000F00 338#define FLD_AFD_FMT_STAT 0x00000f00
339#define FLD_MV_TYPE2_PAIR 0x00000080 339#define FLD_MV_TYPE2_PAIR 0x00000080
340#define FLD_MV_T3CS 0x00000040 340#define FLD_MV_T3CS 0x00000040
341#define FLD_MV_CS 0x00000020 341#define FLD_MV_CS 0x00000020
@@ -383,27 +383,27 @@
383#define BRIGHTNESS_CTRL_BYTE 0x414 383#define BRIGHTNESS_CTRL_BYTE 0x414
384#define CONTRAST_CTRL_BYTE 0x415 384#define CONTRAST_CTRL_BYTE 0x415
385#define LUMA_CTRL_BYTE_3 0x416 385#define LUMA_CTRL_BYTE_3 0x416
386#define FLD_LUMA_CORE_SEL 0x00C00000 386#define FLD_LUMA_CORE_SEL 0x00c00000
387#define FLD_RANGE 0x00300000 387#define FLD_RANGE 0x00300000
388/* Reserved [19] */ 388/* Reserved [19] */
389#define FLD_PEAK_EN 0x00040000 389#define FLD_PEAK_EN 0x00040000
390#define FLD_PEAK_SEL 0x00030000 390#define FLD_PEAK_SEL 0x00030000
391#define FLD_CNTRST 0x0000FF00 391#define FLD_CNTRST 0x0000ff00
392#define FLD_BRITE 0x000000FF 392#define FLD_BRITE 0x000000ff
393 393
394/*****************************************************************************/ 394/*****************************************************************************/
395#define HSCALE_CTRL 0x418 395#define HSCALE_CTRL 0x418
396#define FLD_HFILT 0x03000000 396#define FLD_HFILT 0x03000000
397#define FLD_HSCALE 0x00FFFFFF 397#define FLD_HSCALE 0x00ffffff
398 398
399/*****************************************************************************/ 399/*****************************************************************************/
400#define VSCALE_CTRL 0x41C 400#define VSCALE_CTRL 0x41c
401#define FLD_LINE_AVG_DIS 0x01000000 401#define FLD_LINE_AVG_DIS 0x01000000
402/* Reserved [23:20] */ 402/* Reserved [23:20] */
403#define FLD_VS_INTRLACE 0x00080000 403#define FLD_VS_INTRLACE 0x00080000
404#define FLD_VFILT 0x00070000 404#define FLD_VFILT 0x00070000
405/* Reserved [15:13] */ 405/* Reserved [15:13] */
406#define FLD_VSCALE 0x00001FFF 406#define FLD_VSCALE 0x00001fff
407 407
408/*****************************************************************************/ 408/*****************************************************************************/
409#define CHROMA_CTRL 0x420 409#define CHROMA_CTRL 0x420
@@ -411,76 +411,76 @@
411#define VSAT_CTRL_BYTE 0x421 411#define VSAT_CTRL_BYTE 0x421
412#define HUE_CTRL_BYTE 0x422 412#define HUE_CTRL_BYTE 0x422
413#define FLD_C_LPF_EN 0x20000000 413#define FLD_C_LPF_EN 0x20000000
414#define FLD_CHR_DELAY 0x1C000000 414#define FLD_CHR_DELAY 0x1c000000
415#define FLD_C_CORE_SEL 0x03000000 415#define FLD_C_CORE_SEL 0x03000000
416#define FLD_HUE 0x00FF0000 416#define FLD_HUE 0x00ff0000
417#define FLD_VSAT 0x0000FF00 417#define FLD_VSAT 0x0000ff00
418#define FLD_USAT 0x000000FF 418#define FLD_USAT 0x000000ff
419 419
420/*****************************************************************************/ 420/*****************************************************************************/
421#define VBI_LINE_CTRL1 0x424 421#define VBI_LINE_CTRL1 0x424
422#define FLD_VBI_MD_LINE4 0xFF000000 422#define FLD_VBI_MD_LINE4 0xff000000
423#define FLD_VBI_MD_LINE3 0x00FF0000 423#define FLD_VBI_MD_LINE3 0x00ff0000
424#define FLD_VBI_MD_LINE2 0x0000FF00 424#define FLD_VBI_MD_LINE2 0x0000ff00
425#define FLD_VBI_MD_LINE1 0x000000FF 425#define FLD_VBI_MD_LINE1 0x000000ff
426 426
427/*****************************************************************************/ 427/*****************************************************************************/
428#define VBI_LINE_CTRL2 0x428 428#define VBI_LINE_CTRL2 0x428
429#define FLD_VBI_MD_LINE8 0xFF000000 429#define FLD_VBI_MD_LINE8 0xff000000
430#define FLD_VBI_MD_LINE7 0x00FF0000 430#define FLD_VBI_MD_LINE7 0x00ff0000
431#define FLD_VBI_MD_LINE6 0x0000FF00 431#define FLD_VBI_MD_LINE6 0x0000ff00
432#define FLD_VBI_MD_LINE5 0x000000FF 432#define FLD_VBI_MD_LINE5 0x000000ff
433 433
434/*****************************************************************************/ 434/*****************************************************************************/
435#define VBI_LINE_CTRL3 0x42C 435#define VBI_LINE_CTRL3 0x42c
436#define FLD_VBI_MD_LINE12 0xFF000000 436#define FLD_VBI_MD_LINE12 0xff000000
437#define FLD_VBI_MD_LINE11 0x00FF0000 437#define FLD_VBI_MD_LINE11 0x00ff0000
438#define FLD_VBI_MD_LINE10 0x0000FF00 438#define FLD_VBI_MD_LINE10 0x0000ff00
439#define FLD_VBI_MD_LINE9 0x000000FF 439#define FLD_VBI_MD_LINE9 0x000000ff
440 440
441/*****************************************************************************/ 441/*****************************************************************************/
442#define VBI_LINE_CTRL4 0x430 442#define VBI_LINE_CTRL4 0x430
443#define FLD_VBI_MD_LINE16 0xFF000000 443#define FLD_VBI_MD_LINE16 0xff000000
444#define FLD_VBI_MD_LINE15 0x00FF0000 444#define FLD_VBI_MD_LINE15 0x00ff0000
445#define FLD_VBI_MD_LINE14 0x0000FF00 445#define FLD_VBI_MD_LINE14 0x0000ff00
446#define FLD_VBI_MD_LINE13 0x000000FF 446#define FLD_VBI_MD_LINE13 0x000000ff
447 447
448/*****************************************************************************/ 448/*****************************************************************************/
449#define VBI_LINE_CTRL5 0x434 449#define VBI_LINE_CTRL5 0x434
450#define FLD_VBI_MD_LINE17 0x000000FF 450#define FLD_VBI_MD_LINE17 0x000000ff
451 451
452/*****************************************************************************/ 452/*****************************************************************************/
453#define VBI_FC_CFG 0x438 453#define VBI_FC_CFG 0x438
454#define FLD_FC_ALT2 0xFF000000 454#define FLD_FC_ALT2 0xff000000
455#define FLD_FC_ALT1 0x00FF0000 455#define FLD_FC_ALT1 0x00ff0000
456#define FLD_FC_ALT2_TYPE 0x0000F000 456#define FLD_FC_ALT2_TYPE 0x0000f000
457#define FLD_FC_ALT1_TYPE 0x00000F00 457#define FLD_FC_ALT1_TYPE 0x00000f00
458/* Reserved [7:1] */ 458/* Reserved [7:1] */
459#define FLD_FC_SEARCH_MODE 0x00000001 459#define FLD_FC_SEARCH_MODE 0x00000001
460 460
461/*****************************************************************************/ 461/*****************************************************************************/
462#define VBI_MISC_CFG1 0x43C 462#define VBI_MISC_CFG1 0x43c
463#define FLD_TTX_PKTADRU 0xFFF00000 463#define FLD_TTX_PKTADRU 0xfff00000
464#define FLD_TTX_PKTADRL 0x000FFF00 464#define FLD_TTX_PKTADRL 0x000fff00
465/* Reserved [7:6] */ 465/* Reserved [7:6] */
466#define FLD_MOJI_PACK_DIS 0x00000020 466#define FLD_MOJI_PACK_DIS 0x00000020
467#define FLD_VPS_DEC_DIS 0x00000010 467#define FLD_VPS_DEC_DIS 0x00000010
468#define FLD_CRI_MARG_SCALE 0x0000000C 468#define FLD_CRI_MARG_SCALE 0x0000000c
469#define FLD_EDGE_RESYNC_EN 0x00000002 469#define FLD_EDGE_RESYNC_EN 0x00000002
470#define FLD_ADAPT_SLICE_DIS 0x00000001 470#define FLD_ADAPT_SLICE_DIS 0x00000001
471 471
472/*****************************************************************************/ 472/*****************************************************************************/
473#define VBI_MISC_CFG2 0x440 473#define VBI_MISC_CFG2 0x440
474#define FLD_HAMMING_TYPE 0x0F000000 474#define FLD_HAMMING_TYPE 0x0f000000
475/* Reserved [23:20] */ 475/* Reserved [23:20] */
476#define FLD_WSS_FIFO_RST 0x00080000 476#define FLD_WSS_FIFO_RST 0x00080000
477#define FLD_GS2_FIFO_RST 0x00040000 477#define FLD_GS2_FIFO_RST 0x00040000
478#define FLD_GS1_FIFO_RST 0x00020000 478#define FLD_GS1_FIFO_RST 0x00020000
479#define FLD_CC_FIFO_RST 0x00010000 479#define FLD_CC_FIFO_RST 0x00010000
480/* Reserved [15:12] */ 480/* Reserved [15:12] */
481#define FLD_VBI3_SDID 0x00000F00 481#define FLD_VBI3_SDID 0x00000f00
482#define FLD_VBI2_SDID 0x000000F0 482#define FLD_VBI2_SDID 0x000000f0
483#define FLD_VBI1_SDID 0x0000000F 483#define FLD_VBI1_SDID 0x0000000f
484 484
485/*****************************************************************************/ 485/*****************************************************************************/
486#define VBI_PAY1 0x444 486#define VBI_PAY1 0x444
@@ -491,95 +491,95 @@
491 491
492/*****************************************************************************/ 492/*****************************************************************************/
493#define VBI_PAY2 0x448 493#define VBI_PAY2 0x448
494#define FLD_WSS_FIFO_DAT 0xFF000000 494#define FLD_WSS_FIFO_DAT 0xff000000
495#define FLD_WSS_STAT 0x00FF0000 495#define FLD_WSS_STAT 0x00ff0000
496#define FLD_GS2_FIFO_DAT 0x0000FF00 496#define FLD_GS2_FIFO_DAT 0x0000ff00
497#define FLD_GS2_STAT 0x000000FF 497#define FLD_GS2_STAT 0x000000ff
498 498
499/*****************************************************************************/ 499/*****************************************************************************/
500#define VBI_CUST1_CFG1 0x44C 500#define VBI_CUST1_CFG1 0x44c
501/* Reserved [31] */ 501/* Reserved [31] */
502#define FLD_VBI1_CRIWIN 0x7F000000 502#define FLD_VBI1_CRIWIN 0x7f000000
503#define FLD_VBI1_SLICE_DIST 0x00F00000 503#define FLD_VBI1_SLICE_DIST 0x00f00000
504#define FLD_VBI1_BITINC 0x000FFF00 504#define FLD_VBI1_BITINC 0x000fff00
505#define FLD_VBI1_HDELAY 0x000000FF 505#define FLD_VBI1_HDELAY 0x000000ff
506 506
507/*****************************************************************************/ 507/*****************************************************************************/
508#define VBI_CUST1_CFG2 0x450 508#define VBI_CUST1_CFG2 0x450
509#define FLD_VBI1_FC_LENGTH 0x1F000000 509#define FLD_VBI1_FC_LENGTH 0x1f000000
510#define FLD_VBI1_FRAME_CODE 0x00FFFFFF 510#define FLD_VBI1_FRAME_CODE 0x00ffffff
511 511
512/*****************************************************************************/ 512/*****************************************************************************/
513#define VBI_CUST1_CFG3 0x454 513#define VBI_CUST1_CFG3 0x454
514#define FLD_VBI1_HAM_EN 0x80000000 514#define FLD_VBI1_HAM_EN 0x80000000
515#define FLD_VBI1_FIFO_MODE 0x70000000 515#define FLD_VBI1_FIFO_MODE 0x70000000
516#define FLD_VBI1_FORMAT_TYPE 0x0F000000 516#define FLD_VBI1_FORMAT_TYPE 0x0f000000
517#define FLD_VBI1_PAYLD_LENGTH 0x00FF0000 517#define FLD_VBI1_PAYLD_LENGTH 0x00ff0000
518#define FLD_VBI1_CRI_LENGTH 0x0000F000 518#define FLD_VBI1_CRI_LENGTH 0x0000f000
519#define FLD_VBI1_CRI_MARGIN 0x00000F00 519#define FLD_VBI1_CRI_MARGIN 0x00000f00
520#define FLD_VBI1_CRI_TIME 0x000000FF 520#define FLD_VBI1_CRI_TIME 0x000000ff
521 521
522/*****************************************************************************/ 522/*****************************************************************************/
523#define VBI_CUST2_CFG1 0x458 523#define VBI_CUST2_CFG1 0x458
524/* Reserved [31] */ 524/* Reserved [31] */
525#define FLD_VBI2_CRIWIN 0x7F000000 525#define FLD_VBI2_CRIWIN 0x7f000000
526#define FLD_VBI2_SLICE_DIST 0x00F00000 526#define FLD_VBI2_SLICE_DIST 0x00f00000
527#define FLD_VBI2_BITINC 0x000FFF00 527#define FLD_VBI2_BITINC 0x000fff00
528#define FLD_VBI2_HDELAY 0x000000FF 528#define FLD_VBI2_HDELAY 0x000000ff
529 529
530/*****************************************************************************/ 530/*****************************************************************************/
531#define VBI_CUST2_CFG2 0x45C 531#define VBI_CUST2_CFG2 0x45c
532#define FLD_VBI2_FC_LENGTH 0x1F000000 532#define FLD_VBI2_FC_LENGTH 0x1f000000
533#define FLD_VBI2_FRAME_CODE 0x00FFFFFF 533#define FLD_VBI2_FRAME_CODE 0x00ffffff
534 534
535/*****************************************************************************/ 535/*****************************************************************************/
536#define VBI_CUST2_CFG3 0x460 536#define VBI_CUST2_CFG3 0x460
537#define FLD_VBI2_HAM_EN 0x80000000 537#define FLD_VBI2_HAM_EN 0x80000000
538#define FLD_VBI2_FIFO_MODE 0x70000000 538#define FLD_VBI2_FIFO_MODE 0x70000000
539#define FLD_VBI2_FORMAT_TYPE 0x0F000000 539#define FLD_VBI2_FORMAT_TYPE 0x0f000000
540#define FLD_VBI2_PAYLD_LENGTH 0x00FF0000 540#define FLD_VBI2_PAYLD_LENGTH 0x00ff0000
541#define FLD_VBI2_CRI_LENGTH 0x0000F000 541#define FLD_VBI2_CRI_LENGTH 0x0000f000
542#define FLD_VBI2_CRI_MARGIN 0x00000F00 542#define FLD_VBI2_CRI_MARGIN 0x00000f00
543#define FLD_VBI2_CRI_TIME 0x000000FF 543#define FLD_VBI2_CRI_TIME 0x000000ff
544 544
545/*****************************************************************************/ 545/*****************************************************************************/
546#define VBI_CUST3_CFG1 0x464 546#define VBI_CUST3_CFG1 0x464
547/* Reserved [31] */ 547/* Reserved [31] */
548#define FLD_VBI3_CRIWIN 0x7F000000 548#define FLD_VBI3_CRIWIN 0x7f000000
549#define FLD_VBI3_SLICE_DIST 0x00F00000 549#define FLD_VBI3_SLICE_DIST 0x00f00000
550#define FLD_VBI3_BITINC 0x000FFF00 550#define FLD_VBI3_BITINC 0x000fff00
551#define FLD_VBI3_HDELAY 0x000000FF 551#define FLD_VBI3_HDELAY 0x000000ff
552 552
553/*****************************************************************************/ 553/*****************************************************************************/
554#define VBI_CUST3_CFG2 0x468 554#define VBI_CUST3_CFG2 0x468
555#define FLD_VBI3_FC_LENGTH 0x1F000000 555#define FLD_VBI3_FC_LENGTH 0x1f000000
556#define FLD_VBI3_FRAME_CODE 0x00FFFFFF 556#define FLD_VBI3_FRAME_CODE 0x00ffffff
557 557
558/*****************************************************************************/ 558/*****************************************************************************/
559#define VBI_CUST3_CFG3 0x46C 559#define VBI_CUST3_CFG3 0x46c
560#define FLD_VBI3_HAM_EN 0x80000000 560#define FLD_VBI3_HAM_EN 0x80000000
561#define FLD_VBI3_FIFO_MODE 0x70000000 561#define FLD_VBI3_FIFO_MODE 0x70000000
562#define FLD_VBI3_FORMAT_TYPE 0x0F000000 562#define FLD_VBI3_FORMAT_TYPE 0x0f000000
563#define FLD_VBI3_PAYLD_LENGTH 0x00FF0000 563#define FLD_VBI3_PAYLD_LENGTH 0x00ff0000
564#define FLD_VBI3_CRI_LENGTH 0x0000F000 564#define FLD_VBI3_CRI_LENGTH 0x0000f000
565#define FLD_VBI3_CRI_MARGIN 0x00000F00 565#define FLD_VBI3_CRI_MARGIN 0x00000f00
566#define FLD_VBI3_CRI_TIME 0x000000FF 566#define FLD_VBI3_CRI_TIME 0x000000ff
567 567
568/*****************************************************************************/ 568/*****************************************************************************/
569#define HORIZ_TIM_CTRL 0x470 569#define HORIZ_TIM_CTRL 0x470
570#define FLD_BGDEL_CNT 0xFF000000 570#define FLD_BGDEL_CNT 0xff000000
571/* Reserved [23:22] */ 571/* Reserved [23:22] */
572#define FLD_HACTIVE_CNT 0x003FF000 572#define FLD_HACTIVE_CNT 0x003ff000
573/* Reserved [11:10] */ 573/* Reserved [11:10] */
574#define FLD_HBLANK_CNT 0x000003FF 574#define FLD_HBLANK_CNT 0x000003ff
575 575
576/*****************************************************************************/ 576/*****************************************************************************/
577#define VERT_TIM_CTRL 0x474 577#define VERT_TIM_CTRL 0x474
578#define FLD_V656BLANK_CNT 0xFF000000 578#define FLD_V656BLANK_CNT 0xff000000
579/* Reserved [23:22] */ 579/* Reserved [23:22] */
580#define FLD_VACTIVE_CNT 0x003FF000 580#define FLD_VACTIVE_CNT 0x003ff000
581/* Reserved [11:10] */ 581/* Reserved [11:10] */
582#define FLD_VBLANK_CNT 0x000003FF 582#define FLD_VBLANK_CNT 0x000003ff
583 583
584/*****************************************************************************/ 584/*****************************************************************************/
585#define SRC_COMB_CFG 0x478 585#define SRC_COMB_CFG 0x478
@@ -591,36 +591,36 @@
591#define FLD_LCOMB_3LN_EN 0x04000000 591#define FLD_LCOMB_3LN_EN 0x04000000
592#define FLD_LCOMB_2LN_EN 0x02000000 592#define FLD_LCOMB_2LN_EN 0x02000000
593#define FLD_LCOMB_3D_EN 0x01000000 593#define FLD_LCOMB_3D_EN 0x01000000
594#define FLD_LUMA_LPF_SEL 0x00C00000 594#define FLD_LUMA_LPF_SEL 0x00c00000
595#define FLD_UV_LPF_SEL 0x00300000 595#define FLD_UV_LPF_SEL 0x00300000
596#define FLD_BLEND_SLOPE 0x000F0000 596#define FLD_BLEND_SLOPE 0x000f0000
597#define FLD_CCOMB_REDUCE_EN 0x00008000 597#define FLD_CCOMB_REDUCE_EN 0x00008000
598/* Reserved [14:10] */ 598/* Reserved [14:10] */
599#define FLD_SRC_DECIM_RATIO 0x000003FF 599#define FLD_SRC_DECIM_RATIO 0x000003ff
600 600
601/*****************************************************************************/ 601/*****************************************************************************/
602#define CHROMA_VBIOFF_CFG 0x47C 602#define CHROMA_VBIOFF_CFG 0x47c
603#define FLD_VBI_VOFFSET 0x1F000000 603#define FLD_VBI_VOFFSET 0x1f000000
604/* Reserved [23:20] */ 604/* Reserved [23:20] */
605#define FLD_SC_STEP 0x000FFFFF 605#define FLD_SC_STEP 0x000fffff
606 606
607/*****************************************************************************/ 607/*****************************************************************************/
608#define FIELD_COUNT 0x480 608#define FIELD_COUNT 0x480
609#define FLD_FIELD_COUNT_FLD 0x000003FF 609#define FLD_FIELD_COUNT_FLD 0x000003ff
610 610
611/*****************************************************************************/ 611/*****************************************************************************/
612#define MISC_TIM_CTRL 0x484 612#define MISC_TIM_CTRL 0x484
613#define FLD_DEBOUNCE_COUNT 0xC0000000 613#define FLD_DEBOUNCE_COUNT 0xc0000000
614#define FLD_VT_LINE_CNT_HYST 0x30000000 614#define FLD_VT_LINE_CNT_HYST 0x30000000
615/* Reserved [27] */ 615/* Reserved [27] */
616#define FLD_AFD_STAT 0x07FF0000 616#define FLD_AFD_STAT 0x07ff0000
617#define FLD_VPRES_VERT_EN 0x00008000 617#define FLD_VPRES_VERT_EN 0x00008000
618/* Reserved [14:12] */ 618/* Reserved [14:12] */
619#define FLD_HR32 0x00000800 619#define FLD_HR32 0x00000800
620#define FLD_TDALGN 0x00000400 620#define FLD_TDALGN 0x00000400
621#define FLD_TDFIELD 0x00000200 621#define FLD_TDFIELD 0x00000200
622/* Reserved [8:6] */ 622/* Reserved [8:6] */
623#define FLD_TEMPDEC 0x0000003F 623#define FLD_TEMPDEC 0x0000003f
624 624
625/*****************************************************************************/ 625/*****************************************************************************/
626#define DFE_CTRL1 0x488 626#define DFE_CTRL1 0x488
@@ -632,33 +632,33 @@
632#define FLD_CLAMP_LEVEL 0x07000000 632#define FLD_CLAMP_LEVEL 0x07000000
633/* Reserved [23:22] */ 633/* Reserved [23:22] */
634#define FLD_CLAMP_SKIP_CNT 0x00300000 634#define FLD_CLAMP_SKIP_CNT 0x00300000
635#define FLD_AGC_GAIN 0x000FFF00 635#define FLD_AGC_GAIN 0x000fff00
636/* Reserved [7:6] */ 636/* Reserved [7:6] */
637#define FLD_VGA_GAIN 0x0000003F 637#define FLD_VGA_GAIN 0x0000003f
638 638
639/*****************************************************************************/ 639/*****************************************************************************/
640#define DFE_CTRL2 0x48C 640#define DFE_CTRL2 0x48c
641#define FLD_VGA_ACQUIRE_RANGE 0x00FF0000 641#define FLD_VGA_ACQUIRE_RANGE 0x00ff0000
642#define FLD_VGA_TRACK_RANGE 0x0000FF00 642#define FLD_VGA_TRACK_RANGE 0x0000ff00
643#define FLD_VGA_SYNC 0x000000FF 643#define FLD_VGA_SYNC 0x000000ff
644 644
645/*****************************************************************************/ 645/*****************************************************************************/
646#define DFE_CTRL3 0x490 646#define DFE_CTRL3 0x490
647#define FLD_BP_PERCENT 0xFF000000 647#define FLD_BP_PERCENT 0xff000000
648#define FLD_DFT_THRESHOLD 0x00FF0000 648#define FLD_DFT_THRESHOLD 0x00ff0000
649/* Reserved [15:12] */ 649/* Reserved [15:12] */
650#define FLD_SYNC_WIDTH_SEL 0x00000600 650#define FLD_SYNC_WIDTH_SEL 0x00000600
651#define FLD_BP_LOOP_GAIN 0x00000300 651#define FLD_BP_LOOP_GAIN 0x00000300
652#define FLD_SYNC_LOOP_GAIN 0x000000C0 652#define FLD_SYNC_LOOP_GAIN 0x000000c0
653/* Reserved [5:4] */ 653/* Reserved [5:4] */
654#define FLD_AGC_LOOP_GAIN 0x0000000C 654#define FLD_AGC_LOOP_GAIN 0x0000000c
655#define FLD_DCC_LOOP_GAIN 0x00000003 655#define FLD_DCC_LOOP_GAIN 0x00000003
656 656
657/*****************************************************************************/ 657/*****************************************************************************/
658#define PLL_CTRL 0x494 658#define PLL_CTRL 0x494
659#define FLD_PLL_KD 0xFF000000 659#define FLD_PLL_KD 0xff000000
660#define FLD_PLL_KI 0x00FF0000 660#define FLD_PLL_KI 0x00ff0000
661#define FLD_PLL_MAX_OFFSET 0x0000FFFF 661#define FLD_PLL_MAX_OFFSET 0x0000ffff
662 662
663/*****************************************************************************/ 663/*****************************************************************************/
664#define HTL_CTRL 0x498 664#define HTL_CTRL 0x498
@@ -667,29 +667,29 @@
667#define FLD_MAN_FAST_LOCK 0x00040000 667#define FLD_MAN_FAST_LOCK 0x00040000
668#define FLD_HTL_15K_EN 0x00020000 668#define FLD_HTL_15K_EN 0x00020000
669#define FLD_HTL_500K_EN 0x00010000 669#define FLD_HTL_500K_EN 0x00010000
670#define FLD_HTL_KD 0x0000FF00 670#define FLD_HTL_KD 0x0000ff00
671#define FLD_HTL_KI 0x000000FF 671#define FLD_HTL_KI 0x000000ff
672 672
673/*****************************************************************************/ 673/*****************************************************************************/
674#define COMB_CTRL 0x49C 674#define COMB_CTRL 0x49c
675#define FLD_COMB_PHASE_LIMIT 0xFF000000 675#define FLD_COMB_PHASE_LIMIT 0xff000000
676#define FLD_CCOMB_ERR_LIMIT 0x00FF0000 676#define FLD_CCOMB_ERR_LIMIT 0x00ff0000
677#define FLD_LUMA_THRESHOLD 0x0000FF00 677#define FLD_LUMA_THRESHOLD 0x0000ff00
678#define FLD_LCOMB_ERR_LIMIT 0x000000FF 678#define FLD_LCOMB_ERR_LIMIT 0x000000ff
679 679
680/*****************************************************************************/ 680/*****************************************************************************/
681#define CRUSH_CTRL 0x4A0 681#define CRUSH_CTRL 0x4a0
682#define FLD_WTW_EN 0x00400000 682#define FLD_WTW_EN 0x00400000
683#define FLD_CRUSH_FREQ 0x00200000 683#define FLD_CRUSH_FREQ 0x00200000
684#define FLD_MAJ_SEL_EN 0x00100000 684#define FLD_MAJ_SEL_EN 0x00100000
685#define FLD_MAJ_SEL 0x000C0000 685#define FLD_MAJ_SEL 0x000c0000
686/* Reserved [17:15] */ 686/* Reserved [17:15] */
687#define FLD_SYNC_TIP_REDUCE 0x00007E00 687#define FLD_SYNC_TIP_REDUCE 0x00007e00
688/* Reserved [8:6] */ 688/* Reserved [8:6] */
689#define FLD_SYNC_TIP_INC 0x0000003F 689#define FLD_SYNC_TIP_INC 0x0000003f
690 690
691/*****************************************************************************/ 691/*****************************************************************************/
692#define SOFT_RST_CTRL 0x4A4 692#define SOFT_RST_CTRL 0x4a4
693#define FLD_VD_SOFT_RST 0x00008000 693#define FLD_VD_SOFT_RST 0x00008000
694/* Reserved [14:12] */ 694/* Reserved [14:12] */
695#define FLD_REG_RST_MSK 0x00000800 695#define FLD_REG_RST_MSK 0x00000800
@@ -706,22 +706,22 @@
706/* Reserved [0] */ 706/* Reserved [0] */
707 707
708/*****************************************************************************/ 708/*****************************************************************************/
709#define MV_DT_CTRL1 0x4A8 709#define MV_DT_CTRL1 0x4a8
710/* Reserved [31:29] */ 710/* Reserved [31:29] */
711#define FLD_PSP_STOP_LINE 0x1F000000 711#define FLD_PSP_STOP_LINE 0x1f000000
712/* Reserved [23:21] */ 712/* Reserved [23:21] */
713#define FLD_PSP_STRT_LINE 0x001F0000 713#define FLD_PSP_STRT_LINE 0x001f0000
714/* Reserved [15] */ 714/* Reserved [15] */
715#define FLD_PSP_LLIMW 0x00007F00 715#define FLD_PSP_LLIMW 0x00007f00
716/* Reserved [7] */ 716/* Reserved [7] */
717#define FLD_PSP_ULIMW 0x0000007F 717#define FLD_PSP_ULIMW 0x0000007f
718 718
719/*****************************************************************************/ 719/*****************************************************************************/
720#define MV_DT_CTRL2 0x4AC 720#define MV_DT_CTRL2 0x4aC
721#define FLD_CS_STOPWIN 0xFF000000 721#define FLD_CS_STOPWIN 0xff000000
722#define FLD_CS_STRTWIN 0x00FF0000 722#define FLD_CS_STRTWIN 0x00ff0000
723#define FLD_CS_WIDTH 0x0000FF00 723#define FLD_CS_WIDTH 0x0000ff00
724#define FLD_PSP_SPEC_VAL 0x000000FF 724#define FLD_PSP_SPEC_VAL 0x000000ff
725 725
726/*****************************************************************************/ 726/*****************************************************************************/
727#define MV_DT_CTRL3 0x4B0 727#define MV_DT_CTRL3 0x4B0
@@ -733,47 +733,47 @@
733#define FLD_CS_ATHRESH_SEL 0x04000000 733#define FLD_CS_ATHRESH_SEL 0x04000000
734#define FLD_PSP_SPEC_SEL 0x02000000 734#define FLD_PSP_SPEC_SEL 0x02000000
735#define FLD_PSP_LINES_SEL 0x01000000 735#define FLD_PSP_LINES_SEL 0x01000000
736#define FLD_FIELD_CNT 0x00F00000 736#define FLD_FIELD_CNT 0x00f00000
737#define FLD_CS_TYPE2_CNT 0x000FC000 737#define FLD_CS_TYPE2_CNT 0x000fc000
738#define FLD_CS_LINE_CNT 0x00003F00 738#define FLD_CS_LINE_CNT 0x00003f00
739#define FLD_CS_ATHRESH_LEV 0x000000FF 739#define FLD_CS_ATHRESH_LEV 0x000000ff
740 740
741/*****************************************************************************/ 741/*****************************************************************************/
742#define CHIP_VERSION 0x4B4 742#define CHIP_VERSION 0x4b4
743/* Cx231xx redefine */ 743/* Cx231xx redefine */
744#define VERSION 0x4B4 744#define VERSION 0x4b4
745#define FLD_REV_ID 0x000000FF 745#define FLD_REV_ID 0x000000ff
746 746
747/*****************************************************************************/ 747/*****************************************************************************/
748#define MISC_DIAG_CTRL 0x4B8 748#define MISC_DIAG_CTRL 0x4b8
749/* Reserved [31:24] */ 749/* Reserved [31:24] */
750#define FLD_SC_CONVERGE_THRESH 0x00FF0000 750#define FLD_SC_CONVERGE_THRESH 0x00ff0000
751#define FLD_CCOMB_ERR_LIMIT_3D 0x0000FF00 751#define FLD_CCOMB_ERR_LIMIT_3D 0x0000ff00
752#define FLD_LCOMB_ERR_LIMIT_3D 0x000000FF 752#define FLD_LCOMB_ERR_LIMIT_3D 0x000000ff
753 753
754/*****************************************************************************/ 754/*****************************************************************************/
755#define VBI_PASS_CTRL 0x4BC 755#define VBI_PASS_CTRL 0x4bc
756#define FLD_VBI_PASS_MD 0x00200000 756#define FLD_VBI_PASS_MD 0x00200000
757#define FLD_VBI_SETUP_DIS 0x00100000 757#define FLD_VBI_SETUP_DIS 0x00100000
758#define FLD_PASS_LINE_CTRL 0x000FFFFF 758#define FLD_PASS_LINE_CTRL 0x000fffff
759 759
760/*****************************************************************************/ 760/*****************************************************************************/
761/* Cx231xx redefine */ 761/* Cx231xx redefine */
762#define VCR_DET_CTRL 0x4c0 762#define VCR_DET_CTRL 0x4c0
763#define FLD_EN_FIELD_PHASE_DET 0x80000000 763#define FLD_EN_FIELD_PHASE_DET 0x80000000
764#define FLD_EN_HEAD_SW_DET 0x40000000 764#define FLD_EN_HEAD_SW_DET 0x40000000
765#define FLD_FIELD_PHASE_LENGTH 0x01FF0000 765#define FLD_FIELD_PHASE_LENGTH 0x01ff0000
766/* Reserved [29:25] */ 766/* Reserved [29:25] */
767#define FLD_FIELD_PHASE_DELAY 0x0000FF00 767#define FLD_FIELD_PHASE_DELAY 0x0000ff00
768#define FLD_FIELD_PHASE_LIMIT 0x000000F0 768#define FLD_FIELD_PHASE_LIMIT 0x000000f0
769#define FLD_HEAD_SW_DET_LIMIT 0x0000000F 769#define FLD_HEAD_SW_DET_LIMIT 0x0000000f
770 770
771/*****************************************************************************/ 771/*****************************************************************************/
772#define DL_CTL 0x800 772#define DL_CTL 0x800
773#define DL_CTL_ADDRESS_LOW 0x800 /* Byte 1 in DL_CTL */ 773#define DL_CTL_ADDRESS_LOW 0x800 /* Byte 1 in DL_CTL */
774#define DL_CTL_ADDRESS_HIGH 0x801 /* Byte 2 in DL_CTL */ 774#define DL_CTL_ADDRESS_HIGH 0x801 /* Byte 2 in DL_CTL */
775#define DL_CTL_DATA 0x802 /* Byte 3 in DL_CTL */ 775#define DL_CTL_DATA 0x802 /* Byte 3 in DL_CTL */
776#define DL_CTL_CONTROL 0x803 /* Byte 4 in DL_CTL */ 776#define DL_CTL_CONTROL 0x803 /* Byte 4 in DL_CTL */
777/* Reserved [31:5] */ 777/* Reserved [31:5] */
778#define FLD_START_8051 0x10000000 778#define FLD_START_8051 0x10000000
779#define FLD_DL_ENABLE 0x08000000 779#define FLD_DL_ENABLE 0x08000000
@@ -782,28 +782,28 @@
782 782
783/*****************************************************************************/ 783/*****************************************************************************/
784#define STD_DET_STATUS 0x804 784#define STD_DET_STATUS 0x804
785#define FLD_SPARE_STATUS1 0xFF000000 785#define FLD_SPARE_STATUS1 0xff000000
786#define FLD_SPARE_STATUS0 0x00FF0000 786#define FLD_SPARE_STATUS0 0x00ff0000
787#define FLD_MOD_DET_STATUS1 0x0000FF00 787#define FLD_MOD_DET_STATUS1 0x0000ff00
788#define FLD_MOD_DET_STATUS0 0x000000FF 788#define FLD_MOD_DET_STATUS0 0x000000ff
789 789
790/*****************************************************************************/ 790/*****************************************************************************/
791#define AUD_BUILD_NUM 0x806 791#define AUD_BUILD_NUM 0x806
792#define AUD_VER_NUM 0x807 792#define AUD_VER_NUM 0x807
793#define STD_DET_CTL 0x808 793#define STD_DET_CTL 0x808
794#define STD_DET_CTL_AUD_CTL 0x808 /* Byte 1 in STD_DET_CTL */ 794#define STD_DET_CTL_AUD_CTL 0x808 /* Byte 1 in STD_DET_CTL */
795#define STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */ 795#define STD_DET_CTL_PREF_MODE 0x809 /* Byte 2 in STD_DET_CTL */
796#define FLD_SPARE_CTL0 0xFF000000 796#define FLD_SPARE_CTL0 0xff000000
797#define FLD_DIS_DBX 0x00800000 797#define FLD_DIS_DBX 0x00800000
798#define FLD_DIS_BTSC 0x00400000 798#define FLD_DIS_BTSC 0x00400000
799#define FLD_DIS_NICAM_A2 0x00200000 799#define FLD_DIS_NICAM_A2 0x00200000
800#define FLD_VIDEO_PRESENT 0x00100000 800#define FLD_VIDEO_PRESENT 0x00100000
801#define FLD_DW8051_VIDEO_FORMAT 0x000F0000 801#define FLD_DW8051_VIDEO_FORMAT 0x000f0000
802#define FLD_PREF_DEC_MODE 0x0000FF00 802#define FLD_PREF_DEC_MODE 0x0000ff00
803#define FLD_AUD_CONFIG 0x000000FF 803#define FLD_AUD_CONFIG 0x000000ff
804 804
805/*****************************************************************************/ 805/*****************************************************************************/
806#define DW8051_INT 0x80C 806#define DW8051_INT 0x80c
807#define FLD_VIDEO_PRESENT_CHANGE 0x80000000 807#define FLD_VIDEO_PRESENT_CHANGE 0x80000000
808#define FLD_VIDEO_CHANGE 0x40000000 808#define FLD_VIDEO_CHANGE 0x40000000
809#define FLD_RDS_READY 0x20000000 809#define FLD_RDS_READY 0x20000000
@@ -854,7 +854,7 @@
854#define FLD_FC_INT_DIS 0x00040000 854#define FLD_FC_INT_DIS 0x00040000
855#define FLD_AMC_INT_DIS 0x00020000 855#define FLD_AMC_INT_DIS 0x00020000
856#define FLD_AC97_INT_DIS 0x00010000 856#define FLD_AC97_INT_DIS 0x00010000
857#define FLD_REV_NUM 0x0000FF00 857#define FLD_REV_NUM 0x0000ff00
858/* Reserved [7:5] */ 858/* Reserved [7:5] */
859#define FLD_DBX_SOFT_RESET_REG 0x00000010 859#define FLD_DBX_SOFT_RESET_REG 0x00000010
860#define FLD_AD_SOFT_RESET_REG 0x00000008 860#define FLD_AD_SOFT_RESET_REG 0x00000008
@@ -866,14 +866,14 @@
866#define AAGC_CTL 0x814 866#define AAGC_CTL 0x814
867#define FLD_AFE_12DB_EN 0x80000000 867#define FLD_AFE_12DB_EN 0x80000000
868#define FLD_AAGC_DEFAULT_EN 0x40000000 868#define FLD_AAGC_DEFAULT_EN 0x40000000
869#define FLD_AAGC_DEFAULT 0x3F000000 869#define FLD_AAGC_DEFAULT 0x3f000000
870/* Reserved [23] */ 870/* Reserved [23] */
871#define FLD_AAGC_GAIN 0x00600000 871#define FLD_AAGC_GAIN 0x00600000
872#define FLD_AAGC_TH 0x001F0000 872#define FLD_AAGC_TH 0x001f0000
873/* Reserved [15:14] */ 873/* Reserved [15:14] */
874#define FLD_AAGC_HYST2 0x00003F00 874#define FLD_AAGC_HYST2 0x00003f00
875/* Reserved [7:6] */ 875/* Reserved [7:6] */
876#define FLD_AAGC_HYST1 0x0000003F 876#define FLD_AAGC_HYST1 0x0000003f
877 877
878/*****************************************************************************/ 878/*****************************************************************************/
879#define IF_SRC_CTL 0x818 879#define IF_SRC_CTL 0x818
@@ -881,16 +881,16 @@
881/* Reserved [30:25] */ 881/* Reserved [30:25] */
882#define FLD_IF_SRC_MODE 0x01000000 882#define FLD_IF_SRC_MODE 0x01000000
883/* Reserved [23:18] */ 883/* Reserved [23:18] */
884#define FLD_IF_SRC_PHASE_INC 0x0001FFFF 884#define FLD_IF_SRC_PHASE_INC 0x0001ffff
885 885
886/*****************************************************************************/ 886/*****************************************************************************/
887#define ANALOG_DEMOD_CTL 0x81C 887#define ANALOG_DEMOD_CTL 0x81c
888#define FLD_ROT1_PHACC_PROG 0xFFFF0000 888#define FLD_ROT1_PHACC_PROG 0xffff0000
889/* Reserved [15] */ 889/* Reserved [15] */
890#define FLD_FM1_DELAY_FIX 0x00007000 890#define FLD_FM1_DELAY_FIX 0x00007000
891#define FLD_PDF4_SHIFT 0x00000C00 891#define FLD_PDF4_SHIFT 0x00000c00
892#define FLD_PDF3_SHIFT 0x00000300 892#define FLD_PDF3_SHIFT 0x00000300
893#define FLD_PDF2_SHIFT 0x000000C0 893#define FLD_PDF2_SHIFT 0x000000c0
894#define FLD_PDF1_SHIFT 0x00000030 894#define FLD_PDF1_SHIFT 0x00000030
895#define FLD_FMBYPASS_MODE2 0x00000008 895#define FLD_FMBYPASS_MODE2 0x00000008
896#define FLD_FMBYPASS_MODE1 0x00000004 896#define FLD_FMBYPASS_MODE1 0x00000004
@@ -899,19 +899,19 @@
899 899
900/*****************************************************************************/ 900/*****************************************************************************/
901#define ROT_FREQ_CTL 0x820 901#define ROT_FREQ_CTL 0x820
902#define FLD_ROT3_PHACC_PROG 0xFFFF0000 902#define FLD_ROT3_PHACC_PROG 0xffff0000
903#define FLD_ROT2_PHACC_PROG 0x0000FFFF 903#define FLD_ROT2_PHACC_PROG 0x0000ffff
904 904
905/*****************************************************************************/ 905/*****************************************************************************/
906#define FM_CTL 0x824 906#define FM_CTL 0x824
907#define FLD_FM2_DC_FB_SHIFT 0xF0000000 907#define FLD_FM2_DC_FB_SHIFT 0xf0000000
908#define FLD_FM2_DC_INT_SHIFT 0x0F000000 908#define FLD_FM2_DC_INT_SHIFT 0x0f000000
909#define FLD_FM2_AFC_RESET 0x00800000 909#define FLD_FM2_AFC_RESET 0x00800000
910#define FLD_FM2_DC_PASS_IN 0x00400000 910#define FLD_FM2_DC_PASS_IN 0x00400000
911#define FLD_FM2_DAGC_SHIFT 0x00380000 911#define FLD_FM2_DAGC_SHIFT 0x00380000
912#define FLD_FM2_CORDIC_SHIFT 0x00070000 912#define FLD_FM2_CORDIC_SHIFT 0x00070000
913#define FLD_FM1_DC_FB_SHIFT 0x0000F000 913#define FLD_FM1_DC_FB_SHIFT 0x0000f000
914#define FLD_FM1_DC_INT_SHIFT 0x00000F00 914#define FLD_FM1_DC_INT_SHIFT 0x00000f00
915#define FLD_FM1_AFC_RESET 0x00000080 915#define FLD_FM1_AFC_RESET 0x00000080
916#define FLD_FM1_DC_PASS_IN 0x00000040 916#define FLD_FM1_DC_PASS_IN 0x00000040
917#define FLD_FM1_DAGC_SHIFT 0x00000038 917#define FLD_FM1_DAGC_SHIFT 0x00000038
@@ -921,29 +921,29 @@
921#define LPF_PDF_CTL 0x828 921#define LPF_PDF_CTL 0x828
922/* Reserved [31:30] */ 922/* Reserved [31:30] */
923#define FLD_LPF32_SHIFT1 0x30000000 923#define FLD_LPF32_SHIFT1 0x30000000
924#define FLD_LPF32_SHIFT2 0x0C000000 924#define FLD_LPF32_SHIFT2 0x0c000000
925#define FLD_LPF160_SHIFTA 0x03000000 925#define FLD_LPF160_SHIFTA 0x03000000
926#define FLD_LPF160_SHIFTB 0x00C00000 926#define FLD_LPF160_SHIFTB 0x00c00000
927#define FLD_LPF160_SHIFTC 0x00300000 927#define FLD_LPF160_SHIFTC 0x00300000
928#define FLD_LPF32_COEF_SEL2 0x000C0000 928#define FLD_LPF32_COEF_SEL2 0x000c0000
929#define FLD_LPF32_COEF_SEL1 0x00030000 929#define FLD_LPF32_COEF_SEL1 0x00030000
930#define FLD_LPF160_COEF_SELC 0x0000C000 930#define FLD_LPF160_COEF_SELC 0x0000c000
931#define FLD_LPF160_COEF_SELB 0x00003000 931#define FLD_LPF160_COEF_SELB 0x00003000
932#define FLD_LPF160_COEF_SELA 0x00000C00 932#define FLD_LPF160_COEF_SELA 0x00000c00
933#define FLD_LPF160_IN_EN_REG 0x00000300 933#define FLD_LPF160_IN_EN_REG 0x00000300
934#define FLD_PDF4_PDF_SEL 0x000000C0 934#define FLD_PDF4_PDF_SEL 0x000000c0
935#define FLD_PDF3_PDF_SEL 0x00000030 935#define FLD_PDF3_PDF_SEL 0x00000030
936#define FLD_PDF2_PDF_SEL 0x0000000C 936#define FLD_PDF2_PDF_SEL 0x0000000c
937#define FLD_PDF1_PDF_SEL 0x00000003 937#define FLD_PDF1_PDF_SEL 0x00000003
938 938
939/*****************************************************************************/ 939/*****************************************************************************/
940#define DFT1_CTL1 0x82C 940#define DFT1_CTL1 0x82c
941#define FLD_DFT1_DWELL 0xFFFF0000 941#define FLD_DFT1_DWELL 0xffff0000
942#define FLD_DFT1_FREQ 0x0000FFFF 942#define FLD_DFT1_FREQ 0x0000ffff
943 943
944/*****************************************************************************/ 944/*****************************************************************************/
945#define DFT1_CTL2 0x830 945#define DFT1_CTL2 0x830
946#define FLD_DFT1_THRESHOLD 0xFFFFFF00 946#define FLD_DFT1_THRESHOLD 0xffffff00
947#define FLD_DFT1_CMP_CTL 0x00000080 947#define FLD_DFT1_CMP_CTL 0x00000080
948#define FLD_DFT1_AVG 0x00000070 948#define FLD_DFT1_AVG 0x00000070
949/* Reserved [3:1] */ 949/* Reserved [3:1] */
@@ -953,16 +953,16 @@
953#define DFT1_STATUS 0x834 953#define DFT1_STATUS 0x834
954#define FLD_DFT1_DONE 0x80000000 954#define FLD_DFT1_DONE 0x80000000
955#define FLD_DFT1_TH_CMP_STAT 0x40000000 955#define FLD_DFT1_TH_CMP_STAT 0x40000000
956#define FLD_DFT1_RESULT 0x3FFFFFFF 956#define FLD_DFT1_RESULT 0x3fffffff
957 957
958/*****************************************************************************/ 958/*****************************************************************************/
959#define DFT2_CTL1 0x838 959#define DFT2_CTL1 0x838
960#define FLD_DFT2_DWELL 0xFFFF0000 960#define FLD_DFT2_DWELL 0xffff0000
961#define FLD_DFT2_FREQ 0x0000FFFF 961#define FLD_DFT2_FREQ 0x0000ffff
962 962
963/*****************************************************************************/ 963/*****************************************************************************/
964#define DFT2_CTL2 0x83C 964#define DFT2_CTL2 0x83C
965#define FLD_DFT2_THRESHOLD 0xFFFFFF00 965#define FLD_DFT2_THRESHOLD 0xffffff00
966#define FLD_DFT2_CMP_CTL 0x00000080 966#define FLD_DFT2_CMP_CTL 0x00000080
967#define FLD_DFT2_AVG 0x00000070 967#define FLD_DFT2_AVG 0x00000070
968/* Reserved [3:1] */ 968/* Reserved [3:1] */
@@ -972,35 +972,35 @@
972#define DFT2_STATUS 0x840 972#define DFT2_STATUS 0x840
973#define FLD_DFT2_DONE 0x80000000 973#define FLD_DFT2_DONE 0x80000000
974#define FLD_DFT2_TH_CMP_STAT 0x40000000 974#define FLD_DFT2_TH_CMP_STAT 0x40000000
975#define FLD_DFT2_RESULT 0x3FFFFFFF 975#define FLD_DFT2_RESULT 0x3fffffff
976 976
977/*****************************************************************************/ 977/*****************************************************************************/
978#define DFT3_CTL1 0x844 978#define DFT3_CTL1 0x844
979#define FLD_DFT3_DWELL 0xFFFF0000 979#define FLD_DFT3_DWELL 0xffff0000
980#define FLD_DFT3_FREQ 0x0000FFFF 980#define FLD_DFT3_FREQ 0x0000ffff
981 981
982/*****************************************************************************/ 982/*****************************************************************************/
983#define DFT3_CTL2 0x848 983#define DFT3_CTL2 0x848
984#define FLD_DFT3_THRESHOLD 0xFFFFFF00 984#define FLD_DFT3_THRESHOLD 0xffffff00
985#define FLD_DFT3_CMP_CTL 0x00000080 985#define FLD_DFT3_CMP_CTL 0x00000080
986#define FLD_DFT3_AVG 0x00000070 986#define FLD_DFT3_AVG 0x00000070
987/* Reserved [3:1] */ 987/* Reserved [3:1] */
988#define FLD_DFT3_START 0x00000001 988#define FLD_DFT3_START 0x00000001
989 989
990/*****************************************************************************/ 990/*****************************************************************************/
991#define DFT3_STATUS 0x84C 991#define DFT3_STATUS 0x84c
992#define FLD_DFT3_DONE 0x80000000 992#define FLD_DFT3_DONE 0x80000000
993#define FLD_DFT3_TH_CMP_STAT 0x40000000 993#define FLD_DFT3_TH_CMP_STAT 0x40000000
994#define FLD_DFT3_RESULT 0x3FFFFFFF 994#define FLD_DFT3_RESULT 0x3fffffff
995 995
996/*****************************************************************************/ 996/*****************************************************************************/
997#define DFT4_CTL1 0x850 997#define DFT4_CTL1 0x850
998#define FLD_DFT4_DWELL 0xFFFF0000 998#define FLD_DFT4_DWELL 0xffff0000
999#define FLD_DFT4_FREQ 0x0000FFFF 999#define FLD_DFT4_FREQ 0x0000ffff
1000 1000
1001/*****************************************************************************/ 1001/*****************************************************************************/
1002#define DFT4_CTL2 0x854 1002#define DFT4_CTL2 0x854
1003#define FLD_DFT4_THRESHOLD 0xFFFFFF00 1003#define FLD_DFT4_THRESHOLD 0xffffff00
1004#define FLD_DFT4_CMP_CTL 0x00000080 1004#define FLD_DFT4_CMP_CTL 0x00000080
1005#define FLD_DFT4_AVG 0x00000070 1005#define FLD_DFT4_AVG 0x00000070
1006/* Reserved [3:1] */ 1006/* Reserved [3:1] */
@@ -1010,19 +1010,19 @@
1010#define DFT4_STATUS 0x858 1010#define DFT4_STATUS 0x858
1011#define FLD_DFT4_DONE 0x80000000 1011#define FLD_DFT4_DONE 0x80000000
1012#define FLD_DFT4_TH_CMP_STAT 0x40000000 1012#define FLD_DFT4_TH_CMP_STAT 0x40000000
1013#define FLD_DFT4_RESULT 0x3FFFFFFF 1013#define FLD_DFT4_RESULT 0x3fffffff
1014 1014
1015/*****************************************************************************/ 1015/*****************************************************************************/
1016#define AM_MTS_DET 0x85C 1016#define AM_MTS_DET 0x85c
1017#define FLD_AM_MTS_MODE 0x80000000 1017#define FLD_AM_MTS_MODE 0x80000000
1018/* Reserved [30:26] */ 1018/* Reserved [30:26] */
1019#define FLD_AM_SUB 0x02000000 1019#define FLD_AM_SUB 0x02000000
1020#define FLD_AM_GAIN_EN 0x01000000 1020#define FLD_AM_GAIN_EN 0x01000000
1021/* Reserved [23:16] */ 1021/* Reserved [23:16] */
1022#define FLD_AMMTS_GAIN_SCALE 0x0000E000 1022#define FLD_AMMTS_GAIN_SCALE 0x0000e000
1023#define FLD_MTS_PDF_SHIFT 0x00001800 1023#define FLD_MTS_PDF_SHIFT 0x00001800
1024#define FLD_AM_REG_GAIN 0x00000700 1024#define FLD_AM_REG_GAIN 0x00000700
1025#define FLD_AGC_REF 0x000000FF 1025#define FLD_AGC_REF 0x000000ff
1026 1026
1027/*****************************************************************************/ 1027/*****************************************************************************/
1028#define ANALOG_MUX_CTL 0x860 1028#define ANALOG_MUX_CTL 0x860
@@ -1044,9 +1044,9 @@
1044#define FLD_MUX7_SEL 0x00000800 1044#define FLD_MUX7_SEL 0x00000800
1045#define FLD_MUX6_SEL 0x00000600 1045#define FLD_MUX6_SEL 0x00000600
1046#define FLD_MUX5_SEL 0x00000100 1046#define FLD_MUX5_SEL 0x00000100
1047#define FLD_MUX4_SEL 0x000000C0 1047#define FLD_MUX4_SEL 0x000000c0
1048#define FLD_MUX3_SEL 0x00000030 1048#define FLD_MUX3_SEL 0x00000030
1049#define FLD_MUX2_SEL 0x0000000C 1049#define FLD_MUX2_SEL 0x0000000c
1050#define FLD_MUX1_SEL 0x00000003 1050#define FLD_MUX1_SEL 0x00000003
1051 1051
1052/*****************************************************************************/ 1052/*****************************************************************************/
@@ -1057,48 +1057,48 @@
1057#define FLD_PLL_STATUS 0x07000000 1057#define FLD_PLL_STATUS 0x07000000
1058#define FLD_BANDWIDTH_SELECT 0x00030000 1058#define FLD_BANDWIDTH_SELECT 0x00030000
1059#define FLD_PLL_SHIFT_REG 0x00007000 1059#define FLD_PLL_SHIFT_REG 0x00007000
1060#define FLD_PHASE_SHIFT 0x000007FF 1060#define FLD_PHASE_SHIFT 0x000007ff
1061 1061
1062/*****************************************************************************/ 1062/*****************************************************************************/
1063/* Cx231xx redefine */ 1063/* Cx231xx redefine */
1064#define DPLL_CTRL2 0x868 1064#define DPLL_CTRL2 0x868
1065#define DIG_PLL_CTL2 0x868 1065#define DIG_PLL_CTL2 0x868
1066#define FLD_PLL_UNLOCK_THR 0xFF000000 1066#define FLD_PLL_UNLOCK_THR 0xff000000
1067#define FLD_PLL_LOCK_THR 0x00FF0000 1067#define FLD_PLL_LOCK_THR 0x00ff0000
1068/* Reserved [15:8] */ 1068/* Reserved [15:8] */
1069#define FLD_AM_PDF_SEL2 0x000000C0 1069#define FLD_AM_PDF_SEL2 0x000000c0
1070#define FLD_AM_PDF_SEL1 0x00000030 1070#define FLD_AM_PDF_SEL1 0x00000030
1071#define FLD_DPLL_FSM_CTRL 0x0000000C 1071#define FLD_DPLL_FSM_CTRL 0x0000000c
1072/* Reserved [1] */ 1072/* Reserved [1] */
1073#define FLD_PLL_PILOT_DET 0x00000001 1073#define FLD_PLL_PILOT_DET 0x00000001
1074 1074
1075/*****************************************************************************/ 1075/*****************************************************************************/
1076/* Cx231xx redefine */ 1076/* Cx231xx redefine */
1077#define DPLL_CTRL3 0x86C 1077#define DPLL_CTRL3 0x86c
1078#define DIG_PLL_CTL3 0x86C 1078#define DIG_PLL_CTL3 0x86c
1079#define FLD_DISABLE_LOOP 0x01000000 1079#define FLD_DISABLE_LOOP 0x01000000
1080#define FLD_A1_DS1_SEL 0x000C0000 1080#define FLD_A1_DS1_SEL 0x000c0000
1081#define FLD_A1_DS2_SEL 0x00030000 1081#define FLD_A1_DS2_SEL 0x00030000
1082#define FLD_A1_KI 0x0000FF00 1082#define FLD_A1_KI 0x0000ff00
1083#define FLD_A1_KD 0x000000FF 1083#define FLD_A1_KD 0x000000ff
1084 1084
1085/*****************************************************************************/ 1085/*****************************************************************************/
1086/* Cx231xx redefine */ 1086/* Cx231xx redefine */
1087#define DPLL_CTRL4 0x870 1087#define DPLL_CTRL4 0x870
1088#define DIG_PLL_CTL4 0x870 1088#define DIG_PLL_CTL4 0x870
1089#define FLD_A2_DS1_SEL 0x000C0000 1089#define FLD_A2_DS1_SEL 0x000c0000
1090#define FLD_A2_DS2_SEL 0x00030000 1090#define FLD_A2_DS2_SEL 0x00030000
1091#define FLD_A2_KI 0x0000FF00 1091#define FLD_A2_KI 0x0000ff00
1092#define FLD_A2_KD 0x000000FF 1092#define FLD_A2_KD 0x000000ff
1093 1093
1094/*****************************************************************************/ 1094/*****************************************************************************/
1095/* Cx231xx redefine */ 1095/* Cx231xx redefine */
1096#define DPLL_CTRL5 0x874 1096#define DPLL_CTRL5 0x874
1097#define DIG_PLL_CTL5 0x874 1097#define DIG_PLL_CTL5 0x874
1098#define FLD_TRK_DS1_SEL 0x000C0000 1098#define FLD_TRK_DS1_SEL 0x000c0000
1099#define FLD_TRK_DS2_SEL 0x00030000 1099#define FLD_TRK_DS2_SEL 0x00030000
1100#define FLD_TRK_KI 0x0000FF00 1100#define FLD_TRK_KI 0x0000ff00
1101#define FLD_TRK_KD 0x000000FF 1101#define FLD_TRK_KD 0x000000ff
1102 1102
1103/*****************************************************************************/ 1103/*****************************************************************************/
1104#define DEEMPH_GAIN_CTL 0x878 1104#define DEEMPH_GAIN_CTL 0x878
@@ -1107,10 +1107,10 @@
1107 1107
1108/*****************************************************************************/ 1108/*****************************************************************************/
1109/* Cx231xx redefine */ 1109/* Cx231xx redefine */
1110#define DEEMPH_COEFF1 0x87C 1110#define DEEMPH_COEFF1 0x87c
1111#define DEEMPH_COEF1 0x87C 1111#define DEEMPH_COEF1 0x87c
1112#define FLD_DEEMPH_B0 0xFFFF0000 1112#define FLD_DEEMPH_B0 0xffff0000
1113#define FLD_DEEMPH_A0 0x0000FFFF 1113#define FLD_DEEMPH_A0 0x0000ffff
1114 1114
1115/*****************************************************************************/ 1115/*****************************************************************************/
1116/* Cx231xx redefine */ 1116/* Cx231xx redefine */
@@ -1121,281 +1121,281 @@
1121 1121
1122/*****************************************************************************/ 1122/*****************************************************************************/
1123#define DBX1_CTL1 0x884 1123#define DBX1_CTL1 0x884
1124#define FLD_DBX1_WBE_GAIN 0xFFFF0000 1124#define FLD_DBX1_WBE_GAIN 0xffff0000
1125#define FLD_DBX1_IN_GAIN 0x0000FFFF 1125#define FLD_DBX1_IN_GAIN 0x0000ffff
1126 1126
1127/*****************************************************************************/ 1127/*****************************************************************************/
1128#define DBX1_CTL2 0x888 1128#define DBX1_CTL2 0x888
1129#define FLD_DBX1_SE_BYPASS 0xFFFF0000 1129#define FLD_DBX1_SE_BYPASS 0xffff0000
1130#define FLD_DBX1_SE_GAIN 0x0000FFFF 1130#define FLD_DBX1_SE_GAIN 0x0000ffff
1131 1131
1132/*****************************************************************************/ 1132/*****************************************************************************/
1133#define DBX1_RMS_SE 0x88C 1133#define DBX1_RMS_SE 0x88C
1134#define FLD_DBX1_RMS_WBE 0xFFFF0000 1134#define FLD_DBX1_RMS_WBE 0xffff0000
1135#define FLD_DBX1_RMS_SE_FLD 0x0000FFFF 1135#define FLD_DBX1_RMS_SE_FLD 0x0000ffff
1136 1136
1137/*****************************************************************************/ 1137/*****************************************************************************/
1138#define DBX2_CTL1 0x890 1138#define DBX2_CTL1 0x890
1139#define FLD_DBX2_WBE_GAIN 0xFFFF0000 1139#define FLD_DBX2_WBE_GAIN 0xffff0000
1140#define FLD_DBX2_IN_GAIN 0x0000FFFF 1140#define FLD_DBX2_IN_GAIN 0x0000ffff
1141 1141
1142/*****************************************************************************/ 1142/*****************************************************************************/
1143#define DBX2_CTL2 0x894 1143#define DBX2_CTL2 0x894
1144#define FLD_DBX2_SE_BYPASS 0xFFFF0000 1144#define FLD_DBX2_SE_BYPASS 0xffff0000
1145#define FLD_DBX2_SE_GAIN 0x0000FFFF 1145#define FLD_DBX2_SE_GAIN 0x0000ffff
1146 1146
1147/*****************************************************************************/ 1147/*****************************************************************************/
1148#define DBX2_RMS_SE 0x898 1148#define DBX2_RMS_SE 0x898
1149#define FLD_DBX2_RMS_WBE 0xFFFF0000 1149#define FLD_DBX2_RMS_WBE 0xffff0000
1150#define FLD_DBX2_RMS_SE_FLD 0x0000FFFF 1150#define FLD_DBX2_RMS_SE_FLD 0x0000ffff
1151 1151
1152/*****************************************************************************/ 1152/*****************************************************************************/
1153#define AM_FM_DIFF 0x89C 1153#define AM_FM_DIFF 0x89c
1154/* Reserved [31] */ 1154/* Reserved [31] */
1155#define FLD_FM_DIFF_OUT 0x7FFF0000 1155#define FLD_FM_DIFF_OUT 0x7fff0000
1156/* Reserved [15] */ 1156/* Reserved [15] */
1157#define FLD_AM_DIFF_OUT 0x00007FFF 1157#define FLD_AM_DIFF_OUT 0x00007fff
1158 1158
1159/*****************************************************************************/ 1159/*****************************************************************************/
1160#define NICAM_FAW 0x8A0 1160#define NICAM_FAW 0x8a0
1161#define FLD_FAWDETWINEND 0xFC000000 1161#define FLD_FAWDETWINEND 0xFc000000
1162#define FLD_FAWDETWINSTR 0x03FF0000 1162#define FLD_FAWDETWINSTR 0x03ff0000
1163/* Reserved [15:12] */ 1163/* Reserved [15:12] */
1164#define FLD_FAWDETTHRSHLD3 0x00000F00 1164#define FLD_FAWDETTHRSHLD3 0x00000f00
1165#define FLD_FAWDETTHRSHLD2 0x000000F0 1165#define FLD_FAWDETTHRSHLD2 0x000000f0
1166#define FLD_FAWDETTHRSHLD1 0x0000000F 1166#define FLD_FAWDETTHRSHLD1 0x0000000f
1167 1167
1168/*****************************************************************************/ 1168/*****************************************************************************/
1169/* Cx231xx redefine */ 1169/* Cx231xx redefine */
1170#define DEEMPH_GAIN 0x8A4 1170#define DEEMPH_GAIN 0x8a4
1171#define NICAM_DEEMPHGAIN 0x8A4 1171#define NICAM_DEEMPHGAIN 0x8a4
1172/* Reserved [31:18] */ 1172/* Reserved [31:18] */
1173#define FLD_DEEMPHGAIN 0x0003FFFF 1173#define FLD_DEEMPHGAIN 0x0003ffff
1174 1174
1175/*****************************************************************************/ 1175/*****************************************************************************/
1176/* Cx231xx redefine */ 1176/* Cx231xx redefine */
1177#define DEEMPH_NUMER1 0x8A8 1177#define DEEMPH_NUMER1 0x8a8
1178#define NICAM_DEEMPHNUMER1 0x8A8 1178#define NICAM_DEEMPHNUMER1 0x8a8
1179/* Reserved [31:18] */ 1179/* Reserved [31:18] */
1180#define FLD_DEEMPHNUMER1 0x0003FFFF 1180#define FLD_DEEMPHNUMER1 0x0003ffff
1181 1181
1182/*****************************************************************************/ 1182/*****************************************************************************/
1183/* Cx231xx redefine */ 1183/* Cx231xx redefine */
1184#define DEEMPH_NUMER2 0x8AC 1184#define DEEMPH_NUMER2 0x8ac
1185#define NICAM_DEEMPHNUMER2 0x8AC 1185#define NICAM_DEEMPHNUMER2 0x8ac
1186/* Reserved [31:18] */ 1186/* Reserved [31:18] */
1187#define FLD_DEEMPHNUMER2 0x0003FFFF 1187#define FLD_DEEMPHNUMER2 0x0003ffff
1188 1188
1189/*****************************************************************************/ 1189/*****************************************************************************/
1190/* Cx231xx redefine */ 1190/* Cx231xx redefine */
1191#define DEEMPH_DENOM1 0x8B0 1191#define DEEMPH_DENOM1 0x8b0
1192#define NICAM_DEEMPHDENOM1 0x8B0 1192#define NICAM_DEEMPHDENOM1 0x8b0
1193/* Reserved [31:18] */ 1193/* Reserved [31:18] */
1194#define FLD_DEEMPHDENOM1 0x0003FFFF 1194#define FLD_DEEMPHDENOM1 0x0003ffff
1195 1195
1196/*****************************************************************************/ 1196/*****************************************************************************/
1197/* Cx231xx redefine */ 1197/* Cx231xx redefine */
1198#define DEEMPH_DENOM2 0x8B4 1198#define DEEMPH_DENOM2 0x8b4
1199#define NICAM_DEEMPHDENOM2 0x8B4 1199#define NICAM_DEEMPHDENOM2 0x8b4
1200/* Reserved [31:18] */ 1200/* Reserved [31:18] */
1201#define FLD_DEEMPHDENOM2 0x0003FFFF 1201#define FLD_DEEMPHDENOM2 0x0003ffff
1202 1202
1203/*****************************************************************************/ 1203/*****************************************************************************/
1204#define NICAM_ERRLOG_CTL1 0x8B8 1204#define NICAM_ERRLOG_CTL1 0x8B8
1205/* Reserved [31:28] */ 1205/* Reserved [31:28] */
1206#define FLD_ERRINTRPTTHSHLD1 0x0FFF0000 1206#define FLD_ERRINTRPTTHSHLD1 0x0fff0000
1207/* Reserved [15:12] */ 1207/* Reserved [15:12] */
1208#define FLD_ERRLOGPERIOD 0x00000FFF 1208#define FLD_ERRLOGPERIOD 0x00000fff
1209 1209
1210/*****************************************************************************/ 1210/*****************************************************************************/
1211#define NICAM_ERRLOG_CTL2 0x8BC 1211#define NICAM_ERRLOG_CTL2 0x8bc
1212/* Reserved [31:28] */ 1212/* Reserved [31:28] */
1213#define FLD_ERRINTRPTTHSHLD3 0x0FFF0000 1213#define FLD_ERRINTRPTTHSHLD3 0x0fff0000
1214/* Reserved [15:12] */ 1214/* Reserved [15:12] */
1215#define FLD_ERRINTRPTTHSHLD2 0x00000FFF 1215#define FLD_ERRINTRPTTHSHLD2 0x00000fff
1216 1216
1217/*****************************************************************************/ 1217/*****************************************************************************/
1218#define NICAM_ERRLOG_STS1 0x8C0 1218#define NICAM_ERRLOG_STS1 0x8c0
1219/* Reserved [31:28] */ 1219/* Reserved [31:28] */
1220#define FLD_ERRLOG2 0x0FFF0000 1220#define FLD_ERRLOG2 0x0fff0000
1221/* Reserved [15:12] */ 1221/* Reserved [15:12] */
1222#define FLD_ERRLOG1 0x00000FFF 1222#define FLD_ERRLOG1 0x00000fff
1223 1223
1224/*****************************************************************************/ 1224/*****************************************************************************/
1225#define NICAM_ERRLOG_STS2 0x8C4 1225#define NICAM_ERRLOG_STS2 0x8c4
1226/* Reserved [31:12] */ 1226/* Reserved [31:12] */
1227#define FLD_ERRLOG3 0x00000FFF 1227#define FLD_ERRLOG3 0x00000fff
1228 1228
1229/*****************************************************************************/ 1229/*****************************************************************************/
1230#define NICAM_STATUS 0x8C8 1230#define NICAM_STATUS 0x8c8
1231/* Reserved [31:20] */ 1231/* Reserved [31:20] */
1232#define FLD_NICAM_CIB 0x000C0000 1232#define FLD_NICAM_CIB 0x000c0000
1233#define FLD_NICAM_LOCK_STAT 0x00020000 1233#define FLD_NICAM_LOCK_STAT 0x00020000
1234#define FLD_NICAM_MUTE 0x00010000 1234#define FLD_NICAM_MUTE 0x00010000
1235#define FLD_NICAMADDIT_DATA 0x0000FFE0 1235#define FLD_NICAMADDIT_DATA 0x0000ffe0
1236#define FLD_NICAMCNTRL 0x0000001F 1236#define FLD_NICAMCNTRL 0x0000001f
1237 1237
1238/*****************************************************************************/ 1238/*****************************************************************************/
1239#define DEMATRIX_CTL 0x8CC 1239#define DEMATRIX_CTL 0x8cc
1240#define FLD_AC97_IN_SHIFT 0xF0000000 1240#define FLD_AC97_IN_SHIFT 0xf0000000
1241#define FLD_I2S_IN_SHIFT 0x0F000000 1241#define FLD_I2S_IN_SHIFT 0x0f000000
1242#define FLD_DEMATRIX_SEL_CTL 0x00FF0000 1242#define FLD_DEMATRIX_SEL_CTL 0x00ff0000
1243/* Reserved [15:11] */ 1243/* Reserved [15:11] */
1244#define FLD_DMTRX_BYPASS 0x00000400 1244#define FLD_DMTRX_BYPASS 0x00000400
1245#define FLD_DEMATRIX_MODE 0x00000300 1245#define FLD_DEMATRIX_MODE 0x00000300
1246/* Reserved [7:6] */ 1246/* Reserved [7:6] */
1247#define FLD_PH_DBX_SEL 0x00000020 1247#define FLD_PH_DBX_SEL 0x00000020
1248#define FLD_PH_CH_SEL 0x00000010 1248#define FLD_PH_CH_SEL 0x00000010
1249#define FLD_PHASE_FIX 0x0000000F 1249#define FLD_PHASE_FIX 0x0000000f
1250 1250
1251/*****************************************************************************/ 1251/*****************************************************************************/
1252#define PATH1_CTL1 0x8D0 1252#define PATH1_CTL1 0x8d0
1253/* Reserved [31:29] */ 1253/* Reserved [31:29] */
1254#define FLD_PATH1_MUTE_CTL 0x1F000000 1254#define FLD_PATH1_MUTE_CTL 0x1f000000
1255/* Reserved [23:22] */ 1255/* Reserved [23:22] */
1256#define FLD_PATH1_AVC_CG 0x00300000 1256#define FLD_PATH1_AVC_CG 0x00300000
1257#define FLD_PATH1_AVC_RT 0x000F0000 1257#define FLD_PATH1_AVC_RT 0x000f0000
1258#define FLD_PATH1_AVC_AT 0x0000F000 1258#define FLD_PATH1_AVC_AT 0x0000f000
1259#define FLD_PATH1_AVC_STEREO 0x00000800 1259#define FLD_PATH1_AVC_STEREO 0x00000800
1260#define FLD_PATH1_AVC_CR 0x00000700 1260#define FLD_PATH1_AVC_CR 0x00000700
1261#define FLD_PATH1_AVC_RMS_CON 0x000000F0 1261#define FLD_PATH1_AVC_RMS_CON 0x000000f0
1262#define FLD_PATH1_SEL_CTL 0x0000000F 1262#define FLD_PATH1_SEL_CTL 0x0000000f
1263 1263
1264/*****************************************************************************/ 1264/*****************************************************************************/
1265#define PATH1_VOL_CTL 0x8D4 1265#define PATH1_VOL_CTL 0x8d4
1266#define FLD_PATH1_AVC_THRESHOLD 0x7FFF0000 1266#define FLD_PATH1_AVC_THRESHOLD 0x7fff0000
1267#define FLD_PATH1_BAL_LEFT 0x00008000 1267#define FLD_PATH1_BAL_LEFT 0x00008000
1268#define FLD_PATH1_BAL_LEVEL 0x00007F00 1268#define FLD_PATH1_BAL_LEVEL 0x00007f00
1269#define FLD_PATH1_VOLUME 0x000000FF 1269#define FLD_PATH1_VOLUME 0x000000ff
1270 1270
1271/*****************************************************************************/ 1271/*****************************************************************************/
1272#define PATH1_EQ_CTL 0x8D8 1272#define PATH1_EQ_CTL 0x8d8
1273/* Reserved [31:30] */ 1273/* Reserved [31:30] */
1274#define FLD_PATH1_EQ_TREBLE_VOL 0x3F000000 1274#define FLD_PATH1_EQ_TREBLE_VOL 0x3f000000
1275/* Reserved [23:22] */ 1275/* Reserved [23:22] */
1276#define FLD_PATH1_EQ_MID_VOL 0x003F0000 1276#define FLD_PATH1_EQ_MID_VOL 0x003f0000
1277/* Reserved [15:14] */ 1277/* Reserved [15:14] */
1278#define FLD_PATH1_EQ_BASS_VOL 0x00003F00 1278#define FLD_PATH1_EQ_BASS_VOL 0x00003f00
1279/* Reserved [7:1] */ 1279/* Reserved [7:1] */
1280#define FLD_PATH1_EQ_BAND_SEL 0x00000001 1280#define FLD_PATH1_EQ_BAND_SEL 0x00000001
1281 1281
1282/*****************************************************************************/ 1282/*****************************************************************************/
1283#define PATH1_SC_CTL 0x8DC 1283#define PATH1_SC_CTL 0x8dc
1284#define FLD_PATH1_SC_THRESHOLD 0x7FFF0000 1284#define FLD_PATH1_SC_THRESHOLD 0x7fff0000
1285#define FLD_PATH1_SC_RT 0x0000F000 1285#define FLD_PATH1_SC_RT 0x0000f000
1286#define FLD_PATH1_SC_AT 0x00000F00 1286#define FLD_PATH1_SC_AT 0x00000f00
1287#define FLD_PATH1_SC_STEREO 0x00000080 1287#define FLD_PATH1_SC_STEREO 0x00000080
1288#define FLD_PATH1_SC_CR 0x00000070 1288#define FLD_PATH1_SC_CR 0x00000070
1289#define FLD_PATH1_SC_RMS_CON 0x0000000F 1289#define FLD_PATH1_SC_RMS_CON 0x0000000f
1290 1290
1291/*****************************************************************************/ 1291/*****************************************************************************/
1292#define PATH2_CTL1 0x8E0 1292#define PATH2_CTL1 0x8e0
1293/* Reserved [31:26] */ 1293/* Reserved [31:26] */
1294#define FLD_PATH2_MUTE_CTL 0x03000000 1294#define FLD_PATH2_MUTE_CTL 0x03000000
1295/* Reserved [23:22] */ 1295/* Reserved [23:22] */
1296#define FLD_PATH2_AVC_CG 0x00300000 1296#define FLD_PATH2_AVC_CG 0x00300000
1297#define FLD_PATH2_AVC_RT 0x000F0000 1297#define FLD_PATH2_AVC_RT 0x000f0000
1298#define FLD_PATH2_AVC_AT 0x0000F000 1298#define FLD_PATH2_AVC_AT 0x0000f000
1299#define FLD_PATH2_AVC_STEREO 0x00000800 1299#define FLD_PATH2_AVC_STEREO 0x00000800
1300#define FLD_PATH2_AVC_CR 0x00000700 1300#define FLD_PATH2_AVC_CR 0x00000700
1301#define FLD_PATH2_AVC_RMS_CON 0x000000F0 1301#define FLD_PATH2_AVC_RMS_CON 0x000000f0
1302#define FLD_PATH2_SEL_CTL 0x0000000F 1302#define FLD_PATH2_SEL_CTL 0x0000000f
1303 1303
1304/*****************************************************************************/ 1304/*****************************************************************************/
1305#define PATH2_VOL_CTL 0x8E4 1305#define PATH2_VOL_CTL 0x8e4
1306#define FLD_PATH2_AVC_THRESHOLD 0xFFFF0000 1306#define FLD_PATH2_AVC_THRESHOLD 0xffff0000
1307#define FLD_PATH2_BAL_LEFT 0x00008000 1307#define FLD_PATH2_BAL_LEFT 0x00008000
1308#define FLD_PATH2_BAL_LEVEL 0x00007F00 1308#define FLD_PATH2_BAL_LEVEL 0x00007f00
1309#define FLD_PATH2_VOLUME 0x000000FF 1309#define FLD_PATH2_VOLUME 0x000000ff
1310 1310
1311/*****************************************************************************/ 1311/*****************************************************************************/
1312#define PATH2_EQ_CTL 0x8E8 1312#define PATH2_EQ_CTL 0x8e8
1313/* Reserved [31:30] */ 1313/* Reserved [31:30] */
1314#define FLD_PATH2_EQ_TREBLE_VOL 0x3F000000 1314#define FLD_PATH2_EQ_TREBLE_VOL 0x3f000000
1315/* Reserved [23:22] */ 1315/* Reserved [23:22] */
1316#define FLD_PATH2_EQ_MID_VOL 0x003F0000 1316#define FLD_PATH2_EQ_MID_VOL 0x003f0000
1317/* Reserved [15:14] */ 1317/* Reserved [15:14] */
1318#define FLD_PATH2_EQ_BASS_VOL 0x00003F00 1318#define FLD_PATH2_EQ_BASS_VOL 0x00003f00
1319/* Reserved [7:1] */ 1319/* Reserved [7:1] */
1320#define FLD_PATH2_EQ_BAND_SEL 0x00000001 1320#define FLD_PATH2_EQ_BAND_SEL 0x00000001
1321 1321
1322/*****************************************************************************/ 1322/*****************************************************************************/
1323#define PATH2_SC_CTL 0x8EC 1323#define PATH2_SC_CTL 0x8eC
1324#define FLD_PATH2_SC_THRESHOLD 0xFFFF0000 1324#define FLD_PATH2_SC_THRESHOLD 0xffff0000
1325#define FLD_PATH2_SC_RT 0x0000F000 1325#define FLD_PATH2_SC_RT 0x0000f000
1326#define FLD_PATH2_SC_AT 0x00000F00 1326#define FLD_PATH2_SC_AT 0x00000f00
1327#define FLD_PATH2_SC_STEREO 0x00000080 1327#define FLD_PATH2_SC_STEREO 0x00000080
1328#define FLD_PATH2_SC_CR 0x00000070 1328#define FLD_PATH2_SC_CR 0x00000070
1329#define FLD_PATH2_SC_RMS_CON 0x0000000F 1329#define FLD_PATH2_SC_RMS_CON 0x0000000f
1330 1330
1331/*****************************************************************************/ 1331/*****************************************************************************/
1332#define SRC_CTL 0x8F0 1332#define SRC_CTL 0x8f0
1333#define FLD_SRC_STATUS 0xFFFFFF00 1333#define FLD_SRC_STATUS 0xffffff00
1334#define FLD_FIFO_LF_EN 0x000000FC 1334#define FLD_FIFO_LF_EN 0x000000fc
1335#define FLD_BYPASS_LI 0x00000002 1335#define FLD_BYPASS_LI 0x00000002
1336#define FLD_BYPASS_PF 0x00000001 1336#define FLD_BYPASS_PF 0x00000001
1337 1337
1338/*****************************************************************************/ 1338/*****************************************************************************/
1339#define SRC_LF_COEF 0x8F4 1339#define SRC_LF_COEF 0x8f4
1340#define FLD_LOOP_FILTER_COEF2 0xFFFF0000 1340#define FLD_LOOP_FILTER_COEF2 0xffff0000
1341#define FLD_LOOP_FILTER_COEF1 0x0000FFFF 1341#define FLD_LOOP_FILTER_COEF1 0x0000ffff
1342 1342
1343/*****************************************************************************/ 1343/*****************************************************************************/
1344#define SRC1_CTL 0x8F8 1344#define SRC1_CTL 0x8f8
1345/* Reserved [31:28] */ 1345/* Reserved [31:28] */
1346#define FLD_SRC1_FIFO_RD_TH 0x0F000000 1346#define FLD_SRC1_FIFO_RD_TH 0x0f000000
1347/* Reserved [23:18] */ 1347/* Reserved [23:18] */
1348#define FLD_SRC1_PHASE_INC 0x0003FFFF 1348#define FLD_SRC1_PHASE_INC 0x0003ffff
1349 1349
1350/*****************************************************************************/ 1350/*****************************************************************************/
1351#define SRC2_CTL 0x8FC 1351#define SRC2_CTL 0x8fc
1352/* Reserved [31:28] */ 1352/* Reserved [31:28] */
1353#define FLD_SRC2_FIFO_RD_TH 0x0F000000 1353#define FLD_SRC2_FIFO_RD_TH 0x0f000000
1354/* Reserved [23:18] */ 1354/* Reserved [23:18] */
1355#define FLD_SRC2_PHASE_INC 0x0003FFFF 1355#define FLD_SRC2_PHASE_INC 0x0003ffff
1356 1356
1357/*****************************************************************************/ 1357/*****************************************************************************/
1358#define SRC3_CTL 0x900 1358#define SRC3_CTL 0x900
1359/* Reserved [31:28] */ 1359/* Reserved [31:28] */
1360#define FLD_SRC3_FIFO_RD_TH 0x0F000000 1360#define FLD_SRC3_FIFO_RD_TH 0x0f000000
1361/* Reserved [23:18] */ 1361/* Reserved [23:18] */
1362#define FLD_SRC3_PHASE_INC 0x0003FFFF 1362#define FLD_SRC3_PHASE_INC 0x0003ffff
1363 1363
1364/*****************************************************************************/ 1364/*****************************************************************************/
1365#define SRC4_CTL 0x904 1365#define SRC4_CTL 0x904
1366/* Reserved [31:28] */ 1366/* Reserved [31:28] */
1367#define FLD_SRC4_FIFO_RD_TH 0x0F000000 1367#define FLD_SRC4_FIFO_RD_TH 0x0f000000
1368/* Reserved [23:18] */ 1368/* Reserved [23:18] */
1369#define FLD_SRC4_PHASE_INC 0x0003FFFF 1369#define FLD_SRC4_PHASE_INC 0x0003ffff
1370 1370
1371/*****************************************************************************/ 1371/*****************************************************************************/
1372#define SRC5_CTL 0x908 1372#define SRC5_CTL 0x908
1373/* Reserved [31:28] */ 1373/* Reserved [31:28] */
1374#define FLD_SRC5_FIFO_RD_TH 0x0F000000 1374#define FLD_SRC5_FIFO_RD_TH 0x0f000000
1375/* Reserved [23:18] */ 1375/* Reserved [23:18] */
1376#define FLD_SRC5_PHASE_INC 0x0003FFFF 1376#define FLD_SRC5_PHASE_INC 0x0003ffff
1377 1377
1378/*****************************************************************************/ 1378/*****************************************************************************/
1379#define SRC6_CTL 0x90C 1379#define SRC6_CTL 0x90c
1380/* Reserved [31:28] */ 1380/* Reserved [31:28] */
1381#define FLD_SRC6_FIFO_RD_TH 0x0F000000 1381#define FLD_SRC6_FIFO_RD_TH 0x0f000000
1382/* Reserved [23:18] */ 1382/* Reserved [23:18] */
1383#define FLD_SRC6_PHASE_INC 0x0003FFFF 1383#define FLD_SRC6_PHASE_INC 0x0003ffff
1384 1384
1385/*****************************************************************************/ 1385/*****************************************************************************/
1386#define BAND_OUT_SEL 0x910 1386#define BAND_OUT_SEL 0x910
1387#define FLD_SRC6_IN_SEL 0xC0000000 1387#define FLD_SRC6_IN_SEL 0xc0000000
1388#define FLD_SRC6_CLK_SEL 0x30000000 1388#define FLD_SRC6_CLK_SEL 0x30000000
1389#define FLD_SRC5_IN_SEL 0x0C000000 1389#define FLD_SRC5_IN_SEL 0x0c000000
1390#define FLD_SRC5_CLK_SEL 0x03000000 1390#define FLD_SRC5_CLK_SEL 0x03000000
1391#define FLD_SRC4_IN_SEL 0x00C00000 1391#define FLD_SRC4_IN_SEL 0x00c00000
1392#define FLD_SRC4_CLK_SEL 0x00300000 1392#define FLD_SRC4_CLK_SEL 0x00300000
1393#define FLD_SRC3_IN_SEL 0x000C0000 1393#define FLD_SRC3_IN_SEL 0x000c0000
1394#define FLD_SRC3_CLK_SEL 0x00030000 1394#define FLD_SRC3_CLK_SEL 0x00030000
1395#define FLD_BASEBAND_BYPASS_CTL 0x0000FF00 1395#define FLD_BASEBAND_BYPASS_CTL 0x0000ff00
1396#define FLD_AC97_SRC_SEL 0x000000C0 1396#define FLD_AC97_SRC_SEL 0x000000c0
1397#define FLD_I2S_SRC_SEL 0x00000030 1397#define FLD_I2S_SRC_SEL 0x00000030
1398#define FLD_PARALLEL2_SRC_SEL 0x0000000C 1398#define FLD_PARALLEL2_SRC_SEL 0x0000000c
1399#define FLD_PARALLEL1_SRC_SEL 0x00000003 1399#define FLD_PARALLEL1_SRC_SEL 0x00000003
1400 1400
1401/*****************************************************************************/ 1401/*****************************************************************************/
@@ -1407,7 +1407,7 @@
1407#define FLD_I2S_IN_SONY_MODE 0x00000080 1407#define FLD_I2S_IN_SONY_MODE 0x00000080
1408#define FLD_I2S_IN_RIGHT_JUST 0x00000040 1408#define FLD_I2S_IN_RIGHT_JUST 0x00000040
1409#define FLD_I2S_IN_WS_SEL 0x00000020 1409#define FLD_I2S_IN_WS_SEL 0x00000020
1410#define FLD_I2S_IN_BCN_DEL 0x0000001F 1410#define FLD_I2S_IN_BCN_DEL 0x0000001f
1411 1411
1412/*****************************************************************************/ 1412/*****************************************************************************/
1413#define I2S_OUT_CTL 0x918 1413#define I2S_OUT_CTL 0x918
@@ -1418,10 +1418,10 @@
1418#define FLD_I2S_OUT_SONY_MODE 0x00000080 1418#define FLD_I2S_OUT_SONY_MODE 0x00000080
1419#define FLD_I2S_OUT_RIGHT_JUST 0x00000040 1419#define FLD_I2S_OUT_RIGHT_JUST 0x00000040
1420#define FLD_I2S_OUT_WS_SEL 0x00000020 1420#define FLD_I2S_OUT_WS_SEL 0x00000020
1421#define FLD_I2S_OUT_BCN_DEL 0x0000001F 1421#define FLD_I2S_OUT_BCN_DEL 0x0000001f
1422 1422
1423/*****************************************************************************/ 1423/*****************************************************************************/
1424#define AC97_CTL 0x91C 1424#define AC97_CTL 0x91c
1425/* Reserved [31:26] */ 1425/* Reserved [31:26] */
1426#define FLD_AC97_UP2X_BW20K 0x02000000 1426#define FLD_AC97_UP2X_BW20K 0x02000000
1427#define FLD_AC97_UP2X_BYPASS 0x01000000 1427#define FLD_AC97_UP2X_BYPASS 0x01000000
@@ -1433,20 +1433,20 @@
1433#define FLD_AC97_SHUTDOWN 0x00000001 1433#define FLD_AC97_SHUTDOWN 0x00000001
1434 1434
1435/* Cx231xx redefine */ 1435/* Cx231xx redefine */
1436#define QPSK_IAGC_CTL1 0x94c 1436#define QPSK_IAGC_CTL1 0x94c
1437#define QPSK_IAGC_CTL2 0x950 1437#define QPSK_IAGC_CTL2 0x950
1438#define QPSK_FEPR_FREQ 0x954 1438#define QPSK_FEPR_FREQ 0x954
1439#define QPSK_BTL_CTL1 0x958 1439#define QPSK_BTL_CTL1 0x958
1440#define QPSK_BTL_CTL2 0x95c 1440#define QPSK_BTL_CTL2 0x95c
1441#define QPSK_CTL_CTL1 0x960 1441#define QPSK_CTL_CTL1 0x960
1442#define QPSK_CTL_CTL2 0x964 1442#define QPSK_CTL_CTL2 0x964
1443#define QPSK_MF_FAGC_CTL 0x968 1443#define QPSK_MF_FAGC_CTL 0x968
1444#define QPSK_EQ_CTL 0x96c 1444#define QPSK_EQ_CTL 0x96c
1445#define QPSK_LOCK_CTL 0x970 1445#define QPSK_LOCK_CTL 0x970
1446 1446
1447/*****************************************************************************/ 1447/*****************************************************************************/
1448#define FM1_DFT_CTL 0x9A8 1448#define FM1_DFT_CTL 0x9a8
1449#define FLD_FM1_DFT_THRESHOLD 0xFFFF0000 1449#define FLD_FM1_DFT_THRESHOLD 0xffff0000
1450/* Reserved [15:8] */ 1450/* Reserved [15:8] */
1451#define FLD_FM1_DFT_CMP_CTL 0x00000080 1451#define FLD_FM1_DFT_CMP_CTL 0x00000080
1452#define FLD_FM1_DFT_AVG 0x00000070 1452#define FLD_FM1_DFT_AVG 0x00000070
@@ -1454,15 +1454,15 @@
1454#define FLD_FM1_DFT_START 0x00000001 1454#define FLD_FM1_DFT_START 0x00000001
1455 1455
1456/*****************************************************************************/ 1456/*****************************************************************************/
1457#define FM1_DFT_STATUS 0x9AC 1457#define FM1_DFT_STATUS 0x9ac
1458#define FLD_FM1_DFT_DONE 0x80000000 1458#define FLD_FM1_DFT_DONE 0x80000000
1459/* Reserved [30:19] */ 1459/* Reserved [30:19] */
1460#define FLD_FM_DFT_TH_CMP 0x00040000 1460#define FLD_FM_DFT_TH_CMP 0x00040000
1461#define FLD_FM1_DFT 0x0003FFFF 1461#define FLD_FM1_DFT 0x0003ffff
1462 1462
1463/*****************************************************************************/ 1463/*****************************************************************************/
1464#define FM2_DFT_CTL 0x9B0 1464#define FM2_DFT_CTL 0x9b0
1465#define FLD_FM2_DFT_THRESHOLD 0xFFFF0000 1465#define FLD_FM2_DFT_THRESHOLD 0xffff0000
1466/* Reserved [15:8] */ 1466/* Reserved [15:8] */
1467#define FLD_FM2_DFT_CMP_CTL 0x00000080 1467#define FLD_FM2_DFT_CMP_CTL 0x00000080
1468#define FLD_FM2_DFT_AVG 0x00000070 1468#define FLD_FM2_DFT_AVG 0x00000070
@@ -1470,52 +1470,52 @@
1470#define FLD_FM2_DFT_START 0x00000001 1470#define FLD_FM2_DFT_START 0x00000001
1471 1471
1472/*****************************************************************************/ 1472/*****************************************************************************/
1473#define FM2_DFT_STATUS 0x9B4 1473#define FM2_DFT_STATUS 0x9b4
1474#define FLD_FM2_DFT_DONE 0x80000000 1474#define FLD_FM2_DFT_DONE 0x80000000
1475/* Reserved [30:19] */ 1475/* Reserved [30:19] */
1476#define FLD_FM2_DFT_TH_CMP_STAT 0x00040000 1476#define FLD_FM2_DFT_TH_CMP_STAT 0x00040000
1477#define FLD_FM2_DFT 0x0003FFFF 1477#define FLD_FM2_DFT 0x0003ffff
1478 1478
1479/*****************************************************************************/ 1479/*****************************************************************************/
1480/* Cx231xx redefine */ 1480/* Cx231xx redefine */
1481#define AAGC_STATUS_REG 0x9B8 1481#define AAGC_STATUS_REG 0x9b8
1482#define AAGC_STATUS 0x9B8 1482#define AAGC_STATUS 0x9b8
1483/* Reserved [31:27] */ 1483/* Reserved [31:27] */
1484#define FLD_FM2_DAGC_OUT 0x07000000 1484#define FLD_FM2_DAGC_OUT 0x07000000
1485/* Reserved [23:19] */ 1485/* Reserved [23:19] */
1486#define FLD_FM1_DAGC_OUT 0x00070000 1486#define FLD_FM1_DAGC_OUT 0x00070000
1487/* Reserved [15:6] */ 1487/* Reserved [15:6] */
1488#define FLD_AFE_VGA_OUT 0x0000003F 1488#define FLD_AFE_VGA_OUT 0x0000003f
1489 1489
1490/*****************************************************************************/ 1490/*****************************************************************************/
1491#define MTS_GAIN_STATUS 0x9BC 1491#define MTS_GAIN_STATUS 0x9bc
1492/* Reserved [31:14] */ 1492/* Reserved [31:14] */
1493#define FLD_MTS_GAIN 0x00003FFF 1493#define FLD_MTS_GAIN 0x00003fff
1494 1494
1495#define RDS_OUT 0x9C0 1495#define RDS_OUT 0x9c0
1496#define FLD_RDS_Q 0xFFFF0000 1496#define FLD_RDS_Q 0xffff0000
1497#define FLD_RDS_I 0x0000FFFF 1497#define FLD_RDS_I 0x0000ffff
1498 1498
1499/*****************************************************************************/ 1499/*****************************************************************************/
1500#define AUTOCONFIG_REG 0x9C4 1500#define AUTOCONFIG_REG 0x9c4
1501/* Reserved [31:4] */ 1501/* Reserved [31:4] */
1502#define FLD_AUTOCONFIG_MODE 0x0000000F 1502#define FLD_AUTOCONFIG_MODE 0x0000000f
1503 1503
1504#define FM_AFC 0x9C8 1504#define FM_AFC 0x9c8
1505#define FLD_FM2_AFC 0xFFFF0000 1505#define FLD_FM2_AFC 0xffff0000
1506#define FLD_FM1_AFC 0x0000FFFF 1506#define FLD_FM1_AFC 0x0000ffff
1507 1507
1508/*****************************************************************************/ 1508/*****************************************************************************/
1509/* Cx231xx redefine */ 1509/* Cx231xx redefine */
1510#define NEW_SPARE 0x9CC 1510#define NEW_SPARE 0x9cc
1511#define NEW_SPARE_REG 0x9CC 1511#define NEW_SPARE_REG 0x9cc
1512 1512
1513/*****************************************************************************/ 1513/*****************************************************************************/
1514#define DBX_ADJ 0x9D0 1514#define DBX_ADJ 0x9d0
1515/* Reserved [31:28] */ 1515/* Reserved [31:28] */
1516#define FLD_DBX2_ADJ 0x0FFF0000 1516#define FLD_DBX2_ADJ 0x0fff0000
1517/* Reserved [15:12] */ 1517/* Reserved [15:12] */
1518#define FLD_DBX1_ADJ 0x00000FFF 1518#define FLD_DBX1_ADJ 0x00000fff
1519 1519
1520#define VID_FMT_AUTO 0 1520#define VID_FMT_AUTO 0
1521#define VID_FMT_NTSC_M 1 1521#define VID_FMT_NTSC_M 1
@@ -1529,18 +1529,18 @@
1529#define VID_FMT_SECAM 12 1529#define VID_FMT_SECAM 12
1530#define VID_FMT_SECAM_60 13 1530#define VID_FMT_SECAM_60 13
1531 1531
1532#define INPUT_MODE_CVBS_0 0 /* INPUT_MODE_VALUE(0) */ 1532#define INPUT_MODE_CVBS_0 0 /* INPUT_MODE_VALUE(0) */
1533#define INPUT_MODE_YC_1 1 /* INPUT_MODE_VALUE(1) */ 1533#define INPUT_MODE_YC_1 1 /* INPUT_MODE_VALUE(1) */
1534#define INPUT_MODE_YC2_2 2 /* INPUT_MODE_VALUE(2) */ 1534#define INPUT_MODE_YC2_2 2 /* INPUT_MODE_VALUE(2) */
1535#define INPUT_MODE_YUV_3 3 /* INPUT_MODE_VALUE(3) */ 1535#define INPUT_MODE_YUV_3 3 /* INPUT_MODE_VALUE(3) */
1536 1536
1537#define LUMA_LPF_LOW_BANDPASS 0 /* 0.6Mhz LPF BW */ 1537#define LUMA_LPF_LOW_BANDPASS 0 /* 0.6Mhz LPF BW */
1538#define LUMA_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz LPF BW */ 1538#define LUMA_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz LPF BW */
1539#define LUMA_LPF_HIGH_BANDPASS 2 /* 1.5Mhz LPF BW */ 1539#define LUMA_LPF_HIGH_BANDPASS 2 /* 1.5Mhz LPF BW */
1540 1540
1541#define UV_LPF_LOW_BANDPASS 0 /* 0.6Mhz LPF BW */ 1541#define UV_LPF_LOW_BANDPASS 0 /* 0.6Mhz LPF BW */
1542#define UV_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz LPF BW */ 1542#define UV_LPF_MEDIUM_BANDPASS 1 /* 1.0Mhz LPF BW */
1543#define UV_LPF_HIGH_BANDPASS 2 /* 1.5Mhz LPF BW */ 1543#define UV_LPF_HIGH_BANDPASS 2 /* 1.5Mhz LPF BW */
1544 1544
1545#define TWO_TAP_FILT 0 1545#define TWO_TAP_FILT 0
1546#define THREE_TAP_FILT 1 1546#define THREE_TAP_FILT 1
@@ -1557,8 +1557,8 @@
1557#define OUT_MODE_VIP11 2 1557#define OUT_MODE_VIP11 2
1558#define OUT_MODE_VIP20 3 1558#define OUT_MODE_VIP20 3
1559 1559
1560#define PHASE_INC_49MHZ 0x0DF22 1560#define PHASE_INC_49MHZ 0x0df22
1561#define PHASE_INC_56MHZ 0x0FA5B 1561#define PHASE_INC_56MHZ 0x0fa5b
1562#define PHASE_INC_28MHZ 0x010000 1562#define PHASE_INC_28MHZ 0x010000
1563 1563
1564#endif 1564#endif
diff --git a/drivers/media/video/cx231xx/cx231xx-video.c b/drivers/media/video/cx231xx/cx231xx-video.c
index fc7260a71e8e..606f80129ffb 100644
--- a/drivers/media/video/cx231xx/cx231xx-video.c
+++ b/drivers/media/video/cx231xx/cx231xx-video.c
@@ -1655,10 +1655,12 @@ static int vidioc_querycap(struct file *file, void *priv,
1655 1655
1656 cap->capabilities = V4L2_CAP_VBI_CAPTURE | 1656 cap->capabilities = V4L2_CAP_VBI_CAPTURE |
1657#if 0 1657#if 0
1658 V4L2_CAP_SLICED_VBI_CAPTURE | 1658 V4L2_CAP_SLICED_VBI_CAPTURE |
1659#endif 1659#endif
1660 V4L2_CAP_VIDEO_CAPTURE | 1660 V4L2_CAP_VIDEO_CAPTURE |
1661 V4L2_CAP_AUDIO | V4L2_CAP_READWRITE | V4L2_CAP_STREAMING; 1661 V4L2_CAP_AUDIO |
1662 V4L2_CAP_READWRITE |
1663 V4L2_CAP_STREAMING;
1662 1664
1663 if (dev->tuner_type != TUNER_ABSENT) 1665 if (dev->tuner_type != TUNER_ABSENT)
1664 cap->capabilities |= V4L2_CAP_TUNER; 1666 cap->capabilities |= V4L2_CAP_TUNER;
diff --git a/drivers/media/video/cx231xx/cx231xx.h b/drivers/media/video/cx231xx/cx231xx.h
index f6e34a6de783..7c2a162f5c41 100644
--- a/drivers/media/video/cx231xx/cx231xx.h
+++ b/drivers/media/video/cx231xx/cx231xx.h
@@ -35,7 +35,7 @@
35#endif 35#endif
36 36
37#include "cx231xx-reg.h" 37#include "cx231xx-reg.h"
38#include "cx231xx-pcb-config.h" 38#include "cx231xx-pcb-cfg.h"
39#include "cx231xx-conf-reg.h" 39#include "cx231xx-conf-reg.h"
40 40
41#define DRIVER_NAME "cx231xx" 41#define DRIVER_NAME "cx231xx"
@@ -389,7 +389,7 @@ struct cx231xx_i2c_xfer_data {
389 u8 *p_buffer; /* pointer to the buffer */ 389 u8 *p_buffer; /* pointer to the buffer */
390}; 390};
391 391
392struct VENDOR_REQUEST_IN{ 392struct VENDOR_REQUEST_IN {
393 u8 bRequest; 393 u8 bRequest;
394 u16 wValue; 394 u16 wValue;
395 u16 wIndex; 395 u16 wIndex;
@@ -407,7 +407,7 @@ struct cx231xx_ctrl {
407 u32 shift; 407 u32 shift;
408}; 408};
409 409
410enum TRANSFER_TYPE{ 410enum TRANSFER_TYPE {
411 Raw_Video = 0, 411 Raw_Video = 0,
412 Audio, 412 Audio,
413 Vbi, /* VANC */ 413 Vbi, /* VANC */
@@ -581,12 +581,14 @@ int cx231xx_colibri_init_channels(struct cx231xx *dev);
581int cx231xx_colibri_setup_AFE_for_baseband(struct cx231xx *dev); 581int cx231xx_colibri_setup_AFE_for_baseband(struct cx231xx *dev);
582int cx231xx_colibri_set_input_mux(struct cx231xx *dev, u32 input_mux); 582int cx231xx_colibri_set_input_mux(struct cx231xx *dev, u32 input_mux);
583int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode); 583int cx231xx_colibri_set_mode(struct cx231xx *dev, enum AFE_MODE mode);
584int cx231xx_colibri_update_power_control(struct cx231xx *dev, AV_MODE avmode); 584int cx231xx_colibri_update_power_control(struct cx231xx *dev,
585 enum AV_MODE avmode);
585int cx231xx_colibri_adjust_ref_count(struct cx231xx *dev, u32 video_input); 586int cx231xx_colibri_adjust_ref_count(struct cx231xx *dev, u32 video_input);
586 587
587/* flatiron related functions */ 588/* flatiron related functions */
588int cx231xx_flatiron_initialize(struct cx231xx *dev); 589int cx231xx_flatiron_initialize(struct cx231xx *dev);
589int cx231xx_flatiron_update_power_control(struct cx231xx *dev, AV_MODE avmode); 590int cx231xx_flatiron_update_power_control(struct cx231xx *dev,
591 enum AV_MODE avmode);
590int cx231xx_flatiron_set_audio_input(struct cx231xx *dev, u8 audio_input); 592int cx231xx_flatiron_set_audio_input(struct cx231xx *dev, u8 audio_input);
591 593
592/* DIF related functions */ 594/* DIF related functions */
@@ -692,7 +694,7 @@ int cx231xx_stop_stream(struct cx231xx *dev, u32 ep_mask);
692int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type); 694int cx231xx_initialize_stream_xfer(struct cx231xx *dev, u32 media_type);
693 695
694/* Power control functions */ 696/* Power control functions */
695int cx231xx_set_power_mode(struct cx231xx *dev, AV_MODE mode); 697int cx231xx_set_power_mode(struct cx231xx *dev, enum AV_MODE mode);
696int cx231xx_power_suspend(struct cx231xx *dev); 698int cx231xx_power_suspend(struct cx231xx *dev);
697 699
698/* chip specific control functions */ 700/* chip specific control functions */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-31 23:18:11 -0500