aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/media/video
diff options
context:
space:
mode:
authorChaithrika U S <chaithrika@ti.com>2009-06-09 04:54:02 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2009-09-18 23:18:01 -0400
commit63a8e71c4453a38c3468f84f0f452e2643abdad3 (patch)
treedcaf503593b2923acbd50408a54cce06be2c6522 /drivers/media/video
parentbb3baf89d197f392c011c64935b79ed67a6542db (diff)
V4L/DVB (12175): davinci/vpif: Add Video Port Interface (VPIF) driver
This code be used by the display and capture drivers. Signed-off-by: Manjunath Hadli <mrh@ti.com> Signed-off-by: Brijesh Jadav <brijesh.j@ti.com> Signed-off-by: Chaithrika U S <chaithrika@ti.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/video')
-rw-r--r--drivers/media/video/davinci/vpif.c234
-rw-r--r--drivers/media/video/davinci/vpif.h632
2 files changed, 866 insertions, 0 deletions
diff --git a/drivers/media/video/davinci/vpif.c b/drivers/media/video/davinci/vpif.c
new file mode 100644
index 000000000000..aa771268a5a5
--- /dev/null
+++ b/drivers/media/video/davinci/vpif.c
@@ -0,0 +1,234 @@
1/*
2 * vpif - DM646x Video Port Interface driver
3 * VPIF is a receiver and transmitter for video data. It has two channels(0, 1)
4 * that receiveing video byte stream and two channels(2, 3) for video output.
5 * The hardware supports SDTV, HDTV formats, raw data capture.
6 * Currently, the driver supports NTSC and PAL standards.
7 *
8 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation version 2.
13 *
14 * This program is distributed .as is. WITHOUT ANY WARRANTY of any
15 * kind, whether express or implied; without even the implied warranty
16 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20#include <linux/init.h>
21#include <linux/module.h>
22#include <linux/kernel.h>
23
24#include "vpif.h"
25
26MODULE_DESCRIPTION("TI DaVinci Video Port Interface driver");
27MODULE_LICENSE("GPL");
28
29#define VPIF_CH0_MAX_MODES (22)
30#define VPIF_CH1_MAX_MODES (02)
31#define VPIF_CH2_MAX_MODES (15)
32#define VPIF_CH3_MAX_MODES (02)
33
34static inline void vpif_wr_bit(u32 reg, u32 bit, u32 val)
35{
36 if (val)
37 vpif_set_bit(reg, bit);
38 else
39 vpif_clr_bit(reg, bit);
40}
41
42/* This structure is used to keep track of VPIF size register's offsets */
43struct vpif_registers {
44 u32 h_cfg, v_cfg_00, v_cfg_01, v_cfg_02, v_cfg, ch_ctrl;
45 u32 line_offset, vanc0_strt, vanc0_size, vanc1_strt;
46 u32 vanc1_size, width_mask, len_mask;
47 u8 max_modes;
48};
49
50static const struct vpif_registers vpifregs[VPIF_NUM_CHANNELS] = {
51 /* Channel0 */
52 {
53 VPIF_CH0_H_CFG, VPIF_CH0_V_CFG_00, VPIF_CH0_V_CFG_01,
54 VPIF_CH0_V_CFG_02, VPIF_CH0_V_CFG_03, VPIF_CH0_CTRL,
55 VPIF_CH0_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,
56 VPIF_CH0_MAX_MODES,
57 },
58 /* Channel1 */
59 {
60 VPIF_CH1_H_CFG, VPIF_CH1_V_CFG_00, VPIF_CH1_V_CFG_01,
61 VPIF_CH1_V_CFG_02, VPIF_CH1_V_CFG_03, VPIF_CH1_CTRL,
62 VPIF_CH1_IMG_ADD_OFST, 0, 0, 0, 0, 0x1FFF, 0xFFF,
63 VPIF_CH1_MAX_MODES,
64 },
65 /* Channel2 */
66 {
67 VPIF_CH2_H_CFG, VPIF_CH2_V_CFG_00, VPIF_CH2_V_CFG_01,
68 VPIF_CH2_V_CFG_02, VPIF_CH2_V_CFG_03, VPIF_CH2_CTRL,
69 VPIF_CH2_IMG_ADD_OFST, VPIF_CH2_VANC0_STRT, VPIF_CH2_VANC0_SIZE,
70 VPIF_CH2_VANC1_STRT, VPIF_CH2_VANC1_SIZE, 0x7FF, 0x7FF,
71 VPIF_CH2_MAX_MODES
72 },
73 /* Channel3 */
74 {
75 VPIF_CH3_H_CFG, VPIF_CH3_V_CFG_00, VPIF_CH3_V_CFG_01,
76 VPIF_CH3_V_CFG_02, VPIF_CH3_V_CFG_03, VPIF_CH3_CTRL,
77 VPIF_CH3_IMG_ADD_OFST, VPIF_CH3_VANC0_STRT, VPIF_CH3_VANC0_SIZE,
78 VPIF_CH3_VANC1_STRT, VPIF_CH3_VANC1_SIZE, 0x7FF, 0x7FF,
79 VPIF_CH3_MAX_MODES
80 },
81};
82
83/* vpif_set_mode_info:
84 * This function is used to set horizontal and vertical config parameters
85 * As per the standard in the channel, configure the values of L1, L3,
86 * L5, L7 L9, L11 in VPIF Register , also write width and height
87 */
88static void vpif_set_mode_info(const struct vpif_channel_config_params *config,
89 u8 channel_id, u8 config_channel_id)
90{
91 u32 value;
92
93 value = (config->eav2sav & vpifregs[config_channel_id].width_mask);
94 value <<= VPIF_CH_LEN_SHIFT;
95 value |= (config->sav2eav & vpifregs[config_channel_id].width_mask);
96 regw(value, vpifregs[channel_id].h_cfg);
97
98 value = (config->l1 & vpifregs[config_channel_id].len_mask);
99 value <<= VPIF_CH_LEN_SHIFT;
100 value |= (config->l3 & vpifregs[config_channel_id].len_mask);
101 regw(value, vpifregs[channel_id].v_cfg_00);
102
103 value = (config->l5 & vpifregs[config_channel_id].len_mask);
104 value <<= VPIF_CH_LEN_SHIFT;
105 value |= (config->l7 & vpifregs[config_channel_id].len_mask);
106 regw(value, vpifregs[channel_id].v_cfg_01);
107
108 value = (config->l9 & vpifregs[config_channel_id].len_mask);
109 value <<= VPIF_CH_LEN_SHIFT;
110 value |= (config->l11 & vpifregs[config_channel_id].len_mask);
111 regw(value, vpifregs[channel_id].v_cfg_02);
112
113 value = (config->vsize & vpifregs[config_channel_id].len_mask);
114 regw(value, vpifregs[channel_id].v_cfg);
115}
116
117/* config_vpif_params
118 * Function to set the parameters of a channel
119 * Mainly modifies the channel ciontrol register
120 * It sets frame format, yc mux mode
121 */
122static void config_vpif_params(struct vpif_params *vpifparams,
123 u8 channel_id, u8 found)
124{
125 const struct vpif_channel_config_params *config = &vpifparams->std_info;
126 u32 value, ch_nip, reg;
127 u8 start, end;
128 int i;
129
130 start = channel_id;
131 end = channel_id + found;
132
133 for (i = start; i < end; i++) {
134 reg = vpifregs[i].ch_ctrl;
135 if (channel_id < 2)
136 ch_nip = VPIF_CAPTURE_CH_NIP;
137 else
138 ch_nip = VPIF_DISPLAY_CH_NIP;
139
140 vpif_wr_bit(reg, ch_nip, config->frm_fmt);
141 vpif_wr_bit(reg, VPIF_CH_YC_MUX_BIT, config->ycmux_mode);
142 vpif_wr_bit(reg, VPIF_CH_INPUT_FIELD_FRAME_BIT,
143 vpifparams->video_params.storage_mode);
144
145 /* Set raster scanning SDR Format */
146 vpif_clr_bit(reg, VPIF_CH_SDR_FMT_BIT);
147 vpif_wr_bit(reg, VPIF_CH_DATA_MODE_BIT, config->capture_format);
148
149 if (channel_id > 1) /* Set the Pixel enable bit */
150 vpif_set_bit(reg, VPIF_DISPLAY_PIX_EN_BIT);
151 else if (config->capture_format) {
152 /* Set the polarity of various pins */
153 vpif_wr_bit(reg, VPIF_CH_FID_POLARITY_BIT,
154 vpifparams->params.raw_params.fid_pol);
155 vpif_wr_bit(reg, VPIF_CH_V_VALID_POLARITY_BIT,
156 vpifparams->params.raw_params.vd_pol);
157 vpif_wr_bit(reg, VPIF_CH_H_VALID_POLARITY_BIT,
158 vpifparams->params.raw_params.hd_pol);
159
160 value = regr(reg);
161 /* Set data width */
162 value &= ((~(unsigned int)(0x3)) <<
163 VPIF_CH_DATA_WIDTH_BIT);
164 value |= ((vpifparams->params.raw_params.data_sz) <<
165 VPIF_CH_DATA_WIDTH_BIT);
166 regw(value, reg);
167 }
168
169 /* Write the pitch in the driver */
170 regw((vpifparams->video_params.hpitch),
171 vpifregs[i].line_offset);
172 }
173}
174
175/* vpif_set_video_params
176 * This function is used to set video parameters in VPIF register
177 */
178int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id)
179{
180 const struct vpif_channel_config_params *config = &vpifparams->std_info;
181 int found = 1;
182
183 vpif_set_mode_info(config, channel_id, channel_id);
184 if (!config->ycmux_mode) {
185 /* YC are on separate channels (HDTV formats) */
186 vpif_set_mode_info(config, channel_id + 1, channel_id);
187 found = 2;
188 }
189
190 config_vpif_params(vpifparams, channel_id, found);
191
192 regw(0x80, VPIF_REQ_SIZE);
193 regw(0x01, VPIF_EMULATION_CTRL);
194
195 return found;
196}
197EXPORT_SYMBOL(vpif_set_video_params);
198
199void vpif_set_vbi_display_params(struct vpif_vbi_params *vbiparams,
200 u8 channel_id)
201{
202 u32 value;
203
204 value = 0x3F8 & (vbiparams->hstart0);
205 value |= 0x3FFFFFF & ((vbiparams->vstart0) << 16);
206 regw(value, vpifregs[channel_id].vanc0_strt);
207
208 value = 0x3F8 & (vbiparams->hstart1);
209 value |= 0x3FFFFFF & ((vbiparams->vstart1) << 16);
210 regw(value, vpifregs[channel_id].vanc1_strt);
211
212 value = 0x3F8 & (vbiparams->hsize0);
213 value |= 0x3FFFFFF & ((vbiparams->vsize0) << 16);
214 regw(value, vpifregs[channel_id].vanc0_size);
215
216 value = 0x3F8 & (vbiparams->hsize1);
217 value |= 0x3FFFFFF & ((vbiparams->vsize1) << 16);
218 regw(value, vpifregs[channel_id].vanc1_size);
219
220}
221EXPORT_SYMBOL(vpif_set_vbi_display_params);
222
223int vpif_channel_getfid(u8 channel_id)
224{
225 return (regr(vpifregs[channel_id].ch_ctrl) & VPIF_CH_FID_MASK)
226 >> VPIF_CH_FID_SHIFT;
227}
228EXPORT_SYMBOL(vpif_channel_getfid);
229
230void vpif_base_addr_init(void __iomem *base)
231{
232 vpif_base = base;
233}
234EXPORT_SYMBOL(vpif_base_addr_init);
diff --git a/drivers/media/video/davinci/vpif.h b/drivers/media/video/davinci/vpif.h
new file mode 100644
index 000000000000..fca26dcb54de
--- /dev/null
+++ b/drivers/media/video/davinci/vpif.h
@@ -0,0 +1,632 @@
1/*
2 * VPIF header file
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed .as is. WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef VPIF_H
17#define VPIF_H
18
19#include <linux/io.h>
20#include <linux/videodev2.h>
21#include <mach/hardware.h>
22
23/* Maximum channel allowed */
24#define VPIF_NUM_CHANNELS (4)
25#define VPIF_CAPTURE_NUM_CHANNELS (2)
26#define VPIF_DISPLAY_NUM_CHANNELS (2)
27
28/* Macros to read/write registers */
29static void __iomem *vpif_base;
30#define regr(reg) readl((reg) + vpif_base)
31#define regw(value, reg) writel(value, (reg + vpif_base))
32
33/* Register Addresss Offsets */
34#define VPIF_PID (0x0000)
35#define VPIF_CH0_CTRL (0x0004)
36#define VPIF_CH1_CTRL (0x0008)
37#define VPIF_CH2_CTRL (0x000C)
38#define VPIF_CH3_CTRL (0x0010)
39
40#define VPIF_INTEN (0x0020)
41#define VPIF_INTEN_SET (0x0024)
42#define VPIF_INTEN_CLR (0x0028)
43#define VPIF_STATUS (0x002C)
44#define VPIF_STATUS_CLR (0x0030)
45#define VPIF_EMULATION_CTRL (0x0034)
46#define VPIF_REQ_SIZE (0x0038)
47
48#define VPIF_CH0_TOP_STRT_ADD_LUMA (0x0040)
49#define VPIF_CH0_BTM_STRT_ADD_LUMA (0x0044)
50#define VPIF_CH0_TOP_STRT_ADD_CHROMA (0x0048)
51#define VPIF_CH0_BTM_STRT_ADD_CHROMA (0x004c)
52#define VPIF_CH0_TOP_STRT_ADD_HANC (0x0050)
53#define VPIF_CH0_BTM_STRT_ADD_HANC (0x0054)
54#define VPIF_CH0_TOP_STRT_ADD_VANC (0x0058)
55#define VPIF_CH0_BTM_STRT_ADD_VANC (0x005c)
56#define VPIF_CH0_SP_CFG (0x0060)
57#define VPIF_CH0_IMG_ADD_OFST (0x0064)
58#define VPIF_CH0_HANC_ADD_OFST (0x0068)
59#define VPIF_CH0_H_CFG (0x006c)
60#define VPIF_CH0_V_CFG_00 (0x0070)
61#define VPIF_CH0_V_CFG_01 (0x0074)
62#define VPIF_CH0_V_CFG_02 (0x0078)
63#define VPIF_CH0_V_CFG_03 (0x007c)
64
65#define VPIF_CH1_TOP_STRT_ADD_LUMA (0x0080)
66#define VPIF_CH1_BTM_STRT_ADD_LUMA (0x0084)
67#define VPIF_CH1_TOP_STRT_ADD_CHROMA (0x0088)
68#define VPIF_CH1_BTM_STRT_ADD_CHROMA (0x008c)
69#define VPIF_CH1_TOP_STRT_ADD_HANC (0x0090)
70#define VPIF_CH1_BTM_STRT_ADD_HANC (0x0094)
71#define VPIF_CH1_TOP_STRT_ADD_VANC (0x0098)
72#define VPIF_CH1_BTM_STRT_ADD_VANC (0x009c)
73#define VPIF_CH1_SP_CFG (0x00a0)
74#define VPIF_CH1_IMG_ADD_OFST (0x00a4)
75#define VPIF_CH1_HANC_ADD_OFST (0x00a8)
76#define VPIF_CH1_H_CFG (0x00ac)
77#define VPIF_CH1_V_CFG_00 (0x00b0)
78#define VPIF_CH1_V_CFG_01 (0x00b4)
79#define VPIF_CH1_V_CFG_02 (0x00b8)
80#define VPIF_CH1_V_CFG_03 (0x00bc)
81
82#define VPIF_CH2_TOP_STRT_ADD_LUMA (0x00c0)
83#define VPIF_CH2_BTM_STRT_ADD_LUMA (0x00c4)
84#define VPIF_CH2_TOP_STRT_ADD_CHROMA (0x00c8)
85#define VPIF_CH2_BTM_STRT_ADD_CHROMA (0x00cc)
86#define VPIF_CH2_TOP_STRT_ADD_HANC (0x00d0)
87#define VPIF_CH2_BTM_STRT_ADD_HANC (0x00d4)
88#define VPIF_CH2_TOP_STRT_ADD_VANC (0x00d8)
89#define VPIF_CH2_BTM_STRT_ADD_VANC (0x00dc)
90#define VPIF_CH2_SP_CFG (0x00e0)
91#define VPIF_CH2_IMG_ADD_OFST (0x00e4)
92#define VPIF_CH2_HANC_ADD_OFST (0x00e8)
93#define VPIF_CH2_H_CFG (0x00ec)
94#define VPIF_CH2_V_CFG_00 (0x00f0)
95#define VPIF_CH2_V_CFG_01 (0x00f4)
96#define VPIF_CH2_V_CFG_02 (0x00f8)
97#define VPIF_CH2_V_CFG_03 (0x00fc)
98#define VPIF_CH2_HANC0_STRT (0x0100)
99#define VPIF_CH2_HANC0_SIZE (0x0104)
100#define VPIF_CH2_HANC1_STRT (0x0108)
101#define VPIF_CH2_HANC1_SIZE (0x010c)
102#define VPIF_CH2_VANC0_STRT (0x0110)
103#define VPIF_CH2_VANC0_SIZE (0x0114)
104#define VPIF_CH2_VANC1_STRT (0x0118)
105#define VPIF_CH2_VANC1_SIZE (0x011c)
106
107#define VPIF_CH3_TOP_STRT_ADD_LUMA (0x0140)
108#define VPIF_CH3_BTM_STRT_ADD_LUMA (0x0144)
109#define VPIF_CH3_TOP_STRT_ADD_CHROMA (0x0148)
110#define VPIF_CH3_BTM_STRT_ADD_CHROMA (0x014c)
111#define VPIF_CH3_TOP_STRT_ADD_HANC (0x0150)
112#define VPIF_CH3_BTM_STRT_ADD_HANC (0x0154)
113#define VPIF_CH3_TOP_STRT_ADD_VANC (0x0158)
114#define VPIF_CH3_BTM_STRT_ADD_VANC (0x015c)
115#define VPIF_CH3_SP_CFG (0x0160)
116#define VPIF_CH3_IMG_ADD_OFST (0x0164)
117#define VPIF_CH3_HANC_ADD_OFST (0x0168)
118#define VPIF_CH3_H_CFG (0x016c)
119#define VPIF_CH3_V_CFG_00 (0x0170)
120#define VPIF_CH3_V_CFG_01 (0x0174)
121#define VPIF_CH3_V_CFG_02 (0x0178)
122#define VPIF_CH3_V_CFG_03 (0x017c)
123#define VPIF_CH3_HANC0_STRT (0x0180)
124#define VPIF_CH3_HANC0_SIZE (0x0184)
125#define VPIF_CH3_HANC1_STRT (0x0188)
126#define VPIF_CH3_HANC1_SIZE (0x018c)
127#define VPIF_CH3_VANC0_STRT (0x0190)
128#define VPIF_CH3_VANC0_SIZE (0x0194)
129#define VPIF_CH3_VANC1_STRT (0x0198)
130#define VPIF_CH3_VANC1_SIZE (0x019c)
131
132#define VPIF_IODFT_CTRL (0x01c0)
133
134/* Functions for bit Manipulation */
135static inline void vpif_set_bit(u32 reg, u32 bit)
136{
137 regw((regr(reg)) | (0x01 << bit), reg);
138}
139
140static inline void vpif_clr_bit(u32 reg, u32 bit)
141{
142 regw(((regr(reg)) & ~(0x01 << bit)), reg);
143}
144
145/* Macro for Generating mask */
146#ifdef GENERATE_MASK
147#undef GENERATE_MASK
148#endif
149
150#define GENERATE_MASK(bits, pos) \
151 ((((0xFFFFFFFF) << (32 - bits)) >> (32 - bits)) << pos)
152
153/* Bit positions in the channel control registers */
154#define VPIF_CH_DATA_MODE_BIT (2)
155#define VPIF_CH_YC_MUX_BIT (3)
156#define VPIF_CH_SDR_FMT_BIT (4)
157#define VPIF_CH_HANC_EN_BIT (8)
158#define VPIF_CH_VANC_EN_BIT (9)
159
160#define VPIF_CAPTURE_CH_NIP (10)
161#define VPIF_DISPLAY_CH_NIP (11)
162
163#define VPIF_DISPLAY_PIX_EN_BIT (10)
164
165#define VPIF_CH_INPUT_FIELD_FRAME_BIT (12)
166
167#define VPIF_CH_FID_POLARITY_BIT (15)
168#define VPIF_CH_V_VALID_POLARITY_BIT (14)
169#define VPIF_CH_H_VALID_POLARITY_BIT (13)
170#define VPIF_CH_DATA_WIDTH_BIT (28)
171
172#define VPIF_CH_CLK_EDGE_CTRL_BIT (31)
173
174/* Mask various length */
175#define VPIF_CH_EAVSAV_MASK GENERATE_MASK(13, 0)
176#define VPIF_CH_LEN_MASK GENERATE_MASK(12, 0)
177#define VPIF_CH_WIDTH_MASK GENERATE_MASK(13, 0)
178#define VPIF_CH_LEN_SHIFT (16)
179
180/* VPIF masks for registers */
181#define VPIF_REQ_SIZE_MASK (0x1ff)
182
183/* bit posotion of interrupt vpif_ch_intr register */
184#define VPIF_INTEN_FRAME_CH0 (0x00000001)
185#define VPIF_INTEN_FRAME_CH1 (0x00000002)
186#define VPIF_INTEN_FRAME_CH2 (0x00000004)
187#define VPIF_INTEN_FRAME_CH3 (0x00000008)
188
189/* bit position of clock and channel enable in vpif_chn_ctrl register */
190
191#define VPIF_CH0_CLK_EN (0x00000002)
192#define VPIF_CH0_EN (0x00000001)
193#define VPIF_CH1_CLK_EN (0x00000002)
194#define VPIF_CH1_EN (0x00000001)
195#define VPIF_CH2_CLK_EN (0x00000002)
196#define VPIF_CH2_EN (0x00000001)
197#define VPIF_CH3_CLK_EN (0x00000002)
198#define VPIF_CH3_EN (0x00000001)
199#define VPIF_CH_CLK_EN (0x00000002)
200#define VPIF_CH_EN (0x00000001)
201
202#define VPIF_INT_TOP (0x00)
203#define VPIF_INT_BOTTOM (0x01)
204#define VPIF_INT_BOTH (0x02)
205
206#define VPIF_CH0_INT_CTRL_SHIFT (6)
207#define VPIF_CH1_INT_CTRL_SHIFT (6)
208#define VPIF_CH2_INT_CTRL_SHIFT (6)
209#define VPIF_CH3_INT_CTRL_SHIFT (6)
210#define VPIF_CH_INT_CTRL_SHIFT (6)
211
212/* enabled interrupt on both the fields on vpid_ch0_ctrl register */
213#define channel0_intr_assert() (regw((regr(VPIF_CH0_CTRL)|\
214 (VPIF_INT_BOTH << VPIF_CH0_INT_CTRL_SHIFT)), VPIF_CH0_CTRL))
215
216/* enabled interrupt on both the fields on vpid_ch1_ctrl register */
217#define channel1_intr_assert() (regw((regr(VPIF_CH1_CTRL)|\
218 (VPIF_INT_BOTH << VPIF_CH1_INT_CTRL_SHIFT)), VPIF_CH1_CTRL))
219
220/* enabled interrupt on both the fields on vpid_ch0_ctrl register */
221#define channel2_intr_assert() (regw((regr(VPIF_CH2_CTRL)|\
222 (VPIF_INT_BOTH << VPIF_CH2_INT_CTRL_SHIFT)), VPIF_CH2_CTRL))
223
224/* enabled interrupt on both the fields on vpid_ch1_ctrl register */
225#define channel3_intr_assert() (regw((regr(VPIF_CH3_CTRL)|\
226 (VPIF_INT_BOTH << VPIF_CH3_INT_CTRL_SHIFT)), VPIF_CH3_CTRL))
227
228#define VPIF_CH_FID_MASK (0x20)
229#define VPIF_CH_FID_SHIFT (5)
230
231#define VPIF_NTSC_VBI_START_FIELD0 (1)
232#define VPIF_NTSC_VBI_START_FIELD1 (263)
233#define VPIF_PAL_VBI_START_FIELD0 (624)
234#define VPIF_PAL_VBI_START_FIELD1 (311)
235
236#define VPIF_NTSC_HBI_START_FIELD0 (1)
237#define VPIF_NTSC_HBI_START_FIELD1 (263)
238#define VPIF_PAL_HBI_START_FIELD0 (624)
239#define VPIF_PAL_HBI_START_FIELD1 (311)
240
241#define VPIF_NTSC_VBI_COUNT_FIELD0 (20)
242#define VPIF_NTSC_VBI_COUNT_FIELD1 (19)
243#define VPIF_PAL_VBI_COUNT_FIELD0 (24)
244#define VPIF_PAL_VBI_COUNT_FIELD1 (25)
245
246#define VPIF_NTSC_HBI_COUNT_FIELD0 (263)
247#define VPIF_NTSC_HBI_COUNT_FIELD1 (262)
248#define VPIF_PAL_HBI_COUNT_FIELD0 (312)
249#define VPIF_PAL_HBI_COUNT_FIELD1 (313)
250
251#define VPIF_NTSC_VBI_SAMPLES_PER_LINE (720)
252#define VPIF_PAL_VBI_SAMPLES_PER_LINE (720)
253#define VPIF_NTSC_HBI_SAMPLES_PER_LINE (268)
254#define VPIF_PAL_HBI_SAMPLES_PER_LINE (280)
255
256#define VPIF_CH_VANC_EN (0x20)
257#define VPIF_DMA_REQ_SIZE (0x080)
258#define VPIF_EMULATION_DISABLE (0x01)
259
260extern u8 irq_vpif_capture_channel[VPIF_NUM_CHANNELS];
261
262/* inline function to enable/disable channel0 */
263static inline void enable_channel0(int enable)
264{
265 if (enable)
266 regw((regr(VPIF_CH0_CTRL) | (VPIF_CH0_EN)), VPIF_CH0_CTRL);
267 else
268 regw((regr(VPIF_CH0_CTRL) & (~VPIF_CH0_EN)), VPIF_CH0_CTRL);
269}
270
271/* inline function to enable/disable channel1 */
272static inline void enable_channel1(int enable)
273{
274 if (enable)
275 regw((regr(VPIF_CH1_CTRL) | (VPIF_CH1_EN)), VPIF_CH1_CTRL);
276 else
277 regw((regr(VPIF_CH1_CTRL) & (~VPIF_CH1_EN)), VPIF_CH1_CTRL);
278}
279
280/* inline function to enable interrupt for channel0 */
281static inline void channel0_intr_enable(int enable)
282{
283 if (enable) {
284 regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);
285 regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);
286
287 regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH0), VPIF_INTEN);
288 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0),
289 VPIF_INTEN_SET);
290 } else {
291 regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH0)), VPIF_INTEN);
292 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH0),
293 VPIF_INTEN_SET);
294 }
295}
296
297/* inline function to enable interrupt for channel1 */
298static inline void channel1_intr_enable(int enable)
299{
300 if (enable) {
301 regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);
302 regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);
303
304 regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH1), VPIF_INTEN);
305 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1),
306 VPIF_INTEN_SET);
307 } else {
308 regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH1)), VPIF_INTEN);
309 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH1),
310 VPIF_INTEN_SET);
311 }
312}
313
314/* inline function to set buffer addresses in case of Y/C non mux mode */
315static inline void ch0_set_videobuf_addr_yc_nmux(unsigned long top_strt_luma,
316 unsigned long btm_strt_luma,
317 unsigned long top_strt_chroma,
318 unsigned long btm_strt_chroma)
319{
320 regw(top_strt_luma, VPIF_CH0_TOP_STRT_ADD_LUMA);
321 regw(btm_strt_luma, VPIF_CH0_BTM_STRT_ADD_LUMA);
322 regw(top_strt_chroma, VPIF_CH1_TOP_STRT_ADD_CHROMA);
323 regw(btm_strt_chroma, VPIF_CH1_BTM_STRT_ADD_CHROMA);
324}
325
326/* inline function to set buffer addresses in VPIF registers for video data */
327static inline void ch0_set_videobuf_addr(unsigned long top_strt_luma,
328 unsigned long btm_strt_luma,
329 unsigned long top_strt_chroma,
330 unsigned long btm_strt_chroma)
331{
332 regw(top_strt_luma, VPIF_CH0_TOP_STRT_ADD_LUMA);
333 regw(btm_strt_luma, VPIF_CH0_BTM_STRT_ADD_LUMA);
334 regw(top_strt_chroma, VPIF_CH0_TOP_STRT_ADD_CHROMA);
335 regw(btm_strt_chroma, VPIF_CH0_BTM_STRT_ADD_CHROMA);
336}
337
338static inline void ch1_set_videobuf_addr(unsigned long top_strt_luma,
339 unsigned long btm_strt_luma,
340 unsigned long top_strt_chroma,
341 unsigned long btm_strt_chroma)
342{
343
344 regw(top_strt_luma, VPIF_CH1_TOP_STRT_ADD_LUMA);
345 regw(btm_strt_luma, VPIF_CH1_BTM_STRT_ADD_LUMA);
346 regw(top_strt_chroma, VPIF_CH1_TOP_STRT_ADD_CHROMA);
347 regw(btm_strt_chroma, VPIF_CH1_BTM_STRT_ADD_CHROMA);
348}
349
350static inline void ch0_set_vbi_addr(unsigned long top_vbi,
351 unsigned long btm_vbi, unsigned long a, unsigned long b)
352{
353 regw(top_vbi, VPIF_CH0_TOP_STRT_ADD_VANC);
354 regw(btm_vbi, VPIF_CH0_BTM_STRT_ADD_VANC);
355}
356
357static inline void ch0_set_hbi_addr(unsigned long top_vbi,
358 unsigned long btm_vbi, unsigned long a, unsigned long b)
359{
360 regw(top_vbi, VPIF_CH0_TOP_STRT_ADD_HANC);
361 regw(btm_vbi, VPIF_CH0_BTM_STRT_ADD_HANC);
362}
363
364static inline void ch1_set_vbi_addr(unsigned long top_vbi,
365 unsigned long btm_vbi, unsigned long a, unsigned long b)
366{
367 regw(top_vbi, VPIF_CH1_TOP_STRT_ADD_VANC);
368 regw(btm_vbi, VPIF_CH1_BTM_STRT_ADD_VANC);
369}
370
371static inline void ch1_set_hbi_addr(unsigned long top_vbi,
372 unsigned long btm_vbi, unsigned long a, unsigned long b)
373{
374 regw(top_vbi, VPIF_CH1_TOP_STRT_ADD_HANC);
375 regw(btm_vbi, VPIF_CH1_BTM_STRT_ADD_HANC);
376}
377
378/* Inline function to enable raw vbi in the given channel */
379static inline void disable_raw_feature(u8 channel_id, u8 index)
380{
381 u32 ctrl_reg;
382 if (0 == channel_id)
383 ctrl_reg = VPIF_CH0_CTRL;
384 else
385 ctrl_reg = VPIF_CH1_CTRL;
386
387 if (1 == index)
388 vpif_clr_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT);
389 else
390 vpif_clr_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT);
391}
392
393static inline void enable_raw_feature(u8 channel_id, u8 index)
394{
395 u32 ctrl_reg;
396 if (0 == channel_id)
397 ctrl_reg = VPIF_CH0_CTRL;
398 else
399 ctrl_reg = VPIF_CH1_CTRL;
400
401 if (1 == index)
402 vpif_set_bit(ctrl_reg, VPIF_CH_VANC_EN_BIT);
403 else
404 vpif_set_bit(ctrl_reg, VPIF_CH_HANC_EN_BIT);
405}
406
407/* inline function to enable/disable channel2 */
408static inline void enable_channel2(int enable)
409{
410 if (enable) {
411 regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL);
412 regw((regr(VPIF_CH2_CTRL) | (VPIF_CH2_EN)), VPIF_CH2_CTRL);
413 } else {
414 regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_CLK_EN)), VPIF_CH2_CTRL);
415 regw((regr(VPIF_CH2_CTRL) & (~VPIF_CH2_EN)), VPIF_CH2_CTRL);
416 }
417}
418
419/* inline function to enable/disable channel3 */
420static inline void enable_channel3(int enable)
421{
422 if (enable) {
423 regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL);
424 regw((regr(VPIF_CH3_CTRL) | (VPIF_CH3_EN)), VPIF_CH3_CTRL);
425 } else {
426 regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_CLK_EN)), VPIF_CH3_CTRL);
427 regw((regr(VPIF_CH3_CTRL) & (~VPIF_CH3_EN)), VPIF_CH3_CTRL);
428 }
429}
430
431/* inline function to enable interrupt for channel2 */
432static inline void channel2_intr_enable(int enable)
433{
434 if (enable) {
435 regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);
436 regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);
437 regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH2), VPIF_INTEN);
438 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2),
439 VPIF_INTEN_SET);
440 } else {
441 regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH2)), VPIF_INTEN);
442 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH2),
443 VPIF_INTEN_SET);
444 }
445}
446
447/* inline function to enable interrupt for channel3 */
448static inline void channel3_intr_enable(int enable)
449{
450 if (enable) {
451 regw((regr(VPIF_INTEN) | 0x10), VPIF_INTEN);
452 regw((regr(VPIF_INTEN_SET) | 0x10), VPIF_INTEN_SET);
453
454 regw((regr(VPIF_INTEN) | VPIF_INTEN_FRAME_CH3), VPIF_INTEN);
455 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3),
456 VPIF_INTEN_SET);
457 } else {
458 regw((regr(VPIF_INTEN) & (~VPIF_INTEN_FRAME_CH3)), VPIF_INTEN);
459 regw((regr(VPIF_INTEN_SET) | VPIF_INTEN_FRAME_CH3),
460 VPIF_INTEN_SET);
461 }
462}
463
464/* inline function to enable raw vbi data for channel2 */
465static inline void channel2_raw_enable(int enable, u8 index)
466{
467 u32 mask;
468
469 if (1 == index)
470 mask = VPIF_CH_VANC_EN_BIT;
471 else
472 mask = VPIF_CH_HANC_EN_BIT;
473
474 if (enable)
475 vpif_set_bit(VPIF_CH2_CTRL, mask);
476 else
477 vpif_clr_bit(VPIF_CH2_CTRL, mask);
478}
479
480/* inline function to enable raw vbi data for channel3*/
481static inline void channel3_raw_enable(int enable, u8 index)
482{
483 u32 mask;
484
485 if (1 == index)
486 mask = VPIF_CH_VANC_EN_BIT;
487 else
488 mask = VPIF_CH_HANC_EN_BIT;
489
490 if (enable)
491 vpif_set_bit(VPIF_CH3_CTRL, mask);
492 else
493 vpif_clr_bit(VPIF_CH3_CTRL, mask);
494}
495
496/* inline function to set buffer addresses in case of Y/C non mux mode */
497static inline void ch2_set_videobuf_addr_yc_nmux(unsigned long top_strt_luma,
498 unsigned long btm_strt_luma,
499 unsigned long top_strt_chroma,
500 unsigned long btm_strt_chroma)
501{
502 regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_LUMA);
503 regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_LUMA);
504 regw(top_strt_chroma, VPIF_CH3_TOP_STRT_ADD_CHROMA);
505 regw(btm_strt_chroma, VPIF_CH3_BTM_STRT_ADD_CHROMA);
506}
507
508/* inline function to set buffer addresses in VPIF registers for video data */
509static inline void ch2_set_videobuf_addr(unsigned long top_strt_luma,
510 unsigned long btm_strt_luma,
511 unsigned long top_strt_chroma,
512 unsigned long btm_strt_chroma)
513{
514 regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_LUMA);
515 regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_LUMA);
516 regw(top_strt_chroma, VPIF_CH2_TOP_STRT_ADD_CHROMA);
517 regw(btm_strt_chroma, VPIF_CH2_BTM_STRT_ADD_CHROMA);
518}
519
520static inline void ch3_set_videobuf_addr(unsigned long top_strt_luma,
521 unsigned long btm_strt_luma,
522 unsigned long top_strt_chroma,
523 unsigned long btm_strt_chroma)
524{
525 regw(top_strt_luma, VPIF_CH3_TOP_STRT_ADD_LUMA);
526 regw(btm_strt_luma, VPIF_CH3_BTM_STRT_ADD_LUMA);
527 regw(top_strt_chroma, VPIF_CH3_TOP_STRT_ADD_CHROMA);
528 regw(btm_strt_chroma, VPIF_CH3_BTM_STRT_ADD_CHROMA);
529}
530
531/* inline function to set buffer addresses in VPIF registers for vbi data */
532static inline void ch2_set_vbi_addr(unsigned long top_strt_luma,
533 unsigned long btm_strt_luma,
534 unsigned long top_strt_chroma,
535 unsigned long btm_strt_chroma)
536{
537 regw(top_strt_luma, VPIF_CH2_TOP_STRT_ADD_VANC);
538 regw(btm_strt_luma, VPIF_CH2_BTM_STRT_ADD_VANC);
539}
540
541static inline void ch3_set_vbi_addr(unsigned long top_strt_luma,
542 unsigned long btm_strt_luma,
543 unsigned long top_strt_chroma,
544 unsigned long btm_strt_chroma)
545{
546 regw(top_strt_luma, VPIF_CH3_TOP_STRT_ADD_VANC);
547 regw(btm_strt_luma, VPIF_CH3_BTM_STRT_ADD_VANC);
548}
549
550#define VPIF_MAX_NAME (30)
551
552/* This structure will store size parameters as per the mode selected by user */
553struct vpif_channel_config_params {
554 char name[VPIF_MAX_NAME]; /* Name of the mode */
555 u16 width; /* Indicates width of the image */
556 u16 height; /* Indicates height of the image */
557 u8 fps;
558 u8 frm_fmt; /* Indicates whether this is interlaced
559 * or progressive format */
560 u8 ycmux_mode; /* Indicates whether this mode requires
561 * single or two channels */
562 u16 eav2sav; /* length of sav 2 eav */
563 u16 sav2eav; /* length of sav 2 eav */
564 u16 l1, l3, l5, l7, l9, l11; /* Other parameter configurations */
565 u16 vsize; /* Vertical size of the image */
566 u8 capture_format; /* Indicates whether capture format
567 * is in BT or in CCD/CMOS */
568 u8 vbi_supported; /* Indicates whether this mode
569 * supports capturing vbi or not */
570 u8 hd_sd;
571 v4l2_std_id stdid;
572};
573
574struct vpif_interface;
575struct vpif_params;
576struct vpif_vbi_params;
577
578int vpif_set_video_params(struct vpif_params *vpifparams, u8 channel_id);
579void vpif_set_vbi_display_params(struct vpif_vbi_params *vbiparams,
580 u8 channel_id);
581int vpif_channel_getfid(u8 channel_id);
582void vpif_base_addr_init(void __iomem *base);
583
584/* Enumerated data types */
585enum vpif_capture_pinpol {
586 VPIF_CAPTURE_PINPOL_SAME = 0,
587 VPIF_CAPTURE_PINPOL_INVERT = 1
588};
589
590enum data_size {
591 _8BITS = 0,
592 _10BITS,
593 _12BITS,
594};
595
596struct vpif_capture_params_raw {
597 enum data_size data_sz;
598 enum vpif_capture_pinpol fid_pol;
599 enum vpif_capture_pinpol vd_pol;
600 enum vpif_capture_pinpol hd_pol;
601};
602
603/* Structure for vpif parameters for raw vbi data */
604struct vpif_vbi_params {
605 __u32 hstart0; /* Horizontal start of raw vbi data for first field */
606 __u32 vstart0; /* Vertical start of raw vbi data for first field */
607 __u32 hsize0; /* Horizontal size of raw vbi data for first field */
608 __u32 vsize0; /* Vertical size of raw vbi data for first field */
609 __u32 hstart1; /* Horizontal start of raw vbi data for second field */
610 __u32 vstart1; /* Vertical start of raw vbi data for second field */
611 __u32 hsize1; /* Horizontal size of raw vbi data for second field */
612 __u32 vsize1; /* Vertical size of raw vbi data for second field */
613};
614
615/* structure for vpif parameters */
616struct vpif_interface {
617 __u8 storage_mode; /* Indicates field or frame mode */
618 unsigned long hpitch;
619 v4l2_std_id stdid;
620};
621
622struct vpif_params {
623 struct vpif_interface video_params;
624 struct vpif_channel_config_params std_info;
625 union param {
626 struct vpif_vbi_params vbi_params;
627 struct vpif_capture_params_raw raw_params;
628 } params;
629};
630
631#endif /* End of #ifndef VPIF_H */
632
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 08:33:33 -0500