diff options
author | Andy Walls <awalls@md.metrocast.net> | 2010-07-31 20:57:42 -0400 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2010-08-08 22:42:56 -0400 |
commit | ceb152add687db152d90ba64b54687b3975963cf (patch) | |
tree | c835baf20ce8851187c9ec6142d22189d9203cbc /drivers/media/video | |
parent | 0c82a8fb5a306eac83d536445a77b6523c71d5e4 (diff) |
V4L/DVB: cx23885, cx25840: Report IR max pulse width regardless of mod/demod use
Compute and report the maximum IR pulse measurment width, even
if we are set to perform carrier modulation or demodulation and
the number is fixed by the carrier freq.
Signed-off-by: Andy Walls <awalls@md.metrocast.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/video')
-rw-r--r-- | drivers/media/video/cx23885/cx23888-ir.c | 26 | ||||
-rw-r--r-- | drivers/media/video/cx25840/cx25840-ir.c | 26 |
2 files changed, 28 insertions, 24 deletions
diff --git a/drivers/media/video/cx23885/cx23888-ir.c b/drivers/media/video/cx23885/cx23888-ir.c index 51f21636e639..aa07286b8d9b 100644 --- a/drivers/media/video/cx23885/cx23888-ir.c +++ b/drivers/media/video/cx23885/cx23888-ir.c | |||
@@ -771,12 +771,15 @@ static int cx23888_ir_rx_s_parameters(struct v4l2_subdev *sd, | |||
771 | &p->carrier_range_upper); | 771 | &p->carrier_range_upper); |
772 | o->carrier_range_lower = p->carrier_range_lower; | 772 | o->carrier_range_lower = p->carrier_range_lower; |
773 | o->carrier_range_upper = p->carrier_range_upper; | 773 | o->carrier_range_upper = p->carrier_range_upper; |
774 | |||
775 | p->max_pulse_width = | ||
776 | (u32) pulse_width_count_to_ns(FIFO_RXTX, rxclk_divider); | ||
774 | } else { | 777 | } else { |
775 | p->max_pulse_width = | 778 | p->max_pulse_width = |
776 | rxclk_rx_s_max_pulse_width(dev, p->max_pulse_width, | 779 | rxclk_rx_s_max_pulse_width(dev, p->max_pulse_width, |
777 | &rxclk_divider); | 780 | &rxclk_divider); |
778 | o->max_pulse_width = p->max_pulse_width; | ||
779 | } | 781 | } |
782 | o->max_pulse_width = p->max_pulse_width; | ||
780 | atomic_set(&state->rxclk_divider, rxclk_divider); | 783 | atomic_set(&state->rxclk_divider, rxclk_divider); |
781 | 784 | ||
782 | p->noise_filter_min_width = | 785 | p->noise_filter_min_width = |
@@ -889,12 +892,15 @@ static int cx23888_ir_tx_s_parameters(struct v4l2_subdev *sd, | |||
889 | 892 | ||
890 | p->duty_cycle = cduty_tx_s_duty_cycle(dev, p->duty_cycle); | 893 | p->duty_cycle = cduty_tx_s_duty_cycle(dev, p->duty_cycle); |
891 | o->duty_cycle = p->duty_cycle; | 894 | o->duty_cycle = p->duty_cycle; |
895 | |||
896 | p->max_pulse_width = | ||
897 | (u32) pulse_width_count_to_ns(FIFO_RXTX, txclk_divider); | ||
892 | } else { | 898 | } else { |
893 | p->max_pulse_width = | 899 | p->max_pulse_width = |
894 | txclk_tx_s_max_pulse_width(dev, p->max_pulse_width, | 900 | txclk_tx_s_max_pulse_width(dev, p->max_pulse_width, |
895 | &txclk_divider); | 901 | &txclk_divider); |
896 | o->max_pulse_width = p->max_pulse_width; | ||
897 | } | 902 | } |
903 | o->max_pulse_width = p->max_pulse_width; | ||
898 | atomic_set(&state->txclk_divider, txclk_divider); | 904 | atomic_set(&state->txclk_divider, txclk_divider); |
899 | 905 | ||
900 | p->resolution = clock_divider_to_resolution(txclk_divider); | 906 | p->resolution = clock_divider_to_resolution(txclk_divider); |
@@ -1000,12 +1006,10 @@ static int cx23888_ir_log_status(struct v4l2_subdev *sd) | |||
1000 | "-%1d/+%1d, %u to %u Hz\n", i, j, | 1006 | "-%1d/+%1d, %u to %u Hz\n", i, j, |
1001 | clock_divider_to_freq(rxclk, 16 + j), | 1007 | clock_divider_to_freq(rxclk, 16 + j), |
1002 | clock_divider_to_freq(rxclk, 16 - i)); | 1008 | clock_divider_to_freq(rxclk, 16 - i)); |
1003 | } else { | ||
1004 | v4l2_info(sd, "\tMax measurable pulse width: %u us, " | ||
1005 | "%llu ns\n", | ||
1006 | pulse_width_count_to_us(FIFO_RXTX, rxclk), | ||
1007 | pulse_width_count_to_ns(FIFO_RXTX, rxclk)); | ||
1008 | } | 1009 | } |
1010 | v4l2_info(sd, "\tMax measurable pulse width: %u us, %llu ns\n", | ||
1011 | pulse_width_count_to_us(FIFO_RXTX, rxclk), | ||
1012 | pulse_width_count_to_ns(FIFO_RXTX, rxclk)); | ||
1009 | v4l2_info(sd, "\tLow pass filter: %s\n", | 1013 | v4l2_info(sd, "\tLow pass filter: %s\n", |
1010 | filtr ? "enabled" : "disabled"); | 1014 | filtr ? "enabled" : "disabled"); |
1011 | if (filtr) | 1015 | if (filtr) |
@@ -1047,12 +1051,10 @@ static int cx23888_ir_log_status(struct v4l2_subdev *sd) | |||
1047 | clock_divider_to_carrier_freq(txclk)); | 1051 | clock_divider_to_carrier_freq(txclk)); |
1048 | v4l2_info(sd, "\tCarrier duty cycle: %2u/16\n", | 1052 | v4l2_info(sd, "\tCarrier duty cycle: %2u/16\n", |
1049 | cduty + 1); | 1053 | cduty + 1); |
1050 | } else { | ||
1051 | v4l2_info(sd, "\tMax pulse width: %u us, " | ||
1052 | "%llu ns\n", | ||
1053 | pulse_width_count_to_us(FIFO_RXTX, txclk), | ||
1054 | pulse_width_count_to_ns(FIFO_RXTX, txclk)); | ||
1055 | } | 1054 | } |
1055 | v4l2_info(sd, "\tMax pulse width: %u us, %llu ns\n", | ||
1056 | pulse_width_count_to_us(FIFO_RXTX, txclk), | ||
1057 | pulse_width_count_to_ns(FIFO_RXTX, txclk)); | ||
1056 | v4l2_info(sd, "\tBusy: %s\n", | 1058 | v4l2_info(sd, "\tBusy: %s\n", |
1057 | stats & STATS_TBY ? "yes" : "no"); | 1059 | stats & STATS_TBY ? "yes" : "no"); |
1058 | v4l2_info(sd, "\tFIFO service requested: %s\n", | 1060 | v4l2_info(sd, "\tFIFO service requested: %s\n", |
diff --git a/drivers/media/video/cx25840/cx25840-ir.c b/drivers/media/video/cx25840/cx25840-ir.c index 308e87e9fae7..326c2554c05c 100644 --- a/drivers/media/video/cx25840/cx25840-ir.c +++ b/drivers/media/video/cx25840/cx25840-ir.c | |||
@@ -791,12 +791,15 @@ static int cx25840_ir_rx_s_parameters(struct v4l2_subdev *sd, | |||
791 | &p->carrier_range_upper); | 791 | &p->carrier_range_upper); |
792 | o->carrier_range_lower = p->carrier_range_lower; | 792 | o->carrier_range_lower = p->carrier_range_lower; |
793 | o->carrier_range_upper = p->carrier_range_upper; | 793 | o->carrier_range_upper = p->carrier_range_upper; |
794 | |||
795 | p->max_pulse_width = | ||
796 | (u32) pulse_width_count_to_ns(FIFO_RXTX, rxclk_divider); | ||
794 | } else { | 797 | } else { |
795 | p->max_pulse_width = | 798 | p->max_pulse_width = |
796 | rxclk_rx_s_max_pulse_width(c, p->max_pulse_width, | 799 | rxclk_rx_s_max_pulse_width(c, p->max_pulse_width, |
797 | &rxclk_divider); | 800 | &rxclk_divider); |
798 | o->max_pulse_width = p->max_pulse_width; | ||
799 | } | 801 | } |
802 | o->max_pulse_width = p->max_pulse_width; | ||
800 | atomic_set(&ir_state->rxclk_divider, rxclk_divider); | 803 | atomic_set(&ir_state->rxclk_divider, rxclk_divider); |
801 | 804 | ||
802 | p->noise_filter_min_width = | 805 | p->noise_filter_min_width = |
@@ -970,12 +973,15 @@ static int cx25840_ir_tx_s_parameters(struct v4l2_subdev *sd, | |||
970 | 973 | ||
971 | p->duty_cycle = cduty_tx_s_duty_cycle(c, p->duty_cycle); | 974 | p->duty_cycle = cduty_tx_s_duty_cycle(c, p->duty_cycle); |
972 | o->duty_cycle = p->duty_cycle; | 975 | o->duty_cycle = p->duty_cycle; |
976 | |||
977 | p->max_pulse_width = | ||
978 | (u32) pulse_width_count_to_ns(FIFO_RXTX, txclk_divider); | ||
973 | } else { | 979 | } else { |
974 | p->max_pulse_width = | 980 | p->max_pulse_width = |
975 | txclk_tx_s_max_pulse_width(c, p->max_pulse_width, | 981 | txclk_tx_s_max_pulse_width(c, p->max_pulse_width, |
976 | &txclk_divider); | 982 | &txclk_divider); |
977 | o->max_pulse_width = p->max_pulse_width; | ||
978 | } | 983 | } |
984 | o->max_pulse_width = p->max_pulse_width; | ||
979 | atomic_set(&ir_state->txclk_divider, txclk_divider); | 985 | atomic_set(&ir_state->txclk_divider, txclk_divider); |
980 | 986 | ||
981 | p->resolution = clock_divider_to_resolution(txclk_divider); | 987 | p->resolution = clock_divider_to_resolution(txclk_divider); |
@@ -1094,12 +1100,10 @@ int cx25840_ir_log_status(struct v4l2_subdev *sd) | |||
1094 | "-%1d/+%1d, %u to %u Hz\n", i, j, | 1100 | "-%1d/+%1d, %u to %u Hz\n", i, j, |
1095 | clock_divider_to_freq(rxclk, 16 + j), | 1101 | clock_divider_to_freq(rxclk, 16 + j), |
1096 | clock_divider_to_freq(rxclk, 16 - i)); | 1102 | clock_divider_to_freq(rxclk, 16 - i)); |
1097 | } else { | ||
1098 | v4l2_info(sd, "\tMax measurable pulse width: %u us, " | ||
1099 | "%llu ns\n", | ||
1100 | pulse_width_count_to_us(FIFO_RXTX, rxclk), | ||
1101 | pulse_width_count_to_ns(FIFO_RXTX, rxclk)); | ||
1102 | } | 1103 | } |
1104 | v4l2_info(sd, "\tMax measurable pulse width: %u us, %llu ns\n", | ||
1105 | pulse_width_count_to_us(FIFO_RXTX, rxclk), | ||
1106 | pulse_width_count_to_ns(FIFO_RXTX, rxclk)); | ||
1103 | v4l2_info(sd, "\tLow pass filter: %s\n", | 1107 | v4l2_info(sd, "\tLow pass filter: %s\n", |
1104 | filtr ? "enabled" : "disabled"); | 1108 | filtr ? "enabled" : "disabled"); |
1105 | if (filtr) | 1109 | if (filtr) |
@@ -1139,12 +1143,10 @@ int cx25840_ir_log_status(struct v4l2_subdev *sd) | |||
1139 | clock_divider_to_carrier_freq(txclk)); | 1143 | clock_divider_to_carrier_freq(txclk)); |
1140 | v4l2_info(sd, "\tCarrier duty cycle: %2u/16\n", | 1144 | v4l2_info(sd, "\tCarrier duty cycle: %2u/16\n", |
1141 | cduty + 1); | 1145 | cduty + 1); |
1142 | } else { | ||
1143 | v4l2_info(sd, "\tMax pulse width: %u us, " | ||
1144 | "%llu ns\n", | ||
1145 | pulse_width_count_to_us(FIFO_RXTX, txclk), | ||
1146 | pulse_width_count_to_ns(FIFO_RXTX, txclk)); | ||
1147 | } | 1146 | } |
1147 | v4l2_info(sd, "\tMax pulse width: %u us, %llu ns\n", | ||
1148 | pulse_width_count_to_us(FIFO_RXTX, txclk), | ||
1149 | pulse_width_count_to_ns(FIFO_RXTX, txclk)); | ||
1148 | v4l2_info(sd, "\tBusy: %s\n", | 1150 | v4l2_info(sd, "\tBusy: %s\n", |
1149 | stats & STATS_TBY ? "yes" : "no"); | 1151 | stats & STATS_TBY ? "yes" : "no"); |
1150 | v4l2_info(sd, "\tFIFO service requested: %s\n", | 1152 | v4l2_info(sd, "\tFIFO service requested: %s\n", |