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authorEric Miao <eric.y.miao@gmail.com>2009-01-02 10:16:02 -0500
committerMauro Carvalho Chehab <mchehab@redhat.com>2009-01-07 19:18:55 -0500
commitcfbaf4dfe765ae33e1a26b3eb0eda64ff00fc481 (patch)
treec53de3e63754229994f19a08e41381936db198b4 /drivers/media/video
parentc0cd5010e54e52931c321ee66d81d10a8e2a9ff6 (diff)
V4L/DVB (10176b): pxa-camera: fix redefinition warnings and missing DMA definitions
1. now pxa_camera.c uses ioremap() for register access, pxa_camera.h is totally useless. Remove it. 2. <asm/dma.h> does no longer include <mach/dma.h>, include the latter file explicitly delete mode 100644 drivers/media/video/pxa_camera.h Signed-off-by: Eric Miao <eric.miao@marvell.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/video')
-rw-r--r--drivers/media/video/pxa_camera.c4
-rw-r--r--drivers/media/video/pxa_camera.h95
2 files changed, 1 insertions, 98 deletions
diff --git a/drivers/media/video/pxa_camera.c b/drivers/media/video/pxa_camera.c
index 9d33de22cc48..a1d6008efcbb 100644
--- a/drivers/media/video/pxa_camera.c
+++ b/drivers/media/video/pxa_camera.c
@@ -34,12 +34,10 @@
34 34
35#include <linux/videodev2.h> 35#include <linux/videodev2.h>
36 36
37#include <asm/dma.h> 37#include <mach/dma.h>
38#include <mach/pxa-regs.h> 38#include <mach/pxa-regs.h>
39#include <mach/camera.h> 39#include <mach/camera.h>
40 40
41#include "pxa_camera.h"
42
43#define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5) 41#define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
44#define PXA_CAM_DRV_NAME "pxa27x-camera" 42#define PXA_CAM_DRV_NAME "pxa27x-camera"
45 43
diff --git a/drivers/media/video/pxa_camera.h b/drivers/media/video/pxa_camera.h
deleted file mode 100644
index 89cbfc9a35c5..000000000000
--- a/drivers/media/video/pxa_camera.h
+++ /dev/null
@@ -1,95 +0,0 @@
1/* Camera Interface */
2#define CICR0 __REG(0x50000000)
3#define CICR1 __REG(0x50000004)
4#define CICR2 __REG(0x50000008)
5#define CICR3 __REG(0x5000000C)
6#define CICR4 __REG(0x50000010)
7#define CISR __REG(0x50000014)
8#define CIFR __REG(0x50000018)
9#define CITOR __REG(0x5000001C)
10#define CIBR0 __REG(0x50000028)
11#define CIBR1 __REG(0x50000030)
12#define CIBR2 __REG(0x50000038)
13
14#define CICR0_DMAEN (1 << 31) /* DMA request enable */
15#define CICR0_PAR_EN (1 << 30) /* Parity enable */
16#define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
17#define CICR0_ENB (1 << 28) /* Camera interface enable */
18#define CICR0_DIS (1 << 27) /* Camera interface disable */
19#define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
20#define CICR0_TOM (1 << 9) /* Time-out mask */
21#define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
22#define CICR0_FEM (1 << 7) /* FIFO-empty mask */
23#define CICR0_EOLM (1 << 6) /* End-of-line mask */
24#define CICR0_PERRM (1 << 5) /* Parity-error mask */
25#define CICR0_QDM (1 << 4) /* Quick-disable mask */
26#define CICR0_CDM (1 << 3) /* Disable-done mask */
27#define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
28#define CICR0_EOFM (1 << 1) /* End-of-frame mask */
29#define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
30
31#define CICR1_TBIT (1 << 31) /* Transparency bit */
32#define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
33#define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
34#define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
35#define CICR1_RGB_F (1 << 11) /* RGB format */
36#define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
37#define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
38#define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
39#define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
40#define CICR1_DW (0x7 << 0) /* Data width mask */
41
42#define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
43 wait count mask */
44#define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
45 wait count mask */
46#define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
47#define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
48 wait count mask */
49#define CICR2_FSW (0x7 << 0) /* Frame stabilization
50 wait count mask */
51
52#define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
53 wait count mask */
54#define CICR3_EFW (0xff << 16) /* End-of-frame line clock
55 wait count mask */
56#define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
57#define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
58 wait count mask */
59#define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
60
61#define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
62#define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
63#define CICR4_PCP (1 << 22) /* Pixel clock polarity */
64#define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
65#define CICR4_VSP (1 << 20) /* Vertical sync polarity */
66#define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
67#define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
68#define CICR4_DIV (0xff << 0) /* Clock divisor mask */
69
70#define CISR_FTO (1 << 15) /* FIFO time-out */
71#define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
72#define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
73#define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
74#define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
75#define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
76#define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
77#define CISR_EOL (1 << 8) /* End of line */
78#define CISR_PAR_ERR (1 << 7) /* Parity error */
79#define CISR_CQD (1 << 6) /* Camera interface quick disable */
80#define CISR_CDD (1 << 5) /* Camera interface disable done */
81#define CISR_SOF (1 << 4) /* Start of frame */
82#define CISR_EOF (1 << 3) /* End of frame */
83#define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
84#define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
85#define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
86
87#define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
88#define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
89#define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
90#define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
91#define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
92#define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
93#define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
94#define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
95
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