diff options
author | Hans Verkuil <hverkuil@xs4all.nl> | 2008-10-09 04:51:22 -0400 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2008-10-12 07:39:04 -0400 |
commit | 45d011031d745d2c9a21c21d289428cb7f88a2d0 (patch) | |
tree | f9d8cf3b8dd12541396b3a2b867d7ad8c8207490 /drivers/media/video/zr36060.h | |
parent | 19c309e383610453604092473287f77233f31e90 (diff) |
V4L/DVB (9129): zoran: move zoran sources into a zoran subdirectory
Prevent the zoran driver sources from cluttering the video directory.
This changeset only moves the drivers and it does not fix any of the
checkpatch warnings/errors to keep the changeset clean.
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/video/zr36060.h')
-rw-r--r-- | drivers/media/video/zr36060.h | 220 |
1 files changed, 0 insertions, 220 deletions
diff --git a/drivers/media/video/zr36060.h b/drivers/media/video/zr36060.h deleted file mode 100644 index 914ffa4ad8d3..000000000000 --- a/drivers/media/video/zr36060.h +++ /dev/null | |||
@@ -1,220 +0,0 @@ | |||
1 | /* | ||
2 | * Zoran ZR36060 basic configuration functions - header file | ||
3 | * | ||
4 | * Copyright (C) 2002 Laurent Pinchart <laurent.pinchart@skynet.be> | ||
5 | * | ||
6 | * $Id: zr36060.h,v 1.1.1.1.2.3 2003/01/14 21:18:47 rbultje Exp $ | ||
7 | * | ||
8 | * ------------------------------------------------------------------------ | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License as published by | ||
12 | * the Free Software Foundation; either version 2 of the License, or | ||
13 | * (at your option) any later version. | ||
14 | * | ||
15 | * This program is distributed in the hope that it will be useful, | ||
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
18 | * GNU General Public License for more details. | ||
19 | * | ||
20 | * You should have received a copy of the GNU General Public License | ||
21 | * along with this program; if not, write to the Free Software | ||
22 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
23 | * | ||
24 | * ------------------------------------------------------------------------ | ||
25 | */ | ||
26 | |||
27 | #ifndef ZR36060_H | ||
28 | #define ZR36060_H | ||
29 | |||
30 | #include "videocodec.h" | ||
31 | |||
32 | /* data stored for each zoran jpeg codec chip */ | ||
33 | struct zr36060 { | ||
34 | char name[32]; | ||
35 | int num; | ||
36 | /* io datastructure */ | ||
37 | struct videocodec *codec; | ||
38 | // last coder status | ||
39 | __u8 status; | ||
40 | // actual coder setup | ||
41 | int mode; | ||
42 | |||
43 | __u16 width; | ||
44 | __u16 height; | ||
45 | |||
46 | __u16 bitrate_ctrl; | ||
47 | |||
48 | __u32 total_code_vol; | ||
49 | __u32 real_code_vol; | ||
50 | __u16 max_block_vol; | ||
51 | |||
52 | __u8 h_samp_ratio[8]; | ||
53 | __u8 v_samp_ratio[8]; | ||
54 | __u16 scalefact; | ||
55 | __u16 dri; | ||
56 | |||
57 | /* app/com marker data */ | ||
58 | struct jpeg_app_marker app; | ||
59 | struct jpeg_com_marker com; | ||
60 | }; | ||
61 | |||
62 | /* ZR36060 register addresses */ | ||
63 | #define ZR060_LOAD 0x000 | ||
64 | #define ZR060_CFSR 0x001 | ||
65 | #define ZR060_CIR 0x002 | ||
66 | #define ZR060_CMR 0x003 | ||
67 | #define ZR060_MBZ 0x004 | ||
68 | #define ZR060_MBCVR 0x005 | ||
69 | #define ZR060_MER 0x006 | ||
70 | #define ZR060_IMR 0x007 | ||
71 | #define ZR060_ISR 0x008 | ||
72 | #define ZR060_TCV_NET_HI 0x009 | ||
73 | #define ZR060_TCV_NET_MH 0x00a | ||
74 | #define ZR060_TCV_NET_ML 0x00b | ||
75 | #define ZR060_TCV_NET_LO 0x00c | ||
76 | #define ZR060_TCV_DATA_HI 0x00d | ||
77 | #define ZR060_TCV_DATA_MH 0x00e | ||
78 | #define ZR060_TCV_DATA_ML 0x00f | ||
79 | #define ZR060_TCV_DATA_LO 0x010 | ||
80 | #define ZR060_SF_HI 0x011 | ||
81 | #define ZR060_SF_LO 0x012 | ||
82 | #define ZR060_AF_HI 0x013 | ||
83 | #define ZR060_AF_M 0x014 | ||
84 | #define ZR060_AF_LO 0x015 | ||
85 | #define ZR060_ACV_HI 0x016 | ||
86 | #define ZR060_ACV_MH 0x017 | ||
87 | #define ZR060_ACV_ML 0x018 | ||
88 | #define ZR060_ACV_LO 0x019 | ||
89 | #define ZR060_ACT_HI 0x01a | ||
90 | #define ZR060_ACT_MH 0x01b | ||
91 | #define ZR060_ACT_ML 0x01c | ||
92 | #define ZR060_ACT_LO 0x01d | ||
93 | #define ZR060_ACV_TRUN_HI 0x01e | ||
94 | #define ZR060_ACV_TRUN_MH 0x01f | ||
95 | #define ZR060_ACV_TRUN_ML 0x020 | ||
96 | #define ZR060_ACV_TRUN_LO 0x021 | ||
97 | #define ZR060_IDR_DEV 0x022 | ||
98 | #define ZR060_IDR_REV 0x023 | ||
99 | #define ZR060_TCR_HI 0x024 | ||
100 | #define ZR060_TCR_LO 0x025 | ||
101 | #define ZR060_VCR 0x030 | ||
102 | #define ZR060_VPR 0x031 | ||
103 | #define ZR060_SR 0x032 | ||
104 | #define ZR060_BCR_Y 0x033 | ||
105 | #define ZR060_BCR_U 0x034 | ||
106 | #define ZR060_BCR_V 0x035 | ||
107 | #define ZR060_SGR_VTOTAL_HI 0x036 | ||
108 | #define ZR060_SGR_VTOTAL_LO 0x037 | ||
109 | #define ZR060_SGR_HTOTAL_HI 0x038 | ||
110 | #define ZR060_SGR_HTOTAL_LO 0x039 | ||
111 | #define ZR060_SGR_VSYNC 0x03a | ||
112 | #define ZR060_SGR_HSYNC 0x03b | ||
113 | #define ZR060_SGR_BVSTART 0x03c | ||
114 | #define ZR060_SGR_BHSTART 0x03d | ||
115 | #define ZR060_SGR_BVEND_HI 0x03e | ||
116 | #define ZR060_SGR_BVEND_LO 0x03f | ||
117 | #define ZR060_SGR_BHEND_HI 0x040 | ||
118 | #define ZR060_SGR_BHEND_LO 0x041 | ||
119 | #define ZR060_AAR_VSTART_HI 0x042 | ||
120 | #define ZR060_AAR_VSTART_LO 0x043 | ||
121 | #define ZR060_AAR_VEND_HI 0x044 | ||
122 | #define ZR060_AAR_VEND_LO 0x045 | ||
123 | #define ZR060_AAR_HSTART_HI 0x046 | ||
124 | #define ZR060_AAR_HSTART_LO 0x047 | ||
125 | #define ZR060_AAR_HEND_HI 0x048 | ||
126 | #define ZR060_AAR_HEND_LO 0x049 | ||
127 | #define ZR060_SWR_VSTART_HI 0x04a | ||
128 | #define ZR060_SWR_VSTART_LO 0x04b | ||
129 | #define ZR060_SWR_VEND_HI 0x04c | ||
130 | #define ZR060_SWR_VEND_LO 0x04d | ||
131 | #define ZR060_SWR_HSTART_HI 0x04e | ||
132 | #define ZR060_SWR_HSTART_LO 0x04f | ||
133 | #define ZR060_SWR_HEND_HI 0x050 | ||
134 | #define ZR060_SWR_HEND_LO 0x051 | ||
135 | |||
136 | #define ZR060_SOF_IDX 0x060 | ||
137 | #define ZR060_SOS_IDX 0x07a | ||
138 | #define ZR060_DRI_IDX 0x0c0 | ||
139 | #define ZR060_DQT_IDX 0x0cc | ||
140 | #define ZR060_DHT_IDX 0x1d4 | ||
141 | #define ZR060_APP_IDX 0x380 | ||
142 | #define ZR060_COM_IDX 0x3c0 | ||
143 | |||
144 | /* ZR36060 LOAD register bits */ | ||
145 | |||
146 | #define ZR060_LOAD_Load (1 << 7) | ||
147 | #define ZR060_LOAD_SyncRst (1 << 0) | ||
148 | |||
149 | /* ZR36060 Code FIFO Status register bits */ | ||
150 | |||
151 | #define ZR060_CFSR_Busy (1 << 7) | ||
152 | #define ZR060_CFSR_CBusy (1 << 2) | ||
153 | #define ZR060_CFSR_CFIFO (3 << 0) | ||
154 | |||
155 | /* ZR36060 Code Interface register */ | ||
156 | |||
157 | #define ZR060_CIR_Code16 (1 << 7) | ||
158 | #define ZR060_CIR_Endian (1 << 6) | ||
159 | #define ZR060_CIR_CFIS (1 << 2) | ||
160 | #define ZR060_CIR_CodeMstr (1 << 0) | ||
161 | |||
162 | /* ZR36060 Codec Mode register */ | ||
163 | |||
164 | #define ZR060_CMR_Comp (1 << 7) | ||
165 | #define ZR060_CMR_ATP (1 << 6) | ||
166 | #define ZR060_CMR_Pass2 (1 << 5) | ||
167 | #define ZR060_CMR_TLM (1 << 4) | ||
168 | #define ZR060_CMR_BRB (1 << 2) | ||
169 | #define ZR060_CMR_FSF (1 << 1) | ||
170 | |||
171 | /* ZR36060 Markers Enable register */ | ||
172 | |||
173 | #define ZR060_MER_App (1 << 7) | ||
174 | #define ZR060_MER_Com (1 << 6) | ||
175 | #define ZR060_MER_DRI (1 << 5) | ||
176 | #define ZR060_MER_DQT (1 << 4) | ||
177 | #define ZR060_MER_DHT (1 << 3) | ||
178 | |||
179 | /* ZR36060 Interrupt Mask register */ | ||
180 | |||
181 | #define ZR060_IMR_EOAV (1 << 3) | ||
182 | #define ZR060_IMR_EOI (1 << 2) | ||
183 | #define ZR060_IMR_End (1 << 1) | ||
184 | #define ZR060_IMR_DataErr (1 << 0) | ||
185 | |||
186 | /* ZR36060 Interrupt Status register */ | ||
187 | |||
188 | #define ZR060_ISR_ProCnt (3 << 6) | ||
189 | #define ZR060_ISR_EOAV (1 << 3) | ||
190 | #define ZR060_ISR_EOI (1 << 2) | ||
191 | #define ZR060_ISR_End (1 << 1) | ||
192 | #define ZR060_ISR_DataErr (1 << 0) | ||
193 | |||
194 | /* ZR36060 Video Control register */ | ||
195 | |||
196 | #define ZR060_VCR_Video8 (1 << 7) | ||
197 | #define ZR060_VCR_Range (1 << 6) | ||
198 | #define ZR060_VCR_FIDet (1 << 3) | ||
199 | #define ZR060_VCR_FIVedge (1 << 2) | ||
200 | #define ZR060_VCR_FIExt (1 << 1) | ||
201 | #define ZR060_VCR_SyncMstr (1 << 0) | ||
202 | |||
203 | /* ZR36060 Video Polarity register */ | ||
204 | |||
205 | #define ZR060_VPR_VCLKPol (1 << 7) | ||
206 | #define ZR060_VPR_PValPol (1 << 6) | ||
207 | #define ZR060_VPR_PoePol (1 << 5) | ||
208 | #define ZR060_VPR_SImgPol (1 << 4) | ||
209 | #define ZR060_VPR_BLPol (1 << 3) | ||
210 | #define ZR060_VPR_FIPol (1 << 2) | ||
211 | #define ZR060_VPR_HSPol (1 << 1) | ||
212 | #define ZR060_VPR_VSPol (1 << 0) | ||
213 | |||
214 | /* ZR36060 Scaling register */ | ||
215 | |||
216 | #define ZR060_SR_VScale (1 << 2) | ||
217 | #define ZR060_SR_HScale2 (1 << 0) | ||
218 | #define ZR060_SR_HScale4 (2 << 0) | ||
219 | |||
220 | #endif /*fndef ZR36060_H */ | ||