diff options
author | Mauro Carvalho Chehab <mchehab@infradead.org> | 2006-01-23 14:11:05 -0500 |
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committer | Mauro Carvalho Chehab <mchehab@brturbo.com.br> | 2006-01-23 14:11:05 -0500 |
commit | 3ad96835cedec7704b1b5a211b39262bb794adaf (patch) | |
tree | d62864f757dc9a29d50a072614b04178678596f0 /drivers/media/video/tvp5150_reg.h | |
parent | 439090d7d82a333a21987dcbccb90961f27fd2e9 (diff) |
V4L/DVB (3407): added some code for VBI processing and cleanup debug dump
- Renamed some registers and improved register debug message
- Some cleanups at register dump
- Added code to set VBI processor (VDP)
- VBI code still incomplete
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'drivers/media/video/tvp5150_reg.h')
-rw-r--r-- | drivers/media/video/tvp5150_reg.h | 118 |
1 files changed, 31 insertions, 87 deletions
diff --git a/drivers/media/video/tvp5150_reg.h b/drivers/media/video/tvp5150_reg.h index cd45c1ded786..c81587e06e37 100644 --- a/drivers/media/video/tvp5150_reg.h +++ b/drivers/media/video/tvp5150_reg.h | |||
@@ -64,49 +64,32 @@ | |||
64 | #define TVP5150_STATUS_REG_4 0x8b /* Status register #4 */ | 64 | #define TVP5150_STATUS_REG_4 0x8b /* Status register #4 */ |
65 | #define TVP5150_STATUS_REG_5 0x8c /* Status register #5 */ | 65 | #define TVP5150_STATUS_REG_5 0x8c /* Status register #5 */ |
66 | /* Reserved 8Dh-8Fh */ | 66 | /* Reserved 8Dh-8Fh */ |
67 | #define TVP5150_CC_DATA_REG1 0x90 /* Closed caption data registers */ | 67 | /* Closed caption data registers */ |
68 | #define TVP5150_CC_DATA_REG2 0x91 /* Closed caption data registers */ | 68 | #define TVP5150_CC_DATA_INI 0x90 |
69 | #define TVP5150_CC_DATA_REG3 0x92 /* Closed caption data registers */ | 69 | #define TVP5150_CC_DATA_END 0x93 |
70 | #define TVP5150_CC_DATA_REG4 0x93 /* Closed caption data registers */ | 70 | |
71 | #define TVP5150_WSS_DATA_REG1 0X94 /* WSS data registers */ | 71 | /* WSS data registers */ |
72 | #define TVP5150_WSS_DATA_REG2 0X95 /* WSS data registers */ | 72 | #define TVP5150_WSS_DATA_INI 0x94 |
73 | #define TVP5150_WSS_DATA_REG3 0X96 /* WSS data registers */ | 73 | #define TVP5150_WSS_DATA_END 0x99 |
74 | #define TVP5150_WSS_DATA_REG4 0X97 /* WSS data registers */ | 74 | |
75 | #define TVP5150_WSS_DATA_REG5 0X98 /* WSS data registers */ | 75 | /* VPS data registers */ |
76 | #define TVP5150_WSS_DATA_REG6 0X99 /* WSS data registers */ | 76 | #define TVP5150_VPS_DATA_INI 0x9a |
77 | #define TVP5150_VPS_DATA_REG1 0x9a /* VPS data registers */ | 77 | #define TVP5150_VPS_DATA_END 0xa6 |
78 | #define TVP5150_VPS_DATA_REG2 0x9b /* VPS data registers */ | 78 | |
79 | #define TVP5150_VPS_DATA_REG3 0x9c /* VPS data registers */ | 79 | /* VITC data registers */ |
80 | #define TVP5150_VPS_DATA_REG4 0x9d /* VPS data registers */ | 80 | #define TVP5150_VITC_DATA_INI 0xa7 |
81 | #define TVP5150_VPS_DATA_REG5 0x9e /* VPS data registers */ | 81 | #define TVP5150_VITC_DATA_END 0xaf |
82 | #define TVP5150_VPS_DATA_REG6 0x9f /* VPS data registers */ | 82 | |
83 | #define TVP5150_VPS_DATA_REG7 0xa0 /* VPS data registers */ | ||
84 | #define TVP5150_VPS_DATA_REG8 0xa1 /* VPS data registers */ | ||
85 | #define TVP5150_VPS_DATA_REG9 0xa2 /* VPS data registers */ | ||
86 | #define TVP5150_VPS_DATA_REG10 0xa3 /* VPS data registers */ | ||
87 | #define TVP5150_VPS_DATA_REG11 0xa4 /* VPS data registers */ | ||
88 | #define TVP5150_VPS_DATA_REG12 0xa5 /* VPS data registers */ | ||
89 | #define TVP5150_VPS_DATA_REG13 0xa6 /* VPS data registers */ | ||
90 | #define TVP5150_VITC_DATA_REG1 0xa7 /* VITC data registers */ | ||
91 | #define TVP5150_VITC_DATA_REG2 0xa8 /* VITC data registers */ | ||
92 | #define TVP5150_VITC_DATA_REG3 0xa9 /* VITC data registers */ | ||
93 | #define TVP5150_VITC_DATA_REG4 0xaa /* VITC data registers */ | ||
94 | #define TVP5150_VITC_DATA_REG5 0xab /* VITC data registers */ | ||
95 | #define TVP5150_VITC_DATA_REG6 0xac /* VITC data registers */ | ||
96 | #define TVP5150_VITC_DATA_REG7 0xad /* VITC data registers */ | ||
97 | #define TVP5150_VITC_DATA_REG8 0xae /* VITC data registers */ | ||
98 | #define TVP5150_VITC_DATA_REG9 0xaf /* VITC data registers */ | ||
99 | #define TVP5150_VBI_FIFO_READ_DATA 0xb0 /* VBI FIFO read data */ | 83 | #define TVP5150_VBI_FIFO_READ_DATA 0xb0 /* VBI FIFO read data */ |
100 | #define TVP5150_TELETEXT_FIL_1_1 0xb1 /* Teletext filter 1 */ | 84 | |
101 | #define TVP5150_TELETEXT_FIL_1_2 0xb2 /* Teletext filter 1 */ | 85 | /* Teletext filter 1 */ |
102 | #define TVP5150_TELETEXT_FIL_1_3 0xb3 /* Teletext filter 1 */ | 86 | #define TVP5150_TELETEXT_FIL1_INI 0xb1 |
103 | #define TVP5150_TELETEXT_FIL_1_4 0xb4 /* Teletext filter 1 */ | 87 | #define TVP5150_TELETEXT_FIL1_END 0xb5 |
104 | #define TVP5150_TELETEXT_FIL_1_5 0xb5 /* Teletext filter 1 */ | 88 | |
105 | #define TVP5150_TELETEXT_FIL_2_1 0xb6 /* Teletext filter 2 */ | 89 | /* Teletext filter 2 */ |
106 | #define TVP5150_TELETEXT_FIL_2_2 0xb7 /* Teletext filter 2 */ | 90 | #define TVP5150_TELETEXT_FIL2_INI 0xb6 |
107 | #define TVP5150_TELETEXT_FIL_2_3 0xb8 /* Teletext filter 2 */ | 91 | #define TVP5150_TELETEXT_FIL2_END 0xba |
108 | #define TVP5150_TELETEXT_FIL_2_4 0xb9 /* Teletext filter 2 */ | 92 | |
109 | #define TVP5150_TELETEXT_FIL_2_5 0xba /* Teletext filter 2 */ | ||
110 | #define TVP5150_TELETEXT_FIL_ENA 0xbb /* Teletext filter enable */ | 93 | #define TVP5150_TELETEXT_FIL_ENA 0xbb /* Teletext filter enable */ |
111 | /* Reserved BCh-BFh */ | 94 | /* Reserved BCh-BFh */ |
112 | #define TVP5150_INT_STATUS_REG_A 0xc0 /* Interrupt status register A */ | 95 | #define TVP5150_INT_STATUS_REG_A 0xc0 /* Interrupt status register A */ |
@@ -124,50 +107,11 @@ | |||
124 | #define TVP5150_PIX_ALIGN_REG_HIGH 0xcc /* Pixel alignment register high byte */ | 107 | #define TVP5150_PIX_ALIGN_REG_HIGH 0xcc /* Pixel alignment register high byte */ |
125 | #define TVP5150_FIFO_OUT_CTRL 0xcd /* FIFO output control */ | 108 | #define TVP5150_FIFO_OUT_CTRL 0xcd /* FIFO output control */ |
126 | /* Reserved CEh */ | 109 | /* Reserved CEh */ |
127 | #define TVP5150_FULL_FIELD_ENA_1 0xcf /* Full field enable 1 */ | 110 | #define TVP5150_FULL_FIELD_ENA 0xcf /* Full field enable 1 */ |
128 | #define TVP5150_FULL_FIELD_ENA_2 0xd0 /* Full field enable 2 */ | 111 | |
129 | #define TVP5150_LINE_MODE_REG_1 0xd1 /* Line mode registers */ | 112 | /* Line mode registers */ |
130 | #define TVP5150_LINE_MODE_REG_2 0xd2 /* Line mode registers */ | 113 | #define TVP5150_LINE_MODE_INI 0xd0 |
131 | #define TVP5150_LINE_MODE_REG_3 0xd3 /* Line mode registers */ | 114 | #define TVP5150_LINE_MODE_END 0xfb |
132 | #define TVP5150_LINE_MODE_REG_4 0xd4 /* Line mode registers */ | 115 | |
133 | #define TVP5150_LINE_MODE_REG_5 0xd5 /* Line mode registers */ | ||
134 | #define TVP5150_LINE_MODE_REG_6 0xd6 /* Line mode registers */ | ||
135 | #define TVP5150_LINE_MODE_REG_7 0xd7 /* Line mode registers */ | ||
136 | #define TVP5150_LINE_MODE_REG_8 0xd8 /* Line mode registers */ | ||
137 | #define TVP5150_LINE_MODE_REG_9 0xd9 /* Line mode registers */ | ||
138 | #define TVP5150_LINE_MODE_REG_10 0xda /* Line mode registers */ | ||
139 | #define TVP5150_LINE_MODE_REG_11 0xdb /* Line mode registers */ | ||
140 | #define TVP5150_LINE_MODE_REG_12 0xdc /* Line mode registers */ | ||
141 | #define TVP5150_LINE_MODE_REG_13 0xdd /* Line mode registers */ | ||
142 | #define TVP5150_LINE_MODE_REG_14 0xde /* Line mode registers */ | ||
143 | #define TVP5150_LINE_MODE_REG_15 0xdf /* Line mode registers */ | ||
144 | #define TVP5150_LINE_MODE_REG_16 0xe0 /* Line mode registers */ | ||
145 | #define TVP5150_LINE_MODE_REG_17 0xe1 /* Line mode registers */ | ||
146 | #define TVP5150_LINE_MODE_REG_18 0xe2 /* Line mode registers */ | ||
147 | #define TVP5150_LINE_MODE_REG_19 0xe3 /* Line mode registers */ | ||
148 | #define TVP5150_LINE_MODE_REG_20 0xe4 /* Line mode registers */ | ||
149 | #define TVP5150_LINE_MODE_REG_21 0xe5 /* Line mode registers */ | ||
150 | #define TVP5150_LINE_MODE_REG_22 0xe6 /* Line mode registers */ | ||
151 | #define TVP5150_LINE_MODE_REG_23 0xe7 /* Line mode registers */ | ||
152 | #define TVP5150_LINE_MODE_REG_24 0xe8 /* Line mode registers */ | ||
153 | #define TVP5150_LINE_MODE_REG_25 0xe9 /* Line mode registers */ | ||
154 | #define TVP5150_LINE_MODE_REG_27 0xea /* Line mode registers */ | ||
155 | #define TVP5150_LINE_MODE_REG_28 0xeb /* Line mode registers */ | ||
156 | #define TVP5150_LINE_MODE_REG_29 0xec /* Line mode registers */ | ||
157 | #define TVP5150_LINE_MODE_REG_30 0xed /* Line mode registers */ | ||
158 | #define TVP5150_LINE_MODE_REG_31 0xee /* Line mode registers */ | ||
159 | #define TVP5150_LINE_MODE_REG_32 0xef /* Line mode registers */ | ||
160 | #define TVP5150_LINE_MODE_REG_33 0xf0 /* Line mode registers */ | ||
161 | #define TVP5150_LINE_MODE_REG_34 0xf1 /* Line mode registers */ | ||
162 | #define TVP5150_LINE_MODE_REG_35 0xf2 /* Line mode registers */ | ||
163 | #define TVP5150_LINE_MODE_REG_36 0xf3 /* Line mode registers */ | ||
164 | #define TVP5150_LINE_MODE_REG_37 0xf4 /* Line mode registers */ | ||
165 | #define TVP5150_LINE_MODE_REG_38 0xf5 /* Line mode registers */ | ||
166 | #define TVP5150_LINE_MODE_REG_39 0xf6 /* Line mode registers */ | ||
167 | #define TVP5150_LINE_MODE_REG_40 0xf7 /* Line mode registers */ | ||
168 | #define TVP5150_LINE_MODE_REG_41 0xf8 /* Line mode registers */ | ||
169 | #define TVP5150_LINE_MODE_REG_42 0xf9 /* Line mode registers */ | ||
170 | #define TVP5150_LINE_MODE_REG_43 0xfa /* Line mode registers */ | ||
171 | #define TVP5150_LINE_MODE_REG_44 0xfb /* Line mode registers */ | ||
172 | #define TVP5150_FULL_FIELD_MODE_REG 0xfc /* Full field mode register */ | 116 | #define TVP5150_FULL_FIELD_MODE_REG 0xfc /* Full field mode register */ |
173 | /* Reserved FDh-FFh */ | 117 | /* Reserved FDh-FFh */ |