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authorSylwester Nawrocki <s.nawrocki@samsung.com>2012-04-26 05:26:29 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2012-05-20 08:23:09 -0400
commit3d112d9aced3d4ad959e159a1662503452792295 (patch)
tree389a4a1980585c316687b4cfebdb64e46a931812 /drivers/media/video/s5p-fimc
parent0f735f5236643cbbeb833fa0946bd52c20d00966 (diff)
[media] s5p-fimc: Prefix format enumerations with FIMC_FMT_
Prefix the pixel format enumerations with FIMC_FMT_ to make it more clear, especially when used in new IP drivers, like fimc-lite, etc. Also add IO_ prefix in the input/output enumeration. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/video/s5p-fimc')
-rw-r--r--drivers/media/video/s5p-fimc/fimc-capture.c4
-rw-r--r--drivers/media/video/s5p-fimc/fimc-core.c56
-rw-r--r--drivers/media/video/s5p-fimc/fimc-core.h45
-rw-r--r--drivers/media/video/s5p-fimc/fimc-m2m.c4
-rw-r--r--drivers/media/video/s5p-fimc/fimc-reg.c48
5 files changed, 81 insertions, 76 deletions
diff --git a/drivers/media/video/s5p-fimc/fimc-capture.c b/drivers/media/video/s5p-fimc/fimc-capture.c
index 7c884bb7104f..b36809d2f9fc 100644
--- a/drivers/media/video/s5p-fimc/fimc-capture.c
+++ b/drivers/media/video/s5p-fimc/fimc-capture.c
@@ -1524,8 +1524,8 @@ static int fimc_register_capture_device(struct fimc_dev *fimc,
1524 return -ENOMEM; 1524 return -ENOMEM;
1525 1525
1526 ctx->fimc_dev = fimc; 1526 ctx->fimc_dev = fimc;
1527 ctx->in_path = FIMC_CAMERA; 1527 ctx->in_path = FIMC_IO_CAMERA;
1528 ctx->out_path = FIMC_DMA; 1528 ctx->out_path = FIMC_IO_DMA;
1529 ctx->state = FIMC_CTX_CAP; 1529 ctx->state = FIMC_CTX_CAP;
1530 ctx->s_frame.fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_CAM, 0); 1530 ctx->s_frame.fmt = fimc_find_format(NULL, NULL, FMT_FLAGS_CAM, 0);
1531 ctx->d_frame.fmt = ctx->s_frame.fmt; 1531 ctx->d_frame.fmt = ctx->s_frame.fmt;
diff --git a/drivers/media/video/s5p-fimc/fimc-core.c b/drivers/media/video/s5p-fimc/fimc-core.c
index afd69e3d44c2..e0fe9748ec57 100644
--- a/drivers/media/video/s5p-fimc/fimc-core.c
+++ b/drivers/media/video/s5p-fimc/fimc-core.c
@@ -40,7 +40,7 @@ static struct fimc_fmt fimc_formats[] = {
40 .name = "RGB565", 40 .name = "RGB565",
41 .fourcc = V4L2_PIX_FMT_RGB565, 41 .fourcc = V4L2_PIX_FMT_RGB565,
42 .depth = { 16 }, 42 .depth = { 16 },
43 .color = S5P_FIMC_RGB565, 43 .color = FIMC_FMT_RGB565,
44 .memplanes = 1, 44 .memplanes = 1,
45 .colplanes = 1, 45 .colplanes = 1,
46 .flags = FMT_FLAGS_M2M, 46 .flags = FMT_FLAGS_M2M,
@@ -48,7 +48,7 @@ static struct fimc_fmt fimc_formats[] = {
48 .name = "BGR666", 48 .name = "BGR666",
49 .fourcc = V4L2_PIX_FMT_BGR666, 49 .fourcc = V4L2_PIX_FMT_BGR666,
50 .depth = { 32 }, 50 .depth = { 32 },
51 .color = S5P_FIMC_RGB666, 51 .color = FIMC_FMT_RGB666,
52 .memplanes = 1, 52 .memplanes = 1,
53 .colplanes = 1, 53 .colplanes = 1,
54 .flags = FMT_FLAGS_M2M, 54 .flags = FMT_FLAGS_M2M,
@@ -56,7 +56,7 @@ static struct fimc_fmt fimc_formats[] = {
56 .name = "ARGB8888, 32 bpp", 56 .name = "ARGB8888, 32 bpp",
57 .fourcc = V4L2_PIX_FMT_RGB32, 57 .fourcc = V4L2_PIX_FMT_RGB32,
58 .depth = { 32 }, 58 .depth = { 32 },
59 .color = S5P_FIMC_RGB888, 59 .color = FIMC_FMT_RGB888,
60 .memplanes = 1, 60 .memplanes = 1,
61 .colplanes = 1, 61 .colplanes = 1,
62 .flags = FMT_FLAGS_M2M | FMT_HAS_ALPHA, 62 .flags = FMT_FLAGS_M2M | FMT_HAS_ALPHA,
@@ -64,7 +64,7 @@ static struct fimc_fmt fimc_formats[] = {
64 .name = "ARGB1555", 64 .name = "ARGB1555",
65 .fourcc = V4L2_PIX_FMT_RGB555, 65 .fourcc = V4L2_PIX_FMT_RGB555,
66 .depth = { 16 }, 66 .depth = { 16 },
67 .color = S5P_FIMC_RGB555, 67 .color = FIMC_FMT_RGB555,
68 .memplanes = 1, 68 .memplanes = 1,
69 .colplanes = 1, 69 .colplanes = 1,
70 .flags = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA, 70 .flags = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA,
@@ -72,7 +72,7 @@ static struct fimc_fmt fimc_formats[] = {
72 .name = "ARGB4444", 72 .name = "ARGB4444",
73 .fourcc = V4L2_PIX_FMT_RGB444, 73 .fourcc = V4L2_PIX_FMT_RGB444,
74 .depth = { 16 }, 74 .depth = { 16 },
75 .color = S5P_FIMC_RGB444, 75 .color = FIMC_FMT_RGB444,
76 .memplanes = 1, 76 .memplanes = 1,
77 .colplanes = 1, 77 .colplanes = 1,
78 .flags = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA, 78 .flags = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA,
@@ -80,7 +80,7 @@ static struct fimc_fmt fimc_formats[] = {
80 .name = "YUV 4:2:2 packed, YCbYCr", 80 .name = "YUV 4:2:2 packed, YCbYCr",
81 .fourcc = V4L2_PIX_FMT_YUYV, 81 .fourcc = V4L2_PIX_FMT_YUYV,
82 .depth = { 16 }, 82 .depth = { 16 },
83 .color = S5P_FIMC_YCBYCR422, 83 .color = FIMC_FMT_YCBYCR422,
84 .memplanes = 1, 84 .memplanes = 1,
85 .colplanes = 1, 85 .colplanes = 1,
86 .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8, 86 .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
@@ -89,7 +89,7 @@ static struct fimc_fmt fimc_formats[] = {
89 .name = "YUV 4:2:2 packed, CbYCrY", 89 .name = "YUV 4:2:2 packed, CbYCrY",
90 .fourcc = V4L2_PIX_FMT_UYVY, 90 .fourcc = V4L2_PIX_FMT_UYVY,
91 .depth = { 16 }, 91 .depth = { 16 },
92 .color = S5P_FIMC_CBYCRY422, 92 .color = FIMC_FMT_CBYCRY422,
93 .memplanes = 1, 93 .memplanes = 1,
94 .colplanes = 1, 94 .colplanes = 1,
95 .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8, 95 .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8,
@@ -98,7 +98,7 @@ static struct fimc_fmt fimc_formats[] = {
98 .name = "YUV 4:2:2 packed, CrYCbY", 98 .name = "YUV 4:2:2 packed, CrYCbY",
99 .fourcc = V4L2_PIX_FMT_VYUY, 99 .fourcc = V4L2_PIX_FMT_VYUY,
100 .depth = { 16 }, 100 .depth = { 16 },
101 .color = S5P_FIMC_CRYCBY422, 101 .color = FIMC_FMT_CRYCBY422,
102 .memplanes = 1, 102 .memplanes = 1,
103 .colplanes = 1, 103 .colplanes = 1,
104 .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8, 104 .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8,
@@ -107,7 +107,7 @@ static struct fimc_fmt fimc_formats[] = {
107 .name = "YUV 4:2:2 packed, YCrYCb", 107 .name = "YUV 4:2:2 packed, YCrYCb",
108 .fourcc = V4L2_PIX_FMT_YVYU, 108 .fourcc = V4L2_PIX_FMT_YVYU,
109 .depth = { 16 }, 109 .depth = { 16 },
110 .color = S5P_FIMC_YCRYCB422, 110 .color = FIMC_FMT_YCRYCB422,
111 .memplanes = 1, 111 .memplanes = 1,
112 .colplanes = 1, 112 .colplanes = 1,
113 .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8, 113 .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8,
@@ -116,7 +116,7 @@ static struct fimc_fmt fimc_formats[] = {
116 .name = "YUV 4:2:2 planar, Y/Cb/Cr", 116 .name = "YUV 4:2:2 planar, Y/Cb/Cr",
117 .fourcc = V4L2_PIX_FMT_YUV422P, 117 .fourcc = V4L2_PIX_FMT_YUV422P,
118 .depth = { 12 }, 118 .depth = { 12 },
119 .color = S5P_FIMC_YCBYCR422, 119 .color = FIMC_FMT_YCBYCR422,
120 .memplanes = 1, 120 .memplanes = 1,
121 .colplanes = 3, 121 .colplanes = 3,
122 .flags = FMT_FLAGS_M2M, 122 .flags = FMT_FLAGS_M2M,
@@ -124,7 +124,7 @@ static struct fimc_fmt fimc_formats[] = {
124 .name = "YUV 4:2:2 planar, Y/CbCr", 124 .name = "YUV 4:2:2 planar, Y/CbCr",
125 .fourcc = V4L2_PIX_FMT_NV16, 125 .fourcc = V4L2_PIX_FMT_NV16,
126 .depth = { 16 }, 126 .depth = { 16 },
127 .color = S5P_FIMC_YCBYCR422, 127 .color = FIMC_FMT_YCBYCR422,
128 .memplanes = 1, 128 .memplanes = 1,
129 .colplanes = 2, 129 .colplanes = 2,
130 .flags = FMT_FLAGS_M2M, 130 .flags = FMT_FLAGS_M2M,
@@ -132,7 +132,7 @@ static struct fimc_fmt fimc_formats[] = {
132 .name = "YUV 4:2:2 planar, Y/CrCb", 132 .name = "YUV 4:2:2 planar, Y/CrCb",
133 .fourcc = V4L2_PIX_FMT_NV61, 133 .fourcc = V4L2_PIX_FMT_NV61,
134 .depth = { 16 }, 134 .depth = { 16 },
135 .color = S5P_FIMC_YCRYCB422, 135 .color = FIMC_FMT_YCRYCB422,
136 .memplanes = 1, 136 .memplanes = 1,
137 .colplanes = 2, 137 .colplanes = 2,
138 .flags = FMT_FLAGS_M2M, 138 .flags = FMT_FLAGS_M2M,
@@ -140,7 +140,7 @@ static struct fimc_fmt fimc_formats[] = {
140 .name = "YUV 4:2:0 planar, YCbCr", 140 .name = "YUV 4:2:0 planar, YCbCr",
141 .fourcc = V4L2_PIX_FMT_YUV420, 141 .fourcc = V4L2_PIX_FMT_YUV420,
142 .depth = { 12 }, 142 .depth = { 12 },
143 .color = S5P_FIMC_YCBCR420, 143 .color = FIMC_FMT_YCBCR420,
144 .memplanes = 1, 144 .memplanes = 1,
145 .colplanes = 3, 145 .colplanes = 3,
146 .flags = FMT_FLAGS_M2M, 146 .flags = FMT_FLAGS_M2M,
@@ -148,14 +148,14 @@ static struct fimc_fmt fimc_formats[] = {
148 .name = "YUV 4:2:0 planar, Y/CbCr", 148 .name = "YUV 4:2:0 planar, Y/CbCr",
149 .fourcc = V4L2_PIX_FMT_NV12, 149 .fourcc = V4L2_PIX_FMT_NV12,
150 .depth = { 12 }, 150 .depth = { 12 },
151 .color = S5P_FIMC_YCBCR420, 151 .color = FIMC_FMT_YCBCR420,
152 .memplanes = 1, 152 .memplanes = 1,
153 .colplanes = 2, 153 .colplanes = 2,
154 .flags = FMT_FLAGS_M2M, 154 .flags = FMT_FLAGS_M2M,
155 }, { 155 }, {
156 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr", 156 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
157 .fourcc = V4L2_PIX_FMT_NV12M, 157 .fourcc = V4L2_PIX_FMT_NV12M,
158 .color = S5P_FIMC_YCBCR420, 158 .color = FIMC_FMT_YCBCR420,
159 .depth = { 8, 4 }, 159 .depth = { 8, 4 },
160 .memplanes = 2, 160 .memplanes = 2,
161 .colplanes = 2, 161 .colplanes = 2,
@@ -163,7 +163,7 @@ static struct fimc_fmt fimc_formats[] = {
163 }, { 163 }, {
164 .name = "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr", 164 .name = "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr",
165 .fourcc = V4L2_PIX_FMT_YUV420M, 165 .fourcc = V4L2_PIX_FMT_YUV420M,
166 .color = S5P_FIMC_YCBCR420, 166 .color = FIMC_FMT_YCBCR420,
167 .depth = { 8, 2, 2 }, 167 .depth = { 8, 2, 2 },
168 .memplanes = 3, 168 .memplanes = 3,
169 .colplanes = 3, 169 .colplanes = 3,
@@ -171,7 +171,7 @@ static struct fimc_fmt fimc_formats[] = {
171 }, { 171 }, {
172 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled", 172 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled",
173 .fourcc = V4L2_PIX_FMT_NV12MT, 173 .fourcc = V4L2_PIX_FMT_NV12MT,
174 .color = S5P_FIMC_YCBCR420, 174 .color = FIMC_FMT_YCBCR420,
175 .depth = { 8, 4 }, 175 .depth = { 8, 4 },
176 .memplanes = 2, 176 .memplanes = 2,
177 .colplanes = 2, 177 .colplanes = 2,
@@ -179,7 +179,7 @@ static struct fimc_fmt fimc_formats[] = {
179 }, { 179 }, {
180 .name = "JPEG encoded data", 180 .name = "JPEG encoded data",
181 .fourcc = V4L2_PIX_FMT_JPEG, 181 .fourcc = V4L2_PIX_FMT_JPEG,
182 .color = S5P_FIMC_JPEG, 182 .color = FIMC_FMT_JPEG,
183 .depth = { 8 }, 183 .depth = { 8 },
184 .memplanes = 1, 184 .memplanes = 1,
185 .colplanes = 1, 185 .colplanes = 1,
@@ -361,7 +361,7 @@ int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
361 case 3: 361 case 3:
362 paddr->cb = (u32)(paddr->y + pix_size); 362 paddr->cb = (u32)(paddr->y + pix_size);
363 /* decompose Y into Y/Cb/Cr */ 363 /* decompose Y into Y/Cb/Cr */
364 if (S5P_FIMC_YCBCR420 == frame->fmt->color) 364 if (FIMC_FMT_YCBCR420 == frame->fmt->color)
365 paddr->cr = (u32)(paddr->cb 365 paddr->cr = (u32)(paddr->cb
366 + (pix_size >> 2)); 366 + (pix_size >> 2));
367 else /* 422 */ 367 else /* 422 */
@@ -394,16 +394,16 @@ void fimc_set_yuv_order(struct fimc_ctx *ctx)
394 394
395 /* Set order for 1 plane input formats. */ 395 /* Set order for 1 plane input formats. */
396 switch (ctx->s_frame.fmt->color) { 396 switch (ctx->s_frame.fmt->color) {
397 case S5P_FIMC_YCRYCB422: 397 case FIMC_FMT_YCRYCB422:
398 ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CBYCRY; 398 ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CBYCRY;
399 break; 399 break;
400 case S5P_FIMC_CBYCRY422: 400 case FIMC_FMT_CBYCRY422:
401 ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCRYCB; 401 ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCRYCB;
402 break; 402 break;
403 case S5P_FIMC_CRYCBY422: 403 case FIMC_FMT_CRYCBY422:
404 ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCBYCR; 404 ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_YCBYCR;
405 break; 405 break;
406 case S5P_FIMC_YCBYCR422: 406 case FIMC_FMT_YCBYCR422:
407 default: 407 default:
408 ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CRYCBY; 408 ctx->in_order_1p = FIMC_REG_MSCTRL_ORDER422_CRYCBY;
409 break; 409 break;
@@ -411,16 +411,16 @@ void fimc_set_yuv_order(struct fimc_ctx *ctx)
411 dbg("ctx->in_order_1p= %d", ctx->in_order_1p); 411 dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
412 412
413 switch (ctx->d_frame.fmt->color) { 413 switch (ctx->d_frame.fmt->color) {
414 case S5P_FIMC_YCRYCB422: 414 case FIMC_FMT_YCRYCB422:
415 ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CBYCRY; 415 ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CBYCRY;
416 break; 416 break;
417 case S5P_FIMC_CBYCRY422: 417 case FIMC_FMT_CBYCRY422:
418 ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCRYCB; 418 ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCRYCB;
419 break; 419 break;
420 case S5P_FIMC_CRYCBY422: 420 case FIMC_FMT_CRYCBY422:
421 ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCBYCR; 421 ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_YCBYCR;
422 break; 422 break;
423 case S5P_FIMC_YCBYCR422: 423 case FIMC_FMT_YCBYCR422:
424 default: 424 default:
425 ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CRYCBY; 425 ctx->out_order_1p = FIMC_REG_CIOCTRL_ORDER422_CRYCBY;
426 break; 426 break;
@@ -453,7 +453,7 @@ void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
453 f->dma_offset.cb_h >>= 1; 453 f->dma_offset.cb_h >>= 1;
454 f->dma_offset.cr_h >>= 1; 454 f->dma_offset.cr_h >>= 1;
455 } 455 }
456 if (f->fmt->color == S5P_FIMC_YCBCR420) { 456 if (f->fmt->color == FIMC_FMT_YCBCR420) {
457 f->dma_offset.cb_v >>= 1; 457 f->dma_offset.cb_v >>= 1;
458 f->dma_offset.cr_v >>= 1; 458 f->dma_offset.cr_v >>= 1;
459 } 459 }
diff --git a/drivers/media/video/s5p-fimc/fimc-core.h b/drivers/media/video/s5p-fimc/fimc-core.h
index 8b073979cee8..fbb651cc6a96 100644
--- a/drivers/media/video/s5p-fimc/fimc-core.h
+++ b/drivers/media/video/s5p-fimc/fimc-core.h
@@ -76,26 +76,31 @@ enum fimc_dev_flags {
76#define fimc_capture_busy(dev) test_bit(ST_CAPT_BUSY, &(dev)->state) 76#define fimc_capture_busy(dev) test_bit(ST_CAPT_BUSY, &(dev)->state)
77 77
78enum fimc_datapath { 78enum fimc_datapath {
79 FIMC_CAMERA, 79 FIMC_IO_NONE,
80 FIMC_DMA, 80 FIMC_IO_CAMERA,
81 FIMC_LCDFIFO, 81 FIMC_IO_DMA,
82 FIMC_WRITEBACK 82 FIMC_IO_LCDFIFO,
83 FIMC_IO_WRITEBACK,
84 FIMC_IO_ISP,
83}; 85};
84 86
85enum fimc_color_fmt { 87enum fimc_color_fmt {
86 S5P_FIMC_RGB444 = 0x10, 88 FIMC_FMT_RGB444 = 0x10,
87 S5P_FIMC_RGB555, 89 FIMC_FMT_RGB555,
88 S5P_FIMC_RGB565, 90 FIMC_FMT_RGB565,
89 S5P_FIMC_RGB666, 91 FIMC_FMT_RGB666,
90 S5P_FIMC_RGB888, 92 FIMC_FMT_RGB888,
91 S5P_FIMC_RGB30_LOCAL, 93 FIMC_FMT_RGB30_LOCAL,
92 S5P_FIMC_YCBCR420 = 0x20, 94 FIMC_FMT_YCBCR420 = 0x20,
93 S5P_FIMC_YCBYCR422, 95 FIMC_FMT_YCBYCR422,
94 S5P_FIMC_YCRYCB422, 96 FIMC_FMT_YCRYCB422,
95 S5P_FIMC_CBYCRY422, 97 FIMC_FMT_CBYCRY422,
96 S5P_FIMC_CRYCBY422, 98 FIMC_FMT_CRYCBY422,
97 S5P_FIMC_YCBCR444_LOCAL, 99 FIMC_FMT_YCBCR444_LOCAL,
98 S5P_FIMC_JPEG = 0x40, 100 FIMC_FMT_JPEG = 0x40,
101 FIMC_FMT_RAW8 = 0x80,
102 FIMC_FMT_RAW10,
103 FIMC_FMT_RAW12,
99}; 104};
100 105
101#define fimc_fmt_is_rgb(x) (!!((x) & 0x10)) 106#define fimc_fmt_is_rgb(x) (!!((x) & 0x10))
@@ -563,9 +568,9 @@ static inline int tiled_fmt(struct fimc_fmt *fmt)
563static inline int fimc_get_alpha_mask(struct fimc_fmt *fmt) 568static inline int fimc_get_alpha_mask(struct fimc_fmt *fmt)
564{ 569{
565 switch (fmt->color) { 570 switch (fmt->color) {
566 case S5P_FIMC_RGB444: return 0x0f; 571 case FIMC_FMT_RGB444: return 0x0f;
567 case S5P_FIMC_RGB555: return 0x01; 572 case FIMC_FMT_RGB555: return 0x01;
568 case S5P_FIMC_RGB888: return 0xff; 573 case FIMC_FMT_RGB888: return 0xff;
569 default: return 0; 574 default: return 0;
570 }; 575 };
571} 576}
diff --git a/drivers/media/video/s5p-fimc/fimc-m2m.c b/drivers/media/video/s5p-fimc/fimc-m2m.c
index 70edc75e6fce..60bbab157c24 100644
--- a/drivers/media/video/s5p-fimc/fimc-m2m.c
+++ b/drivers/media/video/s5p-fimc/fimc-m2m.c
@@ -676,8 +676,8 @@ static int fimc_m2m_open(struct file *file)
676 /* Setup the device context for memory-to-memory mode */ 676 /* Setup the device context for memory-to-memory mode */
677 ctx->state = FIMC_CTX_M2M; 677 ctx->state = FIMC_CTX_M2M;
678 ctx->flags = 0; 678 ctx->flags = 0;
679 ctx->in_path = FIMC_DMA; 679 ctx->in_path = FIMC_IO_DMA;
680 ctx->out_path = FIMC_DMA; 680 ctx->out_path = FIMC_IO_DMA;
681 681
682 ctx->m2m_ctx = v4l2_m2m_ctx_init(fimc->m2m.m2m_dev, ctx, queue_init); 682 ctx->m2m_ctx = v4l2_m2m_ctx_init(fimc->m2m.m2m_dev, ctx, queue_init);
683 if (IS_ERR(ctx->m2m_ctx)) { 683 if (IS_ERR(ctx->m2m_ctx)) {
diff --git a/drivers/media/video/s5p-fimc/fimc-reg.c b/drivers/media/video/s5p-fimc/fimc-reg.c
index 31a8b99ee71a..5b1adde5a57a 100644
--- a/drivers/media/video/s5p-fimc/fimc-reg.c
+++ b/drivers/media/video/s5p-fimc/fimc-reg.c
@@ -85,13 +85,13 @@ void fimc_hw_set_rotation(struct fimc_ctx *ctx)
85 * in direct fifo output mode. 85 * in direct fifo output mode.
86 */ 86 */
87 if (ctx->rotation == 90 || ctx->rotation == 270) { 87 if (ctx->rotation == 90 || ctx->rotation == 270) {
88 if (ctx->out_path == FIMC_LCDFIFO) 88 if (ctx->out_path == FIMC_IO_LCDFIFO)
89 cfg |= FIMC_REG_CITRGFMT_INROT90; 89 cfg |= FIMC_REG_CITRGFMT_INROT90;
90 else 90 else
91 cfg |= FIMC_REG_CITRGFMT_OUTROT90; 91 cfg |= FIMC_REG_CITRGFMT_OUTROT90;
92 } 92 }
93 93
94 if (ctx->out_path == FIMC_DMA) { 94 if (ctx->out_path == FIMC_IO_DMA) {
95 cfg |= fimc_hw_get_target_flip(ctx); 95 cfg |= fimc_hw_get_target_flip(ctx);
96 writel(cfg, dev->regs + FIMC_REG_CITRGFMT); 96 writel(cfg, dev->regs + FIMC_REG_CITRGFMT);
97 } else { 97 } else {
@@ -117,13 +117,13 @@ void fimc_hw_set_target_format(struct fimc_ctx *ctx)
117 FIMC_REG_CITRGFMT_VSIZE_MASK); 117 FIMC_REG_CITRGFMT_VSIZE_MASK);
118 118
119 switch (frame->fmt->color) { 119 switch (frame->fmt->color) {
120 case S5P_FIMC_RGB444...S5P_FIMC_RGB888: 120 case FIMC_FMT_RGB444...FIMC_FMT_RGB888:
121 cfg |= FIMC_REG_CITRGFMT_RGB; 121 cfg |= FIMC_REG_CITRGFMT_RGB;
122 break; 122 break;
123 case S5P_FIMC_YCBCR420: 123 case FIMC_FMT_YCBCR420:
124 cfg |= FIMC_REG_CITRGFMT_YCBCR420; 124 cfg |= FIMC_REG_CITRGFMT_YCBCR420;
125 break; 125 break;
126 case S5P_FIMC_YCBYCR422...S5P_FIMC_CRYCBY422: 126 case FIMC_FMT_YCBYCR422...FIMC_FMT_CRYCBY422:
127 if (frame->fmt->colplanes == 1) 127 if (frame->fmt->colplanes == 1)
128 cfg |= FIMC_REG_CITRGFMT_YCBCR422_1P; 128 cfg |= FIMC_REG_CITRGFMT_YCBCR422_1P;
129 else 129 else
@@ -200,11 +200,11 @@ void fimc_hw_set_out_dma(struct fimc_ctx *ctx)
200 else if (fmt->colplanes == 3) 200 else if (fmt->colplanes == 3)
201 cfg |= FIMC_REG_CIOCTRL_YCBCR_3PLANE; 201 cfg |= FIMC_REG_CIOCTRL_YCBCR_3PLANE;
202 202
203 if (fmt->color == S5P_FIMC_RGB565) 203 if (fmt->color == FIMC_FMT_RGB565)
204 cfg |= FIMC_REG_CIOCTRL_RGB565; 204 cfg |= FIMC_REG_CIOCTRL_RGB565;
205 else if (fmt->color == S5P_FIMC_RGB555) 205 else if (fmt->color == FIMC_FMT_RGB555)
206 cfg |= FIMC_REG_CIOCTRL_ARGB1555; 206 cfg |= FIMC_REG_CIOCTRL_ARGB1555;
207 else if (fmt->color == S5P_FIMC_RGB444) 207 else if (fmt->color == FIMC_FMT_RGB444)
208 cfg |= FIMC_REG_CIOCTRL_ARGB4444; 208 cfg |= FIMC_REG_CIOCTRL_ARGB4444;
209 209
210 writel(cfg, dev->regs + FIMC_REG_CIOCTRL); 210 writel(cfg, dev->regs + FIMC_REG_CIOCTRL);
@@ -277,28 +277,28 @@ static void fimc_hw_set_scaler(struct fimc_ctx *ctx)
277 if (sc->copy_mode) 277 if (sc->copy_mode)
278 cfg |= FIMC_REG_CISCCTRL_ONE2ONE; 278 cfg |= FIMC_REG_CISCCTRL_ONE2ONE;
279 279
280 if (ctx->in_path == FIMC_DMA) { 280 if (ctx->in_path == FIMC_IO_DMA) {
281 switch (src_frame->fmt->color) { 281 switch (src_frame->fmt->color) {
282 case S5P_FIMC_RGB565: 282 case FIMC_FMT_RGB565:
283 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB565; 283 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB565;
284 break; 284 break;
285 case S5P_FIMC_RGB666: 285 case FIMC_FMT_RGB666:
286 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB666; 286 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB666;
287 break; 287 break;
288 case S5P_FIMC_RGB888: 288 case FIMC_FMT_RGB888:
289 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB888; 289 cfg |= FIMC_REG_CISCCTRL_INRGB_FMT_RGB888;
290 break; 290 break;
291 } 291 }
292 } 292 }
293 293
294 if (ctx->out_path == FIMC_DMA) { 294 if (ctx->out_path == FIMC_IO_DMA) {
295 u32 color = dst_frame->fmt->color; 295 u32 color = dst_frame->fmt->color;
296 296
297 if (color >= S5P_FIMC_RGB444 && color <= S5P_FIMC_RGB565) 297 if (color >= FIMC_FMT_RGB444 && color <= FIMC_FMT_RGB565)
298 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB565; 298 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB565;
299 else if (color == S5P_FIMC_RGB666) 299 else if (color == FIMC_FMT_RGB666)
300 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB666; 300 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB666;
301 else if (color == S5P_FIMC_RGB888) 301 else if (color == FIMC_FMT_RGB888)
302 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888; 302 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888;
303 } else { 303 } else {
304 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888; 304 cfg |= FIMC_REG_CISCCTRL_OUTRGB_FMT_RGB888;
@@ -351,7 +351,7 @@ void fimc_hw_en_capture(struct fimc_ctx *ctx)
351 351
352 u32 cfg = readl(dev->regs + FIMC_REG_CIIMGCPT); 352 u32 cfg = readl(dev->regs + FIMC_REG_CIIMGCPT);
353 353
354 if (ctx->out_path == FIMC_DMA) { 354 if (ctx->out_path == FIMC_IO_DMA) {
355 /* one shot mode */ 355 /* one shot mode */
356 cfg |= FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE | 356 cfg |= FIMC_REG_CIIMGCPT_CPT_FREN_ENABLE |
357 FIMC_REG_CIIMGCPT_IMGCPTEN; 357 FIMC_REG_CIIMGCPT_IMGCPTEN;
@@ -408,7 +408,7 @@ static void fimc_hw_set_in_dma_size(struct fimc_ctx *ctx)
408 u32 cfg_o = 0; 408 u32 cfg_o = 0;
409 u32 cfg_r = 0; 409 u32 cfg_r = 0;
410 410
411 if (FIMC_LCDFIFO == ctx->out_path) 411 if (FIMC_IO_LCDFIFO == ctx->out_path)
412 cfg_r |= FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN; 412 cfg_r |= FIMC_REG_CIREAL_ISIZE_AUTOLOAD_EN;
413 413
414 cfg_o |= (frame->f_height << 16) | frame->f_width; 414 cfg_o |= (frame->f_height << 16) | frame->f_width;
@@ -439,7 +439,7 @@ void fimc_hw_set_in_dma(struct fimc_ctx *ctx)
439 fimc_hw_set_in_dma_size(ctx); 439 fimc_hw_set_in_dma_size(ctx);
440 440
441 /* Use DMA autoload only in FIFO mode. */ 441 /* Use DMA autoload only in FIFO mode. */
442 fimc_hw_en_autoload(dev, ctx->out_path == FIMC_LCDFIFO); 442 fimc_hw_en_autoload(dev, ctx->out_path == FIMC_IO_LCDFIFO);
443 443
444 /* Set the input DMA to process single frame only. */ 444 /* Set the input DMA to process single frame only. */
445 cfg = readl(dev->regs + FIMC_REG_MSCTRL); 445 cfg = readl(dev->regs + FIMC_REG_MSCTRL);
@@ -454,10 +454,10 @@ void fimc_hw_set_in_dma(struct fimc_ctx *ctx)
454 | FIMC_REG_MSCTRL_FIFO_CTRL_FULL); 454 | FIMC_REG_MSCTRL_FIFO_CTRL_FULL);
455 455
456 switch (frame->fmt->color) { 456 switch (frame->fmt->color) {
457 case S5P_FIMC_RGB565...S5P_FIMC_RGB888: 457 case FIMC_FMT_RGB565...FIMC_FMT_RGB888:
458 cfg |= FIMC_REG_MSCTRL_INFORMAT_RGB; 458 cfg |= FIMC_REG_MSCTRL_INFORMAT_RGB;
459 break; 459 break;
460 case S5P_FIMC_YCBCR420: 460 case FIMC_FMT_YCBCR420:
461 cfg |= FIMC_REG_MSCTRL_INFORMAT_YCBCR420; 461 cfg |= FIMC_REG_MSCTRL_INFORMAT_YCBCR420;
462 462
463 if (frame->fmt->colplanes == 2) 463 if (frame->fmt->colplanes == 2)
@@ -466,7 +466,7 @@ void fimc_hw_set_in_dma(struct fimc_ctx *ctx)
466 cfg |= FIMC_REG_MSCTRL_C_INT_IN_3PLANE; 466 cfg |= FIMC_REG_MSCTRL_C_INT_IN_3PLANE;
467 467
468 break; 468 break;
469 case S5P_FIMC_YCBYCR422...S5P_FIMC_CRYCBY422: 469 case FIMC_FMT_YCBYCR422...FIMC_FMT_CRYCBY422:
470 if (frame->fmt->colplanes == 1) { 470 if (frame->fmt->colplanes == 1) {
471 cfg |= ctx->in_order_1p 471 cfg |= ctx->in_order_1p
472 | FIMC_REG_MSCTRL_INFORMAT_YCBCR422_1P; 472 | FIMC_REG_MSCTRL_INFORMAT_YCBCR422_1P;
@@ -507,7 +507,7 @@ void fimc_hw_set_input_path(struct fimc_ctx *ctx)
507 u32 cfg = readl(dev->regs + FIMC_REG_MSCTRL); 507 u32 cfg = readl(dev->regs + FIMC_REG_MSCTRL);
508 cfg &= ~FIMC_REG_MSCTRL_INPUT_MASK; 508 cfg &= ~FIMC_REG_MSCTRL_INPUT_MASK;
509 509
510 if (ctx->in_path == FIMC_DMA) 510 if (ctx->in_path == FIMC_IO_DMA)
511 cfg |= FIMC_REG_MSCTRL_INPUT_MEMORY; 511 cfg |= FIMC_REG_MSCTRL_INPUT_MEMORY;
512 else 512 else
513 cfg |= FIMC_REG_MSCTRL_INPUT_EXTCAM; 513 cfg |= FIMC_REG_MSCTRL_INPUT_EXTCAM;
@@ -521,7 +521,7 @@ void fimc_hw_set_output_path(struct fimc_ctx *ctx)
521 521
522 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL); 522 u32 cfg = readl(dev->regs + FIMC_REG_CISCCTRL);
523 cfg &= ~FIMC_REG_CISCCTRL_LCDPATHEN_FIFO; 523 cfg &= ~FIMC_REG_CISCCTRL_LCDPATHEN_FIFO;
524 if (ctx->out_path == FIMC_LCDFIFO) 524 if (ctx->out_path == FIMC_IO_LCDFIFO)
525 cfg |= FIMC_REG_CISCCTRL_LCDPATHEN_FIFO; 525 cfg |= FIMC_REG_CISCCTRL_LCDPATHEN_FIFO;
526 writel(cfg, dev->regs + FIMC_REG_CISCCTRL); 526 writel(cfg, dev->regs + FIMC_REG_CISCCTRL);
527} 527}