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authorLinus Torvalds <torvalds@linux-foundation.org>2008-12-30 20:41:32 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2008-12-30 20:41:32 -0500
commitf54a6ec0fd85002d94d05b4bb679508eeb066683 (patch)
tree0f24dd66cce563d2c5e7656c2489e5b96eef31f9 /drivers/media/video/pxa_camera.c
parent5ed1836814d908f45cafde0e79cb85314ab9d41d (diff)
parent134179823b3ca9c8b98e0631906459dbb022ff9b (diff)
Merge branch 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-2.6
* 'for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-2.6: (583 commits) V4L/DVB (10130): use USB API functions rather than constants V4L/DVB (10129): dvb: remove deprecated use of RW_LOCK_UNLOCKED in frontends V4L/DVB (10128): modify V4L documentation to be a valid XHTML V4L/DVB (10127): stv06xx: Avoid having y unitialized V4L/DVB (10125): em28xx: Don't do AC97 vendor detection for i2s audio devices V4L/DVB (10124): em28xx: expand output formats available V4L/DVB (10123): em28xx: fix reversed definitions of I2S audio modes V4L/DVB (10122): em28xx: don't load em28xx-alsa for em2870 based devices V4L/DVB (10121): em28xx: remove worthless Pinnacle PCTV HD Mini 80e device profile V4L/DVB (10120): em28xx: remove redundant Pinnacle Dazzle DVC 100 profile V4L/DVB (10119): em28xx: fix corrupted XCLK value V4L/DVB (10118): zoran: fix warning for a variable not used V4L/DVB (10116): af9013: Fix gcc false warnings V4L/DVB (10111a): usbvideo.h: remove an useless blank line V4L/DVB (10111): quickcam_messenger.c: fix a warning V4L/DVB (10110): v4l2-ioctl: Fix warnings when using .unlocked_ioctl = __video_ioctl2 V4L/DVB (10109): anysee: Fix usage of an unitialized function V4L/DVB (10104): uvcvideo: Add support for video output devices V4L/DVB (10102): uvcvideo: Ignore interrupt endpoint for built-in iSight webcams. V4L/DVB (10101): uvcvideo: Fix bulk URB processing when the header is erroneous ...
Diffstat (limited to 'drivers/media/video/pxa_camera.c')
-rw-r--r--drivers/media/video/pxa_camera.c541
1 files changed, 437 insertions, 104 deletions
diff --git a/drivers/media/video/pxa_camera.c b/drivers/media/video/pxa_camera.c
index 70a77625107d..9d33de22cc48 100644
--- a/drivers/media/video/pxa_camera.c
+++ b/drivers/media/video/pxa_camera.c
@@ -25,7 +25,6 @@
25#include <linux/version.h> 25#include <linux/version.h>
26#include <linux/device.h> 26#include <linux/device.h>
27#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28#include <linux/mutex.h>
29#include <linux/clk.h> 28#include <linux/clk.h>
30 29
31#include <media/v4l2-common.h> 30#include <media/v4l2-common.h>
@@ -44,6 +43,101 @@
44#define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5) 43#define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
45#define PXA_CAM_DRV_NAME "pxa27x-camera" 44#define PXA_CAM_DRV_NAME "pxa27x-camera"
46 45
46/* Camera Interface */
47#define CICR0 0x0000
48#define CICR1 0x0004
49#define CICR2 0x0008
50#define CICR3 0x000C
51#define CICR4 0x0010
52#define CISR 0x0014
53#define CIFR 0x0018
54#define CITOR 0x001C
55#define CIBR0 0x0028
56#define CIBR1 0x0030
57#define CIBR2 0x0038
58
59#define CICR0_DMAEN (1 << 31) /* DMA request enable */
60#define CICR0_PAR_EN (1 << 30) /* Parity enable */
61#define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
62#define CICR0_ENB (1 << 28) /* Camera interface enable */
63#define CICR0_DIS (1 << 27) /* Camera interface disable */
64#define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
65#define CICR0_TOM (1 << 9) /* Time-out mask */
66#define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
67#define CICR0_FEM (1 << 7) /* FIFO-empty mask */
68#define CICR0_EOLM (1 << 6) /* End-of-line mask */
69#define CICR0_PERRM (1 << 5) /* Parity-error mask */
70#define CICR0_QDM (1 << 4) /* Quick-disable mask */
71#define CICR0_CDM (1 << 3) /* Disable-done mask */
72#define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
73#define CICR0_EOFM (1 << 1) /* End-of-frame mask */
74#define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
75
76#define CICR1_TBIT (1 << 31) /* Transparency bit */
77#define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
78#define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
79#define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
80#define CICR1_RGB_F (1 << 11) /* RGB format */
81#define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
82#define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
83#define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
84#define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
85#define CICR1_DW (0x7 << 0) /* Data width mask */
86
87#define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
88 wait count mask */
89#define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
90 wait count mask */
91#define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
92#define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
93 wait count mask */
94#define CICR2_FSW (0x7 << 0) /* Frame stabilization
95 wait count mask */
96
97#define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
98 wait count mask */
99#define CICR3_EFW (0xff << 16) /* End-of-frame line clock
100 wait count mask */
101#define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
102#define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
103 wait count mask */
104#define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
105
106#define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
107#define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
108#define CICR4_PCP (1 << 22) /* Pixel clock polarity */
109#define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
110#define CICR4_VSP (1 << 20) /* Vertical sync polarity */
111#define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
112#define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
113#define CICR4_DIV (0xff << 0) /* Clock divisor mask */
114
115#define CISR_FTO (1 << 15) /* FIFO time-out */
116#define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
117#define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
118#define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
119#define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
120#define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
121#define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
122#define CISR_EOL (1 << 8) /* End of line */
123#define CISR_PAR_ERR (1 << 7) /* Parity error */
124#define CISR_CQD (1 << 6) /* Camera interface quick disable */
125#define CISR_CDD (1 << 5) /* Camera interface disable done */
126#define CISR_SOF (1 << 4) /* Start of frame */
127#define CISR_EOF (1 << 3) /* End of frame */
128#define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
129#define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
130#define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
131
132#define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
133#define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
134#define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
135#define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
136#define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
137#define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
138#define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
139#define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
140
47#define CICR0_SIM_MP (0 << 24) 141#define CICR0_SIM_MP (0 << 24)
48#define CICR0_SIM_SP (1 << 24) 142#define CICR0_SIM_SP (1 << 24)
49#define CICR0_SIM_MS (2 << 24) 143#define CICR0_SIM_MS (2 << 24)
@@ -71,8 +165,6 @@
71 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \ 165 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
72 CICR0_EOFM | CICR0_FOM) 166 CICR0_EOFM | CICR0_FOM)
73 167
74static DEFINE_MUTEX(camera_lock);
75
76/* 168/*
77 * Structures 169 * Structures
78 */ 170 */
@@ -122,7 +214,9 @@ struct pxa_camera_dev {
122 struct pxacamera_platform_data *pdata; 214 struct pxacamera_platform_data *pdata;
123 struct resource *res; 215 struct resource *res;
124 unsigned long platform_flags; 216 unsigned long platform_flags;
125 unsigned long platform_mclk_10khz; 217 unsigned long ciclk;
218 unsigned long mclk;
219 u32 mclk_divisor;
126 220
127 struct list_head capture; 221 struct list_head capture;
128 222
@@ -145,8 +239,7 @@ static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
145 unsigned int *size) 239 unsigned int *size)
146{ 240{
147 struct soc_camera_device *icd = vq->priv_data; 241 struct soc_camera_device *icd = vq->priv_data;
148 struct soc_camera_host *ici = 242 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
149 to_soc_camera_host(icd->dev.parent);
150 struct pxa_camera_dev *pcdev = ici->priv; 243 struct pxa_camera_dev *pcdev = ici->priv;
151 244
152 dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size); 245 dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
@@ -172,8 +265,7 @@ static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
172static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf) 265static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
173{ 266{
174 struct soc_camera_device *icd = vq->priv_data; 267 struct soc_camera_device *icd = vq->priv_data;
175 struct soc_camera_host *ici = 268 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
176 to_soc_camera_host(icd->dev.parent);
177 struct pxa_camera_dev *pcdev = ici->priv; 269 struct pxa_camera_dev *pcdev = ici->priv;
178 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb); 270 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
179 int i; 271 int i;
@@ -249,8 +341,7 @@ static int pxa_videobuf_prepare(struct videobuf_queue *vq,
249 struct videobuf_buffer *vb, enum v4l2_field field) 341 struct videobuf_buffer *vb, enum v4l2_field field)
250{ 342{
251 struct soc_camera_device *icd = vq->priv_data; 343 struct soc_camera_device *icd = vq->priv_data;
252 struct soc_camera_host *ici = 344 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
253 to_soc_camera_host(icd->dev.parent);
254 struct pxa_camera_dev *pcdev = ici->priv; 345 struct pxa_camera_dev *pcdev = ici->priv;
255 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); 346 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
256 int ret; 347 int ret;
@@ -369,8 +460,7 @@ static void pxa_videobuf_queue(struct videobuf_queue *vq,
369 struct videobuf_buffer *vb) 460 struct videobuf_buffer *vb)
370{ 461{
371 struct soc_camera_device *icd = vq->priv_data; 462 struct soc_camera_device *icd = vq->priv_data;
372 struct soc_camera_host *ici = 463 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
373 to_soc_camera_host(icd->dev.parent);
374 struct pxa_camera_dev *pcdev = ici->priv; 464 struct pxa_camera_dev *pcdev = ici->priv;
375 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb); 465 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
376 struct pxa_buffer *active; 466 struct pxa_buffer *active;
@@ -387,7 +477,10 @@ static void pxa_videobuf_queue(struct videobuf_queue *vq,
387 active = pcdev->active; 477 active = pcdev->active;
388 478
389 if (!active) { 479 if (!active) {
390 CIFR |= CIFR_RESET_F; 480 unsigned long cifr, cicr0;
481
482 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
483 __raw_writel(cifr, pcdev->base + CIFR);
391 484
392 for (i = 0; i < pcdev->channels; i++) { 485 for (i = 0; i < pcdev->channels; i++) {
393 DDADR(pcdev->dma_chans[i]) = buf->dmas[i].sg_dma; 486 DDADR(pcdev->dma_chans[i]) = buf->dmas[i].sg_dma;
@@ -396,7 +489,9 @@ static void pxa_videobuf_queue(struct videobuf_queue *vq,
396 } 489 }
397 490
398 pcdev->active = buf; 491 pcdev->active = buf;
399 CICR0 |= CICR0_ENB; 492
493 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
494 __raw_writel(cicr0, pcdev->base + CICR0);
400 } else { 495 } else {
401 struct pxa_cam_dma *buf_dma; 496 struct pxa_cam_dma *buf_dma;
402 struct pxa_cam_dma *act_dma; 497 struct pxa_cam_dma *act_dma;
@@ -480,6 +575,8 @@ static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
480 struct videobuf_buffer *vb, 575 struct videobuf_buffer *vb,
481 struct pxa_buffer *buf) 576 struct pxa_buffer *buf)
482{ 577{
578 unsigned long cicr0;
579
483 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */ 580 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
484 list_del_init(&vb->queue); 581 list_del_init(&vb->queue);
485 vb->state = VIDEOBUF_DONE; 582 vb->state = VIDEOBUF_DONE;
@@ -492,7 +589,9 @@ static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
492 DCSR(pcdev->dma_chans[0]) = 0; 589 DCSR(pcdev->dma_chans[0]) = 0;
493 DCSR(pcdev->dma_chans[1]) = 0; 590 DCSR(pcdev->dma_chans[1]) = 0;
494 DCSR(pcdev->dma_chans[2]) = 0; 591 DCSR(pcdev->dma_chans[2]) = 0;
495 CICR0 &= ~CICR0_ENB; 592
593 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
594 __raw_writel(cicr0, pcdev->base + CICR0);
496 return; 595 return;
497 } 596 }
498 597
@@ -507,6 +606,7 @@ static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
507 unsigned long flags; 606 unsigned long flags;
508 u32 status, camera_status, overrun; 607 u32 status, camera_status, overrun;
509 struct videobuf_buffer *vb; 608 struct videobuf_buffer *vb;
609 unsigned long cifr, cicr0;
510 610
511 spin_lock_irqsave(&pcdev->lock, flags); 611 spin_lock_irqsave(&pcdev->lock, flags);
512 612
@@ -529,22 +629,26 @@ static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
529 goto out; 629 goto out;
530 } 630 }
531 631
532 camera_status = CISR; 632 camera_status = __raw_readl(pcdev->base + CISR);
533 overrun = CISR_IFO_0; 633 overrun = CISR_IFO_0;
534 if (pcdev->channels == 3) 634 if (pcdev->channels == 3)
535 overrun |= CISR_IFO_1 | CISR_IFO_2; 635 overrun |= CISR_IFO_1 | CISR_IFO_2;
536 if (camera_status & overrun) { 636 if (camera_status & overrun) {
537 dev_dbg(pcdev->dev, "FIFO overrun! CISR: %x\n", camera_status); 637 dev_dbg(pcdev->dev, "FIFO overrun! CISR: %x\n", camera_status);
538 /* Stop the Capture Interface */ 638 /* Stop the Capture Interface */
539 CICR0 &= ~CICR0_ENB; 639 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
640 __raw_writel(cicr0, pcdev->base + CICR0);
641
540 /* Stop DMA */ 642 /* Stop DMA */
541 DCSR(channel) = 0; 643 DCSR(channel) = 0;
542 /* Reset the FIFOs */ 644 /* Reset the FIFOs */
543 CIFR |= CIFR_RESET_F; 645 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
646 __raw_writel(cifr, pcdev->base + CIFR);
544 /* Enable End-Of-Frame Interrupt */ 647 /* Enable End-Of-Frame Interrupt */
545 CICR0 &= ~CICR0_EOFM; 648 cicr0 &= ~CICR0_EOFM;
649 __raw_writel(cicr0, pcdev->base + CICR0);
546 /* Restart the Capture Interface */ 650 /* Restart the Capture Interface */
547 CICR0 |= CICR0_ENB; 651 __raw_writel(cicr0 | CICR0_ENB, pcdev->base + CICR0);
548 goto out; 652 goto out;
549 } 653 }
550 654
@@ -600,24 +704,43 @@ static void pxa_camera_init_videobuf(struct videobuf_queue *q,
600 sizeof(struct pxa_buffer), icd); 704 sizeof(struct pxa_buffer), icd);
601} 705}
602 706
603static int mclk_get_divisor(struct pxa_camera_dev *pcdev) 707static u32 mclk_get_divisor(struct pxa_camera_dev *pcdev)
604{ 708{
605 unsigned int mclk_10khz = pcdev->platform_mclk_10khz; 709 unsigned long mclk = pcdev->mclk;
606 unsigned long div; 710 u32 div;
607 unsigned long lcdclk; 711 unsigned long lcdclk;
608 712
609 lcdclk = clk_get_rate(pcdev->clk) / 10000; 713 lcdclk = clk_get_rate(pcdev->clk);
714 pcdev->ciclk = lcdclk;
715
716 /* mclk <= ciclk / 4 (27.4.2) */
717 if (mclk > lcdclk / 4) {
718 mclk = lcdclk / 4;
719 dev_warn(pcdev->dev, "Limiting master clock to %lu\n", mclk);
720 }
721
722 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
723 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
610 724
611 /* We verify platform_mclk_10khz != 0, so if anyone breaks it, here 725 /* If we're not supplying MCLK, leave it at 0 */
612 * they get a nice Oops */ 726 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
613 div = (lcdclk + 2 * mclk_10khz - 1) / (2 * mclk_10khz) - 1; 727 pcdev->mclk = lcdclk / (2 * (div + 1));
614 728
615 dev_dbg(pcdev->dev, "LCD clock %lukHz, target freq %dkHz, " 729 dev_dbg(pcdev->dev, "LCD clock %luHz, target freq %luHz, "
616 "divisor %lu\n", lcdclk * 10, mclk_10khz * 10, div); 730 "divisor %u\n", lcdclk, mclk, div);
617 731
618 return div; 732 return div;
619} 733}
620 734
735static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
736 unsigned long pclk)
737{
738 /* We want a timeout > 1 pixel time, not ">=" */
739 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
740
741 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
742}
743
621static void pxa_camera_activate(struct pxa_camera_dev *pcdev) 744static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
622{ 745{
623 struct pxacamera_platform_data *pdata = pcdev->pdata; 746 struct pxacamera_platform_data *pdata = pcdev->pdata;
@@ -631,7 +754,8 @@ static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
631 pdata->init(pcdev->dev); 754 pdata->init(pcdev->dev);
632 } 755 }
633 756
634 CICR0 = 0x3FF; /* disable all interrupts */ 757 /* disable all interrupts */
758 __raw_writel(0x3ff, pcdev->base + CICR0);
635 759
636 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN) 760 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
637 cicr4 |= CICR4_PCLK_EN; 761 cicr4 |= CICR4_PCLK_EN;
@@ -644,7 +768,14 @@ static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
644 if (pcdev->platform_flags & PXA_CAMERA_VSP) 768 if (pcdev->platform_flags & PXA_CAMERA_VSP)
645 cicr4 |= CICR4_VSP; 769 cicr4 |= CICR4_VSP;
646 770
647 CICR4 = mclk_get_divisor(pcdev) | cicr4; 771 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
772
773 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
774 /* Initialise the timeout under the assumption pclk = mclk */
775 recalculate_fifo_timeout(pcdev, pcdev->mclk);
776 else
777 /* "Safe default" - 13MHz */
778 recalculate_fifo_timeout(pcdev, 13000000);
648 779
649 clk_enable(pcdev->clk); 780 clk_enable(pcdev->clk);
650} 781}
@@ -657,14 +788,15 @@ static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
657static irqreturn_t pxa_camera_irq(int irq, void *data) 788static irqreturn_t pxa_camera_irq(int irq, void *data)
658{ 789{
659 struct pxa_camera_dev *pcdev = data; 790 struct pxa_camera_dev *pcdev = data;
660 unsigned int status = CISR; 791 unsigned long status, cicr0;
661 792
662 dev_dbg(pcdev->dev, "Camera interrupt status 0x%x\n", status); 793 status = __raw_readl(pcdev->base + CISR);
794 dev_dbg(pcdev->dev, "Camera interrupt status 0x%lx\n", status);
663 795
664 if (!status) 796 if (!status)
665 return IRQ_NONE; 797 return IRQ_NONE;
666 798
667 CISR = status; 799 __raw_writel(status, pcdev->base + CISR);
668 800
669 if (status & CISR_EOF) { 801 if (status & CISR_EOF) {
670 int i; 802 int i;
@@ -673,22 +805,24 @@ static irqreturn_t pxa_camera_irq(int irq, void *data)
673 pcdev->active->dmas[i].sg_dma; 805 pcdev->active->dmas[i].sg_dma;
674 DCSR(pcdev->dma_chans[i]) = DCSR_RUN; 806 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
675 } 807 }
676 CICR0 |= CICR0_EOFM; 808 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
809 __raw_writel(cicr0, pcdev->base + CICR0);
677 } 810 }
678 811
679 return IRQ_HANDLED; 812 return IRQ_HANDLED;
680} 813}
681 814
682/* The following two functions absolutely depend on the fact, that 815/*
683 * there can be only one camera on PXA quick capture interface */ 816 * The following two functions absolutely depend on the fact, that
817 * there can be only one camera on PXA quick capture interface
818 * Called with .video_lock held
819 */
684static int pxa_camera_add_device(struct soc_camera_device *icd) 820static int pxa_camera_add_device(struct soc_camera_device *icd)
685{ 821{
686 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); 822 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
687 struct pxa_camera_dev *pcdev = ici->priv; 823 struct pxa_camera_dev *pcdev = ici->priv;
688 int ret; 824 int ret;
689 825
690 mutex_lock(&camera_lock);
691
692 if (pcdev->icd) { 826 if (pcdev->icd) {
693 ret = -EBUSY; 827 ret = -EBUSY;
694 goto ebusy; 828 goto ebusy;
@@ -704,11 +838,10 @@ static int pxa_camera_add_device(struct soc_camera_device *icd)
704 pcdev->icd = icd; 838 pcdev->icd = icd;
705 839
706ebusy: 840ebusy:
707 mutex_unlock(&camera_lock);
708
709 return ret; 841 return ret;
710} 842}
711 843
844/* Called with .video_lock held */
712static void pxa_camera_remove_device(struct soc_camera_device *icd) 845static void pxa_camera_remove_device(struct soc_camera_device *icd)
713{ 846{
714 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent); 847 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
@@ -720,7 +853,7 @@ static void pxa_camera_remove_device(struct soc_camera_device *icd)
720 icd->devnum); 853 icd->devnum);
721 854
722 /* disable capture, disable interrupts */ 855 /* disable capture, disable interrupts */
723 CICR0 = 0x3ff; 856 __raw_writel(0x3ff, pcdev->base + CICR0);
724 857
725 /* Stop DMA engine */ 858 /* Stop DMA engine */
726 DCSR(pcdev->dma_chans[0]) = 0; 859 DCSR(pcdev->dma_chans[0]) = 0;
@@ -767,6 +900,9 @@ static int test_platform_param(struct pxa_camera_dev *pcdev,
767 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)) 900 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8))
768 return -EINVAL; 901 return -EINVAL;
769 *flags |= SOCAM_DATAWIDTH_8; 902 *flags |= SOCAM_DATAWIDTH_8;
903 break;
904 default:
905 return -EINVAL;
770 } 906 }
771 907
772 return 0; 908 return 0;
@@ -774,11 +910,10 @@ static int test_platform_param(struct pxa_camera_dev *pcdev,
774 910
775static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt) 911static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
776{ 912{
777 struct soc_camera_host *ici = 913 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
778 to_soc_camera_host(icd->dev.parent);
779 struct pxa_camera_dev *pcdev = ici->priv; 914 struct pxa_camera_dev *pcdev = ici->priv;
780 unsigned long dw, bpp, bus_flags, camera_flags, common_flags; 915 unsigned long dw, bpp, bus_flags, camera_flags, common_flags;
781 u32 cicr0, cicr1, cicr4 = 0; 916 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0;
782 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags); 917 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags);
783 918
784 if (ret < 0) 919 if (ret < 0)
@@ -825,12 +960,10 @@ static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
825 * We fix bit-per-pixel equal to data-width... */ 960 * We fix bit-per-pixel equal to data-width... */
826 switch (common_flags & SOCAM_DATAWIDTH_MASK) { 961 switch (common_flags & SOCAM_DATAWIDTH_MASK) {
827 case SOCAM_DATAWIDTH_10: 962 case SOCAM_DATAWIDTH_10:
828 icd->buswidth = 10;
829 dw = 4; 963 dw = 4;
830 bpp = 0x40; 964 bpp = 0x40;
831 break; 965 break;
832 case SOCAM_DATAWIDTH_9: 966 case SOCAM_DATAWIDTH_9:
833 icd->buswidth = 9;
834 dw = 3; 967 dw = 3;
835 bpp = 0x20; 968 bpp = 0x20;
836 break; 969 break;
@@ -838,7 +971,6 @@ static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
838 /* Actually it can only be 8 now, 971 /* Actually it can only be 8 now,
839 * default is just to silence compiler warnings */ 972 * default is just to silence compiler warnings */
840 case SOCAM_DATAWIDTH_8: 973 case SOCAM_DATAWIDTH_8:
841 icd->buswidth = 8;
842 dw = 2; 974 dw = 2;
843 bpp = 0; 975 bpp = 0;
844 } 976 }
@@ -854,9 +986,9 @@ static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
854 if (common_flags & SOCAM_VSYNC_ACTIVE_LOW) 986 if (common_flags & SOCAM_VSYNC_ACTIVE_LOW)
855 cicr4 |= CICR4_VSP; 987 cicr4 |= CICR4_VSP;
856 988
857 cicr0 = CICR0; 989 cicr0 = __raw_readl(pcdev->base + CICR0);
858 if (cicr0 & CICR0_ENB) 990 if (cicr0 & CICR0_ENB)
859 CICR0 = cicr0 & ~CICR0_ENB; 991 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
860 992
861 cicr1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw; 993 cicr1 = CICR1_PPL_VAL(icd->width - 1) | bpp | dw;
862 994
@@ -864,7 +996,17 @@ static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
864 case V4L2_PIX_FMT_YUV422P: 996 case V4L2_PIX_FMT_YUV422P:
865 pcdev->channels = 3; 997 pcdev->channels = 3;
866 cicr1 |= CICR1_YCBCR_F; 998 cicr1 |= CICR1_YCBCR_F;
999 /*
1000 * Normally, pxa bus wants as input UYVY format. We allow all
1001 * reorderings of the YUV422 format, as no processing is done,
1002 * and the YUV stream is just passed through without any
1003 * transformation. Note that UYVY is the only format that
1004 * should be used if pxa framebuffer Overlay2 is used.
1005 */
1006 case V4L2_PIX_FMT_UYVY:
1007 case V4L2_PIX_FMT_VYUY:
867 case V4L2_PIX_FMT_YUYV: 1008 case V4L2_PIX_FMT_YUYV:
1009 case V4L2_PIX_FMT_YVYU:
868 cicr1 |= CICR1_COLOR_SP_VAL(2); 1010 cicr1 |= CICR1_COLOR_SP_VAL(2);
869 break; 1011 break;
870 case V4L2_PIX_FMT_RGB555: 1012 case V4L2_PIX_FMT_RGB555:
@@ -876,27 +1018,32 @@ static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
876 break; 1018 break;
877 } 1019 }
878 1020
879 CICR1 = cicr1; 1021 cicr2 = 0;
880 CICR2 = 0; 1022 cicr3 = CICR3_LPF_VAL(icd->height - 1) |
881 CICR3 = CICR3_LPF_VAL(icd->height - 1) |
882 CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top)); 1023 CICR3_BFW_VAL(min((unsigned short)255, icd->y_skip_top));
883 CICR4 = mclk_get_divisor(pcdev) | cicr4; 1024 cicr4 |= pcdev->mclk_divisor;
1025
1026 __raw_writel(cicr1, pcdev->base + CICR1);
1027 __raw_writel(cicr2, pcdev->base + CICR2);
1028 __raw_writel(cicr3, pcdev->base + CICR3);
1029 __raw_writel(cicr4, pcdev->base + CICR4);
884 1030
885 /* CIF interrupts are not used, only DMA */ 1031 /* CIF interrupts are not used, only DMA */
886 CICR0 = (pcdev->platform_flags & PXA_CAMERA_MASTER ? 1032 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
887 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP)) | 1033 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
888 CICR0_DMAEN | CICR0_IRQ_MASK | (cicr0 & CICR0_ENB); 1034 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1035 __raw_writel(cicr0, pcdev->base + CICR0);
889 1036
890 return 0; 1037 return 0;
891} 1038}
892 1039
893static int pxa_camera_try_bus_param(struct soc_camera_device *icd, __u32 pixfmt) 1040static int pxa_camera_try_bus_param(struct soc_camera_device *icd,
1041 unsigned char buswidth)
894{ 1042{
895 struct soc_camera_host *ici = 1043 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
896 to_soc_camera_host(icd->dev.parent);
897 struct pxa_camera_dev *pcdev = ici->priv; 1044 struct pxa_camera_dev *pcdev = ici->priv;
898 unsigned long bus_flags, camera_flags; 1045 unsigned long bus_flags, camera_flags;
899 int ret = test_platform_param(pcdev, icd->buswidth, &bus_flags); 1046 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
900 1047
901 if (ret < 0) 1048 if (ret < 0)
902 return ret; 1049 return ret;
@@ -906,28 +1053,210 @@ static int pxa_camera_try_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
906 return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL; 1053 return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL;
907} 1054}
908 1055
909static int pxa_camera_set_fmt_cap(struct soc_camera_device *icd, 1056static const struct soc_camera_data_format pxa_camera_formats[] = {
910 __u32 pixfmt, struct v4l2_rect *rect) 1057 {
1058 .name = "Planar YUV422 16 bit",
1059 .depth = 16,
1060 .fourcc = V4L2_PIX_FMT_YUV422P,
1061 .colorspace = V4L2_COLORSPACE_JPEG,
1062 },
1063};
1064
1065static bool buswidth_supported(struct soc_camera_device *icd, int depth)
1066{
1067 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1068 struct pxa_camera_dev *pcdev = ici->priv;
1069
1070 switch (depth) {
1071 case 8:
1072 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8);
1073 case 9:
1074 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9);
1075 case 10:
1076 return !!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10);
1077 }
1078 return false;
1079}
1080
1081static int required_buswidth(const struct soc_camera_data_format *fmt)
911{ 1082{
912 return icd->ops->set_fmt_cap(icd, pixfmt, rect); 1083 switch (fmt->fourcc) {
1084 case V4L2_PIX_FMT_UYVY:
1085 case V4L2_PIX_FMT_VYUY:
1086 case V4L2_PIX_FMT_YUYV:
1087 case V4L2_PIX_FMT_YVYU:
1088 case V4L2_PIX_FMT_RGB565:
1089 case V4L2_PIX_FMT_RGB555:
1090 return 8;
1091 default:
1092 return fmt->depth;
1093 }
913} 1094}
914 1095
915static int pxa_camera_try_fmt_cap(struct soc_camera_device *icd, 1096static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx,
916 struct v4l2_format *f) 1097 struct soc_camera_format_xlate *xlate)
917{ 1098{
918 /* limit to pxa hardware capabilities */ 1099 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
919 if (f->fmt.pix.height < 32) 1100 int formats = 0, buswidth, ret;
920 f->fmt.pix.height = 32; 1101
921 if (f->fmt.pix.height > 2048) 1102 buswidth = required_buswidth(icd->formats + idx);
922 f->fmt.pix.height = 2048; 1103
923 if (f->fmt.pix.width < 48) 1104 if (!buswidth_supported(icd, buswidth))
924 f->fmt.pix.width = 48; 1105 return 0;
925 if (f->fmt.pix.width > 2048) 1106
926 f->fmt.pix.width = 2048; 1107 ret = pxa_camera_try_bus_param(icd, buswidth);
927 f->fmt.pix.width &= ~0x01; 1108 if (ret < 0)
1109 return 0;
1110
1111 switch (icd->formats[idx].fourcc) {
1112 case V4L2_PIX_FMT_UYVY:
1113 formats++;
1114 if (xlate) {
1115 xlate->host_fmt = &pxa_camera_formats[0];
1116 xlate->cam_fmt = icd->formats + idx;
1117 xlate->buswidth = buswidth;
1118 xlate++;
1119 dev_dbg(&ici->dev, "Providing format %s using %s\n",
1120 pxa_camera_formats[0].name,
1121 icd->formats[idx].name);
1122 }
1123 case V4L2_PIX_FMT_VYUY:
1124 case V4L2_PIX_FMT_YUYV:
1125 case V4L2_PIX_FMT_YVYU:
1126 case V4L2_PIX_FMT_RGB565:
1127 case V4L2_PIX_FMT_RGB555:
1128 formats++;
1129 if (xlate) {
1130 xlate->host_fmt = icd->formats + idx;
1131 xlate->cam_fmt = icd->formats + idx;
1132 xlate->buswidth = buswidth;
1133 xlate++;
1134 dev_dbg(&ici->dev, "Providing format %s packed\n",
1135 icd->formats[idx].name);
1136 }
1137 break;
1138 default:
1139 /* Generic pass-through */
1140 formats++;
1141 if (xlate) {
1142 xlate->host_fmt = icd->formats + idx;
1143 xlate->cam_fmt = icd->formats + idx;
1144 xlate->buswidth = icd->formats[idx].depth;
1145 xlate++;
1146 dev_dbg(&ici->dev,
1147 "Providing format %s in pass-through mode\n",
1148 icd->formats[idx].name);
1149 }
1150 }
1151
1152 return formats;
1153}
1154
1155static int pxa_camera_set_fmt(struct soc_camera_device *icd,
1156 __u32 pixfmt, struct v4l2_rect *rect)
1157{
1158 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1159 struct pxa_camera_dev *pcdev = ici->priv;
1160 const struct soc_camera_data_format *host_fmt, *cam_fmt = NULL;
1161 const struct soc_camera_format_xlate *xlate;
1162 struct soc_camera_sense sense = {
1163 .master_clock = pcdev->mclk,
1164 .pixel_clock_max = pcdev->ciclk / 4,
1165 };
1166 int ret, buswidth;
1167
1168 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1169 if (!xlate) {
1170 dev_warn(&ici->dev, "Format %x not found\n", pixfmt);
1171 return -EINVAL;
1172 }
1173
1174 buswidth = xlate->buswidth;
1175 host_fmt = xlate->host_fmt;
1176 cam_fmt = xlate->cam_fmt;
1177
1178 /* If PCLK is used to latch data from the sensor, check sense */
1179 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1180 icd->sense = &sense;
1181
1182 switch (pixfmt) {
1183 case 0: /* Only geometry change */
1184 ret = icd->ops->set_fmt(icd, pixfmt, rect);
1185 break;
1186 default:
1187 ret = icd->ops->set_fmt(icd, cam_fmt->fourcc, rect);
1188 }
1189
1190 icd->sense = NULL;
1191
1192 if (ret < 0) {
1193 dev_warn(&ici->dev, "Failed to configure for format %x\n",
1194 pixfmt);
1195 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1196 if (sense.pixel_clock > sense.pixel_clock_max) {
1197 dev_err(&ici->dev,
1198 "pixel clock %lu set by the camera too high!",
1199 sense.pixel_clock);
1200 return -EIO;
1201 }
1202 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1203 }
928 1204
1205 if (pixfmt && !ret) {
1206 icd->buswidth = buswidth;
1207 icd->current_fmt = host_fmt;
1208 }
1209
1210 return ret;
1211}
1212
1213static int pxa_camera_try_fmt(struct soc_camera_device *icd,
1214 struct v4l2_format *f)
1215{
1216 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1217 const struct soc_camera_format_xlate *xlate;
1218 struct v4l2_pix_format *pix = &f->fmt.pix;
1219 __u32 pixfmt = pix->pixelformat;
1220 enum v4l2_field field;
1221 int ret;
1222
1223 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1224 if (!xlate) {
1225 dev_warn(&ici->dev, "Format %x not found\n", pixfmt);
1226 return -EINVAL;
1227 }
1228
1229 /* limit to pxa hardware capabilities */
1230 if (pix->height < 32)
1231 pix->height = 32;
1232 if (pix->height > 2048)
1233 pix->height = 2048;
1234 if (pix->width < 48)
1235 pix->width = 48;
1236 if (pix->width > 2048)
1237 pix->width = 2048;
1238 pix->width &= ~0x01;
1239
1240 pix->bytesperline = pix->width *
1241 DIV_ROUND_UP(xlate->host_fmt->depth, 8);
1242 pix->sizeimage = pix->height * pix->bytesperline;
1243
1244 /* camera has to see its format, but the user the original one */
1245 pix->pixelformat = xlate->cam_fmt->fourcc;
929 /* limit to sensor capabilities */ 1246 /* limit to sensor capabilities */
930 return icd->ops->try_fmt_cap(icd, f); 1247 ret = icd->ops->try_fmt(icd, f);
1248 pix->pixelformat = xlate->host_fmt->fourcc;
1249
1250 field = pix->field;
1251
1252 if (field == V4L2_FIELD_ANY) {
1253 pix->field = V4L2_FIELD_NONE;
1254 } else if (field != V4L2_FIELD_NONE) {
1255 dev_err(&icd->dev, "Field type %d unsupported.\n", field);
1256 return -EINVAL;
1257 }
1258
1259 return ret;
931} 1260}
932 1261
933static int pxa_camera_reqbufs(struct soc_camera_file *icf, 1262static int pxa_camera_reqbufs(struct soc_camera_file *icf,
@@ -979,16 +1308,15 @@ static int pxa_camera_querycap(struct soc_camera_host *ici,
979 1308
980static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state) 1309static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state)
981{ 1310{
982 struct soc_camera_host *ici = 1311 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
983 to_soc_camera_host(icd->dev.parent);
984 struct pxa_camera_dev *pcdev = ici->priv; 1312 struct pxa_camera_dev *pcdev = ici->priv;
985 int i = 0, ret = 0; 1313 int i = 0, ret = 0;
986 1314
987 pcdev->save_cicr[i++] = CICR0; 1315 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
988 pcdev->save_cicr[i++] = CICR1; 1316 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
989 pcdev->save_cicr[i++] = CICR2; 1317 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
990 pcdev->save_cicr[i++] = CICR3; 1318 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
991 pcdev->save_cicr[i++] = CICR4; 1319 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
992 1320
993 if ((pcdev->icd) && (pcdev->icd->ops->suspend)) 1321 if ((pcdev->icd) && (pcdev->icd->ops->suspend))
994 ret = pcdev->icd->ops->suspend(pcdev->icd, state); 1322 ret = pcdev->icd->ops->suspend(pcdev->icd, state);
@@ -998,8 +1326,7 @@ static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state)
998 1326
999static int pxa_camera_resume(struct soc_camera_device *icd) 1327static int pxa_camera_resume(struct soc_camera_device *icd)
1000{ 1328{
1001 struct soc_camera_host *ici = 1329 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1002 to_soc_camera_host(icd->dev.parent);
1003 struct pxa_camera_dev *pcdev = ici->priv; 1330 struct pxa_camera_dev *pcdev = ici->priv;
1004 int i = 0, ret = 0; 1331 int i = 0, ret = 0;
1005 1332
@@ -1007,23 +1334,27 @@ static int pxa_camera_resume(struct soc_camera_device *icd)
1007 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD; 1334 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1008 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD; 1335 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1009 1336
1010 CICR0 = pcdev->save_cicr[i++] & ~CICR0_ENB; 1337 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
1011 CICR1 = pcdev->save_cicr[i++]; 1338 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
1012 CICR2 = pcdev->save_cicr[i++]; 1339 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
1013 CICR3 = pcdev->save_cicr[i++]; 1340 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
1014 CICR4 = pcdev->save_cicr[i++]; 1341 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
1015 1342
1016 if ((pcdev->icd) && (pcdev->icd->ops->resume)) 1343 if ((pcdev->icd) && (pcdev->icd->ops->resume))
1017 ret = pcdev->icd->ops->resume(pcdev->icd); 1344 ret = pcdev->icd->ops->resume(pcdev->icd);
1018 1345
1019 /* Restart frame capture if active buffer exists */ 1346 /* Restart frame capture if active buffer exists */
1020 if (!ret && pcdev->active) { 1347 if (!ret && pcdev->active) {
1348 unsigned long cifr, cicr0;
1349
1021 /* Reset the FIFOs */ 1350 /* Reset the FIFOs */
1022 CIFR |= CIFR_RESET_F; 1351 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
1023 /* Enable End-Of-Frame Interrupt */ 1352 __raw_writel(cifr, pcdev->base + CIFR);
1024 CICR0 &= ~CICR0_EOFM; 1353
1025 /* Restart the Capture Interface */ 1354 cicr0 = __raw_readl(pcdev->base + CICR0);
1026 CICR0 |= CICR0_ENB; 1355 cicr0 &= ~CICR0_EOFM; /* Enable End-Of-Frame Interrupt */
1356 cicr0 |= CICR0_ENB; /* Restart the Capture Interface */
1357 __raw_writel(cicr0, pcdev->base + CICR0);
1027 } 1358 }
1028 1359
1029 return ret; 1360 return ret;
@@ -1035,13 +1366,13 @@ static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1035 .remove = pxa_camera_remove_device, 1366 .remove = pxa_camera_remove_device,
1036 .suspend = pxa_camera_suspend, 1367 .suspend = pxa_camera_suspend,
1037 .resume = pxa_camera_resume, 1368 .resume = pxa_camera_resume,
1038 .set_fmt_cap = pxa_camera_set_fmt_cap, 1369 .get_formats = pxa_camera_get_formats,
1039 .try_fmt_cap = pxa_camera_try_fmt_cap, 1370 .set_fmt = pxa_camera_set_fmt,
1371 .try_fmt = pxa_camera_try_fmt,
1040 .init_videobuf = pxa_camera_init_videobuf, 1372 .init_videobuf = pxa_camera_init_videobuf,
1041 .reqbufs = pxa_camera_reqbufs, 1373 .reqbufs = pxa_camera_reqbufs,
1042 .poll = pxa_camera_poll, 1374 .poll = pxa_camera_poll,
1043 .querycap = pxa_camera_querycap, 1375 .querycap = pxa_camera_querycap,
1044 .try_bus_param = pxa_camera_try_bus_param,
1045 .set_bus_param = pxa_camera_set_bus_param, 1376 .set_bus_param = pxa_camera_set_bus_param,
1046}; 1377};
1047 1378
@@ -1092,14 +1423,17 @@ static int pxa_camera_probe(struct platform_device *pdev)
1092 "data widths, using default 10 bit\n"); 1423 "data widths, using default 10 bit\n");
1093 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10; 1424 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1094 } 1425 }
1095 pcdev->platform_mclk_10khz = pcdev->pdata->mclk_10khz; 1426 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
1096 if (!pcdev->platform_mclk_10khz) { 1427 if (!pcdev->mclk) {
1097 dev_warn(&pdev->dev, 1428 dev_warn(&pdev->dev,
1098 "mclk_10khz == 0! Please, fix your platform data. " 1429 "mclk == 0! Please, fix your platform data. "
1099 "Using default 20MHz\n"); 1430 "Using default 20MHz\n");
1100 pcdev->platform_mclk_10khz = 2000; 1431 pcdev->mclk = 20000000;
1101 } 1432 }
1102 1433
1434 pcdev->dev = &pdev->dev;
1435 pcdev->mclk_divisor = mclk_get_divisor(pcdev);
1436
1103 INIT_LIST_HEAD(&pcdev->capture); 1437 INIT_LIST_HEAD(&pcdev->capture);
1104 spin_lock_init(&pcdev->lock); 1438 spin_lock_init(&pcdev->lock);
1105 1439
@@ -1119,7 +1453,6 @@ static int pxa_camera_probe(struct platform_device *pdev)
1119 } 1453 }
1120 pcdev->irq = irq; 1454 pcdev->irq = irq;
1121 pcdev->base = base; 1455 pcdev->base = base;
1122 pcdev->dev = &pdev->dev;
1123 1456
1124 /* request dma */ 1457 /* request dma */
1125 err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH, 1458 err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,