diff options
author | Hans Verkuil <hverkuil@xs4all.nl> | 2008-04-22 13:42:16 -0400 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@infradead.org> | 2008-04-24 13:07:44 -0400 |
commit | 9b2e5c6bea4e2ddd5d66d23341f9763cbcad8de6 (patch) | |
tree | b0c843189690557a39a5bfc0611184a9edbc4cbd /drivers/media/video/ivtv/ivtv-irq.c | |
parent | c9aec06f4a6029edd84022276e2bfadab5e85ade (diff) |
V4L/DVB (7245): ivtv: start timer for each DMA transfer
The DMA timeout timer was started once for each set of DMA transfers,
but it should be started for each single DMA transfer.
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'drivers/media/video/ivtv/ivtv-irq.c')
-rw-r--r-- | drivers/media/video/ivtv/ivtv-irq.c | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/drivers/media/video/ivtv/ivtv-irq.c b/drivers/media/video/ivtv/ivtv-irq.c index 65604dde9726..a329c4689dbf 100644 --- a/drivers/media/video/ivtv/ivtv-irq.c +++ b/drivers/media/video/ivtv/ivtv-irq.c | |||
@@ -384,6 +384,8 @@ static void ivtv_dma_enc_start_xfer(struct ivtv_stream *s) | |||
384 | ivtv_stream_sync_for_device(s); | 384 | ivtv_stream_sync_for_device(s); |
385 | write_reg(s->sg_handle, IVTV_REG_ENCDMAADDR); | 385 | write_reg(s->sg_handle, IVTV_REG_ENCDMAADDR); |
386 | write_reg_sync(read_reg(IVTV_REG_DMAXFER) | 0x02, IVTV_REG_DMAXFER); | 386 | write_reg_sync(read_reg(IVTV_REG_DMAXFER) | 0x02, IVTV_REG_DMAXFER); |
387 | itv->dma_timer.expires = jiffies + msecs_to_jiffies(100); | ||
388 | add_timer(&itv->dma_timer); | ||
387 | } | 389 | } |
388 | 390 | ||
389 | static void ivtv_dma_dec_start_xfer(struct ivtv_stream *s) | 391 | static void ivtv_dma_dec_start_xfer(struct ivtv_stream *s) |
@@ -398,6 +400,8 @@ static void ivtv_dma_dec_start_xfer(struct ivtv_stream *s) | |||
398 | ivtv_stream_sync_for_device(s); | 400 | ivtv_stream_sync_for_device(s); |
399 | write_reg(s->sg_handle, IVTV_REG_DECDMAADDR); | 401 | write_reg(s->sg_handle, IVTV_REG_DECDMAADDR); |
400 | write_reg_sync(read_reg(IVTV_REG_DMAXFER) | 0x01, IVTV_REG_DMAXFER); | 402 | write_reg_sync(read_reg(IVTV_REG_DMAXFER) | 0x01, IVTV_REG_DMAXFER); |
403 | itv->dma_timer.expires = jiffies + msecs_to_jiffies(100); | ||
404 | add_timer(&itv->dma_timer); | ||
401 | } | 405 | } |
402 | 406 | ||
403 | /* start the encoder DMA */ | 407 | /* start the encoder DMA */ |
@@ -459,8 +463,6 @@ static void ivtv_dma_enc_start(struct ivtv_stream *s) | |||
459 | ivtv_dma_enc_start_xfer(s); | 463 | ivtv_dma_enc_start_xfer(s); |
460 | set_bit(IVTV_F_I_DMA, &itv->i_flags); | 464 | set_bit(IVTV_F_I_DMA, &itv->i_flags); |
461 | itv->cur_dma_stream = s->type; | 465 | itv->cur_dma_stream = s->type; |
462 | itv->dma_timer.expires = jiffies + msecs_to_jiffies(100); | ||
463 | add_timer(&itv->dma_timer); | ||
464 | } | 466 | } |
465 | } | 467 | } |
466 | 468 | ||
@@ -481,8 +483,6 @@ static void ivtv_dma_dec_start(struct ivtv_stream *s) | |||
481 | ivtv_dma_dec_start_xfer(s); | 483 | ivtv_dma_dec_start_xfer(s); |
482 | set_bit(IVTV_F_I_DMA, &itv->i_flags); | 484 | set_bit(IVTV_F_I_DMA, &itv->i_flags); |
483 | itv->cur_dma_stream = s->type; | 485 | itv->cur_dma_stream = s->type; |
484 | itv->dma_timer.expires = jiffies + msecs_to_jiffies(100); | ||
485 | add_timer(&itv->dma_timer); | ||
486 | } | 486 | } |
487 | 487 | ||
488 | static void ivtv_irq_dma_read(struct ivtv *itv) | 488 | static void ivtv_irq_dma_read(struct ivtv *itv) |
@@ -492,10 +492,11 @@ static void ivtv_irq_dma_read(struct ivtv *itv) | |||
492 | int hw_stream_type = 0; | 492 | int hw_stream_type = 0; |
493 | 493 | ||
494 | IVTV_DEBUG_HI_IRQ("DEC DMA READ\n"); | 494 | IVTV_DEBUG_HI_IRQ("DEC DMA READ\n"); |
495 | if (!test_bit(IVTV_F_I_UDMA, &itv->i_flags) && itv->cur_dma_stream < 0) { | 495 | |
496 | del_timer(&itv->dma_timer); | 496 | del_timer(&itv->dma_timer); |
497 | |||
498 | if (!test_bit(IVTV_F_I_UDMA, &itv->i_flags) && itv->cur_dma_stream < 0) | ||
497 | return; | 499 | return; |
498 | } | ||
499 | 500 | ||
500 | if (!test_bit(IVTV_F_I_UDMA, &itv->i_flags)) { | 501 | if (!test_bit(IVTV_F_I_UDMA, &itv->i_flags)) { |
501 | s = &itv->streams[itv->cur_dma_stream]; | 502 | s = &itv->streams[itv->cur_dma_stream]; |
@@ -543,7 +544,6 @@ static void ivtv_irq_dma_read(struct ivtv *itv) | |||
543 | } | 544 | } |
544 | wake_up(&s->waitq); | 545 | wake_up(&s->waitq); |
545 | } | 546 | } |
546 | del_timer(&itv->dma_timer); | ||
547 | clear_bit(IVTV_F_I_UDMA, &itv->i_flags); | 547 | clear_bit(IVTV_F_I_UDMA, &itv->i_flags); |
548 | clear_bit(IVTV_F_I_DMA, &itv->i_flags); | 548 | clear_bit(IVTV_F_I_DMA, &itv->i_flags); |
549 | itv->cur_dma_stream = -1; | 549 | itv->cur_dma_stream = -1; |
@@ -557,10 +557,12 @@ static void ivtv_irq_enc_dma_complete(struct ivtv *itv) | |||
557 | 557 | ||
558 | ivtv_api_get_data(&itv->enc_mbox, IVTV_MBOX_DMA_END, data); | 558 | ivtv_api_get_data(&itv->enc_mbox, IVTV_MBOX_DMA_END, data); |
559 | IVTV_DEBUG_HI_IRQ("ENC DMA COMPLETE %x %d (%d)\n", data[0], data[1], itv->cur_dma_stream); | 559 | IVTV_DEBUG_HI_IRQ("ENC DMA COMPLETE %x %d (%d)\n", data[0], data[1], itv->cur_dma_stream); |
560 | if (itv->cur_dma_stream < 0) { | 560 | |
561 | del_timer(&itv->dma_timer); | 561 | del_timer(&itv->dma_timer); |
562 | |||
563 | if (itv->cur_dma_stream < 0) | ||
562 | return; | 564 | return; |
563 | } | 565 | |
564 | s = &itv->streams[itv->cur_dma_stream]; | 566 | s = &itv->streams[itv->cur_dma_stream]; |
565 | ivtv_stream_sync_for_cpu(s); | 567 | ivtv_stream_sync_for_cpu(s); |
566 | 568 | ||
@@ -585,7 +587,6 @@ static void ivtv_irq_enc_dma_complete(struct ivtv *itv) | |||
585 | ivtv_dma_enc_start_xfer(s); | 587 | ivtv_dma_enc_start_xfer(s); |
586 | return; | 588 | return; |
587 | } | 589 | } |
588 | del_timer(&itv->dma_timer); | ||
589 | clear_bit(IVTV_F_I_DMA, &itv->i_flags); | 590 | clear_bit(IVTV_F_I_DMA, &itv->i_flags); |
590 | itv->cur_dma_stream = -1; | 591 | itv->cur_dma_stream = -1; |
591 | dma_post(s); | 592 | dma_post(s); |