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authorHans Verkuil <hverkuil@xs4all.nl>2008-10-04 07:05:30 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2008-10-13 07:08:01 -0400
commita8b864354e060dda1000e62d1fea7c1274581caf (patch)
tree7b1e70dc49c1605a7cdad6b460ea9f602a24b161 /drivers/media/video/ivtv/ivtv-driver.h
parent3c7b933bea2ee380d54b57b99dee42b1726a4eaa (diff)
V4L/DVB (9162): ivtv: fix raw/sliced VBI mixup
The service_set field was used in saa7115 and cx25840 to determine whether raw or sliced VBI was desired. This is incorrect since it is perfectly valid to select sliced VBI with a service_set of 0. Instead these drivers should checked on VIDIOC_S_FMT whether the type field matches the raw or sliced VBI type. Updated ivtv accordingly. Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/video/ivtv/ivtv-driver.h')
-rw-r--r--drivers/media/video/ivtv/ivtv-driver.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/media/video/ivtv/ivtv-driver.h b/drivers/media/video/ivtv/ivtv-driver.h
index b76a12268637..be2d779dba12 100644
--- a/drivers/media/video/ivtv/ivtv-driver.h
+++ b/drivers/media/video/ivtv/ivtv-driver.h
@@ -750,6 +750,12 @@ void ivtv_read_eeprom(struct ivtv *itv, struct tveeprom *tv);
750/* First-open initialization: load firmware, init cx25840, etc. */ 750/* First-open initialization: load firmware, init cx25840, etc. */
751int ivtv_init_on_first_open(struct ivtv *itv); 751int ivtv_init_on_first_open(struct ivtv *itv);
752 752
753/* Test if the current VBI mode is raw (1) or sliced (0) */
754static inline int ivtv_raw_vbi(const struct ivtv *itv)
755{
756 return itv->vbi.in.type == V4L2_BUF_TYPE_VBI_CAPTURE;
757}
758
753/* This is a PCI post thing, where if the pci register is not read, then 759/* This is a PCI post thing, where if the pci register is not read, then
754 the write doesn't always take effect right away. By reading back the 760 the write doesn't always take effect right away. By reading back the
755 register any pending PCI writes will be performed (in order), and so 761 register any pending PCI writes will be performed (in order), and so