diff options
author | Jean-Francois Moine <moinejf@free.fr> | 2008-07-03 10:09:12 -0400 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@infradead.org> | 2008-07-20 06:16:41 -0400 |
commit | bf7f0b98426b54c29ec8100a3f1963114c2f2ef0 (patch) | |
tree | c3d43d2240020fded85674066fd2cb7a5a503f86 /drivers/media/video/gspca/etoms.c | |
parent | 0d2a722ddae5e736a5c36a1b99ee4ca59a8373bc (diff) |
V4L/DVB (8193): gspca: Input buffer may be changed on reg write.
Done for conex, etoms, pac7311, sonixj, t613 and tv8532.
Code cleanup for some other subdrivers.
Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'drivers/media/video/gspca/etoms.c')
-rw-r--r-- | drivers/media/video/gspca/etoms.c | 279 |
1 files changed, 141 insertions, 138 deletions
diff --git a/drivers/media/video/gspca/etoms.c b/drivers/media/video/gspca/etoms.c index 195b8123ba75..ed7a8f9c0d7a 100644 --- a/drivers/media/video/gspca/etoms.c +++ b/drivers/media/video/gspca/etoms.c | |||
@@ -22,8 +22,8 @@ | |||
22 | 22 | ||
23 | #include "gspca.h" | 23 | #include "gspca.h" |
24 | 24 | ||
25 | #define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 1, 0) | 25 | #define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 1, 3) |
26 | static const char version[] = "2.1.0"; | 26 | static const char version[] = "2.1.3"; |
27 | 27 | ||
28 | MODULE_AUTHOR("Michel Xhaard <mxhaard@users.sourceforge.net>"); | 28 | MODULE_AUTHOR("Michel Xhaard <mxhaard@users.sourceforge.net>"); |
29 | MODULE_DESCRIPTION("Etoms USB Camera Driver"); | 29 | MODULE_DESCRIPTION("Etoms USB Camera Driver"); |
@@ -213,7 +213,7 @@ static __u8 I2c3[] = { 0x12, 0x05 }; | |||
213 | 213 | ||
214 | static __u8 I2c4[] = { 0x41, 0x08 }; | 214 | static __u8 I2c4[] = { 0x41, 0x08 }; |
215 | 215 | ||
216 | static void Et_RegRead(struct usb_device *dev, | 216 | static void reg_r(struct usb_device *dev, |
217 | __u16 index, __u8 *buffer, int len) | 217 | __u16 index, __u8 *buffer, int len) |
218 | { | 218 | { |
219 | usb_control_msg(dev, | 219 | usb_control_msg(dev, |
@@ -223,14 +223,17 @@ static void Et_RegRead(struct usb_device *dev, | |||
223 | 0, index, buffer, len, 500); | 223 | 0, index, buffer, len, 500); |
224 | } | 224 | } |
225 | 225 | ||
226 | static void Et_RegWrite(struct usb_device *dev, | 226 | static void reg_w(struct usb_device *dev, |
227 | __u16 index, __u8 *buffer, __u16 len) | 227 | __u16 index, __u8 *buffer, __u16 len) |
228 | { | 228 | { |
229 | __u8 tmpbuf[8]; | ||
230 | |||
231 | memcpy(tmpbuf, buffer, len); | ||
229 | usb_control_msg(dev, | 232 | usb_control_msg(dev, |
230 | usb_sndctrlpipe(dev, 0), | 233 | usb_sndctrlpipe(dev, 0), |
231 | 0, | 234 | 0, |
232 | USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_INTERFACE, | 235 | USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_INTERFACE, |
233 | 0, index, buffer, len, 500); | 236 | 0, index, tmpbuf, len, 500); |
234 | } | 237 | } |
235 | 238 | ||
236 | static int Et_i2cwrite(struct usb_device *dev, __u8 reg, __u8 *buffer, | 239 | static int Et_i2cwrite(struct usb_device *dev, __u8 reg, __u8 *buffer, |
@@ -243,14 +246,14 @@ static int Et_i2cwrite(struct usb_device *dev, __u8 reg, __u8 *buffer, | |||
243 | 246 | ||
244 | ptchcount = (((length & 0x07) << 4) | (mode & 0x03)); | 247 | ptchcount = (((length & 0x07) << 4) | (mode & 0x03)); |
245 | /* set the base address */ | 248 | /* set the base address */ |
246 | Et_RegWrite(dev, ET_I2C_BASE, &base, 1); | 249 | reg_w(dev, ET_I2C_BASE, &base, 1); |
247 | /* set count and prefetch */ | 250 | /* set count and prefetch */ |
248 | Et_RegWrite(dev, ET_I2C_COUNT, &ptchcount, 1); | 251 | reg_w(dev, ET_I2C_COUNT, &ptchcount, 1); |
249 | /* set the register base */ | 252 | /* set the register base */ |
250 | Et_RegWrite(dev, ET_I2C_REG, ®, 1); | 253 | reg_w(dev, ET_I2C_REG, ®, 1); |
251 | j = length - 1; | 254 | j = length - 1; |
252 | for (i = 0; i < length; i++) { | 255 | for (i = 0; i < length; i++) { |
253 | Et_RegWrite(dev, (ET_I2C_DATA0 + j), &buffer[j], 1); | 256 | reg_w(dev, (ET_I2C_DATA0 + j), &buffer[j], 1); |
254 | j--; | 257 | j--; |
255 | } | 258 | } |
256 | return 0; | 259 | return 0; |
@@ -267,17 +270,17 @@ static int Et_i2cread(struct usb_device *dev, __u8 reg, __u8 *buffer, | |||
267 | 270 | ||
268 | ptchcount = (((length & 0x07) << 4) | (mode & 0x03)); | 271 | ptchcount = (((length & 0x07) << 4) | (mode & 0x03)); |
269 | /* set the base address */ | 272 | /* set the base address */ |
270 | Et_RegWrite(dev, ET_I2C_BASE, &base, 1); | 273 | reg_w(dev, ET_I2C_BASE, &base, 1); |
271 | /* set count and prefetch */ | 274 | /* set count and prefetch */ |
272 | Et_RegWrite(dev, ET_I2C_COUNT, &ptchcount, 1); | 275 | reg_w(dev, ET_I2C_COUNT, &ptchcount, 1); |
273 | /* set the register base */ | 276 | /* set the register base */ |
274 | Et_RegWrite(dev, ET_I2C_REG, ®, 1); | 277 | reg_w(dev, ET_I2C_REG, ®, 1); |
275 | Et_RegWrite(dev, ET_I2C_PREFETCH, &prefetch, 1); | 278 | reg_w(dev, ET_I2C_PREFETCH, &prefetch, 1); |
276 | prefetch = 0x00; | 279 | prefetch = 0x00; |
277 | Et_RegWrite(dev, ET_I2C_PREFETCH, &prefetch, 1); | 280 | reg_w(dev, ET_I2C_PREFETCH, &prefetch, 1); |
278 | j = length - 1; | 281 | j = length - 1; |
279 | for (i = 0; i < length; i++) { | 282 | for (i = 0; i < length; i++) { |
280 | Et_RegRead(dev, (ET_I2C_DATA0 + j), &buffer[j], 1); | 283 | reg_r(dev, (ET_I2C_DATA0 + j), &buffer[j], 1); |
281 | j--; | 284 | j--; |
282 | } | 285 | } |
283 | return 0; | 286 | return 0; |
@@ -289,7 +292,7 @@ static int Et_WaitStatus(struct usb_device *dev) | |||
289 | int retry = 10; | 292 | int retry = 10; |
290 | 293 | ||
291 | while (retry--) { | 294 | while (retry--) { |
292 | Et_RegRead(dev, ET_ClCK, &bytereceived, 1); | 295 | reg_r(dev, ET_ClCK, &bytereceived, 1); |
293 | if (bytereceived != 0) | 296 | if (bytereceived != 0) |
294 | return 1; | 297 | return 1; |
295 | } | 298 | } |
@@ -301,7 +304,7 @@ static int Et_videoOff(struct usb_device *dev) | |||
301 | int err; | 304 | int err; |
302 | __u8 stopvideo = 0; | 305 | __u8 stopvideo = 0; |
303 | 306 | ||
304 | Et_RegWrite(dev, ET_GPIO_OUT, &stopvideo, 1); | 307 | reg_w(dev, ET_GPIO_OUT, &stopvideo, 1); |
305 | err = Et_WaitStatus(dev); | 308 | err = Et_WaitStatus(dev); |
306 | if (!err) | 309 | if (!err) |
307 | PDEBUG(D_ERR, "timeout Et_waitStatus VideoON"); | 310 | PDEBUG(D_ERR, "timeout Et_waitStatus VideoON"); |
@@ -313,7 +316,7 @@ static int Et_videoOn(struct usb_device *dev) | |||
313 | int err; | 316 | int err; |
314 | __u8 startvideo = 0x10; /* set Bit5 */ | 317 | __u8 startvideo = 0x10; /* set Bit5 */ |
315 | 318 | ||
316 | Et_RegWrite(dev, ET_GPIO_OUT, &startvideo, 1); | 319 | reg_w(dev, ET_GPIO_OUT, &startvideo, 1); |
317 | err = Et_WaitStatus(dev); | 320 | err = Et_WaitStatus(dev); |
318 | if (!err) | 321 | if (!err) |
319 | PDEBUG(D_ERR, "timeout Et_waitStatus VideoOFF"); | 322 | PDEBUG(D_ERR, "timeout Et_waitStatus VideoOFF"); |
@@ -329,156 +332,156 @@ static void Et_init2(struct gspca_dev *gspca_dev) | |||
329 | 332 | ||
330 | PDEBUG(D_STREAM, "Open Init2 ET"); | 333 | PDEBUG(D_STREAM, "Open Init2 ET"); |
331 | value = 0x2f; | 334 | value = 0x2f; |
332 | Et_RegWrite(dev, ET_GPIO_DIR_CTRL, &value, 1); | 335 | reg_w(dev, ET_GPIO_DIR_CTRL, &value, 1); |
333 | value = 0x10; | 336 | value = 0x10; |
334 | Et_RegWrite(dev, ET_GPIO_OUT, &value, 1); | 337 | reg_w(dev, ET_GPIO_OUT, &value, 1); |
335 | Et_RegRead(dev, ET_GPIO_IN, &received, 1); | 338 | reg_r(dev, ET_GPIO_IN, &received, 1); |
336 | value = 0x14; /* 0x14 // 0x16 enabled pattern */ | 339 | value = 0x14; /* 0x14 // 0x16 enabled pattern */ |
337 | Et_RegWrite(dev, ET_ClCK, &value, 1); | 340 | reg_w(dev, ET_ClCK, &value, 1); |
338 | value = 0x1b; | 341 | value = 0x1b; |
339 | Et_RegWrite(dev, ET_CTRL, &value, 1); | 342 | reg_w(dev, ET_CTRL, &value, 1); |
340 | 343 | ||
341 | /* compression et subsampling */ | 344 | /* compression et subsampling */ |
342 | if (gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].mode) | 345 | if (gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].mode) |
343 | value = ET_COMP_VAL1; /* 320 */ | 346 | value = ET_COMP_VAL1; /* 320 */ |
344 | else | 347 | else |
345 | value = ET_COMP_VAL0; /* 640 */ | 348 | value = ET_COMP_VAL0; /* 640 */ |
346 | Et_RegWrite(dev, ET_COMP, &value, 1); | 349 | reg_w(dev, ET_COMP, &value, 1); |
347 | value = 0x1f; | 350 | value = 0x1f; |
348 | Et_RegWrite(dev, ET_MAXQt, &value, 1); | 351 | reg_w(dev, ET_MAXQt, &value, 1); |
349 | value = 0x04; | 352 | value = 0x04; |
350 | Et_RegWrite(dev, ET_MINQt, &value, 1); | 353 | reg_w(dev, ET_MINQt, &value, 1); |
351 | /* undocumented registers */ | 354 | /* undocumented registers */ |
352 | value = 0xff; | 355 | value = 0xff; |
353 | Et_RegWrite(dev, ET_REG1d, &value, 1); | 356 | reg_w(dev, ET_REG1d, &value, 1); |
354 | value = 0xff; | 357 | value = 0xff; |
355 | Et_RegWrite(dev, ET_REG1e, &value, 1); | 358 | reg_w(dev, ET_REG1e, &value, 1); |
356 | value = 0xff; | 359 | value = 0xff; |
357 | Et_RegWrite(dev, ET_REG1f, &value, 1); | 360 | reg_w(dev, ET_REG1f, &value, 1); |
358 | value = 0x35; | 361 | value = 0x35; |
359 | Et_RegWrite(dev, ET_REG20, &value, 1); | 362 | reg_w(dev, ET_REG20, &value, 1); |
360 | value = 0x01; | 363 | value = 0x01; |
361 | Et_RegWrite(dev, ET_REG21, &value, 1); | 364 | reg_w(dev, ET_REG21, &value, 1); |
362 | value = 0x00; | 365 | value = 0x00; |
363 | Et_RegWrite(dev, ET_REG22, &value, 1); | 366 | reg_w(dev, ET_REG22, &value, 1); |
364 | value = 0xff; | 367 | value = 0xff; |
365 | Et_RegWrite(dev, ET_REG23, &value, 1); | 368 | reg_w(dev, ET_REG23, &value, 1); |
366 | value = 0xff; | 369 | value = 0xff; |
367 | Et_RegWrite(dev, ET_REG24, &value, 1); | 370 | reg_w(dev, ET_REG24, &value, 1); |
368 | value = 0x0f; | 371 | value = 0x0f; |
369 | Et_RegWrite(dev, ET_REG25, &value, 1); | 372 | reg_w(dev, ET_REG25, &value, 1); |
370 | /* colors setting */ | 373 | /* colors setting */ |
371 | value = 0x11; | 374 | value = 0x11; |
372 | Et_RegWrite(dev, 0x30, &value, 1); /* 0x30 */ | 375 | reg_w(dev, 0x30, &value, 1); /* 0x30 */ |
373 | value = 0x40; | 376 | value = 0x40; |
374 | Et_RegWrite(dev, 0x31, &value, 1); | 377 | reg_w(dev, 0x31, &value, 1); |
375 | value = 0x00; | 378 | value = 0x00; |
376 | Et_RegWrite(dev, 0x32, &value, 1); | 379 | reg_w(dev, 0x32, &value, 1); |
377 | value = 0x00; | 380 | value = 0x00; |
378 | Et_RegWrite(dev, ET_O_RED, &value, 1); /* 0x34 */ | 381 | reg_w(dev, ET_O_RED, &value, 1); /* 0x34 */ |
379 | value = 0x00; | 382 | value = 0x00; |
380 | Et_RegWrite(dev, ET_O_GREEN1, &value, 1); | 383 | reg_w(dev, ET_O_GREEN1, &value, 1); |
381 | value = 0x00; | 384 | value = 0x00; |
382 | Et_RegWrite(dev, ET_O_BLUE, &value, 1); | 385 | reg_w(dev, ET_O_BLUE, &value, 1); |
383 | value = 0x00; | 386 | value = 0x00; |
384 | Et_RegWrite(dev, ET_O_GREEN2, &value, 1); | 387 | reg_w(dev, ET_O_GREEN2, &value, 1); |
385 | /*************/ | 388 | /*************/ |
386 | value = 0x80; | 389 | value = 0x80; |
387 | Et_RegWrite(dev, ET_G_RED, &value, 1); /* 0x4d */ | 390 | reg_w(dev, ET_G_RED, &value, 1); /* 0x4d */ |
388 | value = 0x80; | 391 | value = 0x80; |
389 | Et_RegWrite(dev, ET_G_GREEN1, &value, 1); | 392 | reg_w(dev, ET_G_GREEN1, &value, 1); |
390 | value = 0x80; | 393 | value = 0x80; |
391 | Et_RegWrite(dev, ET_G_BLUE, &value, 1); | 394 | reg_w(dev, ET_G_BLUE, &value, 1); |
392 | value = 0x80; | 395 | value = 0x80; |
393 | Et_RegWrite(dev, ET_G_GREEN2, &value, 1); | 396 | reg_w(dev, ET_G_GREEN2, &value, 1); |
394 | value = 0x00; | 397 | value = 0x00; |
395 | Et_RegWrite(dev, ET_G_GR_H, &value, 1); | 398 | reg_w(dev, ET_G_GR_H, &value, 1); |
396 | value = 0x00; | 399 | value = 0x00; |
397 | Et_RegWrite(dev, ET_G_GB_H, &value, 1); /* 0x52 */ | 400 | reg_w(dev, ET_G_GB_H, &value, 1); /* 0x52 */ |
398 | /* Window control registers */ | 401 | /* Window control registers */ |
399 | 402 | ||
400 | value = 0x80; /* use cmc_out */ | 403 | value = 0x80; /* use cmc_out */ |
401 | Et_RegWrite(dev, 0x61, &value, 1); | 404 | reg_w(dev, 0x61, &value, 1); |
402 | 405 | ||
403 | value = 0x02; | 406 | value = 0x02; |
404 | Et_RegWrite(dev, 0x62, &value, 1); | 407 | reg_w(dev, 0x62, &value, 1); |
405 | value = 0x03; | 408 | value = 0x03; |
406 | Et_RegWrite(dev, 0x63, &value, 1); | 409 | reg_w(dev, 0x63, &value, 1); |
407 | value = 0x14; | 410 | value = 0x14; |
408 | Et_RegWrite(dev, 0x64, &value, 1); | 411 | reg_w(dev, 0x64, &value, 1); |
409 | value = 0x0e; | 412 | value = 0x0e; |
410 | Et_RegWrite(dev, 0x65, &value, 1); | 413 | reg_w(dev, 0x65, &value, 1); |
411 | value = 0x02; | 414 | value = 0x02; |
412 | Et_RegWrite(dev, 0x66, &value, 1); | 415 | reg_w(dev, 0x66, &value, 1); |
413 | value = 0x02; | 416 | value = 0x02; |
414 | Et_RegWrite(dev, 0x67, &value, 1); | 417 | reg_w(dev, 0x67, &value, 1); |
415 | 418 | ||
416 | /**************************************/ | 419 | /**************************************/ |
417 | value = 0x8f; | 420 | value = 0x8f; |
418 | Et_RegWrite(dev, ET_SYNCHRO, &value, 1); /* 0x68 */ | 421 | reg_w(dev, ET_SYNCHRO, &value, 1); /* 0x68 */ |
419 | value = 0x69; /* 0x6a //0x69 */ | 422 | value = 0x69; /* 0x6a //0x69 */ |
420 | Et_RegWrite(dev, ET_STARTX, &value, 1); | 423 | reg_w(dev, ET_STARTX, &value, 1); |
421 | value = 0x0d; /* 0x0d //0x0c */ | 424 | value = 0x0d; /* 0x0d //0x0c */ |
422 | Et_RegWrite(dev, ET_STARTY, &value, 1); | 425 | reg_w(dev, ET_STARTY, &value, 1); |
423 | value = 0x80; | 426 | value = 0x80; |
424 | Et_RegWrite(dev, ET_WIDTH_LOW, &value, 1); | 427 | reg_w(dev, ET_WIDTH_LOW, &value, 1); |
425 | value = 0xe0; | 428 | value = 0xe0; |
426 | Et_RegWrite(dev, ET_HEIGTH_LOW, &value, 1); | 429 | reg_w(dev, ET_HEIGTH_LOW, &value, 1); |
427 | value = 0x60; | 430 | value = 0x60; |
428 | Et_RegWrite(dev, ET_W_H_HEIGTH, &value, 1); /* 6d */ | 431 | reg_w(dev, ET_W_H_HEIGTH, &value, 1); /* 6d */ |
429 | value = 0x86; | 432 | value = 0x86; |
430 | Et_RegWrite(dev, ET_REG6e, &value, 1); | 433 | reg_w(dev, ET_REG6e, &value, 1); |
431 | value = 0x01; | 434 | value = 0x01; |
432 | Et_RegWrite(dev, ET_REG6f, &value, 1); | 435 | reg_w(dev, ET_REG6f, &value, 1); |
433 | value = 0x26; | 436 | value = 0x26; |
434 | Et_RegWrite(dev, ET_REG70, &value, 1); | 437 | reg_w(dev, ET_REG70, &value, 1); |
435 | value = 0x7a; | 438 | value = 0x7a; |
436 | Et_RegWrite(dev, ET_REG71, &value, 1); | 439 | reg_w(dev, ET_REG71, &value, 1); |
437 | value = 0x01; | 440 | value = 0x01; |
438 | Et_RegWrite(dev, ET_REG72, &value, 1); | 441 | reg_w(dev, ET_REG72, &value, 1); |
439 | /* Clock Pattern registers ***************** */ | 442 | /* Clock Pattern registers ***************** */ |
440 | value = 0x00; | 443 | value = 0x00; |
441 | Et_RegWrite(dev, ET_REG73, &value, 1); | 444 | reg_w(dev, ET_REG73, &value, 1); |
442 | value = 0x18; /* 0x28 */ | 445 | value = 0x18; /* 0x28 */ |
443 | Et_RegWrite(dev, ET_REG74, &value, 1); | 446 | reg_w(dev, ET_REG74, &value, 1); |
444 | value = 0x0f; /* 0x01 */ | 447 | value = 0x0f; /* 0x01 */ |
445 | Et_RegWrite(dev, ET_REG75, &value, 1); | 448 | reg_w(dev, ET_REG75, &value, 1); |
446 | /**********************************************/ | 449 | /**********************************************/ |
447 | value = 0x20; | 450 | value = 0x20; |
448 | Et_RegWrite(dev, 0x8a, &value, 1); | 451 | reg_w(dev, 0x8a, &value, 1); |
449 | value = 0x0f; | 452 | value = 0x0f; |
450 | Et_RegWrite(dev, 0x8d, &value, 1); | 453 | reg_w(dev, 0x8d, &value, 1); |
451 | value = 0x08; | 454 | value = 0x08; |
452 | Et_RegWrite(dev, 0x8e, &value, 1); | 455 | reg_w(dev, 0x8e, &value, 1); |
453 | /**************************************/ | 456 | /**************************************/ |
454 | value = 0x08; | 457 | value = 0x08; |
455 | Et_RegWrite(dev, 0x03, &value, 1); | 458 | reg_w(dev, 0x03, &value, 1); |
456 | value = 0x03; | 459 | value = 0x03; |
457 | Et_RegWrite(dev, ET_PXL_CLK, &value, 1); | 460 | reg_w(dev, ET_PXL_CLK, &value, 1); |
458 | value = 0xff; | 461 | value = 0xff; |
459 | Et_RegWrite(dev, 0x81, &value, 1); | 462 | reg_w(dev, 0x81, &value, 1); |
460 | value = 0x00; | 463 | value = 0x00; |
461 | Et_RegWrite(dev, 0x80, &value, 1); | 464 | reg_w(dev, 0x80, &value, 1); |
462 | value = 0xff; | 465 | value = 0xff; |
463 | Et_RegWrite(dev, 0x81, &value, 1); | 466 | reg_w(dev, 0x81, &value, 1); |
464 | value = 0x20; | 467 | value = 0x20; |
465 | Et_RegWrite(dev, 0x80, &value, 1); | 468 | reg_w(dev, 0x80, &value, 1); |
466 | value = 0x01; | 469 | value = 0x01; |
467 | Et_RegWrite(dev, 0x03, &value, 1); | 470 | reg_w(dev, 0x03, &value, 1); |
468 | value = 0x00; | 471 | value = 0x00; |
469 | Et_RegWrite(dev, 0x03, &value, 1); | 472 | reg_w(dev, 0x03, &value, 1); |
470 | value = 0x08; | 473 | value = 0x08; |
471 | Et_RegWrite(dev, 0x03, &value, 1); | 474 | reg_w(dev, 0x03, &value, 1); |
472 | /********************************************/ | 475 | /********************************************/ |
473 | 476 | ||
474 | /* Et_RegRead(dev,0x0,ET_I2C_BASE,&received,1); | 477 | /* reg_r(dev,0x0,ET_I2C_BASE,&received,1); |
475 | always 0x40 as the pas106 ??? */ | 478 | always 0x40 as the pas106 ??? */ |
476 | /* set the sensor */ | 479 | /* set the sensor */ |
477 | if (gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].mode) { | 480 | if (gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].mode) { |
478 | value = 0x04; /* 320 */ | 481 | value = 0x04; /* 320 */ |
479 | Et_RegWrite(dev, ET_PXL_CLK, &value, 1); | 482 | reg_w(dev, ET_PXL_CLK, &value, 1); |
480 | /* now set by fifo the FormatLine setting */ | 483 | /* now set by fifo the FormatLine setting */ |
481 | Et_RegWrite(dev, 0x62, FormLine, 6); | 484 | reg_w(dev, 0x62, FormLine, 6); |
482 | } else { /* 640 */ | 485 | } else { /* 640 */ |
483 | /* setting PixelClock | 486 | /* setting PixelClock |
484 | 0x03 mean 24/(3+1) = 6 Mhz | 487 | 0x03 mean 24/(3+1) = 6 Mhz |
@@ -487,24 +490,24 @@ static void Et_init2(struct gspca_dev *gspca_dev) | |||
487 | 0x17 -> 24/(23+1) = 1 Mhz | 490 | 0x17 -> 24/(23+1) = 1 Mhz |
488 | */ | 491 | */ |
489 | value = 0x1e; /* 0x17 */ | 492 | value = 0x1e; /* 0x17 */ |
490 | Et_RegWrite(dev, ET_PXL_CLK, &value, 1); | 493 | reg_w(dev, ET_PXL_CLK, &value, 1); |
491 | /* now set by fifo the FormatLine setting */ | 494 | /* now set by fifo the FormatLine setting */ |
492 | Et_RegWrite(dev, 0x62, FormLine, 6); | 495 | reg_w(dev, 0x62, FormLine, 6); |
493 | } | 496 | } |
494 | 497 | ||
495 | /* set exposure times [ 0..0x78] 0->longvalue 0x78->shortvalue */ | 498 | /* set exposure times [ 0..0x78] 0->longvalue 0x78->shortvalue */ |
496 | value = 0x47; /* 0x47; */ | 499 | value = 0x47; /* 0x47; */ |
497 | Et_RegWrite(dev, 0x81, &value, 1); | 500 | reg_w(dev, 0x81, &value, 1); |
498 | value = 0x40; /* 0x40; */ | 501 | value = 0x40; /* 0x40; */ |
499 | Et_RegWrite(dev, 0x80, &value, 1); | 502 | reg_w(dev, 0x80, &value, 1); |
500 | /* Pedro change */ | 503 | /* Pedro change */ |
501 | /* Brightness change Brith+ decrease value */ | 504 | /* Brightness change Brith+ decrease value */ |
502 | /* Brigth- increase value */ | 505 | /* Brigth- increase value */ |
503 | /* original value = 0x70; */ | 506 | /* original value = 0x70; */ |
504 | value = 0x30; /* 0x20; */ | 507 | value = 0x30; /* 0x20; */ |
505 | Et_RegWrite(dev, 0x81, &value, 1); /* set brightness */ | 508 | reg_w(dev, 0x81, &value, 1); /* set brightness */ |
506 | value = 0x20; /* 0x20; */ | 509 | value = 0x20; /* 0x20; */ |
507 | Et_RegWrite(dev, 0x80, &value, 1); | 510 | reg_w(dev, 0x80, &value, 1); |
508 | } | 511 | } |
509 | 512 | ||
510 | static void setcolors(struct gspca_dev *gspca_dev) | 513 | static void setcolors(struct gspca_dev *gspca_dev) |
@@ -554,16 +557,16 @@ static void Et_init1(struct gspca_dev *gspca_dev) | |||
554 | 557 | ||
555 | PDEBUG(D_STREAM, "Open Init1 ET"); | 558 | PDEBUG(D_STREAM, "Open Init1 ET"); |
556 | value = 7; | 559 | value = 7; |
557 | Et_RegWrite(dev, ET_GPIO_DIR_CTRL, &value, 1); | 560 | reg_w(dev, ET_GPIO_DIR_CTRL, &value, 1); |
558 | Et_RegRead(dev, ET_GPIO_IN, &received, 1); | 561 | reg_r(dev, ET_GPIO_IN, &received, 1); |
559 | value = 1; | 562 | value = 1; |
560 | Et_RegWrite(dev, ET_RESET_ALL, &value, 1); | 563 | reg_w(dev, ET_RESET_ALL, &value, 1); |
561 | value = 0; | 564 | value = 0; |
562 | Et_RegWrite(dev, ET_RESET_ALL, &value, 1); | 565 | reg_w(dev, ET_RESET_ALL, &value, 1); |
563 | value = 0x10; | 566 | value = 0x10; |
564 | Et_RegWrite(dev, ET_ClCK, &value, 1); | 567 | reg_w(dev, ET_ClCK, &value, 1); |
565 | value = 0x19; | 568 | value = 0x19; |
566 | Et_RegWrite(dev, ET_CTRL, &value, 1); | 569 | reg_w(dev, ET_CTRL, &value, 1); |
567 | /* compression et subsampling */ | 570 | /* compression et subsampling */ |
568 | if (gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].mode) | 571 | if (gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].mode) |
569 | value = ET_COMP_VAL1; | 572 | value = ET_COMP_VAL1; |
@@ -573,77 +576,77 @@ static void Et_init1(struct gspca_dev *gspca_dev) | |||
573 | PDEBUG(D_STREAM, "Open mode %d Compression %d", | 576 | PDEBUG(D_STREAM, "Open mode %d Compression %d", |
574 | gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].mode, | 577 | gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].mode, |
575 | value); | 578 | value); |
576 | Et_RegWrite(dev, ET_COMP, &value, 1); | 579 | reg_w(dev, ET_COMP, &value, 1); |
577 | value = 0x1d; | 580 | value = 0x1d; |
578 | Et_RegWrite(dev, ET_MAXQt, &value, 1); | 581 | reg_w(dev, ET_MAXQt, &value, 1); |
579 | value = 0x02; | 582 | value = 0x02; |
580 | Et_RegWrite(dev, ET_MINQt, &value, 1); | 583 | reg_w(dev, ET_MINQt, &value, 1); |
581 | /* undocumented registers */ | 584 | /* undocumented registers */ |
582 | value = 0xff; | 585 | value = 0xff; |
583 | Et_RegWrite(dev, ET_REG1d, &value, 1); | 586 | reg_w(dev, ET_REG1d, &value, 1); |
584 | value = 0xff; | 587 | value = 0xff; |
585 | Et_RegWrite(dev, ET_REG1e, &value, 1); | 588 | reg_w(dev, ET_REG1e, &value, 1); |
586 | value = 0xff; | 589 | value = 0xff; |
587 | Et_RegWrite(dev, ET_REG1f, &value, 1); | 590 | reg_w(dev, ET_REG1f, &value, 1); |
588 | value = 0x35; | 591 | value = 0x35; |
589 | Et_RegWrite(dev, ET_REG20, &value, 1); | 592 | reg_w(dev, ET_REG20, &value, 1); |
590 | value = 0x01; | 593 | value = 0x01; |
591 | Et_RegWrite(dev, ET_REG21, &value, 1); | 594 | reg_w(dev, ET_REG21, &value, 1); |
592 | value = 0x00; | 595 | value = 0x00; |
593 | Et_RegWrite(dev, ET_REG22, &value, 1); | 596 | reg_w(dev, ET_REG22, &value, 1); |
594 | value = 0xf7; | 597 | value = 0xf7; |
595 | Et_RegWrite(dev, ET_REG23, &value, 1); | 598 | reg_w(dev, ET_REG23, &value, 1); |
596 | value = 0xff; | 599 | value = 0xff; |
597 | Et_RegWrite(dev, ET_REG24, &value, 1); | 600 | reg_w(dev, ET_REG24, &value, 1); |
598 | value = 0x07; | 601 | value = 0x07; |
599 | Et_RegWrite(dev, ET_REG25, &value, 1); | 602 | reg_w(dev, ET_REG25, &value, 1); |
600 | /* colors setting */ | 603 | /* colors setting */ |
601 | value = 0x80; | 604 | value = 0x80; |
602 | Et_RegWrite(dev, ET_G_RED, &value, 1); | 605 | reg_w(dev, ET_G_RED, &value, 1); |
603 | value = 0x80; | 606 | value = 0x80; |
604 | Et_RegWrite(dev, ET_G_GREEN1, &value, 1); | 607 | reg_w(dev, ET_G_GREEN1, &value, 1); |
605 | value = 0x80; | 608 | value = 0x80; |
606 | Et_RegWrite(dev, ET_G_BLUE, &value, 1); | 609 | reg_w(dev, ET_G_BLUE, &value, 1); |
607 | value = 0x80; | 610 | value = 0x80; |
608 | Et_RegWrite(dev, ET_G_GREEN2, &value, 1); | 611 | reg_w(dev, ET_G_GREEN2, &value, 1); |
609 | value = 0x00; | 612 | value = 0x00; |
610 | Et_RegWrite(dev, ET_G_GR_H, &value, 1); | 613 | reg_w(dev, ET_G_GR_H, &value, 1); |
611 | value = 0x00; | 614 | value = 0x00; |
612 | Et_RegWrite(dev, ET_G_GB_H, &value, 1); | 615 | reg_w(dev, ET_G_GB_H, &value, 1); |
613 | /* Window control registers */ | 616 | /* Window control registers */ |
614 | value = 0xf0; | 617 | value = 0xf0; |
615 | Et_RegWrite(dev, ET_SYNCHRO, &value, 1); | 618 | reg_w(dev, ET_SYNCHRO, &value, 1); |
616 | value = 0x56; /* 0x56 */ | 619 | value = 0x56; /* 0x56 */ |
617 | Et_RegWrite(dev, ET_STARTX, &value, 1); | 620 | reg_w(dev, ET_STARTX, &value, 1); |
618 | value = 0x05; /* 0x04 */ | 621 | value = 0x05; /* 0x04 */ |
619 | Et_RegWrite(dev, ET_STARTY, &value, 1); | 622 | reg_w(dev, ET_STARTY, &value, 1); |
620 | value = 0x60; | 623 | value = 0x60; |
621 | Et_RegWrite(dev, ET_WIDTH_LOW, &value, 1); | 624 | reg_w(dev, ET_WIDTH_LOW, &value, 1); |
622 | value = 0x20; | 625 | value = 0x20; |
623 | Et_RegWrite(dev, ET_HEIGTH_LOW, &value, 1); | 626 | reg_w(dev, ET_HEIGTH_LOW, &value, 1); |
624 | value = 0x50; | 627 | value = 0x50; |
625 | Et_RegWrite(dev, ET_W_H_HEIGTH, &value, 1); | 628 | reg_w(dev, ET_W_H_HEIGTH, &value, 1); |
626 | value = 0x86; | 629 | value = 0x86; |
627 | Et_RegWrite(dev, ET_REG6e, &value, 1); | 630 | reg_w(dev, ET_REG6e, &value, 1); |
628 | value = 0x01; | 631 | value = 0x01; |
629 | Et_RegWrite(dev, ET_REG6f, &value, 1); | 632 | reg_w(dev, ET_REG6f, &value, 1); |
630 | value = 0x86; | 633 | value = 0x86; |
631 | Et_RegWrite(dev, ET_REG70, &value, 1); | 634 | reg_w(dev, ET_REG70, &value, 1); |
632 | value = 0x14; | 635 | value = 0x14; |
633 | Et_RegWrite(dev, ET_REG71, &value, 1); | 636 | reg_w(dev, ET_REG71, &value, 1); |
634 | value = 0x00; | 637 | value = 0x00; |
635 | Et_RegWrite(dev, ET_REG72, &value, 1); | 638 | reg_w(dev, ET_REG72, &value, 1); |
636 | /* Clock Pattern registers */ | 639 | /* Clock Pattern registers */ |
637 | value = 0x00; | 640 | value = 0x00; |
638 | Et_RegWrite(dev, ET_REG73, &value, 1); | 641 | reg_w(dev, ET_REG73, &value, 1); |
639 | value = 0x00; | 642 | value = 0x00; |
640 | Et_RegWrite(dev, ET_REG74, &value, 1); | 643 | reg_w(dev, ET_REG74, &value, 1); |
641 | value = 0x0a; | 644 | value = 0x0a; |
642 | Et_RegWrite(dev, ET_REG75, &value, 1); | 645 | reg_w(dev, ET_REG75, &value, 1); |
643 | value = 0x04; | 646 | value = 0x04; |
644 | Et_RegWrite(dev, ET_I2C_CLK, &value, 1); | 647 | reg_w(dev, ET_I2C_CLK, &value, 1); |
645 | value = 0x01; | 648 | value = 0x01; |
646 | Et_RegWrite(dev, ET_PXL_CLK, &value, 1); | 649 | reg_w(dev, ET_PXL_CLK, &value, 1); |
647 | /* set the sensor */ | 650 | /* set the sensor */ |
648 | if (gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].mode) { | 651 | if (gspca_dev->cam.cam_mode[(int) gspca_dev->curr_mode].mode) { |
649 | I2c0[0] = 0x06; | 652 | I2c0[0] = 0x06; |
@@ -679,7 +682,7 @@ static void Et_init1(struct gspca_dev *gspca_dev) | |||
679 | /* magnetude and sign bit for DAC */ | 682 | /* magnetude and sign bit for DAC */ |
680 | Et_i2cwrite(dev, PAS106_REG7, I2c4, sizeof I2c4, 1); | 683 | Et_i2cwrite(dev, PAS106_REG7, I2c4, sizeof I2c4, 1); |
681 | /* now set by fifo the whole colors setting */ | 684 | /* now set by fifo the whole colors setting */ |
682 | Et_RegWrite(dev, ET_G_RED, GainRGBG, 6); | 685 | reg_w(dev, ET_G_RED, GainRGBG, 6); |
683 | getcolors(gspca_dev); | 686 | getcolors(gspca_dev); |
684 | setcolors(gspca_dev); | 687 | setcolors(gspca_dev); |
685 | } | 688 | } |
@@ -738,7 +741,7 @@ static int sd_open(struct gspca_dev *gspca_dev) | |||
738 | else | 741 | else |
739 | Et_init2(gspca_dev); | 742 | Et_init2(gspca_dev); |
740 | value = 0x08; | 743 | value = 0x08; |
741 | Et_RegWrite(dev, ET_RESET_ALL, &value, 1); | 744 | reg_w(dev, ET_RESET_ALL, &value, 1); |
742 | err = Et_videoOff(dev); | 745 | err = Et_videoOff(dev); |
743 | PDEBUG(D_STREAM, "Et_Init_VideoOff %d", err); | 746 | PDEBUG(D_STREAM, "Et_Init_VideoOff %d", err); |
744 | return 0; | 747 | return 0; |
@@ -758,7 +761,7 @@ static void sd_start(struct gspca_dev *gspca_dev) | |||
758 | Et_init2(gspca_dev); | 761 | Et_init2(gspca_dev); |
759 | 762 | ||
760 | value = 0x08; | 763 | value = 0x08; |
761 | Et_RegWrite(dev, ET_RESET_ALL, &value, 1); | 764 | reg_w(dev, ET_RESET_ALL, &value, 1); |
762 | err = Et_videoOn(dev); | 765 | err = Et_videoOn(dev); |
763 | PDEBUG(D_STREAM, "Et_VideoOn %d", err); | 766 | PDEBUG(D_STREAM, "Et_VideoOn %d", err); |
764 | } | 767 | } |
@@ -787,7 +790,7 @@ static void setbrightness(struct gspca_dev *gspca_dev) | |||
787 | __u8 brightness = sd->brightness; | 790 | __u8 brightness = sd->brightness; |
788 | 791 | ||
789 | for (i = 0; i < 4; i++) | 792 | for (i = 0; i < 4; i++) |
790 | Et_RegWrite(gspca_dev->dev, (ET_O_RED + i), &brightness, 1); | 793 | reg_w(gspca_dev->dev, (ET_O_RED + i), &brightness, 1); |
791 | } | 794 | } |
792 | 795 | ||
793 | static void getbrightness(struct gspca_dev *gspca_dev) | 796 | static void getbrightness(struct gspca_dev *gspca_dev) |
@@ -798,7 +801,7 @@ static void getbrightness(struct gspca_dev *gspca_dev) | |||
798 | __u8 value = 0; | 801 | __u8 value = 0; |
799 | 802 | ||
800 | for (i = 0; i < 4; i++) { | 803 | for (i = 0; i < 4; i++) { |
801 | Et_RegRead(gspca_dev->dev, (ET_O_RED + i), &value, 1); | 804 | reg_r(gspca_dev->dev, (ET_O_RED + i), &value, 1); |
802 | brightness += value; | 805 | brightness += value; |
803 | } | 806 | } |
804 | sd->brightness = brightness >> 3; | 807 | sd->brightness = brightness >> 3; |
@@ -811,7 +814,7 @@ static void setcontrast(struct gspca_dev *gspca_dev) | |||
811 | __u8 contrast = sd->contrast; | 814 | __u8 contrast = sd->contrast; |
812 | 815 | ||
813 | memset(RGBG, contrast, sizeof RGBG - 2); | 816 | memset(RGBG, contrast, sizeof RGBG - 2); |
814 | Et_RegWrite(gspca_dev->dev, ET_G_RED, RGBG, 6); | 817 | reg_w(gspca_dev->dev, ET_G_RED, RGBG, 6); |
815 | } | 818 | } |
816 | 819 | ||
817 | static void getcontrast(struct gspca_dev *gspca_dev) | 820 | static void getcontrast(struct gspca_dev *gspca_dev) |
@@ -822,7 +825,7 @@ static void getcontrast(struct gspca_dev *gspca_dev) | |||
822 | __u8 value = 0; | 825 | __u8 value = 0; |
823 | 826 | ||
824 | for (i = 0; i < 4; i++) { | 827 | for (i = 0; i < 4; i++) { |
825 | Et_RegRead(gspca_dev->dev, (ET_G_RED + i), &value, 1); | 828 | reg_r(gspca_dev->dev, (ET_G_RED + i), &value, 1); |
826 | contrast += value; | 829 | contrast += value; |
827 | } | 830 | } |
828 | sd->contrast = contrast >> 2; | 831 | sd->contrast = contrast >> 2; |
@@ -870,7 +873,7 @@ static void setautogain(struct gspca_dev *gspca_dev) | |||
870 | __u8 r, g, b; | 873 | __u8 r, g, b; |
871 | 874 | ||
872 | Gbright = Et_getgainG(gspca_dev); | 875 | Gbright = Et_getgainG(gspca_dev); |
873 | Et_RegRead(dev, ET_LUMA_CENTER, GRBG, 4); | 876 | reg_r(dev, ET_LUMA_CENTER, GRBG, 4); |
874 | g = (GRBG[0] + GRBG[3]) >> 1; | 877 | g = (GRBG[0] + GRBG[3]) >> 1; |
875 | r = GRBG[1]; | 878 | r = GRBG[1]; |
876 | b = GRBG[2]; | 879 | b = GRBG[2]; |