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authorMauro Carvalho Chehab <mchehab@redhat.com>2009-12-05 06:27:49 -0500
committerMauro Carvalho Chehab <mchehab@redhat.com>2009-12-15 21:17:52 -0500
commit1bad429e81f9a9ffa01c4158e6d1b1a3e06d9886 (patch)
treea87f098b83549bd393819c9852524cf811bc7f98 /drivers/media/video/em28xx
parent4039ff28a501cf6b9fc2b6a2c2b28476d7fa14cd (diff)
V4L/DVB (13545): em28xx: properly select IR protocol based on the IR table
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/video/em28xx')
-rw-r--r--drivers/media/video/em28xx/em28xx-core.c2
-rw-r--r--drivers/media/video/em28xx/em28xx-input.c17
-rw-r--r--drivers/media/video/em28xx/em28xx.h2
3 files changed, 16 insertions, 5 deletions
diff --git a/drivers/media/video/em28xx/em28xx-core.c b/drivers/media/video/em28xx/em28xx-core.c
index 3f86d36dff2b..4f61e05d30b4 100644
--- a/drivers/media/video/em28xx/em28xx-core.c
+++ b/drivers/media/video/em28xx/em28xx-core.c
@@ -216,7 +216,7 @@ int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val)
216 * sets only some bits (specified by bitmask) of a register, by first reading 216 * sets only some bits (specified by bitmask) of a register, by first reading
217 * the actual value 217 * the actual value
218 */ 218 */
219static int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val, 219int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
220 u8 bitmask) 220 u8 bitmask)
221{ 221{
222 int oldval; 222 int oldval;
diff --git a/drivers/media/video/em28xx/em28xx-input.c b/drivers/media/video/em28xx/em28xx-input.c
index d96ec7c09dca..3f5cf02f3147 100644
--- a/drivers/media/video/em28xx/em28xx-input.c
+++ b/drivers/media/video/em28xx/em28xx-input.c
@@ -337,19 +337,28 @@ int em28xx_ir_init(struct em28xx *dev)
337 goto err_out_free; 337 goto err_out_free;
338 338
339 ir->input = input_dev; 339 ir->input = input_dev;
340 ir_config = EM2874_IR_RC5;
341
342 /* Adjust xclk based o IR table for RC5/NEC tables */
343 if (dev->board.ir_codes->ir_type == IR_TYPE_RC5) {
344 dev->board.xclk |= EM28XX_XCLK_IR_RC5_MODE;
345 ir->full_code = 1;
346 } else if (dev->board.ir_codes->ir_type == IR_TYPE_NEC) {
347 dev->board.xclk &= ~EM28XX_XCLK_IR_RC5_MODE;
348 ir_config = EM2874_IR_NEC;
349 ir->full_code = 1;
350 }
351 em28xx_write_reg_bits(dev, EM28XX_R0F_XCLK, dev->board.xclk,
352 EM28XX_XCLK_IR_RC5_MODE);
340 353
341 /* Setup the proper handler based on the chip */ 354 /* Setup the proper handler based on the chip */
342 switch (dev->chip_id) { 355 switch (dev->chip_id) {
343 case CHIP_ID_EM2860: 356 case CHIP_ID_EM2860:
344 case CHIP_ID_EM2883: 357 case CHIP_ID_EM2883:
345 if (dev->model == EM2883_BOARD_HAUPPAUGE_WINTV_HVR_950)
346 ir->full_code = 1;
347 ir->get_key = default_polling_getkey; 358 ir->get_key = default_polling_getkey;
348 break; 359 break;
349 case CHIP_ID_EM2874: 360 case CHIP_ID_EM2874:
350 ir->get_key = em2874_polling_getkey; 361 ir->get_key = em2874_polling_getkey;
351 /* For now we only support RC5, so enable it */
352 ir_config = EM2874_IR_RC5;
353 em28xx_write_regs(dev, EM2874_R50_IR_CONFIG, &ir_config, 1); 362 em28xx_write_regs(dev, EM2874_R50_IR_CONFIG, &ir_config, 1);
354 break; 363 break;
355 default: 364 default:
diff --git a/drivers/media/video/em28xx/em28xx.h b/drivers/media/video/em28xx/em28xx.h
index 441df644ddbe..48977832316e 100644
--- a/drivers/media/video/em28xx/em28xx.h
+++ b/drivers/media/video/em28xx/em28xx.h
@@ -643,6 +643,8 @@ int em28xx_write_regs_req(struct em28xx *dev, u8 req, u16 reg, char *buf,
643 int len); 643 int len);
644int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len); 644int em28xx_write_regs(struct em28xx *dev, u16 reg, char *buf, int len);
645int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val); 645int em28xx_write_reg(struct em28xx *dev, u16 reg, u8 val);
646int em28xx_write_reg_bits(struct em28xx *dev, u16 reg, u8 val,
647 u8 bitmask);
646 648
647int em28xx_read_ac97(struct em28xx *dev, u8 reg); 649int em28xx_read_ac97(struct em28xx *dev, u8 reg);
648int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val); 650int em28xx_write_ac97(struct em28xx *dev, u8 reg, u16 val);