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authorNickolay V. Shmyrev <nshmyrev@yandex.ru>2005-11-09 00:36:59 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2005-11-09 10:56:13 -0500
commit7b3c6d659fc392cfd80e57840c10ccd4c6ab62c5 (patch)
tree3e495a13040304f00b11f4c98e7b26176a5131d2 /drivers/media/video/cx88
parent0bcc37c328ac66ede45a6672f85795eee0b05b87 (diff)
[PATCH] v4l: 706: reindent cx88 tvaudio c to keep coding style
- Reindent cx88-tvaudio.c to keep coding style. Signed-off-by: Nickolay V. Shmyrev <nshmyrev@yandex.ru> Signed-off-by: Mauro Carvalho Chehab <mchehab@brturbo.com.br> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/media/video/cx88')
-rw-r--r--drivers/media/video/cx88/cx88-tvaudio.c963
1 files changed, 484 insertions, 479 deletions
diff --git a/drivers/media/video/cx88/cx88-tvaudio.c b/drivers/media/video/cx88/cx88-tvaudio.c
index b6431cb78a59..4ca1128bc76c 100644
--- a/drivers/media/video/cx88/cx88-tvaudio.c
+++ b/drivers/media/video/cx88/cx88-tvaudio.c
@@ -57,39 +57,38 @@
57#include "cx88.h" 57#include "cx88.h"
58 58
59static unsigned int audio_debug = 0; 59static unsigned int audio_debug = 0;
60module_param(audio_debug,int,0644); 60module_param(audio_debug, int, 0644);
61MODULE_PARM_DESC(audio_debug,"enable debug messages [audio]"); 61MODULE_PARM_DESC(audio_debug, "enable debug messages [audio]");
62 62
63#define dprintk(fmt, arg...) if (audio_debug) \ 63#define dprintk(fmt, arg...) if (audio_debug) \
64 printk(KERN_DEBUG "%s/0: " fmt, core->name , ## arg) 64 printk(KERN_DEBUG "%s/0: " fmt, core->name , ## arg)
65 65
66/* ----------------------------------------------------------- */ 66/* ----------------------------------------------------------- */
67 67
68static char *aud_ctl_names[64] = 68static char *aud_ctl_names[64] = {
69{ 69 [EN_BTSC_FORCE_MONO] = "BTSC_FORCE_MONO",
70 [ EN_BTSC_FORCE_MONO ] = "BTSC_FORCE_MONO", 70 [EN_BTSC_FORCE_STEREO] = "BTSC_FORCE_STEREO",
71 [ EN_BTSC_FORCE_STEREO ] = "BTSC_FORCE_STEREO", 71 [EN_BTSC_FORCE_SAP] = "BTSC_FORCE_SAP",
72 [ EN_BTSC_FORCE_SAP ] = "BTSC_FORCE_SAP", 72 [EN_BTSC_AUTO_STEREO] = "BTSC_AUTO_STEREO",
73 [ EN_BTSC_AUTO_STEREO ] = "BTSC_AUTO_STEREO", 73 [EN_BTSC_AUTO_SAP] = "BTSC_AUTO_SAP",
74 [ EN_BTSC_AUTO_SAP ] = "BTSC_AUTO_SAP", 74 [EN_A2_FORCE_MONO1] = "A2_FORCE_MONO1",
75 [ EN_A2_FORCE_MONO1 ] = "A2_FORCE_MONO1", 75 [EN_A2_FORCE_MONO2] = "A2_FORCE_MONO2",
76 [ EN_A2_FORCE_MONO2 ] = "A2_FORCE_MONO2", 76 [EN_A2_FORCE_STEREO] = "A2_FORCE_STEREO",
77 [ EN_A2_FORCE_STEREO ] = "A2_FORCE_STEREO", 77 [EN_A2_AUTO_MONO2] = "A2_AUTO_MONO2",
78 [ EN_A2_AUTO_MONO2 ] = "A2_AUTO_MONO2", 78 [EN_A2_AUTO_STEREO] = "A2_AUTO_STEREO",
79 [ EN_A2_AUTO_STEREO ] = "A2_AUTO_STEREO", 79 [EN_EIAJ_FORCE_MONO1] = "EIAJ_FORCE_MONO1",
80 [ EN_EIAJ_FORCE_MONO1 ] = "EIAJ_FORCE_MONO1", 80 [EN_EIAJ_FORCE_MONO2] = "EIAJ_FORCE_MONO2",
81 [ EN_EIAJ_FORCE_MONO2 ] = "EIAJ_FORCE_MONO2", 81 [EN_EIAJ_FORCE_STEREO] = "EIAJ_FORCE_STEREO",
82 [ EN_EIAJ_FORCE_STEREO ] = "EIAJ_FORCE_STEREO", 82 [EN_EIAJ_AUTO_MONO2] = "EIAJ_AUTO_MONO2",
83 [ EN_EIAJ_AUTO_MONO2 ] = "EIAJ_AUTO_MONO2", 83 [EN_EIAJ_AUTO_STEREO] = "EIAJ_AUTO_STEREO",
84 [ EN_EIAJ_AUTO_STEREO ] = "EIAJ_AUTO_STEREO", 84 [EN_NICAM_FORCE_MONO1] = "NICAM_FORCE_MONO1",
85 [ EN_NICAM_FORCE_MONO1 ] = "NICAM_FORCE_MONO1", 85 [EN_NICAM_FORCE_MONO2] = "NICAM_FORCE_MONO2",
86 [ EN_NICAM_FORCE_MONO2 ] = "NICAM_FORCE_MONO2", 86 [EN_NICAM_FORCE_STEREO] = "NICAM_FORCE_STEREO",
87 [ EN_NICAM_FORCE_STEREO ] = "NICAM_FORCE_STEREO", 87 [EN_NICAM_AUTO_MONO2] = "NICAM_AUTO_MONO2",
88 [ EN_NICAM_AUTO_MONO2 ] = "NICAM_AUTO_MONO2", 88 [EN_NICAM_AUTO_STEREO] = "NICAM_AUTO_STEREO",
89 [ EN_NICAM_AUTO_STEREO ] = "NICAM_AUTO_STEREO", 89 [EN_FMRADIO_FORCE_MONO] = "FMRADIO_FORCE_MONO",
90 [ EN_FMRADIO_FORCE_MONO ] = "FMRADIO_FORCE_MONO", 90 [EN_FMRADIO_FORCE_STEREO] = "FMRADIO_FORCE_STEREO",
91 [ EN_FMRADIO_FORCE_STEREO ] = "FMRADIO_FORCE_STEREO", 91 [EN_FMRADIO_AUTO_STEREO] = "FMRADIO_AUTO_STEREO",
92 [ EN_FMRADIO_AUTO_STEREO ] = "FMRADIO_AUTO_STEREO",
93}; 92};
94 93
95struct rlist { 94struct rlist {
@@ -97,8 +96,7 @@ struct rlist {
97 u32 val; 96 u32 val;
98}; 97};
99 98
100static void set_audio_registers(struct cx88_core *core, 99static void set_audio_registers(struct cx88_core *core, const struct rlist *l)
101 const struct rlist *l)
102{ 100{
103 int i; 101 int i;
104 102
@@ -119,17 +117,16 @@ static void set_audio_registers(struct cx88_core *core,
119 } 117 }
120} 118}
121 119
122static void set_audio_start(struct cx88_core *core, 120static void set_audio_start(struct cx88_core *core, u32 mode)
123 u32 mode)
124{ 121{
125 // mute 122 // mute
126 cx_write(AUD_VOL_CTL, (1 << 6)); 123 cx_write(AUD_VOL_CTL, (1 << 6));
127 124
128 // start programming 125 // start programming
129 cx_write(AUD_CTL, 0x0000); 126 cx_write(AUD_CTL, 0x0000);
130 cx_write(AUD_INIT, mode); 127 cx_write(AUD_INIT, mode);
131 cx_write(AUD_INIT_LD, 0x0001); 128 cx_write(AUD_INIT_LD, 0x0001);
132 cx_write(AUD_SOFT_RESET, 0x0001); 129 cx_write(AUD_SOFT_RESET, 0x0001);
133} 130}
134 131
135static void set_audio_finish(struct cx88_core *core, u32 ctl) 132static void set_audio_finish(struct cx88_core *core, u32 ctl)
@@ -148,8 +145,8 @@ static void set_audio_finish(struct cx88_core *core, u32 ctl)
148 cx_write(AUD_I2SCNTL, 0); 145 cx_write(AUD_I2SCNTL, 0);
149 //cx_write(AUD_APB_IN_RATE_ADJ, 0); 146 //cx_write(AUD_APB_IN_RATE_ADJ, 0);
150 } else { 147 } else {
151 ctl |= EN_DAC_ENABLE; 148 ctl |= EN_DAC_ENABLE;
152 cx_write(AUD_CTL, ctl); 149 cx_write(AUD_CTL, ctl);
153 } 150 }
154 151
155 /* finish programming */ 152 /* finish programming */
@@ -162,110 +159,111 @@ static void set_audio_finish(struct cx88_core *core, u32 ctl)
162 159
163/* ----------------------------------------------------------- */ 160/* ----------------------------------------------------------- */
164 161
165static void set_audio_standard_BTSC(struct cx88_core *core, unsigned int sap, u32 mode) 162static void set_audio_standard_BTSC(struct cx88_core *core, unsigned int sap,
163 u32 mode)
166{ 164{
167 static const struct rlist btsc[] = { 165 static const struct rlist btsc[] = {
168 { AUD_AFE_12DB_EN, 0x00000001 }, 166 {AUD_AFE_12DB_EN, 0x00000001},
169 { AUD_OUT1_SEL, 0x00000013 }, 167 {AUD_OUT1_SEL, 0x00000013},
170 { AUD_OUT1_SHIFT, 0x00000000 }, 168 {AUD_OUT1_SHIFT, 0x00000000},
171 { AUD_POLY0_DDS_CONSTANT, 0x0012010c }, 169 {AUD_POLY0_DDS_CONSTANT, 0x0012010c},
172 { AUD_DMD_RA_DDS, 0x00c3e7aa }, 170 {AUD_DMD_RA_DDS, 0x00c3e7aa},
173 { AUD_DBX_IN_GAIN, 0x00004734 }, 171 {AUD_DBX_IN_GAIN, 0x00004734},
174 { AUD_DBX_WBE_GAIN, 0x00004640 }, 172 {AUD_DBX_WBE_GAIN, 0x00004640},
175 { AUD_DBX_SE_GAIN, 0x00008d31 }, 173 {AUD_DBX_SE_GAIN, 0x00008d31},
176 { AUD_DCOC_0_SRC, 0x0000001a }, 174 {AUD_DCOC_0_SRC, 0x0000001a},
177 { AUD_IIR1_4_SEL, 0x00000021 }, 175 {AUD_IIR1_4_SEL, 0x00000021},
178 { AUD_DCOC_PASS_IN, 0x00000003 }, 176 {AUD_DCOC_PASS_IN, 0x00000003},
179 { AUD_DCOC_0_SHIFT_IN0, 0x0000000a }, 177 {AUD_DCOC_0_SHIFT_IN0, 0x0000000a},
180 { AUD_DCOC_0_SHIFT_IN1, 0x00000008 }, 178 {AUD_DCOC_0_SHIFT_IN1, 0x00000008},
181 { AUD_DCOC_1_SHIFT_IN0, 0x0000000a }, 179 {AUD_DCOC_1_SHIFT_IN0, 0x0000000a},
182 { AUD_DCOC_1_SHIFT_IN1, 0x00000008 }, 180 {AUD_DCOC_1_SHIFT_IN1, 0x00000008},
183 { AUD_DN0_FREQ, 0x0000283b }, 181 {AUD_DN0_FREQ, 0x0000283b},
184 { AUD_DN2_SRC_SEL, 0x00000008 }, 182 {AUD_DN2_SRC_SEL, 0x00000008},
185 { AUD_DN2_FREQ, 0x00003000 }, 183 {AUD_DN2_FREQ, 0x00003000},
186 { AUD_DN2_AFC, 0x00000002 }, 184 {AUD_DN2_AFC, 0x00000002},
187 { AUD_DN2_SHFT, 0x00000000 }, 185 {AUD_DN2_SHFT, 0x00000000},
188 { AUD_IIR2_2_SEL, 0x00000020 }, 186 {AUD_IIR2_2_SEL, 0x00000020},
189 { AUD_IIR2_2_SHIFT, 0x00000000 }, 187 {AUD_IIR2_2_SHIFT, 0x00000000},
190 { AUD_IIR2_3_SEL, 0x0000001f }, 188 {AUD_IIR2_3_SEL, 0x0000001f},
191 { AUD_IIR2_3_SHIFT, 0x00000000 }, 189 {AUD_IIR2_3_SHIFT, 0x00000000},
192 { AUD_CRDC1_SRC_SEL, 0x000003ce }, 190 {AUD_CRDC1_SRC_SEL, 0x000003ce},
193 { AUD_CRDC1_SHIFT, 0x00000000 }, 191 {AUD_CRDC1_SHIFT, 0x00000000},
194 { AUD_CORDIC_SHIFT_1, 0x00000007 }, 192 {AUD_CORDIC_SHIFT_1, 0x00000007},
195 { AUD_DCOC_1_SRC, 0x0000001b }, 193 {AUD_DCOC_1_SRC, 0x0000001b},
196 { AUD_DCOC1_SHIFT, 0x00000000 }, 194 {AUD_DCOC1_SHIFT, 0x00000000},
197 { AUD_RDSI_SEL, 0x00000008 }, 195 {AUD_RDSI_SEL, 0x00000008},
198 { AUD_RDSQ_SEL, 0x00000008 }, 196 {AUD_RDSQ_SEL, 0x00000008},
199 { AUD_RDSI_SHIFT, 0x00000000 }, 197 {AUD_RDSI_SHIFT, 0x00000000},
200 { AUD_RDSQ_SHIFT, 0x00000000 }, 198 {AUD_RDSQ_SHIFT, 0x00000000},
201 { AUD_POLYPH80SCALEFAC, 0x00000003 }, 199 {AUD_POLYPH80SCALEFAC, 0x00000003},
202 { /* end of list */ }, 200 { /* end of list */ },
203 }; 201 };
204 static const struct rlist btsc_sap[] = { 202 static const struct rlist btsc_sap[] = {
205 { AUD_AFE_12DB_EN, 0x00000001 }, 203 {AUD_AFE_12DB_EN, 0x00000001},
206 { AUD_DBX_IN_GAIN, 0x00007200 }, 204 {AUD_DBX_IN_GAIN, 0x00007200},
207 { AUD_DBX_WBE_GAIN, 0x00006200 }, 205 {AUD_DBX_WBE_GAIN, 0x00006200},
208 { AUD_DBX_SE_GAIN, 0x00006200 }, 206 {AUD_DBX_SE_GAIN, 0x00006200},
209 { AUD_IIR1_1_SEL, 0x00000000 }, 207 {AUD_IIR1_1_SEL, 0x00000000},
210 { AUD_IIR1_3_SEL, 0x00000001 }, 208 {AUD_IIR1_3_SEL, 0x00000001},
211 { AUD_DN1_SRC_SEL, 0x00000007 }, 209 {AUD_DN1_SRC_SEL, 0x00000007},
212 { AUD_IIR1_4_SHIFT, 0x00000006 }, 210 {AUD_IIR1_4_SHIFT, 0x00000006},
213 { AUD_IIR2_1_SHIFT, 0x00000000 }, 211 {AUD_IIR2_1_SHIFT, 0x00000000},
214 { AUD_IIR2_2_SHIFT, 0x00000000 }, 212 {AUD_IIR2_2_SHIFT, 0x00000000},
215 { AUD_IIR3_0_SHIFT, 0x00000000 }, 213 {AUD_IIR3_0_SHIFT, 0x00000000},
216 { AUD_IIR3_1_SHIFT, 0x00000000 }, 214 {AUD_IIR3_1_SHIFT, 0x00000000},
217 { AUD_IIR3_0_SEL, 0x0000000d }, 215 {AUD_IIR3_0_SEL, 0x0000000d},
218 { AUD_IIR3_1_SEL, 0x0000000e }, 216 {AUD_IIR3_1_SEL, 0x0000000e},
219 { AUD_DEEMPH1_SRC_SEL, 0x00000014 }, 217 {AUD_DEEMPH1_SRC_SEL, 0x00000014},
220 { AUD_DEEMPH1_SHIFT, 0x00000000 }, 218 {AUD_DEEMPH1_SHIFT, 0x00000000},
221 { AUD_DEEMPH1_G0, 0x00004000 }, 219 {AUD_DEEMPH1_G0, 0x00004000},
222 { AUD_DEEMPH1_A0, 0x00000000 }, 220 {AUD_DEEMPH1_A0, 0x00000000},
223 { AUD_DEEMPH1_B0, 0x00000000 }, 221 {AUD_DEEMPH1_B0, 0x00000000},
224 { AUD_DEEMPH1_A1, 0x00000000 }, 222 {AUD_DEEMPH1_A1, 0x00000000},
225 { AUD_DEEMPH1_B1, 0x00000000 }, 223 {AUD_DEEMPH1_B1, 0x00000000},
226 { AUD_OUT0_SEL, 0x0000003f }, 224 {AUD_OUT0_SEL, 0x0000003f},
227 { AUD_OUT1_SEL, 0x0000003f }, 225 {AUD_OUT1_SEL, 0x0000003f},
228 { AUD_DN1_AFC, 0x00000002 }, 226 {AUD_DN1_AFC, 0x00000002},
229 { AUD_DCOC_0_SHIFT_IN0, 0x0000000a }, 227 {AUD_DCOC_0_SHIFT_IN0, 0x0000000a},
230 { AUD_DCOC_0_SHIFT_IN1, 0x00000008 }, 228 {AUD_DCOC_0_SHIFT_IN1, 0x00000008},
231 { AUD_DCOC_1_SHIFT_IN0, 0x0000000a }, 229 {AUD_DCOC_1_SHIFT_IN0, 0x0000000a},
232 { AUD_DCOC_1_SHIFT_IN1, 0x00000008 }, 230 {AUD_DCOC_1_SHIFT_IN1, 0x00000008},
233 { AUD_IIR1_0_SEL, 0x0000001d }, 231 {AUD_IIR1_0_SEL, 0x0000001d},
234 { AUD_IIR1_2_SEL, 0x0000001e }, 232 {AUD_IIR1_2_SEL, 0x0000001e},
235 { AUD_IIR2_1_SEL, 0x00000002 }, 233 {AUD_IIR2_1_SEL, 0x00000002},
236 { AUD_IIR2_2_SEL, 0x00000004 }, 234 {AUD_IIR2_2_SEL, 0x00000004},
237 { AUD_IIR3_2_SEL, 0x0000000f }, 235 {AUD_IIR3_2_SEL, 0x0000000f},
238 { AUD_DCOC2_SHIFT, 0x00000001 }, 236 {AUD_DCOC2_SHIFT, 0x00000001},
239 { AUD_IIR3_2_SHIFT, 0x00000001 }, 237 {AUD_IIR3_2_SHIFT, 0x00000001},
240 { AUD_DEEMPH0_SRC_SEL, 0x00000014 }, 238 {AUD_DEEMPH0_SRC_SEL, 0x00000014},
241 { AUD_CORDIC_SHIFT_1, 0x00000006 }, 239 {AUD_CORDIC_SHIFT_1, 0x00000006},
242 { AUD_POLY0_DDS_CONSTANT, 0x000e4db2 }, 240 {AUD_POLY0_DDS_CONSTANT, 0x000e4db2},
243 { AUD_DMD_RA_DDS, 0x00f696e6 }, 241 {AUD_DMD_RA_DDS, 0x00f696e6},
244 { AUD_IIR2_3_SEL, 0x00000025 }, 242 {AUD_IIR2_3_SEL, 0x00000025},
245 { AUD_IIR1_4_SEL, 0x00000021 }, 243 {AUD_IIR1_4_SEL, 0x00000021},
246 { AUD_DN1_FREQ, 0x0000c965 }, 244 {AUD_DN1_FREQ, 0x0000c965},
247 { AUD_DCOC_PASS_IN, 0x00000003 }, 245 {AUD_DCOC_PASS_IN, 0x00000003},
248 { AUD_DCOC_0_SRC, 0x0000001a }, 246 {AUD_DCOC_0_SRC, 0x0000001a},
249 { AUD_DCOC_1_SRC, 0x0000001b }, 247 {AUD_DCOC_1_SRC, 0x0000001b},
250 { AUD_DCOC1_SHIFT, 0x00000000 }, 248 {AUD_DCOC1_SHIFT, 0x00000000},
251 { AUD_RDSI_SEL, 0x00000009 }, 249 {AUD_RDSI_SEL, 0x00000009},
252 { AUD_RDSQ_SEL, 0x00000009 }, 250 {AUD_RDSQ_SEL, 0x00000009},
253 { AUD_RDSI_SHIFT, 0x00000000 }, 251 {AUD_RDSI_SHIFT, 0x00000000},
254 { AUD_RDSQ_SHIFT, 0x00000000 }, 252 {AUD_RDSQ_SHIFT, 0x00000000},
255 { AUD_POLYPH80SCALEFAC, 0x00000003 }, 253 {AUD_POLYPH80SCALEFAC, 0x00000003},
256 { /* end of list */ }, 254 { /* end of list */ },
257 }; 255 };
258 256
259 mode |= EN_FMRADIO_EN_RDS; 257 mode |= EN_FMRADIO_EN_RDS;
260 258
261 if (sap) { 259 if (sap) {
262 dprintk("%s SAP (status: unknown)\n",__FUNCTION__); 260 dprintk("%s SAP (status: unknown)\n", __FUNCTION__);
263 set_audio_start(core, SEL_SAP); 261 set_audio_start(core, SEL_SAP);
264 set_audio_registers(core, btsc_sap); 262 set_audio_registers(core, btsc_sap);
265 set_audio_finish(core, mode); 263 set_audio_finish(core, mode);
266 } else { 264 } else {
267 dprintk("%s (status: known-good)\n",__FUNCTION__); 265 dprintk("%s (status: known-good)\n", __FUNCTION__);
268 set_audio_start(core, SEL_BTSC); 266 set_audio_start(core, SEL_BTSC);
269 set_audio_registers(core, btsc); 267 set_audio_registers(core, btsc);
270 set_audio_finish(core, mode); 268 set_audio_finish(core, mode);
271 } 269 }
@@ -274,87 +272,87 @@ static void set_audio_standard_BTSC(struct cx88_core *core, unsigned int sap, u3
274static void set_audio_standard_NICAM(struct cx88_core *core, u32 mode) 272static void set_audio_standard_NICAM(struct cx88_core *core, u32 mode)
275{ 273{
276 static const struct rlist nicam_l[] = { 274 static const struct rlist nicam_l[] = {
277 { AUD_AFE_12DB_EN, 0x00000001}, 275 {AUD_AFE_12DB_EN, 0x00000001},
278 { AUD_RATE_ADJ1, 0x00000060 }, 276 {AUD_RATE_ADJ1, 0x00000060},
279 { AUD_RATE_ADJ2, 0x000000F9 }, 277 {AUD_RATE_ADJ2, 0x000000F9},
280 { AUD_RATE_ADJ3, 0x000001CC }, 278 {AUD_RATE_ADJ3, 0x000001CC},
281 { AUD_RATE_ADJ4, 0x000002B3 }, 279 {AUD_RATE_ADJ4, 0x000002B3},
282 { AUD_RATE_ADJ5, 0x00000726 }, 280 {AUD_RATE_ADJ5, 0x00000726},
283 { AUD_DEEMPHDENOM1_R, 0x0000F3D0 }, 281 {AUD_DEEMPHDENOM1_R, 0x0000F3D0},
284 { AUD_DEEMPHDENOM2_R, 0x00000000 }, 282 {AUD_DEEMPHDENOM2_R, 0x00000000},
285 { AUD_ERRLOGPERIOD_R, 0x00000064 }, 283 {AUD_ERRLOGPERIOD_R, 0x00000064},
286 { AUD_ERRINTRPTTHSHLD1_R, 0x00000FFF }, 284 {AUD_ERRINTRPTTHSHLD1_R, 0x00000FFF},
287 { AUD_ERRINTRPTTHSHLD2_R, 0x0000001F }, 285 {AUD_ERRINTRPTTHSHLD2_R, 0x0000001F},
288 { AUD_ERRINTRPTTHSHLD3_R, 0x0000000F }, 286 {AUD_ERRINTRPTTHSHLD3_R, 0x0000000F},
289 { AUD_POLYPH80SCALEFAC, 0x00000003 }, 287 {AUD_POLYPH80SCALEFAC, 0x00000003},
290 { AUD_DMD_RA_DDS, 0x00C00000 }, 288 {AUD_DMD_RA_DDS, 0x00C00000},
291 { AUD_PLL_INT, 0x0000001E }, 289 {AUD_PLL_INT, 0x0000001E},
292 { AUD_PLL_DDS, 0x00000000 }, 290 {AUD_PLL_DDS, 0x00000000},
293 { AUD_PLL_FRAC, 0x0000E542 }, 291 {AUD_PLL_FRAC, 0x0000E542},
294 { AUD_START_TIMER, 0x00000000 }, 292 {AUD_START_TIMER, 0x00000000},
295 { AUD_DEEMPHNUMER1_R, 0x000353DE }, 293 {AUD_DEEMPHNUMER1_R, 0x000353DE},
296 { AUD_DEEMPHNUMER2_R, 0x000001B1 }, 294 {AUD_DEEMPHNUMER2_R, 0x000001B1},
297 { AUD_PDF_DDS_CNST_BYTE2, 0x06 }, 295 {AUD_PDF_DDS_CNST_BYTE2, 0x06},
298 { AUD_PDF_DDS_CNST_BYTE1, 0x82 }, 296 {AUD_PDF_DDS_CNST_BYTE1, 0x82},
299 { AUD_PDF_DDS_CNST_BYTE0, 0x12 }, 297 {AUD_PDF_DDS_CNST_BYTE0, 0x12},
300 { AUD_QAM_MODE, 0x05 }, 298 {AUD_QAM_MODE, 0x05},
301 { AUD_PHACC_FREQ_8MSB, 0x34 }, 299 {AUD_PHACC_FREQ_8MSB, 0x34},
302 { AUD_PHACC_FREQ_8LSB, 0x4C }, 300 {AUD_PHACC_FREQ_8LSB, 0x4C},
303 { AUD_DEEMPHGAIN_R, 0x00006680 }, 301 {AUD_DEEMPHGAIN_R, 0x00006680},
304 { AUD_RATE_THRES_DMD, 0x000000C0 }, 302 {AUD_RATE_THRES_DMD, 0x000000C0},
305 { /* end of list */ }, 303 { /* end of list */ },
306 } ; 304 };
307 305
308 static const struct rlist nicam_bgdki_common[] = { 306 static const struct rlist nicam_bgdki_common[] = {
309 { AUD_AFE_12DB_EN, 0x00000001}, 307 {AUD_AFE_12DB_EN, 0x00000001},
310 { AUD_RATE_ADJ1, 0x00000010 }, 308 {AUD_RATE_ADJ1, 0x00000010},
311 { AUD_RATE_ADJ2, 0x00000040 }, 309 {AUD_RATE_ADJ2, 0x00000040},
312 { AUD_RATE_ADJ3, 0x00000100 }, 310 {AUD_RATE_ADJ3, 0x00000100},
313 { AUD_RATE_ADJ4, 0x00000400 }, 311 {AUD_RATE_ADJ4, 0x00000400},
314 { AUD_RATE_ADJ5, 0x00001000 }, 312 {AUD_RATE_ADJ5, 0x00001000},
315 //{ AUD_DMD_RA_DDS, 0x00c0d5ce }, 313 //{ AUD_DMD_RA_DDS, 0x00c0d5ce },
316 { AUD_ERRLOGPERIOD_R, 0x00000fff}, 314 {AUD_ERRLOGPERIOD_R, 0x00000fff},
317 { AUD_ERRINTRPTTHSHLD1_R, 0x000003ff}, 315 {AUD_ERRINTRPTTHSHLD1_R, 0x000003ff},
318 { AUD_ERRINTRPTTHSHLD2_R, 0x000000ff}, 316 {AUD_ERRINTRPTTHSHLD2_R, 0x000000ff},
319 { AUD_ERRINTRPTTHSHLD3_R, 0x0000003f}, 317 {AUD_ERRINTRPTTHSHLD3_R, 0x0000003f},
320 { AUD_POLYPH80SCALEFAC, 0x00000003}, 318 {AUD_POLYPH80SCALEFAC, 0x00000003},
321 { AUD_DEEMPHGAIN_R, 0x000023c2}, 319 {AUD_DEEMPHGAIN_R, 0x000023c2},
322 { AUD_DEEMPHNUMER1_R, 0x0002a7bc}, 320 {AUD_DEEMPHNUMER1_R, 0x0002a7bc},
323 { AUD_DEEMPHNUMER2_R, 0x0003023e}, 321 {AUD_DEEMPHNUMER2_R, 0x0003023e},
324 { AUD_DEEMPHDENOM1_R, 0x0000f3d0}, 322 {AUD_DEEMPHDENOM1_R, 0x0000f3d0},
325 { AUD_DEEMPHDENOM2_R, 0x00000000}, 323 {AUD_DEEMPHDENOM2_R, 0x00000000},
326 { AUD_PDF_DDS_CNST_BYTE1, 0x82 }, 324 {AUD_PDF_DDS_CNST_BYTE1, 0x82},
327 { AUD_PDF_DDS_CNST_BYTE0, 0x16 }, 325 {AUD_PDF_DDS_CNST_BYTE0, 0x16},
328 { AUD_QAM_MODE, 0x05 }, 326 {AUD_QAM_MODE, 0x05},
329 { /* end of list */ }, 327 { /* end of list */ },
330 }; 328 };
331 329
332 static const struct rlist nicam_i[] = { 330 static const struct rlist nicam_i[] = {
333 { AUD_PDF_DDS_CNST_BYTE0, 0x12 }, 331 {AUD_PDF_DDS_CNST_BYTE0, 0x12},
334 { AUD_PHACC_FREQ_8MSB, 0x3a }, 332 {AUD_PHACC_FREQ_8MSB, 0x3a},
335 { AUD_PHACC_FREQ_8LSB, 0x93 }, 333 {AUD_PHACC_FREQ_8LSB, 0x93},
336 { /* end of list */ }, 334 { /* end of list */ },
337 }; 335 };
338 336
339 static const struct rlist nicam_default[] = { 337 static const struct rlist nicam_default[] = {
340 { AUD_PDF_DDS_CNST_BYTE0, 0x16 }, 338 {AUD_PDF_DDS_CNST_BYTE0, 0x16},
341 { AUD_PHACC_FREQ_8MSB, 0x34 }, 339 {AUD_PHACC_FREQ_8MSB, 0x34},
342 { AUD_PHACC_FREQ_8LSB, 0x4c }, 340 {AUD_PHACC_FREQ_8LSB, 0x4c},
343 { /* end of list */ }, 341 { /* end of list */ },
344 }; 342 };
345 343
346 switch (core->tvaudio) { 344 switch (core->tvaudio) {
347 case WW_L: 345 case WW_L:
348 dprintk("%s SECAM-L NICAM (status: devel)\n",__FUNCTION__); 346 dprintk("%s SECAM-L NICAM (status: devel)\n", __FUNCTION__);
349 set_audio_registers(core, nicam_l); 347 set_audio_registers(core, nicam_l);
350 break; 348 break;
351 case WW_I: 349 case WW_I:
352 dprintk("%s PAL-I NICAM (status: devel)\n",__FUNCTION__); 350 dprintk("%s PAL-I NICAM (status: devel)\n", __FUNCTION__);
353 set_audio_registers(core, nicam_bgdki_common); 351 set_audio_registers(core, nicam_bgdki_common);
354 set_audio_registers(core, nicam_i); 352 set_audio_registers(core, nicam_i);
355 break; 353 break;
356 default: 354 default:
357 dprintk("%s PAL-BGDK NICAM (status: unknown)\n",__FUNCTION__); 355 dprintk("%s PAL-BGDK NICAM (status: unknown)\n", __FUNCTION__);
358 set_audio_registers(core, nicam_bgdki_common); 356 set_audio_registers(core, nicam_bgdki_common);
359 set_audio_registers(core, nicam_default); 357 set_audio_registers(core, nicam_default);
360 break; 358 break;
@@ -367,255 +365,255 @@ static void set_audio_standard_NICAM(struct cx88_core *core, u32 mode)
367static void set_audio_standard_A2(struct cx88_core *core, u32 mode) 365static void set_audio_standard_A2(struct cx88_core *core, u32 mode)
368{ 366{
369 static const struct rlist a2_bgdk_common[] = { 367 static const struct rlist a2_bgdk_common[] = {
370 {AUD_ERRLOGPERIOD_R, 0x00000064}, 368 {AUD_ERRLOGPERIOD_R, 0x00000064},
371 {AUD_ERRINTRPTTHSHLD1_R, 0x00000fff}, 369 {AUD_ERRINTRPTTHSHLD1_R, 0x00000fff},
372 {AUD_ERRINTRPTTHSHLD2_R, 0x0000001f}, 370 {AUD_ERRINTRPTTHSHLD2_R, 0x0000001f},
373 {AUD_ERRINTRPTTHSHLD3_R, 0x0000000f}, 371 {AUD_ERRINTRPTTHSHLD3_R, 0x0000000f},
374 {AUD_PDF_DDS_CNST_BYTE2, 0x06}, 372 {AUD_PDF_DDS_CNST_BYTE2, 0x06},
375 {AUD_PDF_DDS_CNST_BYTE1, 0x82}, 373 {AUD_PDF_DDS_CNST_BYTE1, 0x82},
376 {AUD_PDF_DDS_CNST_BYTE0, 0x12}, 374 {AUD_PDF_DDS_CNST_BYTE0, 0x12},
377 {AUD_QAM_MODE, 0x05}, 375 {AUD_QAM_MODE, 0x05},
378 {AUD_PHACC_FREQ_8MSB, 0x34}, 376 {AUD_PHACC_FREQ_8MSB, 0x34},
379 {AUD_PHACC_FREQ_8LSB, 0x4c}, 377 {AUD_PHACC_FREQ_8LSB, 0x4c},
380 {AUD_RATE_ADJ1, 0x00000100}, 378 {AUD_RATE_ADJ1, 0x00000100},
381 {AUD_RATE_ADJ2, 0x00000200}, 379 {AUD_RATE_ADJ2, 0x00000200},
382 {AUD_RATE_ADJ3, 0x00000300}, 380 {AUD_RATE_ADJ3, 0x00000300},
383 {AUD_RATE_ADJ4, 0x00000400}, 381 {AUD_RATE_ADJ4, 0x00000400},
384 {AUD_RATE_ADJ5, 0x00000500}, 382 {AUD_RATE_ADJ5, 0x00000500},
385 {AUD_THR_FR, 0x00000000}, 383 {AUD_THR_FR, 0x00000000},
386 {AAGC_HYST, 0x0000001a}, 384 {AAGC_HYST, 0x0000001a},
387 {AUD_PILOT_BQD_1_K0, 0x0000755b}, 385 {AUD_PILOT_BQD_1_K0, 0x0000755b},
388 {AUD_PILOT_BQD_1_K1, 0x00551340}, 386 {AUD_PILOT_BQD_1_K1, 0x00551340},
389 {AUD_PILOT_BQD_1_K2, 0x006d30be}, 387 {AUD_PILOT_BQD_1_K2, 0x006d30be},
390 {AUD_PILOT_BQD_1_K3, 0xffd394af}, 388 {AUD_PILOT_BQD_1_K3, 0xffd394af},
391 {AUD_PILOT_BQD_1_K4, 0x00400000}, 389 {AUD_PILOT_BQD_1_K4, 0x00400000},
392 {AUD_PILOT_BQD_2_K0, 0x00040000}, 390 {AUD_PILOT_BQD_2_K0, 0x00040000},
393 {AUD_PILOT_BQD_2_K1, 0x002a4841}, 391 {AUD_PILOT_BQD_2_K1, 0x002a4841},
394 {AUD_PILOT_BQD_2_K2, 0x00400000}, 392 {AUD_PILOT_BQD_2_K2, 0x00400000},
395 {AUD_PILOT_BQD_2_K3, 0x00000000}, 393 {AUD_PILOT_BQD_2_K3, 0x00000000},
396 {AUD_PILOT_BQD_2_K4, 0x00000000}, 394 {AUD_PILOT_BQD_2_K4, 0x00000000},
397 {AUD_MODE_CHG_TIMER, 0x00000040}, 395 {AUD_MODE_CHG_TIMER, 0x00000040},
398 {AUD_AFE_12DB_EN, 0x00000001}, 396 {AUD_AFE_12DB_EN, 0x00000001},
399 {AUD_CORDIC_SHIFT_0, 0x00000007}, 397 {AUD_CORDIC_SHIFT_0, 0x00000007},
400 {AUD_CORDIC_SHIFT_1, 0x00000007}, 398 {AUD_CORDIC_SHIFT_1, 0x00000007},
401 {AUD_DEEMPH0_G0, 0x00000380}, 399 {AUD_DEEMPH0_G0, 0x00000380},
402 {AUD_DEEMPH1_G0, 0x00000380}, 400 {AUD_DEEMPH1_G0, 0x00000380},
403 {AUD_DCOC_0_SRC, 0x0000001a}, 401 {AUD_DCOC_0_SRC, 0x0000001a},
404 {AUD_DCOC0_SHIFT, 0x00000000}, 402 {AUD_DCOC0_SHIFT, 0x00000000},
405 {AUD_DCOC_0_SHIFT_IN0, 0x0000000a}, 403 {AUD_DCOC_0_SHIFT_IN0, 0x0000000a},
406 {AUD_DCOC_0_SHIFT_IN1, 0x00000008}, 404 {AUD_DCOC_0_SHIFT_IN1, 0x00000008},
407 {AUD_DCOC_PASS_IN, 0x00000003}, 405 {AUD_DCOC_PASS_IN, 0x00000003},
408 {AUD_IIR3_0_SEL, 0x00000021}, 406 {AUD_IIR3_0_SEL, 0x00000021},
409 {AUD_DN2_AFC, 0x00000002}, 407 {AUD_DN2_AFC, 0x00000002},
410 {AUD_DCOC_1_SRC, 0x0000001b}, 408 {AUD_DCOC_1_SRC, 0x0000001b},
411 {AUD_DCOC1_SHIFT, 0x00000000}, 409 {AUD_DCOC1_SHIFT, 0x00000000},
412 {AUD_DCOC_1_SHIFT_IN0, 0x0000000a}, 410 {AUD_DCOC_1_SHIFT_IN0, 0x0000000a},
413 {AUD_DCOC_1_SHIFT_IN1, 0x00000008}, 411 {AUD_DCOC_1_SHIFT_IN1, 0x00000008},
414 {AUD_IIR3_1_SEL, 0x00000023}, 412 {AUD_IIR3_1_SEL, 0x00000023},
415 {AUD_RDSI_SEL, 0x00000017}, 413 {AUD_RDSI_SEL, 0x00000017},
416 {AUD_RDSI_SHIFT, 0x00000000}, 414 {AUD_RDSI_SHIFT, 0x00000000},
417 {AUD_RDSQ_SEL, 0x00000017}, 415 {AUD_RDSQ_SEL, 0x00000017},
418 {AUD_RDSQ_SHIFT, 0x00000000}, 416 {AUD_RDSQ_SHIFT, 0x00000000},
419 {AUD_PLL_INT, 0x0000001e}, 417 {AUD_PLL_INT, 0x0000001e},
420 {AUD_PLL_DDS, 0x00000000}, 418 {AUD_PLL_DDS, 0x00000000},
421 {AUD_PLL_FRAC, 0x0000e542}, 419 {AUD_PLL_FRAC, 0x0000e542},
422 {AUD_POLYPH80SCALEFAC, 0x00000001}, 420 {AUD_POLYPH80SCALEFAC, 0x00000001},
423 {AUD_START_TIMER, 0x00000000}, 421 {AUD_START_TIMER, 0x00000000},
424 { /* end of list */ }, 422 { /* end of list */ },
425 }; 423 };
426 424
427 static const struct rlist a2_bg[] = { 425 static const struct rlist a2_bg[] = {
428 {AUD_DMD_RA_DDS, 0x002a4f2f}, 426 {AUD_DMD_RA_DDS, 0x002a4f2f},
429 {AUD_C1_UP_THR, 0x00007000}, 427 {AUD_C1_UP_THR, 0x00007000},
430 {AUD_C1_LO_THR, 0x00005400}, 428 {AUD_C1_LO_THR, 0x00005400},
431 {AUD_C2_UP_THR, 0x00005400}, 429 {AUD_C2_UP_THR, 0x00005400},
432 {AUD_C2_LO_THR, 0x00003000}, 430 {AUD_C2_LO_THR, 0x00003000},
433 { /* end of list */ }, 431 { /* end of list */ },
434 }; 432 };
435 433
436 static const struct rlist a2_dk[] = { 434 static const struct rlist a2_dk[] = {
437 {AUD_DMD_RA_DDS, 0x002a4f2f}, 435 {AUD_DMD_RA_DDS, 0x002a4f2f},
438 {AUD_C1_UP_THR, 0x00007000}, 436 {AUD_C1_UP_THR, 0x00007000},
439 {AUD_C1_LO_THR, 0x00005400}, 437 {AUD_C1_LO_THR, 0x00005400},
440 {AUD_C2_UP_THR, 0x00005400}, 438 {AUD_C2_UP_THR, 0x00005400},
441 {AUD_C2_LO_THR, 0x00003000}, 439 {AUD_C2_LO_THR, 0x00003000},
442 {AUD_DN0_FREQ, 0x00003a1c}, 440 {AUD_DN0_FREQ, 0x00003a1c},
443 {AUD_DN2_FREQ, 0x0000d2e0}, 441 {AUD_DN2_FREQ, 0x0000d2e0},
444 { /* end of list */ }, 442 { /* end of list */ },
445 }; 443 };
446 444
447 static const struct rlist a1_i[] = { 445 static const struct rlist a1_i[] = {
448 {AUD_ERRLOGPERIOD_R, 0x00000064}, 446 {AUD_ERRLOGPERIOD_R, 0x00000064},
449 {AUD_ERRINTRPTTHSHLD1_R, 0x00000fff}, 447 {AUD_ERRINTRPTTHSHLD1_R, 0x00000fff},
450 {AUD_ERRINTRPTTHSHLD2_R, 0x0000001f}, 448 {AUD_ERRINTRPTTHSHLD2_R, 0x0000001f},
451 {AUD_ERRINTRPTTHSHLD3_R, 0x0000000f}, 449 {AUD_ERRINTRPTTHSHLD3_R, 0x0000000f},
452 {AUD_PDF_DDS_CNST_BYTE2, 0x06}, 450 {AUD_PDF_DDS_CNST_BYTE2, 0x06},
453 {AUD_PDF_DDS_CNST_BYTE1, 0x82}, 451 {AUD_PDF_DDS_CNST_BYTE1, 0x82},
454 {AUD_PDF_DDS_CNST_BYTE0, 0x12}, 452 {AUD_PDF_DDS_CNST_BYTE0, 0x12},
455 {AUD_QAM_MODE, 0x05}, 453 {AUD_QAM_MODE, 0x05},
456 {AUD_PHACC_FREQ_8MSB, 0x3a}, 454 {AUD_PHACC_FREQ_8MSB, 0x3a},
457 {AUD_PHACC_FREQ_8LSB, 0x93}, 455 {AUD_PHACC_FREQ_8LSB, 0x93},
458 {AUD_DMD_RA_DDS, 0x002a4f2f}, 456 {AUD_DMD_RA_DDS, 0x002a4f2f},
459 {AUD_PLL_INT, 0x0000001e}, 457 {AUD_PLL_INT, 0x0000001e},
460 {AUD_PLL_DDS, 0x00000004}, 458 {AUD_PLL_DDS, 0x00000004},
461 {AUD_PLL_FRAC, 0x0000e542}, 459 {AUD_PLL_FRAC, 0x0000e542},
462 {AUD_RATE_ADJ1, 0x00000100}, 460 {AUD_RATE_ADJ1, 0x00000100},
463 {AUD_RATE_ADJ2, 0x00000200}, 461 {AUD_RATE_ADJ2, 0x00000200},
464 {AUD_RATE_ADJ3, 0x00000300}, 462 {AUD_RATE_ADJ3, 0x00000300},
465 {AUD_RATE_ADJ4, 0x00000400}, 463 {AUD_RATE_ADJ4, 0x00000400},
466 {AUD_RATE_ADJ5, 0x00000500}, 464 {AUD_RATE_ADJ5, 0x00000500},
467 {AUD_THR_FR, 0x00000000}, 465 {AUD_THR_FR, 0x00000000},
468 {AUD_PILOT_BQD_1_K0, 0x0000755b}, 466 {AUD_PILOT_BQD_1_K0, 0x0000755b},
469 {AUD_PILOT_BQD_1_K1, 0x00551340}, 467 {AUD_PILOT_BQD_1_K1, 0x00551340},
470 {AUD_PILOT_BQD_1_K2, 0x006d30be}, 468 {AUD_PILOT_BQD_1_K2, 0x006d30be},
471 {AUD_PILOT_BQD_1_K3, 0xffd394af}, 469 {AUD_PILOT_BQD_1_K3, 0xffd394af},
472 {AUD_PILOT_BQD_1_K4, 0x00400000}, 470 {AUD_PILOT_BQD_1_K4, 0x00400000},
473 {AUD_PILOT_BQD_2_K0, 0x00040000}, 471 {AUD_PILOT_BQD_2_K0, 0x00040000},
474 {AUD_PILOT_BQD_2_K1, 0x002a4841}, 472 {AUD_PILOT_BQD_2_K1, 0x002a4841},
475 {AUD_PILOT_BQD_2_K2, 0x00400000}, 473 {AUD_PILOT_BQD_2_K2, 0x00400000},
476 {AUD_PILOT_BQD_2_K3, 0x00000000}, 474 {AUD_PILOT_BQD_2_K3, 0x00000000},
477 {AUD_PILOT_BQD_2_K4, 0x00000000}, 475 {AUD_PILOT_BQD_2_K4, 0x00000000},
478 {AUD_MODE_CHG_TIMER, 0x00000060}, 476 {AUD_MODE_CHG_TIMER, 0x00000060},
479 {AUD_AFE_12DB_EN, 0x00000001}, 477 {AUD_AFE_12DB_EN, 0x00000001},
480 {AAGC_HYST, 0x0000000a}, 478 {AAGC_HYST, 0x0000000a},
481 {AUD_CORDIC_SHIFT_0, 0x00000007}, 479 {AUD_CORDIC_SHIFT_0, 0x00000007},
482 {AUD_CORDIC_SHIFT_1, 0x00000007}, 480 {AUD_CORDIC_SHIFT_1, 0x00000007},
483 {AUD_C1_UP_THR, 0x00007000}, 481 {AUD_C1_UP_THR, 0x00007000},
484 {AUD_C1_LO_THR, 0x00005400}, 482 {AUD_C1_LO_THR, 0x00005400},
485 {AUD_C2_UP_THR, 0x00005400}, 483 {AUD_C2_UP_THR, 0x00005400},
486 {AUD_C2_LO_THR, 0x00003000}, 484 {AUD_C2_LO_THR, 0x00003000},
487 {AUD_DCOC_0_SRC, 0x0000001a}, 485 {AUD_DCOC_0_SRC, 0x0000001a},
488 {AUD_DCOC0_SHIFT, 0x00000000}, 486 {AUD_DCOC0_SHIFT, 0x00000000},
489 {AUD_DCOC_0_SHIFT_IN0, 0x0000000a}, 487 {AUD_DCOC_0_SHIFT_IN0, 0x0000000a},
490 {AUD_DCOC_0_SHIFT_IN1, 0x00000008}, 488 {AUD_DCOC_0_SHIFT_IN1, 0x00000008},
491 {AUD_DCOC_PASS_IN, 0x00000003}, 489 {AUD_DCOC_PASS_IN, 0x00000003},
492 {AUD_IIR3_0_SEL, 0x00000021}, 490 {AUD_IIR3_0_SEL, 0x00000021},
493 {AUD_DN2_AFC, 0x00000002}, 491 {AUD_DN2_AFC, 0x00000002},
494 {AUD_DCOC_1_SRC, 0x0000001b}, 492 {AUD_DCOC_1_SRC, 0x0000001b},
495 {AUD_DCOC1_SHIFT, 0x00000000}, 493 {AUD_DCOC1_SHIFT, 0x00000000},
496 {AUD_DCOC_1_SHIFT_IN0, 0x0000000a}, 494 {AUD_DCOC_1_SHIFT_IN0, 0x0000000a},
497 {AUD_DCOC_1_SHIFT_IN1, 0x00000008}, 495 {AUD_DCOC_1_SHIFT_IN1, 0x00000008},
498 {AUD_IIR3_1_SEL, 0x00000023}, 496 {AUD_IIR3_1_SEL, 0x00000023},
499 {AUD_DN0_FREQ, 0x000035a3}, 497 {AUD_DN0_FREQ, 0x000035a3},
500 {AUD_DN2_FREQ, 0x000029c7}, 498 {AUD_DN2_FREQ, 0x000029c7},
501 {AUD_CRDC0_SRC_SEL, 0x00000511}, 499 {AUD_CRDC0_SRC_SEL, 0x00000511},
502 {AUD_IIR1_0_SEL, 0x00000001}, 500 {AUD_IIR1_0_SEL, 0x00000001},
503 {AUD_IIR1_1_SEL, 0x00000000}, 501 {AUD_IIR1_1_SEL, 0x00000000},
504 {AUD_IIR3_2_SEL, 0x00000003}, 502 {AUD_IIR3_2_SEL, 0x00000003},
505 {AUD_IIR3_2_SHIFT, 0x00000000}, 503 {AUD_IIR3_2_SHIFT, 0x00000000},
506 {AUD_IIR3_0_SEL, 0x00000002}, 504 {AUD_IIR3_0_SEL, 0x00000002},
507 {AUD_IIR2_0_SEL, 0x00000021}, 505 {AUD_IIR2_0_SEL, 0x00000021},
508 {AUD_IIR2_0_SHIFT, 0x00000002}, 506 {AUD_IIR2_0_SHIFT, 0x00000002},
509 {AUD_DEEMPH0_SRC_SEL, 0x0000000b}, 507 {AUD_DEEMPH0_SRC_SEL, 0x0000000b},
510 {AUD_DEEMPH1_SRC_SEL, 0x0000000b}, 508 {AUD_DEEMPH1_SRC_SEL, 0x0000000b},
511 {AUD_POLYPH80SCALEFAC, 0x00000001}, 509 {AUD_POLYPH80SCALEFAC, 0x00000001},
512 {AUD_START_TIMER, 0x00000000}, 510 {AUD_START_TIMER, 0x00000000},
513 { /* end of list */ }, 511 { /* end of list */ },
514 }; 512 };
515 513
516 static const struct rlist am_l[] = { 514 static const struct rlist am_l[] = {
517 {AUD_ERRLOGPERIOD_R, 0x00000064}, 515 {AUD_ERRLOGPERIOD_R, 0x00000064},
518 {AUD_ERRINTRPTTHSHLD1_R, 0x00000FFF}, 516 {AUD_ERRINTRPTTHSHLD1_R, 0x00000FFF},
519 {AUD_ERRINTRPTTHSHLD2_R, 0x0000001F}, 517 {AUD_ERRINTRPTTHSHLD2_R, 0x0000001F},
520 {AUD_ERRINTRPTTHSHLD3_R, 0x0000000F}, 518 {AUD_ERRINTRPTTHSHLD3_R, 0x0000000F},
521 {AUD_PDF_DDS_CNST_BYTE2, 0x48}, 519 {AUD_PDF_DDS_CNST_BYTE2, 0x48},
522 {AUD_PDF_DDS_CNST_BYTE1, 0x3D}, 520 {AUD_PDF_DDS_CNST_BYTE1, 0x3D},
523 {AUD_QAM_MODE, 0x00}, 521 {AUD_QAM_MODE, 0x00},
524 {AUD_PDF_DDS_CNST_BYTE0, 0xf5}, 522 {AUD_PDF_DDS_CNST_BYTE0, 0xf5},
525 {AUD_PHACC_FREQ_8MSB, 0x3a}, 523 {AUD_PHACC_FREQ_8MSB, 0x3a},
526 {AUD_PHACC_FREQ_8LSB, 0x4a}, 524 {AUD_PHACC_FREQ_8LSB, 0x4a},
527 {AUD_DEEMPHGAIN_R, 0x00006680}, 525 {AUD_DEEMPHGAIN_R, 0x00006680},
528 {AUD_DEEMPHNUMER1_R, 0x000353DE}, 526 {AUD_DEEMPHNUMER1_R, 0x000353DE},
529 {AUD_DEEMPHNUMER2_R, 0x000001B1}, 527 {AUD_DEEMPHNUMER2_R, 0x000001B1},
530 {AUD_DEEMPHDENOM1_R, 0x0000F3D0}, 528 {AUD_DEEMPHDENOM1_R, 0x0000F3D0},
531 {AUD_DEEMPHDENOM2_R, 0x00000000}, 529 {AUD_DEEMPHDENOM2_R, 0x00000000},
532 {AUD_FM_MODE_ENABLE, 0x00000007}, 530 {AUD_FM_MODE_ENABLE, 0x00000007},
533 {AUD_POLYPH80SCALEFAC, 0x00000003}, 531 {AUD_POLYPH80SCALEFAC, 0x00000003},
534 {AUD_AFE_12DB_EN, 0x00000001}, 532 {AUD_AFE_12DB_EN, 0x00000001},
535 {AAGC_GAIN, 0x00000000}, 533 {AAGC_GAIN, 0x00000000},
536 {AAGC_HYST, 0x00000018}, 534 {AAGC_HYST, 0x00000018},
537 {AAGC_DEF, 0x00000020}, 535 {AAGC_DEF, 0x00000020},
538 {AUD_DN0_FREQ, 0x00000000}, 536 {AUD_DN0_FREQ, 0x00000000},
539 {AUD_POLY0_DDS_CONSTANT, 0x000E4DB2}, 537 {AUD_POLY0_DDS_CONSTANT, 0x000E4DB2},
540 {AUD_DCOC_0_SRC, 0x00000021}, 538 {AUD_DCOC_0_SRC, 0x00000021},
541 {AUD_IIR1_0_SEL, 0x00000000}, 539 {AUD_IIR1_0_SEL, 0x00000000},
542 {AUD_IIR1_0_SHIFT, 0x00000007}, 540 {AUD_IIR1_0_SHIFT, 0x00000007},
543 {AUD_IIR1_1_SEL, 0x00000002}, 541 {AUD_IIR1_1_SEL, 0x00000002},
544 {AUD_IIR1_1_SHIFT, 0x00000000}, 542 {AUD_IIR1_1_SHIFT, 0x00000000},
545 {AUD_DCOC_1_SRC, 0x00000003}, 543 {AUD_DCOC_1_SRC, 0x00000003},
546 {AUD_DCOC1_SHIFT, 0x00000000}, 544 {AUD_DCOC1_SHIFT, 0x00000000},
547 {AUD_DCOC_PASS_IN, 0x00000000}, 545 {AUD_DCOC_PASS_IN, 0x00000000},
548 {AUD_IIR1_2_SEL, 0x00000023}, 546 {AUD_IIR1_2_SEL, 0x00000023},
549 {AUD_IIR1_2_SHIFT, 0x00000000}, 547 {AUD_IIR1_2_SHIFT, 0x00000000},
550 {AUD_IIR1_3_SEL, 0x00000004}, 548 {AUD_IIR1_3_SEL, 0x00000004},
551 {AUD_IIR1_3_SHIFT, 0x00000007}, 549 {AUD_IIR1_3_SHIFT, 0x00000007},
552 {AUD_IIR1_4_SEL, 0x00000005}, 550 {AUD_IIR1_4_SEL, 0x00000005},
553 {AUD_IIR1_4_SHIFT, 0x00000007}, 551 {AUD_IIR1_4_SHIFT, 0x00000007},
554 {AUD_IIR3_0_SEL, 0x00000007}, 552 {AUD_IIR3_0_SEL, 0x00000007},
555 {AUD_IIR3_0_SHIFT, 0x00000000}, 553 {AUD_IIR3_0_SHIFT, 0x00000000},
556 {AUD_DEEMPH0_SRC_SEL, 0x00000011}, 554 {AUD_DEEMPH0_SRC_SEL, 0x00000011},
557 {AUD_DEEMPH0_SHIFT, 0x00000000}, 555 {AUD_DEEMPH0_SHIFT, 0x00000000},
558 {AUD_DEEMPH0_G0, 0x00007000}, 556 {AUD_DEEMPH0_G0, 0x00007000},
559 {AUD_DEEMPH0_A0, 0x00000000}, 557 {AUD_DEEMPH0_A0, 0x00000000},
560 {AUD_DEEMPH0_B0, 0x00000000}, 558 {AUD_DEEMPH0_B0, 0x00000000},
561 {AUD_DEEMPH0_A1, 0x00000000}, 559 {AUD_DEEMPH0_A1, 0x00000000},
562 {AUD_DEEMPH0_B1, 0x00000000}, 560 {AUD_DEEMPH0_B1, 0x00000000},
563 {AUD_DEEMPH1_SRC_SEL, 0x00000011}, 561 {AUD_DEEMPH1_SRC_SEL, 0x00000011},
564 {AUD_DEEMPH1_SHIFT, 0x00000000}, 562 {AUD_DEEMPH1_SHIFT, 0x00000000},
565 {AUD_DEEMPH1_G0, 0x00007000}, 563 {AUD_DEEMPH1_G0, 0x00007000},
566 {AUD_DEEMPH1_A0, 0x00000000}, 564 {AUD_DEEMPH1_A0, 0x00000000},
567 {AUD_DEEMPH1_B0, 0x00000000}, 565 {AUD_DEEMPH1_B0, 0x00000000},
568 {AUD_DEEMPH1_A1, 0x00000000}, 566 {AUD_DEEMPH1_A1, 0x00000000},
569 {AUD_DEEMPH1_B1, 0x00000000}, 567 {AUD_DEEMPH1_B1, 0x00000000},
570 {AUD_OUT0_SEL, 0x0000003F}, 568 {AUD_OUT0_SEL, 0x0000003F},
571 {AUD_OUT1_SEL, 0x0000003F}, 569 {AUD_OUT1_SEL, 0x0000003F},
572 {AUD_DMD_RA_DDS, 0x00F5C285}, 570 {AUD_DMD_RA_DDS, 0x00F5C285},
573 {AUD_PLL_INT, 0x0000001E}, 571 {AUD_PLL_INT, 0x0000001E},
574 {AUD_PLL_DDS, 0x00000000}, 572 {AUD_PLL_DDS, 0x00000000},
575 {AUD_PLL_FRAC, 0x0000E542}, 573 {AUD_PLL_FRAC, 0x0000E542},
576 {AUD_RATE_ADJ1, 0x00000100}, 574 {AUD_RATE_ADJ1, 0x00000100},
577 {AUD_RATE_ADJ2, 0x00000200}, 575 {AUD_RATE_ADJ2, 0x00000200},
578 {AUD_RATE_ADJ3, 0x00000300}, 576 {AUD_RATE_ADJ3, 0x00000300},
579 {AUD_RATE_ADJ4, 0x00000400}, 577 {AUD_RATE_ADJ4, 0x00000400},
580 {AUD_RATE_ADJ5, 0x00000500}, 578 {AUD_RATE_ADJ5, 0x00000500},
581 {AUD_RATE_THRES_DMD, 0x000000C0}, 579 {AUD_RATE_THRES_DMD, 0x000000C0},
582 {/* end of list */ }, 580 { /* end of list */ },
583 }; 581 };
584 582
585 static const struct rlist a2_deemph50[] = { 583 static const struct rlist a2_deemph50[] = {
586 {AUD_DEEMPH0_G0, 0x00000380}, 584 {AUD_DEEMPH0_G0, 0x00000380},
587 {AUD_DEEMPH1_G0, 0x00000380}, 585 {AUD_DEEMPH1_G0, 0x00000380},
588 {AUD_DEEMPHGAIN_R, 0x000011e1}, 586 {AUD_DEEMPHGAIN_R, 0x000011e1},
589 {AUD_DEEMPHNUMER1_R, 0x0002a7bc}, 587 {AUD_DEEMPHNUMER1_R, 0x0002a7bc},
590 {AUD_DEEMPHNUMER2_R, 0x0003023c}, 588 {AUD_DEEMPHNUMER2_R, 0x0003023c},
591 { /* end of list */ }, 589 { /* end of list */ },
592 }; 590 };
593 591
594 set_audio_start(core, SEL_A2); 592 set_audio_start(core, SEL_A2);
595 switch (core->tvaudio) { 593 switch (core->tvaudio) {
596 case WW_BG: 594 case WW_BG:
597 dprintk("%s PAL-BG A1/2 (status: known-good)\n",__FUNCTION__); 595 dprintk("%s PAL-BG A1/2 (status: known-good)\n", __FUNCTION__);
598 set_audio_registers(core, a2_bgdk_common); 596 set_audio_registers(core, a2_bgdk_common);
599 set_audio_registers(core, a2_bg); 597 set_audio_registers(core, a2_bg);
600 set_audio_registers(core, a2_deemph50); 598 set_audio_registers(core, a2_deemph50);
601 break; 599 break;
602 case WW_DK: 600 case WW_DK:
603 dprintk("%s PAL-DK A1/2 (status: known-good)\n",__FUNCTION__); 601 dprintk("%s PAL-DK A1/2 (status: known-good)\n", __FUNCTION__);
604 set_audio_registers(core, a2_bgdk_common); 602 set_audio_registers(core, a2_bgdk_common);
605 set_audio_registers(core, a2_dk); 603 set_audio_registers(core, a2_dk);
606 set_audio_registers(core, a2_deemph50); 604 set_audio_registers(core, a2_deemph50);
607 break; 605 break;
608 case WW_I: 606 case WW_I:
609 dprintk("%s PAL-I A1 (status: known-good)\n",__FUNCTION__); 607 dprintk("%s PAL-I A1 (status: known-good)\n", __FUNCTION__);
610 set_audio_registers(core, a1_i); 608 set_audio_registers(core, a1_i);
611 set_audio_registers(core, a2_deemph50); 609 set_audio_registers(core, a2_deemph50);
612 break; 610 break;
613 case WW_L: 611 case WW_L:
614 dprintk("%s AM-L (status: devel)\n",__FUNCTION__); 612 dprintk("%s AM-L (status: devel)\n", __FUNCTION__);
615 set_audio_registers(core, am_l); 613 set_audio_registers(core, am_l);
616 break; 614 break;
617 default: 615 default:
618 dprintk("%s Warning: wrong value\n",__FUNCTION__); 616 dprintk("%s Warning: wrong value\n", __FUNCTION__);
619 return; 617 return;
620 break; 618 break;
621 }; 619 };
@@ -631,71 +629,71 @@ static void set_audio_standard_EIAJ(struct cx88_core *core)
631 629
632 { /* end of list */ }, 630 { /* end of list */ },
633 }; 631 };
634 dprintk("%s (status: unknown)\n",__FUNCTION__); 632 dprintk("%s (status: unknown)\n", __FUNCTION__);
635 633
636 set_audio_start(core, SEL_EIAJ); 634 set_audio_start(core, SEL_EIAJ);
637 set_audio_registers(core, eiaj); 635 set_audio_registers(core, eiaj);
638 set_audio_finish(core, EN_EIAJ_AUTO_STEREO); 636 set_audio_finish(core, EN_EIAJ_AUTO_STEREO);
639} 637}
640 638
641static void set_audio_standard_FM(struct cx88_core *core, enum cx88_deemph_type deemph) 639static void set_audio_standard_FM(struct cx88_core *core,
640 enum cx88_deemph_type deemph)
642{ 641{
643 static const struct rlist fm_deemph_50[] = { 642 static const struct rlist fm_deemph_50[] = {
644 { AUD_DEEMPH0_G0, 0x0C45 }, 643 {AUD_DEEMPH0_G0, 0x0C45},
645 { AUD_DEEMPH0_A0, 0x6262 }, 644 {AUD_DEEMPH0_A0, 0x6262},
646 { AUD_DEEMPH0_B0, 0x1C29 }, 645 {AUD_DEEMPH0_B0, 0x1C29},
647 { AUD_DEEMPH0_A1, 0x3FC66}, 646 {AUD_DEEMPH0_A1, 0x3FC66},
648 { AUD_DEEMPH0_B1, 0x399A }, 647 {AUD_DEEMPH0_B1, 0x399A},
649 648
650 { AUD_DEEMPH1_G0, 0x0D80 }, 649 {AUD_DEEMPH1_G0, 0x0D80},
651 { AUD_DEEMPH1_A0, 0x6262 }, 650 {AUD_DEEMPH1_A0, 0x6262},
652 { AUD_DEEMPH1_B0, 0x1C29 }, 651 {AUD_DEEMPH1_B0, 0x1C29},
653 { AUD_DEEMPH1_A1, 0x3FC66}, 652 {AUD_DEEMPH1_A1, 0x3FC66},
654 { AUD_DEEMPH1_B1, 0x399A}, 653 {AUD_DEEMPH1_B1, 0x399A},
655 654
656 { AUD_POLYPH80SCALEFAC, 0x0003}, 655 {AUD_POLYPH80SCALEFAC, 0x0003},
657 { /* end of list */ }, 656 { /* end of list */ },
658 }; 657 };
659 static const struct rlist fm_deemph_75[] = { 658 static const struct rlist fm_deemph_75[] = {
660 { AUD_DEEMPH0_G0, 0x091B }, 659 {AUD_DEEMPH0_G0, 0x091B},
661 { AUD_DEEMPH0_A0, 0x6B68 }, 660 {AUD_DEEMPH0_A0, 0x6B68},
662 { AUD_DEEMPH0_B0, 0x11EC }, 661 {AUD_DEEMPH0_B0, 0x11EC},
663 { AUD_DEEMPH0_A1, 0x3FC66}, 662 {AUD_DEEMPH0_A1, 0x3FC66},
664 { AUD_DEEMPH0_B1, 0x399A }, 663 {AUD_DEEMPH0_B1, 0x399A},
665 664
666 { AUD_DEEMPH1_G0, 0x0AA0 }, 665 {AUD_DEEMPH1_G0, 0x0AA0},
667 { AUD_DEEMPH1_A0, 0x6B68 }, 666 {AUD_DEEMPH1_A0, 0x6B68},
668 { AUD_DEEMPH1_B0, 0x11EC }, 667 {AUD_DEEMPH1_B0, 0x11EC},
669 { AUD_DEEMPH1_A1, 0x3FC66}, 668 {AUD_DEEMPH1_A1, 0x3FC66},
670 { AUD_DEEMPH1_B1, 0x399A}, 669 {AUD_DEEMPH1_B1, 0x399A},
671 670
672 { AUD_POLYPH80SCALEFAC, 0x0003}, 671 {AUD_POLYPH80SCALEFAC, 0x0003},
673 { /* end of list */ }, 672 { /* end of list */ },
674 }; 673 };
675 674
676 /* It is enough to leave default values? */ 675 /* It is enough to leave default values? */
677 static const struct rlist fm_no_deemph[] = { 676 static const struct rlist fm_no_deemph[] = {
678 677
679 { AUD_POLYPH80SCALEFAC, 0x0003}, 678 {AUD_POLYPH80SCALEFAC, 0x0003},
680 { /* end of list */ }, 679 { /* end of list */ },
681 }; 680 };
682 681
683 dprintk("%s (status: unknown)\n",__FUNCTION__); 682 dprintk("%s (status: unknown)\n", __FUNCTION__);
684 set_audio_start(core, SEL_FMRADIO); 683 set_audio_start(core, SEL_FMRADIO);
685 684
686 switch (deemph) 685 switch (deemph) {
687 { 686 case FM_NO_DEEMPH:
688 case FM_NO_DEEMPH: 687 set_audio_registers(core, fm_no_deemph);
689 set_audio_registers(core, fm_no_deemph); 688 break;
690 break;
691 689
692 case FM_DEEMPH_50: 690 case FM_DEEMPH_50:
693 set_audio_registers(core, fm_deemph_50); 691 set_audio_registers(core, fm_deemph_50);
694 break; 692 break;
695 693
696 case FM_DEEMPH_75: 694 case FM_DEEMPH_75:
697 set_audio_registers(core, fm_deemph_75); 695 set_audio_registers(core, fm_deemph_75);
698 break; 696 break;
699 } 697 }
700 698
701 set_audio_finish(core, EN_FMRADIO_AUTO_STEREO); 699 set_audio_finish(core, EN_FMRADIO_AUTO_STEREO);
@@ -705,22 +703,22 @@ static void set_audio_standard_FM(struct cx88_core *core, enum cx88_deemph_type
705 703
706int cx88_detect_nicam(struct cx88_core *core) 704int cx88_detect_nicam(struct cx88_core *core)
707{ 705{
708 int i, j=0; 706 int i, j = 0;
709 707
710 dprintk("start nicam autodetect.\n"); 708 dprintk("start nicam autodetect.\n");
711 709
712 for(i=0; i<6; i++) { 710 for (i = 0; i < 6; i++) {
713 /* if bit1=1 then nicam is detected */ 711 /* if bit1=1 then nicam is detected */
714 j+= ((cx_read(AUD_NICAM_STATUS2) & 0x02) >> 1); 712 j += ((cx_read(AUD_NICAM_STATUS2) & 0x02) >> 1);
715 713
716 /* 3x detected: absolutly sure now */ 714 /* 3x detected: absolutly sure now */
717 if(j==3) { 715 if (j == 3) {
718 dprintk("nicam is detected.\n"); 716 dprintk("nicam is detected.\n");
719 return 1; 717 return 1;
720 } 718 }
721 719
722 /* wait a little bit for next reading status */ 720 /* wait a little bit for next reading status */
723 msleep (10); 721 msleep(10);
724 } 722 }
725 723
726 dprintk("nicam is not detected.\n"); 724 dprintk("nicam is not detected.\n");
@@ -743,24 +741,24 @@ void cx88_set_tvaudio(struct cx88_core *core)
743 /* set nicam mode - otherwise 741 /* set nicam mode - otherwise
744 AUD_NICAM_STATUS2 contains wrong values */ 742 AUD_NICAM_STATUS2 contains wrong values */
745 set_audio_standard_NICAM(core, EN_NICAM_FORCE_MONO1); 743 set_audio_standard_NICAM(core, EN_NICAM_FORCE_MONO1);
746 if(0 == cx88_detect_nicam(core)) { 744 if (0 == cx88_detect_nicam(core)) {
747 /* fall back to fm / am mono */ 745 /* fall back to fm / am mono */
748 set_audio_standard_A2(core, EN_A2_FORCE_MONO1); 746 set_audio_standard_A2(core, EN_A2_FORCE_MONO1);
749 core->use_nicam = 0; 747 core->use_nicam = 0;
750 } else { 748 } else {
751 core->use_nicam = 1; 749 core->use_nicam = 1;
752 } 750 }
753 break; 751 break;
754 case WW_EIAJ: 752 case WW_EIAJ:
755 set_audio_standard_EIAJ(core); 753 set_audio_standard_EIAJ(core);
756 break; 754 break;
757 case WW_FM: 755 case WW_FM:
758 set_audio_standard_FM(core,FM_NO_DEEMPH); 756 set_audio_standard_FM(core, FM_NO_DEEMPH);
759 break; 757 break;
760 case WW_NONE: 758 case WW_NONE:
761 default: 759 default:
762 printk("%s/0: unknown tv audio mode [%d]\n", 760 printk("%s/0: unknown tv audio mode [%d]\n",
763 core->name, core->tvaudio); 761 core->name, core->tvaudio);
764 break; 762 break;
765 } 763 }
766 return; 764 return;
@@ -773,12 +771,12 @@ void cx88_newstation(struct cx88_core *core)
773 771
774void cx88_get_stereo(struct cx88_core *core, struct v4l2_tuner *t) 772void cx88_get_stereo(struct cx88_core *core, struct v4l2_tuner *t)
775{ 773{
776 static char *m[] = {"stereo", "dual mono", "mono", "sap"}; 774 static char *m[] = { "stereo", "dual mono", "mono", "sap" };
777 static char *p[] = {"no pilot", "pilot c1", "pilot c2", "?"}; 775 static char *p[] = { "no pilot", "pilot c1", "pilot c2", "?" };
778 u32 reg,mode,pilot; 776 u32 reg, mode, pilot;
779 777
780 reg = cx_read(AUD_STATUS); 778 reg = cx_read(AUD_STATUS);
781 mode = reg & 0x03; 779 mode = reg & 0x03;
782 pilot = (reg >> 2) & 0x03; 780 pilot = (reg >> 2) & 0x03;
783 781
784 if (core->astat != reg) 782 if (core->astat != reg)
@@ -795,14 +793,13 @@ void cx88_get_stereo(struct cx88_core *core, struct v4l2_tuner *t)
795 793
796# if 0 794# if 0
797 t->capability = V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_SAP | 795 t->capability = V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_SAP |
798 V4L2_TUNER_CAP_LANG1 | V4L2_TUNER_CAP_LANG2; 796 V4L2_TUNER_CAP_LANG1 | V4L2_TUNER_CAP_LANG2;
799 t->rxsubchans = V4L2_TUNER_SUB_MONO; 797 t->rxsubchans = V4L2_TUNER_SUB_MONO;
800 t->audmode = V4L2_TUNER_MODE_MONO; 798 t->audmode = V4L2_TUNER_MODE_MONO;
801 799
802 switch (core->tvaudio) { 800 switch (core->tvaudio) {
803 case WW_BTSC: 801 case WW_BTSC:
804 t->capability = V4L2_TUNER_CAP_STEREO | 802 t->capability = V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_SAP;
805 V4L2_TUNER_CAP_SAP;
806 t->rxsubchans = V4L2_TUNER_SUB_STEREO; 803 t->rxsubchans = V4L2_TUNER_SUB_STEREO;
807 if (1 == pilot) { 804 if (1 == pilot) {
808 /* SAP */ 805 /* SAP */
@@ -814,13 +811,15 @@ void cx88_get_stereo(struct cx88_core *core, struct v4l2_tuner *t)
814 case WW_A2_M: 811 case WW_A2_M:
815 if (1 == pilot) { 812 if (1 == pilot) {
816 /* stereo */ 813 /* stereo */
817 t->rxsubchans = V4L2_TUNER_SUB_MONO | V4L2_TUNER_SUB_STEREO; 814 t->rxsubchans =
815 V4L2_TUNER_SUB_MONO | V4L2_TUNER_SUB_STEREO;
818 if (0 == mode) 816 if (0 == mode)
819 t->audmode = V4L2_TUNER_MODE_STEREO; 817 t->audmode = V4L2_TUNER_MODE_STEREO;
820 } 818 }
821 if (2 == pilot) { 819 if (2 == pilot) {
822 /* dual language -- FIXME */ 820 /* dual language -- FIXME */
823 t->rxsubchans = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2; 821 t->rxsubchans =
822 V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
824 t->audmode = V4L2_TUNER_MODE_LANG1; 823 t->audmode = V4L2_TUNER_MODE_LANG1;
825 } 824 }
826 break; 825 break;
@@ -835,7 +834,7 @@ void cx88_get_stereo(struct cx88_core *core, struct v4l2_tuner *t)
835 t->audmode = V4L2_TUNER_MODE_STEREO; 834 t->audmode = V4L2_TUNER_MODE_STEREO;
836 t->rxsubchans |= V4L2_TUNER_SUB_STEREO; 835 t->rxsubchans |= V4L2_TUNER_SUB_STEREO;
837 } 836 }
838 break ; 837 break;
839 default: 838 default:
840 /* nothing */ 839 /* nothing */
841 break; 840 break;
@@ -846,7 +845,7 @@ void cx88_get_stereo(struct cx88_core *core, struct v4l2_tuner *t)
846 845
847void cx88_set_stereo(struct cx88_core *core, u32 mode, int manual) 846void cx88_set_stereo(struct cx88_core *core, u32 mode, int manual)
848{ 847{
849 u32 ctl = UNSET; 848 u32 ctl = UNSET;
850 u32 mask = UNSET; 849 u32 mask = UNSET;
851 850
852 if (manual) { 851 if (manual) {
@@ -878,21 +877,24 @@ void cx88_set_stereo(struct cx88_core *core, u32 mode, int manual)
878 case WW_DK: 877 case WW_DK:
879 case WW_I: 878 case WW_I:
880 case WW_L: 879 case WW_L:
881 if(1 == core->use_nicam) { 880 if (1 == core->use_nicam) {
882 switch (mode) { 881 switch (mode) {
883 case V4L2_TUNER_MODE_MONO: 882 case V4L2_TUNER_MODE_MONO:
884 case V4L2_TUNER_MODE_LANG1: 883 case V4L2_TUNER_MODE_LANG1:
885 set_audio_standard_NICAM(core, EN_NICAM_FORCE_MONO1); 884 set_audio_standard_NICAM(core,
885 EN_NICAM_FORCE_MONO1);
886 break; 886 break;
887 case V4L2_TUNER_MODE_LANG2: 887 case V4L2_TUNER_MODE_LANG2:
888 set_audio_standard_NICAM(core, EN_NICAM_FORCE_MONO2); 888 set_audio_standard_NICAM(core,
889 EN_NICAM_FORCE_MONO2);
889 break; 890 break;
890 case V4L2_TUNER_MODE_STEREO: 891 case V4L2_TUNER_MODE_STEREO:
891 set_audio_standard_NICAM(core, EN_NICAM_FORCE_STEREO); 892 set_audio_standard_NICAM(core,
893 EN_NICAM_FORCE_STEREO);
892 break; 894 break;
893 } 895 }
894 } else { 896 } else {
895 if ( (core->tvaudio == WW_I) || (core->tvaudio == WW_L) ) { 897 if ((core->tvaudio == WW_I) || (core->tvaudio == WW_L)) {
896 /* fall back to fm / am mono */ 898 /* fall back to fm / am mono */
897 set_audio_standard_A2(core, EN_A2_FORCE_MONO1); 899 set_audio_standard_A2(core, EN_A2_FORCE_MONO1);
898 } else { 900 } else {
@@ -900,13 +902,16 @@ void cx88_set_stereo(struct cx88_core *core, u32 mode, int manual)
900 switch (mode) { 902 switch (mode) {
901 case V4L2_TUNER_MODE_MONO: 903 case V4L2_TUNER_MODE_MONO:
902 case V4L2_TUNER_MODE_LANG1: 904 case V4L2_TUNER_MODE_LANG1:
903 set_audio_standard_A2(core, EN_A2_FORCE_MONO1); 905 set_audio_standard_A2(core,
906 EN_A2_FORCE_MONO1);
904 break; 907 break;
905 case V4L2_TUNER_MODE_LANG2: 908 case V4L2_TUNER_MODE_LANG2:
906 set_audio_standard_A2(core, EN_A2_FORCE_MONO2); 909 set_audio_standard_A2(core,
910 EN_A2_FORCE_MONO2);
907 break; 911 break;
908 case V4L2_TUNER_MODE_STEREO: 912 case V4L2_TUNER_MODE_STEREO:
909 set_audio_standard_A2(core, EN_A2_FORCE_STEREO); 913 set_audio_standard_A2(core,
914 EN_A2_FORCE_STEREO);
910 break; 915 break;
911 } 916 }
912 } 917 }
@@ -915,11 +920,11 @@ void cx88_set_stereo(struct cx88_core *core, u32 mode, int manual)
915 case WW_FM: 920 case WW_FM:
916 switch (mode) { 921 switch (mode) {
917 case V4L2_TUNER_MODE_MONO: 922 case V4L2_TUNER_MODE_MONO:
918 ctl = EN_FMRADIO_FORCE_MONO; 923 ctl = EN_FMRADIO_FORCE_MONO;
919 mask = 0x3f; 924 mask = 0x3f;
920 break; 925 break;
921 case V4L2_TUNER_MODE_STEREO: 926 case V4L2_TUNER_MODE_STEREO:
922 ctl = EN_FMRADIO_AUTO_STEREO; 927 ctl = EN_FMRADIO_AUTO_STEREO;
923 mask = 0x3f; 928 mask = 0x3f;
924 break; 929 break;
925 } 930 }
@@ -949,8 +954,8 @@ int cx88_audio_thread(void *data)
949 break; 954 break;
950 955
951 /* just monitor the audio status for now ... */ 956 /* just monitor the audio status for now ... */
952 memset(&t,0,sizeof(t)); 957 memset(&t, 0, sizeof(t));
953 cx88_get_stereo(core,&t); 958 cx88_get_stereo(core, &t);
954 959
955 if (UNSET != core->audiomode_manual) 960 if (UNSET != core->audiomode_manual)
956 /* manually set, don't do anything. */ 961 /* manually set, don't do anything. */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 09:54:45 -0500