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authorMauro Carvalho Chehab <mchehab@brturbo.com.br>2005-09-09 16:03:41 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2005-09-09 16:57:49 -0400
commite52e98a7eccfb0e7e91630d01690fb11d77db77d (patch)
treed910e743159977ee695c40b795a4b84d43a4dbcb /drivers/media/video/cx88/cx88-tvaudio.c
parent24a70fdce872d70171b1f49dcd1a7c3a4e8396b2 (diff)
[PATCH] v4l: CX88 updates and card additions
- Remove $Id CVS logs for V4L files - add ioctl indirection via cx88_ioctl_hook and cx88_ioctl_translator to cx88-blackbird.c. - declare the indirection hooks from cx88-blackbird.c. - dcprintk macro which uses core instead of dev->core on cx88-video.c. - replace dev->core occurances with core on cx88-video.c. - CodingStyle fixes. - MaxInput replaced by a define. - cx8801 structures moved from cx88.h. - The output_mode needs to be set for the Hauppauge Nova-T DVB-T for versions after 2.6.12. - Corrected GPIO values for cx88 cards #28 & #31 for s-video and composite. - Updated DViCO FusionHDTV5 Gold & added DVB support. - Fixed DViCO FusionHDTV 3 Gold-Q GPIO. - Some clean up in cx88-tvaudio.c - replaced hex values when writing to AUD_CTL to EN_xx for better reading. - Allow select by hand between Mono, Lang1, Lang2 and Stereo for BTSC. - Support for stereo NICAM and BTSC improved. - Broken stereo check removed. - Added support for remote control to Cinergy DVBT-1400. - local var renamed from rc5 to a better name (ircode). - LGDT330X QAM lock bug fixes. - Some reorg: move some bits to struct cx88_core, factor out common ioctl's to cx88_do_ioctl. - Get rid of '//' comments, replace them with #if 0 and /**/. - Minor clean-ups: remove dcprintk and replace all instances of "dev->core" with "core". - Added some registers to control PCI controller at CX2388x chips. - New tuner standby API. - Small mpeg fixes and cleanups for blackbird. - fix mpeg packet size & count - add VIDIOC_QUERYCAP ioctl for the mpeg stream - return more information in struct v4l2_format - fix default window height - small cleanups Signed-off-by: Uli Luckas <luckas@musoft.de> Signed-off-by: Torsten Seeboth <Torsten.Seeboth@t-online.de> Signed-off-by: Nickolay V. Shmyrev <nshmyrev@yandex.ru> Signed-off-by: Michael Krufky <mkrufky@m1k.net> Signed-off-by: Patrick Boettcher <patrick.boettcher@desy.de> Signed-off-by: Catalin Climov <catalin@climov.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@brturbo.com.br> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/media/video/cx88/cx88-tvaudio.c')
-rw-r--r--drivers/media/video/cx88/cx88-tvaudio.c742
1 files changed, 385 insertions, 357 deletions
diff --git a/drivers/media/video/cx88/cx88-tvaudio.c b/drivers/media/video/cx88/cx88-tvaudio.c
index 91207f10bae7..2765acee0285 100644
--- a/drivers/media/video/cx88/cx88-tvaudio.c
+++ b/drivers/media/video/cx88/cx88-tvaudio.c
@@ -1,5 +1,4 @@
1/* 1/*
2 $Id: cx88-tvaudio.c,v 1.37 2005/07/07 13:58:38 mchehab Exp $
3 2
4 cx88x-audio.c - Conexant CX23880/23881 audio downstream driver driver 3 cx88x-audio.c - Conexant CX23880/23881 audio downstream driver driver
5 4
@@ -121,25 +120,19 @@ static void set_audio_registers(struct cx88_core *core,
121} 120}
122 121
123static void set_audio_start(struct cx88_core *core, 122static void set_audio_start(struct cx88_core *core,
124 u32 mode, u32 ctl) 123 u32 mode)
125{ 124{
126 // mute 125 // mute
127 cx_write(AUD_VOL_CTL, (1 << 6)); 126 cx_write(AUD_VOL_CTL, (1 << 6));
128 127
129 // increase level of input by 12dB
130// cx_write(AUD_AFE_12DB_EN, 0x0001);
131 cx_write(AUD_AFE_12DB_EN, 0x0000);
132
133 // start programming 128 // start programming
134 cx_write(AUD_CTL, 0x0000); 129 cx_write(AUD_CTL, 0x0000);
135 cx_write(AUD_INIT, mode); 130 cx_write(AUD_INIT, mode);
136 cx_write(AUD_INIT_LD, 0x0001); 131 cx_write(AUD_INIT_LD, 0x0001);
137 cx_write(AUD_SOFT_RESET, 0x0001); 132 cx_write(AUD_SOFT_RESET, 0x0001);
138
139 cx_write(AUD_CTL, ctl);
140} 133}
141 134
142static void set_audio_finish(struct cx88_core *core) 135static void set_audio_finish(struct cx88_core *core, u32 ctl)
143{ 136{
144 u32 volume; 137 u32 volume;
145 138
@@ -154,25 +147,25 @@ static void set_audio_finish(struct cx88_core *core)
154 cx_write(AUD_I2SOUTPUTCNTL, 1); 147 cx_write(AUD_I2SOUTPUTCNTL, 1);
155 cx_write(AUD_I2SCNTL, 0); 148 cx_write(AUD_I2SCNTL, 0);
156 //cx_write(AUD_APB_IN_RATE_ADJ, 0); 149 //cx_write(AUD_APB_IN_RATE_ADJ, 0);
150 } else {
151 ctl |= EN_DAC_ENABLE;
152 cx_write(AUD_CTL, ctl);
157 } 153 }
158 154
159 // finish programming 155 /* finish programming */
160 cx_write(AUD_SOFT_RESET, 0x0000); 156 cx_write(AUD_SOFT_RESET, 0x0000);
161 157
162 // start audio processing 158 /* unmute */
163 cx_set(AUD_CTL, EN_DAC_ENABLE);
164
165 // unmute
166 volume = cx_sread(SHADOW_AUD_VOL_CTL); 159 volume = cx_sread(SHADOW_AUD_VOL_CTL);
167 cx_swrite(SHADOW_AUD_VOL_CTL, AUD_VOL_CTL, volume); 160 cx_swrite(SHADOW_AUD_VOL_CTL, AUD_VOL_CTL, volume);
168} 161}
169 162
170/* ----------------------------------------------------------- */ 163/* ----------------------------------------------------------- */
171 164
172static void set_audio_standard_BTSC(struct cx88_core *core, unsigned int sap) 165static void set_audio_standard_BTSC(struct cx88_core *core, unsigned int sap, u32 mode)
173{ 166{
174 static const struct rlist btsc[] = { 167 static const struct rlist btsc[] = {
175 /* from dscaler */ 168 { AUD_AFE_12DB_EN, 0x00000001 },
176 { AUD_OUT1_SEL, 0x00000013 }, 169 { AUD_OUT1_SEL, 0x00000013 },
177 { AUD_OUT1_SHIFT, 0x00000000 }, 170 { AUD_OUT1_SHIFT, 0x00000000 },
178 { AUD_POLY0_DDS_CONSTANT, 0x0012010c }, 171 { AUD_POLY0_DDS_CONSTANT, 0x0012010c },
@@ -206,9 +199,10 @@ static void set_audio_standard_BTSC(struct cx88_core *core, unsigned int sap)
206 { AUD_RDSI_SHIFT, 0x00000000 }, 199 { AUD_RDSI_SHIFT, 0x00000000 },
207 { AUD_RDSQ_SHIFT, 0x00000000 }, 200 { AUD_RDSQ_SHIFT, 0x00000000 },
208 { AUD_POLYPH80SCALEFAC, 0x00000003 }, 201 { AUD_POLYPH80SCALEFAC, 0x00000003 },
209 { /* end of list */ }, 202 { /* end of list */ },
210 }; 203 };
211 static const struct rlist btsc_sap[] = { 204 static const struct rlist btsc_sap[] = {
205 { AUD_AFE_12DB_EN, 0x00000001 },
212 { AUD_DBX_IN_GAIN, 0x00007200 }, 206 { AUD_DBX_IN_GAIN, 0x00007200 },
213 { AUD_DBX_WBE_GAIN, 0x00006200 }, 207 { AUD_DBX_WBE_GAIN, 0x00006200 },
214 { AUD_DBX_SE_GAIN, 0x00006200 }, 208 { AUD_DBX_SE_GAIN, 0x00006200 },
@@ -259,371 +253,400 @@ static void set_audio_standard_BTSC(struct cx88_core *core, unsigned int sap)
259 { AUD_RDSI_SHIFT, 0x00000000 }, 253 { AUD_RDSI_SHIFT, 0x00000000 },
260 { AUD_RDSQ_SHIFT, 0x00000000 }, 254 { AUD_RDSQ_SHIFT, 0x00000000 },
261 { AUD_POLYPH80SCALEFAC, 0x00000003 }, 255 { AUD_POLYPH80SCALEFAC, 0x00000003 },
262 { /* end of list */ }, 256 { /* end of list */ },
263 }; 257 };
264 258
265 // dscaler: exactly taken from driver, 259 mode |= EN_FMRADIO_EN_RDS;
266 // dscaler: don't know why to set EN_FMRADIO_EN_RDS 260
267 if (sap) { 261 if (sap) {
268 dprintk("%s SAP (status: unknown)\n",__FUNCTION__); 262 dprintk("%s SAP (status: unknown)\n",__FUNCTION__);
269 set_audio_start(core, 0x0001, 263 set_audio_start(core, SEL_SAP);
270 EN_FMRADIO_EN_RDS | EN_BTSC_FORCE_SAP);
271 set_audio_registers(core, btsc_sap); 264 set_audio_registers(core, btsc_sap);
265 set_audio_finish(core, mode);
272 } else { 266 } else {
273 dprintk("%s (status: known-good)\n",__FUNCTION__); 267 dprintk("%s (status: known-good)\n",__FUNCTION__);
274 set_audio_start(core, 0x0001, 268 set_audio_start(core, SEL_BTSC);
275 EN_FMRADIO_EN_RDS | EN_BTSC_AUTO_STEREO);
276 set_audio_registers(core, btsc); 269 set_audio_registers(core, btsc);
270 set_audio_finish(core, mode);
277 } 271 }
278 set_audio_finish(core);
279} 272}
280 273
281 274
282static void set_audio_standard_NICAM_L(struct cx88_core *core, int stereo) 275static void set_audio_standard_NICAM_L(struct cx88_core *core, int stereo)
283{ 276{
284 /* This is probably weird.. 277 /* This is probably weird..
285 * Let's operate and find out. */ 278 * Let's operate and find out. */
286 279
287 static const struct rlist nicam_l_mono[] = { 280 static const struct rlist nicam_l_mono[] = {
288 { AUD_ERRLOGPERIOD_R, 0x00000064 }, 281 { AUD_ERRLOGPERIOD_R, 0x00000064 },
289 { AUD_ERRINTRPTTHSHLD1_R, 0x00000FFF }, 282 { AUD_ERRINTRPTTHSHLD1_R, 0x00000FFF },
290 { AUD_ERRINTRPTTHSHLD2_R, 0x0000001F }, 283 { AUD_ERRINTRPTTHSHLD2_R, 0x0000001F },
291 { AUD_ERRINTRPTTHSHLD3_R, 0x0000000F }, 284 { AUD_ERRINTRPTTHSHLD3_R, 0x0000000F },
292 285
293 { AUD_PDF_DDS_CNST_BYTE2, 0x48 }, 286 { AUD_PDF_DDS_CNST_BYTE2, 0x48 },
294 { AUD_PDF_DDS_CNST_BYTE1, 0x3D }, 287 { AUD_PDF_DDS_CNST_BYTE1, 0x3D },
295 { AUD_QAM_MODE, 0x00 }, 288 { AUD_QAM_MODE, 0x00 },
296 { AUD_PDF_DDS_CNST_BYTE0, 0xf5 }, 289 { AUD_PDF_DDS_CNST_BYTE0, 0xf5 },
297 { AUD_PHACC_FREQ_8MSB, 0x3a }, 290 { AUD_PHACC_FREQ_8MSB, 0x3a },
298 { AUD_PHACC_FREQ_8LSB, 0x4a }, 291 { AUD_PHACC_FREQ_8LSB, 0x4a },
299 292
300 { AUD_DEEMPHGAIN_R, 0x6680 }, 293 { AUD_DEEMPHGAIN_R, 0x6680 },
301 { AUD_DEEMPHNUMER1_R, 0x353DE }, 294 { AUD_DEEMPHNUMER1_R, 0x353DE },
302 { AUD_DEEMPHNUMER2_R, 0x1B1 }, 295 { AUD_DEEMPHNUMER2_R, 0x1B1 },
303 { AUD_DEEMPHDENOM1_R, 0x0F3D0 }, 296 { AUD_DEEMPHDENOM1_R, 0x0F3D0 },
304 { AUD_DEEMPHDENOM2_R, 0x0 }, 297 { AUD_DEEMPHDENOM2_R, 0x0 },
305 { AUD_FM_MODE_ENABLE, 0x7 }, 298 { AUD_FM_MODE_ENABLE, 0x7 },
306 { AUD_POLYPH80SCALEFAC, 0x3 }, 299 { AUD_POLYPH80SCALEFAC, 0x3 },
307 { AUD_AFE_12DB_EN, 0x1 }, 300 { AUD_AFE_12DB_EN, 0x1 },
308 { AAGC_GAIN, 0x0 }, 301 { AAGC_GAIN, 0x0 },
309 { AAGC_HYST, 0x18 }, 302 { AAGC_HYST, 0x18 },
310 { AAGC_DEF, 0x20 }, 303 { AAGC_DEF, 0x20 },
311 { AUD_DN0_FREQ, 0x0 }, 304 { AUD_DN0_FREQ, 0x0 },
312 { AUD_POLY0_DDS_CONSTANT, 0x0E4DB2 }, 305 { AUD_POLY0_DDS_CONSTANT, 0x0E4DB2 },
313 { AUD_DCOC_0_SRC, 0x21 }, 306 { AUD_DCOC_0_SRC, 0x21 },
314 { AUD_IIR1_0_SEL, 0x0 }, 307 { AUD_IIR1_0_SEL, 0x0 },
315 { AUD_IIR1_0_SHIFT, 0x7 }, 308 { AUD_IIR1_0_SHIFT, 0x7 },
316 { AUD_IIR1_1_SEL, 0x2 }, 309 { AUD_IIR1_1_SEL, 0x2 },
317 { AUD_IIR1_1_SHIFT, 0x0 }, 310 { AUD_IIR1_1_SHIFT, 0x0 },
318 { AUD_DCOC_1_SRC, 0x3 }, 311 { AUD_DCOC_1_SRC, 0x3 },
319 { AUD_DCOC1_SHIFT, 0x0 }, 312 { AUD_DCOC1_SHIFT, 0x0 },
320 { AUD_DCOC_PASS_IN, 0x0 }, 313 { AUD_DCOC_PASS_IN, 0x0 },
321 { AUD_IIR1_2_SEL, 0x23 }, 314 { AUD_IIR1_2_SEL, 0x23 },
322 { AUD_IIR1_2_SHIFT, 0x0 }, 315 { AUD_IIR1_2_SHIFT, 0x0 },
323 { AUD_IIR1_3_SEL, 0x4 }, 316 { AUD_IIR1_3_SEL, 0x4 },
324 { AUD_IIR1_3_SHIFT, 0x7 }, 317 { AUD_IIR1_3_SHIFT, 0x7 },
325 { AUD_IIR1_4_SEL, 0x5 }, 318 { AUD_IIR1_4_SEL, 0x5 },
326 { AUD_IIR1_4_SHIFT, 0x7 }, 319 { AUD_IIR1_4_SHIFT, 0x7 },
327 { AUD_IIR3_0_SEL, 0x7 }, 320 { AUD_IIR3_0_SEL, 0x7 },
328 { AUD_IIR3_0_SHIFT, 0x0 }, 321 { AUD_IIR3_0_SHIFT, 0x0 },
329 { AUD_DEEMPH0_SRC_SEL, 0x11 }, 322 { AUD_DEEMPH0_SRC_SEL, 0x11 },
330 { AUD_DEEMPH0_SHIFT, 0x0 }, 323 { AUD_DEEMPH0_SHIFT, 0x0 },
331 { AUD_DEEMPH0_G0, 0x7000 }, 324 { AUD_DEEMPH0_G0, 0x7000 },
332 { AUD_DEEMPH0_A0, 0x0 }, 325 { AUD_DEEMPH0_A0, 0x0 },
333 { AUD_DEEMPH0_B0, 0x0 }, 326 { AUD_DEEMPH0_B0, 0x0 },
334 { AUD_DEEMPH0_A1, 0x0 }, 327 { AUD_DEEMPH0_A1, 0x0 },
335 { AUD_DEEMPH0_B1, 0x0 }, 328 { AUD_DEEMPH0_B1, 0x0 },
336 { AUD_DEEMPH1_SRC_SEL, 0x11 }, 329 { AUD_DEEMPH1_SRC_SEL, 0x11 },
337 { AUD_DEEMPH1_SHIFT, 0x0 }, 330 { AUD_DEEMPH1_SHIFT, 0x0 },
338 { AUD_DEEMPH1_G0, 0x7000 }, 331 { AUD_DEEMPH1_G0, 0x7000 },
339 { AUD_DEEMPH1_A0, 0x0 }, 332 { AUD_DEEMPH1_A0, 0x0 },
340 { AUD_DEEMPH1_B0, 0x0 }, 333 { AUD_DEEMPH1_B0, 0x0 },
341 { AUD_DEEMPH1_A1, 0x0 }, 334 { AUD_DEEMPH1_A1, 0x0 },
342 { AUD_DEEMPH1_B1, 0x0 }, 335 { AUD_DEEMPH1_B1, 0x0 },
343 { AUD_OUT0_SEL, 0x3F }, 336 { AUD_OUT0_SEL, 0x3F },
344 { AUD_OUT1_SEL, 0x3F }, 337 { AUD_OUT1_SEL, 0x3F },
345 { AUD_DMD_RA_DDS, 0x0F5C285 }, 338 { AUD_DMD_RA_DDS, 0x0F5C285 },
346 { AUD_PLL_INT, 0x1E }, 339 { AUD_PLL_INT, 0x1E },
347 { AUD_PLL_DDS, 0x0 }, 340 { AUD_PLL_DDS, 0x0 },
348 { AUD_PLL_FRAC, 0x0E542 }, 341 { AUD_PLL_FRAC, 0x0E542 },
349 342
350 // setup QAM registers 343 // setup QAM registers
351 { AUD_RATE_ADJ1, 0x00000100 }, 344 { AUD_RATE_ADJ1, 0x00000100 },
352 { AUD_RATE_ADJ2, 0x00000200 }, 345 { AUD_RATE_ADJ2, 0x00000200 },
353 { AUD_RATE_ADJ3, 0x00000300 }, 346 { AUD_RATE_ADJ3, 0x00000300 },
354 { AUD_RATE_ADJ4, 0x00000400 }, 347 { AUD_RATE_ADJ4, 0x00000400 },
355 { AUD_RATE_ADJ5, 0x00000500 }, 348 { AUD_RATE_ADJ5, 0x00000500 },
356 { AUD_RATE_THRES_DMD, 0x000000C0 }, 349 { AUD_RATE_THRES_DMD, 0x000000C0 },
357 { /* end of list */ }, 350 { /* end of list */ },
358 }; 351 };
359
360 static const struct rlist nicam_l[] = {
361 // setup QAM registers
362 { AUD_RATE_ADJ1, 0x00000060 },
363 { AUD_RATE_ADJ2, 0x000000F9 },
364 { AUD_RATE_ADJ3, 0x000001CC },
365 { AUD_RATE_ADJ4, 0x000002B3 },
366 { AUD_RATE_ADJ5, 0x00000726 },
367 { AUD_DEEMPHDENOM1_R, 0x0000F3D0 },
368 { AUD_DEEMPHDENOM2_R, 0x00000000 },
369 { AUD_ERRLOGPERIOD_R, 0x00000064 },
370 { AUD_ERRINTRPTTHSHLD1_R, 0x00000FFF },
371 { AUD_ERRINTRPTTHSHLD2_R, 0x0000001F },
372 { AUD_ERRINTRPTTHSHLD3_R, 0x0000000F },
373 { AUD_POLYPH80SCALEFAC, 0x00000003 },
374 { AUD_DMD_RA_DDS, 0x00C00000 },
375 { AUD_PLL_INT, 0x0000001E },
376 { AUD_PLL_DDS, 0x00000000 },
377 { AUD_PLL_FRAC, 0x0000E542 },
378 { AUD_START_TIMER, 0x00000000 },
379 { AUD_DEEMPHNUMER1_R, 0x000353DE },
380 { AUD_DEEMPHNUMER2_R, 0x000001B1 },
381 { AUD_PDF_DDS_CNST_BYTE2, 0x06 },
382 { AUD_PDF_DDS_CNST_BYTE1, 0x82 },
383 { AUD_QAM_MODE, 0x05 },
384 { AUD_PDF_DDS_CNST_BYTE0, 0x12 },
385 { AUD_PHACC_FREQ_8MSB, 0x34 },
386 { AUD_PHACC_FREQ_8LSB, 0x4C },
387 { AUD_DEEMPHGAIN_R, 0x00006680 },
388 { AUD_RATE_THRES_DMD, 0x000000C0 },
389 { /* end of list */ },
390 } ;
391 dprintk("%s (status: devel), stereo : %d\n",__FUNCTION__,stereo);
392
393 if (!stereo) {
394 /* AM mono sound */
395 set_audio_start(core, 0x0004,
396 0x100c /* FIXME again */);
397 set_audio_registers(core, nicam_l_mono);
398 } else {
399 set_audio_start(core, 0x0010,
400 0x1924 /* FIXME again */);
401 set_audio_registers(core, nicam_l);
402 }
403 set_audio_finish(core);
404 352
353 static const struct rlist nicam_l[] = {
354 // setup QAM registers
355 { AUD_RATE_ADJ1, 0x00000060 },
356 { AUD_RATE_ADJ2, 0x000000F9 },
357 { AUD_RATE_ADJ3, 0x000001CC },
358 { AUD_RATE_ADJ4, 0x000002B3 },
359 { AUD_RATE_ADJ5, 0x00000726 },
360 { AUD_DEEMPHDENOM1_R, 0x0000F3D0 },
361 { AUD_DEEMPHDENOM2_R, 0x00000000 },
362 { AUD_ERRLOGPERIOD_R, 0x00000064 },
363 { AUD_ERRINTRPTTHSHLD1_R, 0x00000FFF },
364 { AUD_ERRINTRPTTHSHLD2_R, 0x0000001F },
365 { AUD_ERRINTRPTTHSHLD3_R, 0x0000000F },
366 { AUD_POLYPH80SCALEFAC, 0x00000003 },
367 { AUD_DMD_RA_DDS, 0x00C00000 },
368 { AUD_PLL_INT, 0x0000001E },
369 { AUD_PLL_DDS, 0x00000000 },
370 { AUD_PLL_FRAC, 0x0000E542 },
371 { AUD_START_TIMER, 0x00000000 },
372 { AUD_DEEMPHNUMER1_R, 0x000353DE },
373 { AUD_DEEMPHNUMER2_R, 0x000001B1 },
374 { AUD_PDF_DDS_CNST_BYTE2, 0x06 },
375 { AUD_PDF_DDS_CNST_BYTE1, 0x82 },
376 { AUD_QAM_MODE, 0x05 },
377 { AUD_PDF_DDS_CNST_BYTE0, 0x12 },
378 { AUD_PHACC_FREQ_8MSB, 0x34 },
379 { AUD_PHACC_FREQ_8LSB, 0x4C },
380 { AUD_DEEMPHGAIN_R, 0x00006680 },
381 { AUD_RATE_THRES_DMD, 0x000000C0 },
382 { /* end of list */ },
383 } ;
384 dprintk("%s (status: devel), stereo : %d\n",__FUNCTION__,stereo);
385
386 if (!stereo) {
387 /* AM Mono */
388 set_audio_start(core, SEL_A2);
389 set_audio_registers(core, nicam_l_mono);
390 set_audio_finish(core, EN_A2_FORCE_MONO1);
391 } else {
392 /* Nicam Stereo */
393 set_audio_start(core, SEL_NICAM);
394 set_audio_registers(core, nicam_l);
395 set_audio_finish(core, 0x1924); /* FIXME */
396 }
405} 397}
406 398
407static void set_audio_standard_PAL_I(struct cx88_core *core, int stereo) 399static void set_audio_standard_PAL_I(struct cx88_core *core, int stereo)
408{ 400{
409 static const struct rlist pal_i_fm_mono[] = { 401 static const struct rlist pal_i_fm_mono[] = {
410 {AUD_ERRLOGPERIOD_R, 0x00000064}, 402 {AUD_ERRLOGPERIOD_R, 0x00000064},
411 {AUD_ERRINTRPTTHSHLD1_R, 0x00000fff}, 403 {AUD_ERRINTRPTTHSHLD1_R, 0x00000fff},
412 {AUD_ERRINTRPTTHSHLD2_R, 0x0000001f}, 404 {AUD_ERRINTRPTTHSHLD2_R, 0x0000001f},
413 {AUD_ERRINTRPTTHSHLD3_R, 0x0000000f}, 405 {AUD_ERRINTRPTTHSHLD3_R, 0x0000000f},
414 {AUD_PDF_DDS_CNST_BYTE2, 0x06}, 406 {AUD_PDF_DDS_CNST_BYTE2, 0x06},
415 {AUD_PDF_DDS_CNST_BYTE1, 0x82}, 407 {AUD_PDF_DDS_CNST_BYTE1, 0x82},
416 {AUD_PDF_DDS_CNST_BYTE0, 0x12}, 408 {AUD_PDF_DDS_CNST_BYTE0, 0x12},
417 {AUD_QAM_MODE, 0x05}, 409 {AUD_QAM_MODE, 0x05},
418 {AUD_PHACC_FREQ_8MSB, 0x3a}, 410 {AUD_PHACC_FREQ_8MSB, 0x3a},
419 {AUD_PHACC_FREQ_8LSB, 0x93}, 411 {AUD_PHACC_FREQ_8LSB, 0x93},
420 {AUD_DMD_RA_DDS, 0x002a4f2f}, 412 {AUD_DMD_RA_DDS, 0x002a4f2f},
421 {AUD_PLL_INT, 0x0000001e}, 413 {AUD_PLL_INT, 0x0000001e},
422 {AUD_PLL_DDS, 0x00000004}, 414 {AUD_PLL_DDS, 0x00000004},
423 {AUD_PLL_FRAC, 0x0000e542}, 415 {AUD_PLL_FRAC, 0x0000e542},
424 {AUD_RATE_ADJ1, 0x00000100}, 416 {AUD_RATE_ADJ1, 0x00000100},
425 {AUD_RATE_ADJ2, 0x00000200}, 417 {AUD_RATE_ADJ2, 0x00000200},
426 {AUD_RATE_ADJ3, 0x00000300}, 418 {AUD_RATE_ADJ3, 0x00000300},
427 {AUD_RATE_ADJ4, 0x00000400}, 419 {AUD_RATE_ADJ4, 0x00000400},
428 {AUD_RATE_ADJ5, 0x00000500}, 420 {AUD_RATE_ADJ5, 0x00000500},
429 {AUD_THR_FR, 0x00000000}, 421 {AUD_THR_FR, 0x00000000},
430 {AUD_PILOT_BQD_1_K0, 0x0000755b}, 422 {AUD_PILOT_BQD_1_K0, 0x0000755b},
431 {AUD_PILOT_BQD_1_K1, 0x00551340}, 423 {AUD_PILOT_BQD_1_K1, 0x00551340},
432 {AUD_PILOT_BQD_1_K2, 0x006d30be}, 424 {AUD_PILOT_BQD_1_K2, 0x006d30be},
433 {AUD_PILOT_BQD_1_K3, 0xffd394af}, 425 {AUD_PILOT_BQD_1_K3, 0xffd394af},
434 {AUD_PILOT_BQD_1_K4, 0x00400000}, 426 {AUD_PILOT_BQD_1_K4, 0x00400000},
435 {AUD_PILOT_BQD_2_K0, 0x00040000}, 427 {AUD_PILOT_BQD_2_K0, 0x00040000},
436 {AUD_PILOT_BQD_2_K1, 0x002a4841}, 428 {AUD_PILOT_BQD_2_K1, 0x002a4841},
437 {AUD_PILOT_BQD_2_K2, 0x00400000}, 429 {AUD_PILOT_BQD_2_K2, 0x00400000},
438 {AUD_PILOT_BQD_2_K3, 0x00000000}, 430 {AUD_PILOT_BQD_2_K3, 0x00000000},
439 {AUD_PILOT_BQD_2_K4, 0x00000000}, 431 {AUD_PILOT_BQD_2_K4, 0x00000000},
440 {AUD_MODE_CHG_TIMER, 0x00000060}, 432 {AUD_MODE_CHG_TIMER, 0x00000060},
441 {AUD_AFE_12DB_EN, 0x00000001}, 433 {AUD_AFE_12DB_EN, 0x00000001},
442 {AAGC_HYST, 0x0000000a}, 434 {AAGC_HYST, 0x0000000a},
443 {AUD_CORDIC_SHIFT_0, 0x00000007}, 435 {AUD_CORDIC_SHIFT_0, 0x00000007},
444 {AUD_CORDIC_SHIFT_1, 0x00000007}, 436 {AUD_CORDIC_SHIFT_1, 0x00000007},
445 {AUD_C1_UP_THR, 0x00007000}, 437 {AUD_C1_UP_THR, 0x00007000},
446 {AUD_C1_LO_THR, 0x00005400}, 438 {AUD_C1_LO_THR, 0x00005400},
447 {AUD_C2_UP_THR, 0x00005400}, 439 {AUD_C2_UP_THR, 0x00005400},
448 {AUD_C2_LO_THR, 0x00003000}, 440 {AUD_C2_LO_THR, 0x00003000},
449 {AUD_DCOC_0_SRC, 0x0000001a}, 441 {AUD_DCOC_0_SRC, 0x0000001a},
450 {AUD_DCOC0_SHIFT, 0x00000000}, 442 {AUD_DCOC0_SHIFT, 0x00000000},
451 {AUD_DCOC_0_SHIFT_IN0, 0x0000000a}, 443 {AUD_DCOC_0_SHIFT_IN0, 0x0000000a},
452 {AUD_DCOC_0_SHIFT_IN1, 0x00000008}, 444 {AUD_DCOC_0_SHIFT_IN1, 0x00000008},
453 {AUD_DCOC_PASS_IN, 0x00000003}, 445 {AUD_DCOC_PASS_IN, 0x00000003},
454 {AUD_IIR3_0_SEL, 0x00000021}, 446 {AUD_IIR3_0_SEL, 0x00000021},
455 {AUD_DN2_AFC, 0x00000002}, 447 {AUD_DN2_AFC, 0x00000002},
456 {AUD_DCOC_1_SRC, 0x0000001b}, 448 {AUD_DCOC_1_SRC, 0x0000001b},
457 {AUD_DCOC1_SHIFT, 0x00000000}, 449 {AUD_DCOC1_SHIFT, 0x00000000},
458 {AUD_DCOC_1_SHIFT_IN0, 0x0000000a}, 450 {AUD_DCOC_1_SHIFT_IN0, 0x0000000a},
459 {AUD_DCOC_1_SHIFT_IN1, 0x00000008}, 451 {AUD_DCOC_1_SHIFT_IN1, 0x00000008},
460 {AUD_IIR3_1_SEL, 0x00000023}, 452 {AUD_IIR3_1_SEL, 0x00000023},
461 {AUD_DN0_FREQ, 0x000035a3}, 453 {AUD_DN0_FREQ, 0x000035a3},
462 {AUD_DN2_FREQ, 0x000029c7}, 454 {AUD_DN2_FREQ, 0x000029c7},
463 {AUD_CRDC0_SRC_SEL, 0x00000511}, 455 {AUD_CRDC0_SRC_SEL, 0x00000511},
464 {AUD_IIR1_0_SEL, 0x00000001}, 456 {AUD_IIR1_0_SEL, 0x00000001},
465 {AUD_IIR1_1_SEL, 0x00000000}, 457 {AUD_IIR1_1_SEL, 0x00000000},
466 {AUD_IIR3_2_SEL, 0x00000003}, 458 {AUD_IIR3_2_SEL, 0x00000003},
467 {AUD_IIR3_2_SHIFT, 0x00000000}, 459 {AUD_IIR3_2_SHIFT, 0x00000000},
468 {AUD_IIR3_0_SEL, 0x00000002}, 460 {AUD_IIR3_0_SEL, 0x00000002},
469 {AUD_IIR2_0_SEL, 0x00000021}, 461 {AUD_IIR2_0_SEL, 0x00000021},
470 {AUD_IIR2_0_SHIFT, 0x00000002}, 462 {AUD_IIR2_0_SHIFT, 0x00000002},
471 {AUD_DEEMPH0_SRC_SEL, 0x0000000b}, 463 {AUD_DEEMPH0_SRC_SEL, 0x0000000b},
472 {AUD_DEEMPH1_SRC_SEL, 0x0000000b}, 464 {AUD_DEEMPH1_SRC_SEL, 0x0000000b},
473 {AUD_POLYPH80SCALEFAC, 0x00000001}, 465 {AUD_POLYPH80SCALEFAC, 0x00000001},
474 {AUD_START_TIMER, 0x00000000}, 466 {AUD_START_TIMER, 0x00000000},
475 { /* end of list */ }, 467 { /* end of list */ },
476 }; 468 };
477 469
478 static const struct rlist pal_i_nicam[] = { 470 static const struct rlist pal_i_nicam[] = {
479 { AUD_RATE_ADJ1, 0x00000010 }, 471 { AUD_RATE_ADJ1, 0x00000010 },
480 { AUD_RATE_ADJ2, 0x00000040 }, 472 { AUD_RATE_ADJ2, 0x00000040 },
481 { AUD_RATE_ADJ3, 0x00000100 }, 473 { AUD_RATE_ADJ3, 0x00000100 },
482 { AUD_RATE_ADJ4, 0x00000400 }, 474 { AUD_RATE_ADJ4, 0x00000400 },
483 { AUD_RATE_ADJ5, 0x00001000 }, 475 { AUD_RATE_ADJ5, 0x00001000 },
484 // { AUD_DMD_RA_DDS, 0x00c0d5ce }, 476 // { AUD_DMD_RA_DDS, 0x00c0d5ce },
485 { AUD_DEEMPHGAIN_R, 0x000023c2 }, 477 { AUD_DEEMPHGAIN_R, 0x000023c2 },
486 { AUD_DEEMPHNUMER1_R, 0x0002a7bc }, 478 { AUD_DEEMPHNUMER1_R, 0x0002a7bc },
487 { AUD_DEEMPHNUMER2_R, 0x0003023e }, 479 { AUD_DEEMPHNUMER2_R, 0x0003023e },
488 { AUD_DEEMPHDENOM1_R, 0x0000f3d0 }, 480 { AUD_DEEMPHDENOM1_R, 0x0000f3d0 },
489 { AUD_DEEMPHDENOM2_R, 0x00000000 }, 481 { AUD_DEEMPHDENOM2_R, 0x00000000 },
490 { AUD_DEEMPHDENOM2_R, 0x00000000 }, 482 { AUD_DEEMPHDENOM2_R, 0x00000000 },
491 { AUD_ERRLOGPERIOD_R, 0x00000fff }, 483 { AUD_ERRLOGPERIOD_R, 0x00000fff },
492 { AUD_ERRINTRPTTHSHLD1_R, 0x000003ff }, 484 { AUD_ERRINTRPTTHSHLD1_R, 0x000003ff },
493 { AUD_ERRINTRPTTHSHLD2_R, 0x000000ff }, 485 { AUD_ERRINTRPTTHSHLD2_R, 0x000000ff },
494 { AUD_ERRINTRPTTHSHLD3_R, 0x0000003f }, 486 { AUD_ERRINTRPTTHSHLD3_R, 0x0000003f },
495 { AUD_POLYPH80SCALEFAC, 0x00000003 }, 487 { AUD_POLYPH80SCALEFAC, 0x00000003 },
496 { AUD_PDF_DDS_CNST_BYTE2, 0x06 }, 488 { AUD_PDF_DDS_CNST_BYTE2, 0x06 },
497 { AUD_PDF_DDS_CNST_BYTE1, 0x82 }, 489 { AUD_PDF_DDS_CNST_BYTE1, 0x82 },
498 { AUD_PDF_DDS_CNST_BYTE0, 0x16 }, 490 { AUD_PDF_DDS_CNST_BYTE0, 0x16 },
499 { AUD_QAM_MODE, 0x05 }, 491 { AUD_QAM_MODE, 0x05 },
500 { AUD_PDF_DDS_CNST_BYTE0, 0x12 }, 492 { AUD_PDF_DDS_CNST_BYTE0, 0x12 },
501 { AUD_PHACC_FREQ_8MSB, 0x3a }, 493 { AUD_PHACC_FREQ_8MSB, 0x3a },
502 { AUD_PHACC_FREQ_8LSB, 0x93 }, 494 { AUD_PHACC_FREQ_8LSB, 0x93 },
503 { /* end of list */ }, 495 { /* end of list */ },
504 }; 496 };
505 497
506 dprintk("%s (status: devel), stereo : %d\n",__FUNCTION__,stereo); 498 dprintk("%s (status: devel), stereo : %d\n",__FUNCTION__,stereo);
507 499
508 if (!stereo) { 500 if (!stereo) {
509 // FM mono 501 /* FM Mono */
510 set_audio_start(core, 0x0004, EN_DMTRX_SUMDIFF | EN_A2_FORCE_MONO1); 502 set_audio_start(core, SEL_A2);
511 set_audio_registers(core, pal_i_fm_mono); 503 set_audio_registers(core, pal_i_fm_mono);
512 } else { 504 set_audio_finish(core, EN_DMTRX_SUMDIFF | EN_A2_FORCE_MONO1);
513 // Nicam Stereo 505 } else {
514 set_audio_start(core, 0x0010, EN_DMTRX_LR | EN_DMTRX_BYPASS | EN_NICAM_AUTO_STEREO); 506 /* Nicam Stereo */
507 set_audio_start(core, SEL_NICAM);
515 set_audio_registers(core, pal_i_nicam); 508 set_audio_registers(core, pal_i_nicam);
516 } 509 set_audio_finish(core, EN_DMTRX_LR | EN_DMTRX_BYPASS | EN_NICAM_AUTO_STEREO);
517 set_audio_finish(core); 510 }
518} 511}
519 512
520static void set_audio_standard_A2(struct cx88_core *core) 513static void set_audio_standard_A2(struct cx88_core *core, u32 mode)
521{ 514{
522 /* from dscaler cvs */
523 static const struct rlist a2_common[] = { 515 static const struct rlist a2_common[] = {
524 { AUD_PDF_DDS_CNST_BYTE2, 0x06 }, 516 {AUD_ERRLOGPERIOD_R, 0x00000064},
525 { AUD_PDF_DDS_CNST_BYTE1, 0x82 }, 517 {AUD_ERRINTRPTTHSHLD1_R, 0x00000fff},
526 { AUD_PDF_DDS_CNST_BYTE0, 0x12 }, 518 {AUD_ERRINTRPTTHSHLD2_R, 0x0000001f},
527 { AUD_QAM_MODE, 0x05 }, 519 {AUD_ERRINTRPTTHSHLD3_R, 0x0000000f},
528 { AUD_PHACC_FREQ_8MSB, 0x34 }, 520 {AUD_PDF_DDS_CNST_BYTE2, 0x06},
529 { AUD_PHACC_FREQ_8LSB, 0x4c }, 521 {AUD_PDF_DDS_CNST_BYTE1, 0x82},
530 522 {AUD_PDF_DDS_CNST_BYTE0, 0x12},
531 { AUD_RATE_ADJ1, 0x00001000 }, 523 {AUD_QAM_MODE, 0x05},
532 { AUD_RATE_ADJ2, 0x00002000 }, 524 {AUD_PHACC_FREQ_8MSB, 0x34},
533 { AUD_RATE_ADJ3, 0x00003000 }, 525 {AUD_PHACC_FREQ_8LSB, 0x4c},
534 { AUD_RATE_ADJ4, 0x00004000 }, 526 {AUD_RATE_ADJ1, 0x00000100},
535 { AUD_RATE_ADJ5, 0x00005000 }, 527 {AUD_RATE_ADJ2, 0x00000200},
536 { AUD_THR_FR, 0x00000000 }, 528 {AUD_RATE_ADJ3, 0x00000300},
537 { AAGC_HYST, 0x0000001a }, 529 {AUD_RATE_ADJ4, 0x00000400},
538 { AUD_PILOT_BQD_1_K0, 0x0000755b }, 530 {AUD_RATE_ADJ5, 0x00000500},
539 { AUD_PILOT_BQD_1_K1, 0x00551340 }, 531 {AUD_THR_FR, 0x00000000},
540 { AUD_PILOT_BQD_1_K2, 0x006d30be }, 532 {AAGC_HYST, 0x0000001a},
541 { AUD_PILOT_BQD_1_K3, 0xffd394af }, 533 {AUD_PILOT_BQD_1_K0, 0x0000755b},
542 { AUD_PILOT_BQD_1_K4, 0x00400000 }, 534 {AUD_PILOT_BQD_1_K1, 0x00551340},
543 { AUD_PILOT_BQD_2_K0, 0x00040000 }, 535 {AUD_PILOT_BQD_1_K2, 0x006d30be},
544 { AUD_PILOT_BQD_2_K1, 0x002a4841 }, 536 {AUD_PILOT_BQD_1_K3, 0xffd394af},
545 { AUD_PILOT_BQD_2_K2, 0x00400000 }, 537 {AUD_PILOT_BQD_1_K4, 0x00400000},
546 { AUD_PILOT_BQD_2_K3, 0x00000000 }, 538 {AUD_PILOT_BQD_2_K0, 0x00040000},
547 { AUD_PILOT_BQD_2_K4, 0x00000000 }, 539 {AUD_PILOT_BQD_2_K1, 0x002a4841},
548 { AUD_MODE_CHG_TIMER, 0x00000040 }, 540 {AUD_PILOT_BQD_2_K2, 0x00400000},
549 { AUD_START_TIMER, 0x00000200 }, 541 {AUD_PILOT_BQD_2_K3, 0x00000000},
550 { AUD_AFE_12DB_EN, 0x00000000 }, 542 {AUD_PILOT_BQD_2_K4, 0x00000000},
551 { AUD_CORDIC_SHIFT_0, 0x00000007 }, 543 {AUD_MODE_CHG_TIMER, 0x00000040},
552 { AUD_CORDIC_SHIFT_1, 0x00000007 }, 544 {AUD_AFE_12DB_EN, 0x00000001},
553 { AUD_DEEMPH0_G0, 0x00000380 }, 545 {AUD_CORDIC_SHIFT_0, 0x00000007},
554 { AUD_DEEMPH1_G0, 0x00000380 }, 546 {AUD_CORDIC_SHIFT_1, 0x00000007},
555 { AUD_DCOC_0_SRC, 0x0000001a }, 547 {AUD_DEEMPH0_G0, 0x00000380},
556 { AUD_DCOC0_SHIFT, 0x00000000 }, 548 {AUD_DEEMPH1_G0, 0x00000380},
557 { AUD_DCOC_0_SHIFT_IN0, 0x0000000a }, 549 {AUD_DCOC_0_SRC, 0x0000001a},
558 { AUD_DCOC_0_SHIFT_IN1, 0x00000008 }, 550 {AUD_DCOC0_SHIFT, 0x00000000},
559 { AUD_DCOC_PASS_IN, 0x00000003 }, 551 {AUD_DCOC_0_SHIFT_IN0, 0x0000000a},
560 { AUD_IIR3_0_SEL, 0x00000021 }, 552 {AUD_DCOC_0_SHIFT_IN1, 0x00000008},
561 { AUD_DN2_AFC, 0x00000002 }, 553 {AUD_DCOC_PASS_IN, 0x00000003},
562 { AUD_DCOC_1_SRC, 0x0000001b }, 554 {AUD_IIR3_0_SEL, 0x00000021},
563 { AUD_DCOC1_SHIFT, 0x00000000 }, 555 {AUD_DN2_AFC, 0x00000002},
564 { AUD_DCOC_1_SHIFT_IN0, 0x0000000a }, 556 {AUD_DCOC_1_SRC, 0x0000001b},
565 { AUD_DCOC_1_SHIFT_IN1, 0x00000008 }, 557 {AUD_DCOC1_SHIFT, 0x00000000},
566 { AUD_IIR3_1_SEL, 0x00000023 }, 558 {AUD_DCOC_1_SHIFT_IN0, 0x0000000a},
567 { AUD_RDSI_SEL, 0x00000017 }, 559 {AUD_DCOC_1_SHIFT_IN1, 0x00000008},
568 { AUD_RDSI_SHIFT, 0x00000000 }, 560 {AUD_IIR3_1_SEL, 0x00000023},
569 { AUD_RDSQ_SEL, 0x00000017 }, 561 {AUD_RDSI_SEL, 0x00000017},
570 { AUD_RDSQ_SHIFT, 0x00000000 }, 562 {AUD_RDSI_SHIFT, 0x00000000},
571 { AUD_POLYPH80SCALEFAC, 0x00000001 }, 563 {AUD_RDSQ_SEL, 0x00000017},
564 {AUD_RDSQ_SHIFT, 0x00000000},
565 {AUD_PLL_INT, 0x0000001e},
566 {AUD_PLL_DDS, 0x00000000},
567 {AUD_PLL_FRAC, 0x0000e542},
568 {AUD_POLYPH80SCALEFAC, 0x00000001},
569 {AUD_START_TIMER, 0x00000000},
570 { /* end of list */ },
571 };
572 572
573 static const struct rlist a2_bg[] = {
574 {AUD_DMD_RA_DDS, 0x002a4f2f},
575 {AUD_C1_UP_THR, 0x00007000},
576 {AUD_C1_LO_THR, 0x00005400},
577 {AUD_C2_UP_THR, 0x00005400},
578 {AUD_C2_LO_THR, 0x00003000},
573 { /* end of list */ }, 579 { /* end of list */ },
574 }; 580 };
575 581
576 static const struct rlist a2_table1[] = { 582 static const struct rlist a2_dk[] = {
577 // PAL-BG 583 {AUD_DMD_RA_DDS, 0x002a4f2f},
578 { AUD_DMD_RA_DDS, 0x002a73bd }, 584 {AUD_C1_UP_THR, 0x00007000},
579 { AUD_C1_UP_THR, 0x00007000 }, 585 {AUD_C1_LO_THR, 0x00005400},
580 { AUD_C1_LO_THR, 0x00005400 }, 586 {AUD_C2_UP_THR, 0x00005400},
581 { AUD_C2_UP_THR, 0x00005400 }, 587 {AUD_C2_LO_THR, 0x00003000},
582 { AUD_C2_LO_THR, 0x00003000 }, 588 {AUD_DN0_FREQ, 0x00003a1c},
589 {AUD_DN2_FREQ, 0x0000d2e0},
583 { /* end of list */ }, 590 { /* end of list */ },
584 }; 591 };
585 static const struct rlist a2_table2[] = { 592/* unknown, probably NTSC-M */
586 // PAL-DK 593 static const struct rlist a2_m[] = {
587 { AUD_DMD_RA_DDS, 0x002a73bd }, 594 {AUD_DMD_RA_DDS, 0x002a0425},
588 { AUD_C1_UP_THR, 0x00007000 }, 595 {AUD_C1_UP_THR, 0x00003c00},
589 { AUD_C1_LO_THR, 0x00005400 }, 596 {AUD_C1_LO_THR, 0x00003000},
590 { AUD_C2_UP_THR, 0x00005400 }, 597 {AUD_C2_UP_THR, 0x00006000},
591 { AUD_C2_LO_THR, 0x00003000 }, 598 {AUD_C2_LO_THR, 0x00003c00},
592 { AUD_DN0_FREQ, 0x00003a1c }, 599 {AUD_DEEMPH0_A0, 0x00007a80},
593 { AUD_DN2_FREQ, 0x0000d2e0 }, 600 {AUD_DEEMPH1_A0, 0x00007a80},
601 {AUD_DEEMPH0_G0, 0x00001200},
602 {AUD_DEEMPH1_G0, 0x00001200},
603 {AUD_DN0_FREQ, 0x0000283b},
604 {AUD_DN1_FREQ, 0x00003418},
605 {AUD_DN2_FREQ, 0x000029c7},
606 {AUD_POLY0_DDS_CONSTANT, 0x000a7540},
594 { /* end of list */ }, 607 { /* end of list */ },
595 }; 608 };
596 static const struct rlist a2_table3[] = { 609
597 // unknown, probably NTSC-M 610 static const struct rlist a2_deemph50[] = {
598 { AUD_DMD_RA_DDS, 0x002a2873 }, 611 {AUD_DEEMPH0_G0, 0x00000380},
599 { AUD_C1_UP_THR, 0x00003c00 }, 612 {AUD_DEEMPH1_G0, 0x00000380},
600 { AUD_C1_LO_THR, 0x00003000 }, 613 {AUD_DEEMPHGAIN_R, 0x000011e1},
601 { AUD_C2_UP_THR, 0x00006000 }, 614 {AUD_DEEMPHNUMER1_R, 0x0002a7bc},
602 { AUD_C2_LO_THR, 0x00003c00 }, 615 {AUD_DEEMPHNUMER2_R, 0x0003023c},
603 { AUD_DN0_FREQ, 0x00002836 }, 616 { /* end of list */ },
604 { AUD_DN1_FREQ, 0x00003418 }, 617 };
605 { AUD_DN2_FREQ, 0x000029c7 }, 618
606 { AUD_POLY0_DDS_CONSTANT, 0x000a7540 }, 619 static const struct rlist a2_deemph75[] = {
620 {AUD_DEEMPH0_G0, 0x00000480},
621 {AUD_DEEMPH1_G0, 0x00000480},
622 {AUD_DEEMPHGAIN_R, 0x00009000},
623 {AUD_DEEMPHNUMER1_R, 0x000353de},
624 {AUD_DEEMPHNUMER2_R, 0x000001b1},
607 { /* end of list */ }, 625 { /* end of list */ },
608 }; 626 };
609 627
610 set_audio_start(core, 0x0004, EN_DMTRX_SUMDIFF | EN_A2_AUTO_STEREO); 628 set_audio_start(core, SEL_A2);
611 set_audio_registers(core, a2_common); 629 set_audio_registers(core, a2_common);
612 switch (core->tvaudio) { 630 switch (core->tvaudio) {
613 case WW_A2_BG: 631 case WW_A2_BG:
614 dprintk("%s PAL-BG A2 (status: known-good)\n",__FUNCTION__); 632 dprintk("%s PAL-BG A2 (status: known-good)\n",__FUNCTION__);
615 set_audio_registers(core, a2_table1); 633 set_audio_registers(core, a2_bg);
634 set_audio_registers(core, a2_deemph50);
616 break; 635 break;
617 case WW_A2_DK: 636 case WW_A2_DK:
618 dprintk("%s PAL-DK A2 (status: known-good)\n",__FUNCTION__); 637 dprintk("%s PAL-DK A2 (status: known-good)\n",__FUNCTION__);
619 set_audio_registers(core, a2_table2); 638 set_audio_registers(core, a2_dk);
639 set_audio_registers(core, a2_deemph50);
620 break; 640 break;
621 case WW_A2_M: 641 case WW_A2_M:
622 dprintk("%s NTSC-M A2 (status: unknown)\n",__FUNCTION__); 642 dprintk("%s NTSC-M A2 (status: unknown)\n",__FUNCTION__);
623 set_audio_registers(core, a2_table3); 643 set_audio_registers(core, a2_m);
644 set_audio_registers(core, a2_deemph75);
624 break; 645 break;
625 }; 646 };
626 set_audio_finish(core); 647
648 mode |= EN_FMRADIO_EN_RDS | EN_DMTRX_SUMDIFF;
649 set_audio_finish(core, mode);
627} 650}
628 651
629static void set_audio_standard_EIAJ(struct cx88_core *core) 652static void set_audio_standard_EIAJ(struct cx88_core *core)
@@ -635,9 +658,9 @@ static void set_audio_standard_EIAJ(struct cx88_core *core)
635 }; 658 };
636 dprintk("%s (status: unknown)\n",__FUNCTION__); 659 dprintk("%s (status: unknown)\n",__FUNCTION__);
637 660
638 set_audio_start(core, 0x0002, EN_EIAJ_AUTO_STEREO); 661 set_audio_start(core, SEL_EIAJ);
639 set_audio_registers(core, eiaj); 662 set_audio_registers(core, eiaj);
640 set_audio_finish(core); 663 set_audio_finish(core, EN_EIAJ_AUTO_STEREO);
641} 664}
642 665
643static void set_audio_standard_FM(struct cx88_core *core, enum cx88_deemph_type deemph) 666static void set_audio_standard_FM(struct cx88_core *core, enum cx88_deemph_type deemph)
@@ -683,7 +706,7 @@ static void set_audio_standard_FM(struct cx88_core *core, enum cx88_deemph_type
683 }; 706 };
684 707
685 dprintk("%s (status: unknown)\n",__FUNCTION__); 708 dprintk("%s (status: unknown)\n",__FUNCTION__);
686 set_audio_start(core, 0x0020, EN_FMRADIO_AUTO_STEREO); 709 set_audio_start(core, SEL_FMRADIO);
687 710
688 switch (deemph) 711 switch (deemph)
689 { 712 {
@@ -700,7 +723,7 @@ static void set_audio_standard_FM(struct cx88_core *core, enum cx88_deemph_type
700 break; 723 break;
701 } 724 }
702 725
703 set_audio_finish(core); 726 set_audio_finish(core, EN_FMRADIO_AUTO_STEREO);
704} 727}
705 728
706/* ----------------------------------------------------------- */ 729/* ----------------------------------------------------------- */
@@ -709,7 +732,7 @@ void cx88_set_tvaudio(struct cx88_core *core)
709{ 732{
710 switch (core->tvaudio) { 733 switch (core->tvaudio) {
711 case WW_BTSC: 734 case WW_BTSC:
712 set_audio_standard_BTSC(core,0); 735 set_audio_standard_BTSC(core, 0, EN_BTSC_AUTO_STEREO);
713 break; 736 break;
714 case WW_NICAM_BGDKL: 737 case WW_NICAM_BGDKL:
715 set_audio_standard_NICAM_L(core,0); 738 set_audio_standard_NICAM_L(core,0);
@@ -720,7 +743,7 @@ void cx88_set_tvaudio(struct cx88_core *core)
720 case WW_A2_BG: 743 case WW_A2_BG:
721 case WW_A2_DK: 744 case WW_A2_DK:
722 case WW_A2_M: 745 case WW_A2_M:
723 set_audio_standard_A2(core); 746 set_audio_standard_A2(core, EN_A2_FORCE_MONO1);
724 break; 747 break;
725 case WW_EIAJ: 748 case WW_EIAJ:
726 set_audio_standard_EIAJ(core); 749 set_audio_standard_EIAJ(core);
@@ -734,7 +757,7 @@ void cx88_set_tvaudio(struct cx88_core *core)
734 case WW_NONE: 757 case WW_NONE:
735 default: 758 default:
736 printk("%s/0: unknown tv audio mode [%d]\n", 759 printk("%s/0: unknown tv audio mode [%d]\n",
737 core->name, core->tvaudio); 760 core->name, core->tvaudio);
738 break; 761 break;
739 } 762 }
740 return; 763 return;
@@ -769,6 +792,13 @@ void cx88_get_stereo(struct cx88_core *core, struct v4l2_tuner *t)
769 aud_ctl_names[cx_read(AUD_CTL) & 63]); 792 aud_ctl_names[cx_read(AUD_CTL) & 63]);
770 core->astat = reg; 793 core->astat = reg;
771 794
795/* TODO
796 Reading from AUD_STATUS is not enough
797 for auto-detecting sap/dual-fm/nicam.
798 Add some code here later.
799*/
800
801# if 0
772 t->capability = V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_SAP | 802 t->capability = V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_SAP |
773 V4L2_TUNER_CAP_LANG1 | V4L2_TUNER_CAP_LANG2; 803 V4L2_TUNER_CAP_LANG1 | V4L2_TUNER_CAP_LANG2;
774 t->rxsubchans = V4L2_TUNER_SUB_MONO; 804 t->rxsubchans = V4L2_TUNER_SUB_MONO;
@@ -779,7 +809,7 @@ void cx88_get_stereo(struct cx88_core *core, struct v4l2_tuner *t)
779 t->capability = V4L2_TUNER_CAP_STEREO | 809 t->capability = V4L2_TUNER_CAP_STEREO |
780 V4L2_TUNER_CAP_SAP; 810 V4L2_TUNER_CAP_SAP;
781 t->rxsubchans = V4L2_TUNER_SUB_STEREO; 811 t->rxsubchans = V4L2_TUNER_SUB_STEREO;
782 if (1 == pilot) { 812 if (1 == pilot) {
783 /* SAP */ 813 /* SAP */
784 t->rxsubchans |= V4L2_TUNER_SUB_SAP; 814 t->rxsubchans |= V4L2_TUNER_SUB_SAP;
785 } 815 }
@@ -787,13 +817,13 @@ void cx88_get_stereo(struct cx88_core *core, struct v4l2_tuner *t)
787 case WW_A2_BG: 817 case WW_A2_BG:
788 case WW_A2_DK: 818 case WW_A2_DK:
789 case WW_A2_M: 819 case WW_A2_M:
790 if (1 == pilot) { 820 if (1 == pilot) {
791 /* stereo */ 821 /* stereo */
792 t->rxsubchans = V4L2_TUNER_SUB_MONO | V4L2_TUNER_SUB_STEREO; 822 t->rxsubchans = V4L2_TUNER_SUB_MONO | V4L2_TUNER_SUB_STEREO;
793 if (0 == mode) 823 if (0 == mode)
794 t->audmode = V4L2_TUNER_MODE_STEREO; 824 t->audmode = V4L2_TUNER_MODE_STEREO;
795 } 825 }
796 if (2 == pilot) { 826 if (2 == pilot) {
797 /* dual language -- FIXME */ 827 /* dual language -- FIXME */
798 t->rxsubchans = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2; 828 t->rxsubchans = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
799 t->audmode = V4L2_TUNER_MODE_LANG1; 829 t->audmode = V4L2_TUNER_MODE_LANG1;
@@ -805,16 +835,17 @@ void cx88_get_stereo(struct cx88_core *core, struct v4l2_tuner *t)
805 t->rxsubchans |= V4L2_TUNER_SUB_STEREO; 835 t->rxsubchans |= V4L2_TUNER_SUB_STEREO;
806 } 836 }
807 break; 837 break;
808 case WW_SYSTEM_L_AM: 838 case WW_SYSTEM_L_AM:
809 if (0x0 == mode && !(cx_read(AUD_INIT) & 0x04)) { 839 if (0x0 == mode && !(cx_read(AUD_INIT) & 0x04)) {
810 t->audmode = V4L2_TUNER_MODE_STEREO; 840 t->audmode = V4L2_TUNER_MODE_STEREO;
811 t->rxsubchans |= V4L2_TUNER_SUB_STEREO; 841 t->rxsubchans |= V4L2_TUNER_SUB_STEREO;
812 } 842 }
813 break ; 843 break ;
814 default: 844 default:
815 /* nothing */ 845 /* nothing */
816 break; 846 break;
817 } 847 }
848# endif
818 return; 849 return;
819} 850}
820 851
@@ -835,16 +866,16 @@ void cx88_set_stereo(struct cx88_core *core, u32 mode, int manual)
835 case WW_BTSC: 866 case WW_BTSC:
836 switch (mode) { 867 switch (mode) {
837 case V4L2_TUNER_MODE_MONO: 868 case V4L2_TUNER_MODE_MONO:
838 ctl = EN_BTSC_FORCE_MONO; 869 set_audio_standard_BTSC(core, 0, EN_BTSC_FORCE_MONO);
839 mask = 0x3f;
840 break; 870 break;
841 case V4L2_TUNER_MODE_SAP: 871 case V4L2_TUNER_MODE_LANG1:
842 ctl = EN_BTSC_FORCE_SAP; 872 set_audio_standard_BTSC(core, 0, EN_BTSC_AUTO_STEREO);
843 mask = 0x3f; 873 break;
874 case V4L2_TUNER_MODE_LANG2:
875 set_audio_standard_BTSC(core, 1, EN_BTSC_FORCE_SAP);
844 break; 876 break;
845 case V4L2_TUNER_MODE_STEREO: 877 case V4L2_TUNER_MODE_STEREO:
846 ctl = EN_BTSC_AUTO_STEREO; 878 set_audio_standard_BTSC(core, 0, EN_BTSC_FORCE_STEREO);
847 mask = 0x3f;
848 break; 879 break;
849 } 880 }
850 break; 881 break;
@@ -854,16 +885,13 @@ void cx88_set_stereo(struct cx88_core *core, u32 mode, int manual)
854 switch (mode) { 885 switch (mode) {
855 case V4L2_TUNER_MODE_MONO: 886 case V4L2_TUNER_MODE_MONO:
856 case V4L2_TUNER_MODE_LANG1: 887 case V4L2_TUNER_MODE_LANG1:
857 ctl = EN_A2_FORCE_MONO1; 888 set_audio_standard_A2(core, EN_A2_FORCE_MONO1);
858 mask = 0x3f;
859 break; 889 break;
860 case V4L2_TUNER_MODE_LANG2: 890 case V4L2_TUNER_MODE_LANG2:
861 ctl = EN_A2_AUTO_MONO2; 891 set_audio_standard_A2(core, EN_A2_FORCE_MONO2);
862 mask = 0x3f;
863 break; 892 break;
864 case V4L2_TUNER_MODE_STEREO: 893 case V4L2_TUNER_MODE_STEREO:
865 ctl = EN_A2_AUTO_STEREO | EN_DMTRX_SUMR; 894 set_audio_standard_A2(core, EN_A2_FORCE_STEREO);
866 mask = 0x8bf;
867 break; 895 break;
868 } 896 }
869 break; 897 break;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 15:45:42 -0500