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authorMichael Krufky <mkrufky@m1k.net>2005-07-07 20:58:39 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2005-07-07 21:24:04 -0400
commitf1798495592c1bcd7871abdc1ef2985d65c34224 (patch)
tree3496ce6e2c6318fbd09b5d9cbfcb51e2ebd87cfa /drivers/media/video/cx88/cx88-mpeg.c
parent9ac4c158b0090462bc356b934024cf0c5d7c8526 (diff)
[PATCH] v4l: add DVB support for DViCO FusionHDTV3 Gold-Q
Add dvb support in v4l for DViCO FusionHDTV3 Gold-Q using lgdt3302 frontend. Signed-off-by: Mac Michaels <wmichaels1@earthlink.net> Signed-off-by: Michael Krufky <mkrufky@m1k.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'drivers/media/video/cx88/cx88-mpeg.c')
-rw-r--r--drivers/media/video/cx88/cx88-mpeg.c13
1 files changed, 9 insertions, 4 deletions
diff --git a/drivers/media/video/cx88/cx88-mpeg.c b/drivers/media/video/cx88/cx88-mpeg.c
index 9ade2ae91e9b..c5f4c595239d 100644
--- a/drivers/media/video/cx88/cx88-mpeg.c
+++ b/drivers/media/video/cx88/cx88-mpeg.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * $Id: cx88-mpeg.c,v 1.26 2005/06/03 13:31:51 mchehab Exp $ 2 * $Id: cx88-mpeg.c,v 1.28 2005/06/20 03:36:00 mkrufky Exp $
3 * 3 *
4 * Support for the mpeg transport stream transfers 4 * Support for the mpeg transport stream transfers
5 * PCI function #2 of the cx2388x. 5 * PCI function #2 of the cx2388x.
@@ -70,11 +70,16 @@ static int cx8802_start_dma(struct cx8802_dev *dev,
70 70
71 if (cx88_boards[core->board].dvb) { 71 if (cx88_boards[core->board].dvb) {
72 /* negedge driven & software reset */ 72 /* negedge driven & software reset */
73 cx_write(TS_GEN_CNTRL, 0x40); 73 cx_write(TS_GEN_CNTRL, 0x0040 | dev->ts_gen_cntrl);
74 udelay(100); 74 udelay(100);
75 cx_write(MO_PINMUX_IO, 0x00); 75 cx_write(MO_PINMUX_IO, 0x00);
76 cx_write(TS_HW_SOP_CNTRL,47<<16|188<<4|0x00); 76 if (core->board == CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q) {
77 cx_write(TS_SOP_STAT,0x00); 77 cx_write(TS_HW_SOP_CNTRL,0x47<<16 | 188<<4 | 0x00);
78 cx_write(TS_SOP_STAT, 0<<16 | 0<<14 | 1<<13 | 0<<12);
79 } else {
80 cx_write(TS_HW_SOP_CNTRL,47<<16|188<<4|0x00);
81 cx_write(TS_SOP_STAT,0x00);
82 }
78 cx_write(TS_GEN_CNTRL, dev->ts_gen_cntrl); 83 cx_write(TS_GEN_CNTRL, dev->ts_gen_cntrl);
79 udelay(100); 84 udelay(100);
80 } 85 }