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authorLinus Torvalds <torvalds@linux-foundation.org>2008-04-24 14:21:08 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-04-24 14:21:08 -0400
commitc328d54cd4ad120d76284e46dcca6c6cf996154a (patch)
tree104c023be66faa5fce6e0a56c0a6d13c62fd21e5 /drivers/media/video/cx23885
parent346ad4b7fe392571f19314f153db9151dbc1d82b (diff)
parentb0166ab3a6ae6d7af8d9a21a7836154963c69a11 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/v4l-dvb
* git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/v4l-dvb: (452 commits) V4L/DVB (7731): tuner-xc2028: fix signal strength calculus V4L/DVB (7730): tuner-xc2028: Fix SCODE load for MTS firmwares V4L/DVB (7729): Fix VIDIOCGAP corruption in ivtv V4L/DVB (7728): tea5761: bugzilla #10462: tea5761 autodetection code were broken V4L/DVB (7726): cx23885: Enable cx23417 support on the HVR1800 V4L/DVB (7725): cx23885: Add generic cx23417 hardware encoder support V4L/DVB (7723): pvrusb2: Clean up input selection list generation in V4L interface V4L/DVB (7722): pvrusb2: Implement FM radio support for Gotview USB2.0 DVD 2 V4L/DVB (7721): pvrusb2: Restructure cx23416 firmware loading to have a common exit point V4L/DVB (7720): pvrusb2: Fix bad error code on cx23416 firmware load failure V4L/DVB (7719): pvrusb2: Implement input selection enforcement V4L/DVB (7718): pvrusb2-dvb: update Kbuild selections V4L/DVB (7717): pvrusb2-dvb: add DVB-T support for Hauppauge pvrusb2 model 73xxx V4L/DVB (7716): pvrusb2: clean up global functions V4L/DVB (7715): pvrusb2: Clean out all use of __FUNCTION__ V4L/DVB (7714): pvrusb2: Fix hang on module removal V4L/DVB (7713): pvrusb2: Implement cleaner DVB kernel thread shutdown V4L/DVB (7712): pvrusb2: Close connect/disconnect race V4L/DVB (7711): pvrusb2: Fix race on module unload V4L/DVB (7710): pvrusb2: Implement critical digital streaming quirk for onair devices ...
Diffstat (limited to 'drivers/media/video/cx23885')
-rw-r--r--drivers/media/video/cx23885/Kconfig2
-rw-r--r--drivers/media/video/cx23885/Makefile2
-rw-r--r--drivers/media/video/cx23885/cx23885-417.c1764
-rw-r--r--drivers/media/video/cx23885/cx23885-cards.c116
-rw-r--r--drivers/media/video/cx23885/cx23885-core.c310
-rw-r--r--drivers/media/video/cx23885/cx23885-dvb.c172
-rw-r--r--drivers/media/video/cx23885/cx23885-i2c.c46
-rw-r--r--drivers/media/video/cx23885/cx23885-video.c58
-rw-r--r--drivers/media/video/cx23885/cx23885.h27
9 files changed, 2359 insertions, 138 deletions
diff --git a/drivers/media/video/cx23885/Kconfig b/drivers/media/video/cx23885/Kconfig
index 1fd326fe4113..ca5fbce3a909 100644
--- a/drivers/media/video/cx23885/Kconfig
+++ b/drivers/media/video/cx23885/Kconfig
@@ -8,6 +8,7 @@ config VIDEO_CX23885
8 select VIDEO_TVEEPROM 8 select VIDEO_TVEEPROM
9 select VIDEO_IR 9 select VIDEO_IR
10 select VIDEOBUF_DVB 10 select VIDEOBUF_DVB
11 select VIDEO_CX25840
11 select DVB_TUNER_MT2131 if !DVB_FE_CUSTOMISE 12 select DVB_TUNER_MT2131 if !DVB_FE_CUSTOMISE
12 select DVB_S5H1409 if !DVB_FE_CUSTOMISE 13 select DVB_S5H1409 if !DVB_FE_CUSTOMISE
13 select DVB_LGDT330X if !DVB_FE_CUSTOMISE 14 select DVB_LGDT330X if !DVB_FE_CUSTOMISE
@@ -16,6 +17,7 @@ config VIDEO_CX23885
16 select TUNER_TDA8290 if !DVB_FE_CUSTOMIZE 17 select TUNER_TDA8290 if !DVB_FE_CUSTOMIZE
17 select DVB_TDA18271 if !DVB_FE_CUSTOMIZE 18 select DVB_TDA18271 if !DVB_FE_CUSTOMIZE
18 select DVB_TUNER_XC5000 if !DVB_FE_CUSTOMIZE 19 select DVB_TUNER_XC5000 if !DVB_FE_CUSTOMIZE
20 select DVB_TDA10048 if !DVB_FE_CUSTOMIZE
19 ---help--- 21 ---help---
20 This is a video4linux driver for Conexant 23885 based 22 This is a video4linux driver for Conexant 23885 based
21 TV cards. 23 TV cards.
diff --git a/drivers/media/video/cx23885/Makefile b/drivers/media/video/cx23885/Makefile
index 32c90be50602..d7b0721af062 100644
--- a/drivers/media/video/cx23885/Makefile
+++ b/drivers/media/video/cx23885/Makefile
@@ -1,4 +1,4 @@
1cx23885-objs := cx23885-cards.o cx23885-video.o cx23885-vbi.o cx23885-core.o cx23885-i2c.o cx23885-dvb.o 1cx23885-objs := cx23885-cards.o cx23885-video.o cx23885-vbi.o cx23885-core.o cx23885-i2c.o cx23885-dvb.o cx23885-417.o
2 2
3obj-$(CONFIG_VIDEO_CX23885) += cx23885.o 3obj-$(CONFIG_VIDEO_CX23885) += cx23885.o
4 4
diff --git a/drivers/media/video/cx23885/cx23885-417.c b/drivers/media/video/cx23885/cx23885-417.c
new file mode 100644
index 000000000000..acdd3b6b3e7c
--- /dev/null
+++ b/drivers/media/video/cx23885/cx23885-417.c
@@ -0,0 +1,1764 @@
1/*
2 *
3 * Support for a cx23417 mpeg encoder via cx23885 host port.
4 *
5 * (c) 2004 Jelle Foks <jelle@foks.8m.com>
6 * (c) 2004 Gerd Knorr <kraxel@bytesex.org>
7 * (c) 2008 Steven Toth <stoth@hauppauge.com>
8 * - CX23885/7/8 support
9 *
10 * Includes parts from the ivtv driver( http://ivtv.sourceforge.net/),
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/init.h>
30#include <linux/fs.h>
31#include <linux/delay.h>
32#include <linux/device.h>
33#include <linux/firmware.h>
34#include <media/v4l2-common.h>
35#include <media/cx2341x.h>
36
37#include "cx23885.h"
38#include "media/cx2341x.h"
39
40#define CX23885_FIRM_IMAGE_SIZE 376836
41#define CX23885_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw"
42
43static unsigned int mpegbufs = 32;
44module_param(mpegbufs, int, 0644);
45MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32");
46static unsigned int mpeglines = 32;
47module_param(mpeglines, int, 0644);
48MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32");
49static unsigned int mpeglinesize = 512;
50module_param(mpeglinesize, int, 0644);
51MODULE_PARM_DESC(mpeglinesize,
52 "number of bytes in each line of an MPEG buffer, range 512-1024");
53
54static unsigned int v4l_debug;
55module_param(v4l_debug, int, 0644);
56MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages");
57
58#define dprintk(level, fmt, arg...)\
59 do { if (v4l_debug >= level) \
60 printk(KERN_DEBUG "%s: " fmt, dev->name , ## arg);\
61 } while (0)
62
63static struct cx23885_tvnorm cx23885_tvnorms[] = {
64 {
65 .name = "NTSC-M",
66 .id = V4L2_STD_NTSC_M,
67 }, {
68 .name = "NTSC-JP",
69 .id = V4L2_STD_NTSC_M_JP,
70 }, {
71 .name = "PAL-BG",
72 .id = V4L2_STD_PAL_BG,
73 }, {
74 .name = "PAL-DK",
75 .id = V4L2_STD_PAL_DK,
76 }, {
77 .name = "PAL-I",
78 .id = V4L2_STD_PAL_I,
79 }, {
80 .name = "PAL-M",
81 .id = V4L2_STD_PAL_M,
82 }, {
83 .name = "PAL-N",
84 .id = V4L2_STD_PAL_N,
85 }, {
86 .name = "PAL-Nc",
87 .id = V4L2_STD_PAL_Nc,
88 }, {
89 .name = "PAL-60",
90 .id = V4L2_STD_PAL_60,
91 }, {
92 .name = "SECAM-L",
93 .id = V4L2_STD_SECAM_L,
94 }, {
95 .name = "SECAM-DK",
96 .id = V4L2_STD_SECAM_DK,
97 }
98};
99
100/* ------------------------------------------------------------------ */
101enum cx23885_capture_type {
102 CX23885_MPEG_CAPTURE,
103 CX23885_RAW_CAPTURE,
104 CX23885_RAW_PASSTHRU_CAPTURE
105};
106enum cx23885_capture_bits {
107 CX23885_RAW_BITS_NONE = 0x00,
108 CX23885_RAW_BITS_YUV_CAPTURE = 0x01,
109 CX23885_RAW_BITS_PCM_CAPTURE = 0x02,
110 CX23885_RAW_BITS_VBI_CAPTURE = 0x04,
111 CX23885_RAW_BITS_PASSTHRU_CAPTURE = 0x08,
112 CX23885_RAW_BITS_TO_HOST_CAPTURE = 0x10
113};
114enum cx23885_capture_end {
115 CX23885_END_AT_GOP, /* stop at the end of gop, generate irq */
116 CX23885_END_NOW, /* stop immediately, no irq */
117};
118enum cx23885_framerate {
119 CX23885_FRAMERATE_NTSC_30, /* NTSC: 30fps */
120 CX23885_FRAMERATE_PAL_25 /* PAL: 25fps */
121};
122enum cx23885_stream_port {
123 CX23885_OUTPUT_PORT_MEMORY,
124 CX23885_OUTPUT_PORT_STREAMING,
125 CX23885_OUTPUT_PORT_SERIAL
126};
127enum cx23885_data_xfer_status {
128 CX23885_MORE_BUFFERS_FOLLOW,
129 CX23885_LAST_BUFFER,
130};
131enum cx23885_picture_mask {
132 CX23885_PICTURE_MASK_NONE,
133 CX23885_PICTURE_MASK_I_FRAMES,
134 CX23885_PICTURE_MASK_I_P_FRAMES = 0x3,
135 CX23885_PICTURE_MASK_ALL_FRAMES = 0x7,
136};
137enum cx23885_vbi_mode_bits {
138 CX23885_VBI_BITS_SLICED,
139 CX23885_VBI_BITS_RAW,
140};
141enum cx23885_vbi_insertion_bits {
142 CX23885_VBI_BITS_INSERT_IN_XTENSION_USR_DATA,
143 CX23885_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1,
144 CX23885_VBI_BITS_SEPARATE_STREAM = 0x2 << 1,
145 CX23885_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1,
146 CX23885_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1,
147};
148enum cx23885_dma_unit {
149 CX23885_DMA_BYTES,
150 CX23885_DMA_FRAMES,
151};
152enum cx23885_dma_transfer_status_bits {
153 CX23885_DMA_TRANSFER_BITS_DONE = 0x01,
154 CX23885_DMA_TRANSFER_BITS_ERROR = 0x04,
155 CX23885_DMA_TRANSFER_BITS_LL_ERROR = 0x10,
156};
157enum cx23885_pause {
158 CX23885_PAUSE_ENCODING,
159 CX23885_RESUME_ENCODING,
160};
161enum cx23885_copyright {
162 CX23885_COPYRIGHT_OFF,
163 CX23885_COPYRIGHT_ON,
164};
165enum cx23885_notification_type {
166 CX23885_NOTIFICATION_REFRESH,
167};
168enum cx23885_notification_status {
169 CX23885_NOTIFICATION_OFF,
170 CX23885_NOTIFICATION_ON,
171};
172enum cx23885_notification_mailbox {
173 CX23885_NOTIFICATION_NO_MAILBOX = -1,
174};
175enum cx23885_field1_lines {
176 CX23885_FIELD1_SAA7114 = 0x00EF, /* 239 */
177 CX23885_FIELD1_SAA7115 = 0x00F0, /* 240 */
178 CX23885_FIELD1_MICRONAS = 0x0105, /* 261 */
179};
180enum cx23885_field2_lines {
181 CX23885_FIELD2_SAA7114 = 0x00EF, /* 239 */
182 CX23885_FIELD2_SAA7115 = 0x00F0, /* 240 */
183 CX23885_FIELD2_MICRONAS = 0x0106, /* 262 */
184};
185enum cx23885_custom_data_type {
186 CX23885_CUSTOM_EXTENSION_USR_DATA,
187 CX23885_CUSTOM_PRIVATE_PACKET,
188};
189enum cx23885_mute {
190 CX23885_UNMUTE,
191 CX23885_MUTE,
192};
193enum cx23885_mute_video_mask {
194 CX23885_MUTE_VIDEO_V_MASK = 0x0000FF00,
195 CX23885_MUTE_VIDEO_U_MASK = 0x00FF0000,
196 CX23885_MUTE_VIDEO_Y_MASK = 0xFF000000,
197};
198enum cx23885_mute_video_shift {
199 CX23885_MUTE_VIDEO_V_SHIFT = 8,
200 CX23885_MUTE_VIDEO_U_SHIFT = 16,
201 CX23885_MUTE_VIDEO_Y_SHIFT = 24,
202};
203
204/* defines below are from ivtv-driver.h */
205#define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF
206
207/* Firmware API commands */
208#define IVTV_API_STD_TIMEOUT 500
209
210/* Registers */
211/* IVTV_REG_OFFSET */
212#define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8)
213#define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC)
214#define IVTV_REG_SPU (0x9050)
215#define IVTV_REG_HW_BLOCKS (0x9054)
216#define IVTV_REG_VPU (0x9058)
217#define IVTV_REG_APU (0xA064)
218
219/**** Bit definitions for MC417_RWD and MC417_OEN registers ***
220 bits 31-16
221+-----------+
222| Reserved |
223+-----------+
224 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
225+-------+-------+-------+-------+-------+-------+-------+-------+
226| MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0|
227+-------+-------+-------+-------+-------+-------+-------+-------+
228 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
229+-------+-------+-------+-------+-------+-------+-------+-------+
230|MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0|
231+-------+-------+-------+-------+-------+-------+-------+-------+
232***/
233#define MC417_MIWR 0x8000
234#define MC417_MIRD 0x4000
235#define MC417_MICS 0x2000
236#define MC417_MIRDY 0x1000
237#define MC417_MIADDR 0x0F00
238#define MC417_MIDATA 0x00FF
239
240/* MIADDR* nibble definitions */
241#define MCI_MEMORY_DATA_BYTE0 0x000
242#define MCI_MEMORY_DATA_BYTE1 0x100
243#define MCI_MEMORY_DATA_BYTE2 0x200
244#define MCI_MEMORY_DATA_BYTE3 0x300
245#define MCI_MEMORY_ADDRESS_BYTE2 0x400
246#define MCI_MEMORY_ADDRESS_BYTE1 0x500
247#define MCI_MEMORY_ADDRESS_BYTE0 0x600
248#define MCI_REGISTER_DATA_BYTE0 0x800
249#define MCI_REGISTER_DATA_BYTE1 0x900
250#define MCI_REGISTER_DATA_BYTE2 0xA00
251#define MCI_REGISTER_DATA_BYTE3 0xB00
252#define MCI_REGISTER_ADDRESS_BYTE0 0xC00
253#define MCI_REGISTER_ADDRESS_BYTE1 0xD00
254#define MCI_REGISTER_MODE 0xE00
255
256/* Read and write modes */
257#define MCI_MODE_REGISTER_READ 0
258#define MCI_MODE_REGISTER_WRITE 1
259#define MCI_MODE_MEMORY_READ 0
260#define MCI_MODE_MEMORY_WRITE 0x40
261
262/*** Bit definitions for MC417_CTL register ****
263 bits 31-6 bits 5-4 bit 3 bits 2-1 Bit 0
264+--------+-------------+--------+--------------+------------+
265|Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN|
266+--------+-------------+--------+--------------+------------+
267***/
268#define MC417_SPD_CTL(x) (((x) << 4) & 0x00000030)
269#define MC417_GPIO_SEL(x) (((x) << 1) & 0x00000006)
270#define MC417_UART_GPIO_EN 0x00000001
271
272/* Values for speed control */
273#define MC417_SPD_CTL_SLOW 0x1
274#define MC417_SPD_CTL_MEDIUM 0x0
275#define MC417_SPD_CTL_FAST 0x3 /* b'1x, but we use b'11 */
276
277/* Values for GPIO select */
278#define MC417_GPIO_SEL_GPIO3 0x3
279#define MC417_GPIO_SEL_GPIO2 0x2
280#define MC417_GPIO_SEL_GPIO1 0x1
281#define MC417_GPIO_SEL_GPIO0 0x0
282
283void cx23885_mc417_init(struct cx23885_dev *dev)
284{
285 u32 regval;
286
287 dprintk(2, "%s()\n", __func__);
288
289 /* Configure MC417_CTL register to defaults. */
290 regval = MC417_SPD_CTL(MC417_SPD_CTL_FAST) |
291 MC417_GPIO_SEL(MC417_GPIO_SEL_GPIO3) |
292 MC417_UART_GPIO_EN;
293 cx_write(MC417_CTL, regval);
294
295 /* Configure MC417_OEN to defaults. */
296 regval = MC417_MIRDY;
297 cx_write(MC417_OEN, regval);
298
299 /* Configure MC417_RWD to defaults. */
300 regval = MC417_MIWR | MC417_MIRD | MC417_MICS;
301 cx_write(MC417_RWD, regval);
302}
303
304static int mc417_wait_ready(struct cx23885_dev *dev)
305{
306 u32 mi_ready;
307 unsigned long timeout = jiffies + msecs_to_jiffies(1);
308
309 for (;;) {
310 mi_ready = cx_read(MC417_RWD) & MC417_MIRDY;
311 if (mi_ready != 0)
312 return 0;
313 if (time_after(jiffies, timeout))
314 return -1;
315 udelay(1);
316 }
317}
318
319static int mc417_register_write(struct cx23885_dev *dev, u16 address, u32 value)
320{
321 u32 regval;
322
323 /* Enable MC417 GPIO outputs except for MC417_MIRDY,
324 * which is an input.
325 */
326 cx_write(MC417_OEN, MC417_MIRDY);
327
328 /* Write data byte 0 */
329 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0 |
330 (value & 0x000000FF);
331 cx_write(MC417_RWD, regval);
332
333 /* Transition CS/WR to effect write transaction across bus. */
334 regval |= MC417_MICS | MC417_MIWR;
335 cx_write(MC417_RWD, regval);
336
337 /* Write data byte 1 */
338 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1 |
339 ((value >> 8) & 0x000000FF);
340 cx_write(MC417_RWD, regval);
341 regval |= MC417_MICS | MC417_MIWR;
342 cx_write(MC417_RWD, regval);
343
344 /* Write data byte 2 */
345 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2 |
346 ((value >> 16) & 0x000000FF);
347 cx_write(MC417_RWD, regval);
348 regval |= MC417_MICS | MC417_MIWR;
349 cx_write(MC417_RWD, regval);
350
351 /* Write data byte 3 */
352 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3 |
353 ((value >> 24) & 0x000000FF);
354 cx_write(MC417_RWD, regval);
355 regval |= MC417_MICS | MC417_MIWR;
356 cx_write(MC417_RWD, regval);
357
358 /* Write address byte 0 */
359 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 |
360 (address & 0xFF);
361 cx_write(MC417_RWD, regval);
362 regval |= MC417_MICS | MC417_MIWR;
363 cx_write(MC417_RWD, regval);
364
365 /* Write address byte 1 */
366 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 |
367 ((address >> 8) & 0xFF);
368 cx_write(MC417_RWD, regval);
369 regval |= MC417_MICS | MC417_MIWR;
370 cx_write(MC417_RWD, regval);
371
372 /* Indicate that this is a write. */
373 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE |
374 MCI_MODE_REGISTER_WRITE;
375 cx_write(MC417_RWD, regval);
376 regval |= MC417_MICS | MC417_MIWR;
377 cx_write(MC417_RWD, regval);
378
379 /* Wait for the trans to complete (MC417_MIRDY asserted). */
380 return mc417_wait_ready(dev);
381}
382
383static int mc417_register_read(struct cx23885_dev *dev, u16 address, u32 *value)
384{
385 int retval;
386 u32 regval;
387 u32 tempval;
388 u32 dataval;
389
390 /* Enable MC417 GPIO outputs except for MC417_MIRDY,
391 * which is an input.
392 */
393 cx_write(MC417_OEN, MC417_MIRDY);
394
395 /* Write address byte 0 */
396 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 |
397 ((address & 0x00FF));
398 cx_write(MC417_RWD, regval);
399 regval |= MC417_MICS | MC417_MIWR;
400 cx_write(MC417_RWD, regval);
401
402 /* Write address byte 1 */
403 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 |
404 ((address >> 8) & 0xFF);
405 cx_write(MC417_RWD, regval);
406 regval |= MC417_MICS | MC417_MIWR;
407 cx_write(MC417_RWD, regval);
408
409 /* Indicate that this is a register read. */
410 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE |
411 MCI_MODE_REGISTER_READ;
412 cx_write(MC417_RWD, regval);
413 regval |= MC417_MICS | MC417_MIWR;
414 cx_write(MC417_RWD, regval);
415
416 /* Wait for the trans to complete (MC417_MIRDY asserted). */
417 retval = mc417_wait_ready(dev);
418
419 /* switch the DAT0-7 GPIO[10:3] to input mode */
420 cx_write(MC417_OEN, MC417_MIRDY | MC417_MIDATA);
421
422 /* Read data byte 0 */
423 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0;
424 cx_write(MC417_RWD, regval);
425
426 /* Transition RD to effect read transaction across bus.
427 * Transtion 0x5000 -> 0x9000 correct (RD/RDY -> WR/RDY)?
428 * Should it be 0x9000 -> 0xF000 (also why is RDY being set, its
429 * input only...)
430 */
431 regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0;
432 cx_write(MC417_RWD, regval);
433
434 /* Collect byte */
435 tempval = cx_read(MC417_RWD);
436 dataval = tempval & 0x000000FF;
437
438 /* Bring CS and RD high. */
439 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
440 cx_write(MC417_RWD, regval);
441
442 /* Read data byte 1 */
443 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1;
444 cx_write(MC417_RWD, regval);
445 regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1;
446 cx_write(MC417_RWD, regval);
447 tempval = cx_read(MC417_RWD);
448 dataval |= ((tempval & 0x000000FF) << 8);
449 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
450 cx_write(MC417_RWD, regval);
451
452 /* Read data byte 2 */
453 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2;
454 cx_write(MC417_RWD, regval);
455 regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2;
456 cx_write(MC417_RWD, regval);
457 tempval = cx_read(MC417_RWD);
458 dataval |= ((tempval & 0x000000FF) << 16);
459 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
460 cx_write(MC417_RWD, regval);
461
462 /* Read data byte 3 */
463 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3;
464 cx_write(MC417_RWD, regval);
465 regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3;
466 cx_write(MC417_RWD, regval);
467 tempval = cx_read(MC417_RWD);
468 dataval |= ((tempval & 0x000000FF) << 24);
469 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
470 cx_write(MC417_RWD, regval);
471
472 *value = dataval;
473
474 return retval;
475}
476
477int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value)
478{
479 u32 regval;
480
481 /* Enable MC417 GPIO outputs except for MC417_MIRDY,
482 * which is an input.
483 */
484 cx_write(MC417_OEN, MC417_MIRDY);
485
486 /* Write data byte 0 */
487 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0 |
488 (value & 0x000000FF);
489 cx_write(MC417_RWD, regval);
490
491 /* Transition CS/WR to effect write transaction across bus. */
492 regval |= MC417_MICS | MC417_MIWR;
493 cx_write(MC417_RWD, regval);
494
495 /* Write data byte 1 */
496 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1 |
497 ((value >> 8) & 0x000000FF);
498 cx_write(MC417_RWD, regval);
499 regval |= MC417_MICS | MC417_MIWR;
500 cx_write(MC417_RWD, regval);
501
502 /* Write data byte 2 */
503 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2 |
504 ((value >> 16) & 0x000000FF);
505 cx_write(MC417_RWD, regval);
506 regval |= MC417_MICS | MC417_MIWR;
507 cx_write(MC417_RWD, regval);
508
509 /* Write data byte 3 */
510 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3 |
511 ((value >> 24) & 0x000000FF);
512 cx_write(MC417_RWD, regval);
513 regval |= MC417_MICS | MC417_MIWR;
514 cx_write(MC417_RWD, regval);
515
516 /* Write address byte 2 */
517 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 |
518 MCI_MODE_MEMORY_WRITE | ((address >> 16) & 0x3F);
519 cx_write(MC417_RWD, regval);
520 regval |= MC417_MICS | MC417_MIWR;
521 cx_write(MC417_RWD, regval);
522
523 /* Write address byte 1 */
524 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 |
525 ((address >> 8) & 0xFF);
526 cx_write(MC417_RWD, regval);
527 regval |= MC417_MICS | MC417_MIWR;
528 cx_write(MC417_RWD, regval);
529
530 /* Write address byte 0 */
531 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 |
532 (address & 0xFF);
533 cx_write(MC417_RWD, regval);
534 regval |= MC417_MICS | MC417_MIWR;
535 cx_write(MC417_RWD, regval);
536
537 /* Wait for the trans to complete (MC417_MIRDY asserted). */
538 return mc417_wait_ready(dev);
539}
540
541int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value)
542{
543 int retval;
544 u32 regval;
545 u32 tempval;
546 u32 dataval;
547
548 /* Enable MC417 GPIO outputs except for MC417_MIRDY,
549 * which is an input.
550 */
551 cx_write(MC417_OEN, MC417_MIRDY);
552
553 /* Write address byte 2 */
554 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 |
555 MCI_MODE_MEMORY_READ | ((address >> 16) & 0x3F);
556 cx_write(MC417_RWD, regval);
557 regval |= MC417_MICS | MC417_MIWR;
558 cx_write(MC417_RWD, regval);
559
560 /* Write address byte 1 */
561 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 |
562 ((address >> 8) & 0xFF);
563 cx_write(MC417_RWD, regval);
564 regval |= MC417_MICS | MC417_MIWR;
565 cx_write(MC417_RWD, regval);
566
567 /* Write address byte 0 */
568 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 |
569 (address & 0xFF);
570 cx_write(MC417_RWD, regval);
571 regval |= MC417_MICS | MC417_MIWR;
572 cx_write(MC417_RWD, regval);
573
574 /* Wait for the trans to complete (MC417_MIRDY asserted). */
575 retval = mc417_wait_ready(dev);
576
577 /* switch the DAT0-7 GPIO[10:3] to input mode */
578 cx_write(MC417_OEN, MC417_MIRDY | MC417_MIDATA);
579
580 /* Read data byte 3 */
581 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3;
582 cx_write(MC417_RWD, regval);
583
584 /* Transition RD to effect read transaction across bus. */
585 regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3;
586 cx_write(MC417_RWD, regval);
587
588 /* Collect byte */
589 tempval = cx_read(MC417_RWD);
590 dataval = ((tempval & 0x000000FF) << 24);
591
592 /* Bring CS and RD high. */
593 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
594 cx_write(MC417_RWD, regval);
595
596 /* Read data byte 2 */
597 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2;
598 cx_write(MC417_RWD, regval);
599 regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2;
600 cx_write(MC417_RWD, regval);
601 tempval = cx_read(MC417_RWD);
602 dataval |= ((tempval & 0x000000FF) << 16);
603 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
604 cx_write(MC417_RWD, regval);
605
606 /* Read data byte 1 */
607 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1;
608 cx_write(MC417_RWD, regval);
609 regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1;
610 cx_write(MC417_RWD, regval);
611 tempval = cx_read(MC417_RWD);
612 dataval |= ((tempval & 0x000000FF) << 8);
613 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
614 cx_write(MC417_RWD, regval);
615
616 /* Read data byte 0 */
617 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0;
618 cx_write(MC417_RWD, regval);
619 regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0;
620 cx_write(MC417_RWD, regval);
621 tempval = cx_read(MC417_RWD);
622 dataval |= (tempval & 0x000000FF);
623 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
624 cx_write(MC417_RWD, regval);
625
626 *value = dataval;
627
628 return retval;
629}
630
631/* ------------------------------------------------------------------ */
632
633/* MPEG encoder API */
634char *cmd_to_str(int cmd)
635{
636 switch (cmd) {
637 case CX2341X_ENC_PING_FW:
638 return "PING_FW";
639 case CX2341X_ENC_START_CAPTURE:
640 return "START_CAPTURE";
641 case CX2341X_ENC_STOP_CAPTURE:
642 return "STOP_CAPTURE";
643 case CX2341X_ENC_SET_AUDIO_ID:
644 return "SET_AUDIO_ID";
645 case CX2341X_ENC_SET_VIDEO_ID:
646 return "SET_VIDEO_ID";
647 case CX2341X_ENC_SET_PCR_ID:
648 return "SET_PCR_PID";
649 case CX2341X_ENC_SET_FRAME_RATE:
650 return "SET_FRAME_RATE";
651 case CX2341X_ENC_SET_FRAME_SIZE:
652 return "SET_FRAME_SIZE";
653 case CX2341X_ENC_SET_BIT_RATE:
654 return "SET_BIT_RATE";
655 case CX2341X_ENC_SET_GOP_PROPERTIES:
656 return "SET_GOP_PROPERTIES";
657 case CX2341X_ENC_SET_ASPECT_RATIO:
658 return "SET_ASPECT_RATIO";
659 case CX2341X_ENC_SET_DNR_FILTER_MODE:
660 return "SET_DNR_FILTER_PROPS";
661 case CX2341X_ENC_SET_DNR_FILTER_PROPS:
662 return "SET_DNR_FILTER_PROPS";
663 case CX2341X_ENC_SET_CORING_LEVELS:
664 return "SET_CORING_LEVELS";
665 case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
666 return "SET_SPATIAL_FILTER_TYPE";
667 case CX2341X_ENC_SET_VBI_LINE:
668 return "SET_VBI_LINE";
669 case CX2341X_ENC_SET_STREAM_TYPE:
670 return "SET_STREAM_TYPE";
671 case CX2341X_ENC_SET_OUTPUT_PORT:
672 return "SET_OUTPUT_PORT";
673 case CX2341X_ENC_SET_AUDIO_PROPERTIES:
674 return "SET_AUDIO_PROPERTIES";
675 case CX2341X_ENC_HALT_FW:
676 return "HALT_FW";
677 case CX2341X_ENC_GET_VERSION:
678 return "GET_VERSION";
679 case CX2341X_ENC_SET_GOP_CLOSURE:
680 return "SET_GOP_CLOSURE";
681 case CX2341X_ENC_GET_SEQ_END:
682 return "GET_SEQ_END";
683 case CX2341X_ENC_SET_PGM_INDEX_INFO:
684 return "SET_PGM_INDEX_INFO";
685 case CX2341X_ENC_SET_VBI_CONFIG:
686 return "SET_VBI_CONFIG";
687 case CX2341X_ENC_SET_DMA_BLOCK_SIZE:
688 return "SET_DMA_BLOCK_SIZE";
689 case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10:
690 return "GET_PREV_DMA_INFO_MB_10";
691 case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9:
692 return "GET_PREV_DMA_INFO_MB_9";
693 case CX2341X_ENC_SCHED_DMA_TO_HOST:
694 return "SCHED_DMA_TO_HOST";
695 case CX2341X_ENC_INITIALIZE_INPUT:
696 return "INITIALIZE_INPUT";
697 case CX2341X_ENC_SET_FRAME_DROP_RATE:
698 return "SET_FRAME_DROP_RATE";
699 case CX2341X_ENC_PAUSE_ENCODER:
700 return "PAUSE_ENCODER";
701 case CX2341X_ENC_REFRESH_INPUT:
702 return "REFRESH_INPUT";
703 case CX2341X_ENC_SET_COPYRIGHT:
704 return "SET_COPYRIGHT";
705 case CX2341X_ENC_SET_EVENT_NOTIFICATION:
706 return "SET_EVENT_NOTIFICATION";
707 case CX2341X_ENC_SET_NUM_VSYNC_LINES:
708 return "SET_NUM_VSYNC_LINES";
709 case CX2341X_ENC_SET_PLACEHOLDER:
710 return "SET_PLACEHOLDER";
711 case CX2341X_ENC_MUTE_VIDEO:
712 return "MUTE_VIDEO";
713 case CX2341X_ENC_MUTE_AUDIO:
714 return "MUTE_AUDIO";
715 case CX2341X_ENC_MISC:
716 return "MISC";
717 default:
718 return "UNKNOWN";
719 }
720}
721
722static int cx23885_mbox_func(void *priv,
723 u32 command,
724 int in,
725 int out,
726 u32 data[CX2341X_MBOX_MAX_DATA])
727{
728 struct cx23885_dev *dev = priv;
729 unsigned long timeout;
730 u32 value, flag, retval = 0;
731 int i;
732
733 dprintk(3, "%s: command(0x%X) = %s\n", __func__, command,
734 cmd_to_str(command));
735
736 /* this may not be 100% safe if we can't read any memory location
737 without side effects */
738 mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value);
739 if (value != 0x12345678) {
740 printk(KERN_ERR
741 "Firmware and/or mailbox pointer not initialized "
742 "or corrupted, signature = 0x%x, cmd = %s\n", value,
743 cmd_to_str(command));
744 return -1;
745 }
746
747 /* This read looks at 32 bits, but flag is only 8 bits.
748 * Seems we also bail if CMD or TIMEOUT bytes are set???
749 */
750 mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
751 if (flag) {
752 printk(KERN_ERR "ERROR: Mailbox appears to be in use "
753 "(%x), cmd = %s\n", flag, cmd_to_str(command));
754 return -1;
755 }
756
757 flag |= 1; /* tell 'em we're working on it */
758 mc417_memory_write(dev, dev->cx23417_mailbox, flag);
759
760 /* write command + args + fill remaining with zeros */
761 /* command code */
762 mc417_memory_write(dev, dev->cx23417_mailbox + 1, command);
763 mc417_memory_write(dev, dev->cx23417_mailbox + 3,
764 IVTV_API_STD_TIMEOUT); /* timeout */
765 for (i = 0; i < in; i++) {
766 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]);
767 dprintk(3, "API Input %d = %d\n", i, data[i]);
768 }
769 for (; i < CX2341X_MBOX_MAX_DATA; i++)
770 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0);
771
772 flag |= 3; /* tell 'em we're done writing */
773 mc417_memory_write(dev, dev->cx23417_mailbox, flag);
774
775 /* wait for firmware to handle the API command */
776 timeout = jiffies + msecs_to_jiffies(10);
777 for (;;) {
778 mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
779 if (0 != (flag & 4))
780 break;
781 if (time_after(jiffies, timeout)) {
782 printk(KERN_ERR "ERROR: API Mailbox timeout\n");
783 return -1;
784 }
785 udelay(10);
786 }
787
788 /* read output values */
789 for (i = 0; i < out; i++) {
790 mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i);
791 dprintk(3, "API Output %d = %d\n", i, data[i]);
792 }
793
794 mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval);
795 dprintk(3, "API result = %d\n", retval);
796
797 flag = 0;
798 mc417_memory_write(dev, dev->cx23417_mailbox, flag);
799
800 return retval;
801}
802
803/* We don't need to call the API often, so using just one
804 * mailbox will probably suffice
805 */
806static int cx23885_api_cmd(struct cx23885_dev *dev,
807 u32 command,
808 u32 inputcnt,
809 u32 outputcnt,
810 ...)
811{
812 u32 data[CX2341X_MBOX_MAX_DATA];
813 va_list vargs;
814 int i, err;
815
816 dprintk(3, "%s() cmds = 0x%08x\n", __func__, command);
817
818 va_start(vargs, outputcnt);
819 for (i = 0; i < inputcnt; i++)
820 data[i] = va_arg(vargs, int);
821
822 err = cx23885_mbox_func(dev, command, inputcnt, outputcnt, data);
823 for (i = 0; i < outputcnt; i++) {
824 int *vptr = va_arg(vargs, int *);
825 *vptr = data[i];
826 }
827 va_end(vargs);
828
829 return err;
830}
831
832static int cx23885_find_mailbox(struct cx23885_dev *dev)
833{
834 u32 signature[4] = {
835 0x12345678, 0x34567812, 0x56781234, 0x78123456
836 };
837 int signaturecnt = 0;
838 u32 value;
839 int i;
840
841 dprintk(2, "%s()\n", __func__);
842
843 for (i = 0; i < CX23885_FIRM_IMAGE_SIZE; i++) {
844 mc417_memory_read(dev, i, &value);
845 if (value == signature[signaturecnt])
846 signaturecnt++;
847 else
848 signaturecnt = 0;
849 if (4 == signaturecnt) {
850 dprintk(1, "Mailbox signature found at 0x%x\n", i+1);
851 return i+1;
852 }
853 }
854 printk(KERN_ERR "Mailbox signature values not found!\n");
855 return -1;
856}
857
858static int cx23885_load_firmware(struct cx23885_dev *dev)
859{
860 static const unsigned char magic[8] = {
861 0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa
862 };
863 const struct firmware *firmware;
864 int i, retval = 0;
865 u32 value = 0;
866 u32 gpio_output = 0;
867 u32 checksum = 0;
868 u32 *dataptr;
869
870 dprintk(2, "%s()\n", __func__);
871
872 /* Save GPIO settings before reset of APU */
873 retval |= mc417_memory_read(dev, 0x9020, &gpio_output);
874 retval |= mc417_memory_read(dev, 0x900C, &value);
875
876 retval = mc417_register_write(dev,
877 IVTV_REG_VPU, 0xFFFFFFED);
878 retval |= mc417_register_write(dev,
879 IVTV_REG_HW_BLOCKS, IVTV_CMD_HW_BLOCKS_RST);
880 retval |= mc417_register_write(dev,
881 IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800);
882 retval |= mc417_register_write(dev,
883 IVTV_REG_ENC_SDRAM_PRECHARGE, 0x1A);
884 retval |= mc417_register_write(dev,
885 IVTV_REG_APU, 0);
886
887 if (retval != 0) {
888 printk(KERN_ERR "%s: Error with mc417_register_write\n",
889 __func__);
890 return -1;
891 }
892
893 retval = request_firmware(&firmware, CX23885_FIRM_IMAGE_NAME,
894 &dev->pci->dev);
895
896 if (retval != 0) {
897 printk(KERN_ERR
898 "ERROR: Hotplug firmware request failed (%s).\n",
899 CX2341X_FIRM_ENC_FILENAME);
900 printk(KERN_ERR "Please fix your hotplug setup, the board will "
901 "not work without firmware loaded!\n");
902 return -1;
903 }
904
905 if (firmware->size != CX23885_FIRM_IMAGE_SIZE) {
906 printk(KERN_ERR "ERROR: Firmware size mismatch "
907 "(have %zd, expected %d)\n",
908 firmware->size, CX23885_FIRM_IMAGE_SIZE);
909 release_firmware(firmware);
910 return -1;
911 }
912
913 if (0 != memcmp(firmware->data, magic, 8)) {
914 printk(KERN_ERR
915 "ERROR: Firmware magic mismatch, wrong file?\n");
916 release_firmware(firmware);
917 return -1;
918 }
919
920 /* transfer to the chip */
921 dprintk(2, "Loading firmware ...\n");
922 dataptr = (u32 *)firmware->data;
923 for (i = 0; i < (firmware->size >> 2); i++) {
924 value = *dataptr;
925 checksum += ~value;
926 if (mc417_memory_write(dev, i, value) != 0) {
927 printk(KERN_ERR "ERROR: Loading firmware failed!\n");
928 release_firmware(firmware);
929 return -1;
930 }
931 dataptr++;
932 }
933
934 /* read back to verify with the checksum */
935 dprintk(1, "Verifying firmware ...\n");
936 for (i--; i >= 0; i--) {
937 if (mc417_memory_read(dev, i, &value) != 0) {
938 printk(KERN_ERR "ERROR: Reading firmware failed!\n");
939 release_firmware(firmware);
940 return -1;
941 }
942 checksum -= ~value;
943 }
944 if (checksum) {
945 printk(KERN_ERR
946 "ERROR: Firmware load failed (checksum mismatch).\n");
947 release_firmware(firmware);
948 return -1;
949 }
950 release_firmware(firmware);
951 dprintk(1, "Firmware upload successful.\n");
952
953 retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS,
954 IVTV_CMD_HW_BLOCKS_RST);
955
956 /* Restore GPIO settings, make sure EIO14 is enabled as an output. */
957 dprintk(2, "%s: GPIO output EIO 0-15 was = 0x%x\n",
958 __func__, gpio_output);
959 /* Power-up seems to have GPIOs AFU. This was causing digital side
960 * to fail at power-up. Seems GPIOs should be set to 0x10ff0411 at
961 * power-up.
962 * gpio_output |= (1<<14);
963 */
964 /* Note: GPIO14 is specific to the HVR1800 here */
965 gpio_output = 0x10ff0411 | (1<<14);
966 retval |= mc417_register_write(dev, 0x9020, gpio_output | (1<<14));
967 dprintk(2, "%s: GPIO output EIO 0-15 now = 0x%x\n",
968 __func__, gpio_output);
969
970 dprintk(1, "%s: GPIO value EIO 0-15 was = 0x%x\n",
971 __func__, value);
972 value |= (1<<14);
973 dprintk(1, "%s: GPIO value EIO 0-15 now = 0x%x\n",
974 __func__, value);
975 retval |= mc417_register_write(dev, 0x900C, value);
976
977 retval |= mc417_register_read(dev, IVTV_REG_VPU, &value);
978 retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8);
979
980 if (retval < 0)
981 printk(KERN_ERR "%s: Error with mc417_register_write\n",
982 __func__);
983 return 0;
984}
985
986void cx23885_417_check_encoder(struct cx23885_dev *dev)
987{
988 u32 status, seq;
989
990 status = seq = 0;
991 cx23885_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq);
992 dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq);
993}
994
995static void cx23885_codec_settings(struct cx23885_dev *dev)
996{
997 dprintk(1, "%s()\n", __func__);
998
999 /* assign frame size */
1000 cx23885_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0,
1001 dev->ts1.height, dev->ts1.width);
1002
1003 dev->mpeg_params.width = dev->ts1.width;
1004 dev->mpeg_params.height = dev->ts1.height;
1005 dev->mpeg_params.is_50hz =
1006 (dev->encodernorm.id & V4L2_STD_625_50) != 0;
1007
1008 cx2341x_update(dev, cx23885_mbox_func, NULL, &dev->mpeg_params);
1009
1010 cx23885_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1);
1011 cx23885_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1);
1012}
1013
1014static int cx23885_initialize_codec(struct cx23885_dev *dev)
1015{
1016 int version;
1017 int retval;
1018 u32 i, data[7];
1019
1020 dprintk(1, "%s()\n", __func__);
1021
1022 retval = cx23885_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */
1023 if (retval < 0) {
1024 dprintk(2, "%s() PING OK\n", __func__);
1025 retval = cx23885_load_firmware(dev);
1026 if (retval < 0) {
1027 printk(KERN_ERR "%s() f/w load failed\n", __func__);
1028 return retval;
1029 }
1030 dev->cx23417_mailbox = cx23885_find_mailbox(dev);
1031 if (dev->cx23417_mailbox < 0) {
1032 printk(KERN_ERR "%s() mailbox < 0, error\n",
1033 __func__);
1034 return -1;
1035 }
1036 retval = cx23885_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0);
1037 if (retval < 0) {
1038 printk(KERN_ERR
1039 "ERROR: cx23417 firmware ping failed!\n");
1040 return -1;
1041 }
1042 retval = cx23885_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1,
1043 &version);
1044 if (retval < 0) {
1045 printk(KERN_ERR "ERROR: cx23417 firmware get encoder :"
1046 "version failed!\n");
1047 return -1;
1048 }
1049 dprintk(1, "cx23417 firmware version is 0x%08x\n", version);
1050 msleep(200);
1051 }
1052
1053 cx23885_codec_settings(dev);
1054 msleep(60);
1055
1056 cx23885_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0,
1057 CX23885_FIELD1_SAA7115, CX23885_FIELD2_SAA7115);
1058 cx23885_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0,
1059 CX23885_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1060 0, 0);
1061
1062 /* Setup to capture VBI */
1063 data[0] = 0x0001BD00;
1064 data[1] = 1; /* frames per interrupt */
1065 data[2] = 4; /* total bufs */
1066 data[3] = 0x91559155; /* start codes */
1067 data[4] = 0x206080C0; /* stop codes */
1068 data[5] = 6; /* lines */
1069 data[6] = 64; /* BPL */
1070
1071 cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1],
1072 data[2], data[3], data[4], data[5], data[6]);
1073
1074 for (i = 2; i <= 24; i++) {
1075 int valid;
1076
1077 valid = ((i >= 19) && (i <= 21));
1078 cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i,
1079 valid, 0 , 0, 0);
1080 cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0,
1081 i | 0x80000000, valid, 0, 0, 0);
1082 }
1083
1084 cx23885_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX23885_UNMUTE);
1085 msleep(60);
1086
1087 /* initialize the video input */
1088 cx23885_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0);
1089 msleep(60);
1090
1091 /* Enable VIP style pixel invalidation so we work with scaled mode */
1092 mc417_memory_write(dev, 2120, 0x00000080);
1093
1094 /* start capturing to the host interface */
1095 cx23885_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0,
1096 CX23885_MPEG_CAPTURE, CX23885_RAW_BITS_NONE);
1097 msleep(10);
1098
1099 return 0;
1100}
1101
1102/* ------------------------------------------------------------------ */
1103
1104static int bb_buf_setup(struct videobuf_queue *q,
1105 unsigned int *count, unsigned int *size)
1106{
1107 struct cx23885_fh *fh = q->priv_data;
1108
1109 fh->dev->ts1.ts_packet_size = mpeglinesize;
1110 fh->dev->ts1.ts_packet_count = mpeglines;
1111
1112 *size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
1113 *count = mpegbufs;
1114
1115 return 0;
1116}
1117
1118static int bb_buf_prepare(struct videobuf_queue *q,
1119 struct videobuf_buffer *vb, enum v4l2_field field)
1120{
1121 struct cx23885_fh *fh = q->priv_data;
1122 return cx23885_buf_prepare(q, &fh->dev->ts1,
1123 (struct cx23885_buffer *)vb,
1124 field);
1125}
1126
1127static void bb_buf_queue(struct videobuf_queue *q,
1128 struct videobuf_buffer *vb)
1129{
1130 struct cx23885_fh *fh = q->priv_data;
1131 cx23885_buf_queue(&fh->dev->ts1, (struct cx23885_buffer *)vb);
1132}
1133
1134static void bb_buf_release(struct videobuf_queue *q,
1135 struct videobuf_buffer *vb)
1136{
1137 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
1138}
1139
1140static struct videobuf_queue_ops cx23885_qops = {
1141 .buf_setup = bb_buf_setup,
1142 .buf_prepare = bb_buf_prepare,
1143 .buf_queue = bb_buf_queue,
1144 .buf_release = bb_buf_release,
1145};
1146
1147/* ------------------------------------------------------------------ */
1148
1149static const u32 *ctrl_classes[] = {
1150 cx2341x_mpeg_ctrls,
1151 NULL
1152};
1153
1154static int cx23885_queryctrl(struct cx23885_dev *dev,
1155 struct v4l2_queryctrl *qctrl)
1156{
1157 qctrl->id = v4l2_ctrl_next(ctrl_classes, qctrl->id);
1158 if (qctrl->id == 0)
1159 return -EINVAL;
1160
1161 /* MPEG V4L2 controls */
1162 if (cx2341x_ctrl_query(&dev->mpeg_params, qctrl))
1163 qctrl->flags |= V4L2_CTRL_FLAG_DISABLED;
1164
1165 return 0;
1166}
1167
1168static int cx23885_querymenu(struct cx23885_dev *dev,
1169 struct v4l2_querymenu *qmenu)
1170{
1171 struct v4l2_queryctrl qctrl;
1172
1173 qctrl.id = qmenu->id;
1174 cx23885_queryctrl(dev, &qctrl);
1175 return v4l2_ctrl_query_menu(qmenu, &qctrl,
1176 cx2341x_ctrl_get_menu(qmenu->id));
1177}
1178
1179int cx23885_do_ioctl(struct inode *inode, struct file *file, int radio,
1180 struct cx23885_dev *dev, unsigned int cmd, void *arg,
1181 v4l2_kioctl driver_ioctl)
1182{
1183 int err;
1184
1185 switch (cmd) {
1186 /* ---------- tv norms ---------- */
1187 case VIDIOC_ENUMSTD:
1188 {
1189 struct v4l2_standard *e = arg;
1190 unsigned int i;
1191
1192 i = e->index;
1193 if (i >= ARRAY_SIZE(cx23885_tvnorms))
1194 return -EINVAL;
1195 err = v4l2_video_std_construct(e,
1196 cx23885_tvnorms[e->index].id,
1197 cx23885_tvnorms[e->index].name);
1198 e->index = i;
1199 if (err < 0)
1200 return err;
1201 return 0;
1202 }
1203 case VIDIOC_G_STD:
1204 {
1205 v4l2_std_id *id = arg;
1206
1207 *id = dev->encodernorm.id;
1208 return 0;
1209 }
1210 case VIDIOC_S_STD:
1211 {
1212 v4l2_std_id *id = arg;
1213 unsigned int i;
1214
1215 for (i = 0; i < ARRAY_SIZE(cx23885_tvnorms); i++)
1216 if (*id & cx23885_tvnorms[i].id)
1217 break;
1218 if (i == ARRAY_SIZE(cx23885_tvnorms))
1219 return -EINVAL;
1220 dev->encodernorm = cx23885_tvnorms[i];
1221
1222 return 0;
1223 }
1224
1225 /* ------ input switching ---------- */
1226 case VIDIOC_ENUMINPUT:
1227 {
1228 struct cx23885_input *input;
1229 struct v4l2_input *i = arg;
1230 unsigned int n;
1231
1232 n = i->index;
1233 if (n >= 4)
1234 return -EINVAL;
1235 input = &cx23885_boards[dev->board].input[n];
1236 if (input->type == 0)
1237 return -EINVAL;
1238 memset(i, 0, sizeof(*i));
1239 i->index = n;
1240 /* FIXME
1241 * strcpy(i->name, input->name); */
1242 strcpy(i->name, "unset");
1243 if (input->type == CX23885_VMUX_TELEVISION ||
1244 input->type == CX23885_VMUX_CABLE)
1245 i->type = V4L2_INPUT_TYPE_TUNER;
1246 else
1247 i->type = V4L2_INPUT_TYPE_CAMERA;
1248
1249 for (n = 0; n < ARRAY_SIZE(cx23885_tvnorms); n++)
1250 i->std |= cx23885_tvnorms[n].id;
1251 return 0;
1252 }
1253 case VIDIOC_G_INPUT:
1254 {
1255 unsigned int *i = arg;
1256
1257 *i = dev->input;
1258 return 0;
1259 }
1260 case VIDIOC_S_INPUT:
1261 {
1262 unsigned int *i = arg;
1263
1264 if (*i >= 4)
1265 return -EINVAL;
1266
1267 return 0;
1268 }
1269
1270 /* --- tuner ioctls ------------------------------------------ */
1271 case VIDIOC_G_TUNER:
1272 {
1273 struct v4l2_tuner *t = arg;
1274
1275 if (UNSET == dev->tuner_type)
1276 return -EINVAL;
1277 if (0 != t->index)
1278 return -EINVAL;
1279 memset(t, 0, sizeof(*t));
1280 strcpy(t->name, "Television");
1281 cx23885_call_i2c_clients(&dev->i2c_bus[2], VIDIOC_G_TUNER, t);
1282 cx23885_call_i2c_clients(&dev->i2c_bus[1], VIDIOC_G_TUNER, t);
1283
1284 dprintk(1, "VIDIOC_G_TUNER: tuner type %d\n", t->type);
1285
1286 return 0;
1287 }
1288 case VIDIOC_S_TUNER:
1289 {
1290 struct v4l2_tuner *t = arg;
1291
1292 if (UNSET == dev->tuner_type)
1293 return -EINVAL;
1294
1295 /* Update the A/V core */
1296 cx23885_call_i2c_clients(&dev->i2c_bus[2], VIDIOC_S_TUNER, t);
1297
1298 return 0;
1299 }
1300 case VIDIOC_G_FREQUENCY:
1301 {
1302 struct v4l2_frequency *f = arg;
1303
1304 memset(f, 0, sizeof(*f));
1305 if (UNSET == dev->tuner_type)
1306 return -EINVAL;
1307 f->type = V4L2_TUNER_ANALOG_TV;
1308 f->frequency = dev->freq;
1309
1310 /* Assumption that tuner is always on bus 1 */
1311 cx23885_call_i2c_clients(&dev->i2c_bus[1],
1312 VIDIOC_G_FREQUENCY, f);
1313
1314 return 0;
1315 }
1316 case VIDIOC_S_FREQUENCY:
1317 {
1318 struct v4l2_frequency *f = arg;
1319
1320 dprintk(1, "VIDIOC_S_FREQUENCY: dev type %d, f\n",
1321 dev->tuner_type);
1322 dprintk(1, "VIDIOC_S_FREQUENCY: f tuner %d, f type %d\n",
1323 f->tuner, f->type);
1324 if (UNSET == dev->tuner_type)
1325 return -EINVAL;
1326 if (f->tuner != 0)
1327 return -EINVAL;
1328 if (f->type != V4L2_TUNER_ANALOG_TV)
1329 return -EINVAL;
1330 dev->freq = f->frequency;
1331
1332 /* Assumption that tuner is always on bus 1 */
1333 cx23885_call_i2c_clients(&dev->i2c_bus[1],
1334 VIDIOC_S_FREQUENCY, f);
1335 return 0;
1336 }
1337 case VIDIOC_S_CTRL:
1338 {
1339 /* Update the A/V core */
1340 cx23885_call_i2c_clients(&dev->i2c_bus[2], VIDIOC_S_CTRL, arg);
1341 return 0;
1342 }
1343 default:
1344 /* Convert V4L ioctl to V4L2 and call mpeg_do_ioctl
1345 * (driver_ioctl) */
1346 return v4l_compat_translate_ioctl(inode, file, cmd, arg,
1347 driver_ioctl);
1348 }
1349
1350 return 0;
1351}
1352
1353static int mpeg_do_ioctl(struct inode *inode, struct file *file,
1354 unsigned int cmd, void *arg)
1355{
1356 struct cx23885_fh *fh = file->private_data;
1357 struct cx23885_dev *dev = fh->dev;
1358 struct cx23885_tsport *tsport = &dev->ts1;
1359
1360 if (v4l_debug > 1)
1361 v4l_print_ioctl(dev->name, cmd);
1362
1363 switch (cmd) {
1364
1365 /* --- capabilities ------------------------------------------ */
1366 case VIDIOC_QUERYCAP:
1367 {
1368 struct v4l2_capability *cap = arg;
1369
1370 memset(cap, 0, sizeof(*cap));
1371 strcpy(cap->driver, dev->name);
1372 strlcpy(cap->card, cx23885_boards[tsport->dev->board].name,
1373 sizeof(cap->card));
1374 sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci));
1375 cap->version = CX23885_VERSION_CODE;
1376 cap->capabilities =
1377 V4L2_CAP_VIDEO_CAPTURE |
1378 V4L2_CAP_READWRITE |
1379 V4L2_CAP_STREAMING |
1380 0;
1381 if (UNSET != dev->tuner_type)
1382 cap->capabilities |= V4L2_CAP_TUNER;
1383
1384 return 0;
1385 }
1386
1387 /* --- capture ioctls ---------------------------------------- */
1388 case VIDIOC_ENUM_FMT:
1389 {
1390 struct v4l2_fmtdesc *f = arg;
1391 int index;
1392
1393 index = f->index;
1394 if (index != 0)
1395 return -EINVAL;
1396
1397 memset(f, 0, sizeof(*f));
1398 f->index = index;
1399 strlcpy(f->description, "MPEG", sizeof(f->description));
1400 f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1401 f->pixelformat = V4L2_PIX_FMT_MPEG;
1402 return 0;
1403 }
1404 case VIDIOC_G_FMT:
1405 {
1406 struct v4l2_format *f = arg;
1407
1408 memset(f, 0, sizeof(*f));
1409 f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1410 f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1411 f->fmt.pix.bytesperline = 0;
1412 f->fmt.pix.sizeimage =
1413 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1414 f->fmt.pix.colorspace = 0;
1415 f->fmt.pix.width = dev->ts1.width;
1416 f->fmt.pix.height = dev->ts1.height;
1417 f->fmt.pix.field = fh->mpegq.field;
1418 dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d, f: %d\n",
1419 dev->ts1.width, dev->ts1.height, fh->mpegq.field);
1420 return 0;
1421 }
1422 case VIDIOC_TRY_FMT:
1423 {
1424 struct v4l2_format *f = arg;
1425
1426 f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1427 f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1428 f->fmt.pix.bytesperline = 0;
1429 f->fmt.pix.sizeimage =
1430 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1431 f->fmt.pix.sizeimage =
1432 f->fmt.pix.colorspace = 0;
1433 dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d, f: %d\n",
1434 dev->ts1.width, dev->ts1.height, fh->mpegq.field);
1435 return 0;
1436 }
1437 case VIDIOC_S_FMT:
1438 {
1439 struct v4l2_format *f = arg;
1440
1441 f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1442 f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1443 f->fmt.pix.bytesperline = 0;
1444 f->fmt.pix.sizeimage =
1445 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1446 f->fmt.pix.colorspace = 0;
1447 dprintk(1, "VIDIOC_S_FMT: w: %d, h: %d, f: %d\n",
1448 f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.field);
1449 return 0;
1450 }
1451
1452 /* --- streaming capture ------------------------------------- */
1453 case VIDIOC_REQBUFS:
1454 return videobuf_reqbufs(&fh->mpegq, arg);
1455
1456 case VIDIOC_QUERYBUF:
1457 return videobuf_querybuf(&fh->mpegq, arg);
1458
1459 case VIDIOC_QBUF:
1460 return videobuf_qbuf(&fh->mpegq, arg);
1461
1462 case VIDIOC_DQBUF:
1463 return videobuf_dqbuf(&fh->mpegq, arg,
1464 file->f_flags & O_NONBLOCK);
1465
1466 case VIDIOC_STREAMON:
1467 return videobuf_streamon(&fh->mpegq);
1468
1469 case VIDIOC_STREAMOFF:
1470 return videobuf_streamoff(&fh->mpegq);
1471
1472 case VIDIOC_G_EXT_CTRLS:
1473 {
1474 struct v4l2_ext_controls *f = arg;
1475
1476 if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1477 return -EINVAL;
1478 return cx2341x_ext_ctrls(&dev->mpeg_params, 0, f, cmd);
1479 }
1480 case VIDIOC_S_EXT_CTRLS:
1481 case VIDIOC_TRY_EXT_CTRLS:
1482 {
1483 struct v4l2_ext_controls *f = arg;
1484 struct cx2341x_mpeg_params p;
1485 int err;
1486
1487 if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1488 return -EINVAL;
1489 p = dev->mpeg_params;
1490 err = cx2341x_ext_ctrls(&p, 0, f, cmd);
1491 if (err == 0 && cmd == VIDIOC_S_EXT_CTRLS) {
1492 err = cx2341x_update(dev, cx23885_mbox_func,
1493 &dev->mpeg_params, &p);
1494 dev->mpeg_params = p;
1495 }
1496 return err;
1497 }
1498 case VIDIOC_S_FREQUENCY:
1499 {
1500 cx23885_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
1501 CX23885_END_NOW, CX23885_MPEG_CAPTURE,
1502 CX23885_RAW_BITS_NONE);
1503 cx23885_do_ioctl(inode, file, 0, dev, cmd, arg,
1504 mpeg_do_ioctl);
1505 cx23885_initialize_codec(dev);
1506
1507 return 0;
1508 }
1509 case VIDIOC_LOG_STATUS:
1510 {
1511 char name[32 + 2];
1512
1513 snprintf(name, sizeof(name), "%s/2", dev->name);
1514 printk(KERN_INFO
1515 "%s/2: ============ START LOG STATUS ============\n",
1516 dev->name);
1517 cx23885_call_i2c_clients(&dev->i2c_bus[0], VIDIOC_LOG_STATUS,
1518 NULL);
1519 cx23885_call_i2c_clients(&dev->i2c_bus[1], VIDIOC_LOG_STATUS,
1520 NULL);
1521 cx23885_call_i2c_clients(&dev->i2c_bus[2], VIDIOC_LOG_STATUS,
1522 NULL);
1523 cx2341x_log_status(&dev->mpeg_params, name);
1524 printk(KERN_INFO
1525 "%s/2: ============= END LOG STATUS =============\n",
1526 dev->name);
1527 return 0;
1528 }
1529 case VIDIOC_QUERYMENU:
1530 return cx23885_querymenu(dev, arg);
1531 case VIDIOC_QUERYCTRL:
1532 {
1533 struct v4l2_queryctrl *c = arg;
1534
1535 return cx23885_queryctrl(dev, c);
1536 }
1537
1538 default:
1539 return cx23885_do_ioctl(inode, file, 0, dev, cmd, arg,
1540 mpeg_do_ioctl);
1541 }
1542 return 0;
1543}
1544
1545static int mpeg_ioctl(struct inode *inode, struct file *file,
1546 unsigned int cmd, unsigned long arg)
1547{
1548 return video_usercopy(inode, file, cmd, arg, mpeg_do_ioctl);
1549}
1550
1551static int mpeg_open(struct inode *inode, struct file *file)
1552{
1553 int minor = iminor(inode);
1554 struct cx23885_dev *h, *dev = NULL;
1555 struct list_head *list;
1556 struct cx23885_fh *fh;
1557
1558 dprintk(2, "%s()\n", __func__);
1559
1560 list_for_each(list, &cx23885_devlist) {
1561 h = list_entry(list, struct cx23885_dev, devlist);
1562 if (h->v4l_device->minor == minor) {
1563 dev = h;
1564 break;
1565 }
1566 }
1567
1568 if (dev == NULL)
1569 return -ENODEV;
1570
1571 /* allocate + initialize per filehandle data */
1572 fh = kzalloc(sizeof(*fh), GFP_KERNEL);
1573 if (NULL == fh)
1574 return -ENOMEM;
1575
1576 file->private_data = fh;
1577 fh->dev = dev;
1578
1579 videobuf_queue_sg_init(&fh->mpegq, &cx23885_qops,
1580 &dev->pci->dev, &dev->ts1.slock,
1581 V4L2_BUF_TYPE_VIDEO_CAPTURE,
1582 V4L2_FIELD_INTERLACED,
1583 sizeof(struct cx23885_buffer),
1584 fh);
1585
1586 return 0;
1587}
1588
1589static int mpeg_release(struct inode *inode, struct file *file)
1590{
1591 struct cx23885_fh *fh = file->private_data;
1592 struct cx23885_dev *dev = fh->dev;
1593
1594 dprintk(2, "%s()\n", __func__);
1595
1596 /* FIXME: Review this crap */
1597 /* Shut device down on last close */
1598 if (atomic_cmpxchg(&fh->v4l_reading, 1, 0) == 1) {
1599 if (atomic_dec_return(&dev->v4l_reader_count) == 0) {
1600 /* stop mpeg capture */
1601 cx23885_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
1602 CX23885_END_NOW, CX23885_MPEG_CAPTURE,
1603 CX23885_RAW_BITS_NONE);
1604
1605 msleep(500);
1606 cx23885_417_check_encoder(dev);
1607
1608 cx23885_cancel_buffers(&fh->dev->ts1);
1609 }
1610 }
1611
1612 if (fh->mpegq.streaming)
1613 videobuf_streamoff(&fh->mpegq);
1614 if (fh->mpegq.reading)
1615 videobuf_read_stop(&fh->mpegq);
1616
1617 videobuf_mmap_free(&fh->mpegq);
1618 file->private_data = NULL;
1619 kfree(fh);
1620
1621 return 0;
1622}
1623
1624static ssize_t mpeg_read(struct file *file, char __user *data,
1625 size_t count, loff_t *ppos)
1626{
1627 struct cx23885_fh *fh = file->private_data;
1628 struct cx23885_dev *dev = fh->dev;
1629
1630 dprintk(2, "%s()\n", __func__);
1631
1632 /* Deal w/ A/V decoder * and mpeg encoder sync issues. */
1633 /* Start mpeg encoder on first read. */
1634 if (atomic_cmpxchg(&fh->v4l_reading, 0, 1) == 0) {
1635 if (atomic_inc_return(&dev->v4l_reader_count) == 1) {
1636 if (cx23885_initialize_codec(dev) < 0)
1637 return -EINVAL;
1638 }
1639 }
1640
1641 return videobuf_read_stream(&fh->mpegq, data, count, ppos, 0,
1642 file->f_flags & O_NONBLOCK);
1643}
1644
1645static unsigned int mpeg_poll(struct file *file,
1646 struct poll_table_struct *wait)
1647{
1648 struct cx23885_fh *fh = file->private_data;
1649 struct cx23885_dev *dev = fh->dev;
1650
1651 dprintk(2, "%s\n", __func__);
1652
1653 return videobuf_poll_stream(file, &fh->mpegq, wait);
1654}
1655
1656static int mpeg_mmap(struct file *file, struct vm_area_struct *vma)
1657{
1658 struct cx23885_fh *fh = file->private_data;
1659 struct cx23885_dev *dev = fh->dev;
1660
1661 dprintk(2, "%s()\n", __func__);
1662
1663 return videobuf_mmap_mapper(&fh->mpegq, vma);
1664}
1665
1666static struct file_operations mpeg_fops = {
1667 .owner = THIS_MODULE,
1668 .open = mpeg_open,
1669 .release = mpeg_release,
1670 .read = mpeg_read,
1671 .poll = mpeg_poll,
1672 .mmap = mpeg_mmap,
1673 .ioctl = mpeg_ioctl,
1674 .llseek = no_llseek,
1675};
1676
1677static struct video_device cx23885_mpeg_template = {
1678 .name = "cx23885",
1679 .type = VID_TYPE_CAPTURE |
1680 VID_TYPE_TUNER |
1681 VID_TYPE_SCALES |
1682 VID_TYPE_MPEG_ENCODER,
1683 .fops = &mpeg_fops,
1684 .minor = -1,
1685};
1686
1687void cx23885_417_unregister(struct cx23885_dev *dev)
1688{
1689 dprintk(1, "%s()\n", __func__);
1690
1691 if (dev->v4l_device) {
1692 if (-1 != dev->v4l_device->minor)
1693 video_unregister_device(dev->v4l_device);
1694 else
1695 video_device_release(dev->v4l_device);
1696 dev->v4l_device = NULL;
1697 }
1698}
1699
1700static struct video_device *cx23885_video_dev_alloc(
1701 struct cx23885_tsport *tsport,
1702 struct pci_dev *pci,
1703 struct video_device *template,
1704 char *type)
1705{
1706 struct video_device *vfd;
1707 struct cx23885_dev *dev = tsport->dev;
1708
1709 dprintk(1, "%s()\n", __func__);
1710
1711 vfd = video_device_alloc();
1712 if (NULL == vfd)
1713 return NULL;
1714 *vfd = *template;
1715 vfd->minor = -1;
1716 snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name,
1717 type, cx23885_boards[tsport->dev->board].name);
1718 vfd->dev = &pci->dev;
1719 vfd->release = video_device_release;
1720 return vfd;
1721}
1722
1723int cx23885_417_register(struct cx23885_dev *dev)
1724{
1725 /* FIXME: Port1 hardcoded here */
1726 int err = -ENODEV;
1727 struct cx23885_tsport *tsport = &dev->ts1;
1728
1729 dprintk(1, "%s()\n", __func__);
1730
1731 if (cx23885_boards[dev->board].portb != CX23885_MPEG_ENCODER)
1732 return err;
1733
1734 /* Set default TV standard */
1735 dev->encodernorm = cx23885_tvnorms[0];
1736
1737 if (dev->encodernorm.id & V4L2_STD_525_60)
1738 tsport->height = 480;
1739 else
1740 tsport->height = 576;
1741
1742 tsport->width = 720;
1743 cx2341x_fill_defaults(&dev->mpeg_params);
1744
1745 dev->mpeg_params.port = CX2341X_PORT_SERIAL;
1746
1747 /* Allocate and initialize V4L video device */
1748 dev->v4l_device = cx23885_video_dev_alloc(tsport,
1749 dev->pci, &cx23885_mpeg_template, "mpeg");
1750 err = video_register_device(dev->v4l_device,
1751 VFL_TYPE_GRABBER, -1);
1752 if (err < 0) {
1753 printk(KERN_INFO "%s: can't register mpeg device\n", dev->name);
1754 return err;
1755 }
1756
1757 /* Initialize MC417 registers */
1758 cx23885_mc417_init(dev);
1759
1760 printk(KERN_INFO "%s: registered device video%d [mpeg]\n",
1761 dev->name, dev->v4l_device->minor & 0x1f);
1762
1763 return 0;
1764}
diff --git a/drivers/media/video/cx23885/cx23885-cards.c b/drivers/media/video/cx23885/cx23885-cards.c
index dfa269838e01..6ebf58724a01 100644
--- a/drivers/media/video/cx23885/cx23885-cards.c
+++ b/drivers/media/video/cx23885/cx23885-cards.c
@@ -73,6 +73,7 @@ struct cx23885_board cx23885_boards[] = {
73 [CX23885_BOARD_HAUPPAUGE_HVR1800] = { 73 [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
74 .name = "Hauppauge WinTV-HVR1800", 74 .name = "Hauppauge WinTV-HVR1800",
75 .porta = CX23885_ANALOG_VIDEO, 75 .porta = CX23885_ANALOG_VIDEO,
76 .portb = CX23885_MPEG_ENCODER,
76 .portc = CX23885_MPEG_DVB, 77 .portc = CX23885_MPEG_DVB,
77 .tuner_type = TUNER_PHILIPS_TDA8290, 78 .tuner_type = TUNER_PHILIPS_TDA8290,
78 .tuner_addr = 0x42, /* 0x84 >> 1 */ 79 .tuner_addr = 0x42, /* 0x84 >> 1 */
@@ -130,6 +131,18 @@ struct cx23885_board cx23885_boards[] = {
130 .name = "Hauppauge WinTV-HVR1500", 131 .name = "Hauppauge WinTV-HVR1500",
131 .portc = CX23885_MPEG_DVB, 132 .portc = CX23885_MPEG_DVB,
132 }, 133 },
134 [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
135 .name = "Hauppauge WinTV-HVR1200",
136 .portc = CX23885_MPEG_DVB,
137 },
138 [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
139 .name = "Hauppauge WinTV-HVR1700",
140 .portc = CX23885_MPEG_DVB,
141 },
142 [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
143 .name = "Hauppauge WinTV-HVR1400",
144 .portc = CX23885_MPEG_DVB,
145 },
133}; 146};
134const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards); 147const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
135 148
@@ -181,6 +194,18 @@ struct cx23885_subid cx23885_subids[] = {
181 .subvendor = 0x0070, 194 .subvendor = 0x0070,
182 .subdevice = 0x7717, 195 .subdevice = 0x7717,
183 .card = CX23885_BOARD_HAUPPAUGE_HVR1500, 196 .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
197 }, {
198 .subvendor = 0x0070,
199 .subdevice = 0x71d1,
200 .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
201 }, {
202 .subvendor = 0x0070,
203 .subdevice = 0x8101,
204 .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
205 }, {
206 .subvendor = 0x0070,
207 .subdevice = 0x8010,
208 .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
184 }, 209 },
185}; 210};
186const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids); 211const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
@@ -235,6 +260,12 @@ static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
235 case 79561: /* WinTV-HVR1250 (PCIe, OEM, No IR, half height, ATSC and Basic analog */ 260 case 79561: /* WinTV-HVR1250 (PCIe, OEM, No IR, half height, ATSC and Basic analog */
236 case 79571: /* WinTV-HVR1250 (PCIe, OEM, No IR, full height, ATSC and Basic analog */ 261 case 79571: /* WinTV-HVR1250 (PCIe, OEM, No IR, full height, ATSC and Basic analog */
237 case 79671: /* WinTV-HVR1250 (PCIe, OEM, No IR, half height, ATSC and Basic analog */ 262 case 79671: /* WinTV-HVR1250 (PCIe, OEM, No IR, half height, ATSC and Basic analog */
263 case 80019:
264 /* WinTV-HVR1400 (Express Card, Retail, IR,
265 * DVB-T and Basic analog */
266 case 81519:
267 /* WinTV-HVR1700 (PCIe, Retail, No IR, half height,
268 * DVB-T and MPEG2 HW Encoder */
238 break; 269 break;
239 default: 270 default:
240 printk("%s: warning: unknown hauppauge model #%d\n", dev->name, tv.model); 271 printk("%s: warning: unknown hauppauge model #%d\n", dev->name, tv.model);
@@ -264,7 +295,7 @@ int cx23885_tuner_callback(void *priv, int command, int arg)
264 } 295 }
265 else { 296 else {
266 printk(KERN_ERR 297 printk(KERN_ERR
267 "%s(): Unknow command.\n", __FUNCTION__); 298 "%s(): Unknow command.\n", __func__);
268 return -EINVAL; 299 return -EINVAL;
269 } 300 }
270 break; 301 break;
@@ -306,6 +337,10 @@ void cx23885_gpio_setup(struct cx23885_dev *dev)
306 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ 337 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
307 /* GPIO-19 IR_RX */ 338 /* GPIO-19 IR_RX */
308 339
340 /* CX23417 GPIO's */
341 /* EIO15 Zilog Reset */
342 /* EIO14 S5H1409/CX24227 Reset */
343
309 /* Force the TDA8295A into reset and back */ 344 /* Force the TDA8295A into reset and back */
310 cx_set(GP0_IO, 0x00040004); 345 cx_set(GP0_IO, 0x00040004);
311 mdelay(20); 346 mdelay(20);
@@ -314,6 +349,50 @@ void cx23885_gpio_setup(struct cx23885_dev *dev)
314 cx_set(GP0_IO, 0x00040004); 349 cx_set(GP0_IO, 0x00040004);
315 mdelay(20); 350 mdelay(20);
316 break; 351 break;
352 case CX23885_BOARD_HAUPPAUGE_HVR1200:
353 /* GPIO-0 tda10048 demodulator reset */
354 /* GPIO-2 tda18271 tuner reset */
355
356 /* Put the parts into reset and back */
357 cx_set(GP0_IO, 0x00050000);
358 mdelay(20);
359 cx_clear(GP0_IO, 0x00000005);
360 mdelay(20);
361 cx_set(GP0_IO, 0x00050005);
362 break;
363 case CX23885_BOARD_HAUPPAUGE_HVR1700:
364 /* GPIO-0 TDA10048 demodulator reset */
365 /* GPIO-2 TDA8295A Reset */
366 /* GPIO-3-10 cx23417 data0-7 */
367 /* GPIO-11-14 cx23417 addr0-3 */
368 /* GPIO-15-18 cx23417 READY, CS, RD, WR */
369
370 /* The following GPIO's are on the interna AVCore (cx25840) */
371 /* GPIO-19 IR_RX */
372 /* GPIO-20 IR_TX 416/DVBT Select */
373 /* GPIO-21 IIS DAT */
374 /* GPIO-22 IIS WCLK */
375 /* GPIO-23 IIS BCLK */
376
377 /* Put the parts into reset and back */
378 cx_set(GP0_IO, 0x00050000);
379 mdelay(20);
380 cx_clear(GP0_IO, 0x00000005);
381 mdelay(20);
382 cx_set(GP0_IO, 0x00050005);
383 break;
384 case CX23885_BOARD_HAUPPAUGE_HVR1400:
385 /* GPIO-0 Dibcom7000p demodulator reset */
386 /* GPIO-2 xc3028L tuner reset */
387 /* GPIO-13 LED */
388
389 /* Put the parts into reset and back */
390 cx_set(GP0_IO, 0x00050000);
391 mdelay(20);
392 cx_clear(GP0_IO, 0x00000005);
393 mdelay(20);
394 cx_set(GP0_IO, 0x00050005);
395 break;
317 } 396 }
318} 397}
319 398
@@ -324,6 +403,8 @@ int cx23885_ir_init(struct cx23885_dev *dev)
324 case CX23885_BOARD_HAUPPAUGE_HVR1500: 403 case CX23885_BOARD_HAUPPAUGE_HVR1500:
325 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 404 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
326 case CX23885_BOARD_HAUPPAUGE_HVR1800: 405 case CX23885_BOARD_HAUPPAUGE_HVR1800:
406 case CX23885_BOARD_HAUPPAUGE_HVR1200:
407 case CX23885_BOARD_HAUPPAUGE_HVR1400:
327 /* FIXME: Implement me */ 408 /* FIXME: Implement me */
328 break; 409 break;
329 } 410 }
@@ -348,11 +429,14 @@ void cx23885_card_setup(struct cx23885_dev *dev)
348 case CX23885_BOARD_HAUPPAUGE_HVR1250: 429 case CX23885_BOARD_HAUPPAUGE_HVR1250:
349 case CX23885_BOARD_HAUPPAUGE_HVR1500: 430 case CX23885_BOARD_HAUPPAUGE_HVR1500:
350 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 431 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
432 case CX23885_BOARD_HAUPPAUGE_HVR1400:
351 if (dev->i2c_bus[0].i2c_rc == 0) 433 if (dev->i2c_bus[0].i2c_rc == 0)
352 hauppauge_eeprom(dev, eeprom+0x80); 434 hauppauge_eeprom(dev, eeprom+0x80);
353 break; 435 break;
354 case CX23885_BOARD_HAUPPAUGE_HVR1800: 436 case CX23885_BOARD_HAUPPAUGE_HVR1800:
355 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 437 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
438 case CX23885_BOARD_HAUPPAUGE_HVR1200:
439 case CX23885_BOARD_HAUPPAUGE_HVR1700:
356 if (dev->i2c_bus[0].i2c_rc == 0) 440 if (dev->i2c_bus[0].i2c_rc == 0)
357 hauppauge_eeprom(dev, eeprom+0xc0); 441 hauppauge_eeprom(dev, eeprom+0xc0);
358 break; 442 break;
@@ -364,17 +448,45 @@ void cx23885_card_setup(struct cx23885_dev *dev)
364 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 448 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
365 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 449 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
366 break; 450 break;
451 case CX23885_BOARD_HAUPPAUGE_HVR1800:
452 /* Defaults for VID B - Analog encoder */
453 /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
454 ts1->gen_ctrl_val = 0x10e;
455 ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
456 ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
457
458 /* APB_TSVALERR_POL (active low)*/
459 ts1->vld_misc_val = 0x2000;
460 ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
461
462 /* Defaults for VID C */
463 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
464 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
465 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
466 break;
367 case CX23885_BOARD_HAUPPAUGE_HVR1250: 467 case CX23885_BOARD_HAUPPAUGE_HVR1250:
368 case CX23885_BOARD_HAUPPAUGE_HVR1500: 468 case CX23885_BOARD_HAUPPAUGE_HVR1500:
369 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 469 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
370 case CX23885_BOARD_HAUPPAUGE_HVR1800:
371 case CX23885_BOARD_HAUPPAUGE_HVR1800lp: 470 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
471 case CX23885_BOARD_HAUPPAUGE_HVR1200:
472 case CX23885_BOARD_HAUPPAUGE_HVR1700:
473 case CX23885_BOARD_HAUPPAUGE_HVR1400:
372 default: 474 default:
373 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */ 475 ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
374 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */ 476 ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
375 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO; 477 ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
376 } 478 }
377 479
480 /* Certain boards support analog, or require the avcore to be
481 * loaded, ensure this happens.
482 */
483 switch (dev->board) {
484 case CX23885_BOARD_HAUPPAUGE_HVR1800:
485 case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
486 case CX23885_BOARD_HAUPPAUGE_HVR1700:
487 request_module("cx25840");
488 break;
489 }
378} 490}
379 491
380/* ------------------------------------------------------------------ */ 492/* ------------------------------------------------------------------ */
diff --git a/drivers/media/video/cx23885/cx23885-core.c b/drivers/media/video/cx23885/cx23885-core.c
index 7f10b273598f..f24abcd06dea 100644
--- a/drivers/media/video/cx23885/cx23885-core.c
+++ b/drivers/media/video/cx23885/cx23885-core.c
@@ -190,25 +190,25 @@ static struct sram_channel cx23887_sram_channels[] = {
190static int cx23885_risc_decode(u32 risc) 190static int cx23885_risc_decode(u32 risc)
191{ 191{
192 static char *instr[16] = { 192 static char *instr[16] = {
193 [ RISC_SYNC >> 28 ] = "sync", 193 [RISC_SYNC >> 28] = "sync",
194 [ RISC_WRITE >> 28 ] = "write", 194 [RISC_WRITE >> 28] = "write",
195 [ RISC_WRITEC >> 28 ] = "writec", 195 [RISC_WRITEC >> 28] = "writec",
196 [ RISC_READ >> 28 ] = "read", 196 [RISC_READ >> 28] = "read",
197 [ RISC_READC >> 28 ] = "readc", 197 [RISC_READC >> 28] = "readc",
198 [ RISC_JUMP >> 28 ] = "jump", 198 [RISC_JUMP >> 28] = "jump",
199 [ RISC_SKIP >> 28 ] = "skip", 199 [RISC_SKIP >> 28] = "skip",
200 [ RISC_WRITERM >> 28 ] = "writerm", 200 [RISC_WRITERM >> 28] = "writerm",
201 [ RISC_WRITECM >> 28 ] = "writecm", 201 [RISC_WRITECM >> 28] = "writecm",
202 [ RISC_WRITECR >> 28 ] = "writecr", 202 [RISC_WRITECR >> 28] = "writecr",
203 }; 203 };
204 static int incr[16] = { 204 static int incr[16] = {
205 [ RISC_WRITE >> 28 ] = 3, 205 [RISC_WRITE >> 28] = 3,
206 [ RISC_JUMP >> 28 ] = 3, 206 [RISC_JUMP >> 28] = 3,
207 [ RISC_SKIP >> 28 ] = 1, 207 [RISC_SKIP >> 28] = 1,
208 [ RISC_SYNC >> 28 ] = 1, 208 [RISC_SYNC >> 28] = 1,
209 [ RISC_WRITERM >> 28 ] = 3, 209 [RISC_WRITERM >> 28] = 3,
210 [ RISC_WRITECM >> 28 ] = 3, 210 [RISC_WRITECM >> 28] = 3,
211 [ RISC_WRITECR >> 28 ] = 4, 211 [RISC_WRITECR >> 28] = 4,
212 }; 212 };
213 static char *bits[] = { 213 static char *bits[] = {
214 "12", "13", "14", "resync", 214 "12", "13", "14", "resync",
@@ -260,7 +260,7 @@ void cx23885_wakeup(struct cx23885_tsport *port,
260 } 260 }
261 if (bc != 1) 261 if (bc != 1)
262 printk("%s: %d buffers handled (should be 1)\n", 262 printk("%s: %d buffers handled (should be 1)\n",
263 __FUNCTION__, bc); 263 __func__, bc);
264} 264}
265 265
266int cx23885_sram_channel_setup(struct cx23885_dev *dev, 266int cx23885_sram_channel_setup(struct cx23885_dev *dev,
@@ -272,7 +272,7 @@ int cx23885_sram_channel_setup(struct cx23885_dev *dev,
272 272
273 if (ch->cmds_start == 0) 273 if (ch->cmds_start == 0)
274 { 274 {
275 dprintk(1, "%s() Erasing channel [%s]\n", __FUNCTION__, 275 dprintk(1, "%s() Erasing channel [%s]\n", __func__,
276 ch->name); 276 ch->name);
277 cx_write(ch->ptr1_reg, 0); 277 cx_write(ch->ptr1_reg, 0);
278 cx_write(ch->ptr2_reg, 0); 278 cx_write(ch->ptr2_reg, 0);
@@ -280,7 +280,7 @@ int cx23885_sram_channel_setup(struct cx23885_dev *dev,
280 cx_write(ch->cnt1_reg, 0); 280 cx_write(ch->cnt1_reg, 0);
281 return 0; 281 return 0;
282 } else { 282 } else {
283 dprintk(1, "%s() Configuring channel [%s]\n", __FUNCTION__, 283 dprintk(1, "%s() Configuring channel [%s]\n", __func__,
284 ch->name); 284 ch->name);
285 } 285 }
286 286
@@ -297,7 +297,7 @@ int cx23885_sram_channel_setup(struct cx23885_dev *dev,
297 297
298 /* write CDT */ 298 /* write CDT */
299 for (i = 0; i < lines; i++) { 299 for (i = 0; i < lines; i++) {
300 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __FUNCTION__, cdt + 16*i, 300 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __func__, cdt + 16*i,
301 ch->fifo_start + bpl*i); 301 ch->fifo_start + bpl*i);
302 cx_write(cdt + 16*i, ch->fifo_start + bpl*i); 302 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
303 cx_write(cdt + 16*i + 4, 0); 303 cx_write(cdt + 16*i + 4, 0);
@@ -449,7 +449,7 @@ static void cx23885_shutdown(struct cx23885_dev *dev)
449 449
450static void cx23885_reset(struct cx23885_dev *dev) 450static void cx23885_reset(struct cx23885_dev *dev)
451{ 451{
452 dprintk(1, "%s()\n", __FUNCTION__); 452 dprintk(1, "%s()\n", __func__);
453 453
454 cx23885_shutdown(dev); 454 cx23885_shutdown(dev);
455 455
@@ -482,7 +482,7 @@ static void cx23885_reset(struct cx23885_dev *dev)
482 482
483static int cx23885_pci_quirks(struct cx23885_dev *dev) 483static int cx23885_pci_quirks(struct cx23885_dev *dev)
484{ 484{
485 dprintk(1, "%s()\n", __FUNCTION__); 485 dprintk(1, "%s()\n", __func__);
486 486
487 /* The cx23885 bridge has a weird bug which causes NMI to be asserted 487 /* The cx23885 bridge has a weird bug which causes NMI to be asserted
488 * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not 488 * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
@@ -513,11 +513,13 @@ int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
513 513
514static int cx23885_init_tsport(struct cx23885_dev *dev, struct cx23885_tsport *port, int portno) 514static int cx23885_init_tsport(struct cx23885_dev *dev, struct cx23885_tsport *port, int portno)
515{ 515{
516 dprintk(1, "%s(portno=%d)\n", __FUNCTION__, portno); 516 dprintk(1, "%s(portno=%d)\n", __func__, portno);
517 517
518 /* Transport bus init dma queue - Common settings */ 518 /* Transport bus init dma queue - Common settings */
519 port->dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */ 519 port->dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
520 port->ts_int_msk_val = 0x1111; /* TS port bits for RISC */ 520 port->ts_int_msk_val = 0x1111; /* TS port bits for RISC */
521 port->vld_misc_val = 0x0;
522 port->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4);
521 523
522 spin_lock_init(&port->slock); 524 spin_lock_init(&port->slock);
523 port->dev = dev; 525 port->dev = dev;
@@ -544,7 +546,7 @@ static int cx23885_init_tsport(struct cx23885_dev *dev, struct cx23885_tsport *p
544 port->reg_ts_clk_en = VID_B_TS_CLK_EN; 546 port->reg_ts_clk_en = VID_B_TS_CLK_EN;
545 port->reg_src_sel = VID_B_SRC_SEL; 547 port->reg_src_sel = VID_B_SRC_SEL;
546 port->reg_ts_int_msk = VID_B_INT_MSK; 548 port->reg_ts_int_msk = VID_B_INT_MSK;
547 port->reg_ts_int_stat = VID_B_INT_STAT; 549 port->reg_ts_int_stat = VID_B_INT_STAT;
548 port->sram_chno = SRAM_CH03; /* VID_B */ 550 port->sram_chno = SRAM_CH03; /* VID_B */
549 port->pci_irqmask = 0x02; /* VID_B bit1 */ 551 port->pci_irqmask = 0x02; /* VID_B bit1 */
550 break; 552 break;
@@ -604,14 +606,14 @@ static void cx23885_dev_checkrevision(struct cx23885_dev *dev)
604 break; 606 break;
605 default: 607 default:
606 printk(KERN_ERR "%s() New hardware revision found 0x%x\n", 608 printk(KERN_ERR "%s() New hardware revision found 0x%x\n",
607 __FUNCTION__, dev->hwrevision); 609 __func__, dev->hwrevision);
608 } 610 }
609 if (dev->hwrevision) 611 if (dev->hwrevision)
610 printk(KERN_INFO "%s() Hardware revision = 0x%02x\n", 612 printk(KERN_INFO "%s() Hardware revision = 0x%02x\n",
611 __FUNCTION__, dev->hwrevision); 613 __func__, dev->hwrevision);
612 else 614 else
613 printk(KERN_ERR "%s() Hardware revision unknown 0x%x\n", 615 printk(KERN_ERR "%s() Hardware revision unknown 0x%x\n",
614 __FUNCTION__, dev->hwrevision); 616 __func__, dev->hwrevision);
615} 617}
616 618
617static int cx23885_dev_setup(struct cx23885_dev *dev) 619static int cx23885_dev_setup(struct cx23885_dev *dev)
@@ -644,7 +646,7 @@ static int cx23885_dev_setup(struct cx23885_dev *dev)
644 BUG(); 646 BUG();
645 647
646 dprintk(1, "%s() Memory configured for PCIe bridge type %d\n", 648 dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
647 __FUNCTION__, dev->bridge); 649 __func__, dev->bridge);
648 650
649 /* board config */ 651 /* board config */
650 dev->board = UNSET; 652 dev->board = UNSET;
@@ -697,10 +699,12 @@ static int cx23885_dev_setup(struct cx23885_dev *dev)
697 dev->i2c_bus[2].reg_wdata = I2C3_WDATA; 699 dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
698 dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */ 700 dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
699 701
700 if(cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) 702 if ((cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) ||
703 (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER))
701 cx23885_init_tsport(dev, &dev->ts1, 1); 704 cx23885_init_tsport(dev, &dev->ts1, 1);
702 705
703 if(cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) 706 if ((cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) ||
707 (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER))
704 cx23885_init_tsport(dev, &dev->ts2, 2); 708 cx23885_init_tsport(dev, &dev->ts2, 2);
705 709
706 if (get_resources(dev) < 0) { 710 if (get_resources(dev) < 0) {
@@ -734,9 +738,9 @@ static int cx23885_dev_setup(struct cx23885_dev *dev)
734 dev->radio_addr = cx23885_boards[dev->board].radio_addr; 738 dev->radio_addr = cx23885_boards[dev->board].radio_addr;
735 739
736 dprintk(1, "%s() tuner_type = 0x%x tuner_addr = 0x%x\n", 740 dprintk(1, "%s() tuner_type = 0x%x tuner_addr = 0x%x\n",
737 __FUNCTION__, dev->tuner_type, dev->tuner_addr); 741 __func__, dev->tuner_type, dev->tuner_addr);
738 dprintk(1, "%s() radio_type = 0x%x radio_addr = 0x%x\n", 742 dprintk(1, "%s() radio_type = 0x%x radio_addr = 0x%x\n",
739 __FUNCTION__, dev->radio_type, dev->radio_addr); 743 __func__, dev->radio_type, dev->radio_addr);
740 744
741 /* init hardware */ 745 /* init hardware */
742 cx23885_reset(dev); 746 cx23885_reset(dev);
@@ -744,28 +748,43 @@ static int cx23885_dev_setup(struct cx23885_dev *dev)
744 cx23885_i2c_register(&dev->i2c_bus[0]); 748 cx23885_i2c_register(&dev->i2c_bus[0]);
745 cx23885_i2c_register(&dev->i2c_bus[1]); 749 cx23885_i2c_register(&dev->i2c_bus[1]);
746 cx23885_i2c_register(&dev->i2c_bus[2]); 750 cx23885_i2c_register(&dev->i2c_bus[2]);
747 cx23885_call_i2c_clients (&dev->i2c_bus[0], TUNER_SET_STANDBY, NULL);
748 cx23885_card_setup(dev); 751 cx23885_card_setup(dev);
752 cx23885_call_i2c_clients (&dev->i2c_bus[0], TUNER_SET_STANDBY, NULL);
749 cx23885_ir_init(dev); 753 cx23885_ir_init(dev);
750 754
751 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) { 755 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) {
752 if (cx23885_video_register(dev) < 0) { 756 if (cx23885_video_register(dev) < 0) {
753 printk(KERN_ERR "%s() Failed to register analog " 757 printk(KERN_ERR "%s() Failed to register analog "
754 "video adapters on VID_A\n", __FUNCTION__); 758 "video adapters on VID_A\n", __func__);
755 } 759 }
756 } 760 }
757 761
758 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) { 762 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
759 if (cx23885_dvb_register(&dev->ts1) < 0) { 763 if (cx23885_dvb_register(&dev->ts1) < 0) {
760 printk(KERN_ERR "%s() Failed to register dvb adapters on VID_B\n", 764 printk(KERN_ERR "%s() Failed to register dvb adapters on VID_B\n",
761 __FUNCTION__); 765 __func__);
766 }
767 } else
768 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER) {
769 if (cx23885_417_register(dev) < 0) {
770 printk(KERN_ERR
771 "%s() Failed to register 417 on VID_B\n",
772 __func__);
762 } 773 }
763 } 774 }
764 775
765 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) { 776 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
766 if (cx23885_dvb_register(&dev->ts2) < 0) { 777 if (cx23885_dvb_register(&dev->ts2) < 0) {
767 printk(KERN_ERR "%s() Failed to register dvb adapters on VID_C\n", 778 printk(KERN_ERR
768 __FUNCTION__); 779 "%s() Failed to register dvb on VID_C\n",
780 __func__);
781 }
782 } else
783 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER) {
784 if (cx23885_417_register(dev) < 0) {
785 printk(KERN_ERR
786 "%s() Failed to register 417 on VID_C\n",
787 __func__);
769 } 788 }
770 } 789 }
771 790
@@ -785,12 +804,18 @@ static void cx23885_dev_unregister(struct cx23885_dev *dev)
785 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) 804 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO)
786 cx23885_video_unregister(dev); 805 cx23885_video_unregister(dev);
787 806
788 if(cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) 807 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
789 cx23885_dvb_unregister(&dev->ts1); 808 cx23885_dvb_unregister(&dev->ts1);
790 809
791 if(cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) 810 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
811 cx23885_417_unregister(dev);
812
813 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
792 cx23885_dvb_unregister(&dev->ts2); 814 cx23885_dvb_unregister(&dev->ts2);
793 815
816 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
817 cx23885_417_unregister(dev);
818
794 cx23885_i2c_unregister(&dev->i2c_bus[2]); 819 cx23885_i2c_unregister(&dev->i2c_bus[2]);
795 cx23885_i2c_unregister(&dev->i2c_bus[1]); 820 cx23885_i2c_unregister(&dev->i2c_bus[1]);
796 cx23885_i2c_unregister(&dev->i2c_bus[0]); 821 cx23885_i2c_unregister(&dev->i2c_bus[0]);
@@ -952,7 +977,7 @@ void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
952 videobuf_waiton(&buf->vb, 0, 0); 977 videobuf_waiton(&buf->vb, 0, 0);
953 videobuf_dma_unmap(q, dma); 978 videobuf_dma_unmap(q, dma);
954 videobuf_dma_free(dma); 979 videobuf_dma_free(dma);
955 btcx_riscmem_free((struct pci_dev *)q->dev, &buf->risc); 980 btcx_riscmem_free(to_pci_dev(q->dev), &buf->risc);
956 buf->vb.state = VIDEOBUF_NEEDS_INIT; 981 buf->vb.state = VIDEOBUF_NEEDS_INIT;
957} 982}
958 983
@@ -960,50 +985,50 @@ static void cx23885_tsport_reg_dump(struct cx23885_tsport *port)
960{ 985{
961 struct cx23885_dev *dev = port->dev; 986 struct cx23885_dev *dev = port->dev;
962 987
963 dprintk(1, "%s() Register Dump\n", __FUNCTION__); 988 dprintk(1, "%s() Register Dump\n", __func__);
964 dprintk(1, "%s() DEV_CNTRL2 0x%08X\n", __FUNCTION__, 989 dprintk(1, "%s() DEV_CNTRL2 0x%08X\n", __func__,
965 cx_read(DEV_CNTRL2)); 990 cx_read(DEV_CNTRL2));
966 dprintk(1, "%s() PCI_INT_MSK 0x%08X\n", __FUNCTION__, 991 dprintk(1, "%s() PCI_INT_MSK 0x%08X\n", __func__,
967 cx_read(PCI_INT_MSK)); 992 cx_read(PCI_INT_MSK));
968 dprintk(1, "%s() AUD_INT_INT_MSK 0x%08X\n", __FUNCTION__, 993 dprintk(1, "%s() AUD_INT_INT_MSK 0x%08X\n", __func__,
969 cx_read(AUDIO_INT_INT_MSK)); 994 cx_read(AUDIO_INT_INT_MSK));
970 dprintk(1, "%s() AUD_INT_DMA_CTL 0x%08X\n", __FUNCTION__, 995 dprintk(1, "%s() AUD_INT_DMA_CTL 0x%08X\n", __func__,
971 cx_read(AUD_INT_DMA_CTL)); 996 cx_read(AUD_INT_DMA_CTL));
972 dprintk(1, "%s() AUD_EXT_INT_MSK 0x%08X\n", __FUNCTION__, 997 dprintk(1, "%s() AUD_EXT_INT_MSK 0x%08X\n", __func__,
973 cx_read(AUDIO_EXT_INT_MSK)); 998 cx_read(AUDIO_EXT_INT_MSK));
974 dprintk(1, "%s() AUD_EXT_DMA_CTL 0x%08X\n", __FUNCTION__, 999 dprintk(1, "%s() AUD_EXT_DMA_CTL 0x%08X\n", __func__,
975 cx_read(AUD_EXT_DMA_CTL)); 1000 cx_read(AUD_EXT_DMA_CTL));
976 dprintk(1, "%s() PAD_CTRL 0x%08X\n", __FUNCTION__, 1001 dprintk(1, "%s() PAD_CTRL 0x%08X\n", __func__,
977 cx_read(PAD_CTRL)); 1002 cx_read(PAD_CTRL));
978 dprintk(1, "%s() ALT_PIN_OUT_SEL 0x%08X\n", __FUNCTION__, 1003 dprintk(1, "%s() ALT_PIN_OUT_SEL 0x%08X\n", __func__,
979 cx_read(ALT_PIN_OUT_SEL)); 1004 cx_read(ALT_PIN_OUT_SEL));
980 dprintk(1, "%s() GPIO2 0x%08X\n", __FUNCTION__, 1005 dprintk(1, "%s() GPIO2 0x%08X\n", __func__,
981 cx_read(GPIO2)); 1006 cx_read(GPIO2));
982 dprintk(1, "%s() gpcnt(0x%08X) 0x%08X\n", __FUNCTION__, 1007 dprintk(1, "%s() gpcnt(0x%08X) 0x%08X\n", __func__,
983 port->reg_gpcnt, cx_read(port->reg_gpcnt)); 1008 port->reg_gpcnt, cx_read(port->reg_gpcnt));
984 dprintk(1, "%s() gpcnt_ctl(0x%08X) 0x%08x\n", __FUNCTION__, 1009 dprintk(1, "%s() gpcnt_ctl(0x%08X) 0x%08x\n", __func__,
985 port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl)); 1010 port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl));
986 dprintk(1, "%s() dma_ctl(0x%08X) 0x%08x\n", __FUNCTION__, 1011 dprintk(1, "%s() dma_ctl(0x%08X) 0x%08x\n", __func__,
987 port->reg_dma_ctl, cx_read(port->reg_dma_ctl)); 1012 port->reg_dma_ctl, cx_read(port->reg_dma_ctl));
988 dprintk(1, "%s() src_sel(0x%08X) 0x%08x\n", __FUNCTION__, 1013 dprintk(1, "%s() src_sel(0x%08X) 0x%08x\n", __func__,
989 port->reg_src_sel, cx_read(port->reg_src_sel)); 1014 port->reg_src_sel, cx_read(port->reg_src_sel));
990 dprintk(1, "%s() lngth(0x%08X) 0x%08x\n", __FUNCTION__, 1015 dprintk(1, "%s() lngth(0x%08X) 0x%08x\n", __func__,
991 port->reg_lngth, cx_read(port->reg_lngth)); 1016 port->reg_lngth, cx_read(port->reg_lngth));
992 dprintk(1, "%s() hw_sop_ctrl(0x%08X) 0x%08x\n", __FUNCTION__, 1017 dprintk(1, "%s() hw_sop_ctrl(0x%08X) 0x%08x\n", __func__,
993 port->reg_hw_sop_ctrl, cx_read(port->reg_hw_sop_ctrl)); 1018 port->reg_hw_sop_ctrl, cx_read(port->reg_hw_sop_ctrl));
994 dprintk(1, "%s() gen_ctrl(0x%08X) 0x%08x\n", __FUNCTION__, 1019 dprintk(1, "%s() gen_ctrl(0x%08X) 0x%08x\n", __func__,
995 port->reg_gen_ctrl, cx_read(port->reg_gen_ctrl)); 1020 port->reg_gen_ctrl, cx_read(port->reg_gen_ctrl));
996 dprintk(1, "%s() bd_pkt_status(0x%08X) 0x%08x\n", __FUNCTION__, 1021 dprintk(1, "%s() bd_pkt_status(0x%08X) 0x%08x\n", __func__,
997 port->reg_bd_pkt_status, cx_read(port->reg_bd_pkt_status)); 1022 port->reg_bd_pkt_status, cx_read(port->reg_bd_pkt_status));
998 dprintk(1, "%s() sop_status(0x%08X) 0x%08x\n", __FUNCTION__, 1023 dprintk(1, "%s() sop_status(0x%08X) 0x%08x\n", __func__,
999 port->reg_sop_status, cx_read(port->reg_sop_status)); 1024 port->reg_sop_status, cx_read(port->reg_sop_status));
1000 dprintk(1, "%s() fifo_ovfl_stat(0x%08X) 0x%08x\n", __FUNCTION__, 1025 dprintk(1, "%s() fifo_ovfl_stat(0x%08X) 0x%08x\n", __func__,
1001 port->reg_fifo_ovfl_stat, cx_read(port->reg_fifo_ovfl_stat)); 1026 port->reg_fifo_ovfl_stat, cx_read(port->reg_fifo_ovfl_stat));
1002 dprintk(1, "%s() vld_misc(0x%08X) 0x%08x\n", __FUNCTION__, 1027 dprintk(1, "%s() vld_misc(0x%08X) 0x%08x\n", __func__,
1003 port->reg_vld_misc, cx_read(port->reg_vld_misc)); 1028 port->reg_vld_misc, cx_read(port->reg_vld_misc));
1004 dprintk(1, "%s() ts_clk_en(0x%08X) 0x%08x\n", __FUNCTION__, 1029 dprintk(1, "%s() ts_clk_en(0x%08X) 0x%08x\n", __func__,
1005 port->reg_ts_clk_en, cx_read(port->reg_ts_clk_en)); 1030 port->reg_ts_clk_en, cx_read(port->reg_ts_clk_en));
1006 dprintk(1, "%s() ts_int_msk(0x%08X) 0x%08x\n", __FUNCTION__, 1031 dprintk(1, "%s() ts_int_msk(0x%08X) 0x%08x\n", __func__,
1007 port->reg_ts_int_msk, cx_read(port->reg_ts_int_msk)); 1032 port->reg_ts_int_msk, cx_read(port->reg_ts_int_msk));
1008} 1033}
1009 1034
@@ -1012,8 +1037,9 @@ static int cx23885_start_dma(struct cx23885_tsport *port,
1012 struct cx23885_buffer *buf) 1037 struct cx23885_buffer *buf)
1013{ 1038{
1014 struct cx23885_dev *dev = port->dev; 1039 struct cx23885_dev *dev = port->dev;
1040 u32 reg;
1015 1041
1016 dprintk(1, "%s() w: %d, h: %d, f: %d\n", __FUNCTION__, 1042 dprintk(1, "%s() w: %d, h: %d, f: %d\n", __func__,
1017 buf->vb.width, buf->vb.height, buf->vb.field); 1043 buf->vb.width, buf->vb.height, buf->vb.field);
1018 1044
1019 /* setup fifo + format */ 1045 /* setup fifo + format */
@@ -1031,21 +1057,24 @@ static int cx23885_start_dma(struct cx23885_tsport *port,
1031 if ( (!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) && 1057 if ( (!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
1032 (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB)) ) { 1058 (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB)) ) {
1033 printk( "%s() Failed. Unsupported value in .portb/c (0x%08x)/(0x%08x)\n", 1059 printk( "%s() Failed. Unsupported value in .portb/c (0x%08x)/(0x%08x)\n",
1034 __FUNCTION__, 1060 __func__,
1035 cx23885_boards[dev->board].portb, 1061 cx23885_boards[dev->board].portb,
1036 cx23885_boards[dev->board].portc ); 1062 cx23885_boards[dev->board].portc );
1037 return -EINVAL; 1063 return -EINVAL;
1038 } 1064 }
1039 1065
1066 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1067 cx23885_av_clk(dev, 0);
1068
1040 udelay(100); 1069 udelay(100);
1041 1070
1042 /* If the port supports SRC SELECT, configure it */ 1071 /* If the port supports SRC SELECT, configure it */
1043 if(port->reg_src_sel) 1072 if(port->reg_src_sel)
1044 cx_write(port->reg_src_sel, port->src_sel_val); 1073 cx_write(port->reg_src_sel, port->src_sel_val);
1045 1074
1046 cx_write(port->reg_hw_sop_ctrl, 0x47 << 16 | 188 << 4); 1075 cx_write(port->reg_hw_sop_ctrl, port->hw_sop_ctrl_val);
1047 cx_write(port->reg_ts_clk_en, port->ts_clk_en_val); 1076 cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1048 cx_write(port->reg_vld_misc, 0x00); 1077 cx_write(port->reg_vld_misc, port->vld_misc_val);
1049 cx_write(port->reg_gen_ctrl, port->gen_ctrl_val); 1078 cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1050 udelay(100); 1079 udelay(100);
1051 1080
@@ -1054,11 +1083,26 @@ static int cx23885_start_dma(struct cx23885_tsport *port,
1054 cx_write(port->reg_gpcnt_ctl, 3); 1083 cx_write(port->reg_gpcnt_ctl, 3);
1055 q->count = 1; 1084 q->count = 1;
1056 1085
1086 if (cx23885_boards[dev->board].portb & CX23885_MPEG_ENCODER) {
1087
1088 reg = cx_read(PAD_CTRL);
1089 reg = reg & ~0x1; /* Clear TS1_OE */
1090
1091 /* FIXME, bit 2 writing here is questionable */
1092 /* set TS1_SOP_OE and TS1_OE_HI */
1093 reg = reg | 0xa;
1094 cx_write(PAD_CTRL, reg);
1095
1096 /* FIXME and these two registers should be documented. */
1097 cx_write(CLK_DELAY, cx_read(CLK_DELAY) | 0x80000011);
1098 cx_write(ALT_PIN_OUT_SEL, 0x10100045);
1099 }
1100
1057 switch(dev->bridge) { 1101 switch(dev->bridge) {
1058 case CX23885_BRIDGE_885: 1102 case CX23885_BRIDGE_885:
1059 case CX23885_BRIDGE_887: 1103 case CX23885_BRIDGE_887:
1060 /* enable irqs */ 1104 /* enable irqs */
1061 dprintk(1, "%s() enabling TS int's and DMA\n", __FUNCTION__ ); 1105 dprintk(1, "%s() enabling TS int's and DMA\n", __func__ );
1062 cx_set(port->reg_ts_int_msk, port->ts_int_msk_val); 1106 cx_set(port->reg_ts_int_msk, port->ts_int_msk_val);
1063 cx_set(port->reg_dma_ctl, port->dma_ctl_val); 1107 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1064 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask); 1108 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
@@ -1069,6 +1113,9 @@ static int cx23885_start_dma(struct cx23885_tsport *port,
1069 1113
1070 cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */ 1114 cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1071 1115
1116 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1117 cx23885_av_clk(dev, 1);
1118
1072 if (debug > 4) 1119 if (debug > 4)
1073 cx23885_tsport_reg_dump(port); 1120 cx23885_tsport_reg_dump(port);
1074 1121
@@ -1078,12 +1125,32 @@ static int cx23885_start_dma(struct cx23885_tsport *port,
1078static int cx23885_stop_dma(struct cx23885_tsport *port) 1125static int cx23885_stop_dma(struct cx23885_tsport *port)
1079{ 1126{
1080 struct cx23885_dev *dev = port->dev; 1127 struct cx23885_dev *dev = port->dev;
1081 dprintk(1, "%s()\n", __FUNCTION__); 1128 u32 reg;
1129
1130 dprintk(1, "%s()\n", __func__);
1082 1131
1083 /* Stop interrupts and DMA */ 1132 /* Stop interrupts and DMA */
1084 cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val); 1133 cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1085 cx_clear(port->reg_dma_ctl, port->dma_ctl_val); 1134 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1086 1135
1136 if (cx23885_boards[dev->board].portb & CX23885_MPEG_ENCODER) {
1137
1138 reg = cx_read(PAD_CTRL);
1139
1140 /* Set TS1_OE */
1141 reg = reg | 0x1;
1142
1143 /* clear TS1_SOP_OE and TS1_OE_HI */
1144 reg = reg & ~0xa;
1145 cx_write(PAD_CTRL, reg);
1146 cx_write(port->reg_src_sel, 0);
1147 cx_write(port->reg_gen_ctrl, 8);
1148
1149 }
1150
1151 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1152 cx23885_av_clk(dev, 0);
1153
1087 return 0; 1154 return 0;
1088} 1155}
1089 1156
@@ -1093,13 +1160,13 @@ int cx23885_restart_queue(struct cx23885_tsport *port,
1093 struct cx23885_dev *dev = port->dev; 1160 struct cx23885_dev *dev = port->dev;
1094 struct cx23885_buffer *buf; 1161 struct cx23885_buffer *buf;
1095 1162
1096 dprintk(5, "%s()\n", __FUNCTION__); 1163 dprintk(5, "%s()\n", __func__);
1097 if (list_empty(&q->active)) 1164 if (list_empty(&q->active))
1098 { 1165 {
1099 struct cx23885_buffer *prev; 1166 struct cx23885_buffer *prev;
1100 prev = NULL; 1167 prev = NULL;
1101 1168
1102 dprintk(5, "%s() queue is empty\n", __FUNCTION__); 1169 dprintk(5, "%s() queue is empty\n", __func__);
1103 1170
1104 for (;;) { 1171 for (;;) {
1105 if (list_empty(&q->queued)) 1172 if (list_empty(&q->queued))
@@ -1154,7 +1221,7 @@ int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1154 int size = port->ts_packet_size * port->ts_packet_count; 1221 int size = port->ts_packet_size * port->ts_packet_count;
1155 int rc; 1222 int rc;
1156 1223
1157 dprintk(1, "%s: %p\n", __FUNCTION__, buf); 1224 dprintk(1, "%s: %p\n", __func__, buf);
1158 if (0 != buf->vb.baddr && buf->vb.bsize < size) 1225 if (0 != buf->vb.baddr && buf->vb.bsize < size)
1159 return -EINVAL; 1226 return -EINVAL;
1160 1227
@@ -1197,7 +1264,7 @@ void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1197 buf->count = cx88q->count++; 1264 buf->count = cx88q->count++;
1198 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT); 1265 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1199 dprintk(1, "[%p/%d] %s - first active\n", 1266 dprintk(1, "[%p/%d] %s - first active\n",
1200 buf, buf->vb.i, __FUNCTION__); 1267 buf, buf->vb.i, __func__);
1201 } else { 1268 } else {
1202 dprintk( 1, "queue is not empty - append to active\n" ); 1269 dprintk( 1, "queue is not empty - append to active\n" );
1203 prev = list_entry(cx88q->active.prev, struct cx23885_buffer, 1270 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
@@ -1208,7 +1275,7 @@ void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1208 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma); 1275 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1209 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */ 1276 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1210 dprintk( 1, "[%p/%d] %s - append to active\n", 1277 dprintk( 1, "[%p/%d] %s - append to active\n",
1211 buf, buf->vb.i, __FUNCTION__); 1278 buf, buf->vb.i, __func__);
1212 } 1279 }
1213} 1280}
1214 1281
@@ -1239,13 +1306,23 @@ static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1239 spin_unlock_irqrestore(&port->slock, flags); 1306 spin_unlock_irqrestore(&port->slock, flags);
1240} 1307}
1241 1308
1309void cx23885_cancel_buffers(struct cx23885_tsport *port)
1310{
1311 struct cx23885_dev *dev = port->dev;
1312 struct cx23885_dmaqueue *q = &port->mpegq;
1313
1314 dprintk(1, "%s()\n", __FUNCTION__);
1315 del_timer_sync(&q->timeout);
1316 cx23885_stop_dma(port);
1317 do_cancel_buffers(port, "cancel", 0);
1318}
1242 1319
1243static void cx23885_timeout(unsigned long data) 1320static void cx23885_timeout(unsigned long data)
1244{ 1321{
1245 struct cx23885_tsport *port = (struct cx23885_tsport *)data; 1322 struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1246 struct cx23885_dev *dev = port->dev; 1323 struct cx23885_dev *dev = port->dev;
1247 1324
1248 dprintk(1, "%s()\n",__FUNCTION__); 1325 dprintk(1, "%s()\n",__func__);
1249 1326
1250 if (debug > 5) 1327 if (debug > 5)
1251 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]); 1328 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
@@ -1254,16 +1331,77 @@ static void cx23885_timeout(unsigned long data)
1254 do_cancel_buffers(port, "timeout", 1); 1331 do_cancel_buffers(port, "timeout", 1);
1255} 1332}
1256 1333
1334int cx23885_irq_417(struct cx23885_dev *dev, u32 status)
1335{
1336 /* FIXME: port1 assumption here. */
1337 struct cx23885_tsport *port = &dev->ts1;
1338 int count = 0;
1339 int handled = 0;
1340
1341 if (status == 0)
1342 return handled;
1343
1344 count = cx_read(port->reg_gpcnt);
1345 dprintk(7, "status: 0x%08x mask: 0x%08x count: 0x%x\n",
1346 status, cx_read(port->reg_ts_int_msk), count);
1347
1348 if ((status & VID_B_MSK_BAD_PKT) ||
1349 (status & VID_B_MSK_OPC_ERR) ||
1350 (status & VID_B_MSK_VBI_OPC_ERR) ||
1351 (status & VID_B_MSK_SYNC) ||
1352 (status & VID_B_MSK_VBI_SYNC) ||
1353 (status & VID_B_MSK_OF) ||
1354 (status & VID_B_MSK_VBI_OF)) {
1355 printk(KERN_ERR "%s: V4L mpeg risc op code error, status "
1356 "= 0x%x\n", dev->name, status);
1357 if (status & VID_B_MSK_BAD_PKT)
1358 dprintk(1, " VID_B_MSK_BAD_PKT\n");
1359 if (status & VID_B_MSK_OPC_ERR)
1360 dprintk(1, " VID_B_MSK_OPC_ERR\n");
1361 if (status & VID_B_MSK_VBI_OPC_ERR)
1362 dprintk(1, " VID_B_MSK_VBI_OPC_ERR\n");
1363 if (status & VID_B_MSK_SYNC)
1364 dprintk(1, " VID_B_MSK_SYNC\n");
1365 if (status & VID_B_MSK_VBI_SYNC)
1366 dprintk(1, " VID_B_MSK_VBI_SYNC\n");
1367 if (status & VID_B_MSK_OF)
1368 dprintk(1, " VID_B_MSK_OF\n");
1369 if (status & VID_B_MSK_VBI_OF)
1370 dprintk(1, " VID_B_MSK_VBI_OF\n");
1371
1372 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1373 cx23885_sram_channel_dump(dev,
1374 &dev->sram_channels[port->sram_chno]);
1375 cx23885_417_check_encoder(dev);
1376 } else if (status & VID_B_MSK_RISCI1) {
1377 dprintk(7, " VID_B_MSK_RISCI1\n");
1378 spin_lock(&port->slock);
1379 cx23885_wakeup(port, &port->mpegq, count);
1380 spin_unlock(&port->slock);
1381 } else if (status & VID_B_MSK_RISCI2) {
1382 dprintk(7, " VID_B_MSK_RISCI2\n");
1383 spin_lock(&port->slock);
1384 cx23885_restart_queue(port, &port->mpegq);
1385 spin_unlock(&port->slock);
1386 }
1387 if (status) {
1388 cx_write(port->reg_ts_int_stat, status);
1389 handled = 1;
1390 }
1391
1392 return handled;
1393}
1394
1257static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status) 1395static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
1258{ 1396{
1259 struct cx23885_dev *dev = port->dev; 1397 struct cx23885_dev *dev = port->dev;
1260 int handled = 0; 1398 int handled = 0;
1261 u32 count; 1399 u32 count;
1262 1400
1263 if ( (status & VID_BC_MSK_OPC_ERR) || 1401 if ((status & VID_BC_MSK_OPC_ERR) ||
1264 (status & VID_BC_MSK_BAD_PKT) || 1402 (status & VID_BC_MSK_BAD_PKT) ||
1265 (status & VID_BC_MSK_SYNC) || 1403 (status & VID_BC_MSK_SYNC) ||
1266 (status & VID_BC_MSK_OF)) 1404 (status & VID_BC_MSK_OF))
1267 { 1405 {
1268 if (status & VID_BC_MSK_OPC_ERR) 1406 if (status & VID_BC_MSK_OPC_ERR)
1269 dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n", VID_BC_MSK_OPC_ERR); 1407 dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n", VID_BC_MSK_OPC_ERR);
@@ -1277,7 +1415,8 @@ static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
1277 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name); 1415 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1278 1416
1279 cx_clear(port->reg_dma_ctl, port->dma_ctl_val); 1417 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1280 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]); 1418 cx23885_sram_channel_dump(dev,
1419 &dev->sram_channels[port->sram_chno]);
1281 1420
1282 } else if (status & VID_BC_MSK_RISCI1) { 1421 } else if (status & VID_BC_MSK_RISCI1) {
1283 1422
@@ -1378,11 +1517,17 @@ static irqreturn_t cx23885_irq(int irq, void *dev_id)
1378 if (ts1_status) { 1517 if (ts1_status) {
1379 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) 1518 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
1380 handled += cx23885_irq_ts(ts1, ts1_status); 1519 handled += cx23885_irq_ts(ts1, ts1_status);
1520 else
1521 if (cx23885_boards[dev->board].portb == CX23885_MPEG_ENCODER)
1522 handled += cx23885_irq_417(dev, ts1_status);
1381 } 1523 }
1382 1524
1383 if (ts2_status) { 1525 if (ts2_status) {
1384 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) 1526 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
1385 handled += cx23885_irq_ts(ts2, ts2_status); 1527 handled += cx23885_irq_ts(ts2, ts2_status);
1528 else
1529 if (cx23885_boards[dev->board].portc == CX23885_MPEG_ENCODER)
1530 handled += cx23885_irq_417(dev, ts2_status);
1386 } 1531 }
1387 1532
1388 if (vida_status) 1533 if (vida_status)
@@ -1422,7 +1567,8 @@ static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
1422 printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, " 1567 printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1423 "latency: %d, mmio: 0x%llx\n", dev->name, 1568 "latency: %d, mmio: 0x%llx\n", dev->name,
1424 pci_name(pci_dev), dev->pci_rev, pci_dev->irq, 1569 pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1425 dev->pci_lat, (unsigned long long)pci_resource_start(pci_dev,0)); 1570 dev->pci_lat,
1571 (unsigned long long)pci_resource_start(pci_dev, 0));
1426 1572
1427 pci_set_master(pci_dev); 1573 pci_set_master(pci_dev);
1428 if (!pci_dma_supported(pci_dev, 0xffffffff)) { 1574 if (!pci_dma_supported(pci_dev, 0xffffffff)) {
diff --git a/drivers/media/video/cx23885/cx23885-dvb.c b/drivers/media/video/cx23885/cx23885-dvb.c
index ed465c007cea..870d6e197d65 100644
--- a/drivers/media/video/cx23885/cx23885-dvb.c
+++ b/drivers/media/video/cx23885/cx23885-dvb.c
@@ -36,9 +36,12 @@
36#include "tda18271.h" 36#include "tda18271.h"
37#include "lgdt330x.h" 37#include "lgdt330x.h"
38#include "xc5000.h" 38#include "xc5000.h"
39#include "tda10048.h"
39#include "dvb-pll.h" 40#include "dvb-pll.h"
40#include "tuner-xc2028.h" 41#include "tuner-xc2028.h"
41#include "tuner-xc2028-types.h" 42#include "tuner-simple.h"
43#include "dib7000p.h"
44#include "dibx000_common.h"
42 45
43static unsigned int debug; 46static unsigned int debug;
44 47
@@ -53,6 +56,8 @@ static unsigned int alt_tuner;
53module_param(alt_tuner, int, 0644); 56module_param(alt_tuner, int, 0644);
54MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration"); 57MODULE_PARM_DESC(alt_tuner, "Enable alternate tuner configuration");
55 58
59DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
60
56/* ------------------------------------------------------------------ */ 61/* ------------------------------------------------------------------ */
57 62
58static int dvb_buf_setup(struct videobuf_queue *q, 63static int dvb_buf_setup(struct videobuf_queue *q,
@@ -104,6 +109,13 @@ static struct s5h1409_config hauppauge_generic_config = {
104 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK, 109 .mpeg_timing = S5H1409_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK,
105}; 110};
106 111
112static struct tda10048_config hauppauge_hvr1200_config = {
113 .demod_address = 0x10 >> 1,
114 .output_mode = TDA10048_SERIAL_OUTPUT,
115 .fwbulkwritelen = TDA10048_BULKWRITE_200,
116 .inversion = TDA10048_INVERSION_ON
117};
118
107static struct s5h1409_config hauppauge_ezqam_config = { 119static struct s5h1409_config hauppauge_ezqam_config = {
108 .demod_address = 0x32 >> 1, 120 .demod_address = 0x32 >> 1,
109 .output_mode = S5H1409_SERIAL_OUTPUT, 121 .output_mode = S5H1409_SERIAL_OUTPUT,
@@ -164,8 +176,10 @@ static struct tda829x_config tda829x_no_probe = {
164}; 176};
165 177
166static struct tda18271_std_map hauppauge_tda18271_std_map = { 178static struct tda18271_std_map hauppauge_tda18271_std_map = {
167 .atsc_6 = { .if_freq = 5380, .std_bits = 0x1b }, 179 .atsc_6 = { .if_freq = 5380, .agc_mode = 3, .std = 3,
168 .qam_6 = { .if_freq = 4000, .std_bits = 0x18 }, 180 .if_lvl = 6, .rfagc_top = 0x37 },
181 .qam_6 = { .if_freq = 4000, .agc_mode = 3, .std = 0,
182 .if_lvl = 6, .rfagc_top = 0x37 },
169}; 183};
170 184
171static struct tda18271_config hauppauge_tda18271_config = { 185static struct tda18271_config hauppauge_tda18271_config = {
@@ -173,6 +187,96 @@ static struct tda18271_config hauppauge_tda18271_config = {
173 .gate = TDA18271_GATE_ANALOG, 187 .gate = TDA18271_GATE_ANALOG,
174}; 188};
175 189
190static struct tda18271_config hauppauge_hvr1200_tuner_config = {
191 .gate = TDA18271_GATE_ANALOG,
192};
193
194struct dibx000_agc_config xc3028_agc_config = {
195 BAND_VHF | BAND_UHF, /* band_caps */
196
197 /* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
198 * P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
199 * P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
200 * P_agc_nb_est=2, P_agc_write=0
201 */
202 (0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
203 (3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), /* setup */
204
205 712, /* inv_gain */
206 21, /* time_stabiliz */
207
208 0, /* alpha_level */
209 118, /* thlock */
210
211 0, /* wbd_inv */
212 2867, /* wbd_ref */
213 0, /* wbd_sel */
214 2, /* wbd_alpha */
215
216 0, /* agc1_max */
217 0, /* agc1_min */
218 39718, /* agc2_max */
219 9930, /* agc2_min */
220 0, /* agc1_pt1 */
221 0, /* agc1_pt2 */
222 0, /* agc1_pt3 */
223 0, /* agc1_slope1 */
224 0, /* agc1_slope2 */
225 0, /* agc2_pt1 */
226 128, /* agc2_pt2 */
227 29, /* agc2_slope1 */
228 29, /* agc2_slope2 */
229
230 17, /* alpha_mant */
231 27, /* alpha_exp */
232 23, /* beta_mant */
233 51, /* beta_exp */
234
235 1, /* perform_agc_softsplit */
236};
237
238/* PLL Configuration for COFDM BW_MHz = 8.000000
239 * With external clock = 30.000000 */
240struct dibx000_bandwidth_config xc3028_bw_config = {
241 60000, /* internal */
242 30000, /* sampling */
243 1, /* pll_cfg: prediv */
244 8, /* pll_cfg: ratio */
245 3, /* pll_cfg: range */
246 1, /* pll_cfg: reset */
247 0, /* pll_cfg: bypass */
248 0, /* misc: refdiv */
249 0, /* misc: bypclk_div */
250 1, /* misc: IO_CLK_en_core */
251 1, /* misc: ADClkSrc */
252 0, /* misc: modulo */
253 (3 << 14) | (1 << 12) | (524 << 0), /* sad_cfg: refsel, sel, freq_15k */
254 (1 << 25) | 5816102, /* ifreq = 5.200000 MHz */
255 20452225, /* timf */
256 30000000 /* xtal_hz */
257};
258
259static struct dib7000p_config hauppauge_hvr1400_dib7000_config = {
260 .output_mpeg2_in_188_bytes = 1,
261 .hostbus_diversity = 1,
262 .tuner_is_baseband = 0,
263 .update_lna = NULL,
264
265 .agc_config_count = 1,
266 .agc = &xc3028_agc_config,
267 .bw = &xc3028_bw_config,
268
269 .gpio_dir = DIB7000P_GPIO_DEFAULT_DIRECTIONS,
270 .gpio_val = DIB7000P_GPIO_DEFAULT_VALUES,
271 .gpio_pwm_pos = DIB7000P_GPIO_DEFAULT_PWM_POS,
272
273 .pwm_freq_div = 0,
274 .agc_control = NULL,
275 .spur_protect = 0,
276
277 .output_mode = OUTMODE_MPEG2_SERIAL,
278};
279
176static int cx23885_hvr1500_xc3028_callback(void *ptr, int command, int arg) 280static int cx23885_hvr1500_xc3028_callback(void *ptr, int command, int arg)
177{ 281{
178 struct cx23885_tsport *port = ptr; 282 struct cx23885_tsport *port = ptr;
@@ -182,7 +286,7 @@ static int cx23885_hvr1500_xc3028_callback(void *ptr, int command, int arg)
182 case XC2028_TUNER_RESET: 286 case XC2028_TUNER_RESET:
183 /* Send the tuner in then out of reset */ 287 /* Send the tuner in then out of reset */
184 /* GPIO-2 xc3028 tuner */ 288 /* GPIO-2 xc3028 tuner */
185 dprintk(1, "%s: XC2028_TUNER_RESET %d\n", __FUNCTION__, arg); 289 dprintk(1, "%s: XC2028_TUNER_RESET %d\n", __func__, arg);
186 290
187 cx_set(GP0_IO, 0x00040000); 291 cx_set(GP0_IO, 0x00040000);
188 cx_clear(GP0_IO, 0x00000004); 292 cx_clear(GP0_IO, 0x00000004);
@@ -192,10 +296,10 @@ static int cx23885_hvr1500_xc3028_callback(void *ptr, int command, int arg)
192 msleep(5); 296 msleep(5);
193 break; 297 break;
194 case XC2028_RESET_CLK: 298 case XC2028_RESET_CLK:
195 dprintk(1, "%s: XC2028_RESET_CLK %d\n", __FUNCTION__, arg); 299 dprintk(1, "%s: XC2028_RESET_CLK %d\n", __func__, arg);
196 break; 300 break;
197 default: 301 default:
198 dprintk(1, "%s: unknown command %d, arg %d\n", __FUNCTION__, 302 dprintk(1, "%s: unknown command %d, arg %d\n", __func__,
199 command, arg); 303 command, arg);
200 return -EINVAL; 304 return -EINVAL;
201 } 305 }
@@ -271,8 +375,9 @@ static int dvb_register(struct cx23885_tsport *port)
271 &fusionhdtv_5_express, 375 &fusionhdtv_5_express,
272 &i2c_bus->i2c_adap); 376 &i2c_bus->i2c_adap);
273 if (port->dvb.frontend != NULL) { 377 if (port->dvb.frontend != NULL) {
274 dvb_attach(dvb_pll_attach, port->dvb.frontend, 0x61, 378 dvb_attach(simple_tuner_attach, port->dvb.frontend,
275 &i2c_bus->i2c_adap, DVB_PLL_LG_TDVS_H06XF); 379 &i2c_bus->i2c_adap, 0x61,
380 TUNER_LG_TDVS_H06XF);
276 } 381 }
277 break; 382 break;
278 case CX23885_BOARD_HAUPPAUGE_HVR1500Q: 383 case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
@@ -297,13 +402,52 @@ static int dvb_register(struct cx23885_tsport *port)
297 struct xc2028_config cfg = { 402 struct xc2028_config cfg = {
298 .i2c_adap = &i2c_bus->i2c_adap, 403 .i2c_adap = &i2c_bus->i2c_adap,
299 .i2c_addr = 0x61, 404 .i2c_addr = 0x61,
300 .video_dev = port,
301 .callback = cx23885_hvr1500_xc3028_callback, 405 .callback = cx23885_hvr1500_xc3028_callback,
302 }; 406 };
303 static struct xc2028_ctrl ctl = { 407 static struct xc2028_ctrl ctl = {
304 .fname = "xc3028-v27.fw", 408 .fname = "xc3028-v27.fw",
305 .max_len = 64, 409 .max_len = 64,
306 .scode_table = OREN538, 410 .scode_table = XC3028_FE_OREN538,
411 };
412
413 fe = dvb_attach(xc2028_attach,
414 port->dvb.frontend, &cfg);
415 if (fe != NULL && fe->ops.tuner_ops.set_config != NULL)
416 fe->ops.tuner_ops.set_config(fe, &ctl);
417 }
418 break;
419 case CX23885_BOARD_HAUPPAUGE_HVR1200:
420 case CX23885_BOARD_HAUPPAUGE_HVR1700:
421 i2c_bus = &dev->i2c_bus[0];
422 port->dvb.frontend = dvb_attach(tda10048_attach,
423 &hauppauge_hvr1200_config,
424 &i2c_bus->i2c_adap);
425 if (port->dvb.frontend != NULL) {
426 dvb_attach(tda829x_attach, port->dvb.frontend,
427 &dev->i2c_bus[1].i2c_adap, 0x42,
428 &tda829x_no_probe);
429 dvb_attach(tda18271_attach, port->dvb.frontend,
430 0x60, &dev->i2c_bus[1].i2c_adap,
431 &hauppauge_hvr1200_tuner_config);
432 }
433 break;
434 case CX23885_BOARD_HAUPPAUGE_HVR1400:
435 i2c_bus = &dev->i2c_bus[0];
436 port->dvb.frontend = dvb_attach(dib7000p_attach,
437 &i2c_bus->i2c_adap,
438 0x12, &hauppauge_hvr1400_dib7000_config);
439 if (port->dvb.frontend != NULL) {
440 struct dvb_frontend *fe;
441 struct xc2028_config cfg = {
442 .i2c_adap = &dev->i2c_bus[1].i2c_adap,
443 .i2c_addr = 0x64,
444 .callback = cx23885_hvr1500_xc3028_callback,
445 };
446 static struct xc2028_ctrl ctl = {
447 .fname = "xc3028L-v36.fw",
448 .max_len = 64,
449 .demod = 5000,
450 .d2633 = 1
307 }; 451 };
308 452
309 fe = dvb_attach(xc2028_attach, 453 fe = dvb_attach(xc2028_attach,
@@ -330,7 +474,7 @@ static int dvb_register(struct cx23885_tsport *port)
330 474
331 /* register everything */ 475 /* register everything */
332 return videobuf_dvb_register(&port->dvb, THIS_MODULE, port, 476 return videobuf_dvb_register(&port->dvb, THIS_MODULE, port,
333 &dev->pci->dev); 477 &dev->pci->dev, adapter_nr);
334} 478}
335 479
336int cx23885_dvb_register(struct cx23885_tsport *port) 480int cx23885_dvb_register(struct cx23885_tsport *port)
@@ -338,7 +482,7 @@ int cx23885_dvb_register(struct cx23885_tsport *port)
338 struct cx23885_dev *dev = port->dev; 482 struct cx23885_dev *dev = port->dev;
339 int err; 483 int err;
340 484
341 dprintk(1, "%s\n", __FUNCTION__); 485 dprintk(1, "%s\n", __func__);
342 dprintk(1, " ->being probed by Card=%d Name=%s, PCI %02x:%02x\n", 486 dprintk(1, " ->being probed by Card=%d Name=%s, PCI %02x:%02x\n",
343 dev->board, 487 dev->board,
344 dev->name, 488 dev->name,
@@ -349,12 +493,12 @@ int cx23885_dvb_register(struct cx23885_tsport *port)
349 493
350 /* dvb stuff */ 494 /* dvb stuff */
351 printk("%s: cx23885 based dvb card\n", dev->name); 495 printk("%s: cx23885 based dvb card\n", dev->name);
352 videobuf_queue_pci_init(&port->dvb.dvbq, &dvb_qops, dev->pci, &port->slock, 496 videobuf_queue_sg_init(&port->dvb.dvbq, &dvb_qops, &dev->pci->dev, &port->slock,
353 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP, 497 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_TOP,
354 sizeof(struct cx23885_buffer), port); 498 sizeof(struct cx23885_buffer), port);
355 err = dvb_register(port); 499 err = dvb_register(port);
356 if (err != 0) 500 if (err != 0)
357 printk("%s() dvb_register failed err = %d\n", __FUNCTION__, err); 501 printk("%s() dvb_register failed err = %d\n", __func__, err);
358 502
359 return err; 503 return err;
360} 504}
diff --git a/drivers/media/video/cx23885/cx23885-i2c.c b/drivers/media/video/cx23885/cx23885-i2c.c
index 92fe0bd37c84..c6bb0a05bc1c 100644
--- a/drivers/media/video/cx23885/cx23885-i2c.c
+++ b/drivers/media/video/cx23885/cx23885-i2c.c
@@ -33,7 +33,7 @@ static unsigned int i2c_debug;
33module_param(i2c_debug, int, 0644); 33module_param(i2c_debug, int, 0644);
34MODULE_PARM_DESC(i2c_debug, "enable debug messages [i2c]"); 34MODULE_PARM_DESC(i2c_debug, "enable debug messages [i2c]");
35 35
36static unsigned int i2c_scan = 0; 36static unsigned int i2c_scan;
37module_param(i2c_scan, int, 0444); 37module_param(i2c_scan, int, 0444);
38MODULE_PARM_DESC(i2c_scan, "scan i2c bus at insmod time"); 38MODULE_PARM_DESC(i2c_scan, "scan i2c bus at insmod time");
39 39
@@ -87,10 +87,10 @@ static int i2c_sendbytes(struct i2c_adapter *i2c_adap,
87 int retval, cnt; 87 int retval, cnt;
88 88
89 if (joined_rlen) 89 if (joined_rlen)
90 dprintk(1, "%s(msg->wlen=%d, nextmsg->rlen=%d)\n", __FUNCTION__, 90 dprintk(1, "%s(msg->wlen=%d, nextmsg->rlen=%d)\n", __func__,
91 msg->len, joined_rlen); 91 msg->len, joined_rlen);
92 else 92 else
93 dprintk(1, "%s(msg->len=%d)\n", __FUNCTION__, msg->len); 93 dprintk(1, "%s(msg->len=%d)\n", __func__, msg->len);
94 94
95 /* Deal with i2c probe functions with zero payload */ 95 /* Deal with i2c probe functions with zero payload */
96 if (msg->len == 0) { 96 if (msg->len == 0) {
@@ -101,7 +101,7 @@ static int i2c_sendbytes(struct i2c_adapter *i2c_adap,
101 if (!i2c_slave_did_ack(i2c_adap)) 101 if (!i2c_slave_did_ack(i2c_adap))
102 return -EIO; 102 return -EIO;
103 103
104 dprintk(1, "%s() returns 0\n", __FUNCTION__); 104 dprintk(1, "%s() returns 0\n", __func__);
105 return 0; 105 return 0;
106 } 106 }
107 107
@@ -176,7 +176,7 @@ static int i2c_readbytes(struct i2c_adapter *i2c_adap,
176 176
177 177
178 if (i2c_debug && !joined) 178 if (i2c_debug && !joined)
179 dprintk(1, "%s(msg->len=%d)\n", __FUNCTION__, msg->len); 179 dprintk(1, "%s(msg->len=%d)\n", __func__, msg->len);
180 180
181 /* Deal with i2c probe functions with zero payload */ 181 /* Deal with i2c probe functions with zero payload */
182 if (msg->len == 0) { 182 if (msg->len == 0) {
@@ -188,7 +188,7 @@ static int i2c_readbytes(struct i2c_adapter *i2c_adap,
188 return -EIO; 188 return -EIO;
189 189
190 190
191 dprintk(1, "%s() returns 0\n", __FUNCTION__); 191 dprintk(1, "%s() returns 0\n", __func__);
192 return 0; 192 return 0;
193 } 193 }
194 194
@@ -238,11 +238,11 @@ static int i2c_xfer(struct i2c_adapter *i2c_adap,
238 struct cx23885_dev *dev = bus->dev; 238 struct cx23885_dev *dev = bus->dev;
239 int i, retval = 0; 239 int i, retval = 0;
240 240
241 dprintk(1, "%s(num = %d)\n", __FUNCTION__, num); 241 dprintk(1, "%s(num = %d)\n", __func__, num);
242 242
243 for (i = 0 ; i < num; i++) { 243 for (i = 0 ; i < num; i++) {
244 dprintk(1, "%s(num = %d) addr = 0x%02x len = 0x%x\n", 244 dprintk(1, "%s(num = %d) addr = 0x%02x len = 0x%x\n",
245 __FUNCTION__, num, msgs[i].addr, msgs[i].len); 245 __func__, num, msgs[i].addr, msgs[i].len);
246 if (msgs[i].flags & I2C_M_RD) { 246 if (msgs[i].flags & I2C_M_RD) {
247 /* read */ 247 /* read */
248 retval = i2c_readbytes(i2c_adap, &msgs[i], 0); 248 retval = i2c_readbytes(i2c_adap, &msgs[i], 0);
@@ -353,6 +353,8 @@ static struct i2c_client cx23885_i2c_client_template = {
353}; 353};
354 354
355static char *i2c_devs[128] = { 355static char *i2c_devs[128] = {
356 [0x10 >> 1] = "tda10048",
357 [0x12 >> 1] = "dib7000pc",
356 [ 0x1c >> 1 ] = "lgdt3303", 358 [ 0x1c >> 1 ] = "lgdt3303",
357 [ 0x86 >> 1 ] = "tda9887", 359 [ 0x86 >> 1 ] = "tda9887",
358 [ 0x32 >> 1 ] = "cx24227", 360 [ 0x32 >> 1 ] = "cx24227",
@@ -360,7 +362,8 @@ static char *i2c_devs[128] = {
360 [ 0x84 >> 1 ] = "tda8295", 362 [ 0x84 >> 1 ] = "tda8295",
361 [ 0xa0 >> 1 ] = "eeprom", 363 [ 0xa0 >> 1 ] = "eeprom",
362 [ 0xc0 >> 1 ] = "tuner/mt2131/tda8275", 364 [ 0xc0 >> 1 ] = "tuner/mt2131/tda8275",
363 [ 0xc2 >> 1 ] = "tuner/mt2131/tda8275/xc5000", 365 [0xc2 >> 1] = "tuner/mt2131/tda8275/xc5000/xc3028",
366 [0xc8 >> 1] = "tuner/xc3028L",
364}; 367};
365 368
366static void do_i2c_scan(char *name, struct i2c_client *c) 369static void do_i2c_scan(char *name, struct i2c_client *c)
@@ -383,7 +386,7 @@ int cx23885_i2c_register(struct cx23885_i2c *bus)
383{ 386{
384 struct cx23885_dev *dev = bus->dev; 387 struct cx23885_dev *dev = bus->dev;
385 388
386 dprintk(1, "%s(bus = %d)\n", __FUNCTION__, bus->nr); 389 dprintk(1, "%s(bus = %d)\n", __func__, bus->nr);
387 390
388 memcpy(&bus->i2c_adap, &cx23885_i2c_adap_template, 391 memcpy(&bus->i2c_adap, &cx23885_i2c_adap_template,
389 sizeof(bus->i2c_adap)); 392 sizeof(bus->i2c_adap));
@@ -420,6 +423,29 @@ int cx23885_i2c_unregister(struct cx23885_i2c *bus)
420 return 0; 423 return 0;
421} 424}
422 425
426void cx23885_av_clk(struct cx23885_dev *dev, int enable)
427{
428 /* write 0 to bus 2 addr 0x144 via i2x_xfer() */
429 char buffer[3];
430 struct i2c_msg msg;
431 dprintk(1, "%s(enabled = %d)\n", __func__, enable);
432
433 /* Register 0x144 */
434 buffer[0] = 0x01;
435 buffer[1] = 0x44;
436 if (enable == 1)
437 buffer[2] = 0x05;
438 else
439 buffer[2] = 0x00;
440
441 msg.addr = 0x44;
442 msg.flags = I2C_M_TEN;
443 msg.len = 3;
444 msg.buf = buffer;
445
446 i2c_xfer(&dev->i2c_bus[2].i2c_adap, &msg, 1);
447}
448
423/* ----------------------------------------------------------------------- */ 449/* ----------------------------------------------------------------------- */
424 450
425/* 451/*
diff --git a/drivers/media/video/cx23885/cx23885-video.c b/drivers/media/video/cx23885/cx23885-video.c
index d3c4d2c5cbe0..84652210a28c 100644
--- a/drivers/media/video/cx23885/cx23885-video.c
+++ b/drivers/media/video/cx23885/cx23885-video.c
@@ -141,7 +141,7 @@ static struct cx23885_fmt *format_by_fourcc(unsigned int fourcc)
141 if (formats[i].fourcc == fourcc) 141 if (formats[i].fourcc == fourcc)
142 return formats+i; 142 return formats+i;
143 143
144 printk(KERN_ERR "%s(0x%08x) NOT FOUND\n", __FUNCTION__, fourcc); 144 printk(KERN_ERR "%s(0x%08x) NOT FOUND\n", __func__, fourcc);
145 return NULL; 145 return NULL;
146} 146}
147 147
@@ -292,13 +292,13 @@ void cx23885_video_wakeup(struct cx23885_dev *dev,
292 } 292 }
293 if (bc != 1) 293 if (bc != 1)
294 printk(KERN_ERR "%s: %d buffers handled (should be 1)\n", 294 printk(KERN_ERR "%s: %d buffers handled (should be 1)\n",
295 __FUNCTION__, bc); 295 __func__, bc);
296} 296}
297 297
298int cx23885_set_tvnorm(struct cx23885_dev *dev, v4l2_std_id norm) 298int cx23885_set_tvnorm(struct cx23885_dev *dev, v4l2_std_id norm)
299{ 299{
300 dprintk(1, "%s(norm = 0x%08x) name: [%s]\n", 300 dprintk(1, "%s(norm = 0x%08x) name: [%s]\n",
301 __FUNCTION__, 301 __func__,
302 (unsigned int)norm, 302 (unsigned int)norm,
303 v4l2_norm_to_name(norm)); 303 v4l2_norm_to_name(norm));
304 304
@@ -319,7 +319,7 @@ struct video_device *cx23885_vdev_init(struct cx23885_dev *dev,
319 char *type) 319 char *type)
320{ 320{
321 struct video_device *vfd; 321 struct video_device *vfd;
322 dprintk(1, "%s()\n", __FUNCTION__); 322 dprintk(1, "%s()\n", __func__);
323 323
324 vfd = video_device_alloc(); 324 vfd = video_device_alloc();
325 if (NULL == vfd) 325 if (NULL == vfd)
@@ -358,7 +358,7 @@ EXPORT_SYMBOL(cx23885_ctrl_query);
358static int res_get(struct cx23885_dev *dev, struct cx23885_fh *fh, 358static int res_get(struct cx23885_dev *dev, struct cx23885_fh *fh,
359 unsigned int bit) 359 unsigned int bit)
360{ 360{
361 dprintk(1, "%s()\n", __FUNCTION__); 361 dprintk(1, "%s()\n", __func__);
362 if (fh->resources & bit) 362 if (fh->resources & bit)
363 /* have it already allocated */ 363 /* have it already allocated */
364 return 1; 364 return 1;
@@ -392,7 +392,7 @@ static void res_free(struct cx23885_dev *dev, struct cx23885_fh *fh,
392 unsigned int bits) 392 unsigned int bits)
393{ 393{
394 BUG_ON((fh->resources & bits) != bits); 394 BUG_ON((fh->resources & bits) != bits);
395 dprintk(1, "%s()\n", __FUNCTION__); 395 dprintk(1, "%s()\n", __func__);
396 396
397 mutex_lock(&dev->lock); 397 mutex_lock(&dev->lock);
398 fh->resources &= ~bits; 398 fh->resources &= ~bits;
@@ -407,7 +407,7 @@ int cx23885_video_mux(struct cx23885_dev *dev, unsigned int input)
407 memset(&route, 0, sizeof(route)); 407 memset(&route, 0, sizeof(route));
408 408
409 dprintk(1, "%s() video_mux: %d [vmux=%d, gpio=0x%x,0x%x,0x%x,0x%x]\n", 409 dprintk(1, "%s() video_mux: %d [vmux=%d, gpio=0x%x,0x%x,0x%x,0x%x]\n",
410 __FUNCTION__, 410 __func__,
411 input, INPUT(input)->vmux, 411 input, INPUT(input)->vmux,
412 INPUT(input)->gpio0, INPUT(input)->gpio1, 412 INPUT(input)->gpio0, INPUT(input)->gpio1,
413 INPUT(input)->gpio2, INPUT(input)->gpio3); 413 INPUT(input)->gpio2, INPUT(input)->gpio3);
@@ -427,7 +427,7 @@ EXPORT_SYMBOL(cx23885_video_mux);
427int cx23885_set_scale(struct cx23885_dev *dev, unsigned int width, 427int cx23885_set_scale(struct cx23885_dev *dev, unsigned int width,
428 unsigned int height, enum v4l2_field field) 428 unsigned int height, enum v4l2_field field)
429{ 429{
430 dprintk(1, "%s()\n", __FUNCTION__); 430 dprintk(1, "%s()\n", __func__);
431 return 0; 431 return 0;
432} 432}
433 433
@@ -435,7 +435,7 @@ static int cx23885_start_video_dma(struct cx23885_dev *dev,
435 struct cx23885_dmaqueue *q, 435 struct cx23885_dmaqueue *q,
436 struct cx23885_buffer *buf) 436 struct cx23885_buffer *buf)
437{ 437{
438 dprintk(1, "%s()\n", __FUNCTION__); 438 dprintk(1, "%s()\n", __func__);
439 439
440 /* setup fifo + format */ 440 /* setup fifo + format */
441 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01], 441 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01],
@@ -463,7 +463,7 @@ static int cx23885_restart_video_queue(struct cx23885_dev *dev,
463{ 463{
464 struct cx23885_buffer *buf, *prev; 464 struct cx23885_buffer *buf, *prev;
465 struct list_head *item; 465 struct list_head *item;
466 dprintk(1, "%s()\n", __FUNCTION__); 466 dprintk(1, "%s()\n", __func__);
467 467
468 if (!list_empty(&q->active)) { 468 if (!list_empty(&q->active)) {
469 buf = list_entry(q->active.next, struct cx23885_buffer, 469 buf = list_entry(q->active.next, struct cx23885_buffer,
@@ -579,13 +579,13 @@ static int buffer_prepare(struct videobuf_queue *q, struct videobuf_buffer *vb,
579 if (dev->tvnorm & V4L2_STD_NTSC) { 579 if (dev->tvnorm & V4L2_STD_NTSC) {
580 /* cx25840 transmits NTSC bottom field first */ 580 /* cx25840 transmits NTSC bottom field first */
581 dprintk(1, "%s() Creating NTSC risc\n", 581 dprintk(1, "%s() Creating NTSC risc\n",
582 __FUNCTION__); 582 __func__);
583 line0_offset = buf->bpl; 583 line0_offset = buf->bpl;
584 line1_offset = 0; 584 line1_offset = 0;
585 } else { 585 } else {
586 /* All other formats are top field first */ 586 /* All other formats are top field first */
587 dprintk(1, "%s() Creating PAL/SECAM risc\n", 587 dprintk(1, "%s() Creating PAL/SECAM risc\n",
588 __FUNCTION__); 588 __func__);
589 line0_offset = 0; 589 line0_offset = 0;
590 line1_offset = buf->bpl; 590 line1_offset = buf->bpl;
591 } 591 }
@@ -765,8 +765,8 @@ static int video_open(struct inode *inode, struct file *file)
765 fh->height = 240; 765 fh->height = 240;
766 fh->fmt = format_by_fourcc(V4L2_PIX_FMT_BGR24); 766 fh->fmt = format_by_fourcc(V4L2_PIX_FMT_BGR24);
767 767
768 videobuf_queue_pci_init(&fh->vidq, &cx23885_video_qops, 768 videobuf_queue_sg_init(&fh->vidq, &cx23885_video_qops,
769 dev->pci, &dev->slock, 769 &dev->pci->dev, &dev->slock,
770 V4L2_BUF_TYPE_VIDEO_CAPTURE, 770 V4L2_BUF_TYPE_VIDEO_CAPTURE,
771 V4L2_FIELD_INTERLACED, 771 V4L2_FIELD_INTERLACED,
772 sizeof(struct cx23885_buffer), 772 sizeof(struct cx23885_buffer),
@@ -885,7 +885,7 @@ static int video_mmap(struct file *file, struct vm_area_struct *vma)
885 885
886int cx23885_get_control(struct cx23885_dev *dev, struct v4l2_control *ctl) 886int cx23885_get_control(struct cx23885_dev *dev, struct v4l2_control *ctl)
887{ 887{
888 dprintk(1, "%s() calling cx25840(VIDIOC_G_CTRL)\n", __FUNCTION__); 888 dprintk(1, "%s() calling cx25840(VIDIOC_G_CTRL)\n", __func__);
889 cx23885_call_i2c_clients(&dev->i2c_bus[2], VIDIOC_G_CTRL, ctl); 889 cx23885_call_i2c_clients(&dev->i2c_bus[2], VIDIOC_G_CTRL, ctl);
890 return 0; 890 return 0;
891} 891}
@@ -894,7 +894,7 @@ EXPORT_SYMBOL(cx23885_get_control);
894int cx23885_set_control(struct cx23885_dev *dev, struct v4l2_control *ctl) 894int cx23885_set_control(struct cx23885_dev *dev, struct v4l2_control *ctl)
895{ 895{
896 dprintk(1, "%s() calling cx25840(VIDIOC_S_CTRL)" 896 dprintk(1, "%s() calling cx25840(VIDIOC_S_CTRL)"
897 " (disabled - no action)\n", __FUNCTION__); 897 " (disabled - no action)\n", __func__);
898 return 0; 898 return 0;
899} 899}
900EXPORT_SYMBOL(cx23885_set_control); 900EXPORT_SYMBOL(cx23885_set_control);
@@ -990,7 +990,7 @@ static int vidioc_s_fmt_cap(struct file *file, void *priv,
990 struct cx23885_dev *dev = ((struct cx23885_fh *)priv)->dev; 990 struct cx23885_dev *dev = ((struct cx23885_fh *)priv)->dev;
991 int err; 991 int err;
992 992
993 dprintk(2, "%s()\n", __FUNCTION__); 993 dprintk(2, "%s()\n", __func__);
994 err = vidioc_try_fmt_cap(file, priv, f); 994 err = vidioc_try_fmt_cap(file, priv, f);
995 995
996 if (0 != err) 996 if (0 != err)
@@ -999,7 +999,7 @@ static int vidioc_s_fmt_cap(struct file *file, void *priv,
999 fh->width = f->fmt.pix.width; 999 fh->width = f->fmt.pix.width;
1000 fh->height = f->fmt.pix.height; 1000 fh->height = f->fmt.pix.height;
1001 fh->vidq.field = f->fmt.pix.field; 1001 fh->vidq.field = f->fmt.pix.field;
1002 dprintk(2, "%s() width=%d height=%d field=%d\n", __FUNCTION__, 1002 dprintk(2, "%s() width=%d height=%d field=%d\n", __func__,
1003 fh->width, fh->height, fh->vidq.field); 1003 fh->width, fh->height, fh->vidq.field);
1004 cx23885_call_i2c_clients(&dev->i2c_bus[2], VIDIOC_S_FMT, f); 1004 cx23885_call_i2c_clients(&dev->i2c_bus[2], VIDIOC_S_FMT, f);
1005 return 0; 1005 return 0;
@@ -1101,7 +1101,7 @@ static int vidioc_streamon(struct file *file, void *priv,
1101{ 1101{
1102 struct cx23885_fh *fh = priv; 1102 struct cx23885_fh *fh = priv;
1103 struct cx23885_dev *dev = fh->dev; 1103 struct cx23885_dev *dev = fh->dev;
1104 dprintk(1, "%s()\n", __FUNCTION__); 1104 dprintk(1, "%s()\n", __func__);
1105 1105
1106 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)) 1106 if (unlikely(fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE))
1107 return -EINVAL; 1107 return -EINVAL;
@@ -1118,7 +1118,7 @@ static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
1118 struct cx23885_fh *fh = priv; 1118 struct cx23885_fh *fh = priv;
1119 struct cx23885_dev *dev = fh->dev; 1119 struct cx23885_dev *dev = fh->dev;
1120 int err, res; 1120 int err, res;
1121 dprintk(1, "%s()\n", __FUNCTION__); 1121 dprintk(1, "%s()\n", __func__);
1122 1122
1123 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) 1123 if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1124 return -EINVAL; 1124 return -EINVAL;
@@ -1136,7 +1136,7 @@ static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
1136static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *tvnorms) 1136static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *tvnorms)
1137{ 1137{
1138 struct cx23885_dev *dev = ((struct cx23885_fh *)priv)->dev; 1138 struct cx23885_dev *dev = ((struct cx23885_fh *)priv)->dev;
1139 dprintk(1, "%s()\n", __FUNCTION__); 1139 dprintk(1, "%s()\n", __func__);
1140 1140
1141 mutex_lock(&dev->lock); 1141 mutex_lock(&dev->lock);
1142 cx23885_set_tvnorm(dev, *tvnorms); 1142 cx23885_set_tvnorm(dev, *tvnorms);
@@ -1159,7 +1159,7 @@ int cx23885_enum_input(struct cx23885_dev *dev, struct v4l2_input *i)
1159 [CX23885_VMUX_DEBUG] = "for debug only", 1159 [CX23885_VMUX_DEBUG] = "for debug only",
1160 }; 1160 };
1161 unsigned int n; 1161 unsigned int n;
1162 dprintk(1, "%s()\n", __FUNCTION__); 1162 dprintk(1, "%s()\n", __func__);
1163 1163
1164 n = i->index; 1164 n = i->index;
1165 if (n >= 4) 1165 if (n >= 4)
@@ -1184,7 +1184,7 @@ static int vidioc_enum_input(struct file *file, void *priv,
1184 struct v4l2_input *i) 1184 struct v4l2_input *i)
1185{ 1185{
1186 struct cx23885_dev *dev = ((struct cx23885_fh *)priv)->dev; 1186 struct cx23885_dev *dev = ((struct cx23885_fh *)priv)->dev;
1187 dprintk(1, "%s()\n", __FUNCTION__); 1187 dprintk(1, "%s()\n", __func__);
1188 return cx23885_enum_input(dev, i); 1188 return cx23885_enum_input(dev, i);
1189} 1189}
1190 1190
@@ -1193,7 +1193,7 @@ static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
1193 struct cx23885_dev *dev = ((struct cx23885_fh *)priv)->dev; 1193 struct cx23885_dev *dev = ((struct cx23885_fh *)priv)->dev;
1194 1194
1195 *i = dev->input; 1195 *i = dev->input;
1196 dprintk(1, "%s() returns %d\n", __FUNCTION__, *i); 1196 dprintk(1, "%s() returns %d\n", __func__, *i);
1197 return 0; 1197 return 0;
1198} 1198}
1199 1199
@@ -1201,10 +1201,10 @@ static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
1201{ 1201{
1202 struct cx23885_dev *dev = ((struct cx23885_fh *)priv)->dev; 1202 struct cx23885_dev *dev = ((struct cx23885_fh *)priv)->dev;
1203 1203
1204 dprintk(1, "%s(%d)\n", __FUNCTION__, i); 1204 dprintk(1, "%s(%d)\n", __func__, i);
1205 1205
1206 if (i >= 4) { 1206 if (i >= 4) {
1207 dprintk(1, "%s() -EINVAL\n", __FUNCTION__); 1207 dprintk(1, "%s() -EINVAL\n", __func__);
1208 return -EINVAL; 1208 return -EINVAL;
1209 } 1209 }
1210 1210
@@ -1389,7 +1389,7 @@ int cx23885_video_irq(struct cx23885_dev *dev, u32 status)
1389 return handled; 1389 return handled;
1390 cx_write(VID_A_INT_STAT, status); 1390 cx_write(VID_A_INT_STAT, status);
1391 1391
1392 dprintk(2, "%s() status = 0x%08x\n", __FUNCTION__, status); 1392 dprintk(2, "%s() status = 0x%08x\n", __func__, status);
1393 /* risc op code error */ 1393 /* risc op code error */
1394 if (status & (1 << 16)) { 1394 if (status & (1 << 16)) {
1395 printk(KERN_WARNING "%s/0: video risc op code error\n", 1395 printk(KERN_WARNING "%s/0: video risc op code error\n",
@@ -1487,7 +1487,7 @@ static const struct file_operations radio_fops = {
1487 1487
1488void cx23885_video_unregister(struct cx23885_dev *dev) 1488void cx23885_video_unregister(struct cx23885_dev *dev)
1489{ 1489{
1490 dprintk(1, "%s()\n", __FUNCTION__); 1490 dprintk(1, "%s()\n", __func__);
1491 cx_clear(PCI_INT_MSK, 1); 1491 cx_clear(PCI_INT_MSK, 1);
1492 1492
1493 if (dev->video_dev) { 1493 if (dev->video_dev) {
@@ -1505,7 +1505,7 @@ int cx23885_video_register(struct cx23885_dev *dev)
1505{ 1505{
1506 int err; 1506 int err;
1507 1507
1508 dprintk(1, "%s()\n", __FUNCTION__); 1508 dprintk(1, "%s()\n", __func__);
1509 spin_lock_init(&dev->slock); 1509 spin_lock_init(&dev->slock);
1510 1510
1511 /* Initialize VBI template */ 1511 /* Initialize VBI template */
diff --git a/drivers/media/video/cx23885/cx23885.h b/drivers/media/video/cx23885/cx23885.h
index 7cb2179f2622..32af87f25e7b 100644
--- a/drivers/media/video/cx23885/cx23885.h
+++ b/drivers/media/video/cx23885/cx23885.h
@@ -32,6 +32,7 @@
32 32
33#include "btcx-risc.h" 33#include "btcx-risc.h"
34#include "cx23885-reg.h" 34#include "cx23885-reg.h"
35#include "media/cx2341x.h"
35 36
36#include <linux/version.h> 37#include <linux/version.h>
37#include <linux/mutex.h> 38#include <linux/mutex.h>
@@ -59,6 +60,9 @@
59#define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP 4 60#define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP 4
60#define CX23885_BOARD_HAUPPAUGE_HVR1500Q 5 61#define CX23885_BOARD_HAUPPAUGE_HVR1500Q 5
61#define CX23885_BOARD_HAUPPAUGE_HVR1500 6 62#define CX23885_BOARD_HAUPPAUGE_HVR1500 6
63#define CX23885_BOARD_HAUPPAUGE_HVR1200 7
64#define CX23885_BOARD_HAUPPAUGE_HVR1700 8
65#define CX23885_BOARD_HAUPPAUGE_HVR1400 9
62 66
63/* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */ 67/* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */
64#define CX23885_NORMS (\ 68#define CX23885_NORMS (\
@@ -154,6 +158,7 @@ typedef enum {
154 CX23885_MPEG_UNDEFINED = 0, 158 CX23885_MPEG_UNDEFINED = 0,
155 CX23885_MPEG_DVB, 159 CX23885_MPEG_DVB,
156 CX23885_ANALOG_VIDEO, 160 CX23885_ANALOG_VIDEO,
161 CX23885_MPEG_ENCODER,
157} port_t; 162} port_t;
158 163
159struct cx23885_board { 164struct cx23885_board {
@@ -252,6 +257,8 @@ struct cx23885_tsport {
252 u32 gen_ctrl_val; 257 u32 gen_ctrl_val;
253 u32 ts_clk_en_val; 258 u32 ts_clk_en_val;
254 u32 src_sel_val; 259 u32 src_sel_val;
260 u32 vld_misc_val;
261 u32 hw_sop_ctrl_val;
255}; 262};
256 263
257struct cx23885_dev { 264struct cx23885_dev {
@@ -312,6 +319,14 @@ struct cx23885_dev {
312 struct cx23885_dmaqueue vidq; 319 struct cx23885_dmaqueue vidq;
313 struct cx23885_dmaqueue vbiq; 320 struct cx23885_dmaqueue vbiq;
314 spinlock_t slock; 321 spinlock_t slock;
322
323 /* MPEG Encoder ONLY settings */
324 u32 cx23417_mailbox;
325 struct cx2341x_mpeg_params mpeg_params;
326 struct video_device *v4l_device;
327 atomic_t v4l_reader_count;
328 struct cx23885_tvnorm encodernorm;
329
315}; 330};
316 331
317extern struct list_head cx23885_devlist; 332extern struct list_head cx23885_devlist;
@@ -431,6 +446,18 @@ extern int cx23885_i2c_register(struct cx23885_i2c *bus);
431extern int cx23885_i2c_unregister(struct cx23885_i2c *bus); 446extern int cx23885_i2c_unregister(struct cx23885_i2c *bus);
432extern void cx23885_call_i2c_clients(struct cx23885_i2c *bus, unsigned int cmd, 447extern void cx23885_call_i2c_clients(struct cx23885_i2c *bus, unsigned int cmd,
433 void *arg); 448 void *arg);
449extern void cx23885_av_clk(struct cx23885_dev *dev, int enable);
450
451/* ----------------------------------------------------------- */
452/* cx23885-417.c */
453extern int cx23885_417_register(struct cx23885_dev *dev);
454extern void cx23885_417_unregister(struct cx23885_dev *dev);
455extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status);
456extern void cx23885_417_check_encoder(struct cx23885_dev *dev);
457extern void cx23885_mc417_init(struct cx23885_dev *dev);
458extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value);
459extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value);
460
434 461
435/* ----------------------------------------------------------- */ 462/* ----------------------------------------------------------- */
436/* tv norms */ 463/* tv norms */