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authorAndy Walls <awalls@radix.net>2009-10-29 21:24:34 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2009-12-05 15:41:08 -0500
commit928213aad76e0036290901d244d614c01cac7278 (patch)
treec8b1cbde12a7f4f1c1a487d1bd8b54d5ca9dbe11 /drivers/media/video/cx23885/cx23888-ir.c
parent7fb101ae2525ea5e8bad43a3fc228e87c5f047c6 (diff)
V4L/DVB (13253): cx23885: CodingStyle fix
Add whitespace around binary operators in cx23888-ir.c Signed-off-by: Andy Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/video/cx23885/cx23888-ir.c')
-rw-r--r--drivers/media/video/cx23885/cx23888-ir.c37
1 files changed, 19 insertions, 18 deletions
diff --git a/drivers/media/video/cx23885/cx23888-ir.c b/drivers/media/video/cx23885/cx23888-ir.c
index e8d949ae06b9..3ccc8afeccf3 100644
--- a/drivers/media/video/cx23885/cx23888-ir.c
+++ b/drivers/media/video/cx23885/cx23888-ir.c
@@ -108,7 +108,7 @@ MODULE_PARM_DESC(ir_888_debug, "enable debug messages [CX23888 IR controller]");
108#define CX23888_IR_LEARN_REG 0x170044 108#define CX23888_IR_LEARN_REG 0x170044
109 109
110#define CX23888_VIDCLK_FREQ 108000000 /* 108 MHz, BT.656 */ 110#define CX23888_VIDCLK_FREQ 108000000 /* 108 MHz, BT.656 */
111#define CX23888_IR_REFCLK_FREQ (CX23888_VIDCLK_FREQ/2) 111#define CX23888_IR_REFCLK_FREQ (CX23888_VIDCLK_FREQ / 2)
112 112
113#define CX23888_IR_RX_KFIFO_SIZE (512 * sizeof(u32)) 113#define CX23888_IR_RX_KFIFO_SIZE (512 * sizeof(u32))
114#define CX23888_IR_TX_KFIFO_SIZE (512 * sizeof(u32)) 114#define CX23888_IR_TX_KFIFO_SIZE (512 * sizeof(u32))
@@ -171,7 +171,7 @@ static inline int cx23888_ir_and_or4(struct cx23885_dev *dev, u32 addr,
171 */ 171 */
172static inline u16 count_to_clock_divider(unsigned int d) 172static inline u16 count_to_clock_divider(unsigned int d)
173{ 173{
174 if (d > RXCLK_RCD+1) 174 if (d > RXCLK_RCD + 1)
175 d = RXCLK_RCD; 175 d = RXCLK_RCD;
176 else if (d < 2) 176 else if (d < 2)
177 d = 1; 177 d = 1;
@@ -183,14 +183,14 @@ static inline u16 count_to_clock_divider(unsigned int d)
183static inline u16 ns_to_clock_divider(unsigned int ns) 183static inline u16 ns_to_clock_divider(unsigned int ns)
184{ 184{
185 return count_to_clock_divider( 185 return count_to_clock_divider(
186 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ/1000000 * ns, 1000)); 186 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000));
187} 187}
188 188
189static inline unsigned int clock_divider_to_ns(unsigned int divider) 189static inline unsigned int clock_divider_to_ns(unsigned int divider)
190{ 190{
191 /* Period of the Rx or Tx clock in ns */ 191 /* Period of the Rx or Tx clock in ns */
192 return DIV_ROUND_CLOSEST((divider + 1) * 1000, 192 return DIV_ROUND_CLOSEST((divider + 1) * 1000,
193 CX23888_IR_REFCLK_FREQ/1000000); 193 CX23888_IR_REFCLK_FREQ / 1000000);
194} 194}
195 195
196static inline u16 carrier_freq_to_clock_divider(unsigned int freq) 196static inline u16 carrier_freq_to_clock_divider(unsigned int freq)
@@ -237,19 +237,20 @@ static inline u16 count_to_lpf_count(unsigned int d)
237static inline u16 ns_to_lpf_count(unsigned int ns) 237static inline u16 ns_to_lpf_count(unsigned int ns)
238{ 238{
239 return count_to_lpf_count( 239 return count_to_lpf_count(
240 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ/1000000 * ns, 1000)); 240 DIV_ROUND_CLOSEST(CX23888_IR_REFCLK_FREQ / 1000000 * ns, 1000));
241} 241}
242 242
243static inline unsigned int lpf_count_to_ns(unsigned int count) 243static inline unsigned int lpf_count_to_ns(unsigned int count)
244{ 244{
245 /* Duration of the Low Pass Filter rejection window in ns */ 245 /* Duration of the Low Pass Filter rejection window in ns */
246 return DIV_ROUND_CLOSEST(count * 1000, CX23888_IR_REFCLK_FREQ/1000000); 246 return DIV_ROUND_CLOSEST(count * 1000,
247 CX23888_IR_REFCLK_FREQ / 1000000);
247} 248}
248 249
249static inline unsigned int lpf_count_to_us(unsigned int count) 250static inline unsigned int lpf_count_to_us(unsigned int count)
250{ 251{
251 /* Duration of the Low Pass Filter rejection window in us */ 252 /* Duration of the Low Pass Filter rejection window in us */
252 return DIV_ROUND_CLOSEST(count, CX23888_IR_REFCLK_FREQ/1000000); 253 return DIV_ROUND_CLOSEST(count, CX23888_IR_REFCLK_FREQ / 1000000);
253} 254}
254 255
255/* 256/*
@@ -263,7 +264,7 @@ static u32 clock_divider_to_resolution(u16 divider)
263 * not readable, hence the << 2. This function returns ns. 264 * not readable, hence the << 2. This function returns ns.
264 */ 265 */
265 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000, 266 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000,
266 CX23888_IR_REFCLK_FREQ/1000000); 267 CX23888_IR_REFCLK_FREQ / 1000000);
267} 268}
268 269
269static u64 pulse_width_count_to_ns(u16 count, u16 divider) 270static u64 pulse_width_count_to_ns(u16 count, u16 divider)
@@ -276,8 +277,8 @@ static u64 pulse_width_count_to_ns(u16 count, u16 divider)
276 * the (count << 2) | 0x3 277 * the (count << 2) | 0x3
277 */ 278 */
278 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */ 279 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
279 rem = do_div(n, CX23888_IR_REFCLK_FREQ/1000000); /* / MHz => ns */ 280 rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => ns */
280 if (rem >= CX23888_IR_REFCLK_FREQ/1000000/2) 281 if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2)
281 n++; 282 n++;
282 return n; 283 return n;
283} 284}
@@ -291,9 +292,9 @@ static unsigned int pulse_width_count_to_us(u16 count, u16 divider)
291 * The 2 lsb's of the pulse width timer count are not readable, hence 292 * The 2 lsb's of the pulse width timer count are not readable, hence
292 * the (count << 2) | 0x3 293 * the (count << 2) | 0x3
293 */ 294 */
294 n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */ 295 n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */
295 rem = do_div(n, CX23888_IR_REFCLK_FREQ/1000000); /* / MHz => us */ 296 rem = do_div(n, CX23888_IR_REFCLK_FREQ / 1000000); /* / MHz => us */
296 if (rem >= CX23888_IR_REFCLK_FREQ/1000000/2) 297 if (rem >= CX23888_IR_REFCLK_FREQ / 1000000 / 2)
297 n++; 298 n++;
298 return (unsigned int) n; 299 return (unsigned int) n;
299} 300}
@@ -310,9 +311,9 @@ static u64 ns_to_pulse_clocks(u32 ns)
310{ 311{
311 u64 clocks; 312 u64 clocks;
312 u32 rem; 313 u32 rem;
313 clocks = CX23888_IR_REFCLK_FREQ/1000000 * (u64) ns; /* millicycles */ 314 clocks = CX23888_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles */
314 rem = do_div(clocks, 1000); /* /1000 = cycles */ 315 rem = do_div(clocks, 1000); /* /1000 = cycles */
315 if (rem >= 1000/2) 316 if (rem >= 1000 / 2)
316 clocks++; 317 clocks++;
317 return clocks; 318 return clocks;
318} 319}
@@ -324,7 +325,7 @@ static u16 pulse_clocks_to_clock_divider(u64 count)
324 rem = do_div(count, (FIFO_RXTX << 2) | 0x3); 325 rem = do_div(count, (FIFO_RXTX << 2) | 0x3);
325 326
326 /* net result needs to be rounded down and decremented by 1 */ 327 /* net result needs to be rounded down and decremented by 1 */
327 if (count > RXCLK_RCD+1) 328 if (count > RXCLK_RCD + 1)
328 count = RXCLK_RCD; 329 count = RXCLK_RCD;
329 else if (count < 2) 330 else if (count < 2)
330 count = 1; 331 count = 1;
@@ -484,7 +485,7 @@ static unsigned int cduty_tx_s_duty_cycle(struct cx23885_dev *dev,
484 if (n > 15) 485 if (n > 15)
485 n = 15; 486 n = 15;
486 cx23888_ir_write4(dev, CX23888_IR_CDUTY_REG, n); 487 cx23888_ir_write4(dev, CX23888_IR_CDUTY_REG, n);
487 return DIV_ROUND_CLOSEST((n+1) * 100, 16); 488 return DIV_ROUND_CLOSEST((n + 1) * 100, 16);
488} 489}
489 490
490/* 491/*
@@ -630,7 +631,7 @@ static int cx23888_ir_irq_handler(struct v4l2_subdev *sd, u32 status,
630 cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl); 631 cx23888_ir_write4(dev, CX23888_IR_CNTRL_REG, cntrl);
631 *handled = true; 632 *handled = true;
632 } 633 }
633 if (kfifo_len(state->rx_kfifo) >= CX23888_IR_RX_KFIFO_SIZE/2) 634 if (kfifo_len(state->rx_kfifo) >= CX23888_IR_RX_KFIFO_SIZE / 2)
634 events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ; 635 events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ;
635 636
636 if (events) 637 if (events)