aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/media/video/cx231xx/cx231xx-conf-reg.h
diff options
context:
space:
mode:
authorMauro Carvalho Chehab <mchehab@redhat.com>2009-03-03 04:14:34 -0500
committerMauro Carvalho Chehab <mchehab@redhat.com>2009-04-06 20:44:01 -0400
commit84b5dbf39ed2f51224841bbbf08439158d69d427 (patch)
treeb24963462dc1ad93860645d8729d1ddfc6ce526e /drivers/media/video/cx231xx/cx231xx-conf-reg.h
parente0d3bafd02586cfde286c320f56906fd9fa8d256 (diff)
V4L/DVB (10955): cx231xx: CodingStyle automatic fixes with Lindent
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/video/cx231xx/cx231xx-conf-reg.h')
-rw-r--r--drivers/media/video/cx231xx/cx231xx-conf-reg.h132
1 files changed, 64 insertions, 68 deletions
diff --git a/drivers/media/video/cx231xx/cx231xx-conf-reg.h b/drivers/media/video/cx231xx/cx231xx-conf-reg.h
index 5ccf6bdfe579..a65f99ba109b 100644
--- a/drivers/media/video/cx231xx/cx231xx-conf-reg.h
+++ b/drivers/media/video/cx231xx/cx231xx-conf-reg.h
@@ -1,6 +1,6 @@
1/* 1/*
2 cx231xx_conf-reg.h - driver for Conexant Cx23100/101/102 USB 2 cx231xx_conf-reg.h - driver for Conexant Cx23100/101/102 USB
3 video capture devices 3 video capture devices
4 4
5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com> 5 Copyright (C) 2008 <srinivasa.deevi at conexant dot com>
6 6
@@ -19,7 +19,6 @@
19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */ 20 */
21 21
22
23#ifndef _POLARIS_REG_H_ 22#ifndef _POLARIS_REG_H_
24#define _POLARIS_REG_H_ 23#define _POLARIS_REG_H_
25 24
@@ -43,30 +42,30 @@
43#define PWR_CTL_EN 0x74 42#define PWR_CTL_EN 0x74
44 43
45/* Polaris Endpoints capture mask for register EP_MODE_SET */ 44/* Polaris Endpoints capture mask for register EP_MODE_SET */
46#define ENABLE_EP1 0x01 /* Bit[0]=1 */ 45#define ENABLE_EP1 0x01 /* Bit[0]=1 */
47#define ENABLE_EP2 0x02 /* Bit[1]=1 */ 46#define ENABLE_EP2 0x02 /* Bit[1]=1 */
48#define ENABLE_EP3 0x04 /* Bit[2]=1 */ 47#define ENABLE_EP3 0x04 /* Bit[2]=1 */
49#define ENABLE_EP4 0x08 /* Bit[3]=1 */ 48#define ENABLE_EP4 0x08 /* Bit[3]=1 */
50#define ENABLE_EP5 0x10 /* Bit[4]=1 */ 49#define ENABLE_EP5 0x10 /* Bit[4]=1 */
51#define ENABLE_EP6 0x20 /* Bit[5]=1 */ 50#define ENABLE_EP6 0x20 /* Bit[5]=1 */
52 51
53/* Bit definition for register PWR_CTL_EN */ 52/* Bit definition for register PWR_CTL_EN */
54#define PWR_MODE_MASK 0x17f 53#define PWR_MODE_MASK 0x17f
55#define PWR_AV_EN 0x08 /* bit3 */ 54#define PWR_AV_EN 0x08 /* bit3 */
56#define PWR_ISO_EN 0x40 /* bit6 */ 55#define PWR_ISO_EN 0x40 /* bit6 */
57#define PWR_AV_MODE 0x30 /* bit4,5 */ 56#define PWR_AV_MODE 0x30 /* bit4,5 */
58#define PWR_TUNER_EN 0x04 /* bit2 */ 57#define PWR_TUNER_EN 0x04 /* bit2 */
59#define PWR_DEMOD_EN 0x02 /* bit1 */ 58#define PWR_DEMOD_EN 0x02 /* bit1 */
60#define I2C_DEMOD_EN 0x01 /* bit0 */ 59#define I2C_DEMOD_EN 0x01 /* bit0 */
61#define PWR_RESETOUT_EN 0x100 /* bit8 */ 60#define PWR_RESETOUT_EN 0x100 /* bit8 */
62 61
63typedef enum{ 62typedef enum {
64 POLARIS_AVMODE_DEFAULT = 0, 63 POLARIS_AVMODE_DEFAULT = 0,
65 POLARIS_AVMODE_DIGITAL = 0x10, 64 POLARIS_AVMODE_DIGITAL = 0x10,
66 POLARIS_AVMODE_ANALOGT_TV = 0x20, 65 POLARIS_AVMODE_ANALOGT_TV = 0x20,
67 POLARIS_AVMODE_ENXTERNAL_AV = 0x30, 66 POLARIS_AVMODE_ENXTERNAL_AV = 0x30,
68 67
69}AV_MODE; 68} AV_MODE;
70 69
71/* Colibri Registers */ 70/* Colibri Registers */
72 71
@@ -75,8 +74,6 @@ typedef enum{
75#define EU_IF 0x9 74#define EU_IF 0x9
76#define US_IF 0xa 75#define US_IF 0xa
77 76
78
79
80#define SUP_BLK_TUNE1 0x00 77#define SUP_BLK_TUNE1 0x00
81#define SUP_BLK_TUNE2 0x01 78#define SUP_BLK_TUNE2 0x01
82#define SUP_BLK_TUNE3 0x02 79#define SUP_BLK_TUNE3 0x02
@@ -129,7 +126,7 @@ typedef enum{
129#define ADC_INPUT_CH1 0x28 126#define ADC_INPUT_CH1 0x28
130#define ADC_INPUT_CH2 0x48 127#define ADC_INPUT_CH2 0x48
131#define ADC_INPUT_CH3 0x68 128#define ADC_INPUT_CH3 0x68
132#define INPUT_SEL_MASK 0x30 /* [5:4] in_sel */ 129#define INPUT_SEL_MASK 0x30 /* [5:4] in_sel */
133 130
134#define ADC_NTF_PRECLMP_EN_CH1 0x29 131#define ADC_NTF_PRECLMP_EN_CH1 0x29
135#define ADC_NTF_PRECLMP_EN_CH2 0x49 132#define ADC_NTF_PRECLMP_EN_CH2 0x49
@@ -148,12 +145,12 @@ typedef enum{
148#define TESTBUS_CTRL_CH3 0x72 145#define TESTBUS_CTRL_CH3 0x72
149 146
150/****************************************************************************** 147/******************************************************************************
151 * DIF registers * 148 * DIF registers *
152 ******************************************************************************/ 149 ******************************************************************************/
153#define DIRECT_IF_REVB_BASE 0x00300 150#define DIRECT_IF_REVB_BASE 0x00300
154 151
155/*****************************************************************************/ 152/*****************************************************************************/
156#define DIF_PLL_FREQ_WORD (DIRECT_IF_REVB_BASE + 0x00000000) /* Reg Size 32 */ 153#define DIF_PLL_FREQ_WORD (DIRECT_IF_REVB_BASE + 0x00000000) /* Reg Size 32 */
157/*****************************************************************************/ 154/*****************************************************************************/
158#define FLD_DIF_PLL_LOCK 0x80000000 155#define FLD_DIF_PLL_LOCK 0x80000000
159/* Reserved [30:29] */ 156/* Reserved [30:29] */
@@ -161,7 +158,7 @@ typedef enum{
161#define FLD_DIF_PLL_FREQ 0x0FFFFFFF 158#define FLD_DIF_PLL_FREQ 0x0FFFFFFF
162 159
163/*****************************************************************************/ 160/*****************************************************************************/
164#define DIF_PLL_CTRL (DIRECT_IF_REVB_BASE + 0x00000004) /* Reg Size 32 */ 161#define DIF_PLL_CTRL (DIRECT_IF_REVB_BASE + 0x00000004) /* Reg Size 32 */
165/*****************************************************************************/ 162/*****************************************************************************/
166#define FLD_DIF_KD_PD 0xFF000000 163#define FLD_DIF_KD_PD 0xFF000000
167/* Reserved [23:20] */ 164/* Reserved [23:20] */
@@ -171,7 +168,7 @@ typedef enum{
171#define FLD_DIF_KIS_PD 0x0000000F 168#define FLD_DIF_KIS_PD 0x0000000F
172 169
173/*****************************************************************************/ 170/*****************************************************************************/
174#define DIF_PLL_CTRL1 (DIRECT_IF_REVB_BASE + 0x00000008) /* Reg Size 32 */ 171#define DIF_PLL_CTRL1 (DIRECT_IF_REVB_BASE + 0x00000008) /* Reg Size 32 */
175/*****************************************************************************/ 172/*****************************************************************************/
176#define FLD_DIF_KD_FD 0xFF000000 173#define FLD_DIF_KD_FD 0xFF000000
177/* Reserved [23:20] */ 174/* Reserved [23:20] */
@@ -181,7 +178,7 @@ typedef enum{
181#define FLD_DIF_KIS_FD 0x0000000F 178#define FLD_DIF_KIS_FD 0x0000000F
182 179
183/*****************************************************************************/ 180/*****************************************************************************/
184#define DIF_PLL_CTRL2 (DIRECT_IF_REVB_BASE + 0x0000000C) /* Reg Size 32 */ 181#define DIF_PLL_CTRL2 (DIRECT_IF_REVB_BASE + 0x0000000C) /* Reg Size 32 */
185/*****************************************************************************/ 182/*****************************************************************************/
186#define FLD_DIF_PLL_AGC_REF 0xFFF00000 183#define FLD_DIF_PLL_AGC_REF 0xFFF00000
187#define FLD_DIF_PLL_AGC_KI 0x000F0000 184#define FLD_DIF_PLL_AGC_KI 0x000F0000
@@ -191,7 +188,7 @@ typedef enum{
191#define FLD_DIF_DOWNSMPL_FD 0x000000FF 188#define FLD_DIF_DOWNSMPL_FD 0x000000FF
192 189
193/*****************************************************************************/ 190/*****************************************************************************/
194#define DIF_PLL_CTRL3 (DIRECT_IF_REVB_BASE + 0x00000010) /* Reg Size 32 */ 191#define DIF_PLL_CTRL3 (DIRECT_IF_REVB_BASE + 0x00000010) /* Reg Size 32 */
195/*****************************************************************************/ 192/*****************************************************************************/
196/* Reserved [31:16] */ 193/* Reserved [31:16] */
197#define FLD_DIF_PLL_AGC_EN 0x00008000 194#define FLD_DIF_PLL_AGC_EN 0x00008000
@@ -199,7 +196,7 @@ typedef enum{
199#define FLD_DIF_PLL_MAN_GAIN 0x00000FFF 196#define FLD_DIF_PLL_MAN_GAIN 0x00000FFF
200 197
201/*****************************************************************************/ 198/*****************************************************************************/
202#define DIF_AGC_IF_REF (DIRECT_IF_REVB_BASE + 0x00000014) /* Reg Size 32 */ 199#define DIF_AGC_IF_REF (DIRECT_IF_REVB_BASE + 0x00000014) /* Reg Size 32 */
203/*****************************************************************************/ 200/*****************************************************************************/
204#define FLD_DIF_K_AGC_RF 0xF0000000 201#define FLD_DIF_K_AGC_RF 0xF0000000
205#define FLD_DIF_K_AGC_IF 0x0F000000 202#define FLD_DIF_K_AGC_IF 0x0F000000
@@ -208,40 +205,40 @@ typedef enum{
208#define FLD_DIF_IF_REF 0x00000FFF 205#define FLD_DIF_IF_REF 0x00000FFF
209 206
210/*****************************************************************************/ 207/*****************************************************************************/
211#define DIF_AGC_CTRL_IF (DIRECT_IF_REVB_BASE + 0x00000018) /* Reg Size 32 */ 208#define DIF_AGC_CTRL_IF (DIRECT_IF_REVB_BASE + 0x00000018) /* Reg Size 32 */
212/*****************************************************************************/ 209/*****************************************************************************/
213#define FLD_DIF_IF_MAX 0xFF000000 210#define FLD_DIF_IF_MAX 0xFF000000
214#define FLD_DIF_IF_MIN 0x00FF0000 211#define FLD_DIF_IF_MIN 0x00FF0000
215#define FLD_DIF_IF_AGC 0x0000FFFF 212#define FLD_DIF_IF_AGC 0x0000FFFF
216 213
217/*****************************************************************************/ 214/*****************************************************************************/
218#define DIF_AGC_CTRL_INT (DIRECT_IF_REVB_BASE + 0x0000001C) /* Reg Size 32 */ 215#define DIF_AGC_CTRL_INT (DIRECT_IF_REVB_BASE + 0x0000001C) /* Reg Size 32 */
219/*****************************************************************************/ 216/*****************************************************************************/
220#define FLD_DIF_INT_MAX 0xFF000000 217#define FLD_DIF_INT_MAX 0xFF000000
221#define FLD_DIF_INT_MIN 0x00FF0000 218#define FLD_DIF_INT_MIN 0x00FF0000
222#define FLD_DIF_INT_AGC 0x0000FFFF 219#define FLD_DIF_INT_AGC 0x0000FFFF
223 220
224/*****************************************************************************/ 221/*****************************************************************************/
225#define DIF_AGC_CTRL_RF (DIRECT_IF_REVB_BASE + 0x00000020) /* Reg Size 32 */ 222#define DIF_AGC_CTRL_RF (DIRECT_IF_REVB_BASE + 0x00000020) /* Reg Size 32 */
226/*****************************************************************************/ 223/*****************************************************************************/
227#define FLD_DIF_RF_MAX 0xFF000000 224#define FLD_DIF_RF_MAX 0xFF000000
228#define FLD_DIF_RF_MIN 0x00FF0000 225#define FLD_DIF_RF_MIN 0x00FF0000
229#define FLD_DIF_RF_AGC 0x0000FFFF 226#define FLD_DIF_RF_AGC 0x0000FFFF
230 227
231/*****************************************************************************/ 228/*****************************************************************************/
232#define DIF_AGC_IF_INT_CURRENT (DIRECT_IF_REVB_BASE + 0x00000024) /* Reg Size 32 */ 229#define DIF_AGC_IF_INT_CURRENT (DIRECT_IF_REVB_BASE + 0x00000024) /* Reg Size 32 */
233/*****************************************************************************/ 230/*****************************************************************************/
234#define FLD_DIF_IF_AGC_IN 0xFFFF0000 231#define FLD_DIF_IF_AGC_IN 0xFFFF0000
235#define FLD_DIF_INT_AGC_IN 0x0000FFFF 232#define FLD_DIF_INT_AGC_IN 0x0000FFFF
236 233
237/*****************************************************************************/ 234/*****************************************************************************/
238#define DIF_AGC_RF_CURRENT (DIRECT_IF_REVB_BASE + 0x00000028) /* Reg Size 32 */ 235#define DIF_AGC_RF_CURRENT (DIRECT_IF_REVB_BASE + 0x00000028) /* Reg Size 32 */
239/*****************************************************************************/ 236/*****************************************************************************/
240/* Reserved [31:16] */ 237/* Reserved [31:16] */
241#define FLD_DIF_RF_AGC_IN 0x0000FFFF 238#define FLD_DIF_RF_AGC_IN 0x0000FFFF
242 239
243/*****************************************************************************/ 240/*****************************************************************************/
244#define DIF_VIDEO_AGC_CTRL (DIRECT_IF_REVB_BASE + 0x0000002C) /* Reg Size 32 */ 241#define DIF_VIDEO_AGC_CTRL (DIRECT_IF_REVB_BASE + 0x0000002C) /* Reg Size 32 */
245/*****************************************************************************/ 242/*****************************************************************************/
246#define FLD_DIF_AFD 0xC0000000 243#define FLD_DIF_AFD 0xC0000000
247#define FLD_DIF_K_VID_AGC 0x30000000 244#define FLD_DIF_K_VID_AGC 0x30000000
@@ -249,7 +246,7 @@ typedef enum{
249#define FLD_DIF_AGC_GAIN 0x0000FFFF 246#define FLD_DIF_AGC_GAIN 0x0000FFFF
250 247
251/*****************************************************************************/ 248/*****************************************************************************/
252#define DIF_VID_AUD_OVERRIDE (DIRECT_IF_REVB_BASE + 0x00000030) /* Reg Size 32 */ 249#define DIF_VID_AUD_OVERRIDE (DIRECT_IF_REVB_BASE + 0x00000030) /* Reg Size 32 */
253/*****************************************************************************/ 250/*****************************************************************************/
254#define FLD_DIF_AUDIO_AGC_OVERRIDE 0x80000000 251#define FLD_DIF_AUDIO_AGC_OVERRIDE 0x80000000
255/* Reserved [30:30] */ 252/* Reserved [30:30] */
@@ -259,14 +256,14 @@ typedef enum{
259#define FLD_DIF_VID_MAN_GAIN 0x0000FFFF 256#define FLD_DIF_VID_MAN_GAIN 0x0000FFFF
260 257
261/*****************************************************************************/ 258/*****************************************************************************/
262#define DIF_AV_SEP_CTRL (DIRECT_IF_REVB_BASE + 0x00000034) /* Reg Size 32 */ 259#define DIF_AV_SEP_CTRL (DIRECT_IF_REVB_BASE + 0x00000034) /* Reg Size 32 */
263/*****************************************************************************/ 260/*****************************************************************************/
264#define FLD_DIF_LPF_FREQ 0xC0000000 261#define FLD_DIF_LPF_FREQ 0xC0000000
265#define FLD_DIF_AV_PHASE_INC 0x3F000000 262#define FLD_DIF_AV_PHASE_INC 0x3F000000
266#define FLD_DIF_AUDIO_FREQ 0x00FFFFFF 263#define FLD_DIF_AUDIO_FREQ 0x00FFFFFF
267 264
268/*****************************************************************************/ 265/*****************************************************************************/
269#define DIF_COMP_FLT_CTRL (DIRECT_IF_REVB_BASE + 0x00000038) /* Reg Size 32 */ 266#define DIF_COMP_FLT_CTRL (DIRECT_IF_REVB_BASE + 0x00000038) /* Reg Size 32 */
270/*****************************************************************************/ 267/*****************************************************************************/
271/* Reserved [31:24] */ 268/* Reserved [31:24] */
272#define FLD_DIF_IIR23_R2 0x00FF0000 269#define FLD_DIF_IIR23_R2 0x00FF0000
@@ -274,7 +271,7 @@ typedef enum{
274#define FLD_DIF_IIR1_R1 0x000000FF 271#define FLD_DIF_IIR1_R1 0x000000FF
275 272
276/*****************************************************************************/ 273/*****************************************************************************/
277#define DIF_MISC_CTRL (DIRECT_IF_REVB_BASE + 0x0000003C) /* Reg Size 32 */ 274#define DIF_MISC_CTRL (DIRECT_IF_REVB_BASE + 0x0000003C) /* Reg Size 32 */
278/*****************************************************************************/ 275/*****************************************************************************/
279#define FLD_DIF_DIF_BYPASS 0x80000000 276#define FLD_DIF_DIF_BYPASS 0x80000000
280#define FLD_DIF_FM_NYQ_GAIN 0x40000000 277#define FLD_DIF_FM_NYQ_GAIN 0x40000000
@@ -299,20 +296,20 @@ typedef enum{
299#define FLD_DIF_RF_IF_LOCK 0x00000001 296#define FLD_DIF_RF_IF_LOCK 0x00000001
300 297
301/*****************************************************************************/ 298/*****************************************************************************/
302#define DIF_SRC_PHASE_INC (DIRECT_IF_REVB_BASE + 0x00000040) /* Reg Size 32 */ 299#define DIF_SRC_PHASE_INC (DIRECT_IF_REVB_BASE + 0x00000040) /* Reg Size 32 */
303/*****************************************************************************/ 300/*****************************************************************************/
304/* Reserved [31:29] */ 301/* Reserved [31:29] */
305#define FLD_DIF_PHASE_INC 0x1FFFFFFF 302#define FLD_DIF_PHASE_INC 0x1FFFFFFF
306 303
307/*****************************************************************************/ 304/*****************************************************************************/
308#define DIF_SRC_GAIN_CONTROL (DIRECT_IF_REVB_BASE + 0x00000044) /* Reg Size 32 */ 305#define DIF_SRC_GAIN_CONTROL (DIRECT_IF_REVB_BASE + 0x00000044) /* Reg Size 32 */
309/*****************************************************************************/ 306/*****************************************************************************/
310/* Reserved [31:16] */ 307/* Reserved [31:16] */
311#define FLD_DIF_SRC_KI 0x0000FF00 308#define FLD_DIF_SRC_KI 0x0000FF00
312#define FLD_DIF_SRC_KD 0x000000FF 309#define FLD_DIF_SRC_KD 0x000000FF
313 310
314/*****************************************************************************/ 311/*****************************************************************************/
315#define DIF_BPF_COEFF01 (DIRECT_IF_REVB_BASE + 0x00000048) /* Reg Size 32 */ 312#define DIF_BPF_COEFF01 (DIRECT_IF_REVB_BASE + 0x00000048) /* Reg Size 32 */
316/*****************************************************************************/ 313/*****************************************************************************/
317/* Reserved [31:19] */ 314/* Reserved [31:19] */
318#define FLD_DIF_BPF_COEFF_0 0x00070000 315#define FLD_DIF_BPF_COEFF_0 0x00070000
@@ -320,7 +317,7 @@ typedef enum{
320#define FLD_DIF_BPF_COEFF_1 0x0000000F 317#define FLD_DIF_BPF_COEFF_1 0x0000000F
321 318
322/*****************************************************************************/ 319/*****************************************************************************/
323#define DIF_BPF_COEFF23 (DIRECT_IF_REVB_BASE + 0x0000004c) /* Reg Size 32 */ 320#define DIF_BPF_COEFF23 (DIRECT_IF_REVB_BASE + 0x0000004c) /* Reg Size 32 */
324/*****************************************************************************/ 321/*****************************************************************************/
325/* Reserved [31:22] */ 322/* Reserved [31:22] */
326#define FLD_DIF_BPF_COEFF_2 0x003F0000 323#define FLD_DIF_BPF_COEFF_2 0x003F0000
@@ -328,7 +325,7 @@ typedef enum{
328#define FLD_DIF_BPF_COEFF_3 0x0000007F 325#define FLD_DIF_BPF_COEFF_3 0x0000007F
329 326
330/*****************************************************************************/ 327/*****************************************************************************/
331#define DIF_BPF_COEFF45 (DIRECT_IF_REVB_BASE + 0x00000050) /* Reg Size 32 */ 328#define DIF_BPF_COEFF45 (DIRECT_IF_REVB_BASE + 0x00000050) /* Reg Size 32 */
332/*****************************************************************************/ 329/*****************************************************************************/
333/* Reserved [31:24] */ 330/* Reserved [31:24] */
334#define FLD_DIF_BPF_COEFF_4 0x00FF0000 331#define FLD_DIF_BPF_COEFF_4 0x00FF0000
@@ -336,7 +333,7 @@ typedef enum{
336#define FLD_DIF_BPF_COEFF_5 0x000000FF 333#define FLD_DIF_BPF_COEFF_5 0x000000FF
337 334
338/*****************************************************************************/ 335/*****************************************************************************/
339#define DIF_BPF_COEFF67 (DIRECT_IF_REVB_BASE + 0x00000054) /* Reg Size 32 */ 336#define DIF_BPF_COEFF67 (DIRECT_IF_REVB_BASE + 0x00000054) /* Reg Size 32 */
340/*****************************************************************************/ 337/*****************************************************************************/
341/* Reserved [31:25] */ 338/* Reserved [31:25] */
342#define FLD_DIF_BPF_COEFF_6 0x01FF0000 339#define FLD_DIF_BPF_COEFF_6 0x01FF0000
@@ -344,7 +341,7 @@ typedef enum{
344#define FLD_DIF_BPF_COEFF_7 0x000001FF 341#define FLD_DIF_BPF_COEFF_7 0x000001FF
345 342
346/*****************************************************************************/ 343/*****************************************************************************/
347#define DIF_BPF_COEFF89 (DIRECT_IF_REVB_BASE + 0x00000058) /* Reg Size 32 */ 344#define DIF_BPF_COEFF89 (DIRECT_IF_REVB_BASE + 0x00000058) /* Reg Size 32 */
348/*****************************************************************************/ 345/*****************************************************************************/
349/* Reserved [31:26] */ 346/* Reserved [31:26] */
350#define FLD_DIF_BPF_COEFF_8 0x03FF0000 347#define FLD_DIF_BPF_COEFF_8 0x03FF0000
@@ -352,7 +349,7 @@ typedef enum{
352#define FLD_DIF_BPF_COEFF_9 0x000003FF 349#define FLD_DIF_BPF_COEFF_9 0x000003FF
353 350
354/*****************************************************************************/ 351/*****************************************************************************/
355#define DIF_BPF_COEFF1011 (DIRECT_IF_REVB_BASE + 0x0000005C) /* Reg Size 32 */ 352#define DIF_BPF_COEFF1011 (DIRECT_IF_REVB_BASE + 0x0000005C) /* Reg Size 32 */
356/*****************************************************************************/ 353/*****************************************************************************/
357/* Reserved [31:27] */ 354/* Reserved [31:27] */
358#define FLD_DIF_BPF_COEFF_10 0x07FF0000 355#define FLD_DIF_BPF_COEFF_10 0x07FF0000
@@ -360,7 +357,7 @@ typedef enum{
360#define FLD_DIF_BPF_COEFF_11 0x000007FF 357#define FLD_DIF_BPF_COEFF_11 0x000007FF
361 358
362/*****************************************************************************/ 359/*****************************************************************************/
363#define DIF_BPF_COEFF1213 (DIRECT_IF_REVB_BASE + 0x00000060) /* Reg Size 32 */ 360#define DIF_BPF_COEFF1213 (DIRECT_IF_REVB_BASE + 0x00000060) /* Reg Size 32 */
364/*****************************************************************************/ 361/*****************************************************************************/
365/* Reserved [31:27] */ 362/* Reserved [31:27] */
366#define FLD_DIF_BPF_COEFF_12 0x07FF0000 363#define FLD_DIF_BPF_COEFF_12 0x07FF0000
@@ -368,7 +365,7 @@ typedef enum{
368#define FLD_DIF_BPF_COEFF_13 0x00000FFF 365#define FLD_DIF_BPF_COEFF_13 0x00000FFF
369 366
370/*****************************************************************************/ 367/*****************************************************************************/
371#define DIF_BPF_COEFF1415 (DIRECT_IF_REVB_BASE + 0x00000064) /* Reg Size 32 */ 368#define DIF_BPF_COEFF1415 (DIRECT_IF_REVB_BASE + 0x00000064) /* Reg Size 32 */
372/*****************************************************************************/ 369/*****************************************************************************/
373/* Reserved [31:28] */ 370/* Reserved [31:28] */
374#define FLD_DIF_BPF_COEFF_14 0x0FFF0000 371#define FLD_DIF_BPF_COEFF_14 0x0FFF0000
@@ -376,7 +373,7 @@ typedef enum{
376#define FLD_DIF_BPF_COEFF_15 0x00000FFF 373#define FLD_DIF_BPF_COEFF_15 0x00000FFF
377 374
378/*****************************************************************************/ 375/*****************************************************************************/
379#define DIF_BPF_COEFF1617 (DIRECT_IF_REVB_BASE + 0x00000068) /* Reg Size 32 */ 376#define DIF_BPF_COEFF1617 (DIRECT_IF_REVB_BASE + 0x00000068) /* Reg Size 32 */
380/*****************************************************************************/ 377/*****************************************************************************/
381/* Reserved [31:29] */ 378/* Reserved [31:29] */
382#define FLD_DIF_BPF_COEFF_16 0x1FFF0000 379#define FLD_DIF_BPF_COEFF_16 0x1FFF0000
@@ -384,7 +381,7 @@ typedef enum{
384#define FLD_DIF_BPF_COEFF_17 0x00001FFF 381#define FLD_DIF_BPF_COEFF_17 0x00001FFF
385 382
386/*****************************************************************************/ 383/*****************************************************************************/
387#define DIF_BPF_COEFF1819 (DIRECT_IF_REVB_BASE + 0x0000006C) /* Reg Size 32 */ 384#define DIF_BPF_COEFF1819 (DIRECT_IF_REVB_BASE + 0x0000006C) /* Reg Size 32 */
388/*****************************************************************************/ 385/*****************************************************************************/
389/* Reserved [31:29] */ 386/* Reserved [31:29] */
390#define FLD_DIF_BPF_COEFF_18 0x1FFF0000 387#define FLD_DIF_BPF_COEFF_18 0x1FFF0000
@@ -392,7 +389,7 @@ typedef enum{
392#define FLD_DIF_BPF_COEFF_19 0x00001FFF 389#define FLD_DIF_BPF_COEFF_19 0x00001FFF
393 390
394/*****************************************************************************/ 391/*****************************************************************************/
395#define DIF_BPF_COEFF2021 (DIRECT_IF_REVB_BASE + 0x00000070) /* Reg Size 32 */ 392#define DIF_BPF_COEFF2021 (DIRECT_IF_REVB_BASE + 0x00000070) /* Reg Size 32 */
396/*****************************************************************************/ 393/*****************************************************************************/
397/* Reserved [31:29] */ 394/* Reserved [31:29] */
398#define FLD_DIF_BPF_COEFF_20 0x1FFF0000 395#define FLD_DIF_BPF_COEFF_20 0x1FFF0000
@@ -400,7 +397,7 @@ typedef enum{
400#define FLD_DIF_BPF_COEFF_21 0x00003FFF 397#define FLD_DIF_BPF_COEFF_21 0x00003FFF
401 398
402/*****************************************************************************/ 399/*****************************************************************************/
403#define DIF_BPF_COEFF2223 (DIRECT_IF_REVB_BASE + 0x00000074) /* Reg Size 32 */ 400#define DIF_BPF_COEFF2223 (DIRECT_IF_REVB_BASE + 0x00000074) /* Reg Size 32 */
404/*****************************************************************************/ 401/*****************************************************************************/
405/* Reserved [31:30] */ 402/* Reserved [31:30] */
406#define FLD_DIF_BPF_COEFF_22 0x3FFF0000 403#define FLD_DIF_BPF_COEFF_22 0x3FFF0000
@@ -408,7 +405,7 @@ typedef enum{
408#define FLD_DIF_BPF_COEFF_23 0x00003FFF 405#define FLD_DIF_BPF_COEFF_23 0x00003FFF
409 406
410/*****************************************************************************/ 407/*****************************************************************************/
411#define DIF_BPF_COEFF2425 (DIRECT_IF_REVB_BASE + 0x00000078) /* Reg Size 32 */ 408#define DIF_BPF_COEFF2425 (DIRECT_IF_REVB_BASE + 0x00000078) /* Reg Size 32 */
412/*****************************************************************************/ 409/*****************************************************************************/
413/* Reserved [31:30] */ 410/* Reserved [31:30] */
414#define FLD_DIF_BPF_COEFF_24 0x3FFF0000 411#define FLD_DIF_BPF_COEFF_24 0x3FFF0000
@@ -416,7 +413,7 @@ typedef enum{
416#define FLD_DIF_BPF_COEFF_25 0x00003FFF 413#define FLD_DIF_BPF_COEFF_25 0x00003FFF
417 414
418/*****************************************************************************/ 415/*****************************************************************************/
419#define DIF_BPF_COEFF2627 (DIRECT_IF_REVB_BASE + 0x0000007C) /* Reg Size 32 */ 416#define DIF_BPF_COEFF2627 (DIRECT_IF_REVB_BASE + 0x0000007C) /* Reg Size 32 */
420/*****************************************************************************/ 417/*****************************************************************************/
421/* Reserved [31:30] */ 418/* Reserved [31:30] */
422#define FLD_DIF_BPF_COEFF_26 0x3FFF0000 419#define FLD_DIF_BPF_COEFF_26 0x3FFF0000
@@ -424,7 +421,7 @@ typedef enum{
424#define FLD_DIF_BPF_COEFF_27 0x00003FFF 421#define FLD_DIF_BPF_COEFF_27 0x00003FFF
425 422
426/*****************************************************************************/ 423/*****************************************************************************/
427#define DIF_BPF_COEFF2829 (DIRECT_IF_REVB_BASE + 0x00000080) /* Reg Size 32 */ 424#define DIF_BPF_COEFF2829 (DIRECT_IF_REVB_BASE + 0x00000080) /* Reg Size 32 */
428/*****************************************************************************/ 425/*****************************************************************************/
429/* Reserved [31:30] */ 426/* Reserved [31:30] */
430#define FLD_DIF_BPF_COEFF_28 0x3FFF0000 427#define FLD_DIF_BPF_COEFF_28 0x3FFF0000
@@ -432,7 +429,7 @@ typedef enum{
432#define FLD_DIF_BPF_COEFF_29 0x00003FFF 429#define FLD_DIF_BPF_COEFF_29 0x00003FFF
433 430
434/*****************************************************************************/ 431/*****************************************************************************/
435#define DIF_BPF_COEFF3031 (DIRECT_IF_REVB_BASE + 0x00000084) /* Reg Size 32 */ 432#define DIF_BPF_COEFF3031 (DIRECT_IF_REVB_BASE + 0x00000084) /* Reg Size 32 */
436/*****************************************************************************/ 433/*****************************************************************************/
437/* Reserved [31:30] */ 434/* Reserved [31:30] */
438#define FLD_DIF_BPF_COEFF_30 0x3FFF0000 435#define FLD_DIF_BPF_COEFF_30 0x3FFF0000
@@ -440,7 +437,7 @@ typedef enum{
440#define FLD_DIF_BPF_COEFF_31 0x00003FFF 437#define FLD_DIF_BPF_COEFF_31 0x00003FFF
441 438
442/*****************************************************************************/ 439/*****************************************************************************/
443#define DIF_BPF_COEFF3233 (DIRECT_IF_REVB_BASE + 0x00000088) /* Reg Size 32 */ 440#define DIF_BPF_COEFF3233 (DIRECT_IF_REVB_BASE + 0x00000088) /* Reg Size 32 */
444/*****************************************************************************/ 441/*****************************************************************************/
445/* Reserved [31:30] */ 442/* Reserved [31:30] */
446#define FLD_DIF_BPF_COEFF_32 0x3FFF0000 443#define FLD_DIF_BPF_COEFF_32 0x3FFF0000
@@ -448,7 +445,7 @@ typedef enum{
448#define FLD_DIF_BPF_COEFF_33 0x00003FFF 445#define FLD_DIF_BPF_COEFF_33 0x00003FFF
449 446
450/*****************************************************************************/ 447/*****************************************************************************/
451#define DIF_BPF_COEFF3435 (DIRECT_IF_REVB_BASE + 0x0000008C) /* Reg Size 32 */ 448#define DIF_BPF_COEFF3435 (DIRECT_IF_REVB_BASE + 0x0000008C) /* Reg Size 32 */
452/*****************************************************************************/ 449/*****************************************************************************/
453/* Reserved [31:30] */ 450/* Reserved [31:30] */
454#define FLD_DIF_BPF_COEFF_34 0x3FFF0000 451#define FLD_DIF_BPF_COEFF_34 0x3FFF0000
@@ -456,20 +453,20 @@ typedef enum{
456#define FLD_DIF_BPF_COEFF_35 0x00003FFF 453#define FLD_DIF_BPF_COEFF_35 0x00003FFF
457 454
458/*****************************************************************************/ 455/*****************************************************************************/
459#define DIF_BPF_COEFF36 (DIRECT_IF_REVB_BASE + 0x00000090) /* Reg Size 32 */ 456#define DIF_BPF_COEFF36 (DIRECT_IF_REVB_BASE + 0x00000090) /* Reg Size 32 */
460/*****************************************************************************/ 457/*****************************************************************************/
461/* Reserved [31:30] */ 458/* Reserved [31:30] */
462#define FLD_DIF_BPF_COEFF_36 0x3FFF0000 459#define FLD_DIF_BPF_COEFF_36 0x3FFF0000
463/* Reserved [15:0] */ 460/* Reserved [15:0] */
464 461
465/*****************************************************************************/ 462/*****************************************************************************/
466#define DIF_RPT_VARIANCE (DIRECT_IF_REVB_BASE + 0x00000094) /* Reg Size 32 */ 463#define DIF_RPT_VARIANCE (DIRECT_IF_REVB_BASE + 0x00000094) /* Reg Size 32 */
467/*****************************************************************************/ 464/*****************************************************************************/
468/* Reserved [31:20] */ 465/* Reserved [31:20] */
469#define FLD_DIF_RPT_VARIANCE 0x000FFFFF 466#define FLD_DIF_RPT_VARIANCE 0x000FFFFF
470 467
471/*****************************************************************************/ 468/*****************************************************************************/
472#define DIF_SOFT_RST_CTRL_REVB (DIRECT_IF_REVB_BASE + 0x00000098) /* Reg Size 32 */ 469#define DIF_SOFT_RST_CTRL_REVB (DIRECT_IF_REVB_BASE + 0x00000098) /* Reg Size 32 */
473/*****************************************************************************/ 470/*****************************************************************************/
474/* Reserved [31:8] */ 471/* Reserved [31:8] */
475#define FLD_DIF_DIF_SOFT_RST 0x00000080 472#define FLD_DIF_DIF_SOFT_RST 0x00000080
@@ -482,10 +479,9 @@ typedef enum{
482#define FLD_DIF_PLL_RST_MSK 0x00000001 479#define FLD_DIF_PLL_RST_MSK 0x00000001
483 480
484/*****************************************************************************/ 481/*****************************************************************************/
485#define DIF_PLL_FREQ_ERR (DIRECT_IF_REVB_BASE + 0x0000009C) /* Reg Size 32 */ 482#define DIF_PLL_FREQ_ERR (DIRECT_IF_REVB_BASE + 0x0000009C) /* Reg Size 32 */
486/*****************************************************************************/ 483/*****************************************************************************/
487/* Reserved [31:25] */ 484/* Reserved [31:25] */
488#define FLD_DIF_CTL_IP 0x01FFFFFF 485#define FLD_DIF_CTL_IP 0x01FFFFFF
489 486
490
491#endif 487#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-15 13:46:19 -0500