diff options
author | Andy Walls <awalls@radix.net> | 2008-10-31 19:49:12 -0400 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2008-11-11 05:11:28 -0500 |
commit | f056d29eebd2c8800cf42528ba0470c77a928821 (patch) | |
tree | ec57c96e5b7b95ef2597c572f6c90dfa0a40581f /drivers/media/video/cx18/cx18-mailbox.c | |
parent | 58ae1c23184772a7b2d02a4a82f5515a7820a155 (diff) |
V4L/DVB (9510): cx18: Fix write retries for registers that always change - part 2.
cx18: Fix write retries for registers that always change - part 2.
Some registers, especially interrupt related ones, will never read
back the value just written. Modified interrupt register readback
checks to make sure the intended effect was achieved.
Signed-off-by: Andy Walls <awalls@radix.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/video/cx18/cx18-mailbox.c')
-rw-r--r-- | drivers/media/video/cx18/cx18-mailbox.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/media/video/cx18/cx18-mailbox.c b/drivers/media/video/cx18/cx18-mailbox.c index 87f7c8e2c181..851a905376bb 100644 --- a/drivers/media/video/cx18/cx18-mailbox.c +++ b/drivers/media/video/cx18/cx18-mailbox.c | |||
@@ -176,7 +176,7 @@ long cx18_mb_ack(struct cx18 *cx, const struct cx18_mailbox *mb) | |||
176 | 176 | ||
177 | cx18_setup_page(cx, SCB_OFFSET); | 177 | cx18_setup_page(cx, SCB_OFFSET); |
178 | cx18_write_sync(cx, mb->request, &ack_mb->ack); | 178 | cx18_write_sync(cx, mb->request, &ack_mb->ack); |
179 | cx18_write_reg_noretry(cx, ack_irq, SW2_INT_SET); | 179 | cx18_write_reg_expect(cx, ack_irq, SW2_INT_SET, ack_irq, ack_irq); |
180 | return 0; | 180 | return 0; |
181 | } | 181 | } |
182 | 182 | ||
@@ -225,7 +225,7 @@ static int cx18_api_call(struct cx18 *cx, u32 cmd, int args, u32 data[]) | |||
225 | } | 225 | } |
226 | if (info->flags & API_FAST) | 226 | if (info->flags & API_FAST) |
227 | timeout /= 2; | 227 | timeout /= 2; |
228 | cx18_write_reg_noretry(cx, irq, SW1_INT_SET); | 228 | cx18_write_reg_expect(cx, irq, SW1_INT_SET, irq, irq); |
229 | 229 | ||
230 | while (!sig && cx18_readl(cx, &mb->ack) != cx18_readl(cx, &mb->request) | 230 | while (!sig && cx18_readl(cx, &mb->ack) != cx18_readl(cx, &mb->request) |
231 | && cnt < 660) { | 231 | && cnt < 660) { |