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authorAndy Walls <awalls@radix.net>2008-11-16 21:33:41 -0500
committerMauro Carvalho Chehab <mchehab@redhat.com>2008-12-30 06:38:09 -0500
commit3f75c6161f28e6a17c547daf552c1127c805c5e7 (patch)
tree1e4db5013c05946832221bfdca743720091f6582 /drivers/media/video/cx18/cx18-io.h
parent72a4f8081af1c53a1673c173ce0fdd85c4b7d403 (diff)
V4L/DVB (9724): cx18: Streamline cx18-io[ch] wrappers and enforce MMIO retry strategy
cx18: Streamline cx18-io[ch] wrappers and enforce MMIO retry strategy so that write retries always occur and read retries never occur (as they never help). Remove MMIO statistics logging to speed up MMIO accesses. Deprecate & ignore retry_mmio and mmio_ndelay module parameters, to essentially force retry_mmio=1 and mmio_ndelay=0. Signed-off-by: Andy Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/video/cx18/cx18-io.h')
-rw-r--r--drivers/media/video/cx18/cx18-io.h320
1 files changed, 55 insertions, 265 deletions
diff --git a/drivers/media/video/cx18/cx18-io.h b/drivers/media/video/cx18/cx18-io.h
index fdc2bcc92fca..73321fb4cbf5 100644
--- a/drivers/media/video/cx18/cx18-io.h
+++ b/drivers/media/video/cx18/cx18-io.h
@@ -25,230 +25,118 @@
25 25
26#include "cx18-driver.h" 26#include "cx18-driver.h"
27 27
28static inline void cx18_io_delay(struct cx18 *cx)
29{
30 if (cx->options.mmio_ndelay)
31 ndelay(cx->options.mmio_ndelay);
32}
33
34/* 28/*
35 * Readback and retry of MMIO access for reliability: 29 * Readback and retry of MMIO access for reliability:
36 * The concept was suggested by Steve Toth <stoth@linuxtv.org>. 30 * The concept was suggested by Steve Toth <stoth@linuxtv.org>.
37 * The implmentation is the fault of Andy Walls <awalls@radix.net>. 31 * The implmentation is the fault of Andy Walls <awalls@radix.net>.
32 *
33 * *write* functions are implied to retry the mmio unless suffixed with _noretry
34 * *read* functions never retry the mmio (it never helps to do so)
38 */ 35 */
39 36
40/* Statistics gathering */ 37/* Statistics gathering */
41static inline
42void cx18_log_write_retries(struct cx18 *cx, int i, const void __iomem *addr)
43{
44 if (i > CX18_MAX_MMIO_WR_RETRIES)
45 i = CX18_MAX_MMIO_WR_RETRIES;
46 atomic_inc(&cx->mmio_stats.retried_write[i]);
47 return;
48}
49
50static inline
51void cx18_log_read_retries(struct cx18 *cx, int i, const void __iomem *addr)
52{
53 if (i > CX18_MAX_MMIO_RD_RETRIES)
54 i = CX18_MAX_MMIO_RD_RETRIES;
55 atomic_inc(&cx->mmio_stats.retried_read[i]);
56 return;
57}
58 38
59void cx18_log_statistics(struct cx18 *cx); 39void cx18_log_statistics(struct cx18 *cx);
60 40
61/* Non byteswapping memory mapped IO */ 41/* Non byteswapping memory mapped IO */
42static inline u32 cx18_raw_readl(struct cx18 *cx, const void __iomem *addr)
43{
44 return __raw_readl(addr);
45}
46
62static inline 47static inline
63void cx18_raw_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr) 48void cx18_raw_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr)
64{ 49{
65 __raw_writel(val, addr); 50 __raw_writel(val, addr);
66 cx18_io_delay(cx);
67} 51}
68 52
69void cx18_raw_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr);
70
71static inline void cx18_raw_writel(struct cx18 *cx, u32 val, void __iomem *addr) 53static inline void cx18_raw_writel(struct cx18 *cx, u32 val, void __iomem *addr)
72{ 54{
73 if (cx18_retry_mmio) 55 int i;
74 cx18_raw_writel_retry(cx, val, addr); 56 for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
75 else
76 cx18_raw_writel_noretry(cx, val, addr); 57 cx18_raw_writel_noretry(cx, val, addr);
58 if (val == cx18_raw_readl(cx, addr))
59 break;
60 }
77} 61}
78 62
79 63/* Normal memory mapped IO */
80static inline 64static inline u32 cx18_readl(struct cx18 *cx, const void __iomem *addr)
81u32 cx18_raw_readl_noretry(struct cx18 *cx, const void __iomem *addr)
82{
83 u32 ret = __raw_readl(addr);
84 cx18_io_delay(cx);
85 return ret;
86}
87
88u32 cx18_raw_readl_retry(struct cx18 *cx, const void __iomem *addr);
89
90static inline u32 cx18_raw_readl(struct cx18 *cx, const void __iomem *addr)
91{ 65{
92 if (cx18_retry_mmio) 66 return readl(addr);
93 return cx18_raw_readl_retry(cx, addr);
94
95 return cx18_raw_readl_noretry(cx, addr);
96} 67}
97 68
98
99static inline 69static inline
100u16 cx18_raw_readw_noretry(struct cx18 *cx, const void __iomem *addr) 70void cx18_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr)
101{ 71{
102 u16 ret = __raw_readw(addr); 72 writel(val, addr);
103 cx18_io_delay(cx);
104 return ret;
105} 73}
106 74
107u16 cx18_raw_readw_retry(struct cx18 *cx, const void __iomem *addr); 75static inline void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr)
108
109static inline u16 cx18_raw_readw(struct cx18 *cx, const void __iomem *addr)
110{ 76{
111 if (cx18_retry_mmio) 77 int i;
112 return cx18_raw_readw_retry(cx, addr); 78 for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
113 79 cx18_writel_noretry(cx, val, addr);
114 return cx18_raw_readw_noretry(cx, addr); 80 if (val == cx18_readl(cx, addr))
81 break;
82 }
115} 83}
116 84
117
118/* Normal memory mapped IO */
119static inline 85static inline
120void cx18_writel_noretry(struct cx18 *cx, u32 val, void __iomem *addr) 86void cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr,
87 u32 eval, u32 mask)
121{ 88{
122 writel(val, addr); 89 int i;
123 cx18_io_delay(cx); 90 eval &= mask;
91 for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
92 cx18_writel_noretry(cx, val, addr);
93 if (eval == (cx18_readl(cx, addr) & mask))
94 break;
95 }
124} 96}
125 97
126void cx18_writel_retry(struct cx18 *cx, u32 val, void __iomem *addr); 98static inline u16 cx18_readw(struct cx18 *cx, const void __iomem *addr)
127
128static inline void cx18_writel(struct cx18 *cx, u32 val, void __iomem *addr)
129{ 99{
130 if (cx18_retry_mmio) 100 return readw(addr);
131 cx18_writel_retry(cx, val, addr);
132 else
133 cx18_writel_noretry(cx, val, addr);
134} 101}
135 102
136void _cx18_writel_expect(struct cx18 *cx, u32 val, void __iomem *addr,
137 u32 eval, u32 mask);
138
139static inline 103static inline
140void cx18_writew_noretry(struct cx18 *cx, u16 val, void __iomem *addr) 104void cx18_writew_noretry(struct cx18 *cx, u16 val, void __iomem *addr)
141{ 105{
142 writew(val, addr); 106 writew(val, addr);
143 cx18_io_delay(cx);
144} 107}
145 108
146void cx18_writew_retry(struct cx18 *cx, u16 val, void __iomem *addr);
147
148static inline void cx18_writew(struct cx18 *cx, u16 val, void __iomem *addr) 109static inline void cx18_writew(struct cx18 *cx, u16 val, void __iomem *addr)
149{ 110{
150 if (cx18_retry_mmio) 111 int i;
151 cx18_writew_retry(cx, val, addr); 112 for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
152 else
153 cx18_writew_noretry(cx, val, addr); 113 cx18_writew_noretry(cx, val, addr);
114 if (val == cx18_readw(cx, addr))
115 break;
116 }
154} 117}
155 118
119static inline u8 cx18_readb(struct cx18 *cx, const void __iomem *addr)
120{
121 return readb(addr);
122}
156 123
157static inline 124static inline
158void cx18_writeb_noretry(struct cx18 *cx, u8 val, void __iomem *addr) 125void cx18_writeb_noretry(struct cx18 *cx, u8 val, void __iomem *addr)
159{ 126{
160 writeb(val, addr); 127 writeb(val, addr);
161 cx18_io_delay(cx);
162} 128}
163 129
164void cx18_writeb_retry(struct cx18 *cx, u8 val, void __iomem *addr);
165
166static inline void cx18_writeb(struct cx18 *cx, u8 val, void __iomem *addr) 130static inline void cx18_writeb(struct cx18 *cx, u8 val, void __iomem *addr)
167{ 131{
168 if (cx18_retry_mmio) 132 int i;
169 cx18_writeb_retry(cx, val, addr); 133 for (i = 0; i < CX18_MAX_MMIO_WR_RETRIES; i++) {
170 else
171 cx18_writeb_noretry(cx, val, addr); 134 cx18_writeb_noretry(cx, val, addr);
135 if (val == cx18_readb(cx, addr))
136 break;
137 }
172} 138}
173 139
174
175static inline u32 cx18_readl_noretry(struct cx18 *cx, const void __iomem *addr)
176{
177 u32 ret = readl(addr);
178 cx18_io_delay(cx);
179 return ret;
180}
181
182u32 cx18_readl_retry(struct cx18 *cx, const void __iomem *addr);
183
184static inline u32 cx18_readl(struct cx18 *cx, const void __iomem *addr)
185{
186 if (cx18_retry_mmio)
187 return cx18_readl_retry(cx, addr);
188
189 return cx18_readl_noretry(cx, addr);
190}
191
192
193static inline u16 cx18_readw_noretry(struct cx18 *cx, const void __iomem *addr)
194{
195 u16 ret = readw(addr);
196 cx18_io_delay(cx);
197 return ret;
198}
199
200u16 cx18_readw_retry(struct cx18 *cx, const void __iomem *addr);
201
202static inline u16 cx18_readw(struct cx18 *cx, const void __iomem *addr)
203{
204 if (cx18_retry_mmio)
205 return cx18_readw_retry(cx, addr);
206
207 return cx18_readw_noretry(cx, addr);
208}
209
210
211static inline u8 cx18_readb_noretry(struct cx18 *cx, const void __iomem *addr)
212{
213 u8 ret = readb(addr);
214 cx18_io_delay(cx);
215 return ret;
216}
217
218u8 cx18_readb_retry(struct cx18 *cx, const void __iomem *addr);
219
220static inline u8 cx18_readb(struct cx18 *cx, const void __iomem *addr)
221{
222 if (cx18_retry_mmio)
223 return cx18_readb_retry(cx, addr);
224
225 return cx18_readb_noretry(cx, addr);
226}
227
228
229static inline
230u32 cx18_write_sync_noretry(struct cx18 *cx, u32 val, void __iomem *addr)
231{
232 cx18_writel_noretry(cx, val, addr);
233 return cx18_readl_noretry(cx, addr);
234}
235
236static inline
237u32 cx18_write_sync_retry(struct cx18 *cx, u32 val, void __iomem *addr)
238{
239 cx18_writel_retry(cx, val, addr);
240 return cx18_readl_retry(cx, addr);
241}
242
243static inline u32 cx18_write_sync(struct cx18 *cx, u32 val, void __iomem *addr)
244{
245 if (cx18_retry_mmio)
246 return cx18_write_sync_retry(cx, val, addr);
247
248 return cx18_write_sync_noretry(cx, val, addr);
249}
250
251
252static inline 140static inline
253void cx18_memcpy_fromio(struct cx18 *cx, void *to, 141void cx18_memcpy_fromio(struct cx18 *cx, void *to,
254 const void __iomem *from, unsigned int len) 142 const void __iomem *from, unsigned int len)
@@ -265,130 +153,32 @@ static inline void cx18_write_reg_noretry(struct cx18 *cx, u32 val, u32 reg)
265 cx18_writel_noretry(cx, val, cx->reg_mem + reg); 153 cx18_writel_noretry(cx, val, cx->reg_mem + reg);
266} 154}
267 155
268static inline void cx18_write_reg_retry(struct cx18 *cx, u32 val, u32 reg)
269{
270 cx18_writel_retry(cx, val, cx->reg_mem + reg);
271}
272
273static inline void cx18_write_reg(struct cx18 *cx, u32 val, u32 reg) 156static inline void cx18_write_reg(struct cx18 *cx, u32 val, u32 reg)
274{ 157{
275 if (cx18_retry_mmio) 158 cx18_writel(cx, val, cx->reg_mem + reg);
276 cx18_write_reg_retry(cx, val, reg);
277 else
278 cx18_write_reg_noretry(cx, val, reg);
279}
280
281static inline void _cx18_write_reg_expect(struct cx18 *cx, u32 val, u32 reg,
282 u32 eval, u32 mask)
283{
284 _cx18_writel_expect(cx, val, cx->reg_mem + reg, eval, mask);
285} 159}
286 160
287static inline void cx18_write_reg_expect(struct cx18 *cx, u32 val, u32 reg, 161static inline void cx18_write_reg_expect(struct cx18 *cx, u32 val, u32 reg,
288 u32 eval, u32 mask) 162 u32 eval, u32 mask)
289{ 163{
290 if (cx18_retry_mmio) 164 cx18_writel_expect(cx, val, cx->reg_mem + reg, eval, mask);
291 _cx18_write_reg_expect(cx, val, reg, eval, mask);
292 else
293 cx18_write_reg_noretry(cx, val, reg);
294}
295
296
297static inline u32 cx18_read_reg_noretry(struct cx18 *cx, u32 reg)
298{
299 return cx18_readl_noretry(cx, cx->reg_mem + reg);
300}
301
302static inline u32 cx18_read_reg_retry(struct cx18 *cx, u32 reg)
303{
304 return cx18_readl_retry(cx, cx->reg_mem + reg);
305} 165}
306 166
307static inline u32 cx18_read_reg(struct cx18 *cx, u32 reg) 167static inline u32 cx18_read_reg(struct cx18 *cx, u32 reg)
308{ 168{
309 if (cx18_retry_mmio) 169 return cx18_readl(cx, cx->reg_mem + reg);
310 return cx18_read_reg_retry(cx, reg);
311
312 return cx18_read_reg_noretry(cx, reg);
313}
314
315
316static inline u32 cx18_write_reg_sync_noretry(struct cx18 *cx, u32 val, u32 reg)
317{
318 return cx18_write_sync_noretry(cx, val, cx->reg_mem + reg);
319}
320
321static inline u32 cx18_write_reg_sync_retry(struct cx18 *cx, u32 val, u32 reg)
322{
323 return cx18_write_sync_retry(cx, val, cx->reg_mem + reg);
324}
325
326static inline u32 cx18_write_reg_sync(struct cx18 *cx, u32 val, u32 reg)
327{
328 if (cx18_retry_mmio)
329 return cx18_write_reg_sync_retry(cx, val, reg);
330
331 return cx18_write_reg_sync_noretry(cx, val, reg);
332} 170}
333 171
334 172
335/* Access "encoder memory" region of CX23418 memory mapped I/O */ 173/* Access "encoder memory" region of CX23418 memory mapped I/O */
336static inline void cx18_write_enc_noretry(struct cx18 *cx, u32 val, u32 addr)
337{
338 cx18_writel_noretry(cx, val, cx->enc_mem + addr);
339}
340
341static inline void cx18_write_enc_retry(struct cx18 *cx, u32 val, u32 addr)
342{
343 cx18_writel_retry(cx, val, cx->enc_mem + addr);
344}
345
346static inline void cx18_write_enc(struct cx18 *cx, u32 val, u32 addr) 174static inline void cx18_write_enc(struct cx18 *cx, u32 val, u32 addr)
347{ 175{
348 if (cx18_retry_mmio) 176 cx18_writel(cx, val, cx->enc_mem + addr);
349 cx18_write_enc_retry(cx, val, addr);
350 else
351 cx18_write_enc_noretry(cx, val, addr);
352}
353
354
355static inline u32 cx18_read_enc_noretry(struct cx18 *cx, u32 addr)
356{
357 return cx18_readl_noretry(cx, cx->enc_mem + addr);
358}
359
360static inline u32 cx18_read_enc_retry(struct cx18 *cx, u32 addr)
361{
362 return cx18_readl_retry(cx, cx->enc_mem + addr);
363} 177}
364 178
365static inline u32 cx18_read_enc(struct cx18 *cx, u32 addr) 179static inline u32 cx18_read_enc(struct cx18 *cx, u32 addr)
366{ 180{
367 if (cx18_retry_mmio) 181 return cx18_readl(cx, cx->enc_mem + addr);
368 return cx18_read_enc_retry(cx, addr);
369
370 return cx18_read_enc_noretry(cx, addr);
371}
372
373static inline
374u32 cx18_write_enc_sync_noretry(struct cx18 *cx, u32 val, u32 addr)
375{
376 return cx18_write_sync_noretry(cx, val, cx->enc_mem + addr);
377}
378
379static inline
380u32 cx18_write_enc_sync_retry(struct cx18 *cx, u32 val, u32 addr)
381{
382 return cx18_write_sync_retry(cx, val, cx->enc_mem + addr);
383}
384
385static inline
386u32 cx18_write_enc_sync(struct cx18 *cx, u32 val, u32 addr)
387{
388 if (cx18_retry_mmio)
389 return cx18_write_enc_sync_retry(cx, val, addr);
390
391 return cx18_write_enc_sync_noretry(cx, val, addr);
392} 182}
393 183
394void cx18_sw1_irq_enable(struct cx18 *cx, u32 val); 184void cx18_sw1_irq_enable(struct cx18 *cx, u32 val);