V4L/DVB (9725): cx18: Remove unnecessary MMIO accesses in time critical irq handling path

Remove unnecessary MMIO accesses in time critical irq handling path.  Also
ensured that the mailbox ack field is read in last, so we know for sure if we
have a stale mailbox or not on receipt.

Signed-off-by: Andy Walls <awalls@radix.net>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

1 files changed, 8 insertions, 12 deletions

diff --git a/drivers/media/video/cx18/cx18-io.c b/drivers/media/video/cx18/cx18-io.c
index a2b5e807faca..c6f1d0d7f2c2 100644
--- a/drivers/media/video/cx18/cx18-io.c
+++ b/drivers/media/video/cx18/cx18-io.c
@@ -71,32 +71,28 @@ void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count)
 
 void cx18_sw1_irq_enable(struct cx18 *cx, u32 val)
 {
-        u32 r;
         cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val);
-        r = cx18_read_reg(cx, SW1_INT_ENABLE_PCI);
-        cx18_write_reg(cx, r | val, SW1_INT_ENABLE_PCI);
+        cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | val;
+        cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
 }
 
 void cx18_sw1_irq_disable(struct cx18 *cx, u32 val)
 {
-        u32 r;
-        r = cx18_read_reg(cx, SW1_INT_ENABLE_PCI);
-        cx18_write_reg(cx, r & ~val, SW1_INT_ENABLE_PCI);
+        cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) & ~val;
+        cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
 }
 
 void cx18_sw2_irq_enable(struct cx18 *cx, u32 val)
 {
-        u32 r;
         cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val);
-        r = cx18_read_reg(cx, SW2_INT_ENABLE_PCI);
-        cx18_write_reg(cx, r | val, SW2_INT_ENABLE_PCI);
+        cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | val;
+        cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
 }
 
 void cx18_sw2_irq_disable(struct cx18 *cx, u32 val)
 {
-        u32 r;
-        r = cx18_read_reg(cx, SW2_INT_ENABLE_PCI);
-        cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_PCI);
+        cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) & ~val;
+        cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
 }
 
 void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val)