diff options
author | Benoît Thébaudeau <benoit.thebaudeau@advansee.com> | 2012-06-28 11:12:13 -0400 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2012-07-06 14:46:17 -0400 |
commit | ebc04047b398d415627f82653c4e722e8fc2c083 (patch) | |
tree | d69a1f781227cf2aa23805abc4292864354e7ffa /drivers/media/video/adv7393.c | |
parent | 993568d4912aa5f4692b060496a4a8d487b86515 (diff) |
[PATCH] media: add Analog Devices ADV7393 video encoder driver
Add ADV7393 I²C-based video encoder driver. This driver has been tested on
custom hardware. It has been tested for composite output. It is derived from the
ADV7343 driver.
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/video/adv7393.c')
-rw-r--r-- | drivers/media/video/adv7393.c | 487 |
1 files changed, 487 insertions, 0 deletions
diff --git a/drivers/media/video/adv7393.c b/drivers/media/video/adv7393.c new file mode 100644 index 000000000000..3dc6098c7267 --- /dev/null +++ b/drivers/media/video/adv7393.c | |||
@@ -0,0 +1,487 @@ | |||
1 | /* | ||
2 | * adv7393 - ADV7393 Video Encoder Driver | ||
3 | * | ||
4 | * The encoder hardware does not support SECAM. | ||
5 | * | ||
6 | * Copyright (C) 2010-2012 ADVANSEE - http://www.advansee.com/ | ||
7 | * Benoît Thébaudeau <benoit.thebaudeau@advansee.com> | ||
8 | * | ||
9 | * Based on ADV7343 driver, | ||
10 | * | ||
11 | * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/ | ||
12 | * | ||
13 | * This program is free software; you can redistribute it and/or | ||
14 | * modify it under the terms of the GNU General Public License as | ||
15 | * published by the Free Software Foundation version 2. | ||
16 | * | ||
17 | * This program is distributed .as is. WITHOUT ANY WARRANTY of any | ||
18 | * kind, whether express or implied; without even the implied warranty | ||
19 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
20 | * GNU General Public License for more details. | ||
21 | */ | ||
22 | |||
23 | #include <linux/kernel.h> | ||
24 | #include <linux/init.h> | ||
25 | #include <linux/ctype.h> | ||
26 | #include <linux/slab.h> | ||
27 | #include <linux/i2c.h> | ||
28 | #include <linux/device.h> | ||
29 | #include <linux/delay.h> | ||
30 | #include <linux/module.h> | ||
31 | #include <linux/videodev2.h> | ||
32 | #include <linux/uaccess.h> | ||
33 | |||
34 | #include <media/adv7393.h> | ||
35 | #include <media/v4l2-device.h> | ||
36 | #include <media/v4l2-chip-ident.h> | ||
37 | #include <media/v4l2-ctrls.h> | ||
38 | |||
39 | #include "adv7393_regs.h" | ||
40 | |||
41 | MODULE_DESCRIPTION("ADV7393 video encoder driver"); | ||
42 | MODULE_LICENSE("GPL"); | ||
43 | |||
44 | static bool debug; | ||
45 | module_param(debug, bool, 0644); | ||
46 | MODULE_PARM_DESC(debug, "Debug level 0-1"); | ||
47 | |||
48 | struct adv7393_state { | ||
49 | struct v4l2_subdev sd; | ||
50 | struct v4l2_ctrl_handler hdl; | ||
51 | u8 reg00; | ||
52 | u8 reg01; | ||
53 | u8 reg02; | ||
54 | u8 reg35; | ||
55 | u8 reg80; | ||
56 | u8 reg82; | ||
57 | u32 output; | ||
58 | v4l2_std_id std; | ||
59 | }; | ||
60 | |||
61 | static inline struct adv7393_state *to_state(struct v4l2_subdev *sd) | ||
62 | { | ||
63 | return container_of(sd, struct adv7393_state, sd); | ||
64 | } | ||
65 | |||
66 | static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl) | ||
67 | { | ||
68 | return &container_of(ctrl->handler, struct adv7393_state, hdl)->sd; | ||
69 | } | ||
70 | |||
71 | static inline int adv7393_write(struct v4l2_subdev *sd, u8 reg, u8 value) | ||
72 | { | ||
73 | struct i2c_client *client = v4l2_get_subdevdata(sd); | ||
74 | |||
75 | return i2c_smbus_write_byte_data(client, reg, value); | ||
76 | } | ||
77 | |||
78 | static const u8 adv7393_init_reg_val[] = { | ||
79 | ADV7393_SOFT_RESET, ADV7393_SOFT_RESET_DEFAULT, | ||
80 | ADV7393_POWER_MODE_REG, ADV7393_POWER_MODE_REG_DEFAULT, | ||
81 | |||
82 | ADV7393_HD_MODE_REG1, ADV7393_HD_MODE_REG1_DEFAULT, | ||
83 | ADV7393_HD_MODE_REG2, ADV7393_HD_MODE_REG2_DEFAULT, | ||
84 | ADV7393_HD_MODE_REG3, ADV7393_HD_MODE_REG3_DEFAULT, | ||
85 | ADV7393_HD_MODE_REG4, ADV7393_HD_MODE_REG4_DEFAULT, | ||
86 | ADV7393_HD_MODE_REG5, ADV7393_HD_MODE_REG5_DEFAULT, | ||
87 | ADV7393_HD_MODE_REG6, ADV7393_HD_MODE_REG6_DEFAULT, | ||
88 | ADV7393_HD_MODE_REG7, ADV7393_HD_MODE_REG7_DEFAULT, | ||
89 | |||
90 | ADV7393_SD_MODE_REG1, ADV7393_SD_MODE_REG1_DEFAULT, | ||
91 | ADV7393_SD_MODE_REG2, ADV7393_SD_MODE_REG2_DEFAULT, | ||
92 | ADV7393_SD_MODE_REG3, ADV7393_SD_MODE_REG3_DEFAULT, | ||
93 | ADV7393_SD_MODE_REG4, ADV7393_SD_MODE_REG4_DEFAULT, | ||
94 | ADV7393_SD_MODE_REG5, ADV7393_SD_MODE_REG5_DEFAULT, | ||
95 | ADV7393_SD_MODE_REG6, ADV7393_SD_MODE_REG6_DEFAULT, | ||
96 | ADV7393_SD_MODE_REG7, ADV7393_SD_MODE_REG7_DEFAULT, | ||
97 | ADV7393_SD_MODE_REG8, ADV7393_SD_MODE_REG8_DEFAULT, | ||
98 | |||
99 | ADV7393_SD_TIMING_REG0, ADV7393_SD_TIMING_REG0_DEFAULT, | ||
100 | |||
101 | ADV7393_SD_HUE_ADJUST, ADV7393_SD_HUE_ADJUST_DEFAULT, | ||
102 | ADV7393_SD_CGMS_WSS0, ADV7393_SD_CGMS_WSS0_DEFAULT, | ||
103 | ADV7393_SD_BRIGHTNESS_WSS, ADV7393_SD_BRIGHTNESS_WSS_DEFAULT, | ||
104 | }; | ||
105 | |||
106 | /* | ||
107 | * 2^32 | ||
108 | * FSC(reg) = FSC (HZ) * -------- | ||
109 | * 27000000 | ||
110 | */ | ||
111 | static const struct adv7393_std_info stdinfo[] = { | ||
112 | { | ||
113 | /* FSC(Hz) = 4,433,618.75 Hz */ | ||
114 | SD_STD_NTSC, 705268427, V4L2_STD_NTSC_443, | ||
115 | }, { | ||
116 | /* FSC(Hz) = 3,579,545.45 Hz */ | ||
117 | SD_STD_NTSC, 569408542, V4L2_STD_NTSC, | ||
118 | }, { | ||
119 | /* FSC(Hz) = 3,575,611.00 Hz */ | ||
120 | SD_STD_PAL_M, 568782678, V4L2_STD_PAL_M, | ||
121 | }, { | ||
122 | /* FSC(Hz) = 3,582,056.00 Hz */ | ||
123 | SD_STD_PAL_N, 569807903, V4L2_STD_PAL_Nc, | ||
124 | }, { | ||
125 | /* FSC(Hz) = 4,433,618.75 Hz */ | ||
126 | SD_STD_PAL_N, 705268427, V4L2_STD_PAL_N, | ||
127 | }, { | ||
128 | /* FSC(Hz) = 4,433,618.75 Hz */ | ||
129 | SD_STD_PAL_M, 705268427, V4L2_STD_PAL_60, | ||
130 | }, { | ||
131 | /* FSC(Hz) = 4,433,618.75 Hz */ | ||
132 | SD_STD_PAL_BDGHI, 705268427, V4L2_STD_PAL, | ||
133 | }, | ||
134 | }; | ||
135 | |||
136 | static int adv7393_setstd(struct v4l2_subdev *sd, v4l2_std_id std) | ||
137 | { | ||
138 | struct adv7393_state *state = to_state(sd); | ||
139 | const struct adv7393_std_info *std_info; | ||
140 | int num_std; | ||
141 | u8 reg; | ||
142 | u32 val; | ||
143 | int err = 0; | ||
144 | int i; | ||
145 | |||
146 | num_std = ARRAY_SIZE(stdinfo); | ||
147 | |||
148 | for (i = 0; i < num_std; i++) { | ||
149 | if (stdinfo[i].stdid & std) | ||
150 | break; | ||
151 | } | ||
152 | |||
153 | if (i == num_std) { | ||
154 | v4l2_dbg(1, debug, sd, | ||
155 | "Invalid std or std is not supported: %llx\n", | ||
156 | (unsigned long long)std); | ||
157 | return -EINVAL; | ||
158 | } | ||
159 | |||
160 | std_info = &stdinfo[i]; | ||
161 | |||
162 | /* Set the standard */ | ||
163 | val = state->reg80 & ~SD_STD_MASK; | ||
164 | val |= std_info->standard_val3; | ||
165 | err = adv7393_write(sd, ADV7393_SD_MODE_REG1, val); | ||
166 | if (err < 0) | ||
167 | goto setstd_exit; | ||
168 | |||
169 | state->reg80 = val; | ||
170 | |||
171 | /* Configure the input mode register */ | ||
172 | val = state->reg01 & ~INPUT_MODE_MASK; | ||
173 | val |= SD_INPUT_MODE; | ||
174 | err = adv7393_write(sd, ADV7393_MODE_SELECT_REG, val); | ||
175 | if (err < 0) | ||
176 | goto setstd_exit; | ||
177 | |||
178 | state->reg01 = val; | ||
179 | |||
180 | /* Program the sub carrier frequency registers */ | ||
181 | val = std_info->fsc_val; | ||
182 | for (reg = ADV7393_FSC_REG0; reg <= ADV7393_FSC_REG3; reg++) { | ||
183 | err = adv7393_write(sd, reg, val); | ||
184 | if (err < 0) | ||
185 | goto setstd_exit; | ||
186 | val >>= 8; | ||
187 | } | ||
188 | |||
189 | val = state->reg82; | ||
190 | |||
191 | /* Pedestal settings */ | ||
192 | if (std & (V4L2_STD_NTSC | V4L2_STD_NTSC_443)) | ||
193 | val |= SD_PEDESTAL_EN; | ||
194 | else | ||
195 | val &= SD_PEDESTAL_DI; | ||
196 | |||
197 | err = adv7393_write(sd, ADV7393_SD_MODE_REG2, val); | ||
198 | if (err < 0) | ||
199 | goto setstd_exit; | ||
200 | |||
201 | state->reg82 = val; | ||
202 | |||
203 | setstd_exit: | ||
204 | if (err != 0) | ||
205 | v4l2_err(sd, "Error setting std, write failed\n"); | ||
206 | |||
207 | return err; | ||
208 | } | ||
209 | |||
210 | static int adv7393_setoutput(struct v4l2_subdev *sd, u32 output_type) | ||
211 | { | ||
212 | struct adv7393_state *state = to_state(sd); | ||
213 | u8 val; | ||
214 | int err = 0; | ||
215 | |||
216 | if (output_type > ADV7393_SVIDEO_ID) { | ||
217 | v4l2_dbg(1, debug, sd, | ||
218 | "Invalid output type or output type not supported:%d\n", | ||
219 | output_type); | ||
220 | return -EINVAL; | ||
221 | } | ||
222 | |||
223 | /* Enable Appropriate DAC */ | ||
224 | val = state->reg00 & 0x03; | ||
225 | |||
226 | if (output_type == ADV7393_COMPOSITE_ID) | ||
227 | val |= ADV7393_COMPOSITE_POWER_VALUE; | ||
228 | else if (output_type == ADV7393_COMPONENT_ID) | ||
229 | val |= ADV7393_COMPONENT_POWER_VALUE; | ||
230 | else | ||
231 | val |= ADV7393_SVIDEO_POWER_VALUE; | ||
232 | |||
233 | err = adv7393_write(sd, ADV7393_POWER_MODE_REG, val); | ||
234 | if (err < 0) | ||
235 | goto setoutput_exit; | ||
236 | |||
237 | state->reg00 = val; | ||
238 | |||
239 | /* Enable YUV output */ | ||
240 | val = state->reg02 | YUV_OUTPUT_SELECT; | ||
241 | err = adv7393_write(sd, ADV7393_MODE_REG0, val); | ||
242 | if (err < 0) | ||
243 | goto setoutput_exit; | ||
244 | |||
245 | state->reg02 = val; | ||
246 | |||
247 | /* configure SD DAC Output 1 bit */ | ||
248 | val = state->reg82; | ||
249 | if (output_type == ADV7393_COMPONENT_ID) | ||
250 | val &= SD_DAC_OUT1_DI; | ||
251 | else | ||
252 | val |= SD_DAC_OUT1_EN; | ||
253 | err = adv7393_write(sd, ADV7393_SD_MODE_REG2, val); | ||
254 | if (err < 0) | ||
255 | goto setoutput_exit; | ||
256 | |||
257 | state->reg82 = val; | ||
258 | |||
259 | /* configure ED/HD Color DAC Swap bit to zero */ | ||
260 | val = state->reg35 & HD_DAC_SWAP_DI; | ||
261 | err = adv7393_write(sd, ADV7393_HD_MODE_REG6, val); | ||
262 | if (err < 0) | ||
263 | goto setoutput_exit; | ||
264 | |||
265 | state->reg35 = val; | ||
266 | |||
267 | setoutput_exit: | ||
268 | if (err != 0) | ||
269 | v4l2_err(sd, "Error setting output, write failed\n"); | ||
270 | |||
271 | return err; | ||
272 | } | ||
273 | |||
274 | static int adv7393_log_status(struct v4l2_subdev *sd) | ||
275 | { | ||
276 | struct adv7393_state *state = to_state(sd); | ||
277 | |||
278 | v4l2_info(sd, "Standard: %llx\n", (unsigned long long)state->std); | ||
279 | v4l2_info(sd, "Output: %s\n", (state->output == 0) ? "Composite" : | ||
280 | ((state->output == 1) ? "Component" : "S-Video")); | ||
281 | return 0; | ||
282 | } | ||
283 | |||
284 | static int adv7393_s_ctrl(struct v4l2_ctrl *ctrl) | ||
285 | { | ||
286 | struct v4l2_subdev *sd = to_sd(ctrl); | ||
287 | |||
288 | switch (ctrl->id) { | ||
289 | case V4L2_CID_BRIGHTNESS: | ||
290 | return adv7393_write(sd, ADV7393_SD_BRIGHTNESS_WSS, | ||
291 | ctrl->val & SD_BRIGHTNESS_VALUE_MASK); | ||
292 | |||
293 | case V4L2_CID_HUE: | ||
294 | return adv7393_write(sd, ADV7393_SD_HUE_ADJUST, | ||
295 | ctrl->val - ADV7393_HUE_MIN); | ||
296 | |||
297 | case V4L2_CID_GAIN: | ||
298 | return adv7393_write(sd, ADV7393_DAC123_OUTPUT_LEVEL, | ||
299 | ctrl->val); | ||
300 | } | ||
301 | return -EINVAL; | ||
302 | } | ||
303 | |||
304 | static int adv7393_g_chip_ident(struct v4l2_subdev *sd, | ||
305 | struct v4l2_dbg_chip_ident *chip) | ||
306 | { | ||
307 | struct i2c_client *client = v4l2_get_subdevdata(sd); | ||
308 | |||
309 | return v4l2_chip_ident_i2c_client(client, chip, V4L2_IDENT_ADV7393, 0); | ||
310 | } | ||
311 | |||
312 | static const struct v4l2_ctrl_ops adv7393_ctrl_ops = { | ||
313 | .s_ctrl = adv7393_s_ctrl, | ||
314 | }; | ||
315 | |||
316 | static const struct v4l2_subdev_core_ops adv7393_core_ops = { | ||
317 | .log_status = adv7393_log_status, | ||
318 | .g_chip_ident = adv7393_g_chip_ident, | ||
319 | .g_ext_ctrls = v4l2_subdev_g_ext_ctrls, | ||
320 | .try_ext_ctrls = v4l2_subdev_try_ext_ctrls, | ||
321 | .s_ext_ctrls = v4l2_subdev_s_ext_ctrls, | ||
322 | .g_ctrl = v4l2_subdev_g_ctrl, | ||
323 | .s_ctrl = v4l2_subdev_s_ctrl, | ||
324 | .queryctrl = v4l2_subdev_queryctrl, | ||
325 | .querymenu = v4l2_subdev_querymenu, | ||
326 | }; | ||
327 | |||
328 | static int adv7393_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std) | ||
329 | { | ||
330 | struct adv7393_state *state = to_state(sd); | ||
331 | int err = 0; | ||
332 | |||
333 | if (state->std == std) | ||
334 | return 0; | ||
335 | |||
336 | err = adv7393_setstd(sd, std); | ||
337 | if (!err) | ||
338 | state->std = std; | ||
339 | |||
340 | return err; | ||
341 | } | ||
342 | |||
343 | static int adv7393_s_routing(struct v4l2_subdev *sd, | ||
344 | u32 input, u32 output, u32 config) | ||
345 | { | ||
346 | struct adv7393_state *state = to_state(sd); | ||
347 | int err = 0; | ||
348 | |||
349 | if (state->output == output) | ||
350 | return 0; | ||
351 | |||
352 | err = adv7393_setoutput(sd, output); | ||
353 | if (!err) | ||
354 | state->output = output; | ||
355 | |||
356 | return err; | ||
357 | } | ||
358 | |||
359 | static const struct v4l2_subdev_video_ops adv7393_video_ops = { | ||
360 | .s_std_output = adv7393_s_std_output, | ||
361 | .s_routing = adv7393_s_routing, | ||
362 | }; | ||
363 | |||
364 | static const struct v4l2_subdev_ops adv7393_ops = { | ||
365 | .core = &adv7393_core_ops, | ||
366 | .video = &adv7393_video_ops, | ||
367 | }; | ||
368 | |||
369 | static int adv7393_initialize(struct v4l2_subdev *sd) | ||
370 | { | ||
371 | struct adv7393_state *state = to_state(sd); | ||
372 | int err = 0; | ||
373 | int i; | ||
374 | |||
375 | for (i = 0; i < ARRAY_SIZE(adv7393_init_reg_val); i += 2) { | ||
376 | |||
377 | err = adv7393_write(sd, adv7393_init_reg_val[i], | ||
378 | adv7393_init_reg_val[i+1]); | ||
379 | if (err) { | ||
380 | v4l2_err(sd, "Error initializing\n"); | ||
381 | return err; | ||
382 | } | ||
383 | } | ||
384 | |||
385 | /* Configure for default video standard */ | ||
386 | err = adv7393_setoutput(sd, state->output); | ||
387 | if (err < 0) { | ||
388 | v4l2_err(sd, "Error setting output during init\n"); | ||
389 | return -EINVAL; | ||
390 | } | ||
391 | |||
392 | err = adv7393_setstd(sd, state->std); | ||
393 | if (err < 0) { | ||
394 | v4l2_err(sd, "Error setting std during init\n"); | ||
395 | return -EINVAL; | ||
396 | } | ||
397 | |||
398 | return err; | ||
399 | } | ||
400 | |||
401 | static int adv7393_probe(struct i2c_client *client, | ||
402 | const struct i2c_device_id *id) | ||
403 | { | ||
404 | struct adv7393_state *state; | ||
405 | int err; | ||
406 | |||
407 | if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) | ||
408 | return -ENODEV; | ||
409 | |||
410 | v4l_info(client, "chip found @ 0x%x (%s)\n", | ||
411 | client->addr << 1, client->adapter->name); | ||
412 | |||
413 | state = kzalloc(sizeof(struct adv7393_state), GFP_KERNEL); | ||
414 | if (state == NULL) | ||
415 | return -ENOMEM; | ||
416 | |||
417 | state->reg00 = ADV7393_POWER_MODE_REG_DEFAULT; | ||
418 | state->reg01 = 0x00; | ||
419 | state->reg02 = 0x20; | ||
420 | state->reg35 = ADV7393_HD_MODE_REG6_DEFAULT; | ||
421 | state->reg80 = ADV7393_SD_MODE_REG1_DEFAULT; | ||
422 | state->reg82 = ADV7393_SD_MODE_REG2_DEFAULT; | ||
423 | |||
424 | state->output = ADV7393_COMPOSITE_ID; | ||
425 | state->std = V4L2_STD_NTSC; | ||
426 | |||
427 | v4l2_i2c_subdev_init(&state->sd, client, &adv7393_ops); | ||
428 | |||
429 | v4l2_ctrl_handler_init(&state->hdl, 3); | ||
430 | v4l2_ctrl_new_std(&state->hdl, &adv7393_ctrl_ops, | ||
431 | V4L2_CID_BRIGHTNESS, ADV7393_BRIGHTNESS_MIN, | ||
432 | ADV7393_BRIGHTNESS_MAX, 1, | ||
433 | ADV7393_BRIGHTNESS_DEF); | ||
434 | v4l2_ctrl_new_std(&state->hdl, &adv7393_ctrl_ops, | ||
435 | V4L2_CID_HUE, ADV7393_HUE_MIN, | ||
436 | ADV7393_HUE_MAX, 1, | ||
437 | ADV7393_HUE_DEF); | ||
438 | v4l2_ctrl_new_std(&state->hdl, &adv7393_ctrl_ops, | ||
439 | V4L2_CID_GAIN, ADV7393_GAIN_MIN, | ||
440 | ADV7393_GAIN_MAX, 1, | ||
441 | ADV7393_GAIN_DEF); | ||
442 | state->sd.ctrl_handler = &state->hdl; | ||
443 | if (state->hdl.error) { | ||
444 | int err = state->hdl.error; | ||
445 | |||
446 | v4l2_ctrl_handler_free(&state->hdl); | ||
447 | kfree(state); | ||
448 | return err; | ||
449 | } | ||
450 | v4l2_ctrl_handler_setup(&state->hdl); | ||
451 | |||
452 | err = adv7393_initialize(&state->sd); | ||
453 | if (err) { | ||
454 | v4l2_ctrl_handler_free(&state->hdl); | ||
455 | kfree(state); | ||
456 | } | ||
457 | return err; | ||
458 | } | ||
459 | |||
460 | static int adv7393_remove(struct i2c_client *client) | ||
461 | { | ||
462 | struct v4l2_subdev *sd = i2c_get_clientdata(client); | ||
463 | struct adv7393_state *state = to_state(sd); | ||
464 | |||
465 | v4l2_device_unregister_subdev(sd); | ||
466 | v4l2_ctrl_handler_free(&state->hdl); | ||
467 | kfree(state); | ||
468 | |||
469 | return 0; | ||
470 | } | ||
471 | |||
472 | static const struct i2c_device_id adv7393_id[] = { | ||
473 | {"adv7393", 0}, | ||
474 | {}, | ||
475 | }; | ||
476 | MODULE_DEVICE_TABLE(i2c, adv7393_id); | ||
477 | |||
478 | static struct i2c_driver adv7393_driver = { | ||
479 | .driver = { | ||
480 | .owner = THIS_MODULE, | ||
481 | .name = "adv7393", | ||
482 | }, | ||
483 | .probe = adv7393_probe, | ||
484 | .remove = adv7393_remove, | ||
485 | .id_table = adv7393_id, | ||
486 | }; | ||
487 | module_i2c_driver(adv7393_driver); | ||