diff options
author | Sylwester Nawrocki <s.nawrocki@samsung.com> | 2013-04-10 05:23:05 -0400 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2013-04-14 14:50:31 -0400 |
commit | a6f5635e63ffa02c30a22ea4af21f3daa1e98cdf (patch) | |
tree | 48581b597f3ff45132d968db30d91cb0e1da5fa9 /drivers/media/platform | |
parent | 4c8f0629f53bb198ed00c2c54cf80cc2be95acab (diff) |
[media] exynos4-is: Improve the ISP chain parameter count calculation
Instead of incrementing p_region_num field each time we set a bit
in the parameter mask calculate the number of bits set only when
this information is needed.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/platform')
-rw-r--r-- | drivers/media/platform/exynos4-is/fimc-is-param.c | 86 | ||||
-rw-r--r-- | drivers/media/platform/exynos4-is/fimc-is-param.h | 4 | ||||
-rw-r--r-- | drivers/media/platform/exynos4-is/fimc-is-regs.c | 3 | ||||
-rw-r--r-- | drivers/media/platform/exynos4-is/fimc-is.c | 2 | ||||
-rw-r--r-- | drivers/media/platform/exynos4-is/fimc-is.h | 1 | ||||
-rw-r--r-- | drivers/media/platform/exynos4-is/fimc-isp.c | 7 |
6 files changed, 34 insertions, 69 deletions
diff --git a/drivers/media/platform/exynos4-is/fimc-is-param.c b/drivers/media/platform/exynos4-is/fimc-is-param.c index 37fd5fe68eef..58123e3e1b62 100644 --- a/drivers/media/platform/exynos4-is/fimc-is-param.c +++ b/drivers/media/platform/exynos4-is/fimc-is-param.c | |||
@@ -12,14 +12,15 @@ | |||
12 | */ | 12 | */ |
13 | #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__ | 13 | #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__ |
14 | 14 | ||
15 | #include <linux/bitops.h> | ||
15 | #include <linux/bug.h> | 16 | #include <linux/bug.h> |
16 | #include <linux/device.h> | 17 | #include <linux/device.h> |
17 | #include <linux/errno.h> | 18 | #include <linux/errno.h> |
18 | #include <linux/kernel.h> | 19 | #include <linux/kernel.h> |
19 | #include <linux/module.h> | 20 | #include <linux/module.h> |
20 | #include <linux/types.h> | ||
21 | #include <linux/platform_device.h> | 21 | #include <linux/platform_device.h> |
22 | #include <linux/slab.h> | 22 | #include <linux/slab.h> |
23 | #include <linux/types.h> | ||
23 | #include <linux/videodev2.h> | 24 | #include <linux/videodev2.h> |
24 | 25 | ||
25 | #include <media/v4l2-device.h> | 26 | #include <media/v4l2-device.h> |
@@ -160,6 +161,20 @@ int __fimc_is_hw_update_param(struct fimc_is *is, u32 offset) | |||
160 | return 0; | 161 | return 0; |
161 | } | 162 | } |
162 | 163 | ||
164 | unsigned int __get_pending_param_count(struct fimc_is *is) | ||
165 | { | ||
166 | struct is_config_param *config = &is->cfg_param[is->scenario_id]; | ||
167 | unsigned long flags; | ||
168 | unsigned int count; | ||
169 | |||
170 | spin_lock_irqsave(&is->slock, flags); | ||
171 | count = hweight32(config->p_region_index1); | ||
172 | count += hweight32(config->p_region_index2); | ||
173 | spin_unlock_irqrestore(&is->slock, flags); | ||
174 | |||
175 | return count; | ||
176 | } | ||
177 | |||
163 | int __is_hw_update_params(struct fimc_is *is) | 178 | int __is_hw_update_params(struct fimc_is *is) |
164 | { | 179 | { |
165 | unsigned long *p_index1, *p_index2; | 180 | unsigned long *p_index1, *p_index2; |
@@ -234,15 +249,10 @@ void __is_set_frame_size(struct fimc_is *is, struct v4l2_mbus_framefmt *mf) | |||
234 | 249 | ||
235 | /* Update field */ | 250 | /* Update field */ |
236 | fimc_is_set_param_bit(is, PARAM_ISP_OTF_INPUT); | 251 | fimc_is_set_param_bit(is, PARAM_ISP_OTF_INPUT); |
237 | fimc_is_inc_param_num(is); | ||
238 | fimc_is_set_param_bit(is, PARAM_ISP_OTF_OUTPUT); | 252 | fimc_is_set_param_bit(is, PARAM_ISP_OTF_OUTPUT); |
239 | fimc_is_inc_param_num(is); | ||
240 | fimc_is_set_param_bit(is, PARAM_DRC_OTF_INPUT); | 253 | fimc_is_set_param_bit(is, PARAM_DRC_OTF_INPUT); |
241 | fimc_is_inc_param_num(is); | ||
242 | fimc_is_set_param_bit(is, PARAM_DRC_OTF_OUTPUT); | 254 | fimc_is_set_param_bit(is, PARAM_DRC_OTF_OUTPUT); |
243 | fimc_is_inc_param_num(is); | ||
244 | fimc_is_set_param_bit(is, PARAM_FD_OTF_INPUT); | 255 | fimc_is_set_param_bit(is, PARAM_FD_OTF_INPUT); |
245 | fimc_is_inc_param_num(is); | ||
246 | } | 256 | } |
247 | 257 | ||
248 | int fimc_is_hw_get_sensor_max_framerate(struct fimc_is *is) | 258 | int fimc_is_hw_get_sensor_max_framerate(struct fimc_is *is) |
@@ -277,14 +287,11 @@ void __is_set_sensor(struct fimc_is *is, int fps) | |||
277 | isp->otf_input.frametime_max = (u32)1000000 / fps; | 287 | isp->otf_input.frametime_max = (u32)1000000 / fps; |
278 | } | 288 | } |
279 | 289 | ||
280 | if (!test_bit(PARAM_SENSOR_FRAME_RATE, p_index)) { | 290 | if (!test_bit(PARAM_SENSOR_FRAME_RATE, p_index)) |
281 | fimc_is_set_param_bit(is, PARAM_SENSOR_FRAME_RATE); | 291 | fimc_is_set_param_bit(is, PARAM_SENSOR_FRAME_RATE); |
282 | fimc_is_inc_param_num(is); | 292 | |
283 | } | 293 | if (!test_bit(PARAM_ISP_OTF_INPUT, p_index)) |
284 | if (!test_bit(PARAM_ISP_OTF_INPUT, p_index)) { | ||
285 | fimc_is_set_param_bit(is, PARAM_ISP_OTF_INPUT); | 294 | fimc_is_set_param_bit(is, PARAM_ISP_OTF_INPUT); |
286 | fimc_is_inc_param_num(is); | ||
287 | } | ||
288 | } | 295 | } |
289 | 296 | ||
290 | void __is_set_init_isp_aa(struct fimc_is *is) | 297 | void __is_set_init_isp_aa(struct fimc_is *is) |
@@ -306,7 +313,6 @@ void __is_set_init_isp_aa(struct fimc_is *is) | |||
306 | isp->aa.err = ISP_AF_ERROR_NONE; | 313 | isp->aa.err = ISP_AF_ERROR_NONE; |
307 | 314 | ||
308 | fimc_is_set_param_bit(is, PARAM_ISP_AA); | 315 | fimc_is_set_param_bit(is, PARAM_ISP_AA); |
309 | fimc_is_inc_param_num(is); | ||
310 | } | 316 | } |
311 | 317 | ||
312 | void __is_set_isp_flash(struct fimc_is *is, u32 cmd, u32 redeye) | 318 | void __is_set_isp_flash(struct fimc_is *is, u32 cmd, u32 redeye) |
@@ -319,10 +325,8 @@ void __is_set_isp_flash(struct fimc_is *is, u32 cmd, u32 redeye) | |||
319 | isp->flash.redeye = redeye; | 325 | isp->flash.redeye = redeye; |
320 | isp->flash.err = ISP_FLASH_ERROR_NONE; | 326 | isp->flash.err = ISP_FLASH_ERROR_NONE; |
321 | 327 | ||
322 | if (!test_bit(PARAM_ISP_FLASH, &cfg->p_region_index1)) { | 328 | if (!test_bit(PARAM_ISP_FLASH, &cfg->p_region_index1)) |
323 | fimc_is_set_param_bit(is, PARAM_ISP_FLASH); | 329 | fimc_is_set_param_bit(is, PARAM_ISP_FLASH); |
324 | fimc_is_inc_param_num(is); | ||
325 | } | ||
326 | } | 330 | } |
327 | 331 | ||
328 | void __is_set_isp_awb(struct fimc_is *is, u32 cmd, u32 val) | 332 | void __is_set_isp_awb(struct fimc_is *is, u32 cmd, u32 val) |
@@ -338,10 +342,8 @@ void __is_set_isp_awb(struct fimc_is *is, u32 cmd, u32 val) | |||
338 | isp->awb.illumination = val; | 342 | isp->awb.illumination = val; |
339 | isp->awb.err = ISP_AWB_ERROR_NONE; | 343 | isp->awb.err = ISP_AWB_ERROR_NONE; |
340 | 344 | ||
341 | if (!test_bit(PARAM_ISP_AWB, p_index)) { | 345 | if (!test_bit(PARAM_ISP_AWB, p_index)) |
342 | fimc_is_set_param_bit(is, PARAM_ISP_AWB); | 346 | fimc_is_set_param_bit(is, PARAM_ISP_AWB); |
343 | fimc_is_inc_param_num(is); | ||
344 | } | ||
345 | } | 347 | } |
346 | 348 | ||
347 | void __is_set_isp_effect(struct fimc_is *is, u32 cmd) | 349 | void __is_set_isp_effect(struct fimc_is *is, u32 cmd) |
@@ -356,10 +358,8 @@ void __is_set_isp_effect(struct fimc_is *is, u32 cmd) | |||
356 | isp->effect.cmd = cmd; | 358 | isp->effect.cmd = cmd; |
357 | isp->effect.err = ISP_IMAGE_EFFECT_ERROR_NONE; | 359 | isp->effect.err = ISP_IMAGE_EFFECT_ERROR_NONE; |
358 | 360 | ||
359 | if (!test_bit(PARAM_ISP_IMAGE_EFFECT, p_index)) { | 361 | if (!test_bit(PARAM_ISP_IMAGE_EFFECT, p_index)) |
360 | fimc_is_set_param_bit(is, PARAM_ISP_IMAGE_EFFECT); | 362 | fimc_is_set_param_bit(is, PARAM_ISP_IMAGE_EFFECT); |
361 | fimc_is_inc_param_num(is); | ||
362 | } | ||
363 | } | 363 | } |
364 | 364 | ||
365 | void __is_set_isp_iso(struct fimc_is *is, u32 cmd, u32 val) | 365 | void __is_set_isp_iso(struct fimc_is *is, u32 cmd, u32 val) |
@@ -375,10 +375,8 @@ void __is_set_isp_iso(struct fimc_is *is, u32 cmd, u32 val) | |||
375 | isp->iso.value = val; | 375 | isp->iso.value = val; |
376 | isp->iso.err = ISP_ISO_ERROR_NONE; | 376 | isp->iso.err = ISP_ISO_ERROR_NONE; |
377 | 377 | ||
378 | if (!test_bit(PARAM_ISP_ISO, p_index)) { | 378 | if (!test_bit(PARAM_ISP_ISO, p_index)) |
379 | fimc_is_set_param_bit(is, PARAM_ISP_ISO); | 379 | fimc_is_set_param_bit(is, PARAM_ISP_ISO); |
380 | fimc_is_inc_param_num(is); | ||
381 | } | ||
382 | } | 380 | } |
383 | 381 | ||
384 | void __is_set_isp_adjust(struct fimc_is *is, u32 cmd, u32 val) | 382 | void __is_set_isp_adjust(struct fimc_is *is, u32 cmd, u32 val) |
@@ -423,7 +421,6 @@ void __is_set_isp_adjust(struct fimc_is *is, u32 cmd, u32 val) | |||
423 | isp->adjust.cmd = cmd; | 421 | isp->adjust.cmd = cmd; |
424 | isp->adjust.err = ISP_ADJUST_ERROR_NONE; | 422 | isp->adjust.err = ISP_ADJUST_ERROR_NONE; |
425 | fimc_is_set_param_bit(is, PARAM_ISP_ADJUST); | 423 | fimc_is_set_param_bit(is, PARAM_ISP_ADJUST); |
426 | fimc_is_inc_param_num(is); | ||
427 | } else { | 424 | } else { |
428 | isp->adjust.cmd |= cmd; | 425 | isp->adjust.cmd |= cmd; |
429 | } | 426 | } |
@@ -461,7 +458,6 @@ void __is_set_isp_metering(struct fimc_is *is, u32 id, u32 val) | |||
461 | if (!test_bit(PARAM_ISP_METERING, p_index)) { | 458 | if (!test_bit(PARAM_ISP_METERING, p_index)) { |
462 | isp->metering.err = ISP_METERING_ERROR_NONE; | 459 | isp->metering.err = ISP_METERING_ERROR_NONE; |
463 | fimc_is_set_param_bit(is, PARAM_ISP_METERING); | 460 | fimc_is_set_param_bit(is, PARAM_ISP_METERING); |
464 | fimc_is_inc_param_num(is); | ||
465 | } | 461 | } |
466 | } | 462 | } |
467 | 463 | ||
@@ -478,10 +474,8 @@ void __is_set_isp_afc(struct fimc_is *is, u32 cmd, u32 val) | |||
478 | isp->afc.manual = val; | 474 | isp->afc.manual = val; |
479 | isp->afc.err = ISP_AFC_ERROR_NONE; | 475 | isp->afc.err = ISP_AFC_ERROR_NONE; |
480 | 476 | ||
481 | if (!test_bit(PARAM_ISP_AFC, p_index)) { | 477 | if (!test_bit(PARAM_ISP_AFC, p_index)) |
482 | fimc_is_set_param_bit(is, PARAM_ISP_AFC); | 478 | fimc_is_set_param_bit(is, PARAM_ISP_AFC); |
483 | fimc_is_inc_param_num(is); | ||
484 | } | ||
485 | } | 479 | } |
486 | 480 | ||
487 | void __is_set_drc_control(struct fimc_is *is, u32 val) | 481 | void __is_set_drc_control(struct fimc_is *is, u32 val) |
@@ -495,10 +489,8 @@ void __is_set_drc_control(struct fimc_is *is, u32 val) | |||
495 | 489 | ||
496 | drc->control.bypass = val; | 490 | drc->control.bypass = val; |
497 | 491 | ||
498 | if (!test_bit(PARAM_DRC_CONTROL, p_index)) { | 492 | if (!test_bit(PARAM_DRC_CONTROL, p_index)) |
499 | fimc_is_set_param_bit(is, PARAM_DRC_CONTROL); | 493 | fimc_is_set_param_bit(is, PARAM_DRC_CONTROL); |
500 | fimc_is_inc_param_num(is); | ||
501 | } | ||
502 | } | 494 | } |
503 | 495 | ||
504 | void __is_set_fd_control(struct fimc_is *is, u32 val) | 496 | void __is_set_fd_control(struct fimc_is *is, u32 val) |
@@ -512,10 +504,8 @@ void __is_set_fd_control(struct fimc_is *is, u32 val) | |||
512 | 504 | ||
513 | fd->control.cmd = val; | 505 | fd->control.cmd = val; |
514 | 506 | ||
515 | if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) { | 507 | if (!test_bit((PARAM_FD_CONFIG - 32), p_index)) |
516 | fimc_is_set_param_bit(is, PARAM_FD_CONTROL); | 508 | fimc_is_set_param_bit(is, PARAM_FD_CONTROL); |
517 | fimc_is_inc_param_num(is); | ||
518 | } | ||
519 | } | 509 | } |
520 | 510 | ||
521 | void __is_set_fd_config_maxface(struct fimc_is *is, u32 val) | 511 | void __is_set_fd_config_maxface(struct fimc_is *is, u32 val) |
@@ -533,7 +523,6 @@ void __is_set_fd_config_maxface(struct fimc_is *is, u32 val) | |||
533 | fd->config.cmd = FD_CONFIG_COMMAND_MAXIMUM_NUMBER; | 523 | fd->config.cmd = FD_CONFIG_COMMAND_MAXIMUM_NUMBER; |
534 | fd->config.err = ERROR_FD_NONE; | 524 | fd->config.err = ERROR_FD_NONE; |
535 | fimc_is_set_param_bit(is, PARAM_FD_CONFIG); | 525 | fimc_is_set_param_bit(is, PARAM_FD_CONFIG); |
536 | fimc_is_inc_param_num(is); | ||
537 | } else { | 526 | } else { |
538 | fd->config.cmd |= FD_CONFIG_COMMAND_MAXIMUM_NUMBER; | 527 | fd->config.cmd |= FD_CONFIG_COMMAND_MAXIMUM_NUMBER; |
539 | } | 528 | } |
@@ -554,7 +543,6 @@ void __is_set_fd_config_rollangle(struct fimc_is *is, u32 val) | |||
554 | fd->config.cmd = FD_CONFIG_COMMAND_ROLL_ANGLE; | 543 | fd->config.cmd = FD_CONFIG_COMMAND_ROLL_ANGLE; |
555 | fd->config.err = ERROR_FD_NONE; | 544 | fd->config.err = ERROR_FD_NONE; |
556 | fimc_is_set_param_bit(is, PARAM_FD_CONFIG); | 545 | fimc_is_set_param_bit(is, PARAM_FD_CONFIG); |
557 | fimc_is_inc_param_num(is); | ||
558 | } else { | 546 | } else { |
559 | fd->config.cmd |= FD_CONFIG_COMMAND_ROLL_ANGLE; | 547 | fd->config.cmd |= FD_CONFIG_COMMAND_ROLL_ANGLE; |
560 | } | 548 | } |
@@ -575,7 +563,6 @@ void __is_set_fd_config_yawangle(struct fimc_is *is, u32 val) | |||
575 | fd->config.cmd = FD_CONFIG_COMMAND_YAW_ANGLE; | 563 | fd->config.cmd = FD_CONFIG_COMMAND_YAW_ANGLE; |
576 | fd->config.err = ERROR_FD_NONE; | 564 | fd->config.err = ERROR_FD_NONE; |
577 | fimc_is_set_param_bit(is, PARAM_FD_CONFIG); | 565 | fimc_is_set_param_bit(is, PARAM_FD_CONFIG); |
578 | fimc_is_inc_param_num(is); | ||
579 | } else { | 566 | } else { |
580 | fd->config.cmd |= FD_CONFIG_COMMAND_YAW_ANGLE; | 567 | fd->config.cmd |= FD_CONFIG_COMMAND_YAW_ANGLE; |
581 | } | 568 | } |
@@ -596,7 +583,6 @@ void __is_set_fd_config_smilemode(struct fimc_is *is, u32 val) | |||
596 | fd->config.cmd = FD_CONFIG_COMMAND_SMILE_MODE; | 583 | fd->config.cmd = FD_CONFIG_COMMAND_SMILE_MODE; |
597 | fd->config.err = ERROR_FD_NONE; | 584 | fd->config.err = ERROR_FD_NONE; |
598 | fimc_is_set_param_bit(is, PARAM_FD_CONFIG); | 585 | fimc_is_set_param_bit(is, PARAM_FD_CONFIG); |
599 | fimc_is_inc_param_num(is); | ||
600 | } else { | 586 | } else { |
601 | fd->config.cmd |= FD_CONFIG_COMMAND_SMILE_MODE; | 587 | fd->config.cmd |= FD_CONFIG_COMMAND_SMILE_MODE; |
602 | } | 588 | } |
@@ -617,7 +603,6 @@ void __is_set_fd_config_blinkmode(struct fimc_is *is, u32 val) | |||
617 | fd->config.cmd = FD_CONFIG_COMMAND_BLINK_MODE; | 603 | fd->config.cmd = FD_CONFIG_COMMAND_BLINK_MODE; |
618 | fd->config.err = ERROR_FD_NONE; | 604 | fd->config.err = ERROR_FD_NONE; |
619 | fimc_is_set_param_bit(is, PARAM_FD_CONFIG); | 605 | fimc_is_set_param_bit(is, PARAM_FD_CONFIG); |
620 | fimc_is_inc_param_num(is); | ||
621 | } else { | 606 | } else { |
622 | fd->config.cmd |= FD_CONFIG_COMMAND_BLINK_MODE; | 607 | fd->config.cmd |= FD_CONFIG_COMMAND_BLINK_MODE; |
623 | } | 608 | } |
@@ -638,7 +623,6 @@ void __is_set_fd_config_eyedetect(struct fimc_is *is, u32 val) | |||
638 | fd->config.cmd = FD_CONFIG_COMMAND_EYES_DETECT; | 623 | fd->config.cmd = FD_CONFIG_COMMAND_EYES_DETECT; |
639 | fd->config.err = ERROR_FD_NONE; | 624 | fd->config.err = ERROR_FD_NONE; |
640 | fimc_is_set_param_bit(is, PARAM_FD_CONFIG); | 625 | fimc_is_set_param_bit(is, PARAM_FD_CONFIG); |
641 | fimc_is_inc_param_num(is); | ||
642 | } else { | 626 | } else { |
643 | fd->config.cmd |= FD_CONFIG_COMMAND_EYES_DETECT; | 627 | fd->config.cmd |= FD_CONFIG_COMMAND_EYES_DETECT; |
644 | } | 628 | } |
@@ -659,7 +643,6 @@ void __is_set_fd_config_mouthdetect(struct fimc_is *is, u32 val) | |||
659 | fd->config.cmd = FD_CONFIG_COMMAND_MOUTH_DETECT; | 643 | fd->config.cmd = FD_CONFIG_COMMAND_MOUTH_DETECT; |
660 | fd->config.err = ERROR_FD_NONE; | 644 | fd->config.err = ERROR_FD_NONE; |
661 | fimc_is_set_param_bit(is, PARAM_FD_CONFIG); | 645 | fimc_is_set_param_bit(is, PARAM_FD_CONFIG); |
662 | fimc_is_inc_param_num(is); | ||
663 | } else { | 646 | } else { |
664 | fd->config.cmd |= FD_CONFIG_COMMAND_MOUTH_DETECT; | 647 | fd->config.cmd |= FD_CONFIG_COMMAND_MOUTH_DETECT; |
665 | } | 648 | } |
@@ -680,7 +663,6 @@ void __is_set_fd_config_orientation(struct fimc_is *is, u32 val) | |||
680 | fd->config.cmd = FD_CONFIG_COMMAND_ORIENTATION; | 663 | fd->config.cmd = FD_CONFIG_COMMAND_ORIENTATION; |
681 | fd->config.err = ERROR_FD_NONE; | 664 | fd->config.err = ERROR_FD_NONE; |
682 | fimc_is_set_param_bit(is, PARAM_FD_CONFIG); | 665 | fimc_is_set_param_bit(is, PARAM_FD_CONFIG); |
683 | fimc_is_inc_param_num(is); | ||
684 | } else { | 666 | } else { |
685 | fd->config.cmd |= FD_CONFIG_COMMAND_ORIENTATION; | 667 | fd->config.cmd |= FD_CONFIG_COMMAND_ORIENTATION; |
686 | } | 668 | } |
@@ -701,7 +683,6 @@ void __is_set_fd_config_orientation_val(struct fimc_is *is, u32 val) | |||
701 | fd->config.cmd = FD_CONFIG_COMMAND_ORIENTATION_VALUE; | 683 | fd->config.cmd = FD_CONFIG_COMMAND_ORIENTATION_VALUE; |
702 | fd->config.err = ERROR_FD_NONE; | 684 | fd->config.err = ERROR_FD_NONE; |
703 | fimc_is_set_param_bit(is, PARAM_FD_CONFIG); | 685 | fimc_is_set_param_bit(is, PARAM_FD_CONFIG); |
704 | fimc_is_inc_param_num(is); | ||
705 | } else { | 686 | } else { |
706 | fd->config.cmd |= FD_CONFIG_COMMAND_ORIENTATION_VALUE; | 687 | fd->config.cmd |= FD_CONFIG_COMMAND_ORIENTATION_VALUE; |
707 | } | 688 | } |
@@ -729,21 +710,18 @@ void fimc_is_set_initial_params(struct fimc_is *is) | |||
729 | /* Global */ | 710 | /* Global */ |
730 | global->shotmode.cmd = 1; | 711 | global->shotmode.cmd = 1; |
731 | fimc_is_set_param_bit(is, PARAM_GLOBAL_SHOTMODE); | 712 | fimc_is_set_param_bit(is, PARAM_GLOBAL_SHOTMODE); |
732 | fimc_is_inc_param_num(is); | ||
733 | 713 | ||
734 | /* ISP */ | 714 | /* ISP */ |
735 | isp->control.cmd = CONTROL_COMMAND_START; | 715 | isp->control.cmd = CONTROL_COMMAND_START; |
736 | isp->control.bypass = CONTROL_BYPASS_DISABLE; | 716 | isp->control.bypass = CONTROL_BYPASS_DISABLE; |
737 | isp->control.err = CONTROL_ERROR_NONE; | 717 | isp->control.err = CONTROL_ERROR_NONE; |
738 | fimc_is_set_param_bit(is, PARAM_ISP_CONTROL); | 718 | fimc_is_set_param_bit(is, PARAM_ISP_CONTROL); |
739 | fimc_is_inc_param_num(is); | ||
740 | 719 | ||
741 | isp->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE; | 720 | isp->otf_input.cmd = OTF_INPUT_COMMAND_ENABLE; |
742 | if (!test_bit(PARAM_ISP_OTF_INPUT, p_index1)) { | 721 | if (!test_bit(PARAM_ISP_OTF_INPUT, p_index1)) { |
743 | isp->otf_input.width = DEFAULT_PREVIEW_STILL_WIDTH; | 722 | isp->otf_input.width = DEFAULT_PREVIEW_STILL_WIDTH; |
744 | isp->otf_input.height = DEFAULT_PREVIEW_STILL_HEIGHT; | 723 | isp->otf_input.height = DEFAULT_PREVIEW_STILL_HEIGHT; |
745 | fimc_is_set_param_bit(is, PARAM_ISP_OTF_INPUT); | 724 | fimc_is_set_param_bit(is, PARAM_ISP_OTF_INPUT); |
746 | fimc_is_inc_param_num(is); | ||
747 | } | 725 | } |
748 | if (is->sensor->test_pattern) | 726 | if (is->sensor->test_pattern) |
749 | isp->otf_input.format = OTF_INPUT_FORMAT_STRGEN_COLORBAR_BAYER; | 727 | isp->otf_input.format = OTF_INPUT_FORMAT_STRGEN_COLORBAR_BAYER; |
@@ -766,7 +744,6 @@ void fimc_is_set_initial_params(struct fimc_is *is) | |||
766 | isp->dma1_input.width = 0; | 744 | isp->dma1_input.width = 0; |
767 | isp->dma1_input.err = DMA_INPUT_ERROR_NONE; | 745 | isp->dma1_input.err = DMA_INPUT_ERROR_NONE; |
768 | fimc_is_set_param_bit(is, PARAM_ISP_DMA1_INPUT); | 746 | fimc_is_set_param_bit(is, PARAM_ISP_DMA1_INPUT); |
769 | fimc_is_inc_param_num(is); | ||
770 | 747 | ||
771 | isp->dma2_input.cmd = DMA_INPUT_COMMAND_DISABLE; | 748 | isp->dma2_input.cmd = DMA_INPUT_COMMAND_DISABLE; |
772 | isp->dma2_input.width = 0; | 749 | isp->dma2_input.width = 0; |
@@ -779,12 +756,10 @@ void fimc_is_set_initial_params(struct fimc_is *is) | |||
779 | isp->dma2_input.width = 0; | 756 | isp->dma2_input.width = 0; |
780 | isp->dma2_input.err = DMA_INPUT_ERROR_NONE; | 757 | isp->dma2_input.err = DMA_INPUT_ERROR_NONE; |
781 | fimc_is_set_param_bit(is, PARAM_ISP_DMA2_INPUT); | 758 | fimc_is_set_param_bit(is, PARAM_ISP_DMA2_INPUT); |
782 | fimc_is_inc_param_num(is); | ||
783 | 759 | ||
784 | isp->aa.cmd = ISP_AA_COMMAND_START; | 760 | isp->aa.cmd = ISP_AA_COMMAND_START; |
785 | isp->aa.target = ISP_AA_TARGET_AE | ISP_AA_TARGET_AWB; | 761 | isp->aa.target = ISP_AA_TARGET_AE | ISP_AA_TARGET_AWB; |
786 | fimc_is_set_param_bit(is, PARAM_ISP_AA); | 762 | fimc_is_set_param_bit(is, PARAM_ISP_AA); |
787 | fimc_is_inc_param_num(is); | ||
788 | 763 | ||
789 | if (!test_bit(PARAM_ISP_FLASH, p_index1)) | 764 | if (!test_bit(PARAM_ISP_FLASH, p_index1)) |
790 | __is_set_isp_flash(is, ISP_FLASH_COMMAND_DISABLE, | 765 | __is_set_isp_flash(is, ISP_FLASH_COMMAND_DISABLE, |
@@ -826,7 +801,6 @@ void fimc_is_set_initial_params(struct fimc_is *is) | |||
826 | isp->otf_output.width = DEFAULT_PREVIEW_STILL_WIDTH; | 801 | isp->otf_output.width = DEFAULT_PREVIEW_STILL_WIDTH; |
827 | isp->otf_output.height = DEFAULT_PREVIEW_STILL_HEIGHT; | 802 | isp->otf_output.height = DEFAULT_PREVIEW_STILL_HEIGHT; |
828 | fimc_is_set_param_bit(is, PARAM_ISP_OTF_OUTPUT); | 803 | fimc_is_set_param_bit(is, PARAM_ISP_OTF_OUTPUT); |
829 | fimc_is_inc_param_num(is); | ||
830 | } | 804 | } |
831 | isp->otf_output.format = OTF_OUTPUT_FORMAT_YUV444; | 805 | isp->otf_output.format = OTF_OUTPUT_FORMAT_YUV444; |
832 | isp->otf_output.bitwidth = 12; | 806 | isp->otf_output.bitwidth = 12; |
@@ -847,7 +821,6 @@ void fimc_is_set_initial_params(struct fimc_is *is) | |||
847 | isp->dma1_output.dma_out_mask = 0; | 821 | isp->dma1_output.dma_out_mask = 0; |
848 | isp->dma1_output.err = DMA_OUTPUT_ERROR_NONE; | 822 | isp->dma1_output.err = DMA_OUTPUT_ERROR_NONE; |
849 | fimc_is_set_param_bit(is, PARAM_ISP_DMA1_OUTPUT); | 823 | fimc_is_set_param_bit(is, PARAM_ISP_DMA1_OUTPUT); |
850 | fimc_is_inc_param_num(is); | ||
851 | } | 824 | } |
852 | 825 | ||
853 | if (!test_bit(PARAM_ISP_DMA2_OUTPUT, p_index1)) { | 826 | if (!test_bit(PARAM_ISP_DMA2_OUTPUT, p_index1)) { |
@@ -864,7 +837,6 @@ void fimc_is_set_initial_params(struct fimc_is *is) | |||
864 | isp->dma2_output.dma_out_mask = 0; | 837 | isp->dma2_output.dma_out_mask = 0; |
865 | isp->dma2_output.err = DMA_OUTPUT_ERROR_NONE; | 838 | isp->dma2_output.err = DMA_OUTPUT_ERROR_NONE; |
866 | fimc_is_set_param_bit(is, PARAM_ISP_DMA2_OUTPUT); | 839 | fimc_is_set_param_bit(is, PARAM_ISP_DMA2_OUTPUT); |
867 | fimc_is_inc_param_num(is); | ||
868 | } | 840 | } |
869 | 841 | ||
870 | /* Sensor */ | 842 | /* Sensor */ |
@@ -882,7 +854,6 @@ void fimc_is_set_initial_params(struct fimc_is *is) | |||
882 | drc->otf_input.width = DEFAULT_PREVIEW_STILL_WIDTH; | 854 | drc->otf_input.width = DEFAULT_PREVIEW_STILL_WIDTH; |
883 | drc->otf_input.height = DEFAULT_PREVIEW_STILL_HEIGHT; | 855 | drc->otf_input.height = DEFAULT_PREVIEW_STILL_HEIGHT; |
884 | fimc_is_set_param_bit(is, PARAM_DRC_OTF_INPUT); | 856 | fimc_is_set_param_bit(is, PARAM_DRC_OTF_INPUT); |
885 | fimc_is_inc_param_num(is); | ||
886 | } | 857 | } |
887 | drc->otf_input.format = OTF_INPUT_FORMAT_YUV444; | 858 | drc->otf_input.format = OTF_INPUT_FORMAT_YUV444; |
888 | drc->otf_input.bitwidth = 12; | 859 | drc->otf_input.bitwidth = 12; |
@@ -900,14 +871,12 @@ void fimc_is_set_initial_params(struct fimc_is *is) | |||
900 | drc->dma_input.width = 0; | 871 | drc->dma_input.width = 0; |
901 | drc->dma_input.err = DMA_INPUT_ERROR_NONE; | 872 | drc->dma_input.err = DMA_INPUT_ERROR_NONE; |
902 | fimc_is_set_param_bit(is, PARAM_DRC_DMA_INPUT); | 873 | fimc_is_set_param_bit(is, PARAM_DRC_DMA_INPUT); |
903 | fimc_is_inc_param_num(is); | ||
904 | 874 | ||
905 | drc->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE; | 875 | drc->otf_output.cmd = OTF_OUTPUT_COMMAND_ENABLE; |
906 | if (!test_bit(PARAM_DRC_OTF_OUTPUT, p_index1)) { | 876 | if (!test_bit(PARAM_DRC_OTF_OUTPUT, p_index1)) { |
907 | drc->otf_output.width = DEFAULT_PREVIEW_STILL_WIDTH; | 877 | drc->otf_output.width = DEFAULT_PREVIEW_STILL_WIDTH; |
908 | drc->otf_output.height = DEFAULT_PREVIEW_STILL_HEIGHT; | 878 | drc->otf_output.height = DEFAULT_PREVIEW_STILL_HEIGHT; |
909 | fimc_is_set_param_bit(is, PARAM_DRC_OTF_OUTPUT); | 879 | fimc_is_set_param_bit(is, PARAM_DRC_OTF_OUTPUT); |
910 | fimc_is_inc_param_num(is); | ||
911 | } | 880 | } |
912 | drc->otf_output.format = OTF_OUTPUT_FORMAT_YUV444; | 881 | drc->otf_output.format = OTF_OUTPUT_FORMAT_YUV444; |
913 | drc->otf_output.bitwidth = 8; | 882 | drc->otf_output.bitwidth = 8; |
@@ -923,8 +892,8 @@ void fimc_is_set_initial_params(struct fimc_is *is) | |||
923 | fd->otf_input.width = DEFAULT_PREVIEW_STILL_WIDTH; | 892 | fd->otf_input.width = DEFAULT_PREVIEW_STILL_WIDTH; |
924 | fd->otf_input.height = DEFAULT_PREVIEW_STILL_HEIGHT; | 893 | fd->otf_input.height = DEFAULT_PREVIEW_STILL_HEIGHT; |
925 | fimc_is_set_param_bit(is, PARAM_FD_OTF_INPUT); | 894 | fimc_is_set_param_bit(is, PARAM_FD_OTF_INPUT); |
926 | fimc_is_inc_param_num(is); | ||
927 | } | 895 | } |
896 | |||
928 | fd->otf_input.format = OTF_INPUT_FORMAT_YUV444; | 897 | fd->otf_input.format = OTF_INPUT_FORMAT_YUV444; |
929 | fd->otf_input.bitwidth = 8; | 898 | fd->otf_input.bitwidth = 8; |
930 | fd->otf_input.order = 0; | 899 | fd->otf_input.order = 0; |
@@ -941,7 +910,6 @@ void fimc_is_set_initial_params(struct fimc_is *is) | |||
941 | fd->dma_input.width = 0; | 910 | fd->dma_input.width = 0; |
942 | fd->dma_input.err = DMA_INPUT_ERROR_NONE; | 911 | fd->dma_input.err = DMA_INPUT_ERROR_NONE; |
943 | fimc_is_set_param_bit(is, PARAM_FD_DMA_INPUT); | 912 | fimc_is_set_param_bit(is, PARAM_FD_DMA_INPUT); |
944 | fimc_is_inc_param_num(is); | ||
945 | 913 | ||
946 | __is_set_fd_config_maxface(is, 5); | 914 | __is_set_fd_config_maxface(is, 5); |
947 | __is_set_fd_config_rollangle(is, FD_CONFIG_ROLL_ANGLE_FULL); | 915 | __is_set_fd_config_rollangle(is, FD_CONFIG_ROLL_ANGLE_FULL); |
diff --git a/drivers/media/platform/exynos4-is/fimc-is-param.h b/drivers/media/platform/exynos4-is/fimc-is-param.h index 71464a58b56b..f9358c27ae2d 100644 --- a/drivers/media/platform/exynos4-is/fimc-is-param.h +++ b/drivers/media/platform/exynos4-is/fimc-is-param.h | |||
@@ -985,13 +985,11 @@ struct sensor_open_extended { | |||
985 | u32 i2c_sclk; | 985 | u32 i2c_sclk; |
986 | }; | 986 | }; |
987 | 987 | ||
988 | #define fimc_is_inc_param_num(is) \ | ||
989 | atomic_inc(&(is)->cfg_param[(is)->scenario_id].p_region_num) | ||
990 | |||
991 | struct fimc_is; | 988 | struct fimc_is; |
992 | 989 | ||
993 | int fimc_is_hw_get_sensor_max_framerate(struct fimc_is *is); | 990 | int fimc_is_hw_get_sensor_max_framerate(struct fimc_is *is); |
994 | void fimc_is_set_initial_params(struct fimc_is *is); | 991 | void fimc_is_set_initial_params(struct fimc_is *is); |
992 | unsigned int __get_pending_param_count(struct fimc_is *is); | ||
995 | 993 | ||
996 | int __is_hw_update_params(struct fimc_is *is); | 994 | int __is_hw_update_params(struct fimc_is *is); |
997 | void __is_get_frame_size(struct fimc_is *is, struct v4l2_mbus_framefmt *mf); | 995 | void __is_get_frame_size(struct fimc_is *is, struct v4l2_mbus_framefmt *mf); |
diff --git a/drivers/media/platform/exynos4-is/fimc-is-regs.c b/drivers/media/platform/exynos4-is/fimc-is-regs.c index efb9da06052c..f59a289c530d 100644 --- a/drivers/media/platform/exynos4-is/fimc-is-regs.c +++ b/drivers/media/platform/exynos4-is/fimc-is-regs.c | |||
@@ -80,6 +80,7 @@ int fimc_is_hw_wait_intmsr0_intmsd0(struct fimc_is *is) | |||
80 | int fimc_is_hw_set_param(struct fimc_is *is) | 80 | int fimc_is_hw_set_param(struct fimc_is *is) |
81 | { | 81 | { |
82 | struct is_config_param *cfg = &is->cfg_param[is->scenario_id]; | 82 | struct is_config_param *cfg = &is->cfg_param[is->scenario_id]; |
83 | unsigned int param_count = __get_pending_param_count(is); | ||
83 | 84 | ||
84 | fimc_is_hw_wait_intmsr0_intmsd0(is); | 85 | fimc_is_hw_wait_intmsr0_intmsd0(is); |
85 | 86 | ||
@@ -87,7 +88,7 @@ int fimc_is_hw_set_param(struct fimc_is *is) | |||
87 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); | 88 | mcuctl_write(is->sensor_index, is, MCUCTL_REG_ISSR(1)); |
88 | mcuctl_write(is->scenario_id, is, MCUCTL_REG_ISSR(2)); | 89 | mcuctl_write(is->scenario_id, is, MCUCTL_REG_ISSR(2)); |
89 | 90 | ||
90 | mcuctl_write(atomic_read(&cfg->p_region_num), is, MCUCTL_REG_ISSR(3)); | 91 | mcuctl_write(param_count, is, MCUCTL_REG_ISSR(3)); |
91 | mcuctl_write(cfg->p_region_index1, is, MCUCTL_REG_ISSR(4)); | 92 | mcuctl_write(cfg->p_region_index1, is, MCUCTL_REG_ISSR(4)); |
92 | mcuctl_write(cfg->p_region_index2, is, MCUCTL_REG_ISSR(5)); | 93 | mcuctl_write(cfg->p_region_index2, is, MCUCTL_REG_ISSR(5)); |
93 | 94 | ||
diff --git a/drivers/media/platform/exynos4-is/fimc-is.c b/drivers/media/platform/exynos4-is/fimc-is.c index c5e4c5380f24..10ec173d1254 100644 --- a/drivers/media/platform/exynos4-is/fimc-is.c +++ b/drivers/media/platform/exynos4-is/fimc-is.c | |||
@@ -532,7 +532,6 @@ static void fimc_is_general_irq_handler(struct fimc_is *is) | |||
532 | case HIC_SET_PARAMETER: | 532 | case HIC_SET_PARAMETER: |
533 | is->cfg_param[is->scenario_id].p_region_index1 = 0; | 533 | is->cfg_param[is->scenario_id].p_region_index1 = 0; |
534 | is->cfg_param[is->scenario_id].p_region_index2 = 0; | 534 | is->cfg_param[is->scenario_id].p_region_index2 = 0; |
535 | atomic_set(&is->cfg_param[is->scenario_id].p_region_num, 0); | ||
536 | set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state); | 535 | set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state); |
537 | pr_debug("HIC_SET_PARAMETER\n"); | 536 | pr_debug("HIC_SET_PARAMETER\n"); |
538 | break; | 537 | break; |
@@ -593,7 +592,6 @@ static void fimc_is_general_irq_handler(struct fimc_is *is) | |||
593 | case HIC_SET_PARAMETER: | 592 | case HIC_SET_PARAMETER: |
594 | is->cfg_param[is->scenario_id].p_region_index1 = 0; | 593 | is->cfg_param[is->scenario_id].p_region_index1 = 0; |
595 | is->cfg_param[is->scenario_id].p_region_index2 = 0; | 594 | is->cfg_param[is->scenario_id].p_region_index2 = 0; |
596 | atomic_set(&is->cfg_param[is->scenario_id].p_region_num, 0); | ||
597 | set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state); | 595 | set_bit(IS_ST_BLOCK_CMD_CLEARED, &is->state); |
598 | break; | 596 | break; |
599 | } | 597 | } |
diff --git a/drivers/media/platform/exynos4-is/fimc-is.h b/drivers/media/platform/exynos4-is/fimc-is.h index 936e2ca5c1d2..9406894f306d 100644 --- a/drivers/media/platform/exynos4-is/fimc-is.h +++ b/drivers/media/platform/exynos4-is/fimc-is.h | |||
@@ -226,7 +226,6 @@ struct is_config_param { | |||
226 | struct drc_param drc; | 226 | struct drc_param drc; |
227 | struct fd_param fd; | 227 | struct fd_param fd; |
228 | 228 | ||
229 | atomic_t p_region_num; | ||
230 | unsigned long p_region_index1; | 229 | unsigned long p_region_index1; |
231 | unsigned long p_region_index2; | 230 | unsigned long p_region_index2; |
232 | }; | 231 | }; |
diff --git a/drivers/media/platform/exynos4-is/fimc-isp.c b/drivers/media/platform/exynos4-is/fimc-isp.c index 59502b111a8b..b11c001ad388 100644 --- a/drivers/media/platform/exynos4-is/fimc-isp.c +++ b/drivers/media/platform/exynos4-is/fimc-isp.c | |||
@@ -229,8 +229,11 @@ static int fimc_isp_subdev_s_stream(struct v4l2_subdev *sd, int on) | |||
229 | fimc_is_mem_barrier(); | 229 | fimc_is_mem_barrier(); |
230 | 230 | ||
231 | if (on) { | 231 | if (on) { |
232 | if (atomic_read(&is->cfg_param[is->scenario_id].p_region_num)) | 232 | if (__get_pending_param_count(is)) { |
233 | ret = fimc_is_itf_s_param(is, true); | 233 | ret = fimc_is_itf_s_param(is, true); |
234 | if (ret < 0) | ||
235 | return ret; | ||
236 | } | ||
234 | 237 | ||
235 | v4l2_dbg(1, debug, sd, "changing mode to %d\n", | 238 | v4l2_dbg(1, debug, sd, "changing mode to %d\n", |
236 | is->scenario_id); | 239 | is->scenario_id); |
@@ -414,7 +417,6 @@ static int __ctrl_set_aewb_lock(struct fimc_is *is, | |||
414 | isp->aa.cmd = cmd; | 417 | isp->aa.cmd = cmd; |
415 | isp->aa.target = ISP_AA_TARGET_AE; | 418 | isp->aa.target = ISP_AA_TARGET_AE; |
416 | fimc_is_set_param_bit(is, PARAM_ISP_AA); | 419 | fimc_is_set_param_bit(is, PARAM_ISP_AA); |
417 | fimc_is_inc_param_num(is); | ||
418 | is->af.ae_lock_state = ae_lock; | 420 | is->af.ae_lock_state = ae_lock; |
419 | wmb(); | 421 | wmb(); |
420 | 422 | ||
@@ -426,7 +428,6 @@ static int __ctrl_set_aewb_lock(struct fimc_is *is, | |||
426 | isp->aa.cmd = cmd; | 428 | isp->aa.cmd = cmd; |
427 | isp->aa.target = ISP_AA_TARGET_AE; | 429 | isp->aa.target = ISP_AA_TARGET_AE; |
428 | fimc_is_set_param_bit(is, PARAM_ISP_AA); | 430 | fimc_is_set_param_bit(is, PARAM_ISP_AA); |
429 | fimc_is_inc_param_num(is); | ||
430 | is->af.awb_lock_state = awb_lock; | 431 | is->af.awb_lock_state = awb_lock; |
431 | wmb(); | 432 | wmb(); |
432 | 433 | ||