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authorSungchun Kang <sungchun.kang@samsung.com>2012-07-31 09:44:03 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2012-09-15 10:03:09 -0400
commit199854a3a8e44d685ede39f9aaba4f73669e1039 (patch)
tree9937fbaf2e62ac0900d4c9d678ddde24b9a8d175 /drivers/media/platform
parent8ab023812b2b5e81bb1876a925541bceaf62538a (diff)
[media] gscaler: Add new driver for generic scaler
This patch adds support for G-Scaler (Generic Scaler) device which is a new device for scaling and color space conversion on EXYNOS5 SoCs. This patch adds the code for register definitions and register operations. This device supports the followings as key feature. 1) Input image format - RGB888/565, YUV422 1P/2P, YUV420 2P/3P, TILE 2) Output image format - RGB888/565, YUV422 1P/2P, YUV420 2P/3P, YUV444 3) Input rotation - 0/90/180/270 degree, X/Y Flip 4) Scale ratio - 1/16 scale down to 8 scale up 5) CSC - RGB to YUV / YUV to RGB 6) Size - 2048 x 2048 for tile or rotation - 4800 x 3344 other case Signed-off-by: Hynwoong Kim <khw0178.kim@samsung.com> Signed-off-by: Sungchun Kang <sungchun.kang@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/platform')
-rw-r--r--drivers/media/platform/exynos-gsc/gsc-regs.c425
-rw-r--r--drivers/media/platform/exynos-gsc/gsc-regs.h172
2 files changed, 597 insertions, 0 deletions
diff --git a/drivers/media/platform/exynos-gsc/gsc-regs.c b/drivers/media/platform/exynos-gsc/gsc-regs.c
new file mode 100644
index 000000000000..0d8625f03a32
--- /dev/null
+++ b/drivers/media/platform/exynos-gsc/gsc-regs.c
@@ -0,0 +1,425 @@
1/*
2 * Copyright (c) 2011 - 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Samsung EXYNOS5 SoC series G-Scaler driver
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published
9 * by the Free Software Foundation, either version 2 of the License,
10 * or (at your option) any later version.
11 */
12
13#include <linux/io.h>
14#include <linux/delay.h>
15#include <mach/map.h>
16
17#include "gsc-core.h"
18
19void gsc_hw_set_sw_reset(struct gsc_dev *dev)
20{
21 writel(GSC_SW_RESET_SRESET, dev->regs + GSC_SW_RESET);
22}
23
24int gsc_wait_reset(struct gsc_dev *dev)
25{
26 unsigned long end = jiffies + msecs_to_jiffies(50);
27 u32 cfg;
28
29 while (time_before(jiffies, end)) {
30 cfg = readl(dev->regs + GSC_SW_RESET);
31 if (!cfg)
32 return 0;
33 usleep_range(10, 20);
34 }
35
36 return -EBUSY;
37}
38
39void gsc_hw_set_frm_done_irq_mask(struct gsc_dev *dev, bool mask)
40{
41 u32 cfg;
42
43 cfg = readl(dev->regs + GSC_IRQ);
44 if (mask)
45 cfg |= GSC_IRQ_FRMDONE_MASK;
46 else
47 cfg &= ~GSC_IRQ_FRMDONE_MASK;
48 writel(cfg, dev->regs + GSC_IRQ);
49}
50
51void gsc_hw_set_gsc_irq_enable(struct gsc_dev *dev, bool mask)
52{
53 u32 cfg;
54
55 cfg = readl(dev->regs + GSC_IRQ);
56 if (mask)
57 cfg |= GSC_IRQ_ENABLE;
58 else
59 cfg &= ~GSC_IRQ_ENABLE;
60 writel(cfg, dev->regs + GSC_IRQ);
61}
62
63void gsc_hw_set_input_buf_masking(struct gsc_dev *dev, u32 shift,
64 bool enable)
65{
66 u32 cfg = readl(dev->regs + GSC_IN_BASE_ADDR_Y_MASK);
67 u32 mask = 1 << shift;
68
69 cfg &= ~mask;
70 cfg |= enable << shift;
71
72 writel(cfg, dev->regs + GSC_IN_BASE_ADDR_Y_MASK);
73 writel(cfg, dev->regs + GSC_IN_BASE_ADDR_CB_MASK);
74 writel(cfg, dev->regs + GSC_IN_BASE_ADDR_CR_MASK);
75}
76
77void gsc_hw_set_output_buf_masking(struct gsc_dev *dev, u32 shift,
78 bool enable)
79{
80 u32 cfg = readl(dev->regs + GSC_OUT_BASE_ADDR_Y_MASK);
81 u32 mask = 1 << shift;
82
83 cfg &= ~mask;
84 cfg |= enable << shift;
85
86 writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_Y_MASK);
87 writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_CB_MASK);
88 writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_CR_MASK);
89}
90
91void gsc_hw_set_input_addr(struct gsc_dev *dev, struct gsc_addr *addr,
92 int index)
93{
94 pr_debug("src_buf[%d]: 0x%X, cb: 0x%X, cr: 0x%X", index,
95 addr->y, addr->cb, addr->cr);
96 writel(addr->y, dev->regs + GSC_IN_BASE_ADDR_Y(index));
97 writel(addr->cb, dev->regs + GSC_IN_BASE_ADDR_CB(index));
98 writel(addr->cr, dev->regs + GSC_IN_BASE_ADDR_CR(index));
99
100}
101
102void gsc_hw_set_output_addr(struct gsc_dev *dev,
103 struct gsc_addr *addr, int index)
104{
105 pr_debug("dst_buf[%d]: 0x%X, cb: 0x%X, cr: 0x%X",
106 index, addr->y, addr->cb, addr->cr);
107 writel(addr->y, dev->regs + GSC_OUT_BASE_ADDR_Y(index));
108 writel(addr->cb, dev->regs + GSC_OUT_BASE_ADDR_CB(index));
109 writel(addr->cr, dev->regs + GSC_OUT_BASE_ADDR_CR(index));
110}
111
112void gsc_hw_set_input_path(struct gsc_ctx *ctx)
113{
114 struct gsc_dev *dev = ctx->gsc_dev;
115
116 u32 cfg = readl(dev->regs + GSC_IN_CON);
117 cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK);
118
119 if (ctx->in_path == GSC_DMA)
120 cfg |= GSC_IN_PATH_MEMORY;
121
122 writel(cfg, dev->regs + GSC_IN_CON);
123}
124
125void gsc_hw_set_in_size(struct gsc_ctx *ctx)
126{
127 struct gsc_dev *dev = ctx->gsc_dev;
128 struct gsc_frame *frame = &ctx->s_frame;
129 u32 cfg;
130
131 /* Set input pixel offset */
132 cfg = GSC_SRCIMG_OFFSET_X(frame->crop.left);
133 cfg |= GSC_SRCIMG_OFFSET_Y(frame->crop.top);
134 writel(cfg, dev->regs + GSC_SRCIMG_OFFSET);
135
136 /* Set input original size */
137 cfg = GSC_SRCIMG_WIDTH(frame->f_width);
138 cfg |= GSC_SRCIMG_HEIGHT(frame->f_height);
139 writel(cfg, dev->regs + GSC_SRCIMG_SIZE);
140
141 /* Set input cropped size */
142 cfg = GSC_CROPPED_WIDTH(frame->crop.width);
143 cfg |= GSC_CROPPED_HEIGHT(frame->crop.height);
144 writel(cfg, dev->regs + GSC_CROPPED_SIZE);
145}
146
147void gsc_hw_set_in_image_rgb(struct gsc_ctx *ctx)
148{
149 struct gsc_dev *dev = ctx->gsc_dev;
150 struct gsc_frame *frame = &ctx->s_frame;
151 u32 cfg;
152
153 cfg = readl(dev->regs + GSC_IN_CON);
154 if (frame->colorspace == V4L2_COLORSPACE_REC709)
155 cfg |= GSC_IN_RGB_HD_WIDE;
156 else
157 cfg |= GSC_IN_RGB_SD_WIDE;
158
159 if (frame->fmt->pixelformat == V4L2_PIX_FMT_RGB565X)
160 cfg |= GSC_IN_RGB565;
161 else if (frame->fmt->pixelformat == V4L2_PIX_FMT_RGB32)
162 cfg |= GSC_IN_XRGB8888;
163
164 writel(cfg, dev->regs + GSC_IN_CON);
165}
166
167void gsc_hw_set_in_image_format(struct gsc_ctx *ctx)
168{
169 struct gsc_dev *dev = ctx->gsc_dev;
170 struct gsc_frame *frame = &ctx->s_frame;
171 u32 i, depth = 0;
172 u32 cfg;
173
174 cfg = readl(dev->regs + GSC_IN_CON);
175 cfg &= ~(GSC_IN_RGB_TYPE_MASK | GSC_IN_YUV422_1P_ORDER_MASK |
176 GSC_IN_CHROMA_ORDER_MASK | GSC_IN_FORMAT_MASK |
177 GSC_IN_TILE_TYPE_MASK | GSC_IN_TILE_MODE);
178 writel(cfg, dev->regs + GSC_IN_CON);
179
180 if (is_rgb(frame->fmt->color)) {
181 gsc_hw_set_in_image_rgb(ctx);
182 return;
183 }
184 for (i = 0; i < frame->fmt->num_planes; i++)
185 depth += frame->fmt->depth[i];
186
187 switch (frame->fmt->num_comp) {
188 case 1:
189 cfg |= GSC_IN_YUV422_1P;
190 if (frame->fmt->yorder == GSC_LSB_Y)
191 cfg |= GSC_IN_YUV422_1P_ORDER_LSB_Y;
192 else
193 cfg |= GSC_IN_YUV422_1P_OEDER_LSB_C;
194 if (frame->fmt->corder == GSC_CBCR)
195 cfg |= GSC_IN_CHROMA_ORDER_CBCR;
196 else
197 cfg |= GSC_IN_CHROMA_ORDER_CRCB;
198 break;
199 case 2:
200 if (depth == 12)
201 cfg |= GSC_IN_YUV420_2P;
202 else
203 cfg |= GSC_IN_YUV422_2P;
204 if (frame->fmt->corder == GSC_CBCR)
205 cfg |= GSC_IN_CHROMA_ORDER_CBCR;
206 else
207 cfg |= GSC_IN_CHROMA_ORDER_CRCB;
208 break;
209 case 3:
210 if (depth == 12)
211 cfg |= GSC_IN_YUV420_3P;
212 else
213 cfg |= GSC_IN_YUV422_3P;
214 break;
215 };
216
217 writel(cfg, dev->regs + GSC_IN_CON);
218}
219
220void gsc_hw_set_output_path(struct gsc_ctx *ctx)
221{
222 struct gsc_dev *dev = ctx->gsc_dev;
223
224 u32 cfg = readl(dev->regs + GSC_OUT_CON);
225 cfg &= ~GSC_OUT_PATH_MASK;
226
227 if (ctx->out_path == GSC_DMA)
228 cfg |= GSC_OUT_PATH_MEMORY;
229 else
230 cfg |= GSC_OUT_PATH_LOCAL;
231
232 writel(cfg, dev->regs + GSC_OUT_CON);
233}
234
235void gsc_hw_set_out_size(struct gsc_ctx *ctx)
236{
237 struct gsc_dev *dev = ctx->gsc_dev;
238 struct gsc_frame *frame = &ctx->d_frame;
239 u32 cfg;
240
241 /* Set output original size */
242 if (ctx->out_path == GSC_DMA) {
243 cfg = GSC_DSTIMG_OFFSET_X(frame->crop.left);
244 cfg |= GSC_DSTIMG_OFFSET_Y(frame->crop.top);
245 writel(cfg, dev->regs + GSC_DSTIMG_OFFSET);
246
247 cfg = GSC_DSTIMG_WIDTH(frame->f_width);
248 cfg |= GSC_DSTIMG_HEIGHT(frame->f_height);
249 writel(cfg, dev->regs + GSC_DSTIMG_SIZE);
250 }
251
252 /* Set output scaled size */
253 if (ctx->gsc_ctrls.rotate->val == 90 ||
254 ctx->gsc_ctrls.rotate->val == 270) {
255 cfg = GSC_SCALED_WIDTH(frame->crop.height);
256 cfg |= GSC_SCALED_HEIGHT(frame->crop.width);
257 } else {
258 cfg = GSC_SCALED_WIDTH(frame->crop.width);
259 cfg |= GSC_SCALED_HEIGHT(frame->crop.height);
260 }
261 writel(cfg, dev->regs + GSC_SCALED_SIZE);
262}
263
264void gsc_hw_set_out_image_rgb(struct gsc_ctx *ctx)
265{
266 struct gsc_dev *dev = ctx->gsc_dev;
267 struct gsc_frame *frame = &ctx->d_frame;
268 u32 cfg;
269
270 cfg = readl(dev->regs + GSC_OUT_CON);
271 if (frame->colorspace == V4L2_COLORSPACE_REC709)
272 cfg |= GSC_OUT_RGB_HD_WIDE;
273 else
274 cfg |= GSC_OUT_RGB_SD_WIDE;
275
276 if (frame->fmt->pixelformat == V4L2_PIX_FMT_RGB565X)
277 cfg |= GSC_OUT_RGB565;
278 else if (frame->fmt->pixelformat == V4L2_PIX_FMT_RGB32)
279 cfg |= GSC_OUT_XRGB8888;
280
281 writel(cfg, dev->regs + GSC_OUT_CON);
282}
283
284void gsc_hw_set_out_image_format(struct gsc_ctx *ctx)
285{
286 struct gsc_dev *dev = ctx->gsc_dev;
287 struct gsc_frame *frame = &ctx->d_frame;
288 u32 i, depth = 0;
289 u32 cfg;
290
291 cfg = readl(dev->regs + GSC_OUT_CON);
292 cfg &= ~(GSC_OUT_RGB_TYPE_MASK | GSC_OUT_YUV422_1P_ORDER_MASK |
293 GSC_OUT_CHROMA_ORDER_MASK | GSC_OUT_FORMAT_MASK |
294 GSC_OUT_TILE_TYPE_MASK | GSC_OUT_TILE_MODE);
295 writel(cfg, dev->regs + GSC_OUT_CON);
296
297 if (is_rgb(frame->fmt->color)) {
298 gsc_hw_set_out_image_rgb(ctx);
299 return;
300 }
301
302 if (ctx->out_path != GSC_DMA) {
303 cfg |= GSC_OUT_YUV444;
304 goto end_set;
305 }
306
307 for (i = 0; i < frame->fmt->num_planes; i++)
308 depth += frame->fmt->depth[i];
309
310 switch (frame->fmt->num_comp) {
311 case 1:
312 cfg |= GSC_OUT_YUV422_1P;
313 if (frame->fmt->yorder == GSC_LSB_Y)
314 cfg |= GSC_OUT_YUV422_1P_ORDER_LSB_Y;
315 else
316 cfg |= GSC_OUT_YUV422_1P_OEDER_LSB_C;
317 if (frame->fmt->corder == GSC_CBCR)
318 cfg |= GSC_OUT_CHROMA_ORDER_CBCR;
319 else
320 cfg |= GSC_OUT_CHROMA_ORDER_CRCB;
321 break;
322 case 2:
323 if (depth == 12)
324 cfg |= GSC_OUT_YUV420_2P;
325 else
326 cfg |= GSC_OUT_YUV422_2P;
327 if (frame->fmt->corder == GSC_CBCR)
328 cfg |= GSC_OUT_CHROMA_ORDER_CBCR;
329 else
330 cfg |= GSC_OUT_CHROMA_ORDER_CRCB;
331 break;
332 case 3:
333 cfg |= GSC_OUT_YUV420_3P;
334 break;
335 };
336
337end_set:
338 writel(cfg, dev->regs + GSC_OUT_CON);
339}
340
341void gsc_hw_set_prescaler(struct gsc_ctx *ctx)
342{
343 struct gsc_dev *dev = ctx->gsc_dev;
344 struct gsc_scaler *sc = &ctx->scaler;
345 u32 cfg;
346
347 cfg = GSC_PRESC_SHFACTOR(sc->pre_shfactor);
348 cfg |= GSC_PRESC_H_RATIO(sc->pre_hratio);
349 cfg |= GSC_PRESC_V_RATIO(sc->pre_vratio);
350 writel(cfg, dev->regs + GSC_PRE_SCALE_RATIO);
351}
352
353void gsc_hw_set_mainscaler(struct gsc_ctx *ctx)
354{
355 struct gsc_dev *dev = ctx->gsc_dev;
356 struct gsc_scaler *sc = &ctx->scaler;
357 u32 cfg;
358
359 cfg = GSC_MAIN_H_RATIO_VALUE(sc->main_hratio);
360 writel(cfg, dev->regs + GSC_MAIN_H_RATIO);
361
362 cfg = GSC_MAIN_V_RATIO_VALUE(sc->main_vratio);
363 writel(cfg, dev->regs + GSC_MAIN_V_RATIO);
364}
365
366void gsc_hw_set_rotation(struct gsc_ctx *ctx)
367{
368 struct gsc_dev *dev = ctx->gsc_dev;
369 u32 cfg;
370
371 cfg = readl(dev->regs + GSC_IN_CON);
372 cfg &= ~GSC_IN_ROT_MASK;
373
374 switch (ctx->gsc_ctrls.rotate->val) {
375 case 270:
376 cfg |= GSC_IN_ROT_270;
377 break;
378 case 180:
379 cfg |= GSC_IN_ROT_180;
380 break;
381 case 90:
382 if (ctx->gsc_ctrls.hflip->val)
383 cfg |= GSC_IN_ROT_90_XFLIP;
384 else if (ctx->gsc_ctrls.vflip->val)
385 cfg |= GSC_IN_ROT_90_YFLIP;
386 else
387 cfg |= GSC_IN_ROT_90;
388 break;
389 case 0:
390 if (ctx->gsc_ctrls.hflip->val)
391 cfg |= GSC_IN_ROT_XFLIP;
392 else if (ctx->gsc_ctrls.vflip->val)
393 cfg |= GSC_IN_ROT_YFLIP;
394 }
395
396 writel(cfg, dev->regs + GSC_IN_CON);
397}
398
399void gsc_hw_set_global_alpha(struct gsc_ctx *ctx)
400{
401 struct gsc_dev *dev = ctx->gsc_dev;
402 struct gsc_frame *frame = &ctx->d_frame;
403 u32 cfg;
404
405 if (!is_rgb(frame->fmt->color)) {
406 pr_debug("Not a RGB format");
407 return;
408 }
409
410 cfg = readl(dev->regs + GSC_OUT_CON);
411 cfg &= ~GSC_OUT_GLOBAL_ALPHA_MASK;
412
413 cfg |= GSC_OUT_GLOBAL_ALPHA(ctx->gsc_ctrls.global_alpha->val);
414 writel(cfg, dev->regs + GSC_OUT_CON);
415}
416
417void gsc_hw_set_sfr_update(struct gsc_ctx *ctx)
418{
419 struct gsc_dev *dev = ctx->gsc_dev;
420 u32 cfg;
421
422 cfg = readl(dev->regs + GSC_ENABLE);
423 cfg |= GSC_ENABLE_SFR_UPDATE;
424 writel(cfg, dev->regs + GSC_ENABLE);
425}
diff --git a/drivers/media/platform/exynos-gsc/gsc-regs.h b/drivers/media/platform/exynos-gsc/gsc-regs.h
new file mode 100644
index 000000000000..533e9947a925
--- /dev/null
+++ b/drivers/media/platform/exynos-gsc/gsc-regs.h
@@ -0,0 +1,172 @@
1/*
2 * Copyright (c) 2011 - 2012 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Register definition file for Samsung G-Scaler driver
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef REGS_GSC_H_
13#define REGS_GSC_H_
14
15/* G-Scaler enable */
16#define GSC_ENABLE 0x00
17#define GSC_ENABLE_OP_STATUS (1 << 2)
18#define GSC_ENABLE_SFR_UPDATE (1 << 1)
19#define GSC_ENABLE_ON (1 << 0)
20
21/* G-Scaler S/W reset */
22#define GSC_SW_RESET 0x04
23#define GSC_SW_RESET_SRESET (1 << 0)
24
25/* G-Scaler IRQ */
26#define GSC_IRQ 0x08
27#define GSC_IRQ_STATUS_OR_IRQ (1 << 17)
28#define GSC_IRQ_STATUS_FRM_DONE_IRQ (1 << 16)
29#define GSC_IRQ_FRMDONE_MASK (1 << 1)
30#define GSC_IRQ_ENABLE (1 << 0)
31
32/* G-Scaler input control */
33#define GSC_IN_CON 0x10
34#define GSC_IN_ROT_MASK (7 << 16)
35#define GSC_IN_ROT_270 (7 << 16)
36#define GSC_IN_ROT_90_YFLIP (6 << 16)
37#define GSC_IN_ROT_90_XFLIP (5 << 16)
38#define GSC_IN_ROT_90 (4 << 16)
39#define GSC_IN_ROT_180 (3 << 16)
40#define GSC_IN_ROT_YFLIP (2 << 16)
41#define GSC_IN_ROT_XFLIP (1 << 16)
42#define GSC_IN_RGB_TYPE_MASK (3 << 14)
43#define GSC_IN_RGB_HD_WIDE (3 << 14)
44#define GSC_IN_RGB_HD_NARROW (2 << 14)
45#define GSC_IN_RGB_SD_WIDE (1 << 14)
46#define GSC_IN_RGB_SD_NARROW (0 << 14)
47#define GSC_IN_YUV422_1P_ORDER_MASK (1 << 13)
48#define GSC_IN_YUV422_1P_ORDER_LSB_Y (0 << 13)
49#define GSC_IN_YUV422_1P_OEDER_LSB_C (1 << 13)
50#define GSC_IN_CHROMA_ORDER_MASK (1 << 12)
51#define GSC_IN_CHROMA_ORDER_CBCR (0 << 12)
52#define GSC_IN_CHROMA_ORDER_CRCB (1 << 12)
53#define GSC_IN_FORMAT_MASK (7 << 8)
54#define GSC_IN_XRGB8888 (0 << 8)
55#define GSC_IN_RGB565 (1 << 8)
56#define GSC_IN_YUV420_2P (2 << 8)
57#define GSC_IN_YUV420_3P (3 << 8)
58#define GSC_IN_YUV422_1P (4 << 8)
59#define GSC_IN_YUV422_2P (5 << 8)
60#define GSC_IN_YUV422_3P (6 << 8)
61#define GSC_IN_TILE_TYPE_MASK (1 << 4)
62#define GSC_IN_TILE_C_16x8 (0 << 4)
63#define GSC_IN_TILE_MODE (1 << 3)
64#define GSC_IN_LOCAL_SEL_MASK (3 << 1)
65#define GSC_IN_PATH_MASK (1 << 0)
66#define GSC_IN_PATH_MEMORY (0 << 0)
67
68/* G-Scaler source image size */
69#define GSC_SRCIMG_SIZE 0x14
70#define GSC_SRCIMG_HEIGHT(x) ((x) << 16)
71#define GSC_SRCIMG_WIDTH(x) ((x) << 0)
72
73/* G-Scaler source image offset */
74#define GSC_SRCIMG_OFFSET 0x18
75#define GSC_SRCIMG_OFFSET_Y(x) ((x) << 16)
76#define GSC_SRCIMG_OFFSET_X(x) ((x) << 0)
77
78/* G-Scaler cropped source image size */
79#define GSC_CROPPED_SIZE 0x1c
80#define GSC_CROPPED_HEIGHT(x) ((x) << 16)
81#define GSC_CROPPED_WIDTH(x) ((x) << 0)
82
83/* G-Scaler output control */
84#define GSC_OUT_CON 0x20
85#define GSC_OUT_GLOBAL_ALPHA_MASK (0xff << 24)
86#define GSC_OUT_GLOBAL_ALPHA(x) ((x) << 24)
87#define GSC_OUT_RGB_TYPE_MASK (3 << 10)
88#define GSC_OUT_RGB_HD_NARROW (3 << 10)
89#define GSC_OUT_RGB_HD_WIDE (2 << 10)
90#define GSC_OUT_RGB_SD_NARROW (1 << 10)
91#define GSC_OUT_RGB_SD_WIDE (0 << 10)
92#define GSC_OUT_YUV422_1P_ORDER_MASK (1 << 9)
93#define GSC_OUT_YUV422_1P_ORDER_LSB_Y (0 << 9)
94#define GSC_OUT_YUV422_1P_OEDER_LSB_C (1 << 9)
95#define GSC_OUT_CHROMA_ORDER_MASK (1 << 8)
96#define GSC_OUT_CHROMA_ORDER_CBCR (0 << 8)
97#define GSC_OUT_CHROMA_ORDER_CRCB (1 << 8)
98#define GSC_OUT_FORMAT_MASK (7 << 4)
99#define GSC_OUT_XRGB8888 (0 << 4)
100#define GSC_OUT_RGB565 (1 << 4)
101#define GSC_OUT_YUV420_2P (2 << 4)
102#define GSC_OUT_YUV420_3P (3 << 4)
103#define GSC_OUT_YUV422_1P (4 << 4)
104#define GSC_OUT_YUV422_2P (5 << 4)
105#define GSC_OUT_YUV444 (7 << 4)
106#define GSC_OUT_TILE_TYPE_MASK (1 << 2)
107#define GSC_OUT_TILE_C_16x8 (0 << 2)
108#define GSC_OUT_TILE_MODE (1 << 1)
109#define GSC_OUT_PATH_MASK (1 << 0)
110#define GSC_OUT_PATH_LOCAL (1 << 0)
111#define GSC_OUT_PATH_MEMORY (0 << 0)
112
113/* G-Scaler scaled destination image size */
114#define GSC_SCALED_SIZE 0x24
115#define GSC_SCALED_HEIGHT(x) ((x) << 16)
116#define GSC_SCALED_WIDTH(x) ((x) << 0)
117
118/* G-Scaler pre scale ratio */
119#define GSC_PRE_SCALE_RATIO 0x28
120#define GSC_PRESC_SHFACTOR(x) ((x) << 28)
121#define GSC_PRESC_V_RATIO(x) ((x) << 16)
122#define GSC_PRESC_H_RATIO(x) ((x) << 0)
123
124/* G-Scaler main scale horizontal ratio */
125#define GSC_MAIN_H_RATIO 0x2c
126#define GSC_MAIN_H_RATIO_VALUE(x) ((x) << 0)
127
128/* G-Scaler main scale vertical ratio */
129#define GSC_MAIN_V_RATIO 0x30
130#define GSC_MAIN_V_RATIO_VALUE(x) ((x) << 0)
131
132/* G-Scaler destination image size */
133#define GSC_DSTIMG_SIZE 0x40
134#define GSC_DSTIMG_HEIGHT(x) ((x) << 16)
135#define GSC_DSTIMG_WIDTH(x) ((x) << 0)
136
137/* G-Scaler destination image offset */
138#define GSC_DSTIMG_OFFSET 0x44
139#define GSC_DSTIMG_OFFSET_Y(x) ((x) << 16)
140#define GSC_DSTIMG_OFFSET_X(x) ((x) << 0)
141
142/* G-Scaler input y address mask */
143#define GSC_IN_BASE_ADDR_Y_MASK 0x4c
144/* G-Scaler input y base address */
145#define GSC_IN_BASE_ADDR_Y(n) (0x50 + (n) * 0x4)
146
147/* G-Scaler input cb address mask */
148#define GSC_IN_BASE_ADDR_CB_MASK 0x7c
149/* G-Scaler input cb base address */
150#define GSC_IN_BASE_ADDR_CB(n) (0x80 + (n) * 0x4)
151
152/* G-Scaler input cr address mask */
153#define GSC_IN_BASE_ADDR_CR_MASK 0xac
154/* G-Scaler input cr base address */
155#define GSC_IN_BASE_ADDR_CR(n) (0xb0 + (n) * 0x4)
156
157/* G-Scaler output y address mask */
158#define GSC_OUT_BASE_ADDR_Y_MASK 0x10c
159/* G-Scaler output y base address */
160#define GSC_OUT_BASE_ADDR_Y(n) (0x110 + (n) * 0x4)
161
162/* G-Scaler output cb address mask */
163#define GSC_OUT_BASE_ADDR_CB_MASK 0x15c
164/* G-Scaler output cb base address */
165#define GSC_OUT_BASE_ADDR_CB(n) (0x160 + (n) * 0x4)
166
167/* G-Scaler output cr address mask */
168#define GSC_OUT_BASE_ADDR_CR_MASK 0x1ac
169/* G-Scaler output cr base address */
170#define GSC_OUT_BASE_ADDR_CR(n) (0x1b0 + (n) * 0x4)
171
172#endif /* REGS_GSC_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-02 22:14:49 -0400