[media] smiapp-pll: Unify OP and VT PLL structs

Uniform representation for VT and OP clocks. This is preparation for
calculating the VT clocks using the OP clock code.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>

1 files changed, 7 insertions, 7 deletions

diff --git a/drivers/media/i2c/smiapp/smiapp-core.c b/drivers/media/i2c/smiapp/smiapp-core.c
index 6174a592adcc..389e7751ebb4 100644
--- a/drivers/media/i2c/smiapp/smiapp-core.c
+++ b/drivers/media/i2c/smiapp/smiapp-core.c
@@ -205,12 +205,12 @@ static int smiapp_pll_configure(struct smiapp_sensor *sensor)
         int rval;
 
         rval = smiapp_write(
-                sensor, SMIAPP_REG_U16_VT_PIX_CLK_DIV, pll->vt_pix_clk_div);
+                sensor, SMIAPP_REG_U16_VT_PIX_CLK_DIV, pll->vt.pix_clk_div);
         if (rval < 0)
                 return rval;
 
         rval = smiapp_write(
-                sensor, SMIAPP_REG_U16_VT_SYS_CLK_DIV, pll->vt_sys_clk_div);
+                sensor, SMIAPP_REG_U16_VT_SYS_CLK_DIV, pll->vt.sys_clk_div);
         if (rval < 0)
                 return rval;
 
@@ -227,17 +227,17 @@ static int smiapp_pll_configure(struct smiapp_sensor *sensor)
         /* Lane op clock ratio does not apply here. */
         rval = smiapp_write(
                 sensor, SMIAPP_REG_U32_REQUESTED_LINK_BIT_RATE_MBPS,
-                DIV_ROUND_UP(pll->op_sys_clk_freq_hz, 1000000 / 256 / 256));
+                DIV_ROUND_UP(pll->op.sys_clk_freq_hz, 1000000 / 256 / 256));
         if (rval < 0 || sensor->minfo.smiapp_profile == SMIAPP_PROFILE_0)
                 return rval;
 
         rval = smiapp_write(
-                sensor, SMIAPP_REG_U16_OP_PIX_CLK_DIV, pll->op_pix_clk_div);
+                sensor, SMIAPP_REG_U16_OP_PIX_CLK_DIV, pll->op.pix_clk_div);
         if (rval < 0)
                 return rval;
 
         return smiapp_write(
-                sensor, SMIAPP_REG_U16_OP_SYS_CLK_DIV, pll->op_sys_clk_div);
+                sensor, SMIAPP_REG_U16_OP_SYS_CLK_DIV, pll->op.sys_clk_div);
 }
 
 static int smiapp_pll_update(struct smiapp_sensor *sensor)
@@ -299,7 +299,7 @@ static int smiapp_pll_update(struct smiapp_sensor *sensor)
                 return rval;
 
         __v4l2_ctrl_s_ctrl_int64(sensor->pixel_rate_parray,
-                                 pll->vt_pix_clk_freq_hz);
+                                 pll->vt.pix_clk_freq_hz);
         __v4l2_ctrl_s_ctrl_int64(sensor->pixel_rate_csi, pll->pixel_rate_csi);
 
         return 0;
@@ -904,7 +904,7 @@ static int smiapp_update_mode(struct smiapp_sensor *sensor)
         dev_dbg(&client->dev, "hblank\t\t%d\n", sensor->hblank->val);
 
         dev_dbg(&client->dev, "real timeperframe\t100/%d\n",
-                sensor->pll.vt_pix_clk_freq_hz /
+                sensor->pll.vt.pix_clk_freq_hz /
                 ((sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].width
                   + sensor->hblank->val) *
                  (sensor->pixel_array->crop[SMIAPP_PA_PAD_SRC].height