diff options
author | Lad, Prabhakar <prabhakar.csengg@gmail.com> | 2014-01-21 00:20:57 -0500 |
---|---|---|
committer | Mauro Carvalho Chehab <m.chehab@samsung.com> | 2014-02-24 11:12:53 -0500 |
commit | ee2d16d7b3c95a65ed0434841568bd3f82712338 (patch) | |
tree | 07e8c3bb0d77060d4eabcdf4ccde894e4eeb10b9 /drivers/media/i2c/mt9p031.c | |
parent | a970449e40789a0056424668da5b56f57569ea73 (diff) |
[media] mt9p031: Check return value of clk_prepare_enable/clk_set_rate
clk_set_rate(), clk_prepare_enable() functions can fail, so check the return
values to avoid surprises.
Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
Diffstat (limited to 'drivers/media/i2c/mt9p031.c')
-rw-r--r-- | drivers/media/i2c/mt9p031.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index fec76d3f056c..dd7b258a9802 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c | |||
@@ -232,12 +232,15 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) | |||
232 | 232 | ||
233 | struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); | 233 | struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); |
234 | struct mt9p031_platform_data *pdata = mt9p031->pdata; | 234 | struct mt9p031_platform_data *pdata = mt9p031->pdata; |
235 | int ret; | ||
235 | 236 | ||
236 | mt9p031->clk = devm_clk_get(&client->dev, NULL); | 237 | mt9p031->clk = devm_clk_get(&client->dev, NULL); |
237 | if (IS_ERR(mt9p031->clk)) | 238 | if (IS_ERR(mt9p031->clk)) |
238 | return PTR_ERR(mt9p031->clk); | 239 | return PTR_ERR(mt9p031->clk); |
239 | 240 | ||
240 | clk_set_rate(mt9p031->clk, pdata->ext_freq); | 241 | ret = clk_set_rate(mt9p031->clk, pdata->ext_freq); |
242 | if (ret < 0) | ||
243 | return ret; | ||
241 | 244 | ||
242 | /* If the external clock frequency is out of bounds for the PLL use the | 245 | /* If the external clock frequency is out of bounds for the PLL use the |
243 | * pixel clock divider only and disable the PLL. | 246 | * pixel clock divider only and disable the PLL. |
@@ -318,8 +321,14 @@ static int mt9p031_power_on(struct mt9p031 *mt9p031) | |||
318 | return ret; | 321 | return ret; |
319 | 322 | ||
320 | /* Enable clock */ | 323 | /* Enable clock */ |
321 | if (mt9p031->clk) | 324 | if (mt9p031->clk) { |
322 | clk_prepare_enable(mt9p031->clk); | 325 | ret = clk_prepare_enable(mt9p031->clk); |
326 | if (ret) { | ||
327 | regulator_bulk_disable(ARRAY_SIZE(mt9p031->regulators), | ||
328 | mt9p031->regulators); | ||
329 | return ret; | ||
330 | } | ||
331 | } | ||
323 | 332 | ||
324 | /* Now RESET_BAR must be high */ | 333 | /* Now RESET_BAR must be high */ |
325 | if (gpio_is_valid(mt9p031->reset)) { | 334 | if (gpio_is_valid(mt9p031->reset)) { |