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authorMauro Carvalho Chehab <mchehab@redhat.com>2012-08-14 15:23:43 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2012-08-15 15:42:14 -0400
commitcb7a01ac324bf2ee2c666f37ac867e4135f9785a (patch)
tree7246b915a9334d4bc823c93ba9acab65ef882678 /drivers/media/i2c/cx25840
parentf0af8fa4dad0839f844fd0633e1936493f6d685a (diff)
[media] move i2c files into drivers/media/i2c
Move ancillary I2C drivers into drivers/media/i2c, in order to better organize them. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/i2c/cx25840')
-rw-r--r--drivers/media/i2c/cx25840/Kconfig8
-rw-r--r--drivers/media/i2c/cx25840/Makefile6
-rw-r--r--drivers/media/i2c/cx25840/cx25840-audio.c571
-rw-r--r--drivers/media/i2c/cx25840/cx25840-core.c5340
-rw-r--r--drivers/media/i2c/cx25840/cx25840-core.h137
-rw-r--r--drivers/media/i2c/cx25840/cx25840-firmware.c175
-rw-r--r--drivers/media/i2c/cx25840/cx25840-ir.c1281
-rw-r--r--drivers/media/i2c/cx25840/cx25840-vbi.c256
8 files changed, 7774 insertions, 0 deletions
diff --git a/drivers/media/i2c/cx25840/Kconfig b/drivers/media/i2c/cx25840/Kconfig
new file mode 100644
index 000000000000..451133ad41ff
--- /dev/null
+++ b/drivers/media/i2c/cx25840/Kconfig
@@ -0,0 +1,8 @@
1config VIDEO_CX25840
2 tristate "Conexant CX2584x audio/video decoders"
3 depends on VIDEO_V4L2 && I2C
4 ---help---
5 Support for the Conexant CX2584x audio/video decoders.
6
7 To compile this driver as a module, choose M here: the
8 module will be called cx25840
diff --git a/drivers/media/i2c/cx25840/Makefile b/drivers/media/i2c/cx25840/Makefile
new file mode 100644
index 000000000000..898eb13340ae
--- /dev/null
+++ b/drivers/media/i2c/cx25840/Makefile
@@ -0,0 +1,6 @@
1cx25840-objs := cx25840-core.o cx25840-audio.o cx25840-firmware.o \
2 cx25840-vbi.o cx25840-ir.o
3
4obj-$(CONFIG_VIDEO_CX25840) += cx25840.o
5
6ccflags-y += -Idrivers/media/i2c
diff --git a/drivers/media/i2c/cx25840/cx25840-audio.c b/drivers/media/i2c/cx25840/cx25840-audio.c
new file mode 100644
index 000000000000..34b96c7cfd62
--- /dev/null
+++ b/drivers/media/i2c/cx25840/cx25840-audio.c
@@ -0,0 +1,571 @@
1/* cx25840 audio functions
2 *
3 * This program is free software; you can redistribute it and/or
4 * modify it under the terms of the GNU General Public License
5 * as published by the Free Software Foundation; either version 2
6 * of the License, or (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
16 */
17
18
19#include <linux/videodev2.h>
20#include <linux/i2c.h>
21#include <media/v4l2-common.h>
22#include <media/cx25840.h>
23
24#include "cx25840-core.h"
25
26/*
27 * Note: The PLL and SRC parameters are based on a reference frequency that
28 * would ideally be:
29 *
30 * NTSC Color subcarrier freq * 8 = 4.5 MHz/286 * 455/2 * 8 = 28.63636363... MHz
31 *
32 * However, it's not the exact reference frequency that matters, only that the
33 * firmware and modules that comprise the driver for a particular board all
34 * use the same value (close to the ideal value).
35 *
36 * Comments below will note which reference frequency is assumed for various
37 * parameters. They will usually be one of
38 *
39 * ref_freq = 28.636360 MHz
40 * or
41 * ref_freq = 28.636363 MHz
42 */
43
44static int cx25840_set_audclk_freq(struct i2c_client *client, u32 freq)
45{
46 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
47
48 if (state->aud_input != CX25840_AUDIO_SERIAL) {
49 switch (freq) {
50 case 32000:
51 /*
52 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
53 * AUX_PLL Integer = 0x06, AUX PLL Post Divider = 0x10
54 */
55 cx25840_write4(client, 0x108, 0x1006040f);
56
57 /*
58 * VID_PLL Fraction (register 0x10c) = 0x2be2fe
59 * 28636360 * 0xf.15f17f0/4 = 108 MHz
60 * 432 MHz pre-postdivide
61 */
62
63 /*
64 * AUX_PLL Fraction = 0x1bb39ee
65 * 28636363 * 0x6.dd9cf70/0x10 = 32000 * 384
66 * 196.6 MHz pre-postdivide
67 * FIXME < 200 MHz is out of specified valid range
68 * FIXME 28636363 ref_freq doesn't match VID PLL ref
69 */
70 cx25840_write4(client, 0x110, 0x01bb39ee);
71
72 /*
73 * SA_MCLK_SEL = 1
74 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider
75 */
76 cx25840_write(client, 0x127, 0x50);
77
78 if (is_cx2583x(state))
79 break;
80
81 /* src3/4/6_ctl */
82 /* 0x1.f77f = (4 * 28636360/8 * 2/455) / 32000 */
83 cx25840_write4(client, 0x900, 0x0801f77f);
84 cx25840_write4(client, 0x904, 0x0801f77f);
85 cx25840_write4(client, 0x90c, 0x0801f77f);
86 break;
87
88 case 44100:
89 /*
90 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
91 * AUX_PLL Integer = 0x09, AUX PLL Post Divider = 0x10
92 */
93 cx25840_write4(client, 0x108, 0x1009040f);
94
95 /*
96 * VID_PLL Fraction (register 0x10c) = 0x2be2fe
97 * 28636360 * 0xf.15f17f0/4 = 108 MHz
98 * 432 MHz pre-postdivide
99 */
100
101 /*
102 * AUX_PLL Fraction = 0x0ec6bd6
103 * 28636363 * 0x9.7635eb0/0x10 = 44100 * 384
104 * 271 MHz pre-postdivide
105 * FIXME 28636363 ref_freq doesn't match VID PLL ref
106 */
107 cx25840_write4(client, 0x110, 0x00ec6bd6);
108
109 /*
110 * SA_MCLK_SEL = 1
111 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider
112 */
113 cx25840_write(client, 0x127, 0x50);
114
115 if (is_cx2583x(state))
116 break;
117
118 /* src3/4/6_ctl */
119 /* 0x1.6d59 = (4 * 28636360/8 * 2/455) / 44100 */
120 cx25840_write4(client, 0x900, 0x08016d59);
121 cx25840_write4(client, 0x904, 0x08016d59);
122 cx25840_write4(client, 0x90c, 0x08016d59);
123 break;
124
125 case 48000:
126 /*
127 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
128 * AUX_PLL Integer = 0x0a, AUX PLL Post Divider = 0x10
129 */
130 cx25840_write4(client, 0x108, 0x100a040f);
131
132 /*
133 * VID_PLL Fraction (register 0x10c) = 0x2be2fe
134 * 28636360 * 0xf.15f17f0/4 = 108 MHz
135 * 432 MHz pre-postdivide
136 */
137
138 /*
139 * AUX_PLL Fraction = 0x098d6e5
140 * 28636363 * 0xa.4c6b728/0x10 = 48000 * 384
141 * 295 MHz pre-postdivide
142 * FIXME 28636363 ref_freq doesn't match VID PLL ref
143 */
144 cx25840_write4(client, 0x110, 0x0098d6e5);
145
146 /*
147 * SA_MCLK_SEL = 1
148 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider
149 */
150 cx25840_write(client, 0x127, 0x50);
151
152 if (is_cx2583x(state))
153 break;
154
155 /* src3/4/6_ctl */
156 /* 0x1.4faa = (4 * 28636360/8 * 2/455) / 48000 */
157 cx25840_write4(client, 0x900, 0x08014faa);
158 cx25840_write4(client, 0x904, 0x08014faa);
159 cx25840_write4(client, 0x90c, 0x08014faa);
160 break;
161 }
162 } else {
163 switch (freq) {
164 case 32000:
165 /*
166 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
167 * AUX_PLL Integer = 0x08, AUX PLL Post Divider = 0x1e
168 */
169 cx25840_write4(client, 0x108, 0x1e08040f);
170
171 /*
172 * VID_PLL Fraction (register 0x10c) = 0x2be2fe
173 * 28636360 * 0xf.15f17f0/4 = 108 MHz
174 * 432 MHz pre-postdivide
175 */
176
177 /*
178 * AUX_PLL Fraction = 0x12a0869
179 * 28636363 * 0x8.9504348/0x1e = 32000 * 256
180 * 246 MHz pre-postdivide
181 * FIXME 28636363 ref_freq doesn't match VID PLL ref
182 */
183 cx25840_write4(client, 0x110, 0x012a0869);
184
185 /*
186 * SA_MCLK_SEL = 1
187 * SA_MCLK_DIV = 0x14 = 256/384 * AUX_PLL post dvivider
188 */
189 cx25840_write(client, 0x127, 0x54);
190
191 if (is_cx2583x(state))
192 break;
193
194 /* src1_ctl */
195 /* 0x1.0000 = 32000/32000 */
196 cx25840_write4(client, 0x8f8, 0x08010000);
197
198 /* src3/4/6_ctl */
199 /* 0x2.0000 = 2 * (32000/32000) */
200 cx25840_write4(client, 0x900, 0x08020000);
201 cx25840_write4(client, 0x904, 0x08020000);
202 cx25840_write4(client, 0x90c, 0x08020000);
203 break;
204
205 case 44100:
206 /*
207 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
208 * AUX_PLL Integer = 0x09, AUX PLL Post Divider = 0x18
209 */
210 cx25840_write4(client, 0x108, 0x1809040f);
211
212 /*
213 * VID_PLL Fraction (register 0x10c) = 0x2be2fe
214 * 28636360 * 0xf.15f17f0/4 = 108 MHz
215 * 432 MHz pre-postdivide
216 */
217
218 /*
219 * AUX_PLL Fraction = 0x0ec6bd6
220 * 28636363 * 0x9.7635eb0/0x18 = 44100 * 256
221 * 271 MHz pre-postdivide
222 * FIXME 28636363 ref_freq doesn't match VID PLL ref
223 */
224 cx25840_write4(client, 0x110, 0x00ec6bd6);
225
226 /*
227 * SA_MCLK_SEL = 1
228 * SA_MCLK_DIV = 0x10 = 256/384 * AUX_PLL post dvivider
229 */
230 cx25840_write(client, 0x127, 0x50);
231
232 if (is_cx2583x(state))
233 break;
234
235 /* src1_ctl */
236 /* 0x1.60cd = 44100/32000 */
237 cx25840_write4(client, 0x8f8, 0x080160cd);
238
239 /* src3/4/6_ctl */
240 /* 0x1.7385 = 2 * (32000/44100) */
241 cx25840_write4(client, 0x900, 0x08017385);
242 cx25840_write4(client, 0x904, 0x08017385);
243 cx25840_write4(client, 0x90c, 0x08017385);
244 break;
245
246 case 48000:
247 /*
248 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04
249 * AUX_PLL Integer = 0x0a, AUX PLL Post Divider = 0x18
250 */
251 cx25840_write4(client, 0x108, 0x180a040f);
252
253 /*
254 * VID_PLL Fraction (register 0x10c) = 0x2be2fe
255 * 28636360 * 0xf.15f17f0/4 = 108 MHz
256 * 432 MHz pre-postdivide
257 */
258
259 /*
260 * AUX_PLL Fraction = 0x098d6e5
261 * 28636363 * 0xa.4c6b728/0x18 = 48000 * 256
262 * 295 MHz pre-postdivide
263 * FIXME 28636363 ref_freq doesn't match VID PLL ref
264 */
265 cx25840_write4(client, 0x110, 0x0098d6e5);
266
267 /*
268 * SA_MCLK_SEL = 1
269 * SA_MCLK_DIV = 0x10 = 256/384 * AUX_PLL post dvivider
270 */
271 cx25840_write(client, 0x127, 0x50);
272
273 if (is_cx2583x(state))
274 break;
275
276 /* src1_ctl */
277 /* 0x1.8000 = 48000/32000 */
278 cx25840_write4(client, 0x8f8, 0x08018000);
279
280 /* src3/4/6_ctl */
281 /* 0x1.5555 = 2 * (32000/48000) */
282 cx25840_write4(client, 0x900, 0x08015555);
283 cx25840_write4(client, 0x904, 0x08015555);
284 cx25840_write4(client, 0x90c, 0x08015555);
285 break;
286 }
287 }
288
289 state->audclk_freq = freq;
290
291 return 0;
292}
293
294static inline int cx25836_set_audclk_freq(struct i2c_client *client, u32 freq)
295{
296 return cx25840_set_audclk_freq(client, freq);
297}
298
299static int cx23885_set_audclk_freq(struct i2c_client *client, u32 freq)
300{
301 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
302
303 if (state->aud_input != CX25840_AUDIO_SERIAL) {
304 switch (freq) {
305 case 32000:
306 case 44100:
307 case 48000:
308 /* We don't have register values
309 * so avoid destroying registers. */
310 /* FIXME return -EINVAL; */
311 break;
312 }
313 } else {
314 switch (freq) {
315 case 32000:
316 case 44100:
317 /* We don't have register values
318 * so avoid destroying registers. */
319 /* FIXME return -EINVAL; */
320 break;
321
322 case 48000:
323 /* src1_ctl */
324 /* 0x1.867c = 48000 / (2 * 28636360/8 * 2/455) */
325 cx25840_write4(client, 0x8f8, 0x0801867c);
326
327 /* src3/4/6_ctl */
328 /* 0x1.4faa = (4 * 28636360/8 * 2/455) / 48000 */
329 cx25840_write4(client, 0x900, 0x08014faa);
330 cx25840_write4(client, 0x904, 0x08014faa);
331 cx25840_write4(client, 0x90c, 0x08014faa);
332 break;
333 }
334 }
335
336 state->audclk_freq = freq;
337
338 return 0;
339}
340
341static int cx231xx_set_audclk_freq(struct i2c_client *client, u32 freq)
342{
343 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
344
345 if (state->aud_input != CX25840_AUDIO_SERIAL) {
346 switch (freq) {
347 case 32000:
348 /* src3/4/6_ctl */
349 /* 0x1.f77f = (4 * 28636360/8 * 2/455) / 32000 */
350 cx25840_write4(client, 0x900, 0x0801f77f);
351 cx25840_write4(client, 0x904, 0x0801f77f);
352 cx25840_write4(client, 0x90c, 0x0801f77f);
353 break;
354
355 case 44100:
356 /* src3/4/6_ctl */
357 /* 0x1.6d59 = (4 * 28636360/8 * 2/455) / 44100 */
358 cx25840_write4(client, 0x900, 0x08016d59);
359 cx25840_write4(client, 0x904, 0x08016d59);
360 cx25840_write4(client, 0x90c, 0x08016d59);
361 break;
362
363 case 48000:
364 /* src3/4/6_ctl */
365 /* 0x1.4faa = (4 * 28636360/8 * 2/455) / 48000 */
366 cx25840_write4(client, 0x900, 0x08014faa);
367 cx25840_write4(client, 0x904, 0x08014faa);
368 cx25840_write4(client, 0x90c, 0x08014faa);
369 break;
370 }
371 } else {
372 switch (freq) {
373 /* FIXME These cases make different assumptions about audclk */
374 case 32000:
375 /* src1_ctl */
376 /* 0x1.0000 = 32000/32000 */
377 cx25840_write4(client, 0x8f8, 0x08010000);
378
379 /* src3/4/6_ctl */
380 /* 0x2.0000 = 2 * (32000/32000) */
381 cx25840_write4(client, 0x900, 0x08020000);
382 cx25840_write4(client, 0x904, 0x08020000);
383 cx25840_write4(client, 0x90c, 0x08020000);
384 break;
385
386 case 44100:
387 /* src1_ctl */
388 /* 0x1.60cd = 44100/32000 */
389 cx25840_write4(client, 0x8f8, 0x080160cd);
390
391 /* src3/4/6_ctl */
392 /* 0x1.7385 = 2 * (32000/44100) */
393 cx25840_write4(client, 0x900, 0x08017385);
394 cx25840_write4(client, 0x904, 0x08017385);
395 cx25840_write4(client, 0x90c, 0x08017385);
396 break;
397
398 case 48000:
399 /* src1_ctl */
400 /* 0x1.867c = 48000 / (2 * 28636360/8 * 2/455) */
401 cx25840_write4(client, 0x8f8, 0x0801867c);
402
403 /* src3/4/6_ctl */
404 /* 0x1.4faa = (4 * 28636360/8 * 2/455) / 48000 */
405 cx25840_write4(client, 0x900, 0x08014faa);
406 cx25840_write4(client, 0x904, 0x08014faa);
407 cx25840_write4(client, 0x90c, 0x08014faa);
408 break;
409 }
410 }
411
412 state->audclk_freq = freq;
413
414 return 0;
415}
416
417static int set_audclk_freq(struct i2c_client *client, u32 freq)
418{
419 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
420
421 if (freq != 32000 && freq != 44100 && freq != 48000)
422 return -EINVAL;
423
424 if (is_cx231xx(state))
425 return cx231xx_set_audclk_freq(client, freq);
426
427 if (is_cx2388x(state))
428 return cx23885_set_audclk_freq(client, freq);
429
430 if (is_cx2583x(state))
431 return cx25836_set_audclk_freq(client, freq);
432
433 return cx25840_set_audclk_freq(client, freq);
434}
435
436void cx25840_audio_set_path(struct i2c_client *client)
437{
438 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
439
440 if (!is_cx2583x(state)) {
441 /* assert soft reset */
442 cx25840_and_or(client, 0x810, ~0x1, 0x01);
443
444 /* stop microcontroller */
445 cx25840_and_or(client, 0x803, ~0x10, 0);
446
447 /* Mute everything to prevent the PFFT! */
448 cx25840_write(client, 0x8d3, 0x1f);
449
450 if (state->aud_input == CX25840_AUDIO_SERIAL) {
451 /* Set Path1 to Serial Audio Input */
452 cx25840_write4(client, 0x8d0, 0x01011012);
453
454 /* The microcontroller should not be started for the
455 * non-tuner inputs: autodetection is specific for
456 * TV audio. */
457 } else {
458 /* Set Path1 to Analog Demod Main Channel */
459 cx25840_write4(client, 0x8d0, 0x1f063870);
460 }
461 }
462
463 set_audclk_freq(client, state->audclk_freq);
464
465 if (!is_cx2583x(state)) {
466 if (state->aud_input != CX25840_AUDIO_SERIAL) {
467 /* When the microcontroller detects the
468 * audio format, it will unmute the lines */
469 cx25840_and_or(client, 0x803, ~0x10, 0x10);
470 }
471
472 /* deassert soft reset */
473 cx25840_and_or(client, 0x810, ~0x1, 0x00);
474
475 /* Ensure the controller is running when we exit */
476 if (is_cx2388x(state) || is_cx231xx(state))
477 cx25840_and_or(client, 0x803, ~0x10, 0x10);
478 }
479}
480
481static void set_volume(struct i2c_client *client, int volume)
482{
483 int vol;
484
485 /* Convert the volume to msp3400 values (0-127) */
486 vol = volume >> 9;
487
488 /* now scale it up to cx25840 values
489 * -114dB to -96dB maps to 0
490 * this should be 19, but in my testing that was 4dB too loud */
491 if (vol <= 23) {
492 vol = 0;
493 } else {
494 vol -= 23;
495 }
496
497 /* PATH1_VOLUME */
498 cx25840_write(client, 0x8d4, 228 - (vol * 2));
499}
500
501static void set_balance(struct i2c_client *client, int balance)
502{
503 int bal = balance >> 8;
504 if (bal > 0x80) {
505 /* PATH1_BAL_LEFT */
506 cx25840_and_or(client, 0x8d5, 0x7f, 0x80);
507 /* PATH1_BAL_LEVEL */
508 cx25840_and_or(client, 0x8d5, ~0x7f, bal & 0x7f);
509 } else {
510 /* PATH1_BAL_LEFT */
511 cx25840_and_or(client, 0x8d5, 0x7f, 0x00);
512 /* PATH1_BAL_LEVEL */
513 cx25840_and_or(client, 0x8d5, ~0x7f, 0x80 - bal);
514 }
515}
516
517int cx25840_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
518{
519 struct i2c_client *client = v4l2_get_subdevdata(sd);
520 struct cx25840_state *state = to_state(sd);
521 int retval;
522
523 if (!is_cx2583x(state))
524 cx25840_and_or(client, 0x810, ~0x1, 1);
525 if (state->aud_input != CX25840_AUDIO_SERIAL) {
526 cx25840_and_or(client, 0x803, ~0x10, 0);
527 cx25840_write(client, 0x8d3, 0x1f);
528 }
529 retval = set_audclk_freq(client, freq);
530 if (state->aud_input != CX25840_AUDIO_SERIAL)
531 cx25840_and_or(client, 0x803, ~0x10, 0x10);
532 if (!is_cx2583x(state))
533 cx25840_and_or(client, 0x810, ~0x1, 0);
534 return retval;
535}
536
537static int cx25840_audio_s_ctrl(struct v4l2_ctrl *ctrl)
538{
539 struct v4l2_subdev *sd = to_sd(ctrl);
540 struct cx25840_state *state = to_state(sd);
541 struct i2c_client *client = v4l2_get_subdevdata(sd);
542
543 switch (ctrl->id) {
544 case V4L2_CID_AUDIO_VOLUME:
545 if (state->mute->val)
546 set_volume(client, 0);
547 else
548 set_volume(client, state->volume->val);
549 break;
550 case V4L2_CID_AUDIO_BASS:
551 /* PATH1_EQ_BASS_VOL */
552 cx25840_and_or(client, 0x8d9, ~0x3f,
553 48 - (ctrl->val * 48 / 0xffff));
554 break;
555 case V4L2_CID_AUDIO_TREBLE:
556 /* PATH1_EQ_TREBLE_VOL */
557 cx25840_and_or(client, 0x8db, ~0x3f,
558 48 - (ctrl->val * 48 / 0xffff));
559 break;
560 case V4L2_CID_AUDIO_BALANCE:
561 set_balance(client, ctrl->val);
562 break;
563 default:
564 return -EINVAL;
565 }
566 return 0;
567}
568
569const struct v4l2_ctrl_ops cx25840_audio_ctrl_ops = {
570 .s_ctrl = cx25840_audio_s_ctrl,
571};
diff --git a/drivers/media/i2c/cx25840/cx25840-core.c b/drivers/media/i2c/cx25840/cx25840-core.c
new file mode 100644
index 000000000000..d8eac3e30a7e
--- /dev/null
+++ b/drivers/media/i2c/cx25840/cx25840-core.c
@@ -0,0 +1,5340 @@
1/* cx25840 - Conexant CX25840 audio/video decoder driver
2 *
3 * Copyright (C) 2004 Ulf Eklund
4 *
5 * Based on the saa7115 driver and on the first version of Chris Kennedy's
6 * cx25840 driver.
7 *
8 * Changes by Tyler Trafford <tatrafford@comcast.net>
9 * - cleanup/rewrite for V4L2 API (2005)
10 *
11 * VBI support by Hans Verkuil <hverkuil@xs4all.nl>.
12 *
13 * NTSC sliced VBI support by Christopher Neufeld <television@cneufeld.ca>
14 * with additional fixes by Hans Verkuil <hverkuil@xs4all.nl>.
15 *
16 * CX23885 support by Steven Toth <stoth@linuxtv.org>.
17 *
18 * CX2388[578] IRQ handling, IO Pin mux configuration and other small fixes are
19 * Copyright (C) 2010 Andy Walls <awalls@md.metrocast.net>
20 *
21 * CX23888 DIF support for the HVR1850
22 * Copyright (C) 2011 Steven Toth <stoth@kernellabs.com>
23 *
24 * This program is free software; you can redistribute it and/or
25 * modify it under the terms of the GNU General Public License
26 * as published by the Free Software Foundation; either version 2
27 * of the License, or (at your option) any later version.
28 *
29 * This program is distributed in the hope that it will be useful,
30 * but WITHOUT ANY WARRANTY; without even the implied warranty of
31 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
32 * GNU General Public License for more details.
33 *
34 * You should have received a copy of the GNU General Public License
35 * along with this program; if not, write to the Free Software
36 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
37 */
38
39
40#include <linux/kernel.h>
41#include <linux/module.h>
42#include <linux/slab.h>
43#include <linux/videodev2.h>
44#include <linux/i2c.h>
45#include <linux/delay.h>
46#include <linux/math64.h>
47#include <media/v4l2-common.h>
48#include <media/v4l2-chip-ident.h>
49#include <media/cx25840.h>
50
51#include "cx25840-core.h"
52
53MODULE_DESCRIPTION("Conexant CX25840 audio/video decoder driver");
54MODULE_AUTHOR("Ulf Eklund, Chris Kennedy, Hans Verkuil, Tyler Trafford");
55MODULE_LICENSE("GPL");
56
57#define CX25840_VID_INT_STAT_REG 0x410
58#define CX25840_VID_INT_STAT_BITS 0x0000ffff
59#define CX25840_VID_INT_MASK_BITS 0xffff0000
60#define CX25840_VID_INT_MASK_SHFT 16
61#define CX25840_VID_INT_MASK_REG 0x412
62
63#define CX23885_AUD_MC_INT_MASK_REG 0x80c
64#define CX23885_AUD_MC_INT_STAT_BITS 0xffff0000
65#define CX23885_AUD_MC_INT_CTRL_BITS 0x0000ffff
66#define CX23885_AUD_MC_INT_STAT_SHFT 16
67
68#define CX25840_AUD_INT_CTRL_REG 0x812
69#define CX25840_AUD_INT_STAT_REG 0x813
70
71#define CX23885_PIN_CTRL_IRQ_REG 0x123
72#define CX23885_PIN_CTRL_IRQ_IR_STAT 0x40
73#define CX23885_PIN_CTRL_IRQ_AUD_STAT 0x20
74#define CX23885_PIN_CTRL_IRQ_VID_STAT 0x10
75
76#define CX25840_IR_STATS_REG 0x210
77#define CX25840_IR_IRQEN_REG 0x214
78
79static int cx25840_debug;
80
81module_param_named(debug,cx25840_debug, int, 0644);
82
83MODULE_PARM_DESC(debug, "Debugging messages [0=Off (default) 1=On]");
84
85
86/* ----------------------------------------------------------------------- */
87static void cx23888_std_setup(struct i2c_client *client);
88
89int cx25840_write(struct i2c_client *client, u16 addr, u8 value)
90{
91 u8 buffer[3];
92 buffer[0] = addr >> 8;
93 buffer[1] = addr & 0xff;
94 buffer[2] = value;
95 return i2c_master_send(client, buffer, 3);
96}
97
98int cx25840_write4(struct i2c_client *client, u16 addr, u32 value)
99{
100 u8 buffer[6];
101 buffer[0] = addr >> 8;
102 buffer[1] = addr & 0xff;
103 buffer[2] = value & 0xff;
104 buffer[3] = (value >> 8) & 0xff;
105 buffer[4] = (value >> 16) & 0xff;
106 buffer[5] = value >> 24;
107 return i2c_master_send(client, buffer, 6);
108}
109
110u8 cx25840_read(struct i2c_client * client, u16 addr)
111{
112 struct i2c_msg msgs[2];
113 u8 tx_buf[2], rx_buf[1];
114
115 /* Write register address */
116 tx_buf[0] = addr >> 8;
117 tx_buf[1] = addr & 0xff;
118 msgs[0].addr = client->addr;
119 msgs[0].flags = 0;
120 msgs[0].len = 2;
121 msgs[0].buf = (char *) tx_buf;
122
123 /* Read data from register */
124 msgs[1].addr = client->addr;
125 msgs[1].flags = I2C_M_RD;
126 msgs[1].len = 1;
127 msgs[1].buf = (char *) rx_buf;
128
129 if (i2c_transfer(client->adapter, msgs, 2) < 2)
130 return 0;
131
132 return rx_buf[0];
133}
134
135u32 cx25840_read4(struct i2c_client * client, u16 addr)
136{
137 struct i2c_msg msgs[2];
138 u8 tx_buf[2], rx_buf[4];
139
140 /* Write register address */
141 tx_buf[0] = addr >> 8;
142 tx_buf[1] = addr & 0xff;
143 msgs[0].addr = client->addr;
144 msgs[0].flags = 0;
145 msgs[0].len = 2;
146 msgs[0].buf = (char *) tx_buf;
147
148 /* Read data from registers */
149 msgs[1].addr = client->addr;
150 msgs[1].flags = I2C_M_RD;
151 msgs[1].len = 4;
152 msgs[1].buf = (char *) rx_buf;
153
154 if (i2c_transfer(client->adapter, msgs, 2) < 2)
155 return 0;
156
157 return (rx_buf[3] << 24) | (rx_buf[2] << 16) | (rx_buf[1] << 8) |
158 rx_buf[0];
159}
160
161int cx25840_and_or(struct i2c_client *client, u16 addr, unsigned and_mask,
162 u8 or_value)
163{
164 return cx25840_write(client, addr,
165 (cx25840_read(client, addr) & and_mask) |
166 or_value);
167}
168
169int cx25840_and_or4(struct i2c_client *client, u16 addr, u32 and_mask,
170 u32 or_value)
171{
172 return cx25840_write4(client, addr,
173 (cx25840_read4(client, addr) & and_mask) |
174 or_value);
175}
176
177/* ----------------------------------------------------------------------- */
178
179static int set_input(struct i2c_client *client, enum cx25840_video_input vid_input,
180 enum cx25840_audio_input aud_input);
181
182/* ----------------------------------------------------------------------- */
183
184static int cx23885_s_io_pin_config(struct v4l2_subdev *sd, size_t n,
185 struct v4l2_subdev_io_pin_config *p)
186{
187 struct i2c_client *client = v4l2_get_subdevdata(sd);
188 int i;
189 u32 pin_ctrl;
190 u8 gpio_oe, gpio_data, strength;
191
192 pin_ctrl = cx25840_read4(client, 0x120);
193 gpio_oe = cx25840_read(client, 0x160);
194 gpio_data = cx25840_read(client, 0x164);
195
196 for (i = 0; i < n; i++) {
197 strength = p[i].strength;
198 if (strength > CX25840_PIN_DRIVE_FAST)
199 strength = CX25840_PIN_DRIVE_FAST;
200
201 switch (p[i].pin) {
202 case CX23885_PIN_IRQ_N_GPIO16:
203 if (p[i].function != CX23885_PAD_IRQ_N) {
204 /* GPIO16 */
205 pin_ctrl &= ~(0x1 << 25);
206 } else {
207 /* IRQ_N */
208 if (p[i].flags &
209 (V4L2_SUBDEV_IO_PIN_DISABLE |
210 V4L2_SUBDEV_IO_PIN_INPUT)) {
211 pin_ctrl &= ~(0x1 << 25);
212 } else {
213 pin_ctrl |= (0x1 << 25);
214 }
215 if (p[i].flags &
216 V4L2_SUBDEV_IO_PIN_ACTIVE_LOW) {
217 pin_ctrl &= ~(0x1 << 24);
218 } else {
219 pin_ctrl |= (0x1 << 24);
220 }
221 }
222 break;
223 case CX23885_PIN_IR_RX_GPIO19:
224 if (p[i].function != CX23885_PAD_GPIO19) {
225 /* IR_RX */
226 gpio_oe |= (0x1 << 0);
227 pin_ctrl &= ~(0x3 << 18);
228 pin_ctrl |= (strength << 18);
229 } else {
230 /* GPIO19 */
231 gpio_oe &= ~(0x1 << 0);
232 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
233 gpio_data &= ~(0x1 << 0);
234 gpio_data |= ((p[i].value & 0x1) << 0);
235 }
236 pin_ctrl &= ~(0x3 << 12);
237 pin_ctrl |= (strength << 12);
238 }
239 break;
240 case CX23885_PIN_IR_TX_GPIO20:
241 if (p[i].function != CX23885_PAD_GPIO20) {
242 /* IR_TX */
243 gpio_oe |= (0x1 << 1);
244 if (p[i].flags & V4L2_SUBDEV_IO_PIN_DISABLE)
245 pin_ctrl &= ~(0x1 << 10);
246 else
247 pin_ctrl |= (0x1 << 10);
248 pin_ctrl &= ~(0x3 << 18);
249 pin_ctrl |= (strength << 18);
250 } else {
251 /* GPIO20 */
252 gpio_oe &= ~(0x1 << 1);
253 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
254 gpio_data &= ~(0x1 << 1);
255 gpio_data |= ((p[i].value & 0x1) << 1);
256 }
257 pin_ctrl &= ~(0x3 << 12);
258 pin_ctrl |= (strength << 12);
259 }
260 break;
261 case CX23885_PIN_I2S_SDAT_GPIO21:
262 if (p[i].function != CX23885_PAD_GPIO21) {
263 /* I2S_SDAT */
264 /* TODO: Input or Output config */
265 gpio_oe |= (0x1 << 2);
266 pin_ctrl &= ~(0x3 << 22);
267 pin_ctrl |= (strength << 22);
268 } else {
269 /* GPIO21 */
270 gpio_oe &= ~(0x1 << 2);
271 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
272 gpio_data &= ~(0x1 << 2);
273 gpio_data |= ((p[i].value & 0x1) << 2);
274 }
275 pin_ctrl &= ~(0x3 << 12);
276 pin_ctrl |= (strength << 12);
277 }
278 break;
279 case CX23885_PIN_I2S_WCLK_GPIO22:
280 if (p[i].function != CX23885_PAD_GPIO22) {
281 /* I2S_WCLK */
282 /* TODO: Input or Output config */
283 gpio_oe |= (0x1 << 3);
284 pin_ctrl &= ~(0x3 << 22);
285 pin_ctrl |= (strength << 22);
286 } else {
287 /* GPIO22 */
288 gpio_oe &= ~(0x1 << 3);
289 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
290 gpio_data &= ~(0x1 << 3);
291 gpio_data |= ((p[i].value & 0x1) << 3);
292 }
293 pin_ctrl &= ~(0x3 << 12);
294 pin_ctrl |= (strength << 12);
295 }
296 break;
297 case CX23885_PIN_I2S_BCLK_GPIO23:
298 if (p[i].function != CX23885_PAD_GPIO23) {
299 /* I2S_BCLK */
300 /* TODO: Input or Output config */
301 gpio_oe |= (0x1 << 4);
302 pin_ctrl &= ~(0x3 << 22);
303 pin_ctrl |= (strength << 22);
304 } else {
305 /* GPIO23 */
306 gpio_oe &= ~(0x1 << 4);
307 if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
308 gpio_data &= ~(0x1 << 4);
309 gpio_data |= ((p[i].value & 0x1) << 4);
310 }
311 pin_ctrl &= ~(0x3 << 12);
312 pin_ctrl |= (strength << 12);
313 }
314 break;
315 }
316 }
317
318 cx25840_write(client, 0x164, gpio_data);
319 cx25840_write(client, 0x160, gpio_oe);
320 cx25840_write4(client, 0x120, pin_ctrl);
321 return 0;
322}
323
324static int common_s_io_pin_config(struct v4l2_subdev *sd, size_t n,
325 struct v4l2_subdev_io_pin_config *pincfg)
326{
327 struct cx25840_state *state = to_state(sd);
328
329 if (is_cx2388x(state))
330 return cx23885_s_io_pin_config(sd, n, pincfg);
331 return 0;
332}
333
334/* ----------------------------------------------------------------------- */
335
336static void init_dll1(struct i2c_client *client)
337{
338 /* This is the Hauppauge sequence used to
339 * initialize the Delay Lock Loop 1 (ADC DLL). */
340 cx25840_write(client, 0x159, 0x23);
341 cx25840_write(client, 0x15a, 0x87);
342 cx25840_write(client, 0x15b, 0x06);
343 udelay(10);
344 cx25840_write(client, 0x159, 0xe1);
345 udelay(10);
346 cx25840_write(client, 0x15a, 0x86);
347 cx25840_write(client, 0x159, 0xe0);
348 cx25840_write(client, 0x159, 0xe1);
349 cx25840_write(client, 0x15b, 0x10);
350}
351
352static void init_dll2(struct i2c_client *client)
353{
354 /* This is the Hauppauge sequence used to
355 * initialize the Delay Lock Loop 2 (ADC DLL). */
356 cx25840_write(client, 0x15d, 0xe3);
357 cx25840_write(client, 0x15e, 0x86);
358 cx25840_write(client, 0x15f, 0x06);
359 udelay(10);
360 cx25840_write(client, 0x15d, 0xe1);
361 cx25840_write(client, 0x15d, 0xe0);
362 cx25840_write(client, 0x15d, 0xe1);
363}
364
365static void cx25836_initialize(struct i2c_client *client)
366{
367 /* reset configuration is described on page 3-77 of the CX25836 datasheet */
368 /* 2. */
369 cx25840_and_or(client, 0x000, ~0x01, 0x01);
370 cx25840_and_or(client, 0x000, ~0x01, 0x00);
371 /* 3a. */
372 cx25840_and_or(client, 0x15a, ~0x70, 0x00);
373 /* 3b. */
374 cx25840_and_or(client, 0x15b, ~0x1e, 0x06);
375 /* 3c. */
376 cx25840_and_or(client, 0x159, ~0x02, 0x02);
377 /* 3d. */
378 udelay(10);
379 /* 3e. */
380 cx25840_and_or(client, 0x159, ~0x02, 0x00);
381 /* 3f. */
382 cx25840_and_or(client, 0x159, ~0xc0, 0xc0);
383 /* 3g. */
384 cx25840_and_or(client, 0x159, ~0x01, 0x00);
385 cx25840_and_or(client, 0x159, ~0x01, 0x01);
386 /* 3h. */
387 cx25840_and_or(client, 0x15b, ~0x1e, 0x10);
388}
389
390static void cx25840_work_handler(struct work_struct *work)
391{
392 struct cx25840_state *state = container_of(work, struct cx25840_state, fw_work);
393 cx25840_loadfw(state->c);
394 wake_up(&state->fw_wait);
395}
396
397static void cx25840_initialize(struct i2c_client *client)
398{
399 DEFINE_WAIT(wait);
400 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
401 struct workqueue_struct *q;
402
403 /* datasheet startup in numbered steps, refer to page 3-77 */
404 /* 2. */
405 cx25840_and_or(client, 0x803, ~0x10, 0x00);
406 /* The default of this register should be 4, but I get 0 instead.
407 * Set this register to 4 manually. */
408 cx25840_write(client, 0x000, 0x04);
409 /* 3. */
410 init_dll1(client);
411 init_dll2(client);
412 cx25840_write(client, 0x136, 0x0a);
413 /* 4. */
414 cx25840_write(client, 0x13c, 0x01);
415 cx25840_write(client, 0x13c, 0x00);
416 /* 5. */
417 /* Do the firmware load in a work handler to prevent.
418 Otherwise the kernel is blocked waiting for the
419 bit-banging i2c interface to finish uploading the
420 firmware. */
421 INIT_WORK(&state->fw_work, cx25840_work_handler);
422 init_waitqueue_head(&state->fw_wait);
423 q = create_singlethread_workqueue("cx25840_fw");
424 prepare_to_wait(&state->fw_wait, &wait, TASK_UNINTERRUPTIBLE);
425 queue_work(q, &state->fw_work);
426 schedule();
427 finish_wait(&state->fw_wait, &wait);
428 destroy_workqueue(q);
429
430 /* 6. */
431 cx25840_write(client, 0x115, 0x8c);
432 cx25840_write(client, 0x116, 0x07);
433 cx25840_write(client, 0x118, 0x02);
434 /* 7. */
435 cx25840_write(client, 0x4a5, 0x80);
436 cx25840_write(client, 0x4a5, 0x00);
437 cx25840_write(client, 0x402, 0x00);
438 /* 8. */
439 cx25840_and_or(client, 0x401, ~0x18, 0);
440 cx25840_and_or(client, 0x4a2, ~0x10, 0x10);
441 /* steps 8c and 8d are done in change_input() */
442 /* 10. */
443 cx25840_write(client, 0x8d3, 0x1f);
444 cx25840_write(client, 0x8e3, 0x03);
445
446 cx25840_std_setup(client);
447
448 /* trial and error says these are needed to get audio */
449 cx25840_write(client, 0x914, 0xa0);
450 cx25840_write(client, 0x918, 0xa0);
451 cx25840_write(client, 0x919, 0x01);
452
453 /* stereo preferred */
454 cx25840_write(client, 0x809, 0x04);
455 /* AC97 shift */
456 cx25840_write(client, 0x8cf, 0x0f);
457
458 /* (re)set input */
459 set_input(client, state->vid_input, state->aud_input);
460
461 /* start microcontroller */
462 cx25840_and_or(client, 0x803, ~0x10, 0x10);
463}
464
465static void cx23885_initialize(struct i2c_client *client)
466{
467 DEFINE_WAIT(wait);
468 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
469 struct workqueue_struct *q;
470
471 /*
472 * Come out of digital power down
473 * The CX23888, at least, needs this, otherwise registers aside from
474 * 0x0-0x2 can't be read or written.
475 */
476 cx25840_write(client, 0x000, 0);
477
478 /* Internal Reset */
479 cx25840_and_or(client, 0x102, ~0x01, 0x01);
480 cx25840_and_or(client, 0x102, ~0x01, 0x00);
481
482 /* Stop microcontroller */
483 cx25840_and_or(client, 0x803, ~0x10, 0x00);
484
485 /* DIF in reset? */
486 cx25840_write(client, 0x398, 0);
487
488 /*
489 * Trust the default xtal, no division
490 * '885: 28.636363... MHz
491 * '887: 25.000000 MHz
492 * '888: 50.000000 MHz
493 */
494 cx25840_write(client, 0x2, 0x76);
495
496 /* Power up all the PLL's and DLL */
497 cx25840_write(client, 0x1, 0x40);
498
499 /* Sys PLL */
500 switch (state->id) {
501 case V4L2_IDENT_CX23888_AV:
502 /*
503 * 50.0 MHz * (0xb + 0xe8ba26/0x2000000)/4 = 5 * 28.636363 MHz
504 * 572.73 MHz before post divide
505 */
506 /* HVR1850 or 50MHz xtal */
507 cx25840_write(client, 0x2, 0x71);
508 cx25840_write4(client, 0x11c, 0x01d1744c);
509 cx25840_write4(client, 0x118, 0x00000416);
510 cx25840_write4(client, 0x404, 0x0010253e);
511 cx25840_write4(client, 0x42c, 0x42600000);
512 cx25840_write4(client, 0x44c, 0x161f1000);
513 break;
514 case V4L2_IDENT_CX23887_AV:
515 /*
516 * 25.0 MHz * (0x16 + 0x1d1744c/0x2000000)/4 = 5 * 28.636363 MHz
517 * 572.73 MHz before post divide
518 */
519 cx25840_write4(client, 0x11c, 0x01d1744c);
520 cx25840_write4(client, 0x118, 0x00000416);
521 break;
522 case V4L2_IDENT_CX23885_AV:
523 default:
524 /*
525 * 28.636363 MHz * (0x14 + 0x0/0x2000000)/4 = 5 * 28.636363 MHz
526 * 572.73 MHz before post divide
527 */
528 cx25840_write4(client, 0x11c, 0x00000000);
529 cx25840_write4(client, 0x118, 0x00000414);
530 break;
531 }
532
533 /* Disable DIF bypass */
534 cx25840_write4(client, 0x33c, 0x00000001);
535
536 /* DIF Src phase inc */
537 cx25840_write4(client, 0x340, 0x0df7df83);
538
539 /*
540 * Vid PLL
541 * Setup for a BT.656 pixel clock of 13.5 Mpixels/second
542 *
543 * 28.636363 MHz * (0xf + 0x02be2c9/0x2000000)/4 = 8 * 13.5 MHz
544 * 432.0 MHz before post divide
545 */
546
547 /* HVR1850 */
548 switch (state->id) {
549 case V4L2_IDENT_CX23888_AV:
550 /* 888/HVR1250 specific */
551 cx25840_write4(client, 0x10c, 0x13333333);
552 cx25840_write4(client, 0x108, 0x00000515);
553 break;
554 default:
555 cx25840_write4(client, 0x10c, 0x002be2c9);
556 cx25840_write4(client, 0x108, 0x0000040f);
557 }
558
559 /* Luma */
560 cx25840_write4(client, 0x414, 0x00107d12);
561
562 /* Chroma */
563 cx25840_write4(client, 0x420, 0x3d008282);
564
565 /*
566 * Aux PLL
567 * Initial setup for audio sample clock:
568 * 48 ksps, 16 bits/sample, x160 multiplier = 122.88 MHz
569 * Initial I2S output/master clock(?):
570 * 48 ksps, 16 bits/sample, x16 multiplier = 12.288 MHz
571 */
572 switch (state->id) {
573 case V4L2_IDENT_CX23888_AV:
574 /*
575 * 50.0 MHz * (0x7 + 0x0bedfa4/0x2000000)/3 = 122.88 MHz
576 * 368.64 MHz before post divide
577 * 122.88 MHz / 0xa = 12.288 MHz
578 */
579 /* HVR1850 or 50MHz xtal */
580 cx25840_write4(client, 0x114, 0x017dbf48);
581 cx25840_write4(client, 0x110, 0x000a030e);
582 break;
583 case V4L2_IDENT_CX23887_AV:
584 /*
585 * 25.0 MHz * (0xe + 0x17dbf48/0x2000000)/3 = 122.88 MHz
586 * 368.64 MHz before post divide
587 * 122.88 MHz / 0xa = 12.288 MHz
588 */
589 cx25840_write4(client, 0x114, 0x017dbf48);
590 cx25840_write4(client, 0x110, 0x000a030e);
591 break;
592 case V4L2_IDENT_CX23885_AV:
593 default:
594 /*
595 * 28.636363 MHz * (0xc + 0x1bf0c9e/0x2000000)/3 = 122.88 MHz
596 * 368.64 MHz before post divide
597 * 122.88 MHz / 0xa = 12.288 MHz
598 */
599 cx25840_write4(client, 0x114, 0x01bf0c9e);
600 cx25840_write4(client, 0x110, 0x000a030c);
601 break;
602 };
603
604 /* ADC2 input select */
605 cx25840_write(client, 0x102, 0x10);
606
607 /* VIN1 & VIN5 */
608 cx25840_write(client, 0x103, 0x11);
609
610 /* Enable format auto detect */
611 cx25840_write(client, 0x400, 0);
612 /* Fast subchroma lock */
613 /* White crush, Chroma AGC & Chroma Killer enabled */
614 cx25840_write(client, 0x401, 0xe8);
615
616 /* Select AFE clock pad output source */
617 cx25840_write(client, 0x144, 0x05);
618
619 /* Drive GPIO2 direction and values for HVR1700
620 * where an onboard mux selects the output of demodulator
621 * vs the 417. Failure to set this results in no DTV.
622 * It's safe to set this across all Hauppauge boards
623 * currently, regardless of the board type.
624 */
625 cx25840_write(client, 0x160, 0x1d);
626 cx25840_write(client, 0x164, 0x00);
627
628 /* Do the firmware load in a work handler to prevent.
629 Otherwise the kernel is blocked waiting for the
630 bit-banging i2c interface to finish uploading the
631 firmware. */
632 INIT_WORK(&state->fw_work, cx25840_work_handler);
633 init_waitqueue_head(&state->fw_wait);
634 q = create_singlethread_workqueue("cx25840_fw");
635 prepare_to_wait(&state->fw_wait, &wait, TASK_UNINTERRUPTIBLE);
636 queue_work(q, &state->fw_work);
637 schedule();
638 finish_wait(&state->fw_wait, &wait);
639 destroy_workqueue(q);
640
641 /* Call the cx23888 specific std setup func, we no longer rely on
642 * the generic cx24840 func.
643 */
644 if (is_cx23888(state))
645 cx23888_std_setup(client);
646 else
647 cx25840_std_setup(client);
648
649 /* (re)set input */
650 set_input(client, state->vid_input, state->aud_input);
651
652 /* start microcontroller */
653 cx25840_and_or(client, 0x803, ~0x10, 0x10);
654
655 /* Disable and clear video interrupts - we don't use them */
656 cx25840_write4(client, CX25840_VID_INT_STAT_REG, 0xffffffff);
657
658 /* Disable and clear audio interrupts - we don't use them */
659 cx25840_write(client, CX25840_AUD_INT_CTRL_REG, 0xff);
660 cx25840_write(client, CX25840_AUD_INT_STAT_REG, 0xff);
661
662 /* CC raw enable */
663 /* - VIP 1.1 control codes - 10bit, blue field enable.
664 * - enable raw data during vertical blanking.
665 * - enable ancillary Data insertion for 656 or VIP.
666 */
667 cx25840_write4(client, 0x404, 0x0010253e);
668
669 /* CC on - Undocumented Register */
670 cx25840_write(client, 0x42f, 0x66);
671
672 /* HVR-1250 / HVR1850 DIF related */
673 /* Power everything up */
674 cx25840_write4(client, 0x130, 0x0);
675
676 /* Undocumented */
677 cx25840_write4(client, 0x478, 0x6628021F);
678
679 /* AFE_CLK_OUT_CTRL - Select the clock output source as output */
680 cx25840_write4(client, 0x144, 0x5);
681
682 /* I2C_OUT_CTL - I2S output configuration as
683 * Master, Sony, Left justified, left sample on WS=1
684 */
685 cx25840_write4(client, 0x918, 0x1a0);
686
687 /* AFE_DIAG_CTRL1 */
688 cx25840_write4(client, 0x134, 0x000a1800);
689
690 /* AFE_DIAG_CTRL3 - Inverted Polarity for Audio and Video */
691 cx25840_write4(client, 0x13c, 0x00310000);
692}
693
694/* ----------------------------------------------------------------------- */
695
696static void cx231xx_initialize(struct i2c_client *client)
697{
698 DEFINE_WAIT(wait);
699 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
700 struct workqueue_struct *q;
701
702 /* Internal Reset */
703 cx25840_and_or(client, 0x102, ~0x01, 0x01);
704 cx25840_and_or(client, 0x102, ~0x01, 0x00);
705
706 /* Stop microcontroller */
707 cx25840_and_or(client, 0x803, ~0x10, 0x00);
708
709 /* DIF in reset? */
710 cx25840_write(client, 0x398, 0);
711
712 /* Trust the default xtal, no division */
713 /* This changes for the cx23888 products */
714 cx25840_write(client, 0x2, 0x76);
715
716 /* Bring down the regulator for AUX clk */
717 cx25840_write(client, 0x1, 0x40);
718
719 /* Disable DIF bypass */
720 cx25840_write4(client, 0x33c, 0x00000001);
721
722 /* DIF Src phase inc */
723 cx25840_write4(client, 0x340, 0x0df7df83);
724
725 /* Luma */
726 cx25840_write4(client, 0x414, 0x00107d12);
727
728 /* Chroma */
729 cx25840_write4(client, 0x420, 0x3d008282);
730
731 /* ADC2 input select */
732 cx25840_write(client, 0x102, 0x10);
733
734 /* VIN1 & VIN5 */
735 cx25840_write(client, 0x103, 0x11);
736
737 /* Enable format auto detect */
738 cx25840_write(client, 0x400, 0);
739 /* Fast subchroma lock */
740 /* White crush, Chroma AGC & Chroma Killer enabled */
741 cx25840_write(client, 0x401, 0xe8);
742
743 /* Do the firmware load in a work handler to prevent.
744 Otherwise the kernel is blocked waiting for the
745 bit-banging i2c interface to finish uploading the
746 firmware. */
747 INIT_WORK(&state->fw_work, cx25840_work_handler);
748 init_waitqueue_head(&state->fw_wait);
749 q = create_singlethread_workqueue("cx25840_fw");
750 prepare_to_wait(&state->fw_wait, &wait, TASK_UNINTERRUPTIBLE);
751 queue_work(q, &state->fw_work);
752 schedule();
753 finish_wait(&state->fw_wait, &wait);
754 destroy_workqueue(q);
755
756 cx25840_std_setup(client);
757
758 /* (re)set input */
759 set_input(client, state->vid_input, state->aud_input);
760
761 /* start microcontroller */
762 cx25840_and_or(client, 0x803, ~0x10, 0x10);
763
764 /* CC raw enable */
765 cx25840_write(client, 0x404, 0x0b);
766
767 /* CC on */
768 cx25840_write(client, 0x42f, 0x66);
769 cx25840_write4(client, 0x474, 0x1e1e601a);
770}
771
772/* ----------------------------------------------------------------------- */
773
774void cx25840_std_setup(struct i2c_client *client)
775{
776 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
777 v4l2_std_id std = state->std;
778 int hblank, hactive, burst, vblank, vactive, sc;
779 int vblank656, src_decimation;
780 int luma_lpf, uv_lpf, comb;
781 u32 pll_int, pll_frac, pll_post;
782
783 /* datasheet startup, step 8d */
784 if (std & ~V4L2_STD_NTSC)
785 cx25840_write(client, 0x49f, 0x11);
786 else
787 cx25840_write(client, 0x49f, 0x14);
788
789 if (std & V4L2_STD_625_50) {
790 hblank = 132;
791 hactive = 720;
792 burst = 93;
793 vblank = 36;
794 vactive = 580;
795 vblank656 = 40;
796 src_decimation = 0x21f;
797 luma_lpf = 2;
798
799 if (std & V4L2_STD_SECAM) {
800 uv_lpf = 0;
801 comb = 0;
802 sc = 0x0a425f;
803 } else if (std == V4L2_STD_PAL_Nc) {
804 uv_lpf = 1;
805 comb = 0x20;
806 sc = 556453;
807 } else {
808 uv_lpf = 1;
809 comb = 0x20;
810 sc = 688739;
811 }
812 } else {
813 hactive = 720;
814 hblank = 122;
815 vactive = 487;
816 luma_lpf = 1;
817 uv_lpf = 1;
818
819 src_decimation = 0x21f;
820 if (std == V4L2_STD_PAL_60) {
821 vblank = 26;
822 vblank656 = 26;
823 burst = 0x5b;
824 luma_lpf = 2;
825 comb = 0x20;
826 sc = 688739;
827 } else if (std == V4L2_STD_PAL_M) {
828 vblank = 20;
829 vblank656 = 24;
830 burst = 0x61;
831 comb = 0x20;
832 sc = 555452;
833 } else {
834 vblank = 26;
835 vblank656 = 26;
836 burst = 0x5b;
837 comb = 0x66;
838 sc = 556063;
839 }
840 }
841
842 /* DEBUG: Displays configured PLL frequency */
843 if (!is_cx231xx(state)) {
844 pll_int = cx25840_read(client, 0x108);
845 pll_frac = cx25840_read4(client, 0x10c) & 0x1ffffff;
846 pll_post = cx25840_read(client, 0x109);
847 v4l_dbg(1, cx25840_debug, client,
848 "PLL regs = int: %u, frac: %u, post: %u\n",
849 pll_int, pll_frac, pll_post);
850
851 if (pll_post) {
852 int fin, fsc;
853 int pll = (28636363L * ((((u64)pll_int) << 25L) + pll_frac)) >> 25L;
854
855 pll /= pll_post;
856 v4l_dbg(1, cx25840_debug, client, "PLL = %d.%06d MHz\n",
857 pll / 1000000, pll % 1000000);
858 v4l_dbg(1, cx25840_debug, client, "PLL/8 = %d.%06d MHz\n",
859 pll / 8000000, (pll / 8) % 1000000);
860
861 fin = ((u64)src_decimation * pll) >> 12;
862 v4l_dbg(1, cx25840_debug, client,
863 "ADC Sampling freq = %d.%06d MHz\n",
864 fin / 1000000, fin % 1000000);
865
866 fsc = (((u64)sc) * pll) >> 24L;
867 v4l_dbg(1, cx25840_debug, client,
868 "Chroma sub-carrier freq = %d.%06d MHz\n",
869 fsc / 1000000, fsc % 1000000);
870
871 v4l_dbg(1, cx25840_debug, client, "hblank %i, hactive %i, "
872 "vblank %i, vactive %i, vblank656 %i, src_dec %i, "
873 "burst 0x%02x, luma_lpf %i, uv_lpf %i, comb 0x%02x, "
874 "sc 0x%06x\n",
875 hblank, hactive, vblank, vactive, vblank656,
876 src_decimation, burst, luma_lpf, uv_lpf, comb, sc);
877 }
878 }
879
880 /* Sets horizontal blanking delay and active lines */
881 cx25840_write(client, 0x470, hblank);
882 cx25840_write(client, 0x471,
883 0xff & (((hblank >> 8) & 0x3) | (hactive << 4)));
884 cx25840_write(client, 0x472, hactive >> 4);
885
886 /* Sets burst gate delay */
887 cx25840_write(client, 0x473, burst);
888
889 /* Sets vertical blanking delay and active duration */
890 cx25840_write(client, 0x474, vblank);
891 cx25840_write(client, 0x475,
892 0xff & (((vblank >> 8) & 0x3) | (vactive << 4)));
893 cx25840_write(client, 0x476, vactive >> 4);
894 cx25840_write(client, 0x477, vblank656);
895
896 /* Sets src decimation rate */
897 cx25840_write(client, 0x478, 0xff & src_decimation);
898 cx25840_write(client, 0x479, 0xff & (src_decimation >> 8));
899
900 /* Sets Luma and UV Low pass filters */
901 cx25840_write(client, 0x47a, luma_lpf << 6 | ((uv_lpf << 4) & 0x30));
902
903 /* Enables comb filters */
904 cx25840_write(client, 0x47b, comb);
905
906 /* Sets SC Step*/
907 cx25840_write(client, 0x47c, sc);
908 cx25840_write(client, 0x47d, 0xff & sc >> 8);
909 cx25840_write(client, 0x47e, 0xff & sc >> 16);
910
911 /* Sets VBI parameters */
912 if (std & V4L2_STD_625_50) {
913 cx25840_write(client, 0x47f, 0x01);
914 state->vbi_line_offset = 5;
915 } else {
916 cx25840_write(client, 0x47f, 0x00);
917 state->vbi_line_offset = 8;
918 }
919}
920
921/* ----------------------------------------------------------------------- */
922
923static void input_change(struct i2c_client *client)
924{
925 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
926 v4l2_std_id std = state->std;
927
928 /* Follow step 8c and 8d of section 3.16 in the cx25840 datasheet */
929 if (std & V4L2_STD_SECAM) {
930 cx25840_write(client, 0x402, 0);
931 }
932 else {
933 cx25840_write(client, 0x402, 0x04);
934 cx25840_write(client, 0x49f, (std & V4L2_STD_NTSC) ? 0x14 : 0x11);
935 }
936 cx25840_and_or(client, 0x401, ~0x60, 0);
937 cx25840_and_or(client, 0x401, ~0x60, 0x60);
938
939 /* Don't write into audio registers on cx2583x chips */
940 if (is_cx2583x(state))
941 return;
942
943 cx25840_and_or(client, 0x810, ~0x01, 1);
944
945 if (state->radio) {
946 cx25840_write(client, 0x808, 0xf9);
947 cx25840_write(client, 0x80b, 0x00);
948 }
949 else if (std & V4L2_STD_525_60) {
950 /* Certain Hauppauge PVR150 models have a hardware bug
951 that causes audio to drop out. For these models the
952 audio standard must be set explicitly.
953 To be precise: it affects cards with tuner models
954 85, 99 and 112 (model numbers from tveeprom). */
955 int hw_fix = state->pvr150_workaround;
956
957 if (std == V4L2_STD_NTSC_M_JP) {
958 /* Japan uses EIAJ audio standard */
959 cx25840_write(client, 0x808, hw_fix ? 0x2f : 0xf7);
960 } else if (std == V4L2_STD_NTSC_M_KR) {
961 /* South Korea uses A2 audio standard */
962 cx25840_write(client, 0x808, hw_fix ? 0x3f : 0xf8);
963 } else {
964 /* Others use the BTSC audio standard */
965 cx25840_write(client, 0x808, hw_fix ? 0x1f : 0xf6);
966 }
967 cx25840_write(client, 0x80b, 0x00);
968 } else if (std & V4L2_STD_PAL) {
969 /* Autodetect audio standard and audio system */
970 cx25840_write(client, 0x808, 0xff);
971 /* Since system PAL-L is pretty much non-existent and
972 not used by any public broadcast network, force
973 6.5 MHz carrier to be interpreted as System DK,
974 this avoids DK audio detection instability */
975 cx25840_write(client, 0x80b, 0x00);
976 } else if (std & V4L2_STD_SECAM) {
977 /* Autodetect audio standard and audio system */
978 cx25840_write(client, 0x808, 0xff);
979 /* If only one of SECAM-DK / SECAM-L is required, then force
980 6.5MHz carrier, else autodetect it */
981 if ((std & V4L2_STD_SECAM_DK) &&
982 !(std & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC))) {
983 /* 6.5 MHz carrier to be interpreted as System DK */
984 cx25840_write(client, 0x80b, 0x00);
985 } else if (!(std & V4L2_STD_SECAM_DK) &&
986 (std & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC))) {
987 /* 6.5 MHz carrier to be interpreted as System L */
988 cx25840_write(client, 0x80b, 0x08);
989 } else {
990 /* 6.5 MHz carrier to be autodetected */
991 cx25840_write(client, 0x80b, 0x10);
992 }
993 }
994
995 cx25840_and_or(client, 0x810, ~0x01, 0);
996}
997
998static int set_input(struct i2c_client *client, enum cx25840_video_input vid_input,
999 enum cx25840_audio_input aud_input)
1000{
1001 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
1002 u8 is_composite = (vid_input >= CX25840_COMPOSITE1 &&
1003 vid_input <= CX25840_COMPOSITE8);
1004 u8 is_component = (vid_input & CX25840_COMPONENT_ON) ==
1005 CX25840_COMPONENT_ON;
1006 u8 is_dif = (vid_input & CX25840_DIF_ON) ==
1007 CX25840_DIF_ON;
1008 u8 is_svideo = (vid_input & CX25840_SVIDEO_ON) ==
1009 CX25840_SVIDEO_ON;
1010 int luma = vid_input & 0xf0;
1011 int chroma = vid_input & 0xf00;
1012 u8 reg;
1013 u32 val;
1014
1015 v4l_dbg(1, cx25840_debug, client,
1016 "decoder set video input %d, audio input %d\n",
1017 vid_input, aud_input);
1018
1019 if (vid_input >= CX25840_VIN1_CH1) {
1020 v4l_dbg(1, cx25840_debug, client, "vid_input 0x%x\n",
1021 vid_input);
1022 reg = vid_input & 0xff;
1023 is_composite = !is_component &&
1024 ((vid_input & CX25840_SVIDEO_ON) != CX25840_SVIDEO_ON);
1025
1026 v4l_dbg(1, cx25840_debug, client, "mux cfg 0x%x comp=%d\n",
1027 reg, is_composite);
1028 } else if (is_composite) {
1029 reg = 0xf0 + (vid_input - CX25840_COMPOSITE1);
1030 } else {
1031 if ((vid_input & ~0xff0) ||
1032 luma < CX25840_SVIDEO_LUMA1 || luma > CX25840_SVIDEO_LUMA8 ||
1033 chroma < CX25840_SVIDEO_CHROMA4 || chroma > CX25840_SVIDEO_CHROMA8) {
1034 v4l_err(client, "0x%04x is not a valid video input!\n",
1035 vid_input);
1036 return -EINVAL;
1037 }
1038 reg = 0xf0 + ((luma - CX25840_SVIDEO_LUMA1) >> 4);
1039 if (chroma >= CX25840_SVIDEO_CHROMA7) {
1040 reg &= 0x3f;
1041 reg |= (chroma - CX25840_SVIDEO_CHROMA7) >> 2;
1042 } else {
1043 reg &= 0xcf;
1044 reg |= (chroma - CX25840_SVIDEO_CHROMA4) >> 4;
1045 }
1046 }
1047
1048 /* The caller has previously prepared the correct routing
1049 * configuration in reg (for the cx23885) so we have no
1050 * need to attempt to flip bits for earlier av decoders.
1051 */
1052 if (!is_cx2388x(state) && !is_cx231xx(state)) {
1053 switch (aud_input) {
1054 case CX25840_AUDIO_SERIAL:
1055 /* do nothing, use serial audio input */
1056 break;
1057 case CX25840_AUDIO4: reg &= ~0x30; break;
1058 case CX25840_AUDIO5: reg &= ~0x30; reg |= 0x10; break;
1059 case CX25840_AUDIO6: reg &= ~0x30; reg |= 0x20; break;
1060 case CX25840_AUDIO7: reg &= ~0xc0; break;
1061 case CX25840_AUDIO8: reg &= ~0xc0; reg |= 0x40; break;
1062
1063 default:
1064 v4l_err(client, "0x%04x is not a valid audio input!\n",
1065 aud_input);
1066 return -EINVAL;
1067 }
1068 }
1069
1070 cx25840_write(client, 0x103, reg);
1071
1072 /* Set INPUT_MODE to Composite, S-Video or Component */
1073 if (is_component)
1074 cx25840_and_or(client, 0x401, ~0x6, 0x6);
1075 else
1076 cx25840_and_or(client, 0x401, ~0x6, is_composite ? 0 : 0x02);
1077
1078 if (is_cx2388x(state)) {
1079
1080 /* Enable or disable the DIF for tuner use */
1081 if (is_dif) {
1082 cx25840_and_or(client, 0x102, ~0x80, 0x80);
1083
1084 /* Set of defaults for NTSC and PAL */
1085 cx25840_write4(client, 0x31c, 0xc2262600);
1086 cx25840_write4(client, 0x320, 0xc2262600);
1087
1088 /* 18271 IF - Nobody else yet uses a different
1089 * tuner with the DIF, so these are reasonable
1090 * assumptions (HVR1250 and HVR1850 specific).
1091 */
1092 cx25840_write4(client, 0x318, 0xda262600);
1093 cx25840_write4(client, 0x33c, 0x2a24c800);
1094 cx25840_write4(client, 0x104, 0x0704dd00);
1095 } else {
1096 cx25840_write4(client, 0x300, 0x015c28f5);
1097
1098 cx25840_and_or(client, 0x102, ~0x80, 0);
1099 cx25840_write4(client, 0x340, 0xdf7df83);
1100 cx25840_write4(client, 0x104, 0x0704dd80);
1101 cx25840_write4(client, 0x314, 0x22400600);
1102 cx25840_write4(client, 0x318, 0x40002600);
1103 cx25840_write4(client, 0x324, 0x40002600);
1104 cx25840_write4(client, 0x32c, 0x0250e620);
1105 cx25840_write4(client, 0x39c, 0x01FF0B00);
1106
1107 cx25840_write4(client, 0x410, 0xffff0dbf);
1108 cx25840_write4(client, 0x414, 0x00137d03);
1109
1110 /* on the 887, 0x418 is HSCALE_CTRL, on the 888 it is
1111 CHROMA_CTRL */
1112 if (is_cx23888(state))
1113 cx25840_write4(client, 0x418, 0x01008080);
1114 else
1115 cx25840_write4(client, 0x418, 0x01000000);
1116
1117 cx25840_write4(client, 0x41c, 0x00000000);
1118
1119 /* on the 887, 0x420 is CHROMA_CTRL, on the 888 it is
1120 CRUSH_CTRL */
1121 if (is_cx23888(state))
1122 cx25840_write4(client, 0x420, 0x001c3e0f);
1123 else
1124 cx25840_write4(client, 0x420, 0x001c8282);
1125
1126 cx25840_write4(client, 0x42c, 0x42600000);
1127 cx25840_write4(client, 0x430, 0x0000039b);
1128 cx25840_write4(client, 0x438, 0x00000000);
1129
1130 cx25840_write4(client, 0x440, 0xF8E3E824);
1131 cx25840_write4(client, 0x444, 0x401040dc);
1132 cx25840_write4(client, 0x448, 0xcd3f02a0);
1133 cx25840_write4(client, 0x44c, 0x161f1000);
1134 cx25840_write4(client, 0x450, 0x00000802);
1135
1136 cx25840_write4(client, 0x91c, 0x01000000);
1137 cx25840_write4(client, 0x8e0, 0x03063870);
1138 cx25840_write4(client, 0x8d4, 0x7FFF0024);
1139 cx25840_write4(client, 0x8d0, 0x00063073);
1140
1141 cx25840_write4(client, 0x8c8, 0x00010000);
1142 cx25840_write4(client, 0x8cc, 0x00080023);
1143
1144 /* DIF BYPASS */
1145 cx25840_write4(client, 0x33c, 0x2a04c800);
1146 }
1147
1148 /* Reset the DIF */
1149 cx25840_write4(client, 0x398, 0);
1150 }
1151
1152 if (!is_cx2388x(state) && !is_cx231xx(state)) {
1153 /* Set CH_SEL_ADC2 to 1 if input comes from CH3 */
1154 cx25840_and_or(client, 0x102, ~0x2, (reg & 0x80) == 0 ? 2 : 0);
1155 /* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2&CH3 */
1156 if ((reg & 0xc0) != 0xc0 && (reg & 0x30) != 0x30)
1157 cx25840_and_or(client, 0x102, ~0x4, 4);
1158 else
1159 cx25840_and_or(client, 0x102, ~0x4, 0);
1160 } else {
1161 /* Set DUAL_MODE_ADC2 to 1 if component*/
1162 cx25840_and_or(client, 0x102, ~0x4, is_component ? 0x4 : 0x0);
1163 if (is_composite) {
1164 /* ADC2 input select channel 2 */
1165 cx25840_and_or(client, 0x102, ~0x2, 0);
1166 } else if (!is_component) {
1167 /* S-Video */
1168 if (chroma >= CX25840_SVIDEO_CHROMA7) {
1169 /* ADC2 input select channel 3 */
1170 cx25840_and_or(client, 0x102, ~0x2, 2);
1171 } else {
1172 /* ADC2 input select channel 2 */
1173 cx25840_and_or(client, 0x102, ~0x2, 0);
1174 }
1175 }
1176
1177 /* cx23885 / SVIDEO */
1178 if (is_cx2388x(state) && is_svideo) {
1179#define AFE_CTRL (0x104)
1180#define MODE_CTRL (0x400)
1181 cx25840_and_or(client, 0x102, ~0x2, 0x2);
1182
1183 val = cx25840_read4(client, MODE_CTRL);
1184 val &= 0xFFFFF9FF;
1185
1186 /* YC */
1187 val |= 0x00000200;
1188 val &= ~0x2000;
1189 cx25840_write4(client, MODE_CTRL, val);
1190
1191 val = cx25840_read4(client, AFE_CTRL);
1192
1193 /* Chroma in select */
1194 val |= 0x00001000;
1195 val &= 0xfffffe7f;
1196 /* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8).
1197 * This sets them to use video rather than audio.
1198 * Only one of the two will be in use.
1199 */
1200 cx25840_write4(client, AFE_CTRL, val);
1201 } else
1202 cx25840_and_or(client, 0x102, ~0x2, 0);
1203 }
1204
1205 state->vid_input = vid_input;
1206 state->aud_input = aud_input;
1207 cx25840_audio_set_path(client);
1208 input_change(client);
1209
1210 if (is_cx2388x(state)) {
1211 /* Audio channel 1 src : Parallel 1 */
1212 cx25840_write(client, 0x124, 0x03);
1213
1214 /* Select AFE clock pad output source */
1215 cx25840_write(client, 0x144, 0x05);
1216
1217 /* I2S_IN_CTL: I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1 */
1218 cx25840_write(client, 0x914, 0xa0);
1219
1220 /* I2S_OUT_CTL:
1221 * I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1
1222 * I2S_OUT_MASTER_MODE = Master
1223 */
1224 cx25840_write(client, 0x918, 0xa0);
1225 cx25840_write(client, 0x919, 0x01);
1226 } else if (is_cx231xx(state)) {
1227 /* Audio channel 1 src : Parallel 1 */
1228 cx25840_write(client, 0x124, 0x03);
1229
1230 /* I2S_IN_CTL: I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1 */
1231 cx25840_write(client, 0x914, 0xa0);
1232
1233 /* I2S_OUT_CTL:
1234 * I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1
1235 * I2S_OUT_MASTER_MODE = Master
1236 */
1237 cx25840_write(client, 0x918, 0xa0);
1238 cx25840_write(client, 0x919, 0x01);
1239 }
1240
1241 if (is_cx2388x(state) && ((aud_input == CX25840_AUDIO7) ||
1242 (aud_input == CX25840_AUDIO6))) {
1243 /* Configure audio from LR1 or LR2 input */
1244 cx25840_write4(client, 0x910, 0);
1245 cx25840_write4(client, 0x8d0, 0x63073);
1246 } else
1247 if (is_cx2388x(state) && (aud_input == CX25840_AUDIO8)) {
1248 /* Configure audio from tuner/sif input */
1249 cx25840_write4(client, 0x910, 0x12b000c9);
1250 cx25840_write4(client, 0x8d0, 0x1f063870);
1251 }
1252
1253 if (is_cx23888(state)) {
1254 /* HVR1850 */
1255 /* AUD_IO_CTRL - I2S Input, Parallel1*/
1256 /* - Channel 1 src - Parallel1 (Merlin out) */
1257 /* - Channel 2 src - Parallel2 (Merlin out) */
1258 /* - Channel 3 src - Parallel3 (Merlin AC97 out) */
1259 /* - I2S source and dir - Merlin, output */
1260 cx25840_write4(client, 0x124, 0x100);
1261
1262 if (!is_dif) {
1263 /* Stop microcontroller if we don't need it
1264 * to avoid audio popping on svideo/composite use.
1265 */
1266 cx25840_and_or(client, 0x803, ~0x10, 0x00);
1267 }
1268 }
1269
1270 return 0;
1271}
1272
1273/* ----------------------------------------------------------------------- */
1274
1275static int set_v4lstd(struct i2c_client *client)
1276{
1277 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
1278 u8 fmt = 0; /* zero is autodetect */
1279 u8 pal_m = 0;
1280
1281 /* First tests should be against specific std */
1282 if (state->std == V4L2_STD_NTSC_M_JP) {
1283 fmt = 0x2;
1284 } else if (state->std == V4L2_STD_NTSC_443) {
1285 fmt = 0x3;
1286 } else if (state->std == V4L2_STD_PAL_M) {
1287 pal_m = 1;
1288 fmt = 0x5;
1289 } else if (state->std == V4L2_STD_PAL_N) {
1290 fmt = 0x6;
1291 } else if (state->std == V4L2_STD_PAL_Nc) {
1292 fmt = 0x7;
1293 } else if (state->std == V4L2_STD_PAL_60) {
1294 fmt = 0x8;
1295 } else {
1296 /* Then, test against generic ones */
1297 if (state->std & V4L2_STD_NTSC)
1298 fmt = 0x1;
1299 else if (state->std & V4L2_STD_PAL)
1300 fmt = 0x4;
1301 else if (state->std & V4L2_STD_SECAM)
1302 fmt = 0xc;
1303 }
1304
1305 v4l_dbg(1, cx25840_debug, client, "changing video std to fmt %i\n",fmt);
1306
1307 /* Follow step 9 of section 3.16 in the cx25840 datasheet.
1308 Without this PAL may display a vertical ghosting effect.
1309 This happens for example with the Yuan MPC622. */
1310 if (fmt >= 4 && fmt < 8) {
1311 /* Set format to NTSC-M */
1312 cx25840_and_or(client, 0x400, ~0xf, 1);
1313 /* Turn off LCOMB */
1314 cx25840_and_or(client, 0x47b, ~6, 0);
1315 }
1316 cx25840_and_or(client, 0x400, ~0xf, fmt);
1317 cx25840_and_or(client, 0x403, ~0x3, pal_m);
1318 if (is_cx23888(state))
1319 cx23888_std_setup(client);
1320 else
1321 cx25840_std_setup(client);
1322 if (!is_cx2583x(state))
1323 input_change(client);
1324 return 0;
1325}
1326
1327/* ----------------------------------------------------------------------- */
1328
1329static int cx25840_s_ctrl(struct v4l2_ctrl *ctrl)
1330{
1331 struct v4l2_subdev *sd = to_sd(ctrl);
1332 struct cx25840_state *state = to_state(sd);
1333 struct i2c_client *client = v4l2_get_subdevdata(sd);
1334
1335 switch (ctrl->id) {
1336 case V4L2_CID_BRIGHTNESS:
1337 cx25840_write(client, 0x414, ctrl->val - 128);
1338 break;
1339
1340 case V4L2_CID_CONTRAST:
1341 cx25840_write(client, 0x415, ctrl->val << 1);
1342 break;
1343
1344 case V4L2_CID_SATURATION:
1345 if (is_cx23888(state)) {
1346 cx25840_write(client, 0x418, ctrl->val << 1);
1347 cx25840_write(client, 0x419, ctrl->val << 1);
1348 } else {
1349 cx25840_write(client, 0x420, ctrl->val << 1);
1350 cx25840_write(client, 0x421, ctrl->val << 1);
1351 }
1352 break;
1353
1354 case V4L2_CID_HUE:
1355 if (is_cx23888(state))
1356 cx25840_write(client, 0x41a, ctrl->val);
1357 else
1358 cx25840_write(client, 0x422, ctrl->val);
1359 break;
1360
1361 default:
1362 return -EINVAL;
1363 }
1364
1365 return 0;
1366}
1367
1368/* ----------------------------------------------------------------------- */
1369
1370static int cx25840_s_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *fmt)
1371{
1372 struct cx25840_state *state = to_state(sd);
1373 struct i2c_client *client = v4l2_get_subdevdata(sd);
1374 int HSC, VSC, Vsrc, Hsrc, filter, Vlines;
1375 int is_50Hz = !(state->std & V4L2_STD_525_60);
1376
1377 if (fmt->code != V4L2_MBUS_FMT_FIXED)
1378 return -EINVAL;
1379
1380 fmt->field = V4L2_FIELD_INTERLACED;
1381 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
1382
1383 if (is_cx23888(state)) {
1384 Vsrc = (cx25840_read(client, 0x42a) & 0x3f) << 4;
1385 Vsrc |= (cx25840_read(client, 0x429) & 0xf0) >> 4;
1386 } else {
1387 Vsrc = (cx25840_read(client, 0x476) & 0x3f) << 4;
1388 Vsrc |= (cx25840_read(client, 0x475) & 0xf0) >> 4;
1389 }
1390
1391 if (is_cx23888(state)) {
1392 Hsrc = (cx25840_read(client, 0x426) & 0x3f) << 4;
1393 Hsrc |= (cx25840_read(client, 0x425) & 0xf0) >> 4;
1394 } else {
1395 Hsrc = (cx25840_read(client, 0x472) & 0x3f) << 4;
1396 Hsrc |= (cx25840_read(client, 0x471) & 0xf0) >> 4;
1397 }
1398
1399 Vlines = fmt->height + (is_50Hz ? 4 : 7);
1400
1401 if ((fmt->width * 16 < Hsrc) || (Hsrc < fmt->width) ||
1402 (Vlines * 8 < Vsrc) || (Vsrc < Vlines)) {
1403 v4l_err(client, "%dx%d is not a valid size!\n",
1404 fmt->width, fmt->height);
1405 return -ERANGE;
1406 }
1407
1408 HSC = (Hsrc * (1 << 20)) / fmt->width - (1 << 20);
1409 VSC = (1 << 16) - (Vsrc * (1 << 9) / Vlines - (1 << 9));
1410 VSC &= 0x1fff;
1411
1412 if (fmt->width >= 385)
1413 filter = 0;
1414 else if (fmt->width > 192)
1415 filter = 1;
1416 else if (fmt->width > 96)
1417 filter = 2;
1418 else
1419 filter = 3;
1420
1421 v4l_dbg(1, cx25840_debug, client, "decoder set size %dx%d -> scale %ux%u\n",
1422 fmt->width, fmt->height, HSC, VSC);
1423
1424 /* HSCALE=HSC */
1425 cx25840_write(client, 0x418, HSC & 0xff);
1426 cx25840_write(client, 0x419, (HSC >> 8) & 0xff);
1427 cx25840_write(client, 0x41a, HSC >> 16);
1428 /* VSCALE=VSC */
1429 cx25840_write(client, 0x41c, VSC & 0xff);
1430 cx25840_write(client, 0x41d, VSC >> 8);
1431 /* VS_INTRLACE=1 VFILT=filter */
1432 cx25840_write(client, 0x41e, 0x8 | filter);
1433 return 0;
1434}
1435
1436/* ----------------------------------------------------------------------- */
1437
1438static void log_video_status(struct i2c_client *client)
1439{
1440 static const char *const fmt_strs[] = {
1441 "0x0",
1442 "NTSC-M", "NTSC-J", "NTSC-4.43",
1443 "PAL-BDGHI", "PAL-M", "PAL-N", "PAL-Nc", "PAL-60",
1444 "0x9", "0xA", "0xB",
1445 "SECAM",
1446 "0xD", "0xE", "0xF"
1447 };
1448
1449 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
1450 u8 vidfmt_sel = cx25840_read(client, 0x400) & 0xf;
1451 u8 gen_stat1 = cx25840_read(client, 0x40d);
1452 u8 gen_stat2 = cx25840_read(client, 0x40e);
1453 int vid_input = state->vid_input;
1454
1455 v4l_info(client, "Video signal: %spresent\n",
1456 (gen_stat2 & 0x20) ? "" : "not ");
1457 v4l_info(client, "Detected format: %s\n",
1458 fmt_strs[gen_stat1 & 0xf]);
1459
1460 v4l_info(client, "Specified standard: %s\n",
1461 vidfmt_sel ? fmt_strs[vidfmt_sel] : "automatic detection");
1462
1463 if (vid_input >= CX25840_COMPOSITE1 &&
1464 vid_input <= CX25840_COMPOSITE8) {
1465 v4l_info(client, "Specified video input: Composite %d\n",
1466 vid_input - CX25840_COMPOSITE1 + 1);
1467 } else {
1468 v4l_info(client, "Specified video input: S-Video (Luma In%d, Chroma In%d)\n",
1469 (vid_input & 0xf0) >> 4, (vid_input & 0xf00) >> 8);
1470 }
1471
1472 v4l_info(client, "Specified audioclock freq: %d Hz\n", state->audclk_freq);
1473}
1474
1475/* ----------------------------------------------------------------------- */
1476
1477static void log_audio_status(struct i2c_client *client)
1478{
1479 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
1480 u8 download_ctl = cx25840_read(client, 0x803);
1481 u8 mod_det_stat0 = cx25840_read(client, 0x804);
1482 u8 mod_det_stat1 = cx25840_read(client, 0x805);
1483 u8 audio_config = cx25840_read(client, 0x808);
1484 u8 pref_mode = cx25840_read(client, 0x809);
1485 u8 afc0 = cx25840_read(client, 0x80b);
1486 u8 mute_ctl = cx25840_read(client, 0x8d3);
1487 int aud_input = state->aud_input;
1488 char *p;
1489
1490 switch (mod_det_stat0) {
1491 case 0x00: p = "mono"; break;
1492 case 0x01: p = "stereo"; break;
1493 case 0x02: p = "dual"; break;
1494 case 0x04: p = "tri"; break;
1495 case 0x10: p = "mono with SAP"; break;
1496 case 0x11: p = "stereo with SAP"; break;
1497 case 0x12: p = "dual with SAP"; break;
1498 case 0x14: p = "tri with SAP"; break;
1499 case 0xfe: p = "forced mode"; break;
1500 default: p = "not defined";
1501 }
1502 v4l_info(client, "Detected audio mode: %s\n", p);
1503
1504 switch (mod_det_stat1) {
1505 case 0x00: p = "not defined"; break;
1506 case 0x01: p = "EIAJ"; break;
1507 case 0x02: p = "A2-M"; break;
1508 case 0x03: p = "A2-BG"; break;
1509 case 0x04: p = "A2-DK1"; break;
1510 case 0x05: p = "A2-DK2"; break;
1511 case 0x06: p = "A2-DK3"; break;
1512 case 0x07: p = "A1 (6.0 MHz FM Mono)"; break;
1513 case 0x08: p = "AM-L"; break;
1514 case 0x09: p = "NICAM-BG"; break;
1515 case 0x0a: p = "NICAM-DK"; break;
1516 case 0x0b: p = "NICAM-I"; break;
1517 case 0x0c: p = "NICAM-L"; break;
1518 case 0x0d: p = "BTSC/EIAJ/A2-M Mono (4.5 MHz FMMono)"; break;
1519 case 0x0e: p = "IF FM Radio"; break;
1520 case 0x0f: p = "BTSC"; break;
1521 case 0x10: p = "high-deviation FM"; break;
1522 case 0x11: p = "very high-deviation FM"; break;
1523 case 0xfd: p = "unknown audio standard"; break;
1524 case 0xfe: p = "forced audio standard"; break;
1525 case 0xff: p = "no detected audio standard"; break;
1526 default: p = "not defined";
1527 }
1528 v4l_info(client, "Detected audio standard: %s\n", p);
1529 v4l_info(client, "Audio microcontroller: %s\n",
1530 (download_ctl & 0x10) ?
1531 ((mute_ctl & 0x2) ? "detecting" : "running") : "stopped");
1532
1533 switch (audio_config >> 4) {
1534 case 0x00: p = "undefined"; break;
1535 case 0x01: p = "BTSC"; break;
1536 case 0x02: p = "EIAJ"; break;
1537 case 0x03: p = "A2-M"; break;
1538 case 0x04: p = "A2-BG"; break;
1539 case 0x05: p = "A2-DK1"; break;
1540 case 0x06: p = "A2-DK2"; break;
1541 case 0x07: p = "A2-DK3"; break;
1542 case 0x08: p = "A1 (6.0 MHz FM Mono)"; break;
1543 case 0x09: p = "AM-L"; break;
1544 case 0x0a: p = "NICAM-BG"; break;
1545 case 0x0b: p = "NICAM-DK"; break;
1546 case 0x0c: p = "NICAM-I"; break;
1547 case 0x0d: p = "NICAM-L"; break;
1548 case 0x0e: p = "FM radio"; break;
1549 case 0x0f: p = "automatic detection"; break;
1550 default: p = "undefined";
1551 }
1552 v4l_info(client, "Configured audio standard: %s\n", p);
1553
1554 if ((audio_config >> 4) < 0xF) {
1555 switch (audio_config & 0xF) {
1556 case 0x00: p = "MONO1 (LANGUAGE A/Mono L+R channel for BTSC, EIAJ, A2)"; break;
1557 case 0x01: p = "MONO2 (LANGUAGE B)"; break;
1558 case 0x02: p = "MONO3 (STEREO forced MONO)"; break;
1559 case 0x03: p = "MONO4 (NICAM ANALOG-Language C/Analog Fallback)"; break;
1560 case 0x04: p = "STEREO"; break;
1561 case 0x05: p = "DUAL1 (AB)"; break;
1562 case 0x06: p = "DUAL2 (AC) (FM)"; break;
1563 case 0x07: p = "DUAL3 (BC) (FM)"; break;
1564 case 0x08: p = "DUAL4 (AC) (AM)"; break;
1565 case 0x09: p = "DUAL5 (BC) (AM)"; break;
1566 case 0x0a: p = "SAP"; break;
1567 default: p = "undefined";
1568 }
1569 v4l_info(client, "Configured audio mode: %s\n", p);
1570 } else {
1571 switch (audio_config & 0xF) {
1572 case 0x00: p = "BG"; break;
1573 case 0x01: p = "DK1"; break;
1574 case 0x02: p = "DK2"; break;
1575 case 0x03: p = "DK3"; break;
1576 case 0x04: p = "I"; break;
1577 case 0x05: p = "L"; break;
1578 case 0x06: p = "BTSC"; break;
1579 case 0x07: p = "EIAJ"; break;
1580 case 0x08: p = "A2-M"; break;
1581 case 0x09: p = "FM Radio"; break;
1582 case 0x0f: p = "automatic standard and mode detection"; break;
1583 default: p = "undefined";
1584 }
1585 v4l_info(client, "Configured audio system: %s\n", p);
1586 }
1587
1588 if (aud_input) {
1589 v4l_info(client, "Specified audio input: Tuner (In%d)\n", aud_input);
1590 } else {
1591 v4l_info(client, "Specified audio input: External\n");
1592 }
1593
1594 switch (pref_mode & 0xf) {
1595 case 0: p = "mono/language A"; break;
1596 case 1: p = "language B"; break;
1597 case 2: p = "language C"; break;
1598 case 3: p = "analog fallback"; break;
1599 case 4: p = "stereo"; break;
1600 case 5: p = "language AC"; break;
1601 case 6: p = "language BC"; break;
1602 case 7: p = "language AB"; break;
1603 default: p = "undefined";
1604 }
1605 v4l_info(client, "Preferred audio mode: %s\n", p);
1606
1607 if ((audio_config & 0xf) == 0xf) {
1608 switch ((afc0 >> 3) & 0x3) {
1609 case 0: p = "system DK"; break;
1610 case 1: p = "system L"; break;
1611 case 2: p = "autodetect"; break;
1612 default: p = "undefined";
1613 }
1614 v4l_info(client, "Selected 65 MHz format: %s\n", p);
1615
1616 switch (afc0 & 0x7) {
1617 case 0: p = "chroma"; break;
1618 case 1: p = "BTSC"; break;
1619 case 2: p = "EIAJ"; break;
1620 case 3: p = "A2-M"; break;
1621 case 4: p = "autodetect"; break;
1622 default: p = "undefined";
1623 }
1624 v4l_info(client, "Selected 45 MHz format: %s\n", p);
1625 }
1626}
1627
1628/* ----------------------------------------------------------------------- */
1629
1630/* This load_fw operation must be called to load the driver's firmware.
1631 Without this the audio standard detection will fail and you will
1632 only get mono.
1633
1634 Since loading the firmware is often problematic when the driver is
1635 compiled into the kernel I recommend postponing calling this function
1636 until the first open of the video device. Another reason for
1637 postponing it is that loading this firmware takes a long time (seconds)
1638 due to the slow i2c bus speed. So it will speed up the boot process if
1639 you can avoid loading the fw as long as the video device isn't used. */
1640static int cx25840_load_fw(struct v4l2_subdev *sd)
1641{
1642 struct cx25840_state *state = to_state(sd);
1643 struct i2c_client *client = v4l2_get_subdevdata(sd);
1644
1645 if (!state->is_initialized) {
1646 /* initialize and load firmware */
1647 state->is_initialized = 1;
1648 if (is_cx2583x(state))
1649 cx25836_initialize(client);
1650 else if (is_cx2388x(state))
1651 cx23885_initialize(client);
1652 else if (is_cx231xx(state))
1653 cx231xx_initialize(client);
1654 else
1655 cx25840_initialize(client);
1656 }
1657 return 0;
1658}
1659
1660#ifdef CONFIG_VIDEO_ADV_DEBUG
1661static int cx25840_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1662{
1663 struct i2c_client *client = v4l2_get_subdevdata(sd);
1664
1665 if (!v4l2_chip_match_i2c_client(client, &reg->match))
1666 return -EINVAL;
1667 if (!capable(CAP_SYS_ADMIN))
1668 return -EPERM;
1669 reg->size = 1;
1670 reg->val = cx25840_read(client, reg->reg & 0x0fff);
1671 return 0;
1672}
1673
1674static int cx25840_s_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1675{
1676 struct i2c_client *client = v4l2_get_subdevdata(sd);
1677
1678 if (!v4l2_chip_match_i2c_client(client, &reg->match))
1679 return -EINVAL;
1680 if (!capable(CAP_SYS_ADMIN))
1681 return -EPERM;
1682 cx25840_write(client, reg->reg & 0x0fff, reg->val & 0xff);
1683 return 0;
1684}
1685#endif
1686
1687static int cx25840_s_audio_stream(struct v4l2_subdev *sd, int enable)
1688{
1689 struct cx25840_state *state = to_state(sd);
1690 struct i2c_client *client = v4l2_get_subdevdata(sd);
1691 u8 v;
1692
1693 if (is_cx2583x(state) || is_cx2388x(state) || is_cx231xx(state))
1694 return 0;
1695
1696 v4l_dbg(1, cx25840_debug, client, "%s audio output\n",
1697 enable ? "enable" : "disable");
1698
1699 if (enable) {
1700 v = cx25840_read(client, 0x115) | 0x80;
1701 cx25840_write(client, 0x115, v);
1702 v = cx25840_read(client, 0x116) | 0x03;
1703 cx25840_write(client, 0x116, v);
1704 } else {
1705 v = cx25840_read(client, 0x115) & ~(0x80);
1706 cx25840_write(client, 0x115, v);
1707 v = cx25840_read(client, 0x116) & ~(0x03);
1708 cx25840_write(client, 0x116, v);
1709 }
1710 return 0;
1711}
1712
1713static int cx25840_s_stream(struct v4l2_subdev *sd, int enable)
1714{
1715 struct cx25840_state *state = to_state(sd);
1716 struct i2c_client *client = v4l2_get_subdevdata(sd);
1717 u8 v;
1718
1719 v4l_dbg(1, cx25840_debug, client, "%s video output\n",
1720 enable ? "enable" : "disable");
1721 if (enable) {
1722 if (is_cx2388x(state) || is_cx231xx(state)) {
1723 v = cx25840_read(client, 0x421) | 0x0b;
1724 cx25840_write(client, 0x421, v);
1725 } else {
1726 v = cx25840_read(client, 0x115) | 0x0c;
1727 cx25840_write(client, 0x115, v);
1728 v = cx25840_read(client, 0x116) | 0x04;
1729 cx25840_write(client, 0x116, v);
1730 }
1731 } else {
1732 if (is_cx2388x(state) || is_cx231xx(state)) {
1733 v = cx25840_read(client, 0x421) & ~(0x0b);
1734 cx25840_write(client, 0x421, v);
1735 } else {
1736 v = cx25840_read(client, 0x115) & ~(0x0c);
1737 cx25840_write(client, 0x115, v);
1738 v = cx25840_read(client, 0x116) & ~(0x04);
1739 cx25840_write(client, 0x116, v);
1740 }
1741 }
1742 return 0;
1743}
1744
1745/* Query the current detected video format */
1746static int cx25840_g_std(struct v4l2_subdev *sd, v4l2_std_id *std)
1747{
1748 struct i2c_client *client = v4l2_get_subdevdata(sd);
1749
1750 v4l2_std_id stds[] = {
1751 /* 0000 */ V4L2_STD_UNKNOWN,
1752
1753 /* 0001 */ V4L2_STD_NTSC_M,
1754 /* 0010 */ V4L2_STD_NTSC_M_JP,
1755 /* 0011 */ V4L2_STD_NTSC_443,
1756 /* 0100 */ V4L2_STD_PAL,
1757 /* 0101 */ V4L2_STD_PAL_M,
1758 /* 0110 */ V4L2_STD_PAL_N,
1759 /* 0111 */ V4L2_STD_PAL_Nc,
1760 /* 1000 */ V4L2_STD_PAL_60,
1761
1762 /* 1001 */ V4L2_STD_UNKNOWN,
1763 /* 1010 */ V4L2_STD_UNKNOWN,
1764 /* 1001 */ V4L2_STD_UNKNOWN,
1765 /* 1010 */ V4L2_STD_UNKNOWN,
1766 /* 1011 */ V4L2_STD_UNKNOWN,
1767 /* 1110 */ V4L2_STD_UNKNOWN,
1768 /* 1111 */ V4L2_STD_UNKNOWN
1769 };
1770
1771 u32 fmt = (cx25840_read4(client, 0x40c) >> 8) & 0xf;
1772 *std = stds[ fmt ];
1773
1774 v4l_dbg(1, cx25840_debug, client, "g_std fmt = %x, v4l2_std_id = 0x%x\n",
1775 fmt, (unsigned int)stds[ fmt ]);
1776
1777 return 0;
1778}
1779
1780static int cx25840_g_input_status(struct v4l2_subdev *sd, u32 *status)
1781{
1782 struct i2c_client *client = v4l2_get_subdevdata(sd);
1783
1784 /* A limited function that checks for signal status and returns
1785 * the state.
1786 */
1787
1788 /* Check for status of Horizontal lock (SRC lock isn't reliable) */
1789 if ((cx25840_read4(client, 0x40c) & 0x00010000) == 0)
1790 *status |= V4L2_IN_ST_NO_SIGNAL;
1791
1792 return 0;
1793}
1794
1795static int cx25840_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
1796{
1797 struct cx25840_state *state = to_state(sd);
1798 struct i2c_client *client = v4l2_get_subdevdata(sd);
1799
1800 if (state->radio == 0 && state->std == std)
1801 return 0;
1802 state->radio = 0;
1803 state->std = std;
1804 return set_v4lstd(client);
1805}
1806
1807static int cx25840_s_radio(struct v4l2_subdev *sd)
1808{
1809 struct cx25840_state *state = to_state(sd);
1810
1811 state->radio = 1;
1812 return 0;
1813}
1814
1815static int cx25840_s_video_routing(struct v4l2_subdev *sd,
1816 u32 input, u32 output, u32 config)
1817{
1818 struct cx25840_state *state = to_state(sd);
1819 struct i2c_client *client = v4l2_get_subdevdata(sd);
1820
1821 if (is_cx23888(state))
1822 cx23888_std_setup(client);
1823
1824 return set_input(client, input, state->aud_input);
1825}
1826
1827static int cx25840_s_audio_routing(struct v4l2_subdev *sd,
1828 u32 input, u32 output, u32 config)
1829{
1830 struct cx25840_state *state = to_state(sd);
1831 struct i2c_client *client = v4l2_get_subdevdata(sd);
1832
1833 if (is_cx23888(state))
1834 cx23888_std_setup(client);
1835 return set_input(client, state->vid_input, input);
1836}
1837
1838static int cx25840_s_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *freq)
1839{
1840 struct i2c_client *client = v4l2_get_subdevdata(sd);
1841
1842 input_change(client);
1843 return 0;
1844}
1845
1846static int cx25840_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1847{
1848 struct cx25840_state *state = to_state(sd);
1849 struct i2c_client *client = v4l2_get_subdevdata(sd);
1850 u8 vpres = cx25840_read(client, 0x40e) & 0x20;
1851 u8 mode;
1852 int val = 0;
1853
1854 if (state->radio)
1855 return 0;
1856
1857 vt->signal = vpres ? 0xffff : 0x0;
1858 if (is_cx2583x(state))
1859 return 0;
1860
1861 vt->capability |=
1862 V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
1863 V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
1864
1865 mode = cx25840_read(client, 0x804);
1866
1867 /* get rxsubchans and audmode */
1868 if ((mode & 0xf) == 1)
1869 val |= V4L2_TUNER_SUB_STEREO;
1870 else
1871 val |= V4L2_TUNER_SUB_MONO;
1872
1873 if (mode == 2 || mode == 4)
1874 val = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
1875
1876 if (mode & 0x10)
1877 val |= V4L2_TUNER_SUB_SAP;
1878
1879 vt->rxsubchans = val;
1880 vt->audmode = state->audmode;
1881 return 0;
1882}
1883
1884static int cx25840_s_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1885{
1886 struct cx25840_state *state = to_state(sd);
1887 struct i2c_client *client = v4l2_get_subdevdata(sd);
1888
1889 if (state->radio || is_cx2583x(state))
1890 return 0;
1891
1892 switch (vt->audmode) {
1893 case V4L2_TUNER_MODE_MONO:
1894 /* mono -> mono
1895 stereo -> mono
1896 bilingual -> lang1 */
1897 cx25840_and_or(client, 0x809, ~0xf, 0x00);
1898 break;
1899 case V4L2_TUNER_MODE_STEREO:
1900 case V4L2_TUNER_MODE_LANG1:
1901 /* mono -> mono
1902 stereo -> stereo
1903 bilingual -> lang1 */
1904 cx25840_and_or(client, 0x809, ~0xf, 0x04);
1905 break;
1906 case V4L2_TUNER_MODE_LANG1_LANG2:
1907 /* mono -> mono
1908 stereo -> stereo
1909 bilingual -> lang1/lang2 */
1910 cx25840_and_or(client, 0x809, ~0xf, 0x07);
1911 break;
1912 case V4L2_TUNER_MODE_LANG2:
1913 /* mono -> mono
1914 stereo -> stereo
1915 bilingual -> lang2 */
1916 cx25840_and_or(client, 0x809, ~0xf, 0x01);
1917 break;
1918 default:
1919 return -EINVAL;
1920 }
1921 state->audmode = vt->audmode;
1922 return 0;
1923}
1924
1925static int cx25840_reset(struct v4l2_subdev *sd, u32 val)
1926{
1927 struct cx25840_state *state = to_state(sd);
1928 struct i2c_client *client = v4l2_get_subdevdata(sd);
1929
1930 if (is_cx2583x(state))
1931 cx25836_initialize(client);
1932 else if (is_cx2388x(state))
1933 cx23885_initialize(client);
1934 else if (is_cx231xx(state))
1935 cx231xx_initialize(client);
1936 else
1937 cx25840_initialize(client);
1938 return 0;
1939}
1940
1941static int cx25840_g_chip_ident(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip)
1942{
1943 struct cx25840_state *state = to_state(sd);
1944 struct i2c_client *client = v4l2_get_subdevdata(sd);
1945
1946 return v4l2_chip_ident_i2c_client(client, chip, state->id, state->rev);
1947}
1948
1949static int cx25840_log_status(struct v4l2_subdev *sd)
1950{
1951 struct cx25840_state *state = to_state(sd);
1952 struct i2c_client *client = v4l2_get_subdevdata(sd);
1953
1954 log_video_status(client);
1955 if (!is_cx2583x(state))
1956 log_audio_status(client);
1957 cx25840_ir_log_status(sd);
1958 v4l2_ctrl_handler_log_status(&state->hdl, sd->name);
1959 return 0;
1960}
1961
1962static int cx23885_irq_handler(struct v4l2_subdev *sd, u32 status,
1963 bool *handled)
1964{
1965 struct cx25840_state *state = to_state(sd);
1966 struct i2c_client *c = v4l2_get_subdevdata(sd);
1967 u8 irq_stat, aud_stat, aud_en, ir_stat, ir_en;
1968 u32 vid_stat, aud_mc_stat;
1969 bool block_handled;
1970 int ret = 0;
1971
1972 irq_stat = cx25840_read(c, CX23885_PIN_CTRL_IRQ_REG);
1973 v4l_dbg(2, cx25840_debug, c, "AV Core IRQ status (entry): %s %s %s\n",
1974 irq_stat & CX23885_PIN_CTRL_IRQ_IR_STAT ? "ir" : " ",
1975 irq_stat & CX23885_PIN_CTRL_IRQ_AUD_STAT ? "aud" : " ",
1976 irq_stat & CX23885_PIN_CTRL_IRQ_VID_STAT ? "vid" : " ");
1977
1978 if ((is_cx23885(state) || is_cx23887(state))) {
1979 ir_stat = cx25840_read(c, CX25840_IR_STATS_REG);
1980 ir_en = cx25840_read(c, CX25840_IR_IRQEN_REG);
1981 v4l_dbg(2, cx25840_debug, c,
1982 "AV Core ir IRQ status: %#04x disables: %#04x\n",
1983 ir_stat, ir_en);
1984 if (irq_stat & CX23885_PIN_CTRL_IRQ_IR_STAT) {
1985 block_handled = false;
1986 ret = cx25840_ir_irq_handler(sd,
1987 status, &block_handled);
1988 if (block_handled)
1989 *handled = true;
1990 }
1991 }
1992
1993 aud_stat = cx25840_read(c, CX25840_AUD_INT_STAT_REG);
1994 aud_en = cx25840_read(c, CX25840_AUD_INT_CTRL_REG);
1995 v4l_dbg(2, cx25840_debug, c,
1996 "AV Core audio IRQ status: %#04x disables: %#04x\n",
1997 aud_stat, aud_en);
1998 aud_mc_stat = cx25840_read4(c, CX23885_AUD_MC_INT_MASK_REG);
1999 v4l_dbg(2, cx25840_debug, c,
2000 "AV Core audio MC IRQ status: %#06x enables: %#06x\n",
2001 aud_mc_stat >> CX23885_AUD_MC_INT_STAT_SHFT,
2002 aud_mc_stat & CX23885_AUD_MC_INT_CTRL_BITS);
2003 if (irq_stat & CX23885_PIN_CTRL_IRQ_AUD_STAT) {
2004 if (aud_stat) {
2005 cx25840_write(c, CX25840_AUD_INT_STAT_REG, aud_stat);
2006 *handled = true;
2007 }
2008 }
2009
2010 vid_stat = cx25840_read4(c, CX25840_VID_INT_STAT_REG);
2011 v4l_dbg(2, cx25840_debug, c,
2012 "AV Core video IRQ status: %#06x disables: %#06x\n",
2013 vid_stat & CX25840_VID_INT_STAT_BITS,
2014 vid_stat >> CX25840_VID_INT_MASK_SHFT);
2015 if (irq_stat & CX23885_PIN_CTRL_IRQ_VID_STAT) {
2016 if (vid_stat & CX25840_VID_INT_STAT_BITS) {
2017 cx25840_write4(c, CX25840_VID_INT_STAT_REG, vid_stat);
2018 *handled = true;
2019 }
2020 }
2021
2022 irq_stat = cx25840_read(c, CX23885_PIN_CTRL_IRQ_REG);
2023 v4l_dbg(2, cx25840_debug, c, "AV Core IRQ status (exit): %s %s %s\n",
2024 irq_stat & CX23885_PIN_CTRL_IRQ_IR_STAT ? "ir" : " ",
2025 irq_stat & CX23885_PIN_CTRL_IRQ_AUD_STAT ? "aud" : " ",
2026 irq_stat & CX23885_PIN_CTRL_IRQ_VID_STAT ? "vid" : " ");
2027
2028 return ret;
2029}
2030
2031static int cx25840_irq_handler(struct v4l2_subdev *sd, u32 status,
2032 bool *handled)
2033{
2034 struct cx25840_state *state = to_state(sd);
2035
2036 *handled = false;
2037
2038 /* Only support the CX2388[578] AV Core for now */
2039 if (is_cx2388x(state))
2040 return cx23885_irq_handler(sd, status, handled);
2041
2042 return -ENODEV;
2043}
2044
2045/* ----------------------------------------------------------------------- */
2046
2047#define DIF_PLL_FREQ_WORD (0x300)
2048#define DIF_BPF_COEFF01 (0x348)
2049#define DIF_BPF_COEFF23 (0x34c)
2050#define DIF_BPF_COEFF45 (0x350)
2051#define DIF_BPF_COEFF67 (0x354)
2052#define DIF_BPF_COEFF89 (0x358)
2053#define DIF_BPF_COEFF1011 (0x35c)
2054#define DIF_BPF_COEFF1213 (0x360)
2055#define DIF_BPF_COEFF1415 (0x364)
2056#define DIF_BPF_COEFF1617 (0x368)
2057#define DIF_BPF_COEFF1819 (0x36c)
2058#define DIF_BPF_COEFF2021 (0x370)
2059#define DIF_BPF_COEFF2223 (0x374)
2060#define DIF_BPF_COEFF2425 (0x378)
2061#define DIF_BPF_COEFF2627 (0x37c)
2062#define DIF_BPF_COEFF2829 (0x380)
2063#define DIF_BPF_COEFF3031 (0x384)
2064#define DIF_BPF_COEFF3233 (0x388)
2065#define DIF_BPF_COEFF3435 (0x38c)
2066#define DIF_BPF_COEFF36 (0x390)
2067
2068void cx23885_dif_setup(struct i2c_client *client, u32 ifHz)
2069{
2070 u64 pll_freq;
2071 u32 pll_freq_word;
2072
2073 v4l_dbg(1, cx25840_debug, client, "%s(%d)\n", __func__, ifHz);
2074
2075 /* Assuming TV */
2076 /* Calculate the PLL frequency word based on the adjusted ifHz */
2077 pll_freq = div_u64((u64)ifHz * 268435456, 50000000);
2078 pll_freq_word = (u32)pll_freq;
2079
2080 cx25840_write4(client, DIF_PLL_FREQ_WORD, pll_freq_word);
2081
2082 /* Round down to the nearest 100KHz */
2083 ifHz = (ifHz / 100000) * 100000;
2084
2085 if (ifHz < 3000000)
2086 ifHz = 3000000;
2087
2088 if (ifHz > 16000000)
2089 ifHz = 16000000;
2090
2091 v4l_dbg(1, cx25840_debug, client, "%s(%d) again\n", __func__, ifHz);
2092
2093 switch (ifHz) {
2094 case 3000000:
2095 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000002);
2096 cx25840_write4(client, DIF_BPF_COEFF23, 0x00080012);
2097 cx25840_write4(client, DIF_BPF_COEFF45, 0x001e0024);
2098 cx25840_write4(client, DIF_BPF_COEFF67, 0x001bfff8);
2099 cx25840_write4(client, DIF_BPF_COEFF89, 0xffb4ff50);
2100 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfed8fe68);
2101 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe24fe34);
2102 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfebaffc7);
2103 cx25840_write4(client, DIF_BPF_COEFF1617, 0x014d031f);
2104 cx25840_write4(client, DIF_BPF_COEFF1819, 0x04f0065d);
2105 cx25840_write4(client, DIF_BPF_COEFF2021, 0x07010688);
2106 cx25840_write4(client, DIF_BPF_COEFF2223, 0x04c901d6);
2107 cx25840_write4(client, DIF_BPF_COEFF2425, 0xfe00f9d3);
2108 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf600f342);
2109 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf235f337);
2110 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf64efb22);
2111 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0105070f);
2112 cx25840_write4(client, DIF_BPF_COEFF3435, 0x0c460fce);
2113 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2114 break;
2115
2116 case 3100000:
2117 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000001);
2118 cx25840_write4(client, DIF_BPF_COEFF23, 0x00070012);
2119 cx25840_write4(client, DIF_BPF_COEFF45, 0x00220032);
2120 cx25840_write4(client, DIF_BPF_COEFF67, 0x00370026);
2121 cx25840_write4(client, DIF_BPF_COEFF89, 0xfff0ff91);
2122 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff0efe7c);
2123 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe01fdcc);
2124 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfe0afedb);
2125 cx25840_write4(client, DIF_BPF_COEFF1617, 0x00440224);
2126 cx25840_write4(client, DIF_BPF_COEFF1819, 0x0434060c);
2127 cx25840_write4(client, DIF_BPF_COEFF2021, 0x0738074e);
2128 cx25840_write4(client, DIF_BPF_COEFF2223, 0x06090361);
2129 cx25840_write4(client, DIF_BPF_COEFF2425, 0xff99fb39);
2130 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf6fef3b6);
2131 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf21af2a5);
2132 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf573fa33);
2133 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0034067d);
2134 cx25840_write4(client, DIF_BPF_COEFF3435, 0x0bfb0fb9);
2135 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2136 break;
2137
2138 case 3200000:
2139 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000000);
2140 cx25840_write4(client, DIF_BPF_COEFF23, 0x0004000e);
2141 cx25840_write4(client, DIF_BPF_COEFF45, 0x00200038);
2142 cx25840_write4(client, DIF_BPF_COEFF67, 0x004c004f);
2143 cx25840_write4(client, DIF_BPF_COEFF89, 0x002fffdf);
2144 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff5cfeb6);
2145 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe0dfd92);
2146 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd7ffe03);
2147 cx25840_write4(client, DIF_BPF_COEFF1617, 0xff36010a);
2148 cx25840_write4(client, DIF_BPF_COEFF1819, 0x03410575);
2149 cx25840_write4(client, DIF_BPF_COEFF2021, 0x072607d2);
2150 cx25840_write4(client, DIF_BPF_COEFF2223, 0x071804d5);
2151 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0134fcb7);
2152 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf81ff451);
2153 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf223f22e);
2154 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf4a7f94b);
2155 cx25840_write4(client, DIF_BPF_COEFF3233, 0xff6405e8);
2156 cx25840_write4(client, DIF_BPF_COEFF3435, 0x0bae0fa4);
2157 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2158 break;
2159
2160 case 3300000:
2161 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000ffff);
2162 cx25840_write4(client, DIF_BPF_COEFF23, 0x00000008);
2163 cx25840_write4(client, DIF_BPF_COEFF45, 0x001a0036);
2164 cx25840_write4(client, DIF_BPF_COEFF67, 0x0056006d);
2165 cx25840_write4(client, DIF_BPF_COEFF89, 0x00670030);
2166 cx25840_write4(client, DIF_BPF_COEFF1011, 0xffbdff10);
2167 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe46fd8d);
2168 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd25fd4f);
2169 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfe35ffe0);
2170 cx25840_write4(client, DIF_BPF_COEFF1819, 0x0224049f);
2171 cx25840_write4(client, DIF_BPF_COEFF2021, 0x06c9080e);
2172 cx25840_write4(client, DIF_BPF_COEFF2223, 0x07ef0627);
2173 cx25840_write4(client, DIF_BPF_COEFF2425, 0x02c9fe45);
2174 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf961f513);
2175 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf250f1d2);
2176 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf3ecf869);
2177 cx25840_write4(client, DIF_BPF_COEFF3233, 0xfe930552);
2178 cx25840_write4(client, DIF_BPF_COEFF3435, 0x0b5f0f8f);
2179 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2180 break;
2181
2182 case 3400000:
2183 cx25840_write4(client, DIF_BPF_COEFF01, 0xfffffffe);
2184 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffd0001);
2185 cx25840_write4(client, DIF_BPF_COEFF45, 0x000f002c);
2186 cx25840_write4(client, DIF_BPF_COEFF67, 0x0054007d);
2187 cx25840_write4(client, DIF_BPF_COEFF89, 0x0093007c);
2188 cx25840_write4(client, DIF_BPF_COEFF1011, 0x0024ff82);
2189 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfea6fdbb);
2190 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd03fcca);
2191 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfd51feb9);
2192 cx25840_write4(client, DIF_BPF_COEFF1819, 0x00eb0392);
2193 cx25840_write4(client, DIF_BPF_COEFF2021, 0x06270802);
2194 cx25840_write4(client, DIF_BPF_COEFF2223, 0x08880750);
2195 cx25840_write4(client, DIF_BPF_COEFF2425, 0x044dffdb);
2196 cx25840_write4(client, DIF_BPF_COEFF2627, 0xfabdf5f8);
2197 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf2a0f193);
2198 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf342f78f);
2199 cx25840_write4(client, DIF_BPF_COEFF3233, 0xfdc404b9);
2200 cx25840_write4(client, DIF_BPF_COEFF3435, 0x0b0e0f78);
2201 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2202 break;
2203
2204 case 3500000:
2205 cx25840_write4(client, DIF_BPF_COEFF01, 0xfffffffd);
2206 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffafff9);
2207 cx25840_write4(client, DIF_BPF_COEFF45, 0x0002001b);
2208 cx25840_write4(client, DIF_BPF_COEFF67, 0x0046007d);
2209 cx25840_write4(client, DIF_BPF_COEFF89, 0x00ad00ba);
2210 cx25840_write4(client, DIF_BPF_COEFF1011, 0x00870000);
2211 cx25840_write4(client, DIF_BPF_COEFF1213, 0xff26fe1a);
2212 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd1bfc7e);
2213 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc99fda4);
2214 cx25840_write4(client, DIF_BPF_COEFF1819, 0xffa5025c);
2215 cx25840_write4(client, DIF_BPF_COEFF2021, 0x054507ad);
2216 cx25840_write4(client, DIF_BPF_COEFF2223, 0x08dd0847);
2217 cx25840_write4(client, DIF_BPF_COEFF2425, 0x05b80172);
2218 cx25840_write4(client, DIF_BPF_COEFF2627, 0xfc2ef6ff);
2219 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf313f170);
2220 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf2abf6bd);
2221 cx25840_write4(client, DIF_BPF_COEFF3233, 0xfcf6041f);
2222 cx25840_write4(client, DIF_BPF_COEFF3435, 0x0abc0f61);
2223 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2224 break;
2225
2226 case 3600000:
2227 cx25840_write4(client, DIF_BPF_COEFF01, 0xfffffffd);
2228 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff8fff3);
2229 cx25840_write4(client, DIF_BPF_COEFF45, 0xfff50006);
2230 cx25840_write4(client, DIF_BPF_COEFF67, 0x002f006c);
2231 cx25840_write4(client, DIF_BPF_COEFF89, 0x00b200e3);
2232 cx25840_write4(client, DIF_BPF_COEFF1011, 0x00dc007e);
2233 cx25840_write4(client, DIF_BPF_COEFF1213, 0xffb9fea0);
2234 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd6bfc71);
2235 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc17fcb1);
2236 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfe65010b);
2237 cx25840_write4(client, DIF_BPF_COEFF2021, 0x042d0713);
2238 cx25840_write4(client, DIF_BPF_COEFF2223, 0x08ec0906);
2239 cx25840_write4(client, DIF_BPF_COEFF2425, 0x07020302);
2240 cx25840_write4(client, DIF_BPF_COEFF2627, 0xfdaff823);
2241 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf3a7f16a);
2242 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf228f5f5);
2243 cx25840_write4(client, DIF_BPF_COEFF3233, 0xfc2a0384);
2244 cx25840_write4(client, DIF_BPF_COEFF3435, 0x0a670f4a);
2245 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2246 break;
2247
2248 case 3700000:
2249 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffd);
2250 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff7ffef);
2251 cx25840_write4(client, DIF_BPF_COEFF45, 0xffe9fff1);
2252 cx25840_write4(client, DIF_BPF_COEFF67, 0x0010004d);
2253 cx25840_write4(client, DIF_BPF_COEFF89, 0x00a100f2);
2254 cx25840_write4(client, DIF_BPF_COEFF1011, 0x011a00f0);
2255 cx25840_write4(client, DIF_BPF_COEFF1213, 0x0053ff44);
2256 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfdedfca2);
2257 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfbd3fbef);
2258 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfd39ffae);
2259 cx25840_write4(client, DIF_BPF_COEFF2021, 0x02ea0638);
2260 cx25840_write4(client, DIF_BPF_COEFF2223, 0x08b50987);
2261 cx25840_write4(client, DIF_BPF_COEFF2425, 0x08230483);
2262 cx25840_write4(client, DIF_BPF_COEFF2627, 0xff39f960);
2263 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf45bf180);
2264 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf1b8f537);
2265 cx25840_write4(client, DIF_BPF_COEFF3233, 0xfb6102e7);
2266 cx25840_write4(client, DIF_BPF_COEFF3435, 0x0a110f32);
2267 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2268 break;
2269
2270 case 3800000:
2271 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffe);
2272 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff9ffee);
2273 cx25840_write4(client, DIF_BPF_COEFF45, 0xffe1ffdd);
2274 cx25840_write4(client, DIF_BPF_COEFF67, 0xfff00024);
2275 cx25840_write4(client, DIF_BPF_COEFF89, 0x007c00e5);
2276 cx25840_write4(client, DIF_BPF_COEFF1011, 0x013a014a);
2277 cx25840_write4(client, DIF_BPF_COEFF1213, 0x00e6fff8);
2278 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfe98fd0f);
2279 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfbd3fb67);
2280 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfc32fe54);
2281 cx25840_write4(client, DIF_BPF_COEFF2021, 0x01880525);
2282 cx25840_write4(client, DIF_BPF_COEFF2223, 0x083909c7);
2283 cx25840_write4(client, DIF_BPF_COEFF2425, 0x091505ee);
2284 cx25840_write4(client, DIF_BPF_COEFF2627, 0x00c7fab3);
2285 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf52df1b4);
2286 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf15df484);
2287 cx25840_write4(client, DIF_BPF_COEFF3233, 0xfa9b0249);
2288 cx25840_write4(client, DIF_BPF_COEFF3435, 0x09ba0f19);
2289 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2290 break;
2291
2292 case 3900000:
2293 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000000);
2294 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffbfff0);
2295 cx25840_write4(client, DIF_BPF_COEFF45, 0xffdeffcf);
2296 cx25840_write4(client, DIF_BPF_COEFF67, 0xffd1fff6);
2297 cx25840_write4(client, DIF_BPF_COEFF89, 0x004800be);
2298 cx25840_write4(client, DIF_BPF_COEFF1011, 0x01390184);
2299 cx25840_write4(client, DIF_BPF_COEFF1213, 0x016300ac);
2300 cx25840_write4(client, DIF_BPF_COEFF1415, 0xff5efdb1);
2301 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc17fb23);
2302 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfb5cfd0d);
2303 cx25840_write4(client, DIF_BPF_COEFF2021, 0x001703e4);
2304 cx25840_write4(client, DIF_BPF_COEFF2223, 0x077b09c4);
2305 cx25840_write4(client, DIF_BPF_COEFF2425, 0x09d2073c);
2306 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0251fc18);
2307 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf61cf203);
2308 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf118f3dc);
2309 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf9d801aa);
2310 cx25840_write4(client, DIF_BPF_COEFF3435, 0x09600eff);
2311 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2312 break;
2313
2314 case 4000000:
2315 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000001);
2316 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffefff4);
2317 cx25840_write4(client, DIF_BPF_COEFF45, 0xffe1ffc8);
2318 cx25840_write4(client, DIF_BPF_COEFF67, 0xffbaffca);
2319 cx25840_write4(client, DIF_BPF_COEFF89, 0x000b0082);
2320 cx25840_write4(client, DIF_BPF_COEFF1011, 0x01170198);
2321 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01c10152);
2322 cx25840_write4(client, DIF_BPF_COEFF1415, 0x0030fe7b);
2323 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc99fb24);
2324 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfac3fbe9);
2325 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfea5027f);
2326 cx25840_write4(client, DIF_BPF_COEFF2223, 0x0683097f);
2327 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0a560867);
2328 cx25840_write4(client, DIF_BPF_COEFF2627, 0x03d2fd89);
2329 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf723f26f);
2330 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf0e8f341);
2331 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf919010a);
2332 cx25840_write4(client, DIF_BPF_COEFF3435, 0x09060ee5);
2333 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2334 break;
2335
2336 case 4100000:
2337 cx25840_write4(client, DIF_BPF_COEFF01, 0x00010002);
2338 cx25840_write4(client, DIF_BPF_COEFF23, 0x0002fffb);
2339 cx25840_write4(client, DIF_BPF_COEFF45, 0xffe8ffca);
2340 cx25840_write4(client, DIF_BPF_COEFF67, 0xffacffa4);
2341 cx25840_write4(client, DIF_BPF_COEFF89, 0xffcd0036);
2342 cx25840_write4(client, DIF_BPF_COEFF1011, 0x00d70184);
2343 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01f601dc);
2344 cx25840_write4(client, DIF_BPF_COEFF1415, 0x00ffff60);
2345 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfd51fb6d);
2346 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfa6efaf5);
2347 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfd410103);
2348 cx25840_write4(client, DIF_BPF_COEFF2223, 0x055708f9);
2349 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0a9e0969);
2350 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0543ff02);
2351 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf842f2f5);
2352 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf0cef2b2);
2353 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf85e006b);
2354 cx25840_write4(client, DIF_BPF_COEFF3435, 0x08aa0ecb);
2355 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2356 break;
2357
2358 case 4200000:
2359 cx25840_write4(client, DIF_BPF_COEFF01, 0x00010003);
2360 cx25840_write4(client, DIF_BPF_COEFF23, 0x00050003);
2361 cx25840_write4(client, DIF_BPF_COEFF45, 0xfff3ffd3);
2362 cx25840_write4(client, DIF_BPF_COEFF67, 0xffaaff8b);
2363 cx25840_write4(client, DIF_BPF_COEFF89, 0xff95ffe5);
2364 cx25840_write4(client, DIF_BPF_COEFF1011, 0x0080014a);
2365 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01fe023f);
2366 cx25840_write4(client, DIF_BPF_COEFF1415, 0x01ba0050);
2367 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfe35fbf8);
2368 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfa62fa3b);
2369 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfbf9ff7e);
2370 cx25840_write4(client, DIF_BPF_COEFF2223, 0x04010836);
2371 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0aa90a3d);
2372 cx25840_write4(client, DIF_BPF_COEFF2627, 0x069f007f);
2373 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf975f395);
2374 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf0cbf231);
2375 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf7a9ffcb);
2376 cx25840_write4(client, DIF_BPF_COEFF3435, 0x084c0eaf);
2377 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2378 break;
2379
2380 case 4300000:
2381 cx25840_write4(client, DIF_BPF_COEFF01, 0x00010003);
2382 cx25840_write4(client, DIF_BPF_COEFF23, 0x0008000a);
2383 cx25840_write4(client, DIF_BPF_COEFF45, 0x0000ffe4);
2384 cx25840_write4(client, DIF_BPF_COEFF67, 0xffb4ff81);
2385 cx25840_write4(client, DIF_BPF_COEFF89, 0xff6aff96);
2386 cx25840_write4(client, DIF_BPF_COEFF1011, 0x001c00f0);
2387 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01d70271);
2388 cx25840_write4(client, DIF_BPF_COEFF1415, 0x0254013b);
2389 cx25840_write4(client, DIF_BPF_COEFF1617, 0xff36fcbd);
2390 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfa9ff9c5);
2391 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfadbfdfe);
2392 cx25840_write4(client, DIF_BPF_COEFF2223, 0x028c073b);
2393 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0a750adf);
2394 cx25840_write4(client, DIF_BPF_COEFF2627, 0x07e101fa);
2395 cx25840_write4(client, DIF_BPF_COEFF2829, 0xfab8f44e);
2396 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf0ddf1be);
2397 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf6f9ff2b);
2398 cx25840_write4(client, DIF_BPF_COEFF3435, 0x07ed0e94);
2399 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2400 break;
2401
2402 case 4400000:
2403 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000003);
2404 cx25840_write4(client, DIF_BPF_COEFF23, 0x0009000f);
2405 cx25840_write4(client, DIF_BPF_COEFF45, 0x000efff8);
2406 cx25840_write4(client, DIF_BPF_COEFF67, 0xffc9ff87);
2407 cx25840_write4(client, DIF_BPF_COEFF89, 0xff52ff54);
2408 cx25840_write4(client, DIF_BPF_COEFF1011, 0xffb5007e);
2409 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01860270);
2410 cx25840_write4(client, DIF_BPF_COEFF1415, 0x02c00210);
2411 cx25840_write4(client, DIF_BPF_COEFF1617, 0x0044fdb2);
2412 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfb22f997);
2413 cx25840_write4(client, DIF_BPF_COEFF2021, 0xf9f2fc90);
2414 cx25840_write4(client, DIF_BPF_COEFF2223, 0x0102060f);
2415 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0a050b4c);
2416 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0902036e);
2417 cx25840_write4(client, DIF_BPF_COEFF2829, 0xfc0af51e);
2418 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf106f15a);
2419 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf64efe8b);
2420 cx25840_write4(client, DIF_BPF_COEFF3435, 0x078d0e77);
2421 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2422 break;
2423
2424 case 4500000:
2425 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000002);
2426 cx25840_write4(client, DIF_BPF_COEFF23, 0x00080012);
2427 cx25840_write4(client, DIF_BPF_COEFF45, 0x0019000e);
2428 cx25840_write4(client, DIF_BPF_COEFF67, 0xffe5ff9e);
2429 cx25840_write4(client, DIF_BPF_COEFF89, 0xff4fff25);
2430 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff560000);
2431 cx25840_write4(client, DIF_BPF_COEFF1213, 0x0112023b);
2432 cx25840_write4(client, DIF_BPF_COEFF1415, 0x02f702c0);
2433 cx25840_write4(client, DIF_BPF_COEFF1617, 0x014dfec8);
2434 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfbe5f9b3);
2435 cx25840_write4(client, DIF_BPF_COEFF2021, 0xf947fb41);
2436 cx25840_write4(client, DIF_BPF_COEFF2223, 0xff7004b9);
2437 cx25840_write4(client, DIF_BPF_COEFF2425, 0x095a0b81);
2438 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0a0004d8);
2439 cx25840_write4(client, DIF_BPF_COEFF2829, 0xfd65f603);
2440 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf144f104);
2441 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf5aafdec);
2442 cx25840_write4(client, DIF_BPF_COEFF3435, 0x072b0e5a);
2443 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2444 break;
2445
2446 case 4600000:
2447 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000001);
2448 cx25840_write4(client, DIF_BPF_COEFF23, 0x00060012);
2449 cx25840_write4(client, DIF_BPF_COEFF45, 0x00200022);
2450 cx25840_write4(client, DIF_BPF_COEFF67, 0x0005ffc1);
2451 cx25840_write4(client, DIF_BPF_COEFF89, 0xff61ff10);
2452 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff09ff82);
2453 cx25840_write4(client, DIF_BPF_COEFF1213, 0x008601d7);
2454 cx25840_write4(client, DIF_BPF_COEFF1415, 0x02f50340);
2455 cx25840_write4(client, DIF_BPF_COEFF1617, 0x0241fff0);
2456 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfcddfa19);
2457 cx25840_write4(client, DIF_BPF_COEFF2021, 0xf8e2fa1e);
2458 cx25840_write4(client, DIF_BPF_COEFF2223, 0xfde30343);
2459 cx25840_write4(client, DIF_BPF_COEFF2425, 0x08790b7f);
2460 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0ad50631);
2461 cx25840_write4(client, DIF_BPF_COEFF2829, 0xfec7f6fc);
2462 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf198f0bd);
2463 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf50dfd4e);
2464 cx25840_write4(client, DIF_BPF_COEFF3435, 0x06c90e3d);
2465 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2466 break;
2467
2468 case 4700000:
2469 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000ffff);
2470 cx25840_write4(client, DIF_BPF_COEFF23, 0x0003000f);
2471 cx25840_write4(client, DIF_BPF_COEFF45, 0x00220030);
2472 cx25840_write4(client, DIF_BPF_COEFF67, 0x0025ffed);
2473 cx25840_write4(client, DIF_BPF_COEFF89, 0xff87ff15);
2474 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfed6ff10);
2475 cx25840_write4(client, DIF_BPF_COEFF1213, 0xffed014c);
2476 cx25840_write4(client, DIF_BPF_COEFF1415, 0x02b90386);
2477 cx25840_write4(client, DIF_BPF_COEFF1617, 0x03110119);
2478 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfdfefac4);
2479 cx25840_write4(client, DIF_BPF_COEFF2021, 0xf8c6f92f);
2480 cx25840_write4(client, DIF_BPF_COEFF2223, 0xfc6701b7);
2481 cx25840_write4(client, DIF_BPF_COEFF2425, 0x07670b44);
2482 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0b7e0776);
2483 cx25840_write4(client, DIF_BPF_COEFF2829, 0x002df807);
2484 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf200f086);
2485 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf477fcb1);
2486 cx25840_write4(client, DIF_BPF_COEFF3435, 0x06650e1e);
2487 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2488 break;
2489
2490 case 4800000:
2491 cx25840_write4(client, DIF_BPF_COEFF01, 0xfffffffe);
2492 cx25840_write4(client, DIF_BPF_COEFF23, 0xffff0009);
2493 cx25840_write4(client, DIF_BPF_COEFF45, 0x001e0038);
2494 cx25840_write4(client, DIF_BPF_COEFF67, 0x003f001b);
2495 cx25840_write4(client, DIF_BPF_COEFF89, 0xffbcff36);
2496 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfec2feb6);
2497 cx25840_write4(client, DIF_BPF_COEFF1213, 0xff5600a5);
2498 cx25840_write4(client, DIF_BPF_COEFF1415, 0x0248038d);
2499 cx25840_write4(client, DIF_BPF_COEFF1617, 0x03b00232);
2500 cx25840_write4(client, DIF_BPF_COEFF1819, 0xff39fbab);
2501 cx25840_write4(client, DIF_BPF_COEFF2021, 0xf8f4f87f);
2502 cx25840_write4(client, DIF_BPF_COEFF2223, 0xfb060020);
2503 cx25840_write4(client, DIF_BPF_COEFF2425, 0x062a0ad2);
2504 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0bf908a3);
2505 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0192f922);
2506 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf27df05e);
2507 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf3e8fc14);
2508 cx25840_write4(client, DIF_BPF_COEFF3435, 0x06000e00);
2509 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2510 break;
2511
2512 case 4900000:
2513 cx25840_write4(client, DIF_BPF_COEFF01, 0xfffffffd);
2514 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffc0002);
2515 cx25840_write4(client, DIF_BPF_COEFF45, 0x00160037);
2516 cx25840_write4(client, DIF_BPF_COEFF67, 0x00510046);
2517 cx25840_write4(client, DIF_BPF_COEFF89, 0xfff9ff6d);
2518 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfed0fe7c);
2519 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfecefff0);
2520 cx25840_write4(client, DIF_BPF_COEFF1415, 0x01aa0356);
2521 cx25840_write4(client, DIF_BPF_COEFF1617, 0x0413032b);
2522 cx25840_write4(client, DIF_BPF_COEFF1819, 0x007ffcc5);
2523 cx25840_write4(client, DIF_BPF_COEFF2021, 0xf96cf812);
2524 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf9cefe87);
2525 cx25840_write4(client, DIF_BPF_COEFF2425, 0x04c90a2c);
2526 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0c4309b4);
2527 cx25840_write4(client, DIF_BPF_COEFF2829, 0x02f3fa4a);
2528 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf30ef046);
2529 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf361fb7a);
2530 cx25840_write4(client, DIF_BPF_COEFF3435, 0x059b0de0);
2531 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2532 break;
2533
2534 case 5000000:
2535 cx25840_write4(client, DIF_BPF_COEFF01, 0xfffffffd);
2536 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff9fffa);
2537 cx25840_write4(client, DIF_BPF_COEFF45, 0x000a002d);
2538 cx25840_write4(client, DIF_BPF_COEFF67, 0x00570067);
2539 cx25840_write4(client, DIF_BPF_COEFF89, 0x0037ffb5);
2540 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfefffe68);
2541 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe62ff3d);
2542 cx25840_write4(client, DIF_BPF_COEFF1415, 0x00ec02e3);
2543 cx25840_write4(client, DIF_BPF_COEFF1617, 0x043503f6);
2544 cx25840_write4(client, DIF_BPF_COEFF1819, 0x01befe05);
2545 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfa27f7ee);
2546 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf8c6fcf8);
2547 cx25840_write4(client, DIF_BPF_COEFF2425, 0x034c0954);
2548 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0c5c0aa4);
2549 cx25840_write4(client, DIF_BPF_COEFF2829, 0x044cfb7e);
2550 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf3b1f03f);
2551 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf2e2fae1);
2552 cx25840_write4(client, DIF_BPF_COEFF3435, 0x05340dc0);
2553 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2554 break;
2555
2556 case 5100000:
2557 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffd);
2558 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff8fff4);
2559 cx25840_write4(client, DIF_BPF_COEFF45, 0xfffd001e);
2560 cx25840_write4(client, DIF_BPF_COEFF67, 0x0051007b);
2561 cx25840_write4(client, DIF_BPF_COEFF89, 0x006e0006);
2562 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff48fe7c);
2563 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe1bfe9a);
2564 cx25840_write4(client, DIF_BPF_COEFF1415, 0x001d023e);
2565 cx25840_write4(client, DIF_BPF_COEFF1617, 0x04130488);
2566 cx25840_write4(client, DIF_BPF_COEFF1819, 0x02e6ff5b);
2567 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfb1ef812);
2568 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf7f7fb7f);
2569 cx25840_write4(client, DIF_BPF_COEFF2425, 0x01bc084e);
2570 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0c430b72);
2571 cx25840_write4(client, DIF_BPF_COEFF2829, 0x059afcba);
2572 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf467f046);
2573 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf26cfa4a);
2574 cx25840_write4(client, DIF_BPF_COEFF3435, 0x04cd0da0);
2575 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2576 break;
2577
2578 case 5200000:
2579 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffe);
2580 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff8ffef);
2581 cx25840_write4(client, DIF_BPF_COEFF45, 0xfff00009);
2582 cx25840_write4(client, DIF_BPF_COEFF67, 0x003f007f);
2583 cx25840_write4(client, DIF_BPF_COEFF89, 0x00980056);
2584 cx25840_write4(client, DIF_BPF_COEFF1011, 0xffa5feb6);
2585 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe00fe15);
2586 cx25840_write4(client, DIF_BPF_COEFF1415, 0xff4b0170);
2587 cx25840_write4(client, DIF_BPF_COEFF1617, 0x03b004d7);
2588 cx25840_write4(client, DIF_BPF_COEFF1819, 0x03e800b9);
2589 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfc48f87f);
2590 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf768fa23);
2591 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0022071f);
2592 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0bf90c1b);
2593 cx25840_write4(client, DIF_BPF_COEFF2829, 0x06dafdfd);
2594 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf52df05e);
2595 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf1fef9b5);
2596 cx25840_write4(client, DIF_BPF_COEFF3435, 0x04640d7f);
2597 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2598 break;
2599
2600 case 5300000:
2601 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000ffff);
2602 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff9ffee);
2603 cx25840_write4(client, DIF_BPF_COEFF45, 0xffe6fff3);
2604 cx25840_write4(client, DIF_BPF_COEFF67, 0x00250072);
2605 cx25840_write4(client, DIF_BPF_COEFF89, 0x00af009c);
2606 cx25840_write4(client, DIF_BPF_COEFF1011, 0x000cff10);
2607 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe13fdb8);
2608 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfe870089);
2609 cx25840_write4(client, DIF_BPF_COEFF1617, 0x031104e1);
2610 cx25840_write4(client, DIF_BPF_COEFF1819, 0x04b8020f);
2611 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfd98f92f);
2612 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf71df8f0);
2613 cx25840_write4(client, DIF_BPF_COEFF2425, 0xfe8805ce);
2614 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0b7e0c9c);
2615 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0808ff44);
2616 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf603f086);
2617 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf19af922);
2618 cx25840_write4(client, DIF_BPF_COEFF3435, 0x03fb0d5e);
2619 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2620 break;
2621
2622 case 5400000:
2623 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000001);
2624 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffcffef);
2625 cx25840_write4(client, DIF_BPF_COEFF45, 0xffe0ffe0);
2626 cx25840_write4(client, DIF_BPF_COEFF67, 0x00050056);
2627 cx25840_write4(client, DIF_BPF_COEFF89, 0x00b000d1);
2628 cx25840_write4(client, DIF_BPF_COEFF1011, 0x0071ff82);
2629 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe53fd8c);
2630 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfddfff99);
2631 cx25840_write4(client, DIF_BPF_COEFF1617, 0x024104a3);
2632 cx25840_write4(client, DIF_BPF_COEFF1819, 0x054a034d);
2633 cx25840_write4(client, DIF_BPF_COEFF2021, 0xff01fa1e);
2634 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf717f7ed);
2635 cx25840_write4(client, DIF_BPF_COEFF2425, 0xfcf50461);
2636 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0ad50cf4);
2637 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0921008d);
2638 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf6e7f0bd);
2639 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf13ff891);
2640 cx25840_write4(client, DIF_BPF_COEFF3435, 0x03920d3b);
2641 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2642 break;
2643
2644 case 5500000:
2645 cx25840_write4(client, DIF_BPF_COEFF01, 0x00010002);
2646 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffffff3);
2647 cx25840_write4(client, DIF_BPF_COEFF45, 0xffdeffd1);
2648 cx25840_write4(client, DIF_BPF_COEFF67, 0xffe5002f);
2649 cx25840_write4(client, DIF_BPF_COEFF89, 0x009c00ed);
2650 cx25840_write4(client, DIF_BPF_COEFF1011, 0x00cb0000);
2651 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfebafd94);
2652 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd61feb0);
2653 cx25840_write4(client, DIF_BPF_COEFF1617, 0x014d0422);
2654 cx25840_write4(client, DIF_BPF_COEFF1819, 0x05970464);
2655 cx25840_write4(client, DIF_BPF_COEFF2021, 0x0074fb41);
2656 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf759f721);
2657 cx25840_write4(client, DIF_BPF_COEFF2425, 0xfb7502de);
2658 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0a000d21);
2659 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0a2201d4);
2660 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf7d9f104);
2661 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf0edf804);
2662 cx25840_write4(client, DIF_BPF_COEFF3435, 0x03280d19);
2663 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2664 break;
2665
2666 case 5600000:
2667 cx25840_write4(client, DIF_BPF_COEFF01, 0x00010003);
2668 cx25840_write4(client, DIF_BPF_COEFF23, 0x0003fffa);
2669 cx25840_write4(client, DIF_BPF_COEFF45, 0xffe3ffc9);
2670 cx25840_write4(client, DIF_BPF_COEFF67, 0xffc90002);
2671 cx25840_write4(client, DIF_BPF_COEFF89, 0x007500ef);
2672 cx25840_write4(client, DIF_BPF_COEFF1011, 0x010e007e);
2673 cx25840_write4(client, DIF_BPF_COEFF1213, 0xff3dfdcf);
2674 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd16fddd);
2675 cx25840_write4(client, DIF_BPF_COEFF1617, 0x00440365);
2676 cx25840_write4(client, DIF_BPF_COEFF1819, 0x059b0548);
2677 cx25840_write4(client, DIF_BPF_COEFF2021, 0x01e3fc90);
2678 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf7dff691);
2679 cx25840_write4(client, DIF_BPF_COEFF2425, 0xfa0f014d);
2680 cx25840_write4(client, DIF_BPF_COEFF2627, 0x09020d23);
2681 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0b0a0318);
2682 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf8d7f15a);
2683 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf0a5f779);
2684 cx25840_write4(client, DIF_BPF_COEFF3435, 0x02bd0cf6);
2685 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2686 break;
2687
2688 case 5700000:
2689 cx25840_write4(client, DIF_BPF_COEFF01, 0x00010003);
2690 cx25840_write4(client, DIF_BPF_COEFF23, 0x00060001);
2691 cx25840_write4(client, DIF_BPF_COEFF45, 0xffecffc9);
2692 cx25840_write4(client, DIF_BPF_COEFF67, 0xffb4ffd4);
2693 cx25840_write4(client, DIF_BPF_COEFF89, 0x004000d5);
2694 cx25840_write4(client, DIF_BPF_COEFF1011, 0x013600f0);
2695 cx25840_write4(client, DIF_BPF_COEFF1213, 0xffd3fe39);
2696 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd04fd31);
2697 cx25840_write4(client, DIF_BPF_COEFF1617, 0xff360277);
2698 cx25840_write4(client, DIF_BPF_COEFF1819, 0x055605ef);
2699 cx25840_write4(client, DIF_BPF_COEFF2021, 0x033efdfe);
2700 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf8a5f642);
2701 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf8cbffb6);
2702 cx25840_write4(client, DIF_BPF_COEFF2627, 0x07e10cfb);
2703 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0bd50456);
2704 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf9dff1be);
2705 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf067f6f2);
2706 cx25840_write4(client, DIF_BPF_COEFF3435, 0x02520cd2);
2707 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2708 break;
2709
2710 case 5800000:
2711 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000003);
2712 cx25840_write4(client, DIF_BPF_COEFF23, 0x00080009);
2713 cx25840_write4(client, DIF_BPF_COEFF45, 0xfff8ffd2);
2714 cx25840_write4(client, DIF_BPF_COEFF67, 0xffaaffac);
2715 cx25840_write4(client, DIF_BPF_COEFF89, 0x000200a3);
2716 cx25840_write4(client, DIF_BPF_COEFF1011, 0x013c014a);
2717 cx25840_write4(client, DIF_BPF_COEFF1213, 0x006dfec9);
2718 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd2bfcb7);
2719 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfe350165);
2720 cx25840_write4(client, DIF_BPF_COEFF1819, 0x04cb0651);
2721 cx25840_write4(client, DIF_BPF_COEFF2021, 0x0477ff7e);
2722 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf9a5f635);
2723 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf7b1fe20);
2724 cx25840_write4(client, DIF_BPF_COEFF2627, 0x069f0ca8);
2725 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0c81058b);
2726 cx25840_write4(client, DIF_BPF_COEFF3031, 0xfaf0f231);
2727 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf033f66d);
2728 cx25840_write4(client, DIF_BPF_COEFF3435, 0x01e60cae);
2729 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2730 break;
2731
2732 case 5900000:
2733 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000002);
2734 cx25840_write4(client, DIF_BPF_COEFF23, 0x0009000e);
2735 cx25840_write4(client, DIF_BPF_COEFF45, 0x0005ffe1);
2736 cx25840_write4(client, DIF_BPF_COEFF67, 0xffacff90);
2737 cx25840_write4(client, DIF_BPF_COEFF89, 0xffc5005f);
2738 cx25840_write4(client, DIF_BPF_COEFF1011, 0x01210184);
2739 cx25840_write4(client, DIF_BPF_COEFF1213, 0x00fcff72);
2740 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd8afc77);
2741 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfd51003f);
2742 cx25840_write4(client, DIF_BPF_COEFF1819, 0x04020669);
2743 cx25840_write4(client, DIF_BPF_COEFF2021, 0x05830103);
2744 cx25840_write4(client, DIF_BPF_COEFF2223, 0xfad7f66b);
2745 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf6c8fc93);
2746 cx25840_write4(client, DIF_BPF_COEFF2627, 0x05430c2b);
2747 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0d0d06b5);
2748 cx25840_write4(client, DIF_BPF_COEFF3031, 0xfc08f2b2);
2749 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf00af5ec);
2750 cx25840_write4(client, DIF_BPF_COEFF3435, 0x017b0c89);
2751 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2752 break;
2753
2754 case 6000000:
2755 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000001);
2756 cx25840_write4(client, DIF_BPF_COEFF23, 0x00070012);
2757 cx25840_write4(client, DIF_BPF_COEFF45, 0x0012fff5);
2758 cx25840_write4(client, DIF_BPF_COEFF67, 0xffbaff82);
2759 cx25840_write4(client, DIF_BPF_COEFF89, 0xff8e000f);
2760 cx25840_write4(client, DIF_BPF_COEFF1011, 0x00e80198);
2761 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01750028);
2762 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfe18fc75);
2763 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc99ff15);
2764 cx25840_write4(client, DIF_BPF_COEFF1819, 0x03050636);
2765 cx25840_write4(client, DIF_BPF_COEFF2021, 0x0656027f);
2766 cx25840_write4(client, DIF_BPF_COEFF2223, 0xfc32f6e2);
2767 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf614fb17);
2768 cx25840_write4(client, DIF_BPF_COEFF2627, 0x03d20b87);
2769 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0d7707d2);
2770 cx25840_write4(client, DIF_BPF_COEFF3031, 0xfd26f341);
2771 cx25840_write4(client, DIF_BPF_COEFF3233, 0xefeaf56f);
2772 cx25840_write4(client, DIF_BPF_COEFF3435, 0x010f0c64);
2773 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2774 break;
2775
2776 case 6100000:
2777 cx25840_write4(client, DIF_BPF_COEFF01, 0xffff0000);
2778 cx25840_write4(client, DIF_BPF_COEFF23, 0x00050012);
2779 cx25840_write4(client, DIF_BPF_COEFF45, 0x001c000b);
2780 cx25840_write4(client, DIF_BPF_COEFF67, 0xffd1ff84);
2781 cx25840_write4(client, DIF_BPF_COEFF89, 0xff66ffbe);
2782 cx25840_write4(client, DIF_BPF_COEFF1011, 0x00960184);
2783 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01cd00da);
2784 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfeccfcb2);
2785 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc17fdf9);
2786 cx25840_write4(client, DIF_BPF_COEFF1819, 0x01e005bc);
2787 cx25840_write4(client, DIF_BPF_COEFF2021, 0x06e703e4);
2788 cx25840_write4(client, DIF_BPF_COEFF2223, 0xfdabf798);
2789 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf599f9b3);
2790 cx25840_write4(client, DIF_BPF_COEFF2627, 0x02510abd);
2791 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0dbf08df);
2792 cx25840_write4(client, DIF_BPF_COEFF3031, 0xfe48f3dc);
2793 cx25840_write4(client, DIF_BPF_COEFF3233, 0xefd5f4f6);
2794 cx25840_write4(client, DIF_BPF_COEFF3435, 0x00a20c3e);
2795 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2796 break;
2797
2798 case 6200000:
2799 cx25840_write4(client, DIF_BPF_COEFF01, 0xfffffffe);
2800 cx25840_write4(client, DIF_BPF_COEFF23, 0x0002000f);
2801 cx25840_write4(client, DIF_BPF_COEFF45, 0x0021001f);
2802 cx25840_write4(client, DIF_BPF_COEFF67, 0xfff0ff97);
2803 cx25840_write4(client, DIF_BPF_COEFF89, 0xff50ff74);
2804 cx25840_write4(client, DIF_BPF_COEFF1011, 0x0034014a);
2805 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01fa0179);
2806 cx25840_write4(client, DIF_BPF_COEFF1415, 0xff97fd2a);
2807 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfbd3fcfa);
2808 cx25840_write4(client, DIF_BPF_COEFF1819, 0x00a304fe);
2809 cx25840_write4(client, DIF_BPF_COEFF2021, 0x07310525);
2810 cx25840_write4(client, DIF_BPF_COEFF2223, 0xff37f886);
2811 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf55cf86e);
2812 cx25840_write4(client, DIF_BPF_COEFF2627, 0x00c709d0);
2813 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0de209db);
2814 cx25840_write4(client, DIF_BPF_COEFF3031, 0xff6df484);
2815 cx25840_write4(client, DIF_BPF_COEFF3233, 0xefcbf481);
2816 cx25840_write4(client, DIF_BPF_COEFF3435, 0x00360c18);
2817 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2818 break;
2819
2820 case 6300000:
2821 cx25840_write4(client, DIF_BPF_COEFF01, 0xfffffffd);
2822 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffe000a);
2823 cx25840_write4(client, DIF_BPF_COEFF45, 0x0021002f);
2824 cx25840_write4(client, DIF_BPF_COEFF67, 0x0010ffb8);
2825 cx25840_write4(client, DIF_BPF_COEFF89, 0xff50ff3b);
2826 cx25840_write4(client, DIF_BPF_COEFF1011, 0xffcc00f0);
2827 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01fa01fa);
2828 cx25840_write4(client, DIF_BPF_COEFF1415, 0x0069fdd4);
2829 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfbd3fc26);
2830 cx25840_write4(client, DIF_BPF_COEFF1819, 0xff5d0407);
2831 cx25840_write4(client, DIF_BPF_COEFF2021, 0x07310638);
2832 cx25840_write4(client, DIF_BPF_COEFF2223, 0x00c9f9a8);
2833 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf55cf74e);
2834 cx25840_write4(client, DIF_BPF_COEFF2627, 0xff3908c3);
2835 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0de20ac3);
2836 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0093f537);
2837 cx25840_write4(client, DIF_BPF_COEFF3233, 0xefcbf410);
2838 cx25840_write4(client, DIF_BPF_COEFF3435, 0xffca0bf2);
2839 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2840 break;
2841
2842 case 6400000:
2843 cx25840_write4(client, DIF_BPF_COEFF01, 0xfffffffd);
2844 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffb0003);
2845 cx25840_write4(client, DIF_BPF_COEFF45, 0x001c0037);
2846 cx25840_write4(client, DIF_BPF_COEFF67, 0x002fffe2);
2847 cx25840_write4(client, DIF_BPF_COEFF89, 0xff66ff17);
2848 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff6a007e);
2849 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01cd0251);
2850 cx25840_write4(client, DIF_BPF_COEFF1415, 0x0134fea5);
2851 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc17fb8b);
2852 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfe2002e0);
2853 cx25840_write4(client, DIF_BPF_COEFF2021, 0x06e70713);
2854 cx25840_write4(client, DIF_BPF_COEFF2223, 0x0255faf5);
2855 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf599f658);
2856 cx25840_write4(client, DIF_BPF_COEFF2627, 0xfdaf0799);
2857 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0dbf0b96);
2858 cx25840_write4(client, DIF_BPF_COEFF3031, 0x01b8f5f5);
2859 cx25840_write4(client, DIF_BPF_COEFF3233, 0xefd5f3a3);
2860 cx25840_write4(client, DIF_BPF_COEFF3435, 0xff5e0bca);
2861 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2862 break;
2863
2864 case 6500000:
2865 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffd);
2866 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff9fffb);
2867 cx25840_write4(client, DIF_BPF_COEFF45, 0x00120037);
2868 cx25840_write4(client, DIF_BPF_COEFF67, 0x00460010);
2869 cx25840_write4(client, DIF_BPF_COEFF89, 0xff8eff0f);
2870 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff180000);
2871 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01750276);
2872 cx25840_write4(client, DIF_BPF_COEFF1415, 0x01e8ff8d);
2873 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc99fb31);
2874 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfcfb0198);
2875 cx25840_write4(client, DIF_BPF_COEFF2021, 0x065607ad);
2876 cx25840_write4(client, DIF_BPF_COEFF2223, 0x03cefc64);
2877 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf614f592);
2878 cx25840_write4(client, DIF_BPF_COEFF2627, 0xfc2e0656);
2879 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0d770c52);
2880 cx25840_write4(client, DIF_BPF_COEFF3031, 0x02daf6bd);
2881 cx25840_write4(client, DIF_BPF_COEFF3233, 0xefeaf33b);
2882 cx25840_write4(client, DIF_BPF_COEFF3435, 0xfef10ba3);
2883 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2884 break;
2885
2886 case 6600000:
2887 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffe);
2888 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff7fff5);
2889 cx25840_write4(client, DIF_BPF_COEFF45, 0x0005002f);
2890 cx25840_write4(client, DIF_BPF_COEFF67, 0x0054003c);
2891 cx25840_write4(client, DIF_BPF_COEFF89, 0xffc5ff22);
2892 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfedfff82);
2893 cx25840_write4(client, DIF_BPF_COEFF1213, 0x00fc0267);
2894 cx25840_write4(client, DIF_BPF_COEFF1415, 0x0276007e);
2895 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfd51fb1c);
2896 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfbfe003e);
2897 cx25840_write4(client, DIF_BPF_COEFF2021, 0x05830802);
2898 cx25840_write4(client, DIF_BPF_COEFF2223, 0x0529fdec);
2899 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf6c8f4fe);
2900 cx25840_write4(client, DIF_BPF_COEFF2627, 0xfabd04ff);
2901 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0d0d0cf6);
2902 cx25840_write4(client, DIF_BPF_COEFF3031, 0x03f8f78f);
2903 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf00af2d7);
2904 cx25840_write4(client, DIF_BPF_COEFF3435, 0xfe850b7b);
2905 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2906 break;
2907
2908 case 6700000:
2909 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000ffff);
2910 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff8fff0);
2911 cx25840_write4(client, DIF_BPF_COEFF45, 0xfff80020);
2912 cx25840_write4(client, DIF_BPF_COEFF67, 0x00560060);
2913 cx25840_write4(client, DIF_BPF_COEFF89, 0x0002ff4e);
2914 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfec4ff10);
2915 cx25840_write4(client, DIF_BPF_COEFF1213, 0x006d0225);
2916 cx25840_write4(client, DIF_BPF_COEFF1415, 0x02d50166);
2917 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfe35fb4e);
2918 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfb35fee1);
2919 cx25840_write4(client, DIF_BPF_COEFF2021, 0x0477080e);
2920 cx25840_write4(client, DIF_BPF_COEFF2223, 0x065bff82);
2921 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf7b1f4a0);
2922 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf9610397);
2923 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0c810d80);
2924 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0510f869);
2925 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf033f278);
2926 cx25840_write4(client, DIF_BPF_COEFF3435, 0xfe1a0b52);
2927 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2928 break;
2929
2930 case 6800000:
2931 cx25840_write4(client, DIF_BPF_COEFF01, 0x00010000);
2932 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffaffee);
2933 cx25840_write4(client, DIF_BPF_COEFF45, 0xffec000c);
2934 cx25840_write4(client, DIF_BPF_COEFF67, 0x004c0078);
2935 cx25840_write4(client, DIF_BPF_COEFF89, 0x0040ff8e);
2936 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfecafeb6);
2937 cx25840_write4(client, DIF_BPF_COEFF1213, 0xffd301b6);
2938 cx25840_write4(client, DIF_BPF_COEFF1415, 0x02fc0235);
2939 cx25840_write4(client, DIF_BPF_COEFF1617, 0xff36fbc5);
2940 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfaaafd90);
2941 cx25840_write4(client, DIF_BPF_COEFF2021, 0x033e07d2);
2942 cx25840_write4(client, DIF_BPF_COEFF2223, 0x075b011b);
2943 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf8cbf47a);
2944 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf81f0224);
2945 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0bd50def);
2946 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0621f94b);
2947 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf067f21e);
2948 cx25840_write4(client, DIF_BPF_COEFF3435, 0xfdae0b29);
2949 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2950 break;
2951
2952 case 6900000:
2953 cx25840_write4(client, DIF_BPF_COEFF01, 0x00010001);
2954 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffdffef);
2955 cx25840_write4(client, DIF_BPF_COEFF45, 0xffe3fff6);
2956 cx25840_write4(client, DIF_BPF_COEFF67, 0x0037007f);
2957 cx25840_write4(client, DIF_BPF_COEFF89, 0x0075ffdc);
2958 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfef2fe7c);
2959 cx25840_write4(client, DIF_BPF_COEFF1213, 0xff3d0122);
2960 cx25840_write4(client, DIF_BPF_COEFF1415, 0x02ea02dd);
2961 cx25840_write4(client, DIF_BPF_COEFF1617, 0x0044fc79);
2962 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfa65fc5d);
2963 cx25840_write4(client, DIF_BPF_COEFF2021, 0x01e3074e);
2964 cx25840_write4(client, DIF_BPF_COEFF2223, 0x082102ad);
2965 cx25840_write4(client, DIF_BPF_COEFF2425, 0xfa0ff48c);
2966 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf6fe00a9);
2967 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0b0a0e43);
2968 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0729fa33);
2969 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf0a5f1c9);
2970 cx25840_write4(client, DIF_BPF_COEFF3435, 0xfd430b00);
2971 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2972 break;
2973
2974 case 7000000:
2975 cx25840_write4(client, DIF_BPF_COEFF01, 0x00010002);
2976 cx25840_write4(client, DIF_BPF_COEFF23, 0x0001fff3);
2977 cx25840_write4(client, DIF_BPF_COEFF45, 0xffdeffe2);
2978 cx25840_write4(client, DIF_BPF_COEFF67, 0x001b0076);
2979 cx25840_write4(client, DIF_BPF_COEFF89, 0x009c002d);
2980 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff35fe68);
2981 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfeba0076);
2982 cx25840_write4(client, DIF_BPF_COEFF1415, 0x029f0352);
2983 cx25840_write4(client, DIF_BPF_COEFF1617, 0x014dfd60);
2984 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfa69fb53);
2985 cx25840_write4(client, DIF_BPF_COEFF2021, 0x00740688);
2986 cx25840_write4(client, DIF_BPF_COEFF2223, 0x08a7042d);
2987 cx25840_write4(client, DIF_BPF_COEFF2425, 0xfb75f4d6);
2988 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf600ff2d);
2989 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0a220e7a);
2990 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0827fb22);
2991 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf0edf17a);
2992 cx25840_write4(client, DIF_BPF_COEFF3435, 0xfcd80ad6);
2993 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
2994 break;
2995
2996 case 7100000:
2997 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000003);
2998 cx25840_write4(client, DIF_BPF_COEFF23, 0x0004fff9);
2999 cx25840_write4(client, DIF_BPF_COEFF45, 0xffe0ffd2);
3000 cx25840_write4(client, DIF_BPF_COEFF67, 0xfffb005e);
3001 cx25840_write4(client, DIF_BPF_COEFF89, 0x00b0007a);
3002 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff8ffe7c);
3003 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe53ffc1);
3004 cx25840_write4(client, DIF_BPF_COEFF1415, 0x0221038c);
3005 cx25840_write4(client, DIF_BPF_COEFF1617, 0x0241fe6e);
3006 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfab6fa80);
3007 cx25840_write4(client, DIF_BPF_COEFF2021, 0xff010587);
3008 cx25840_write4(client, DIF_BPF_COEFF2223, 0x08e90590);
3009 cx25840_write4(client, DIF_BPF_COEFF2425, 0xfcf5f556);
3010 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf52bfdb3);
3011 cx25840_write4(client, DIF_BPF_COEFF2829, 0x09210e95);
3012 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0919fc15);
3013 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf13ff12f);
3014 cx25840_write4(client, DIF_BPF_COEFF3435, 0xfc6e0aab);
3015 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3016 break;
3017
3018 case 7200000:
3019 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000003);
3020 cx25840_write4(client, DIF_BPF_COEFF23, 0x00070000);
3021 cx25840_write4(client, DIF_BPF_COEFF45, 0xffe6ffc9);
3022 cx25840_write4(client, DIF_BPF_COEFF67, 0xffdb0039);
3023 cx25840_write4(client, DIF_BPF_COEFF89, 0x00af00b8);
3024 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfff4feb6);
3025 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe13ff10);
3026 cx25840_write4(client, DIF_BPF_COEFF1415, 0x01790388);
3027 cx25840_write4(client, DIF_BPF_COEFF1617, 0x0311ff92);
3028 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfb48f9ed);
3029 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfd980453);
3030 cx25840_write4(client, DIF_BPF_COEFF2223, 0x08e306cd);
3031 cx25840_write4(client, DIF_BPF_COEFF2425, 0xfe88f60a);
3032 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf482fc40);
3033 cx25840_write4(client, DIF_BPF_COEFF2829, 0x08080e93);
3034 cx25840_write4(client, DIF_BPF_COEFF3031, 0x09fdfd0c);
3035 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf19af0ea);
3036 cx25840_write4(client, DIF_BPF_COEFF3435, 0xfc050a81);
3037 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3038 break;
3039
3040 case 7300000:
3041 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000002);
3042 cx25840_write4(client, DIF_BPF_COEFF23, 0x00080008);
3043 cx25840_write4(client, DIF_BPF_COEFF45, 0xfff0ffc9);
3044 cx25840_write4(client, DIF_BPF_COEFF67, 0xffc1000d);
3045 cx25840_write4(client, DIF_BPF_COEFF89, 0x009800e2);
3046 cx25840_write4(client, DIF_BPF_COEFF1011, 0x005bff10);
3047 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe00fe74);
3048 cx25840_write4(client, DIF_BPF_COEFF1415, 0x00b50345);
3049 cx25840_write4(client, DIF_BPF_COEFF1617, 0x03b000bc);
3050 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfc18f9a1);
3051 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfc4802f9);
3052 cx25840_write4(client, DIF_BPF_COEFF2223, 0x089807dc);
3053 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0022f6f0);
3054 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf407fada);
3055 cx25840_write4(client, DIF_BPF_COEFF2829, 0x06da0e74);
3056 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0ad3fe06);
3057 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf1fef0ab);
3058 cx25840_write4(client, DIF_BPF_COEFF3435, 0xfb9c0a55);
3059 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3060 break;
3061
3062 case 7400000:
3063 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000001);
3064 cx25840_write4(client, DIF_BPF_COEFF23, 0x0008000e);
3065 cx25840_write4(client, DIF_BPF_COEFF45, 0xfffdffd0);
3066 cx25840_write4(client, DIF_BPF_COEFF67, 0xffafffdf);
3067 cx25840_write4(client, DIF_BPF_COEFF89, 0x006e00f2);
3068 cx25840_write4(client, DIF_BPF_COEFF1011, 0x00b8ff82);
3069 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe1bfdf8);
3070 cx25840_write4(client, DIF_BPF_COEFF1415, 0xffe302c8);
3071 cx25840_write4(client, DIF_BPF_COEFF1617, 0x041301dc);
3072 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfd1af99e);
3073 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfb1e0183);
3074 cx25840_write4(client, DIF_BPF_COEFF2223, 0x080908b5);
3075 cx25840_write4(client, DIF_BPF_COEFF2425, 0x01bcf801);
3076 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf3bdf985);
3077 cx25840_write4(client, DIF_BPF_COEFF2829, 0x059a0e38);
3078 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0b99ff03);
3079 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf26cf071);
3080 cx25840_write4(client, DIF_BPF_COEFF3435, 0xfb330a2a);
3081 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3082 break;
3083
3084 case 7500000:
3085 cx25840_write4(client, DIF_BPF_COEFF01, 0xffff0000);
3086 cx25840_write4(client, DIF_BPF_COEFF23, 0x00070011);
3087 cx25840_write4(client, DIF_BPF_COEFF45, 0x000affdf);
3088 cx25840_write4(client, DIF_BPF_COEFF67, 0xffa9ffb5);
3089 cx25840_write4(client, DIF_BPF_COEFF89, 0x003700e6);
3090 cx25840_write4(client, DIF_BPF_COEFF1011, 0x01010000);
3091 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe62fda8);
3092 cx25840_write4(client, DIF_BPF_COEFF1415, 0xff140219);
3093 cx25840_write4(client, DIF_BPF_COEFF1617, 0x043502e1);
3094 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfe42f9e6);
3095 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfa270000);
3096 cx25840_write4(client, DIF_BPF_COEFF2223, 0x073a0953);
3097 cx25840_write4(client, DIF_BPF_COEFF2425, 0x034cf939);
3098 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf3a4f845);
3099 cx25840_write4(client, DIF_BPF_COEFF2829, 0x044c0de1);
3100 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0c4f0000);
3101 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf2e2f03c);
3102 cx25840_write4(client, DIF_BPF_COEFF3435, 0xfacc09fe);
3103 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3104 break;
3105
3106 case 7600000:
3107 cx25840_write4(client, DIF_BPF_COEFF01, 0xffffffff);
3108 cx25840_write4(client, DIF_BPF_COEFF23, 0x00040012);
3109 cx25840_write4(client, DIF_BPF_COEFF45, 0x0016fff3);
3110 cx25840_write4(client, DIF_BPF_COEFF67, 0xffafff95);
3111 cx25840_write4(client, DIF_BPF_COEFF89, 0xfff900c0);
3112 cx25840_write4(client, DIF_BPF_COEFF1011, 0x0130007e);
3113 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfecefd89);
3114 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfe560146);
3115 cx25840_write4(client, DIF_BPF_COEFF1617, 0x041303bc);
3116 cx25840_write4(client, DIF_BPF_COEFF1819, 0xff81fa76);
3117 cx25840_write4(client, DIF_BPF_COEFF2021, 0xf96cfe7d);
3118 cx25840_write4(client, DIF_BPF_COEFF2223, 0x063209b1);
3119 cx25840_write4(client, DIF_BPF_COEFF2425, 0x04c9fa93);
3120 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf3bdf71e);
3121 cx25840_write4(client, DIF_BPF_COEFF2829, 0x02f30d6e);
3122 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0cf200fd);
3123 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf361f00e);
3124 cx25840_write4(client, DIF_BPF_COEFF3435, 0xfa6509d1);
3125 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3126 break;
3127
3128 case 7700000:
3129 cx25840_write4(client, DIF_BPF_COEFF01, 0xfffffffe);
3130 cx25840_write4(client, DIF_BPF_COEFF23, 0x00010010);
3131 cx25840_write4(client, DIF_BPF_COEFF45, 0x001e0008);
3132 cx25840_write4(client, DIF_BPF_COEFF67, 0xffc1ff84);
3133 cx25840_write4(client, DIF_BPF_COEFF89, 0xffbc0084);
3134 cx25840_write4(client, DIF_BPF_COEFF1011, 0x013e00f0);
3135 cx25840_write4(client, DIF_BPF_COEFF1213, 0xff56fd9f);
3136 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfdb8005c);
3137 cx25840_write4(client, DIF_BPF_COEFF1617, 0x03b00460);
3138 cx25840_write4(client, DIF_BPF_COEFF1819, 0x00c7fb45);
3139 cx25840_write4(client, DIF_BPF_COEFF2021, 0xf8f4fd07);
3140 cx25840_write4(client, DIF_BPF_COEFF2223, 0x04fa09ce);
3141 cx25840_write4(client, DIF_BPF_COEFF2425, 0x062afc07);
3142 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf407f614);
3143 cx25840_write4(client, DIF_BPF_COEFF2829, 0x01920ce0);
3144 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0d8301fa);
3145 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf3e8efe5);
3146 cx25840_write4(client, DIF_BPF_COEFF3435, 0xfa0009a4);
3147 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3148 break;
3149
3150 case 7800000:
3151 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffd);
3152 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffd000b);
3153 cx25840_write4(client, DIF_BPF_COEFF45, 0x0022001d);
3154 cx25840_write4(client, DIF_BPF_COEFF67, 0xffdbff82);
3155 cx25840_write4(client, DIF_BPF_COEFF89, 0xff870039);
3156 cx25840_write4(client, DIF_BPF_COEFF1011, 0x012a014a);
3157 cx25840_write4(client, DIF_BPF_COEFF1213, 0xffedfde7);
3158 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd47ff6b);
3159 cx25840_write4(client, DIF_BPF_COEFF1617, 0x031104c6);
3160 cx25840_write4(client, DIF_BPF_COEFF1819, 0x0202fc4c);
3161 cx25840_write4(client, DIF_BPF_COEFF2021, 0xf8c6fbad);
3162 cx25840_write4(client, DIF_BPF_COEFF2223, 0x039909a7);
3163 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0767fd8e);
3164 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf482f52b);
3165 cx25840_write4(client, DIF_BPF_COEFF2829, 0x002d0c39);
3166 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0e0002f4);
3167 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf477efc2);
3168 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf99b0977);
3169 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3170 break;
3171
3172 case 7900000:
3173 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffd);
3174 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffa0004);
3175 cx25840_write4(client, DIF_BPF_COEFF45, 0x0020002d);
3176 cx25840_write4(client, DIF_BPF_COEFF67, 0xfffbff91);
3177 cx25840_write4(client, DIF_BPF_COEFF89, 0xff61ffe8);
3178 cx25840_write4(client, DIF_BPF_COEFF1011, 0x00f70184);
3179 cx25840_write4(client, DIF_BPF_COEFF1213, 0x0086fe5c);
3180 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd0bfe85);
3181 cx25840_write4(client, DIF_BPF_COEFF1617, 0x024104e5);
3182 cx25840_write4(client, DIF_BPF_COEFF1819, 0x0323fd7d);
3183 cx25840_write4(client, DIF_BPF_COEFF2021, 0xf8e2fa79);
3184 cx25840_write4(client, DIF_BPF_COEFF2223, 0x021d093f);
3185 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0879ff22);
3186 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf52bf465);
3187 cx25840_write4(client, DIF_BPF_COEFF2829, 0xfec70b79);
3188 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0e6803eb);
3189 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf50defa5);
3190 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf937094a);
3191 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3192 break;
3193
3194 case 8000000:
3195 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffe);
3196 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff8fffd);
3197 cx25840_write4(client, DIF_BPF_COEFF45, 0x00190036);
3198 cx25840_write4(client, DIF_BPF_COEFF67, 0x001bffaf);
3199 cx25840_write4(client, DIF_BPF_COEFF89, 0xff4fff99);
3200 cx25840_write4(client, DIF_BPF_COEFF1011, 0x00aa0198);
3201 cx25840_write4(client, DIF_BPF_COEFF1213, 0x0112fef3);
3202 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd09fdb9);
3203 cx25840_write4(client, DIF_BPF_COEFF1617, 0x014d04be);
3204 cx25840_write4(client, DIF_BPF_COEFF1819, 0x041bfecc);
3205 cx25840_write4(client, DIF_BPF_COEFF2021, 0xf947f978);
3206 cx25840_write4(client, DIF_BPF_COEFF2223, 0x00900897);
3207 cx25840_write4(client, DIF_BPF_COEFF2425, 0x095a00b9);
3208 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf600f3c5);
3209 cx25840_write4(client, DIF_BPF_COEFF2829, 0xfd650aa3);
3210 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0ebc04de);
3211 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf5aaef8e);
3212 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf8d5091c);
3213 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3214 break;
3215
3216 case 8100000:
3217 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000ffff);
3218 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff7fff6);
3219 cx25840_write4(client, DIF_BPF_COEFF45, 0x000e0038);
3220 cx25840_write4(client, DIF_BPF_COEFF67, 0x0037ffd7);
3221 cx25840_write4(client, DIF_BPF_COEFF89, 0xff52ff56);
3222 cx25840_write4(client, DIF_BPF_COEFF1011, 0x004b0184);
3223 cx25840_write4(client, DIF_BPF_COEFF1213, 0x0186ffa1);
3224 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd40fd16);
3225 cx25840_write4(client, DIF_BPF_COEFF1617, 0x00440452);
3226 cx25840_write4(client, DIF_BPF_COEFF1819, 0x04de0029);
3227 cx25840_write4(client, DIF_BPF_COEFF2021, 0xf9f2f8b2);
3228 cx25840_write4(client, DIF_BPF_COEFF2223, 0xfefe07b5);
3229 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0a05024d);
3230 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf6fef34d);
3231 cx25840_write4(client, DIF_BPF_COEFF2829, 0xfc0a09b8);
3232 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0efa05cd);
3233 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf64eef7d);
3234 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf87308ed);
3235 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3236 break;
3237
3238 case 8200000:
3239 cx25840_write4(client, DIF_BPF_COEFF01, 0x00010000);
3240 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff8fff0);
3241 cx25840_write4(client, DIF_BPF_COEFF45, 0x00000031);
3242 cx25840_write4(client, DIF_BPF_COEFF67, 0x004c0005);
3243 cx25840_write4(client, DIF_BPF_COEFF89, 0xff6aff27);
3244 cx25840_write4(client, DIF_BPF_COEFF1011, 0xffe4014a);
3245 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01d70057);
3246 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfdacfca6);
3247 cx25840_write4(client, DIF_BPF_COEFF1617, 0xff3603a7);
3248 cx25840_write4(client, DIF_BPF_COEFF1819, 0x05610184);
3249 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfadbf82e);
3250 cx25840_write4(client, DIF_BPF_COEFF2223, 0xfd74069f);
3251 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0a7503d6);
3252 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf81ff2ff);
3253 cx25840_write4(client, DIF_BPF_COEFF2829, 0xfab808b9);
3254 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0f2306b5);
3255 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf6f9ef72);
3256 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf81308bf);
3257 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3258 break;
3259
3260 case 8300000:
3261 cx25840_write4(client, DIF_BPF_COEFF01, 0x00010001);
3262 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffbffee);
3263 cx25840_write4(client, DIF_BPF_COEFF45, 0xfff30022);
3264 cx25840_write4(client, DIF_BPF_COEFF67, 0x00560032);
3265 cx25840_write4(client, DIF_BPF_COEFF89, 0xff95ff10);
3266 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff8000f0);
3267 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01fe0106);
3268 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfe46fc71);
3269 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfe3502c7);
3270 cx25840_write4(client, DIF_BPF_COEFF1819, 0x059e02ce);
3271 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfbf9f7f2);
3272 cx25840_write4(client, DIF_BPF_COEFF2223, 0xfbff055b);
3273 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0aa9054c);
3274 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf961f2db);
3275 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf97507aa);
3276 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0f350797);
3277 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf7a9ef6d);
3278 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf7b40890);
3279 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3280 break;
3281
3282 case 8400000:
3283 cx25840_write4(client, DIF_BPF_COEFF01, 0x00010002);
3284 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffeffee);
3285 cx25840_write4(client, DIF_BPF_COEFF45, 0xffe8000f);
3286 cx25840_write4(client, DIF_BPF_COEFF67, 0x00540058);
3287 cx25840_write4(client, DIF_BPF_COEFF89, 0xffcdff14);
3288 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff29007e);
3289 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01f6019e);
3290 cx25840_write4(client, DIF_BPF_COEFF1415, 0xff01fc7c);
3291 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfd5101bf);
3292 cx25840_write4(client, DIF_BPF_COEFF1819, 0x059203f6);
3293 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfd41f7fe);
3294 cx25840_write4(client, DIF_BPF_COEFF2223, 0xfaa903f3);
3295 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0a9e06a9);
3296 cx25840_write4(client, DIF_BPF_COEFF2627, 0xfabdf2e2);
3297 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf842068b);
3298 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0f320871);
3299 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf85eef6e);
3300 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf7560860);
3301 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3302 break;
3303
3304 case 8500000:
3305 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000003);
3306 cx25840_write4(client, DIF_BPF_COEFF23, 0x0002fff2);
3307 cx25840_write4(client, DIF_BPF_COEFF45, 0xffe1fff9);
3308 cx25840_write4(client, DIF_BPF_COEFF67, 0x00460073);
3309 cx25840_write4(client, DIF_BPF_COEFF89, 0x000bff34);
3310 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfee90000);
3311 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01c10215);
3312 cx25840_write4(client, DIF_BPF_COEFF1415, 0xffd0fcc5);
3313 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc99009d);
3314 cx25840_write4(client, DIF_BPF_COEFF1819, 0x053d04f1);
3315 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfea5f853);
3316 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf97d0270);
3317 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0a5607e4);
3318 cx25840_write4(client, DIF_BPF_COEFF2627, 0xfc2ef314);
3319 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf723055f);
3320 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0f180943);
3321 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf919ef75);
3322 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf6fa0830);
3323 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3324 break;
3325
3326 case 8600000:
3327 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000003);
3328 cx25840_write4(client, DIF_BPF_COEFF23, 0x0005fff8);
3329 cx25840_write4(client, DIF_BPF_COEFF45, 0xffdeffe4);
3330 cx25840_write4(client, DIF_BPF_COEFF67, 0x002f007f);
3331 cx25840_write4(client, DIF_BPF_COEFF89, 0x0048ff6b);
3332 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfec7ff82);
3333 cx25840_write4(client, DIF_BPF_COEFF1213, 0x0163025f);
3334 cx25840_write4(client, DIF_BPF_COEFF1415, 0x00a2fd47);
3335 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc17ff73);
3336 cx25840_write4(client, DIF_BPF_COEFF1819, 0x04a405b2);
3337 cx25840_write4(client, DIF_BPF_COEFF2021, 0x0017f8ed);
3338 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf88500dc);
3339 cx25840_write4(client, DIF_BPF_COEFF2425, 0x09d208f9);
3340 cx25840_write4(client, DIF_BPF_COEFF2627, 0xfdaff370);
3341 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf61c0429);
3342 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0ee80a0b);
3343 cx25840_write4(client, DIF_BPF_COEFF3233, 0xf9d8ef82);
3344 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf6a00800);
3345 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3346 break;
3347
3348 case 8700000:
3349 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000003);
3350 cx25840_write4(client, DIF_BPF_COEFF23, 0x0007ffff);
3351 cx25840_write4(client, DIF_BPF_COEFF45, 0xffe1ffd4);
3352 cx25840_write4(client, DIF_BPF_COEFF67, 0x0010007a);
3353 cx25840_write4(client, DIF_BPF_COEFF89, 0x007cffb2);
3354 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfec6ff10);
3355 cx25840_write4(client, DIF_BPF_COEFF1213, 0x00e60277);
3356 cx25840_write4(client, DIF_BPF_COEFF1415, 0x0168fdf9);
3357 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfbd3fe50);
3358 cx25840_write4(client, DIF_BPF_COEFF1819, 0x03ce0631);
3359 cx25840_write4(client, DIF_BPF_COEFF2021, 0x0188f9c8);
3360 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf7c7ff43);
3361 cx25840_write4(client, DIF_BPF_COEFF2425, 0x091509e3);
3362 cx25840_write4(client, DIF_BPF_COEFF2627, 0xff39f3f6);
3363 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf52d02ea);
3364 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0ea30ac9);
3365 cx25840_write4(client, DIF_BPF_COEFF3233, 0xfa9bef95);
3366 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf64607d0);
3367 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3368 break;
3369
3370 case 8800000:
3371 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000002);
3372 cx25840_write4(client, DIF_BPF_COEFF23, 0x00090007);
3373 cx25840_write4(client, DIF_BPF_COEFF45, 0xffe9ffca);
3374 cx25840_write4(client, DIF_BPF_COEFF67, 0xfff00065);
3375 cx25840_write4(client, DIF_BPF_COEFF89, 0x00a10003);
3376 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfee6feb6);
3377 cx25840_write4(client, DIF_BPF_COEFF1213, 0x0053025b);
3378 cx25840_write4(client, DIF_BPF_COEFF1415, 0x0213fed0);
3379 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfbd3fd46);
3380 cx25840_write4(client, DIF_BPF_COEFF1819, 0x02c70668);
3381 cx25840_write4(client, DIF_BPF_COEFF2021, 0x02eafadb);
3382 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf74bfdae);
3383 cx25840_write4(client, DIF_BPF_COEFF2425, 0x08230a9c);
3384 cx25840_write4(client, DIF_BPF_COEFF2627, 0x00c7f4a3);
3385 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf45b01a6);
3386 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0e480b7c);
3387 cx25840_write4(client, DIF_BPF_COEFF3233, 0xfb61efae);
3388 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf5ef079f);
3389 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3390 break;
3391
3392 case 8900000:
3393 cx25840_write4(client, DIF_BPF_COEFF01, 0xffff0000);
3394 cx25840_write4(client, DIF_BPF_COEFF23, 0x0008000d);
3395 cx25840_write4(client, DIF_BPF_COEFF45, 0xfff5ffc8);
3396 cx25840_write4(client, DIF_BPF_COEFF67, 0xffd10043);
3397 cx25840_write4(client, DIF_BPF_COEFF89, 0x00b20053);
3398 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff24fe7c);
3399 cx25840_write4(client, DIF_BPF_COEFF1213, 0xffb9020c);
3400 cx25840_write4(client, DIF_BPF_COEFF1415, 0x0295ffbb);
3401 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc17fc64);
3402 cx25840_write4(client, DIF_BPF_COEFF1819, 0x019b0654);
3403 cx25840_write4(client, DIF_BPF_COEFF2021, 0x042dfc1c);
3404 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf714fc2a);
3405 cx25840_write4(client, DIF_BPF_COEFF2425, 0x07020b21);
3406 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0251f575);
3407 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf3a7005e);
3408 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0dd80c24);
3409 cx25840_write4(client, DIF_BPF_COEFF3233, 0xfc2aefcd);
3410 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf599076e);
3411 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3412 break;
3413
3414 case 9000000:
3415 cx25840_write4(client, DIF_BPF_COEFF01, 0xffffffff);
3416 cx25840_write4(client, DIF_BPF_COEFF23, 0x00060011);
3417 cx25840_write4(client, DIF_BPF_COEFF45, 0x0002ffcf);
3418 cx25840_write4(client, DIF_BPF_COEFF67, 0xffba0018);
3419 cx25840_write4(client, DIF_BPF_COEFF89, 0x00ad009a);
3420 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff79fe68);
3421 cx25840_write4(client, DIF_BPF_COEFF1213, 0xff260192);
3422 cx25840_write4(client, DIF_BPF_COEFF1415, 0x02e500ab);
3423 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc99fbb6);
3424 cx25840_write4(client, DIF_BPF_COEFF1819, 0x005b05f7);
3425 cx25840_write4(client, DIF_BPF_COEFF2021, 0x0545fd81);
3426 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf723fabf);
3427 cx25840_write4(client, DIF_BPF_COEFF2425, 0x05b80b70);
3428 cx25840_write4(client, DIF_BPF_COEFF2627, 0x03d2f669);
3429 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf313ff15);
3430 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0d550cbf);
3431 cx25840_write4(client, DIF_BPF_COEFF3233, 0xfcf6eff2);
3432 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf544073d);
3433 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3434 break;
3435
3436 case 9100000:
3437 cx25840_write4(client, DIF_BPF_COEFF01, 0xfffffffe);
3438 cx25840_write4(client, DIF_BPF_COEFF23, 0x00030012);
3439 cx25840_write4(client, DIF_BPF_COEFF45, 0x000fffdd);
3440 cx25840_write4(client, DIF_BPF_COEFF67, 0xffacffea);
3441 cx25840_write4(client, DIF_BPF_COEFF89, 0x009300cf);
3442 cx25840_write4(client, DIF_BPF_COEFF1011, 0xffdcfe7c);
3443 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfea600f7);
3444 cx25840_write4(client, DIF_BPF_COEFF1415, 0x02fd0190);
3445 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfd51fb46);
3446 cx25840_write4(client, DIF_BPF_COEFF1819, 0xff150554);
3447 cx25840_write4(client, DIF_BPF_COEFF2021, 0x0627fefd);
3448 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf778f978);
3449 cx25840_write4(client, DIF_BPF_COEFF2425, 0x044d0b87);
3450 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0543f77d);
3451 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf2a0fdcf);
3452 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0cbe0d4e);
3453 cx25840_write4(client, DIF_BPF_COEFF3233, 0xfdc4f01d);
3454 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf4f2070b);
3455 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3456 break;
3457
3458 case 9200000:
3459 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffd);
3460 cx25840_write4(client, DIF_BPF_COEFF23, 0x00000010);
3461 cx25840_write4(client, DIF_BPF_COEFF45, 0x001afff0);
3462 cx25840_write4(client, DIF_BPF_COEFF67, 0xffaaffbf);
3463 cx25840_write4(client, DIF_BPF_COEFF89, 0x006700ed);
3464 cx25840_write4(client, DIF_BPF_COEFF1011, 0x0043feb6);
3465 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe460047);
3466 cx25840_write4(client, DIF_BPF_COEFF1415, 0x02db0258);
3467 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfe35fb1b);
3468 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfddc0473);
3469 cx25840_write4(client, DIF_BPF_COEFF2021, 0x06c90082);
3470 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf811f85e);
3471 cx25840_write4(client, DIF_BPF_COEFF2425, 0x02c90b66);
3472 cx25840_write4(client, DIF_BPF_COEFF2627, 0x069ff8ad);
3473 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf250fc8d);
3474 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0c140dcf);
3475 cx25840_write4(client, DIF_BPF_COEFF3233, 0xfe93f04d);
3476 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf4a106d9);
3477 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3478 break;
3479
3480 case 9300000:
3481 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffd);
3482 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffc000c);
3483 cx25840_write4(client, DIF_BPF_COEFF45, 0x00200006);
3484 cx25840_write4(client, DIF_BPF_COEFF67, 0xffb4ff9c);
3485 cx25840_write4(client, DIF_BPF_COEFF89, 0x002f00ef);
3486 cx25840_write4(client, DIF_BPF_COEFF1011, 0x00a4ff10);
3487 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe0dff92);
3488 cx25840_write4(client, DIF_BPF_COEFF1415, 0x028102f7);
3489 cx25840_write4(client, DIF_BPF_COEFF1617, 0xff36fb37);
3490 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfcbf035e);
3491 cx25840_write4(client, DIF_BPF_COEFF2021, 0x07260202);
3492 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf8e8f778);
3493 cx25840_write4(client, DIF_BPF_COEFF2425, 0x01340b0d);
3494 cx25840_write4(client, DIF_BPF_COEFF2627, 0x07e1f9f4);
3495 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf223fb51);
3496 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0b590e42);
3497 cx25840_write4(client, DIF_BPF_COEFF3233, 0xff64f083);
3498 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf45206a7);
3499 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3500 break;
3501
3502 case 9400000:
3503 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffd);
3504 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff90005);
3505 cx25840_write4(client, DIF_BPF_COEFF45, 0x0022001a);
3506 cx25840_write4(client, DIF_BPF_COEFF67, 0xffc9ff86);
3507 cx25840_write4(client, DIF_BPF_COEFF89, 0xfff000d7);
3508 cx25840_write4(client, DIF_BPF_COEFF1011, 0x00f2ff82);
3509 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe01fee5);
3510 cx25840_write4(client, DIF_BPF_COEFF1415, 0x01f60362);
3511 cx25840_write4(client, DIF_BPF_COEFF1617, 0x0044fb99);
3512 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfbcc0222);
3513 cx25840_write4(client, DIF_BPF_COEFF2021, 0x07380370);
3514 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf9f7f6cc);
3515 cx25840_write4(client, DIF_BPF_COEFF2425, 0xff990a7e);
3516 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0902fb50);
3517 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf21afa1f);
3518 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0a8d0ea6);
3519 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0034f0bf);
3520 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf4050675);
3521 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3522 break;
3523
3524 case 9500000:
3525 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffe);
3526 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff8fffe);
3527 cx25840_write4(client, DIF_BPF_COEFF45, 0x001e002b);
3528 cx25840_write4(client, DIF_BPF_COEFF67, 0xffe5ff81);
3529 cx25840_write4(client, DIF_BPF_COEFF89, 0xffb400a5);
3530 cx25840_write4(client, DIF_BPF_COEFF1011, 0x01280000);
3531 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe24fe50);
3532 cx25840_write4(client, DIF_BPF_COEFF1415, 0x01460390);
3533 cx25840_write4(client, DIF_BPF_COEFF1617, 0x014dfc3a);
3534 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfb1000ce);
3535 cx25840_write4(client, DIF_BPF_COEFF2021, 0x070104bf);
3536 cx25840_write4(client, DIF_BPF_COEFF2223, 0xfb37f65f);
3537 cx25840_write4(client, DIF_BPF_COEFF2425, 0xfe0009bc);
3538 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0a00fcbb);
3539 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf235f8f8);
3540 cx25840_write4(client, DIF_BPF_COEFF3031, 0x09b20efc);
3541 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0105f101);
3542 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf3ba0642);
3543 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3544 break;
3545
3546 case 9600000:
3547 cx25840_write4(client, DIF_BPF_COEFF01, 0x0001ffff);
3548 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff8fff7);
3549 cx25840_write4(client, DIF_BPF_COEFF45, 0x00150036);
3550 cx25840_write4(client, DIF_BPF_COEFF67, 0x0005ff8c);
3551 cx25840_write4(client, DIF_BPF_COEFF89, 0xff810061);
3552 cx25840_write4(client, DIF_BPF_COEFF1011, 0x013d007e);
3553 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe71fddf);
3554 cx25840_write4(client, DIF_BPF_COEFF1415, 0x007c0380);
3555 cx25840_write4(client, DIF_BPF_COEFF1617, 0x0241fd13);
3556 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfa94ff70);
3557 cx25840_write4(client, DIF_BPF_COEFF2021, 0x068005e2);
3558 cx25840_write4(client, DIF_BPF_COEFF2223, 0xfc9bf633);
3559 cx25840_write4(client, DIF_BPF_COEFF2425, 0xfc7308ca);
3560 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0ad5fe30);
3561 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf274f7e0);
3562 cx25840_write4(client, DIF_BPF_COEFF3031, 0x08c90f43);
3563 cx25840_write4(client, DIF_BPF_COEFF3233, 0x01d4f147);
3564 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf371060f);
3565 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3566 break;
3567
3568 case 9700000:
3569 cx25840_write4(client, DIF_BPF_COEFF01, 0x00010001);
3570 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff9fff1);
3571 cx25840_write4(client, DIF_BPF_COEFF45, 0x00090038);
3572 cx25840_write4(client, DIF_BPF_COEFF67, 0x0025ffa7);
3573 cx25840_write4(client, DIF_BPF_COEFF89, 0xff5e0012);
3574 cx25840_write4(client, DIF_BPF_COEFF1011, 0x013200f0);
3575 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfee3fd9b);
3576 cx25840_write4(client, DIF_BPF_COEFF1415, 0xffaa0331);
3577 cx25840_write4(client, DIF_BPF_COEFF1617, 0x0311fe15);
3578 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfa60fe18);
3579 cx25840_write4(client, DIF_BPF_COEFF2021, 0x05bd06d1);
3580 cx25840_write4(client, DIF_BPF_COEFF2223, 0xfe1bf64a);
3581 cx25840_write4(client, DIF_BPF_COEFF2425, 0xfafa07ae);
3582 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0b7effab);
3583 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf2d5f6d7);
3584 cx25840_write4(client, DIF_BPF_COEFF3031, 0x07d30f7a);
3585 cx25840_write4(client, DIF_BPF_COEFF3233, 0x02a3f194);
3586 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf32905dc);
3587 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3588 break;
3589
3590 case 9800000:
3591 cx25840_write4(client, DIF_BPF_COEFF01, 0x00010002);
3592 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffcffee);
3593 cx25840_write4(client, DIF_BPF_COEFF45, 0xfffb0032);
3594 cx25840_write4(client, DIF_BPF_COEFF67, 0x003fffcd);
3595 cx25840_write4(client, DIF_BPF_COEFF89, 0xff4effc1);
3596 cx25840_write4(client, DIF_BPF_COEFF1011, 0x0106014a);
3597 cx25840_write4(client, DIF_BPF_COEFF1213, 0xff6efd8a);
3598 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfedd02aa);
3599 cx25840_write4(client, DIF_BPF_COEFF1617, 0x03b0ff34);
3600 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfa74fcd7);
3601 cx25840_write4(client, DIF_BPF_COEFF2021, 0x04bf0781);
3602 cx25840_write4(client, DIF_BPF_COEFF2223, 0xffaaf6a3);
3603 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf99e066b);
3604 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0bf90128);
3605 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf359f5e1);
3606 cx25840_write4(client, DIF_BPF_COEFF3031, 0x06d20fa2);
3607 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0370f1e5);
3608 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf2e405a8);
3609 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3610 break;
3611
3612 case 9900000:
3613 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000003);
3614 cx25840_write4(client, DIF_BPF_COEFF23, 0xffffffee);
3615 cx25840_write4(client, DIF_BPF_COEFF45, 0xffef0024);
3616 cx25840_write4(client, DIF_BPF_COEFF67, 0x0051fffa);
3617 cx25840_write4(client, DIF_BPF_COEFF89, 0xff54ff77);
3618 cx25840_write4(client, DIF_BPF_COEFF1011, 0x00be0184);
3619 cx25840_write4(client, DIF_BPF_COEFF1213, 0x0006fdad);
3620 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfe2701f3);
3621 cx25840_write4(client, DIF_BPF_COEFF1617, 0x0413005e);
3622 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfad1fbba);
3623 cx25840_write4(client, DIF_BPF_COEFF2021, 0x039007ee);
3624 cx25840_write4(client, DIF_BPF_COEFF2223, 0x013bf73d);
3625 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf868050a);
3626 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0c4302a1);
3627 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf3fdf4fe);
3628 cx25840_write4(client, DIF_BPF_COEFF3031, 0x05c70fba);
3629 cx25840_write4(client, DIF_BPF_COEFF3233, 0x043bf23c);
3630 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf2a10575);
3631 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3632 break;
3633
3634 case 10000000:
3635 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000003);
3636 cx25840_write4(client, DIF_BPF_COEFF23, 0x0003fff1);
3637 cx25840_write4(client, DIF_BPF_COEFF45, 0xffe50011);
3638 cx25840_write4(client, DIF_BPF_COEFF67, 0x00570027);
3639 cx25840_write4(client, DIF_BPF_COEFF89, 0xff70ff3c);
3640 cx25840_write4(client, DIF_BPF_COEFF1011, 0x00620198);
3641 cx25840_write4(client, DIF_BPF_COEFF1213, 0x009efe01);
3642 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd95011a);
3643 cx25840_write4(client, DIF_BPF_COEFF1617, 0x04350183);
3644 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfb71fad0);
3645 cx25840_write4(client, DIF_BPF_COEFF2021, 0x023c0812);
3646 cx25840_write4(client, DIF_BPF_COEFF2223, 0x02c3f811);
3647 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf75e0390);
3648 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0c5c0411);
3649 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf4c1f432);
3650 cx25840_write4(client, DIF_BPF_COEFF3031, 0x04b30fc1);
3651 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0503f297);
3652 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf2610541);
3653 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3654 break;
3655
3656 case 10100000:
3657 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000003);
3658 cx25840_write4(client, DIF_BPF_COEFF23, 0x0006fff7);
3659 cx25840_write4(client, DIF_BPF_COEFF45, 0xffdffffc);
3660 cx25840_write4(client, DIF_BPF_COEFF67, 0x00510050);
3661 cx25840_write4(client, DIF_BPF_COEFF89, 0xff9dff18);
3662 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfffc0184);
3663 cx25840_write4(client, DIF_BPF_COEFF1213, 0x0128fe80);
3664 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd32002e);
3665 cx25840_write4(client, DIF_BPF_COEFF1617, 0x04130292);
3666 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfc4dfa21);
3667 cx25840_write4(client, DIF_BPF_COEFF2021, 0x00d107ee);
3668 cx25840_write4(client, DIF_BPF_COEFF2223, 0x0435f91c);
3669 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf6850205);
3670 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0c430573);
3671 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf5a1f37d);
3672 cx25840_write4(client, DIF_BPF_COEFF3031, 0x03990fba);
3673 cx25840_write4(client, DIF_BPF_COEFF3233, 0x05c7f2f8);
3674 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf222050d);
3675 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3676 break;
3677
3678 case 10200000:
3679 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000002);
3680 cx25840_write4(client, DIF_BPF_COEFF23, 0x0008fffe);
3681 cx25840_write4(client, DIF_BPF_COEFF45, 0xffdfffe7);
3682 cx25840_write4(client, DIF_BPF_COEFF67, 0x003f006e);
3683 cx25840_write4(client, DIF_BPF_COEFF89, 0xffd6ff0f);
3684 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff96014a);
3685 cx25840_write4(client, DIF_BPF_COEFF1213, 0x0197ff1f);
3686 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd05ff3e);
3687 cx25840_write4(client, DIF_BPF_COEFF1617, 0x03b0037c);
3688 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfd59f9b7);
3689 cx25840_write4(client, DIF_BPF_COEFF2021, 0xff5d0781);
3690 cx25840_write4(client, DIF_BPF_COEFF2223, 0x0585fa56);
3691 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf5e4006f);
3692 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0bf906c4);
3693 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf69df2e0);
3694 cx25840_write4(client, DIF_BPF_COEFF3031, 0x02790fa2);
3695 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0688f35d);
3696 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf1e604d8);
3697 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3698 break;
3699
3700 case 10300000:
3701 cx25840_write4(client, DIF_BPF_COEFF01, 0xffff0001);
3702 cx25840_write4(client, DIF_BPF_COEFF23, 0x00090005);
3703 cx25840_write4(client, DIF_BPF_COEFF45, 0xffe4ffd6);
3704 cx25840_write4(client, DIF_BPF_COEFF67, 0x0025007e);
3705 cx25840_write4(client, DIF_BPF_COEFF89, 0x0014ff20);
3706 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff3c00f0);
3707 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01e1ffd0);
3708 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd12fe5c);
3709 cx25840_write4(client, DIF_BPF_COEFF1617, 0x03110433);
3710 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfe88f996);
3711 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfdf106d1);
3712 cx25840_write4(client, DIF_BPF_COEFF2223, 0x06aafbb7);
3713 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf57efed8);
3714 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0b7e07ff);
3715 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf7b0f25e);
3716 cx25840_write4(client, DIF_BPF_COEFF3031, 0x01560f7a);
3717 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0745f3c7);
3718 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf1ac04a4);
3719 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3720 break;
3721
3722 case 10400000:
3723 cx25840_write4(client, DIF_BPF_COEFF01, 0xffffffff);
3724 cx25840_write4(client, DIF_BPF_COEFF23, 0x0008000c);
3725 cx25840_write4(client, DIF_BPF_COEFF45, 0xffedffcb);
3726 cx25840_write4(client, DIF_BPF_COEFF67, 0x0005007d);
3727 cx25840_write4(client, DIF_BPF_COEFF89, 0x0050ff4c);
3728 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfef6007e);
3729 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01ff0086);
3730 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd58fd97);
3731 cx25840_write4(client, DIF_BPF_COEFF1617, 0x024104ad);
3732 cx25840_write4(client, DIF_BPF_COEFF1819, 0xffcaf9c0);
3733 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfc9905e2);
3734 cx25840_write4(client, DIF_BPF_COEFF2223, 0x079afd35);
3735 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf555fd46);
3736 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0ad50920);
3737 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf8d9f1f6);
3738 cx25840_write4(client, DIF_BPF_COEFF3031, 0x00310f43);
3739 cx25840_write4(client, DIF_BPF_COEFF3233, 0x07fdf435);
3740 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf174046f);
3741 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3742 break;
3743
3744 case 10500000:
3745 cx25840_write4(client, DIF_BPF_COEFF01, 0xfffffffe);
3746 cx25840_write4(client, DIF_BPF_COEFF23, 0x00050011);
3747 cx25840_write4(client, DIF_BPF_COEFF45, 0xfffaffc8);
3748 cx25840_write4(client, DIF_BPF_COEFF67, 0xffe5006b);
3749 cx25840_write4(client, DIF_BPF_COEFF89, 0x0082ff8c);
3750 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfecc0000);
3751 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01f00130);
3752 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfdd2fcfc);
3753 cx25840_write4(client, DIF_BPF_COEFF1617, 0x014d04e3);
3754 cx25840_write4(client, DIF_BPF_COEFF1819, 0x010efa32);
3755 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfb6404bf);
3756 cx25840_write4(client, DIF_BPF_COEFF2223, 0x084efec5);
3757 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf569fbc2);
3758 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0a000a23);
3759 cx25840_write4(client, DIF_BPF_COEFF2829, 0xfa15f1ab);
3760 cx25840_write4(client, DIF_BPF_COEFF3031, 0xff0b0efc);
3761 cx25840_write4(client, DIF_BPF_COEFF3233, 0x08b0f4a7);
3762 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf13f043a);
3763 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3764 break;
3765
3766 case 10600000:
3767 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffd);
3768 cx25840_write4(client, DIF_BPF_COEFF23, 0x00020012);
3769 cx25840_write4(client, DIF_BPF_COEFF45, 0x0007ffcd);
3770 cx25840_write4(client, DIF_BPF_COEFF67, 0xffc9004c);
3771 cx25840_write4(client, DIF_BPF_COEFF89, 0x00a4ffd9);
3772 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfec3ff82);
3773 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01b401c1);
3774 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfe76fc97);
3775 cx25840_write4(client, DIF_BPF_COEFF1617, 0x004404d2);
3776 cx25840_write4(client, DIF_BPF_COEFF1819, 0x0245fae8);
3777 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfa5f0370);
3778 cx25840_write4(client, DIF_BPF_COEFF2223, 0x08c1005f);
3779 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf5bcfa52);
3780 cx25840_write4(client, DIF_BPF_COEFF2627, 0x09020b04);
3781 cx25840_write4(client, DIF_BPF_COEFF2829, 0xfb60f17b);
3782 cx25840_write4(client, DIF_BPF_COEFF3031, 0xfde70ea6);
3783 cx25840_write4(client, DIF_BPF_COEFF3233, 0x095df51e);
3784 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf10c0405);
3785 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3786 break;
3787
3788 case 10700000:
3789 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffd);
3790 cx25840_write4(client, DIF_BPF_COEFF23, 0xffff0011);
3791 cx25840_write4(client, DIF_BPF_COEFF45, 0x0014ffdb);
3792 cx25840_write4(client, DIF_BPF_COEFF67, 0xffb40023);
3793 cx25840_write4(client, DIF_BPF_COEFF89, 0x00b2002a);
3794 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfedbff10);
3795 cx25840_write4(client, DIF_BPF_COEFF1213, 0x0150022d);
3796 cx25840_write4(client, DIF_BPF_COEFF1415, 0xff38fc6f);
3797 cx25840_write4(client, DIF_BPF_COEFF1617, 0xff36047b);
3798 cx25840_write4(client, DIF_BPF_COEFF1819, 0x035efbda);
3799 cx25840_write4(client, DIF_BPF_COEFF2021, 0xf9940202);
3800 cx25840_write4(client, DIF_BPF_COEFF2223, 0x08ee01f5);
3801 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf649f8fe);
3802 cx25840_write4(client, DIF_BPF_COEFF2627, 0x07e10bc2);
3803 cx25840_write4(client, DIF_BPF_COEFF2829, 0xfcb6f169);
3804 cx25840_write4(client, DIF_BPF_COEFF3031, 0xfcc60e42);
3805 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0a04f599);
3806 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf0db03d0);
3807 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3808 break;
3809
3810 case 10800000:
3811 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffd);
3812 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffb000d);
3813 cx25840_write4(client, DIF_BPF_COEFF45, 0x001dffed);
3814 cx25840_write4(client, DIF_BPF_COEFF67, 0xffaafff5);
3815 cx25840_write4(client, DIF_BPF_COEFF89, 0x00aa0077);
3816 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff13feb6);
3817 cx25840_write4(client, DIF_BPF_COEFF1213, 0x00ce026b);
3818 cx25840_write4(client, DIF_BPF_COEFF1415, 0x000afc85);
3819 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfe3503e3);
3820 cx25840_write4(client, DIF_BPF_COEFF1819, 0x044cfcfb);
3821 cx25840_write4(client, DIF_BPF_COEFF2021, 0xf90c0082);
3822 cx25840_write4(client, DIF_BPF_COEFF2223, 0x08d5037f);
3823 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf710f7cc);
3824 cx25840_write4(client, DIF_BPF_COEFF2627, 0x069f0c59);
3825 cx25840_write4(client, DIF_BPF_COEFF2829, 0xfe16f173);
3826 cx25840_write4(client, DIF_BPF_COEFF3031, 0xfbaa0dcf);
3827 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0aa5f617);
3828 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf0ad039b);
3829 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3830 break;
3831
3832 case 10900000:
3833 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffe);
3834 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff90006);
3835 cx25840_write4(client, DIF_BPF_COEFF45, 0x00210003);
3836 cx25840_write4(client, DIF_BPF_COEFF67, 0xffacffc8);
3837 cx25840_write4(client, DIF_BPF_COEFF89, 0x008e00b6);
3838 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff63fe7c);
3839 cx25840_write4(client, DIF_BPF_COEFF1213, 0x003a0275);
3840 cx25840_write4(client, DIF_BPF_COEFF1415, 0x00dafcda);
3841 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfd510313);
3842 cx25840_write4(client, DIF_BPF_COEFF1819, 0x0501fe40);
3843 cx25840_write4(client, DIF_BPF_COEFF2021, 0xf8cbfefd);
3844 cx25840_write4(client, DIF_BPF_COEFF2223, 0x087604f0);
3845 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf80af6c2);
3846 cx25840_write4(client, DIF_BPF_COEFF2627, 0x05430cc8);
3847 cx25840_write4(client, DIF_BPF_COEFF2829, 0xff7af19a);
3848 cx25840_write4(client, DIF_BPF_COEFF3031, 0xfa940d4e);
3849 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0b3ff699);
3850 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf0810365);
3851 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3852 break;
3853
3854 case 11000000:
3855 cx25840_write4(client, DIF_BPF_COEFF01, 0x0001ffff);
3856 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff8ffff);
3857 cx25840_write4(client, DIF_BPF_COEFF45, 0x00210018);
3858 cx25840_write4(client, DIF_BPF_COEFF67, 0xffbaffa3);
3859 cx25840_write4(client, DIF_BPF_COEFF89, 0x006000e1);
3860 cx25840_write4(client, DIF_BPF_COEFF1011, 0xffc4fe68);
3861 cx25840_write4(client, DIF_BPF_COEFF1213, 0xffa0024b);
3862 cx25840_write4(client, DIF_BPF_COEFF1415, 0x019afd66);
3863 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc990216);
3864 cx25840_write4(client, DIF_BPF_COEFF1819, 0x0575ff99);
3865 cx25840_write4(client, DIF_BPF_COEFF2021, 0xf8d4fd81);
3866 cx25840_write4(client, DIF_BPF_COEFF2223, 0x07d40640);
3867 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf932f5e6);
3868 cx25840_write4(client, DIF_BPF_COEFF2627, 0x03d20d0d);
3869 cx25840_write4(client, DIF_BPF_COEFF2829, 0x00dff1de);
3870 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf9860cbf);
3871 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0bd1f71e);
3872 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf058032f);
3873 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3874 break;
3875
3876 case 11100000:
3877 cx25840_write4(client, DIF_BPF_COEFF01, 0x00010000);
3878 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff8fff8);
3879 cx25840_write4(client, DIF_BPF_COEFF45, 0x001b0029);
3880 cx25840_write4(client, DIF_BPF_COEFF67, 0xffd1ff8a);
3881 cx25840_write4(client, DIF_BPF_COEFF89, 0x002600f2);
3882 cx25840_write4(client, DIF_BPF_COEFF1011, 0x002cfe7c);
3883 cx25840_write4(client, DIF_BPF_COEFF1213, 0xff0f01f0);
3884 cx25840_write4(client, DIF_BPF_COEFF1415, 0x023bfe20);
3885 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc1700fa);
3886 cx25840_write4(client, DIF_BPF_COEFF1819, 0x05a200f7);
3887 cx25840_write4(client, DIF_BPF_COEFF2021, 0xf927fc1c);
3888 cx25840_write4(client, DIF_BPF_COEFF2223, 0x06f40765);
3889 cx25840_write4(client, DIF_BPF_COEFF2425, 0xfa82f53b);
3890 cx25840_write4(client, DIF_BPF_COEFF2627, 0x02510d27);
3891 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0243f23d);
3892 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf8810c24);
3893 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0c5cf7a7);
3894 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf03102fa);
3895 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3896 break;
3897
3898 case 11200000:
3899 cx25840_write4(client, DIF_BPF_COEFF01, 0x00010002);
3900 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffafff2);
3901 cx25840_write4(client, DIF_BPF_COEFF45, 0x00110035);
3902 cx25840_write4(client, DIF_BPF_COEFF67, 0xfff0ff81);
3903 cx25840_write4(client, DIF_BPF_COEFF89, 0xffe700e7);
3904 cx25840_write4(client, DIF_BPF_COEFF1011, 0x008ffeb6);
3905 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe94016d);
3906 cx25840_write4(client, DIF_BPF_COEFF1415, 0x02b0fefb);
3907 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfbd3ffd1);
3908 cx25840_write4(client, DIF_BPF_COEFF1819, 0x05850249);
3909 cx25840_write4(client, DIF_BPF_COEFF2021, 0xf9c1fadb);
3910 cx25840_write4(client, DIF_BPF_COEFF2223, 0x05de0858);
3911 cx25840_write4(client, DIF_BPF_COEFF2425, 0xfbf2f4c4);
3912 cx25840_write4(client, DIF_BPF_COEFF2627, 0x00c70d17);
3913 cx25840_write4(client, DIF_BPF_COEFF2829, 0x03a0f2b8);
3914 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf7870b7c);
3915 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0cdff833);
3916 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf00d02c4);
3917 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3918 break;
3919
3920 case 11300000:
3921 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000003);
3922 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffdffee);
3923 cx25840_write4(client, DIF_BPF_COEFF45, 0x00040038);
3924 cx25840_write4(client, DIF_BPF_COEFF67, 0x0010ff88);
3925 cx25840_write4(client, DIF_BPF_COEFF89, 0xffac00c2);
3926 cx25840_write4(client, DIF_BPF_COEFF1011, 0x00e2ff10);
3927 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe3900cb);
3928 cx25840_write4(client, DIF_BPF_COEFF1415, 0x02f1ffe9);
3929 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfbd3feaa);
3930 cx25840_write4(client, DIF_BPF_COEFF1819, 0x05210381);
3931 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfa9cf9c8);
3932 cx25840_write4(client, DIF_BPF_COEFF2223, 0x04990912);
3933 cx25840_write4(client, DIF_BPF_COEFF2425, 0xfd7af484);
3934 cx25840_write4(client, DIF_BPF_COEFF2627, 0xff390cdb);
3935 cx25840_write4(client, DIF_BPF_COEFF2829, 0x04f4f34d);
3936 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf69a0ac9);
3937 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0d5af8c1);
3938 cx25840_write4(client, DIF_BPF_COEFF3435, 0xefec028e);
3939 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3940 break;
3941
3942 case 11400000:
3943 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000003);
3944 cx25840_write4(client, DIF_BPF_COEFF23, 0x0000ffee);
3945 cx25840_write4(client, DIF_BPF_COEFF45, 0xfff60033);
3946 cx25840_write4(client, DIF_BPF_COEFF67, 0x002fff9f);
3947 cx25840_write4(client, DIF_BPF_COEFF89, 0xff7b0087);
3948 cx25840_write4(client, DIF_BPF_COEFF1011, 0x011eff82);
3949 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe080018);
3950 cx25840_write4(client, DIF_BPF_COEFF1415, 0x02f900d8);
3951 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc17fd96);
3952 cx25840_write4(client, DIF_BPF_COEFF1819, 0x04790490);
3953 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfbadf8ed);
3954 cx25840_write4(client, DIF_BPF_COEFF2223, 0x032f098e);
3955 cx25840_write4(client, DIF_BPF_COEFF2425, 0xff10f47d);
3956 cx25840_write4(client, DIF_BPF_COEFF2627, 0xfdaf0c75);
3957 cx25840_write4(client, DIF_BPF_COEFF2829, 0x063cf3fc);
3958 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf5ba0a0b);
3959 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0dccf952);
3960 cx25840_write4(client, DIF_BPF_COEFF3435, 0xefcd0258);
3961 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3962 break;
3963
3964 case 11500000:
3965 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000003);
3966 cx25840_write4(client, DIF_BPF_COEFF23, 0x0004fff1);
3967 cx25840_write4(client, DIF_BPF_COEFF45, 0xffea0026);
3968 cx25840_write4(client, DIF_BPF_COEFF67, 0x0046ffc3);
3969 cx25840_write4(client, DIF_BPF_COEFF89, 0xff5a003c);
3970 cx25840_write4(client, DIF_BPF_COEFF1011, 0x013b0000);
3971 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe04ff63);
3972 cx25840_write4(client, DIF_BPF_COEFF1415, 0x02c801b8);
3973 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc99fca6);
3974 cx25840_write4(client, DIF_BPF_COEFF1819, 0x0397056a);
3975 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfcecf853);
3976 cx25840_write4(client, DIF_BPF_COEFF2223, 0x01ad09c9);
3977 cx25840_write4(client, DIF_BPF_COEFF2425, 0x00acf4ad);
3978 cx25840_write4(client, DIF_BPF_COEFF2627, 0xfc2e0be7);
3979 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0773f4c2);
3980 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf4e90943);
3981 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0e35f9e6);
3982 cx25840_write4(client, DIF_BPF_COEFF3435, 0xefb10221);
3983 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
3984 break;
3985
3986 case 11600000:
3987 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000002);
3988 cx25840_write4(client, DIF_BPF_COEFF23, 0x0007fff6);
3989 cx25840_write4(client, DIF_BPF_COEFF45, 0xffe20014);
3990 cx25840_write4(client, DIF_BPF_COEFF67, 0x0054ffee);
3991 cx25840_write4(client, DIF_BPF_COEFF89, 0xff4effeb);
3992 cx25840_write4(client, DIF_BPF_COEFF1011, 0x0137007e);
3993 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe2efebb);
3994 cx25840_write4(client, DIF_BPF_COEFF1415, 0x0260027a);
3995 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfd51fbe6);
3996 cx25840_write4(client, DIF_BPF_COEFF1819, 0x02870605);
3997 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfe4af7fe);
3998 cx25840_write4(client, DIF_BPF_COEFF2223, 0x001d09c1);
3999 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0243f515);
4000 cx25840_write4(client, DIF_BPF_COEFF2627, 0xfabd0b32);
4001 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0897f59e);
4002 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf4280871);
4003 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0e95fa7c);
4004 cx25840_write4(client, DIF_BPF_COEFF3435, 0xef9701eb);
4005 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4006 break;
4007
4008 case 11700000:
4009 cx25840_write4(client, DIF_BPF_COEFF01, 0xffff0001);
4010 cx25840_write4(client, DIF_BPF_COEFF23, 0x0008fffd);
4011 cx25840_write4(client, DIF_BPF_COEFF45, 0xffdeffff);
4012 cx25840_write4(client, DIF_BPF_COEFF67, 0x0056001d);
4013 cx25840_write4(client, DIF_BPF_COEFF89, 0xff57ff9c);
4014 cx25840_write4(client, DIF_BPF_COEFF1011, 0x011300f0);
4015 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe82fe2e);
4016 cx25840_write4(client, DIF_BPF_COEFF1415, 0x01ca0310);
4017 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfe35fb62);
4018 cx25840_write4(client, DIF_BPF_COEFF1819, 0x0155065a);
4019 cx25840_write4(client, DIF_BPF_COEFF2021, 0xffbaf7f2);
4020 cx25840_write4(client, DIF_BPF_COEFF2223, 0xfe8c0977);
4021 cx25840_write4(client, DIF_BPF_COEFF2425, 0x03cef5b2);
4022 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf9610a58);
4023 cx25840_write4(client, DIF_BPF_COEFF2829, 0x09a5f68f);
4024 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf3790797);
4025 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0eebfb14);
4026 cx25840_write4(client, DIF_BPF_COEFF3435, 0xef8001b5);
4027 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4028 break;
4029
4030 case 11800000:
4031 cx25840_write4(client, DIF_BPF_COEFF01, 0xffff0000);
4032 cx25840_write4(client, DIF_BPF_COEFF23, 0x00080004);
4033 cx25840_write4(client, DIF_BPF_COEFF45, 0xffe0ffe9);
4034 cx25840_write4(client, DIF_BPF_COEFF67, 0x004c0047);
4035 cx25840_write4(client, DIF_BPF_COEFF89, 0xff75ff58);
4036 cx25840_write4(client, DIF_BPF_COEFF1011, 0x00d1014a);
4037 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfef9fdc8);
4038 cx25840_write4(client, DIF_BPF_COEFF1415, 0x0111036f);
4039 cx25840_write4(client, DIF_BPF_COEFF1617, 0xff36fb21);
4040 cx25840_write4(client, DIF_BPF_COEFF1819, 0x00120665);
4041 cx25840_write4(client, DIF_BPF_COEFF2021, 0x012df82e);
4042 cx25840_write4(client, DIF_BPF_COEFF2223, 0xfd0708ec);
4043 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0542f682);
4044 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf81f095c);
4045 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0a9af792);
4046 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf2db06b5);
4047 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0f38fbad);
4048 cx25840_write4(client, DIF_BPF_COEFF3435, 0xef6c017e);
4049 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4050 break;
4051
4052 case 11900000:
4053 cx25840_write4(client, DIF_BPF_COEFF01, 0xffffffff);
4054 cx25840_write4(client, DIF_BPF_COEFF23, 0x0007000b);
4055 cx25840_write4(client, DIF_BPF_COEFF45, 0xffe7ffd8);
4056 cx25840_write4(client, DIF_BPF_COEFF67, 0x00370068);
4057 cx25840_write4(client, DIF_BPF_COEFF89, 0xffa4ff28);
4058 cx25840_write4(client, DIF_BPF_COEFF1011, 0x00790184);
4059 cx25840_write4(client, DIF_BPF_COEFF1213, 0xff87fd91);
4060 cx25840_write4(client, DIF_BPF_COEFF1415, 0x00430392);
4061 cx25840_write4(client, DIF_BPF_COEFF1617, 0x0044fb26);
4062 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfece0626);
4063 cx25840_write4(client, DIF_BPF_COEFF2021, 0x0294f8b2);
4064 cx25840_write4(client, DIF_BPF_COEFF2223, 0xfb990825);
4065 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0698f77f);
4066 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf6fe0842);
4067 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0b73f8a7);
4068 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf25105cd);
4069 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0f7bfc48);
4070 cx25840_write4(client, DIF_BPF_COEFF3435, 0xef5a0148);
4071 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4072 break;
4073
4074 case 12000000:
4075 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffe);
4076 cx25840_write4(client, DIF_BPF_COEFF23, 0x00050010);
4077 cx25840_write4(client, DIF_BPF_COEFF45, 0xfff2ffcc);
4078 cx25840_write4(client, DIF_BPF_COEFF67, 0x001b007b);
4079 cx25840_write4(client, DIF_BPF_COEFF89, 0xffdfff10);
4080 cx25840_write4(client, DIF_BPF_COEFF1011, 0x00140198);
4081 cx25840_write4(client, DIF_BPF_COEFF1213, 0x0020fd8e);
4082 cx25840_write4(client, DIF_BPF_COEFF1415, 0xff710375);
4083 cx25840_write4(client, DIF_BPF_COEFF1617, 0x014dfb73);
4084 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfd9a059f);
4085 cx25840_write4(client, DIF_BPF_COEFF2021, 0x03e0f978);
4086 cx25840_write4(client, DIF_BPF_COEFF2223, 0xfa4e0726);
4087 cx25840_write4(client, DIF_BPF_COEFF2425, 0x07c8f8a7);
4088 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf600070c);
4089 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0c2ff9c9);
4090 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf1db04de);
4091 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0fb4fce5);
4092 cx25840_write4(client, DIF_BPF_COEFF3435, 0xef4b0111);
4093 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4094 break;
4095
4096 case 12100000:
4097 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffd);
4098 cx25840_write4(client, DIF_BPF_COEFF23, 0x00010012);
4099 cx25840_write4(client, DIF_BPF_COEFF45, 0xffffffc8);
4100 cx25840_write4(client, DIF_BPF_COEFF67, 0xfffb007e);
4101 cx25840_write4(client, DIF_BPF_COEFF89, 0x001dff14);
4102 cx25840_write4(client, DIF_BPF_COEFF1011, 0xffad0184);
4103 cx25840_write4(client, DIF_BPF_COEFF1213, 0x00b7fdbe);
4104 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfea9031b);
4105 cx25840_write4(client, DIF_BPF_COEFF1617, 0x0241fc01);
4106 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfc8504d6);
4107 cx25840_write4(client, DIF_BPF_COEFF2021, 0x0504fa79);
4108 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf93005f6);
4109 cx25840_write4(client, DIF_BPF_COEFF2425, 0x08caf9f2);
4110 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf52b05c0);
4111 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0ccbfaf9);
4112 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf17903eb);
4113 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0fe3fd83);
4114 cx25840_write4(client, DIF_BPF_COEFF3435, 0xef3f00db);
4115 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4116 break;
4117
4118 case 12200000:
4119 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffd);
4120 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffe0011);
4121 cx25840_write4(client, DIF_BPF_COEFF45, 0x000cffcc);
4122 cx25840_write4(client, DIF_BPF_COEFF67, 0xffdb0071);
4123 cx25840_write4(client, DIF_BPF_COEFF89, 0x0058ff32);
4124 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff4f014a);
4125 cx25840_write4(client, DIF_BPF_COEFF1213, 0x013cfe1f);
4126 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfdfb028a);
4127 cx25840_write4(client, DIF_BPF_COEFF1617, 0x0311fcc9);
4128 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfb9d03d6);
4129 cx25840_write4(client, DIF_BPF_COEFF2021, 0x05f4fbad);
4130 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf848049d);
4131 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0999fb5b);
4132 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf4820461);
4133 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0d46fc32);
4134 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf12d02f4);
4135 cx25840_write4(client, DIF_BPF_COEFF3233, 0x1007fe21);
4136 cx25840_write4(client, DIF_BPF_COEFF3435, 0xef3600a4);
4137 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4138 break;
4139
4140 case 12300000:
4141 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffe);
4142 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffa000e);
4143 cx25840_write4(client, DIF_BPF_COEFF45, 0x0017ffd9);
4144 cx25840_write4(client, DIF_BPF_COEFF67, 0xffc10055);
4145 cx25840_write4(client, DIF_BPF_COEFF89, 0x0088ff68);
4146 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff0400f0);
4147 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01a6fea7);
4148 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd7501cc);
4149 cx25840_write4(client, DIF_BPF_COEFF1617, 0x03b0fdc0);
4150 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfaef02a8);
4151 cx25840_write4(client, DIF_BPF_COEFF2021, 0x06a7fd07);
4152 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf79d0326);
4153 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0a31fcda);
4154 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf40702f3);
4155 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0d9ffd72);
4156 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf0f601fa);
4157 cx25840_write4(client, DIF_BPF_COEFF3233, 0x1021fec0);
4158 cx25840_write4(client, DIF_BPF_COEFF3435, 0xef2f006d);
4159 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4160 break;
4161
4162 case 12400000:
4163 cx25840_write4(client, DIF_BPF_COEFF01, 0x0001ffff);
4164 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff80007);
4165 cx25840_write4(client, DIF_BPF_COEFF45, 0x001fffeb);
4166 cx25840_write4(client, DIF_BPF_COEFF67, 0xffaf002d);
4167 cx25840_write4(client, DIF_BPF_COEFF89, 0x00a8ffb0);
4168 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfed3007e);
4169 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01e9ff4c);
4170 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd2000ee);
4171 cx25840_write4(client, DIF_BPF_COEFF1617, 0x0413fed8);
4172 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfa82015c);
4173 cx25840_write4(client, DIF_BPF_COEFF2021, 0x0715fe7d);
4174 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf7340198);
4175 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0a8dfe69);
4176 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf3bd017c);
4177 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0dd5feb8);
4178 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf0d500fd);
4179 cx25840_write4(client, DIF_BPF_COEFF3233, 0x1031ff60);
4180 cx25840_write4(client, DIF_BPF_COEFF3435, 0xef2b0037);
4181 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4182 break;
4183
4184 case 12500000:
4185 cx25840_write4(client, DIF_BPF_COEFF01, 0x00010000);
4186 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff70000);
4187 cx25840_write4(client, DIF_BPF_COEFF45, 0x00220000);
4188 cx25840_write4(client, DIF_BPF_COEFF67, 0xffa90000);
4189 cx25840_write4(client, DIF_BPF_COEFF89, 0x00b30000);
4190 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfec20000);
4191 cx25840_write4(client, DIF_BPF_COEFF1213, 0x02000000);
4192 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd030000);
4193 cx25840_write4(client, DIF_BPF_COEFF1617, 0x04350000);
4194 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfa5e0000);
4195 cx25840_write4(client, DIF_BPF_COEFF2021, 0x073b0000);
4196 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf7110000);
4197 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0aac0000);
4198 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf3a40000);
4199 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0de70000);
4200 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf0c90000);
4201 cx25840_write4(client, DIF_BPF_COEFF3233, 0x10360000);
4202 cx25840_write4(client, DIF_BPF_COEFF3435, 0xef290000);
4203 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4204 break;
4205
4206 case 12600000:
4207 cx25840_write4(client, DIF_BPF_COEFF01, 0x00010001);
4208 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff8fff9);
4209 cx25840_write4(client, DIF_BPF_COEFF45, 0x001f0015);
4210 cx25840_write4(client, DIF_BPF_COEFF67, 0xffafffd3);
4211 cx25840_write4(client, DIF_BPF_COEFF89, 0x00a80050);
4212 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfed3ff82);
4213 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01e900b4);
4214 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd20ff12);
4215 cx25840_write4(client, DIF_BPF_COEFF1617, 0x04130128);
4216 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfa82fea4);
4217 cx25840_write4(client, DIF_BPF_COEFF2021, 0x07150183);
4218 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf734fe68);
4219 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0a8d0197);
4220 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf3bdfe84);
4221 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0dd50148);
4222 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf0d5ff03);
4223 cx25840_write4(client, DIF_BPF_COEFF3233, 0x103100a0);
4224 cx25840_write4(client, DIF_BPF_COEFF3435, 0xef2bffc9);
4225 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4226 break;
4227
4228 case 12700000:
4229 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000002);
4230 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffafff2);
4231 cx25840_write4(client, DIF_BPF_COEFF45, 0x00170027);
4232 cx25840_write4(client, DIF_BPF_COEFF67, 0xffc1ffab);
4233 cx25840_write4(client, DIF_BPF_COEFF89, 0x00880098);
4234 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff04ff10);
4235 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01a60159);
4236 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd75fe34);
4237 cx25840_write4(client, DIF_BPF_COEFF1617, 0x03b00240);
4238 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfaeffd58);
4239 cx25840_write4(client, DIF_BPF_COEFF2021, 0x06a702f9);
4240 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf79dfcda);
4241 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0a310326);
4242 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf407fd0d);
4243 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0d9f028e);
4244 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf0f6fe06);
4245 cx25840_write4(client, DIF_BPF_COEFF3233, 0x10210140);
4246 cx25840_write4(client, DIF_BPF_COEFF3435, 0xef2fff93);
4247 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4248 break;
4249
4250 case 12800000:
4251 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000003);
4252 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffeffef);
4253 cx25840_write4(client, DIF_BPF_COEFF45, 0x000c0034);
4254 cx25840_write4(client, DIF_BPF_COEFF67, 0xffdbff8f);
4255 cx25840_write4(client, DIF_BPF_COEFF89, 0x005800ce);
4256 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff4ffeb6);
4257 cx25840_write4(client, DIF_BPF_COEFF1213, 0x013c01e1);
4258 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfdfbfd76);
4259 cx25840_write4(client, DIF_BPF_COEFF1617, 0x03110337);
4260 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfb9dfc2a);
4261 cx25840_write4(client, DIF_BPF_COEFF2021, 0x05f40453);
4262 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf848fb63);
4263 cx25840_write4(client, DIF_BPF_COEFF2425, 0x099904a5);
4264 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf482fb9f);
4265 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0d4603ce);
4266 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf12dfd0c);
4267 cx25840_write4(client, DIF_BPF_COEFF3233, 0x100701df);
4268 cx25840_write4(client, DIF_BPF_COEFF3435, 0xef36ff5c);
4269 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4270 break;
4271
4272 case 12900000:
4273 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000003);
4274 cx25840_write4(client, DIF_BPF_COEFF23, 0x0001ffee);
4275 cx25840_write4(client, DIF_BPF_COEFF45, 0xffff0038);
4276 cx25840_write4(client, DIF_BPF_COEFF67, 0xfffbff82);
4277 cx25840_write4(client, DIF_BPF_COEFF89, 0x001d00ec);
4278 cx25840_write4(client, DIF_BPF_COEFF1011, 0xffadfe7c);
4279 cx25840_write4(client, DIF_BPF_COEFF1213, 0x00b70242);
4280 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfea9fce5);
4281 cx25840_write4(client, DIF_BPF_COEFF1617, 0x024103ff);
4282 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfc85fb2a);
4283 cx25840_write4(client, DIF_BPF_COEFF2021, 0x05040587);
4284 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf930fa0a);
4285 cx25840_write4(client, DIF_BPF_COEFF2425, 0x08ca060e);
4286 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf52bfa40);
4287 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0ccb0507);
4288 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf179fc15);
4289 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0fe3027d);
4290 cx25840_write4(client, DIF_BPF_COEFF3435, 0xef3fff25);
4291 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4292 break;
4293
4294 case 13000000:
4295 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000002);
4296 cx25840_write4(client, DIF_BPF_COEFF23, 0x0005fff0);
4297 cx25840_write4(client, DIF_BPF_COEFF45, 0xfff20034);
4298 cx25840_write4(client, DIF_BPF_COEFF67, 0x001bff85);
4299 cx25840_write4(client, DIF_BPF_COEFF89, 0xffdf00f0);
4300 cx25840_write4(client, DIF_BPF_COEFF1011, 0x0014fe68);
4301 cx25840_write4(client, DIF_BPF_COEFF1213, 0x00200272);
4302 cx25840_write4(client, DIF_BPF_COEFF1415, 0xff71fc8b);
4303 cx25840_write4(client, DIF_BPF_COEFF1617, 0x014d048d);
4304 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfd9afa61);
4305 cx25840_write4(client, DIF_BPF_COEFF2021, 0x03e00688);
4306 cx25840_write4(client, DIF_BPF_COEFF2223, 0xfa4ef8da);
4307 cx25840_write4(client, DIF_BPF_COEFF2425, 0x07c80759);
4308 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf600f8f4);
4309 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0c2f0637);
4310 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf1dbfb22);
4311 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0fb4031b);
4312 cx25840_write4(client, DIF_BPF_COEFF3435, 0xef4bfeef);
4313 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4314 break;
4315
4316 case 13100000:
4317 cx25840_write4(client, DIF_BPF_COEFF01, 0xffff0001);
4318 cx25840_write4(client, DIF_BPF_COEFF23, 0x0007fff5);
4319 cx25840_write4(client, DIF_BPF_COEFF45, 0xffe70028);
4320 cx25840_write4(client, DIF_BPF_COEFF67, 0x0037ff98);
4321 cx25840_write4(client, DIF_BPF_COEFF89, 0xffa400d8);
4322 cx25840_write4(client, DIF_BPF_COEFF1011, 0x0079fe7c);
4323 cx25840_write4(client, DIF_BPF_COEFF1213, 0xff87026f);
4324 cx25840_write4(client, DIF_BPF_COEFF1415, 0x0043fc6e);
4325 cx25840_write4(client, DIF_BPF_COEFF1617, 0x004404da);
4326 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfecef9da);
4327 cx25840_write4(client, DIF_BPF_COEFF2021, 0x0294074e);
4328 cx25840_write4(client, DIF_BPF_COEFF2223, 0xfb99f7db);
4329 cx25840_write4(client, DIF_BPF_COEFF2425, 0x06980881);
4330 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf6fef7be);
4331 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0b730759);
4332 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf251fa33);
4333 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0f7b03b8);
4334 cx25840_write4(client, DIF_BPF_COEFF3435, 0xef5afeb8);
4335 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4336 break;
4337
4338 case 13200000:
4339 cx25840_write4(client, DIF_BPF_COEFF01, 0xffff0000);
4340 cx25840_write4(client, DIF_BPF_COEFF23, 0x0008fffc);
4341 cx25840_write4(client, DIF_BPF_COEFF45, 0xffe00017);
4342 cx25840_write4(client, DIF_BPF_COEFF67, 0x004cffb9);
4343 cx25840_write4(client, DIF_BPF_COEFF89, 0xff7500a8);
4344 cx25840_write4(client, DIF_BPF_COEFF1011, 0x00d1feb6);
4345 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfef90238);
4346 cx25840_write4(client, DIF_BPF_COEFF1415, 0x0111fc91);
4347 cx25840_write4(client, DIF_BPF_COEFF1617, 0xff3604df);
4348 cx25840_write4(client, DIF_BPF_COEFF1819, 0x0012f99b);
4349 cx25840_write4(client, DIF_BPF_COEFF2021, 0x012d07d2);
4350 cx25840_write4(client, DIF_BPF_COEFF2223, 0xfd07f714);
4351 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0542097e);
4352 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf81ff6a4);
4353 cx25840_write4(client, DIF_BPF_COEFF2829, 0x0a9a086e);
4354 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf2dbf94b);
4355 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0f380453);
4356 cx25840_write4(client, DIF_BPF_COEFF3435, 0xef6cfe82);
4357 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4358 break;
4359
4360 case 13300000:
4361 cx25840_write4(client, DIF_BPF_COEFF01, 0xffffffff);
4362 cx25840_write4(client, DIF_BPF_COEFF23, 0x00080003);
4363 cx25840_write4(client, DIF_BPF_COEFF45, 0xffde0001);
4364 cx25840_write4(client, DIF_BPF_COEFF67, 0x0056ffe3);
4365 cx25840_write4(client, DIF_BPF_COEFF89, 0xff570064);
4366 cx25840_write4(client, DIF_BPF_COEFF1011, 0x0113ff10);
4367 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe8201d2);
4368 cx25840_write4(client, DIF_BPF_COEFF1415, 0x01cafcf0);
4369 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfe35049e);
4370 cx25840_write4(client, DIF_BPF_COEFF1819, 0x0155f9a6);
4371 cx25840_write4(client, DIF_BPF_COEFF2021, 0xffba080e);
4372 cx25840_write4(client, DIF_BPF_COEFF2223, 0xfe8cf689);
4373 cx25840_write4(client, DIF_BPF_COEFF2425, 0x03ce0a4e);
4374 cx25840_write4(client, DIF_BPF_COEFF2627, 0xf961f5a8);
4375 cx25840_write4(client, DIF_BPF_COEFF2829, 0x09a50971);
4376 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf379f869);
4377 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0eeb04ec);
4378 cx25840_write4(client, DIF_BPF_COEFF3435, 0xef80fe4b);
4379 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4380 break;
4381
4382 case 13400000:
4383 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffe);
4384 cx25840_write4(client, DIF_BPF_COEFF23, 0x0007000a);
4385 cx25840_write4(client, DIF_BPF_COEFF45, 0xffe2ffec);
4386 cx25840_write4(client, DIF_BPF_COEFF67, 0x00540012);
4387 cx25840_write4(client, DIF_BPF_COEFF89, 0xff4e0015);
4388 cx25840_write4(client, DIF_BPF_COEFF1011, 0x0137ff82);
4389 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe2e0145);
4390 cx25840_write4(client, DIF_BPF_COEFF1415, 0x0260fd86);
4391 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfd51041a);
4392 cx25840_write4(client, DIF_BPF_COEFF1819, 0x0287f9fb);
4393 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfe4a0802);
4394 cx25840_write4(client, DIF_BPF_COEFF2223, 0x001df63f);
4395 cx25840_write4(client, DIF_BPF_COEFF2425, 0x02430aeb);
4396 cx25840_write4(client, DIF_BPF_COEFF2627, 0xfabdf4ce);
4397 cx25840_write4(client, DIF_BPF_COEFF2829, 0x08970a62);
4398 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf428f78f);
4399 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0e950584);
4400 cx25840_write4(client, DIF_BPF_COEFF3435, 0xef97fe15);
4401 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4402 break;
4403
4404 case 13500000:
4405 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffd);
4406 cx25840_write4(client, DIF_BPF_COEFF23, 0x0004000f);
4407 cx25840_write4(client, DIF_BPF_COEFF45, 0xffeaffda);
4408 cx25840_write4(client, DIF_BPF_COEFF67, 0x0046003d);
4409 cx25840_write4(client, DIF_BPF_COEFF89, 0xff5affc4);
4410 cx25840_write4(client, DIF_BPF_COEFF1011, 0x013b0000);
4411 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe04009d);
4412 cx25840_write4(client, DIF_BPF_COEFF1415, 0x02c8fe48);
4413 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc99035a);
4414 cx25840_write4(client, DIF_BPF_COEFF1819, 0x0397fa96);
4415 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfcec07ad);
4416 cx25840_write4(client, DIF_BPF_COEFF2223, 0x01adf637);
4417 cx25840_write4(client, DIF_BPF_COEFF2425, 0x00ac0b53);
4418 cx25840_write4(client, DIF_BPF_COEFF2627, 0xfc2ef419);
4419 cx25840_write4(client, DIF_BPF_COEFF2829, 0x07730b3e);
4420 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf4e9f6bd);
4421 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0e35061a);
4422 cx25840_write4(client, DIF_BPF_COEFF3435, 0xefb1fddf);
4423 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4424 break;
4425
4426 case 13600000:
4427 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffd);
4428 cx25840_write4(client, DIF_BPF_COEFF23, 0x00000012);
4429 cx25840_write4(client, DIF_BPF_COEFF45, 0xfff6ffcd);
4430 cx25840_write4(client, DIF_BPF_COEFF67, 0x002f0061);
4431 cx25840_write4(client, DIF_BPF_COEFF89, 0xff7bff79);
4432 cx25840_write4(client, DIF_BPF_COEFF1011, 0x011e007e);
4433 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe08ffe8);
4434 cx25840_write4(client, DIF_BPF_COEFF1415, 0x02f9ff28);
4435 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc17026a);
4436 cx25840_write4(client, DIF_BPF_COEFF1819, 0x0479fb70);
4437 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfbad0713);
4438 cx25840_write4(client, DIF_BPF_COEFF2223, 0x032ff672);
4439 cx25840_write4(client, DIF_BPF_COEFF2425, 0xff100b83);
4440 cx25840_write4(client, DIF_BPF_COEFF2627, 0xfdaff38b);
4441 cx25840_write4(client, DIF_BPF_COEFF2829, 0x063c0c04);
4442 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf5baf5f5);
4443 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0dcc06ae);
4444 cx25840_write4(client, DIF_BPF_COEFF3435, 0xefcdfda8);
4445 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4446 break;
4447
4448 case 13700000:
4449 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffd);
4450 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffd0012);
4451 cx25840_write4(client, DIF_BPF_COEFF45, 0x0004ffc8);
4452 cx25840_write4(client, DIF_BPF_COEFF67, 0x00100078);
4453 cx25840_write4(client, DIF_BPF_COEFF89, 0xffacff3e);
4454 cx25840_write4(client, DIF_BPF_COEFF1011, 0x00e200f0);
4455 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe39ff35);
4456 cx25840_write4(client, DIF_BPF_COEFF1415, 0x02f10017);
4457 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfbd30156);
4458 cx25840_write4(client, DIF_BPF_COEFF1819, 0x0521fc7f);
4459 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfa9c0638);
4460 cx25840_write4(client, DIF_BPF_COEFF2223, 0x0499f6ee);
4461 cx25840_write4(client, DIF_BPF_COEFF2425, 0xfd7a0b7c);
4462 cx25840_write4(client, DIF_BPF_COEFF2627, 0xff39f325);
4463 cx25840_write4(client, DIF_BPF_COEFF2829, 0x04f40cb3);
4464 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf69af537);
4465 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0d5a073f);
4466 cx25840_write4(client, DIF_BPF_COEFF3435, 0xefecfd72);
4467 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4468 break;
4469
4470 case 13800000:
4471 cx25840_write4(client, DIF_BPF_COEFF01, 0x0001fffe);
4472 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffa000e);
4473 cx25840_write4(client, DIF_BPF_COEFF45, 0x0011ffcb);
4474 cx25840_write4(client, DIF_BPF_COEFF67, 0xfff0007f);
4475 cx25840_write4(client, DIF_BPF_COEFF89, 0xffe7ff19);
4476 cx25840_write4(client, DIF_BPF_COEFF1011, 0x008f014a);
4477 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe94fe93);
4478 cx25840_write4(client, DIF_BPF_COEFF1415, 0x02b00105);
4479 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfbd3002f);
4480 cx25840_write4(client, DIF_BPF_COEFF1819, 0x0585fdb7);
4481 cx25840_write4(client, DIF_BPF_COEFF2021, 0xf9c10525);
4482 cx25840_write4(client, DIF_BPF_COEFF2223, 0x05def7a8);
4483 cx25840_write4(client, DIF_BPF_COEFF2425, 0xfbf20b3c);
4484 cx25840_write4(client, DIF_BPF_COEFF2627, 0x00c7f2e9);
4485 cx25840_write4(client, DIF_BPF_COEFF2829, 0x03a00d48);
4486 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf787f484);
4487 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0cdf07cd);
4488 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf00dfd3c);
4489 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4490 break;
4491
4492 case 13900000:
4493 cx25840_write4(client, DIF_BPF_COEFF01, 0x00010000);
4494 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff80008);
4495 cx25840_write4(client, DIF_BPF_COEFF45, 0x001bffd7);
4496 cx25840_write4(client, DIF_BPF_COEFF67, 0xffd10076);
4497 cx25840_write4(client, DIF_BPF_COEFF89, 0x0026ff0e);
4498 cx25840_write4(client, DIF_BPF_COEFF1011, 0x002c0184);
4499 cx25840_write4(client, DIF_BPF_COEFF1213, 0xff0ffe10);
4500 cx25840_write4(client, DIF_BPF_COEFF1415, 0x023b01e0);
4501 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc17ff06);
4502 cx25840_write4(client, DIF_BPF_COEFF1819, 0x05a2ff09);
4503 cx25840_write4(client, DIF_BPF_COEFF2021, 0xf92703e4);
4504 cx25840_write4(client, DIF_BPF_COEFF2223, 0x06f4f89b);
4505 cx25840_write4(client, DIF_BPF_COEFF2425, 0xfa820ac5);
4506 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0251f2d9);
4507 cx25840_write4(client, DIF_BPF_COEFF2829, 0x02430dc3);
4508 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf881f3dc);
4509 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0c5c0859);
4510 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf031fd06);
4511 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4512 break;
4513
4514 case 14000000:
4515 cx25840_write4(client, DIF_BPF_COEFF01, 0x00010001);
4516 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff80001);
4517 cx25840_write4(client, DIF_BPF_COEFF45, 0x0021ffe8);
4518 cx25840_write4(client, DIF_BPF_COEFF67, 0xffba005d);
4519 cx25840_write4(client, DIF_BPF_COEFF89, 0x0060ff1f);
4520 cx25840_write4(client, DIF_BPF_COEFF1011, 0xffc40198);
4521 cx25840_write4(client, DIF_BPF_COEFF1213, 0xffa0fdb5);
4522 cx25840_write4(client, DIF_BPF_COEFF1415, 0x019a029a);
4523 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc99fdea);
4524 cx25840_write4(client, DIF_BPF_COEFF1819, 0x05750067);
4525 cx25840_write4(client, DIF_BPF_COEFF2021, 0xf8d4027f);
4526 cx25840_write4(client, DIF_BPF_COEFF2223, 0x07d4f9c0);
4527 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf9320a1a);
4528 cx25840_write4(client, DIF_BPF_COEFF2627, 0x03d2f2f3);
4529 cx25840_write4(client, DIF_BPF_COEFF2829, 0x00df0e22);
4530 cx25840_write4(client, DIF_BPF_COEFF3031, 0xf986f341);
4531 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0bd108e2);
4532 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf058fcd1);
4533 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4534 break;
4535
4536 case 14100000:
4537 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000002);
4538 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff9fffa);
4539 cx25840_write4(client, DIF_BPF_COEFF45, 0x0021fffd);
4540 cx25840_write4(client, DIF_BPF_COEFF67, 0xffac0038);
4541 cx25840_write4(client, DIF_BPF_COEFF89, 0x008eff4a);
4542 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff630184);
4543 cx25840_write4(client, DIF_BPF_COEFF1213, 0x003afd8b);
4544 cx25840_write4(client, DIF_BPF_COEFF1415, 0x00da0326);
4545 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfd51fced);
4546 cx25840_write4(client, DIF_BPF_COEFF1819, 0x050101c0);
4547 cx25840_write4(client, DIF_BPF_COEFF2021, 0xf8cb0103);
4548 cx25840_write4(client, DIF_BPF_COEFF2223, 0x0876fb10);
4549 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf80a093e);
4550 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0543f338);
4551 cx25840_write4(client, DIF_BPF_COEFF2829, 0xff7a0e66);
4552 cx25840_write4(client, DIF_BPF_COEFF3031, 0xfa94f2b2);
4553 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0b3f0967);
4554 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf081fc9b);
4555 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4556 break;
4557
4558 case 14200000:
4559 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000003);
4560 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffbfff3);
4561 cx25840_write4(client, DIF_BPF_COEFF45, 0x001d0013);
4562 cx25840_write4(client, DIF_BPF_COEFF67, 0xffaa000b);
4563 cx25840_write4(client, DIF_BPF_COEFF89, 0x00aaff89);
4564 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff13014a);
4565 cx25840_write4(client, DIF_BPF_COEFF1213, 0x00cefd95);
4566 cx25840_write4(client, DIF_BPF_COEFF1415, 0x000a037b);
4567 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfe35fc1d);
4568 cx25840_write4(client, DIF_BPF_COEFF1819, 0x044c0305);
4569 cx25840_write4(client, DIF_BPF_COEFF2021, 0xf90cff7e);
4570 cx25840_write4(client, DIF_BPF_COEFF2223, 0x08d5fc81);
4571 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf7100834);
4572 cx25840_write4(client, DIF_BPF_COEFF2627, 0x069ff3a7);
4573 cx25840_write4(client, DIF_BPF_COEFF2829, 0xfe160e8d);
4574 cx25840_write4(client, DIF_BPF_COEFF3031, 0xfbaaf231);
4575 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0aa509e9);
4576 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf0adfc65);
4577 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4578 break;
4579
4580 case 14300000:
4581 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000003);
4582 cx25840_write4(client, DIF_BPF_COEFF23, 0xffffffef);
4583 cx25840_write4(client, DIF_BPF_COEFF45, 0x00140025);
4584 cx25840_write4(client, DIF_BPF_COEFF67, 0xffb4ffdd);
4585 cx25840_write4(client, DIF_BPF_COEFF89, 0x00b2ffd6);
4586 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfedb00f0);
4587 cx25840_write4(client, DIF_BPF_COEFF1213, 0x0150fdd3);
4588 cx25840_write4(client, DIF_BPF_COEFF1415, 0xff380391);
4589 cx25840_write4(client, DIF_BPF_COEFF1617, 0xff36fb85);
4590 cx25840_write4(client, DIF_BPF_COEFF1819, 0x035e0426);
4591 cx25840_write4(client, DIF_BPF_COEFF2021, 0xf994fdfe);
4592 cx25840_write4(client, DIF_BPF_COEFF2223, 0x08eefe0b);
4593 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf6490702);
4594 cx25840_write4(client, DIF_BPF_COEFF2627, 0x07e1f43e);
4595 cx25840_write4(client, DIF_BPF_COEFF2829, 0xfcb60e97);
4596 cx25840_write4(client, DIF_BPF_COEFF3031, 0xfcc6f1be);
4597 cx25840_write4(client, DIF_BPF_COEFF3233, 0x0a040a67);
4598 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf0dbfc30);
4599 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4600 break;
4601
4602 case 14400000:
4603 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000003);
4604 cx25840_write4(client, DIF_BPF_COEFF23, 0x0002ffee);
4605 cx25840_write4(client, DIF_BPF_COEFF45, 0x00070033);
4606 cx25840_write4(client, DIF_BPF_COEFF67, 0xffc9ffb4);
4607 cx25840_write4(client, DIF_BPF_COEFF89, 0x00a40027);
4608 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfec3007e);
4609 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01b4fe3f);
4610 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfe760369);
4611 cx25840_write4(client, DIF_BPF_COEFF1617, 0x0044fb2e);
4612 cx25840_write4(client, DIF_BPF_COEFF1819, 0x02450518);
4613 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfa5ffc90);
4614 cx25840_write4(client, DIF_BPF_COEFF2223, 0x08c1ffa1);
4615 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf5bc05ae);
4616 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0902f4fc);
4617 cx25840_write4(client, DIF_BPF_COEFF2829, 0xfb600e85);
4618 cx25840_write4(client, DIF_BPF_COEFF3031, 0xfde7f15a);
4619 cx25840_write4(client, DIF_BPF_COEFF3233, 0x095d0ae2);
4620 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf10cfbfb);
4621 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4622 break;
4623
4624 case 14500000:
4625 cx25840_write4(client, DIF_BPF_COEFF01, 0xffff0002);
4626 cx25840_write4(client, DIF_BPF_COEFF23, 0x0005ffef);
4627 cx25840_write4(client, DIF_BPF_COEFF45, 0xfffa0038);
4628 cx25840_write4(client, DIF_BPF_COEFF67, 0xffe5ff95);
4629 cx25840_write4(client, DIF_BPF_COEFF89, 0x00820074);
4630 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfecc0000);
4631 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01f0fed0);
4632 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfdd20304);
4633 cx25840_write4(client, DIF_BPF_COEFF1617, 0x014dfb1d);
4634 cx25840_write4(client, DIF_BPF_COEFF1819, 0x010e05ce);
4635 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfb64fb41);
4636 cx25840_write4(client, DIF_BPF_COEFF2223, 0x084e013b);
4637 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf569043e);
4638 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0a00f5dd);
4639 cx25840_write4(client, DIF_BPF_COEFF2829, 0xfa150e55);
4640 cx25840_write4(client, DIF_BPF_COEFF3031, 0xff0bf104);
4641 cx25840_write4(client, DIF_BPF_COEFF3233, 0x08b00b59);
4642 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf13ffbc6);
4643 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4644 break;
4645
4646 case 14600000:
4647 cx25840_write4(client, DIF_BPF_COEFF01, 0xffff0001);
4648 cx25840_write4(client, DIF_BPF_COEFF23, 0x0008fff4);
4649 cx25840_write4(client, DIF_BPF_COEFF45, 0xffed0035);
4650 cx25840_write4(client, DIF_BPF_COEFF67, 0x0005ff83);
4651 cx25840_write4(client, DIF_BPF_COEFF89, 0x005000b4);
4652 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfef6ff82);
4653 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01ffff7a);
4654 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd580269);
4655 cx25840_write4(client, DIF_BPF_COEFF1617, 0x0241fb53);
4656 cx25840_write4(client, DIF_BPF_COEFF1819, 0xffca0640);
4657 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfc99fa1e);
4658 cx25840_write4(client, DIF_BPF_COEFF2223, 0x079a02cb);
4659 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf55502ba);
4660 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0ad5f6e0);
4661 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf8d90e0a);
4662 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0031f0bd);
4663 cx25840_write4(client, DIF_BPF_COEFF3233, 0x07fd0bcb);
4664 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf174fb91);
4665 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4666 break;
4667
4668 case 14700000:
4669 cx25840_write4(client, DIF_BPF_COEFF01, 0xffffffff);
4670 cx25840_write4(client, DIF_BPF_COEFF23, 0x0009fffb);
4671 cx25840_write4(client, DIF_BPF_COEFF45, 0xffe4002a);
4672 cx25840_write4(client, DIF_BPF_COEFF67, 0x0025ff82);
4673 cx25840_write4(client, DIF_BPF_COEFF89, 0x001400e0);
4674 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff3cff10);
4675 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01e10030);
4676 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd1201a4);
4677 cx25840_write4(client, DIF_BPF_COEFF1617, 0x0311fbcd);
4678 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfe88066a);
4679 cx25840_write4(client, DIF_BPF_COEFF2021, 0xfdf1f92f);
4680 cx25840_write4(client, DIF_BPF_COEFF2223, 0x06aa0449);
4681 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf57e0128);
4682 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0b7ef801);
4683 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf7b00da2);
4684 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0156f086);
4685 cx25840_write4(client, DIF_BPF_COEFF3233, 0x07450c39);
4686 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf1acfb5c);
4687 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4688 break;
4689
4690 case 14800000:
4691 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffe);
4692 cx25840_write4(client, DIF_BPF_COEFF23, 0x00080002);
4693 cx25840_write4(client, DIF_BPF_COEFF45, 0xffdf0019);
4694 cx25840_write4(client, DIF_BPF_COEFF67, 0x003fff92);
4695 cx25840_write4(client, DIF_BPF_COEFF89, 0xffd600f1);
4696 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff96feb6);
4697 cx25840_write4(client, DIF_BPF_COEFF1213, 0x019700e1);
4698 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd0500c2);
4699 cx25840_write4(client, DIF_BPF_COEFF1617, 0x03b0fc84);
4700 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfd590649);
4701 cx25840_write4(client, DIF_BPF_COEFF2021, 0xff5df87f);
4702 cx25840_write4(client, DIF_BPF_COEFF2223, 0x058505aa);
4703 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf5e4ff91);
4704 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0bf9f93c);
4705 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf69d0d20);
4706 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0279f05e);
4707 cx25840_write4(client, DIF_BPF_COEFF3233, 0x06880ca3);
4708 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf1e6fb28);
4709 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4710 break;
4711
4712 case 14900000:
4713 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffd);
4714 cx25840_write4(client, DIF_BPF_COEFF23, 0x00060009);
4715 cx25840_write4(client, DIF_BPF_COEFF45, 0xffdf0004);
4716 cx25840_write4(client, DIF_BPF_COEFF67, 0x0051ffb0);
4717 cx25840_write4(client, DIF_BPF_COEFF89, 0xff9d00e8);
4718 cx25840_write4(client, DIF_BPF_COEFF1011, 0xfffcfe7c);
4719 cx25840_write4(client, DIF_BPF_COEFF1213, 0x01280180);
4720 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd32ffd2);
4721 cx25840_write4(client, DIF_BPF_COEFF1617, 0x0413fd6e);
4722 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfc4d05df);
4723 cx25840_write4(client, DIF_BPF_COEFF2021, 0x00d1f812);
4724 cx25840_write4(client, DIF_BPF_COEFF2223, 0x043506e4);
4725 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf685fdfb);
4726 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0c43fa8d);
4727 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf5a10c83);
4728 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0399f046);
4729 cx25840_write4(client, DIF_BPF_COEFF3233, 0x05c70d08);
4730 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf222faf3);
4731 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4732 break;
4733
4734 case 15000000:
4735 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffd);
4736 cx25840_write4(client, DIF_BPF_COEFF23, 0x0003000f);
4737 cx25840_write4(client, DIF_BPF_COEFF45, 0xffe5ffef);
4738 cx25840_write4(client, DIF_BPF_COEFF67, 0x0057ffd9);
4739 cx25840_write4(client, DIF_BPF_COEFF89, 0xff7000c4);
4740 cx25840_write4(client, DIF_BPF_COEFF1011, 0x0062fe68);
4741 cx25840_write4(client, DIF_BPF_COEFF1213, 0x009e01ff);
4742 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd95fee6);
4743 cx25840_write4(client, DIF_BPF_COEFF1617, 0x0435fe7d);
4744 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfb710530);
4745 cx25840_write4(client, DIF_BPF_COEFF2021, 0x023cf7ee);
4746 cx25840_write4(client, DIF_BPF_COEFF2223, 0x02c307ef);
4747 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf75efc70);
4748 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0c5cfbef);
4749 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf4c10bce);
4750 cx25840_write4(client, DIF_BPF_COEFF3031, 0x04b3f03f);
4751 cx25840_write4(client, DIF_BPF_COEFF3233, 0x05030d69);
4752 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf261fabf);
4753 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4754 break;
4755
4756 case 15100000:
4757 cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffd);
4758 cx25840_write4(client, DIF_BPF_COEFF23, 0xffff0012);
4759 cx25840_write4(client, DIF_BPF_COEFF45, 0xffefffdc);
4760 cx25840_write4(client, DIF_BPF_COEFF67, 0x00510006);
4761 cx25840_write4(client, DIF_BPF_COEFF89, 0xff540089);
4762 cx25840_write4(client, DIF_BPF_COEFF1011, 0x00befe7c);
4763 cx25840_write4(client, DIF_BPF_COEFF1213, 0x00060253);
4764 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfe27fe0d);
4765 cx25840_write4(client, DIF_BPF_COEFF1617, 0x0413ffa2);
4766 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfad10446);
4767 cx25840_write4(client, DIF_BPF_COEFF2021, 0x0390f812);
4768 cx25840_write4(client, DIF_BPF_COEFF2223, 0x013b08c3);
4769 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf868faf6);
4770 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0c43fd5f);
4771 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf3fd0b02);
4772 cx25840_write4(client, DIF_BPF_COEFF3031, 0x05c7f046);
4773 cx25840_write4(client, DIF_BPF_COEFF3233, 0x043b0dc4);
4774 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf2a1fa8b);
4775 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4776 break;
4777
4778 case 15200000:
4779 cx25840_write4(client, DIF_BPF_COEFF01, 0x0001fffe);
4780 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffc0012);
4781 cx25840_write4(client, DIF_BPF_COEFF45, 0xfffbffce);
4782 cx25840_write4(client, DIF_BPF_COEFF67, 0x003f0033);
4783 cx25840_write4(client, DIF_BPF_COEFF89, 0xff4e003f);
4784 cx25840_write4(client, DIF_BPF_COEFF1011, 0x0106feb6);
4785 cx25840_write4(client, DIF_BPF_COEFF1213, 0xff6e0276);
4786 cx25840_write4(client, DIF_BPF_COEFF1415, 0xfeddfd56);
4787 cx25840_write4(client, DIF_BPF_COEFF1617, 0x03b000cc);
4788 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfa740329);
4789 cx25840_write4(client, DIF_BPF_COEFF2021, 0x04bff87f);
4790 cx25840_write4(client, DIF_BPF_COEFF2223, 0xffaa095d);
4791 cx25840_write4(client, DIF_BPF_COEFF2425, 0xf99ef995);
4792 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0bf9fed8);
4793 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf3590a1f);
4794 cx25840_write4(client, DIF_BPF_COEFF3031, 0x06d2f05e);
4795 cx25840_write4(client, DIF_BPF_COEFF3233, 0x03700e1b);
4796 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf2e4fa58);
4797 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4798 break;
4799
4800 case 15300000:
4801 cx25840_write4(client, DIF_BPF_COEFF01, 0x0001ffff);
4802 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff9000f);
4803 cx25840_write4(client, DIF_BPF_COEFF45, 0x0009ffc8);
4804 cx25840_write4(client, DIF_BPF_COEFF67, 0x00250059);
4805 cx25840_write4(client, DIF_BPF_COEFF89, 0xff5effee);
4806 cx25840_write4(client, DIF_BPF_COEFF1011, 0x0132ff10);
4807 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfee30265);
4808 cx25840_write4(client, DIF_BPF_COEFF1415, 0xffaafccf);
4809 cx25840_write4(client, DIF_BPF_COEFF1617, 0x031101eb);
4810 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfa6001e8);
4811 cx25840_write4(client, DIF_BPF_COEFF2021, 0x05bdf92f);
4812 cx25840_write4(client, DIF_BPF_COEFF2223, 0xfe1b09b6);
4813 cx25840_write4(client, DIF_BPF_COEFF2425, 0xfafaf852);
4814 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0b7e0055);
4815 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf2d50929);
4816 cx25840_write4(client, DIF_BPF_COEFF3031, 0x07d3f086);
4817 cx25840_write4(client, DIF_BPF_COEFF3233, 0x02a30e6c);
4818 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf329fa24);
4819 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4820 break;
4821
4822 case 15400000:
4823 cx25840_write4(client, DIF_BPF_COEFF01, 0x00010001);
4824 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff80009);
4825 cx25840_write4(client, DIF_BPF_COEFF45, 0x0015ffca);
4826 cx25840_write4(client, DIF_BPF_COEFF67, 0x00050074);
4827 cx25840_write4(client, DIF_BPF_COEFF89, 0xff81ff9f);
4828 cx25840_write4(client, DIF_BPF_COEFF1011, 0x013dff82);
4829 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe710221);
4830 cx25840_write4(client, DIF_BPF_COEFF1415, 0x007cfc80);
4831 cx25840_write4(client, DIF_BPF_COEFF1617, 0x024102ed);
4832 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfa940090);
4833 cx25840_write4(client, DIF_BPF_COEFF2021, 0x0680fa1e);
4834 cx25840_write4(client, DIF_BPF_COEFF2223, 0xfc9b09cd);
4835 cx25840_write4(client, DIF_BPF_COEFF2425, 0xfc73f736);
4836 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0ad501d0);
4837 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf2740820);
4838 cx25840_write4(client, DIF_BPF_COEFF3031, 0x08c9f0bd);
4839 cx25840_write4(client, DIF_BPF_COEFF3233, 0x01d40eb9);
4840 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf371f9f1);
4841 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4842 break;
4843
4844 case 15500000:
4845 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000002);
4846 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff80002);
4847 cx25840_write4(client, DIF_BPF_COEFF45, 0x001effd5);
4848 cx25840_write4(client, DIF_BPF_COEFF67, 0xffe5007f);
4849 cx25840_write4(client, DIF_BPF_COEFF89, 0xffb4ff5b);
4850 cx25840_write4(client, DIF_BPF_COEFF1011, 0x01280000);
4851 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe2401b0);
4852 cx25840_write4(client, DIF_BPF_COEFF1415, 0x0146fc70);
4853 cx25840_write4(client, DIF_BPF_COEFF1617, 0x014d03c6);
4854 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfb10ff32);
4855 cx25840_write4(client, DIF_BPF_COEFF2021, 0x0701fb41);
4856 cx25840_write4(client, DIF_BPF_COEFF2223, 0xfb3709a1);
4857 cx25840_write4(client, DIF_BPF_COEFF2425, 0xfe00f644);
4858 cx25840_write4(client, DIF_BPF_COEFF2627, 0x0a000345);
4859 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf2350708);
4860 cx25840_write4(client, DIF_BPF_COEFF3031, 0x09b2f104);
4861 cx25840_write4(client, DIF_BPF_COEFF3233, 0x01050eff);
4862 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf3baf9be);
4863 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4864 break;
4865
4866 case 15600000:
4867 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000003);
4868 cx25840_write4(client, DIF_BPF_COEFF23, 0xfff9fffb);
4869 cx25840_write4(client, DIF_BPF_COEFF45, 0x0022ffe6);
4870 cx25840_write4(client, DIF_BPF_COEFF67, 0xffc9007a);
4871 cx25840_write4(client, DIF_BPF_COEFF89, 0xfff0ff29);
4872 cx25840_write4(client, DIF_BPF_COEFF1011, 0x00f2007e);
4873 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe01011b);
4874 cx25840_write4(client, DIF_BPF_COEFF1415, 0x01f6fc9e);
4875 cx25840_write4(client, DIF_BPF_COEFF1617, 0x00440467);
4876 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfbccfdde);
4877 cx25840_write4(client, DIF_BPF_COEFF2021, 0x0738fc90);
4878 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf9f70934);
4879 cx25840_write4(client, DIF_BPF_COEFF2425, 0xff99f582);
4880 cx25840_write4(client, DIF_BPF_COEFF2627, 0x090204b0);
4881 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf21a05e1);
4882 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0a8df15a);
4883 cx25840_write4(client, DIF_BPF_COEFF3233, 0x00340f41);
4884 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf405f98b);
4885 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4886 break;
4887
4888 case 15700000:
4889 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000003);
4890 cx25840_write4(client, DIF_BPF_COEFF23, 0xfffcfff4);
4891 cx25840_write4(client, DIF_BPF_COEFF45, 0x0020fffa);
4892 cx25840_write4(client, DIF_BPF_COEFF67, 0xffb40064);
4893 cx25840_write4(client, DIF_BPF_COEFF89, 0x002fff11);
4894 cx25840_write4(client, DIF_BPF_COEFF1011, 0x00a400f0);
4895 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe0d006e);
4896 cx25840_write4(client, DIF_BPF_COEFF1415, 0x0281fd09);
4897 cx25840_write4(client, DIF_BPF_COEFF1617, 0xff3604c9);
4898 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfcbffca2);
4899 cx25840_write4(client, DIF_BPF_COEFF2021, 0x0726fdfe);
4900 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf8e80888);
4901 cx25840_write4(client, DIF_BPF_COEFF2425, 0x0134f4f3);
4902 cx25840_write4(client, DIF_BPF_COEFF2627, 0x07e1060c);
4903 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf22304af);
4904 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0b59f1be);
4905 cx25840_write4(client, DIF_BPF_COEFF3233, 0xff640f7d);
4906 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf452f959);
4907 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4908 break;
4909
4910 case 15800000:
4911 cx25840_write4(client, DIF_BPF_COEFF01, 0x00000003);
4912 cx25840_write4(client, DIF_BPF_COEFF23, 0x0000fff0);
4913 cx25840_write4(client, DIF_BPF_COEFF45, 0x001a0010);
4914 cx25840_write4(client, DIF_BPF_COEFF67, 0xffaa0041);
4915 cx25840_write4(client, DIF_BPF_COEFF89, 0x0067ff13);
4916 cx25840_write4(client, DIF_BPF_COEFF1011, 0x0043014a);
4917 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe46ffb9);
4918 cx25840_write4(client, DIF_BPF_COEFF1415, 0x02dbfda8);
4919 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfe3504e5);
4920 cx25840_write4(client, DIF_BPF_COEFF1819, 0xfddcfb8d);
4921 cx25840_write4(client, DIF_BPF_COEFF2021, 0x06c9ff7e);
4922 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf81107a2);
4923 cx25840_write4(client, DIF_BPF_COEFF2425, 0x02c9f49a);
4924 cx25840_write4(client, DIF_BPF_COEFF2627, 0x069f0753);
4925 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf2500373);
4926 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0c14f231);
4927 cx25840_write4(client, DIF_BPF_COEFF3233, 0xfe930fb3);
4928 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf4a1f927);
4929 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4930 break;
4931
4932 case 15900000:
4933 cx25840_write4(client, DIF_BPF_COEFF01, 0xffff0002);
4934 cx25840_write4(client, DIF_BPF_COEFF23, 0x0003ffee);
4935 cx25840_write4(client, DIF_BPF_COEFF45, 0x000f0023);
4936 cx25840_write4(client, DIF_BPF_COEFF67, 0xffac0016);
4937 cx25840_write4(client, DIF_BPF_COEFF89, 0x0093ff31);
4938 cx25840_write4(client, DIF_BPF_COEFF1011, 0xffdc0184);
4939 cx25840_write4(client, DIF_BPF_COEFF1213, 0xfea6ff09);
4940 cx25840_write4(client, DIF_BPF_COEFF1415, 0x02fdfe70);
4941 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfd5104ba);
4942 cx25840_write4(client, DIF_BPF_COEFF1819, 0xff15faac);
4943 cx25840_write4(client, DIF_BPF_COEFF2021, 0x06270103);
4944 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf7780688);
4945 cx25840_write4(client, DIF_BPF_COEFF2425, 0x044df479);
4946 cx25840_write4(client, DIF_BPF_COEFF2627, 0x05430883);
4947 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf2a00231);
4948 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0cbef2b2);
4949 cx25840_write4(client, DIF_BPF_COEFF3233, 0xfdc40fe3);
4950 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf4f2f8f5);
4951 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4952 break;
4953
4954 case 16000000:
4955 cx25840_write4(client, DIF_BPF_COEFF01, 0xffff0001);
4956 cx25840_write4(client, DIF_BPF_COEFF23, 0x0006ffef);
4957 cx25840_write4(client, DIF_BPF_COEFF45, 0x00020031);
4958 cx25840_write4(client, DIF_BPF_COEFF67, 0xffbaffe8);
4959 cx25840_write4(client, DIF_BPF_COEFF89, 0x00adff66);
4960 cx25840_write4(client, DIF_BPF_COEFF1011, 0xff790198);
4961 cx25840_write4(client, DIF_BPF_COEFF1213, 0xff26fe6e);
4962 cx25840_write4(client, DIF_BPF_COEFF1415, 0x02e5ff55);
4963 cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc99044a);
4964 cx25840_write4(client, DIF_BPF_COEFF1819, 0x005bfa09);
4965 cx25840_write4(client, DIF_BPF_COEFF2021, 0x0545027f);
4966 cx25840_write4(client, DIF_BPF_COEFF2223, 0xf7230541);
4967 cx25840_write4(client, DIF_BPF_COEFF2425, 0x05b8f490);
4968 cx25840_write4(client, DIF_BPF_COEFF2627, 0x03d20997);
4969 cx25840_write4(client, DIF_BPF_COEFF2829, 0xf31300eb);
4970 cx25840_write4(client, DIF_BPF_COEFF3031, 0x0d55f341);
4971 cx25840_write4(client, DIF_BPF_COEFF3233, 0xfcf6100e);
4972 cx25840_write4(client, DIF_BPF_COEFF3435, 0xf544f8c3);
4973 cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
4974 break;
4975 }
4976}
4977
4978static void cx23888_std_setup(struct i2c_client *client)
4979{
4980 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
4981 v4l2_std_id std = state->std;
4982 u32 ifHz;
4983
4984 cx25840_write4(client, 0x478, 0x6628021F);
4985 cx25840_write4(client, 0x400, 0x0);
4986 cx25840_write4(client, 0x4b4, 0x20524030);
4987 cx25840_write4(client, 0x47c, 0x010a8263);
4988
4989 if (std & V4L2_STD_NTSC) {
4990 v4l_dbg(1, cx25840_debug, client, "%s() Selecting NTSC",
4991 __func__);
4992
4993 /* Horiz / vert timing */
4994 cx25840_write4(client, 0x428, 0x1e1e601a);
4995 cx25840_write4(client, 0x424, 0x5b2d007a);
4996
4997 /* DIF NTSC */
4998 cx25840_write4(client, 0x304, 0x6503bc0c);
4999 cx25840_write4(client, 0x308, 0xbd038c85);
5000 cx25840_write4(client, 0x30c, 0x1db4640a);
5001 cx25840_write4(client, 0x310, 0x00008800);
5002 cx25840_write4(client, 0x314, 0x44400400);
5003 cx25840_write4(client, 0x32c, 0x0c800800);
5004 cx25840_write4(client, 0x330, 0x27000100);
5005 cx25840_write4(client, 0x334, 0x1f296e1f);
5006 cx25840_write4(client, 0x338, 0x009f50c1);
5007 cx25840_write4(client, 0x340, 0x1befbf06);
5008 cx25840_write4(client, 0x344, 0x000035e8);
5009
5010 /* DIF I/F */
5011 ifHz = 5400000;
5012
5013 } else {
5014 v4l_dbg(1, cx25840_debug, client, "%s() Selecting PAL-BG",
5015 __func__);
5016
5017 /* Horiz / vert timing */
5018 cx25840_write4(client, 0x428, 0x28244024);
5019 cx25840_write4(client, 0x424, 0x5d2d0084);
5020
5021 /* DIF */
5022 cx25840_write4(client, 0x304, 0x6503bc0c);
5023 cx25840_write4(client, 0x308, 0xbd038c85);
5024 cx25840_write4(client, 0x30c, 0x1db4640a);
5025 cx25840_write4(client, 0x310, 0x00008800);
5026 cx25840_write4(client, 0x314, 0x44400600);
5027 cx25840_write4(client, 0x32c, 0x0c800800);
5028 cx25840_write4(client, 0x330, 0x27000100);
5029 cx25840_write4(client, 0x334, 0x213530ec);
5030 cx25840_write4(client, 0x338, 0x00a65ba8);
5031 cx25840_write4(client, 0x340, 0x1befbf06);
5032 cx25840_write4(client, 0x344, 0x000035e8);
5033
5034 /* DIF I/F */
5035 ifHz = 6000000;
5036 }
5037
5038 cx23885_dif_setup(client, ifHz);
5039
5040 /* Explicitly ensure the inputs are reconfigured after
5041 * a standard change.
5042 */
5043 set_input(client, state->vid_input, state->aud_input);
5044}
5045
5046/* ----------------------------------------------------------------------- */
5047
5048static const struct v4l2_ctrl_ops cx25840_ctrl_ops = {
5049 .s_ctrl = cx25840_s_ctrl,
5050};
5051
5052static const struct v4l2_subdev_core_ops cx25840_core_ops = {
5053 .log_status = cx25840_log_status,
5054 .g_chip_ident = cx25840_g_chip_ident,
5055 .g_ctrl = v4l2_subdev_g_ctrl,
5056 .s_ctrl = v4l2_subdev_s_ctrl,
5057 .s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
5058 .try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
5059 .g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
5060 .queryctrl = v4l2_subdev_queryctrl,
5061 .querymenu = v4l2_subdev_querymenu,
5062 .s_std = cx25840_s_std,
5063 .g_std = cx25840_g_std,
5064 .reset = cx25840_reset,
5065 .load_fw = cx25840_load_fw,
5066 .s_io_pin_config = common_s_io_pin_config,
5067#ifdef CONFIG_VIDEO_ADV_DEBUG
5068 .g_register = cx25840_g_register,
5069 .s_register = cx25840_s_register,
5070#endif
5071 .interrupt_service_routine = cx25840_irq_handler,
5072};
5073
5074static const struct v4l2_subdev_tuner_ops cx25840_tuner_ops = {
5075 .s_frequency = cx25840_s_frequency,
5076 .s_radio = cx25840_s_radio,
5077 .g_tuner = cx25840_g_tuner,
5078 .s_tuner = cx25840_s_tuner,
5079};
5080
5081static const struct v4l2_subdev_audio_ops cx25840_audio_ops = {
5082 .s_clock_freq = cx25840_s_clock_freq,
5083 .s_routing = cx25840_s_audio_routing,
5084 .s_stream = cx25840_s_audio_stream,
5085};
5086
5087static const struct v4l2_subdev_video_ops cx25840_video_ops = {
5088 .s_routing = cx25840_s_video_routing,
5089 .s_mbus_fmt = cx25840_s_mbus_fmt,
5090 .s_stream = cx25840_s_stream,
5091 .g_input_status = cx25840_g_input_status,
5092};
5093
5094static const struct v4l2_subdev_vbi_ops cx25840_vbi_ops = {
5095 .decode_vbi_line = cx25840_decode_vbi_line,
5096 .s_raw_fmt = cx25840_s_raw_fmt,
5097 .s_sliced_fmt = cx25840_s_sliced_fmt,
5098 .g_sliced_fmt = cx25840_g_sliced_fmt,
5099};
5100
5101static const struct v4l2_subdev_ops cx25840_ops = {
5102 .core = &cx25840_core_ops,
5103 .tuner = &cx25840_tuner_ops,
5104 .audio = &cx25840_audio_ops,
5105 .video = &cx25840_video_ops,
5106 .vbi = &cx25840_vbi_ops,
5107 .ir = &cx25840_ir_ops,
5108};
5109
5110/* ----------------------------------------------------------------------- */
5111
5112static u32 get_cx2388x_ident(struct i2c_client *client)
5113{
5114 u32 ret;
5115
5116 /* Come out of digital power down */
5117 cx25840_write(client, 0x000, 0);
5118
5119 /* Detecting whether the part is cx23885/7/8 is more
5120 * difficult than it needs to be. No ID register. Instead we
5121 * probe certain registers indicated in the datasheets to look
5122 * for specific defaults that differ between the silicon designs. */
5123
5124 /* It's either 885/7 if the IR Tx Clk Divider register exists */
5125 if (cx25840_read4(client, 0x204) & 0xffff) {
5126 /* CX23885 returns bogus repetitive byte values for the DIF,
5127 * which doesn't exist for it. (Ex. 8a8a8a8a or 31313131) */
5128 ret = cx25840_read4(client, 0x300);
5129 if (((ret & 0xffff0000) >> 16) == (ret & 0xffff)) {
5130 /* No DIF */
5131 ret = V4L2_IDENT_CX23885_AV;
5132 } else {
5133 /* CX23887 has a broken DIF, but the registers
5134 * appear valid (but unused), good enough to detect. */
5135 ret = V4L2_IDENT_CX23887_AV;
5136 }
5137 } else if (cx25840_read4(client, 0x300) & 0x0fffffff) {
5138 /* DIF PLL Freq Word reg exists; chip must be a CX23888 */
5139 ret = V4L2_IDENT_CX23888_AV;
5140 } else {
5141 v4l_err(client, "Unable to detect h/w, assuming cx23887\n");
5142 ret = V4L2_IDENT_CX23887_AV;
5143 }
5144
5145 /* Back into digital power down */
5146 cx25840_write(client, 0x000, 2);
5147 return ret;
5148}
5149
5150static int cx25840_probe(struct i2c_client *client,
5151 const struct i2c_device_id *did)
5152{
5153 struct cx25840_state *state;
5154 struct v4l2_subdev *sd;
5155 int default_volume;
5156 u32 id = V4L2_IDENT_NONE;
5157 u16 device_id;
5158
5159 /* Check if the adapter supports the needed features */
5160 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
5161 return -EIO;
5162
5163 v4l_dbg(1, cx25840_debug, client, "detecting cx25840 client on address 0x%x\n", client->addr << 1);
5164
5165 device_id = cx25840_read(client, 0x101) << 8;
5166 device_id |= cx25840_read(client, 0x100);
5167 v4l_dbg(1, cx25840_debug, client, "device_id = 0x%04x\n", device_id);
5168
5169 /* The high byte of the device ID should be
5170 * 0x83 for the cx2583x and 0x84 for the cx2584x */
5171 if ((device_id & 0xff00) == 0x8300) {
5172 id = V4L2_IDENT_CX25836 + ((device_id >> 4) & 0xf) - 6;
5173 } else if ((device_id & 0xff00) == 0x8400) {
5174 id = V4L2_IDENT_CX25840 + ((device_id >> 4) & 0xf);
5175 } else if (device_id == 0x0000) {
5176 id = get_cx2388x_ident(client);
5177 } else if ((device_id & 0xfff0) == 0x5A30) {
5178 /* The CX23100 (0x5A3C = 23100) doesn't have an A/V decoder */
5179 id = V4L2_IDENT_CX2310X_AV;
5180 } else if ((device_id & 0xff) == (device_id >> 8)) {
5181 v4l_err(client,
5182 "likely a confused/unresponsive cx2388[578] A/V decoder"
5183 " found @ 0x%x (%s)\n",
5184 client->addr << 1, client->adapter->name);
5185 v4l_err(client, "A method to reset it from the cx25840 driver"
5186 " software is not known at this time\n");
5187 return -ENODEV;
5188 } else {
5189 v4l_dbg(1, cx25840_debug, client, "cx25840 not found\n");
5190 return -ENODEV;
5191 }
5192
5193 state = kzalloc(sizeof(struct cx25840_state), GFP_KERNEL);
5194 if (state == NULL)
5195 return -ENOMEM;
5196
5197 sd = &state->sd;
5198 v4l2_i2c_subdev_init(sd, client, &cx25840_ops);
5199
5200 switch (id) {
5201 case V4L2_IDENT_CX23885_AV:
5202 v4l_info(client, "cx23885 A/V decoder found @ 0x%x (%s)\n",
5203 client->addr << 1, client->adapter->name);
5204 break;
5205 case V4L2_IDENT_CX23887_AV:
5206 v4l_info(client, "cx23887 A/V decoder found @ 0x%x (%s)\n",
5207 client->addr << 1, client->adapter->name);
5208 break;
5209 case V4L2_IDENT_CX23888_AV:
5210 v4l_info(client, "cx23888 A/V decoder found @ 0x%x (%s)\n",
5211 client->addr << 1, client->adapter->name);
5212 break;
5213 case V4L2_IDENT_CX2310X_AV:
5214 v4l_info(client, "cx%d A/V decoder found @ 0x%x (%s)\n",
5215 device_id, client->addr << 1, client->adapter->name);
5216 break;
5217 case V4L2_IDENT_CX25840:
5218 case V4L2_IDENT_CX25841:
5219 case V4L2_IDENT_CX25842:
5220 case V4L2_IDENT_CX25843:
5221 /* Note: revision '(device_id & 0x0f) == 2' was never built. The
5222 marking skips from 0x1 == 22 to 0x3 == 23. */
5223 v4l_info(client, "cx25%3x-2%x found @ 0x%x (%s)\n",
5224 (device_id & 0xfff0) >> 4,
5225 (device_id & 0x0f) < 3 ? (device_id & 0x0f) + 1
5226 : (device_id & 0x0f),
5227 client->addr << 1, client->adapter->name);
5228 break;
5229 case V4L2_IDENT_CX25836:
5230 case V4L2_IDENT_CX25837:
5231 default:
5232 v4l_info(client, "cx25%3x-%x found @ 0x%x (%s)\n",
5233 (device_id & 0xfff0) >> 4, device_id & 0x0f,
5234 client->addr << 1, client->adapter->name);
5235 break;
5236 }
5237
5238 state->c = client;
5239 state->vid_input = CX25840_COMPOSITE7;
5240 state->aud_input = CX25840_AUDIO8;
5241 state->audclk_freq = 48000;
5242 state->audmode = V4L2_TUNER_MODE_LANG1;
5243 state->vbi_line_offset = 8;
5244 state->id = id;
5245 state->rev = device_id;
5246 v4l2_ctrl_handler_init(&state->hdl, 9);
5247 v4l2_ctrl_new_std(&state->hdl, &cx25840_ctrl_ops,
5248 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
5249 v4l2_ctrl_new_std(&state->hdl, &cx25840_ctrl_ops,
5250 V4L2_CID_CONTRAST, 0, 127, 1, 64);
5251 v4l2_ctrl_new_std(&state->hdl, &cx25840_ctrl_ops,
5252 V4L2_CID_SATURATION, 0, 127, 1, 64);
5253 v4l2_ctrl_new_std(&state->hdl, &cx25840_ctrl_ops,
5254 V4L2_CID_HUE, -128, 127, 1, 0);
5255 if (!is_cx2583x(state)) {
5256 default_volume = cx25840_read(client, 0x8d4);
5257 /*
5258 * Enforce the legacy PVR-350/MSP3400 to PVR-150/CX25843 volume
5259 * scale mapping limits to avoid -ERANGE errors when
5260 * initializing the volume control
5261 */
5262 if (default_volume > 228) {
5263 /* Bottom out at -96 dB, v4l2 vol range 0x2e00-0x2fff */
5264 default_volume = 228;
5265 cx25840_write(client, 0x8d4, 228);
5266 }
5267 else if (default_volume < 20) {
5268 /* Top out at + 8 dB, v4l2 vol range 0xfe00-0xffff */
5269 default_volume = 20;
5270 cx25840_write(client, 0x8d4, 20);
5271 }
5272 default_volume = (((228 - default_volume) >> 1) + 23) << 9;
5273
5274 state->volume = v4l2_ctrl_new_std(&state->hdl,
5275 &cx25840_audio_ctrl_ops, V4L2_CID_AUDIO_VOLUME,
5276 0, 65535, 65535 / 100, default_volume);
5277 state->mute = v4l2_ctrl_new_std(&state->hdl,
5278 &cx25840_audio_ctrl_ops, V4L2_CID_AUDIO_MUTE,
5279 0, 1, 1, 0);
5280 v4l2_ctrl_new_std(&state->hdl, &cx25840_audio_ctrl_ops,
5281 V4L2_CID_AUDIO_BALANCE,
5282 0, 65535, 65535 / 100, 32768);
5283 v4l2_ctrl_new_std(&state->hdl, &cx25840_audio_ctrl_ops,
5284 V4L2_CID_AUDIO_BASS,
5285 0, 65535, 65535 / 100, 32768);
5286 v4l2_ctrl_new_std(&state->hdl, &cx25840_audio_ctrl_ops,
5287 V4L2_CID_AUDIO_TREBLE,
5288 0, 65535, 65535 / 100, 32768);
5289 }
5290 sd->ctrl_handler = &state->hdl;
5291 if (state->hdl.error) {
5292 int err = state->hdl.error;
5293
5294 v4l2_ctrl_handler_free(&state->hdl);
5295 kfree(state);
5296 return err;
5297 }
5298 if (!is_cx2583x(state))
5299 v4l2_ctrl_cluster(2, &state->volume);
5300 v4l2_ctrl_handler_setup(&state->hdl);
5301
5302 if (client->dev.platform_data) {
5303 struct cx25840_platform_data *pdata = client->dev.platform_data;
5304
5305 state->pvr150_workaround = pdata->pvr150_workaround;
5306 }
5307
5308 cx25840_ir_probe(sd);
5309 return 0;
5310}
5311
5312static int cx25840_remove(struct i2c_client *client)
5313{
5314 struct v4l2_subdev *sd = i2c_get_clientdata(client);
5315 struct cx25840_state *state = to_state(sd);
5316
5317 cx25840_ir_remove(sd);
5318 v4l2_device_unregister_subdev(sd);
5319 v4l2_ctrl_handler_free(&state->hdl);
5320 kfree(state);
5321 return 0;
5322}
5323
5324static const struct i2c_device_id cx25840_id[] = {
5325 { "cx25840", 0 },
5326 { }
5327};
5328MODULE_DEVICE_TABLE(i2c, cx25840_id);
5329
5330static struct i2c_driver cx25840_driver = {
5331 .driver = {
5332 .owner = THIS_MODULE,
5333 .name = "cx25840",
5334 },
5335 .probe = cx25840_probe,
5336 .remove = cx25840_remove,
5337 .id_table = cx25840_id,
5338};
5339
5340module_i2c_driver(cx25840_driver);
diff --git a/drivers/media/i2c/cx25840/cx25840-core.h b/drivers/media/i2c/cx25840/cx25840-core.h
new file mode 100644
index 000000000000..bd4ada28b490
--- /dev/null
+++ b/drivers/media/i2c/cx25840/cx25840-core.h
@@ -0,0 +1,137 @@
1/* cx25840 internal API header
2 *
3 * Copyright (C) 2003-2004 Chris Kennedy
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
18 */
19
20#ifndef _CX25840_CORE_H_
21#define _CX25840_CORE_H_
22
23
24#include <linux/videodev2.h>
25#include <media/v4l2-device.h>
26#include <media/v4l2-chip-ident.h>
27#include <media/v4l2-ctrls.h>
28#include <linux/i2c.h>
29
30struct cx25840_ir_state;
31
32struct cx25840_state {
33 struct i2c_client *c;
34 struct v4l2_subdev sd;
35 struct v4l2_ctrl_handler hdl;
36 struct {
37 /* volume cluster */
38 struct v4l2_ctrl *volume;
39 struct v4l2_ctrl *mute;
40 };
41 int pvr150_workaround;
42 int radio;
43 v4l2_std_id std;
44 enum cx25840_video_input vid_input;
45 enum cx25840_audio_input aud_input;
46 u32 audclk_freq;
47 int audmode;
48 int vbi_line_offset;
49 u32 id;
50 u32 rev;
51 int is_initialized;
52 wait_queue_head_t fw_wait; /* wake up when the fw load is finished */
53 struct work_struct fw_work; /* work entry for fw load */
54 struct cx25840_ir_state *ir_state;
55};
56
57static inline struct cx25840_state *to_state(struct v4l2_subdev *sd)
58{
59 return container_of(sd, struct cx25840_state, sd);
60}
61
62static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
63{
64 return &container_of(ctrl->handler, struct cx25840_state, hdl)->sd;
65}
66
67static inline bool is_cx2583x(struct cx25840_state *state)
68{
69 return state->id == V4L2_IDENT_CX25836 ||
70 state->id == V4L2_IDENT_CX25837;
71}
72
73static inline bool is_cx231xx(struct cx25840_state *state)
74{
75 return state->id == V4L2_IDENT_CX2310X_AV;
76}
77
78static inline bool is_cx2388x(struct cx25840_state *state)
79{
80 return state->id == V4L2_IDENT_CX23885_AV ||
81 state->id == V4L2_IDENT_CX23887_AV ||
82 state->id == V4L2_IDENT_CX23888_AV;
83}
84
85static inline bool is_cx23885(struct cx25840_state *state)
86{
87 return state->id == V4L2_IDENT_CX23885_AV;
88}
89
90static inline bool is_cx23887(struct cx25840_state *state)
91{
92 return state->id == V4L2_IDENT_CX23887_AV;
93}
94
95static inline bool is_cx23888(struct cx25840_state *state)
96{
97 return state->id == V4L2_IDENT_CX23888_AV;
98}
99
100/* ----------------------------------------------------------------------- */
101/* cx25850-core.c */
102int cx25840_write(struct i2c_client *client, u16 addr, u8 value);
103int cx25840_write4(struct i2c_client *client, u16 addr, u32 value);
104u8 cx25840_read(struct i2c_client *client, u16 addr);
105u32 cx25840_read4(struct i2c_client *client, u16 addr);
106int cx25840_and_or(struct i2c_client *client, u16 addr, unsigned mask, u8 value);
107int cx25840_and_or4(struct i2c_client *client, u16 addr, u32 and_mask,
108 u32 or_value);
109void cx25840_std_setup(struct i2c_client *client);
110
111/* ----------------------------------------------------------------------- */
112/* cx25850-firmware.c */
113int cx25840_loadfw(struct i2c_client *client);
114
115/* ----------------------------------------------------------------------- */
116/* cx25850-audio.c */
117void cx25840_audio_set_path(struct i2c_client *client);
118int cx25840_s_clock_freq(struct v4l2_subdev *sd, u32 freq);
119
120extern const struct v4l2_ctrl_ops cx25840_audio_ctrl_ops;
121
122/* ----------------------------------------------------------------------- */
123/* cx25850-vbi.c */
124int cx25840_s_raw_fmt(struct v4l2_subdev *sd, struct v4l2_vbi_format *fmt);
125int cx25840_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt);
126int cx25840_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt);
127int cx25840_decode_vbi_line(struct v4l2_subdev *sd, struct v4l2_decode_vbi_line *vbi);
128
129/* ----------------------------------------------------------------------- */
130/* cx25850-ir.c */
131extern const struct v4l2_subdev_ir_ops cx25840_ir_ops;
132int cx25840_ir_log_status(struct v4l2_subdev *sd);
133int cx25840_ir_irq_handler(struct v4l2_subdev *sd, u32 status, bool *handled);
134int cx25840_ir_probe(struct v4l2_subdev *sd);
135int cx25840_ir_remove(struct v4l2_subdev *sd);
136
137#endif
diff --git a/drivers/media/i2c/cx25840/cx25840-firmware.c b/drivers/media/i2c/cx25840/cx25840-firmware.c
new file mode 100644
index 000000000000..b3169f94ece8
--- /dev/null
+++ b/drivers/media/i2c/cx25840/cx25840-firmware.c
@@ -0,0 +1,175 @@
1/* cx25840 firmware functions
2 *
3 * This program is free software; you can redistribute it and/or
4 * modify it under the terms of the GNU General Public License
5 * as published by the Free Software Foundation; either version 2
6 * of the License, or (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
16 */
17
18#include <linux/module.h>
19#include <linux/i2c.h>
20#include <linux/firmware.h>
21#include <media/v4l2-common.h>
22#include <media/cx25840.h>
23
24#include "cx25840-core.h"
25
26/*
27 * Mike Isely <isely@pobox.com> - The FWSEND parameter controls the
28 * size of the firmware chunks sent down the I2C bus to the chip.
29 * Previously this had been set to 1024 but unfortunately some I2C
30 * implementations can't transfer data in such big gulps.
31 * Specifically, the pvrusb2 driver has a hard limit of around 60
32 * bytes, due to the encapsulation there of I2C traffic into USB
33 * messages. So we have to significantly reduce this parameter.
34 */
35#define FWSEND 48
36
37#define FWDEV(x) &((x)->dev)
38
39static char *firmware = "";
40
41module_param(firmware, charp, 0444);
42
43MODULE_PARM_DESC(firmware, "Firmware image to load");
44
45static void start_fw_load(struct i2c_client *client)
46{
47 /* DL_ADDR_LB=0 DL_ADDR_HB=0 */
48 cx25840_write(client, 0x800, 0x00);
49 cx25840_write(client, 0x801, 0x00);
50 // DL_MAP=3 DL_AUTO_INC=0 DL_ENABLE=1
51 cx25840_write(client, 0x803, 0x0b);
52 /* AUTO_INC_DIS=1 */
53 cx25840_write(client, 0x000, 0x20);
54}
55
56static void end_fw_load(struct i2c_client *client)
57{
58 /* AUTO_INC_DIS=0 */
59 cx25840_write(client, 0x000, 0x00);
60 /* DL_ENABLE=0 */
61 cx25840_write(client, 0x803, 0x03);
62}
63
64#define CX2388x_FIRMWARE "v4l-cx23885-avcore-01.fw"
65#define CX231xx_FIRMWARE "v4l-cx231xx-avcore-01.fw"
66#define CX25840_FIRMWARE "v4l-cx25840.fw"
67
68static const char *get_fw_name(struct i2c_client *client)
69{
70 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
71
72 if (firmware[0])
73 return firmware;
74 if (is_cx2388x(state))
75 return CX2388x_FIRMWARE;
76 if (is_cx231xx(state))
77 return CX231xx_FIRMWARE;
78 return CX25840_FIRMWARE;
79}
80
81static int check_fw_load(struct i2c_client *client, int size)
82{
83 /* DL_ADDR_HB DL_ADDR_LB */
84 int s = cx25840_read(client, 0x801) << 8;
85 s |= cx25840_read(client, 0x800);
86
87 if (size != s) {
88 v4l_err(client, "firmware %s load failed\n",
89 get_fw_name(client));
90 return -EINVAL;
91 }
92
93 v4l_info(client, "loaded %s firmware (%d bytes)\n",
94 get_fw_name(client), size);
95 return 0;
96}
97
98static int fw_write(struct i2c_client *client, const u8 *data, int size)
99{
100 if (i2c_master_send(client, data, size) < size) {
101 v4l_err(client, "firmware load i2c failure\n");
102 return -ENOSYS;
103 }
104
105 return 0;
106}
107
108int cx25840_loadfw(struct i2c_client *client)
109{
110 struct cx25840_state *state = to_state(i2c_get_clientdata(client));
111 const struct firmware *fw = NULL;
112 u8 buffer[FWSEND];
113 const u8 *ptr;
114 const char *fwname = get_fw_name(client);
115 int size, retval;
116 int MAX_BUF_SIZE = FWSEND;
117 u32 gpio_oe = 0, gpio_da = 0;
118
119 if (is_cx2388x(state)) {
120 /* Preserve the GPIO OE and output bits */
121 gpio_oe = cx25840_read(client, 0x160);
122 gpio_da = cx25840_read(client, 0x164);
123 }
124
125 if (is_cx231xx(state) && MAX_BUF_SIZE > 16) {
126 v4l_err(client, " Firmware download size changed to 16 bytes max length\n");
127 MAX_BUF_SIZE = 16; /* cx231xx cannot accept more than 16 bytes at a time */
128 }
129
130 if (request_firmware(&fw, fwname, FWDEV(client)) != 0) {
131 v4l_err(client, "unable to open firmware %s\n", fwname);
132 return -EINVAL;
133 }
134
135 start_fw_load(client);
136
137 buffer[0] = 0x08;
138 buffer[1] = 0x02;
139
140 size = fw->size;
141 ptr = fw->data;
142 while (size > 0) {
143 int len = min(MAX_BUF_SIZE - 2, size);
144
145 memcpy(buffer + 2, ptr, len);
146
147 retval = fw_write(client, buffer, len + 2);
148
149 if (retval < 0) {
150 release_firmware(fw);
151 return retval;
152 }
153
154 size -= len;
155 ptr += len;
156 }
157
158 end_fw_load(client);
159
160 size = fw->size;
161 release_firmware(fw);
162
163 if (is_cx2388x(state)) {
164 /* Restore GPIO configuration after f/w load */
165 cx25840_write(client, 0x160, gpio_oe);
166 cx25840_write(client, 0x164, gpio_da);
167 }
168
169 return check_fw_load(client, size);
170}
171
172MODULE_FIRMWARE(CX2388x_FIRMWARE);
173MODULE_FIRMWARE(CX231xx_FIRMWARE);
174MODULE_FIRMWARE(CX25840_FIRMWARE);
175
diff --git a/drivers/media/i2c/cx25840/cx25840-ir.c b/drivers/media/i2c/cx25840/cx25840-ir.c
new file mode 100644
index 000000000000..38ce76ed1924
--- /dev/null
+++ b/drivers/media/i2c/cx25840/cx25840-ir.c
@@ -0,0 +1,1281 @@
1/*
2 * Driver for the Conexant CX2584x Audio/Video decoder chip and related cores
3 *
4 * Integrated Consumer Infrared Controller
5 *
6 * Copyright (C) 2010 Andy Walls <awalls@md.metrocast.net>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
21 * 02110-1301, USA.
22 */
23
24#include <linux/slab.h>
25#include <linux/kfifo.h>
26#include <linux/module.h>
27#include <media/cx25840.h>
28#include <media/rc-core.h>
29
30#include "cx25840-core.h"
31
32static unsigned int ir_debug;
33module_param(ir_debug, int, 0644);
34MODULE_PARM_DESC(ir_debug, "enable integrated IR debug messages");
35
36#define CX25840_IR_REG_BASE 0x200
37
38#define CX25840_IR_CNTRL_REG 0x200
39#define CNTRL_WIN_3_3 0x00000000
40#define CNTRL_WIN_4_3 0x00000001
41#define CNTRL_WIN_3_4 0x00000002
42#define CNTRL_WIN_4_4 0x00000003
43#define CNTRL_WIN 0x00000003
44#define CNTRL_EDG_NONE 0x00000000
45#define CNTRL_EDG_FALL 0x00000004
46#define CNTRL_EDG_RISE 0x00000008
47#define CNTRL_EDG_BOTH 0x0000000C
48#define CNTRL_EDG 0x0000000C
49#define CNTRL_DMD 0x00000010
50#define CNTRL_MOD 0x00000020
51#define CNTRL_RFE 0x00000040
52#define CNTRL_TFE 0x00000080
53#define CNTRL_RXE 0x00000100
54#define CNTRL_TXE 0x00000200
55#define CNTRL_RIC 0x00000400
56#define CNTRL_TIC 0x00000800
57#define CNTRL_CPL 0x00001000
58#define CNTRL_LBM 0x00002000
59#define CNTRL_R 0x00004000
60
61#define CX25840_IR_TXCLK_REG 0x204
62#define TXCLK_TCD 0x0000FFFF
63
64#define CX25840_IR_RXCLK_REG 0x208
65#define RXCLK_RCD 0x0000FFFF
66
67#define CX25840_IR_CDUTY_REG 0x20C
68#define CDUTY_CDC 0x0000000F
69
70#define CX25840_IR_STATS_REG 0x210
71#define STATS_RTO 0x00000001
72#define STATS_ROR 0x00000002
73#define STATS_RBY 0x00000004
74#define STATS_TBY 0x00000008
75#define STATS_RSR 0x00000010
76#define STATS_TSR 0x00000020
77
78#define CX25840_IR_IRQEN_REG 0x214
79#define IRQEN_RTE 0x00000001
80#define IRQEN_ROE 0x00000002
81#define IRQEN_RSE 0x00000010
82#define IRQEN_TSE 0x00000020
83#define IRQEN_MSK 0x00000033
84
85#define CX25840_IR_FILTR_REG 0x218
86#define FILTR_LPF 0x0000FFFF
87
88#define CX25840_IR_FIFO_REG 0x23C
89#define FIFO_RXTX 0x0000FFFF
90#define FIFO_RXTX_LVL 0x00010000
91#define FIFO_RXTX_RTO 0x0001FFFF
92#define FIFO_RX_NDV 0x00020000
93#define FIFO_RX_DEPTH 8
94#define FIFO_TX_DEPTH 8
95
96#define CX25840_VIDCLK_FREQ 108000000 /* 108 MHz, BT.656 */
97#define CX25840_IR_REFCLK_FREQ (CX25840_VIDCLK_FREQ / 2)
98
99/*
100 * We use this union internally for convenience, but callers to tx_write
101 * and rx_read will be expecting records of type struct ir_raw_event.
102 * Always ensure the size of this union is dictated by struct ir_raw_event.
103 */
104union cx25840_ir_fifo_rec {
105 u32 hw_fifo_data;
106 struct ir_raw_event ir_core_data;
107};
108
109#define CX25840_IR_RX_KFIFO_SIZE (256 * sizeof(union cx25840_ir_fifo_rec))
110#define CX25840_IR_TX_KFIFO_SIZE (256 * sizeof(union cx25840_ir_fifo_rec))
111
112struct cx25840_ir_state {
113 struct i2c_client *c;
114
115 struct v4l2_subdev_ir_parameters rx_params;
116 struct mutex rx_params_lock; /* protects Rx parameter settings cache */
117 atomic_t rxclk_divider;
118 atomic_t rx_invert;
119
120 struct kfifo rx_kfifo;
121 spinlock_t rx_kfifo_lock; /* protect Rx data kfifo */
122
123 struct v4l2_subdev_ir_parameters tx_params;
124 struct mutex tx_params_lock; /* protects Tx parameter settings cache */
125 atomic_t txclk_divider;
126};
127
128static inline struct cx25840_ir_state *to_ir_state(struct v4l2_subdev *sd)
129{
130 struct cx25840_state *state = to_state(sd);
131 return state ? state->ir_state : NULL;
132}
133
134
135/*
136 * Rx and Tx Clock Divider register computations
137 *
138 * Note the largest clock divider value of 0xffff corresponds to:
139 * (0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns
140 * which fits in 21 bits, so we'll use unsigned int for time arguments.
141 */
142static inline u16 count_to_clock_divider(unsigned int d)
143{
144 if (d > RXCLK_RCD + 1)
145 d = RXCLK_RCD;
146 else if (d < 2)
147 d = 1;
148 else
149 d--;
150 return (u16) d;
151}
152
153static inline u16 ns_to_clock_divider(unsigned int ns)
154{
155 return count_to_clock_divider(
156 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ / 1000000 * ns, 1000));
157}
158
159static inline unsigned int clock_divider_to_ns(unsigned int divider)
160{
161 /* Period of the Rx or Tx clock in ns */
162 return DIV_ROUND_CLOSEST((divider + 1) * 1000,
163 CX25840_IR_REFCLK_FREQ / 1000000);
164}
165
166static inline u16 carrier_freq_to_clock_divider(unsigned int freq)
167{
168 return count_to_clock_divider(
169 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, freq * 16));
170}
171
172static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider)
173{
174 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, (divider + 1) * 16);
175}
176
177static inline u16 freq_to_clock_divider(unsigned int freq,
178 unsigned int rollovers)
179{
180 return count_to_clock_divider(
181 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ, freq * rollovers));
182}
183
184static inline unsigned int clock_divider_to_freq(unsigned int divider,
185 unsigned int rollovers)
186{
187 return DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ,
188 (divider + 1) * rollovers);
189}
190
191/*
192 * Low Pass Filter register calculations
193 *
194 * Note the largest count value of 0xffff corresponds to:
195 * 0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns
196 * which fits in 21 bits, so we'll use unsigned int for time arguments.
197 */
198static inline u16 count_to_lpf_count(unsigned int d)
199{
200 if (d > FILTR_LPF)
201 d = FILTR_LPF;
202 else if (d < 4)
203 d = 0;
204 return (u16) d;
205}
206
207static inline u16 ns_to_lpf_count(unsigned int ns)
208{
209 return count_to_lpf_count(
210 DIV_ROUND_CLOSEST(CX25840_IR_REFCLK_FREQ / 1000000 * ns, 1000));
211}
212
213static inline unsigned int lpf_count_to_ns(unsigned int count)
214{
215 /* Duration of the Low Pass Filter rejection window in ns */
216 return DIV_ROUND_CLOSEST(count * 1000,
217 CX25840_IR_REFCLK_FREQ / 1000000);
218}
219
220static inline unsigned int lpf_count_to_us(unsigned int count)
221{
222 /* Duration of the Low Pass Filter rejection window in us */
223 return DIV_ROUND_CLOSEST(count, CX25840_IR_REFCLK_FREQ / 1000000);
224}
225
226/*
227 * FIFO register pulse width count compuations
228 */
229static u32 clock_divider_to_resolution(u16 divider)
230{
231 /*
232 * Resolution is the duration of 1 tick of the readable portion of
233 * of the pulse width counter as read from the FIFO. The two lsb's are
234 * not readable, hence the << 2. This function returns ns.
235 */
236 return DIV_ROUND_CLOSEST((1 << 2) * ((u32) divider + 1) * 1000,
237 CX25840_IR_REFCLK_FREQ / 1000000);
238}
239
240static u64 pulse_width_count_to_ns(u16 count, u16 divider)
241{
242 u64 n;
243 u32 rem;
244
245 /*
246 * The 2 lsb's of the pulse width timer count are not readable, hence
247 * the (count << 2) | 0x3
248 */
249 n = (((u64) count << 2) | 0x3) * (divider + 1) * 1000; /* millicycles */
250 rem = do_div(n, CX25840_IR_REFCLK_FREQ / 1000000); /* / MHz => ns */
251 if (rem >= CX25840_IR_REFCLK_FREQ / 1000000 / 2)
252 n++;
253 return n;
254}
255
256#if 0
257/* Keep as we will need this for Transmit functionality */
258static u16 ns_to_pulse_width_count(u32 ns, u16 divider)
259{
260 u64 n;
261 u32 d;
262 u32 rem;
263
264 /*
265 * The 2 lsb's of the pulse width timer count are not accessible, hence
266 * the (1 << 2)
267 */
268 n = ((u64) ns) * CX25840_IR_REFCLK_FREQ / 1000000; /* millicycles */
269 d = (1 << 2) * ((u32) divider + 1) * 1000; /* millicycles/count */
270 rem = do_div(n, d);
271 if (rem >= d / 2)
272 n++;
273
274 if (n > FIFO_RXTX)
275 n = FIFO_RXTX;
276 else if (n == 0)
277 n = 1;
278 return (u16) n;
279}
280
281#endif
282static unsigned int pulse_width_count_to_us(u16 count, u16 divider)
283{
284 u64 n;
285 u32 rem;
286
287 /*
288 * The 2 lsb's of the pulse width timer count are not readable, hence
289 * the (count << 2) | 0x3
290 */
291 n = (((u64) count << 2) | 0x3) * (divider + 1); /* cycles */
292 rem = do_div(n, CX25840_IR_REFCLK_FREQ / 1000000); /* / MHz => us */
293 if (rem >= CX25840_IR_REFCLK_FREQ / 1000000 / 2)
294 n++;
295 return (unsigned int) n;
296}
297
298/*
299 * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts
300 *
301 * The total pulse clock count is an 18 bit pulse width timer count as the most
302 * significant part and (up to) 16 bit clock divider count as a modulus.
303 * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse
304 * width timer count's least significant bit.
305 */
306static u64 ns_to_pulse_clocks(u32 ns)
307{
308 u64 clocks;
309 u32 rem;
310 clocks = CX25840_IR_REFCLK_FREQ / 1000000 * (u64) ns; /* millicycles */
311 rem = do_div(clocks, 1000); /* /1000 = cycles */
312 if (rem >= 1000 / 2)
313 clocks++;
314 return clocks;
315}
316
317static u16 pulse_clocks_to_clock_divider(u64 count)
318{
319 do_div(count, (FIFO_RXTX << 2) | 0x3);
320
321 /* net result needs to be rounded down and decremented by 1 */
322 if (count > RXCLK_RCD + 1)
323 count = RXCLK_RCD;
324 else if (count < 2)
325 count = 1;
326 else
327 count--;
328 return (u16) count;
329}
330
331/*
332 * IR Control Register helpers
333 */
334enum tx_fifo_watermark {
335 TX_FIFO_HALF_EMPTY = 0,
336 TX_FIFO_EMPTY = CNTRL_TIC,
337};
338
339enum rx_fifo_watermark {
340 RX_FIFO_HALF_FULL = 0,
341 RX_FIFO_NOT_EMPTY = CNTRL_RIC,
342};
343
344static inline void control_tx_irq_watermark(struct i2c_client *c,
345 enum tx_fifo_watermark level)
346{
347 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_TIC, level);
348}
349
350static inline void control_rx_irq_watermark(struct i2c_client *c,
351 enum rx_fifo_watermark level)
352{
353 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_RIC, level);
354}
355
356static inline void control_tx_enable(struct i2c_client *c, bool enable)
357{
358 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~(CNTRL_TXE | CNTRL_TFE),
359 enable ? (CNTRL_TXE | CNTRL_TFE) : 0);
360}
361
362static inline void control_rx_enable(struct i2c_client *c, bool enable)
363{
364 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~(CNTRL_RXE | CNTRL_RFE),
365 enable ? (CNTRL_RXE | CNTRL_RFE) : 0);
366}
367
368static inline void control_tx_modulation_enable(struct i2c_client *c,
369 bool enable)
370{
371 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_MOD,
372 enable ? CNTRL_MOD : 0);
373}
374
375static inline void control_rx_demodulation_enable(struct i2c_client *c,
376 bool enable)
377{
378 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_DMD,
379 enable ? CNTRL_DMD : 0);
380}
381
382static inline void control_rx_s_edge_detection(struct i2c_client *c,
383 u32 edge_types)
384{
385 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_EDG_BOTH,
386 edge_types & CNTRL_EDG_BOTH);
387}
388
389static void control_rx_s_carrier_window(struct i2c_client *c,
390 unsigned int carrier,
391 unsigned int *carrier_range_low,
392 unsigned int *carrier_range_high)
393{
394 u32 v;
395 unsigned int c16 = carrier * 16;
396
397 if (*carrier_range_low < DIV_ROUND_CLOSEST(c16, 16 + 3)) {
398 v = CNTRL_WIN_3_4;
399 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 4);
400 } else {
401 v = CNTRL_WIN_3_3;
402 *carrier_range_low = DIV_ROUND_CLOSEST(c16, 16 + 3);
403 }
404
405 if (*carrier_range_high > DIV_ROUND_CLOSEST(c16, 16 - 3)) {
406 v |= CNTRL_WIN_4_3;
407 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 4);
408 } else {
409 v |= CNTRL_WIN_3_3;
410 *carrier_range_high = DIV_ROUND_CLOSEST(c16, 16 - 3);
411 }
412 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_WIN, v);
413}
414
415static inline void control_tx_polarity_invert(struct i2c_client *c,
416 bool invert)
417{
418 cx25840_and_or4(c, CX25840_IR_CNTRL_REG, ~CNTRL_CPL,
419 invert ? CNTRL_CPL : 0);
420}
421
422/*
423 * IR Rx & Tx Clock Register helpers
424 */
425static unsigned int txclk_tx_s_carrier(struct i2c_client *c,
426 unsigned int freq,
427 u16 *divider)
428{
429 *divider = carrier_freq_to_clock_divider(freq);
430 cx25840_write4(c, CX25840_IR_TXCLK_REG, *divider);
431 return clock_divider_to_carrier_freq(*divider);
432}
433
434static unsigned int rxclk_rx_s_carrier(struct i2c_client *c,
435 unsigned int freq,
436 u16 *divider)
437{
438 *divider = carrier_freq_to_clock_divider(freq);
439 cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider);
440 return clock_divider_to_carrier_freq(*divider);
441}
442
443static u32 txclk_tx_s_max_pulse_width(struct i2c_client *c, u32 ns,
444 u16 *divider)
445{
446 u64 pulse_clocks;
447
448 if (ns > IR_MAX_DURATION)
449 ns = IR_MAX_DURATION;
450 pulse_clocks = ns_to_pulse_clocks(ns);
451 *divider = pulse_clocks_to_clock_divider(pulse_clocks);
452 cx25840_write4(c, CX25840_IR_TXCLK_REG, *divider);
453 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
454}
455
456static u32 rxclk_rx_s_max_pulse_width(struct i2c_client *c, u32 ns,
457 u16 *divider)
458{
459 u64 pulse_clocks;
460
461 if (ns > IR_MAX_DURATION)
462 ns = IR_MAX_DURATION;
463 pulse_clocks = ns_to_pulse_clocks(ns);
464 *divider = pulse_clocks_to_clock_divider(pulse_clocks);
465 cx25840_write4(c, CX25840_IR_RXCLK_REG, *divider);
466 return (u32) pulse_width_count_to_ns(FIFO_RXTX, *divider);
467}
468
469/*
470 * IR Tx Carrier Duty Cycle register helpers
471 */
472static unsigned int cduty_tx_s_duty_cycle(struct i2c_client *c,
473 unsigned int duty_cycle)
474{
475 u32 n;
476 n = DIV_ROUND_CLOSEST(duty_cycle * 100, 625); /* 16ths of 100% */
477 if (n != 0)
478 n--;
479 if (n > 15)
480 n = 15;
481 cx25840_write4(c, CX25840_IR_CDUTY_REG, n);
482 return DIV_ROUND_CLOSEST((n + 1) * 100, 16);
483}
484
485/*
486 * IR Filter Register helpers
487 */
488static u32 filter_rx_s_min_width(struct i2c_client *c, u32 min_width_ns)
489{
490 u32 count = ns_to_lpf_count(min_width_ns);
491 cx25840_write4(c, CX25840_IR_FILTR_REG, count);
492 return lpf_count_to_ns(count);
493}
494
495/*
496 * IR IRQ Enable Register helpers
497 */
498static inline void irqenable_rx(struct v4l2_subdev *sd, u32 mask)
499{
500 struct cx25840_state *state = to_state(sd);
501
502 if (is_cx23885(state) || is_cx23887(state))
503 mask ^= IRQEN_MSK;
504 mask &= (IRQEN_RTE | IRQEN_ROE | IRQEN_RSE);
505 cx25840_and_or4(state->c, CX25840_IR_IRQEN_REG,
506 ~(IRQEN_RTE | IRQEN_ROE | IRQEN_RSE), mask);
507}
508
509static inline void irqenable_tx(struct v4l2_subdev *sd, u32 mask)
510{
511 struct cx25840_state *state = to_state(sd);
512
513 if (is_cx23885(state) || is_cx23887(state))
514 mask ^= IRQEN_MSK;
515 mask &= IRQEN_TSE;
516 cx25840_and_or4(state->c, CX25840_IR_IRQEN_REG, ~IRQEN_TSE, mask);
517}
518
519/*
520 * V4L2 Subdevice IR Ops
521 */
522int cx25840_ir_irq_handler(struct v4l2_subdev *sd, u32 status, bool *handled)
523{
524 struct cx25840_state *state = to_state(sd);
525 struct cx25840_ir_state *ir_state = to_ir_state(sd);
526 struct i2c_client *c = NULL;
527 unsigned long flags;
528
529 union cx25840_ir_fifo_rec rx_data[FIFO_RX_DEPTH];
530 unsigned int i, j, k;
531 u32 events, v;
532 int tsr, rsr, rto, ror, tse, rse, rte, roe, kror;
533 u32 cntrl, irqen, stats;
534
535 *handled = false;
536 if (ir_state == NULL)
537 return -ENODEV;
538
539 c = ir_state->c;
540
541 /* Only support the IR controller for the CX2388[57] AV Core for now */
542 if (!(is_cx23885(state) || is_cx23887(state)))
543 return -ENODEV;
544
545 cntrl = cx25840_read4(c, CX25840_IR_CNTRL_REG);
546 irqen = cx25840_read4(c, CX25840_IR_IRQEN_REG);
547 if (is_cx23885(state) || is_cx23887(state))
548 irqen ^= IRQEN_MSK;
549 stats = cx25840_read4(c, CX25840_IR_STATS_REG);
550
551 tsr = stats & STATS_TSR; /* Tx FIFO Service Request */
552 rsr = stats & STATS_RSR; /* Rx FIFO Service Request */
553 rto = stats & STATS_RTO; /* Rx Pulse Width Timer Time Out */
554 ror = stats & STATS_ROR; /* Rx FIFO Over Run */
555
556 tse = irqen & IRQEN_TSE; /* Tx FIFO Service Request IRQ Enable */
557 rse = irqen & IRQEN_RSE; /* Rx FIFO Service Reuqest IRQ Enable */
558 rte = irqen & IRQEN_RTE; /* Rx Pulse Width Timer Time Out IRQ Enable */
559 roe = irqen & IRQEN_ROE; /* Rx FIFO Over Run IRQ Enable */
560
561 v4l2_dbg(2, ir_debug, sd, "IR IRQ Status: %s %s %s %s %s %s\n",
562 tsr ? "tsr" : " ", rsr ? "rsr" : " ",
563 rto ? "rto" : " ", ror ? "ror" : " ",
564 stats & STATS_TBY ? "tby" : " ",
565 stats & STATS_RBY ? "rby" : " ");
566
567 v4l2_dbg(2, ir_debug, sd, "IR IRQ Enables: %s %s %s %s\n",
568 tse ? "tse" : " ", rse ? "rse" : " ",
569 rte ? "rte" : " ", roe ? "roe" : " ");
570
571 /*
572 * Transmitter interrupt service
573 */
574 if (tse && tsr) {
575 /*
576 * TODO:
577 * Check the watermark threshold setting
578 * Pull FIFO_TX_DEPTH or FIFO_TX_DEPTH/2 entries from tx_kfifo
579 * Push the data to the hardware FIFO.
580 * If there was nothing more to send in the tx_kfifo, disable
581 * the TSR IRQ and notify the v4l2_device.
582 * If there was something in the tx_kfifo, check the tx_kfifo
583 * level and notify the v4l2_device, if it is low.
584 */
585 /* For now, inhibit TSR interrupt until Tx is implemented */
586 irqenable_tx(sd, 0);
587 events = V4L2_SUBDEV_IR_TX_FIFO_SERVICE_REQ;
588 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_TX_NOTIFY, &events);
589 *handled = true;
590 }
591
592 /*
593 * Receiver interrupt service
594 */
595 kror = 0;
596 if ((rse && rsr) || (rte && rto)) {
597 /*
598 * Receive data on RSR to clear the STATS_RSR.
599 * Receive data on RTO, since we may not have yet hit the RSR
600 * watermark when we receive the RTO.
601 */
602 for (i = 0, v = FIFO_RX_NDV;
603 (v & FIFO_RX_NDV) && !kror; i = 0) {
604 for (j = 0;
605 (v & FIFO_RX_NDV) && j < FIFO_RX_DEPTH; j++) {
606 v = cx25840_read4(c, CX25840_IR_FIFO_REG);
607 rx_data[i].hw_fifo_data = v & ~FIFO_RX_NDV;
608 i++;
609 }
610 if (i == 0)
611 break;
612 j = i * sizeof(union cx25840_ir_fifo_rec);
613 k = kfifo_in_locked(&ir_state->rx_kfifo,
614 (unsigned char *) rx_data, j,
615 &ir_state->rx_kfifo_lock);
616 if (k != j)
617 kror++; /* rx_kfifo over run */
618 }
619 *handled = true;
620 }
621
622 events = 0;
623 v = 0;
624 if (kror) {
625 events |= V4L2_SUBDEV_IR_RX_SW_FIFO_OVERRUN;
626 v4l2_err(sd, "IR receiver software FIFO overrun\n");
627 }
628 if (roe && ror) {
629 /*
630 * The RX FIFO Enable (CNTRL_RFE) must be toggled to clear
631 * the Rx FIFO Over Run status (STATS_ROR)
632 */
633 v |= CNTRL_RFE;
634 events |= V4L2_SUBDEV_IR_RX_HW_FIFO_OVERRUN;
635 v4l2_err(sd, "IR receiver hardware FIFO overrun\n");
636 }
637 if (rte && rto) {
638 /*
639 * The IR Receiver Enable (CNTRL_RXE) must be toggled to clear
640 * the Rx Pulse Width Timer Time Out (STATS_RTO)
641 */
642 v |= CNTRL_RXE;
643 events |= V4L2_SUBDEV_IR_RX_END_OF_RX_DETECTED;
644 }
645 if (v) {
646 /* Clear STATS_ROR & STATS_RTO as needed by reseting hardware */
647 cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl & ~v);
648 cx25840_write4(c, CX25840_IR_CNTRL_REG, cntrl);
649 *handled = true;
650 }
651 spin_lock_irqsave(&ir_state->rx_kfifo_lock, flags);
652 if (kfifo_len(&ir_state->rx_kfifo) >= CX25840_IR_RX_KFIFO_SIZE / 2)
653 events |= V4L2_SUBDEV_IR_RX_FIFO_SERVICE_REQ;
654 spin_unlock_irqrestore(&ir_state->rx_kfifo_lock, flags);
655
656 if (events)
657 v4l2_subdev_notify(sd, V4L2_SUBDEV_IR_RX_NOTIFY, &events);
658 return 0;
659}
660
661/* Receiver */
662static int cx25840_ir_rx_read(struct v4l2_subdev *sd, u8 *buf, size_t count,
663 ssize_t *num)
664{
665 struct cx25840_ir_state *ir_state = to_ir_state(sd);
666 bool invert;
667 u16 divider;
668 unsigned int i, n;
669 union cx25840_ir_fifo_rec *p;
670 unsigned u, v, w;
671
672 if (ir_state == NULL)
673 return -ENODEV;
674
675 invert = (bool) atomic_read(&ir_state->rx_invert);
676 divider = (u16) atomic_read(&ir_state->rxclk_divider);
677
678 n = count / sizeof(union cx25840_ir_fifo_rec)
679 * sizeof(union cx25840_ir_fifo_rec);
680 if (n == 0) {
681 *num = 0;
682 return 0;
683 }
684
685 n = kfifo_out_locked(&ir_state->rx_kfifo, buf, n,
686 &ir_state->rx_kfifo_lock);
687
688 n /= sizeof(union cx25840_ir_fifo_rec);
689 *num = n * sizeof(union cx25840_ir_fifo_rec);
690
691 for (p = (union cx25840_ir_fifo_rec *) buf, i = 0; i < n; p++, i++) {
692
693 if ((p->hw_fifo_data & FIFO_RXTX_RTO) == FIFO_RXTX_RTO) {
694 /* Assume RTO was because of no IR light input */
695 u = 0;
696 w = 1;
697 } else {
698 u = (p->hw_fifo_data & FIFO_RXTX_LVL) ? 1 : 0;
699 if (invert)
700 u = u ? 0 : 1;
701 w = 0;
702 }
703
704 v = (unsigned) pulse_width_count_to_ns(
705 (u16) (p->hw_fifo_data & FIFO_RXTX), divider);
706 if (v > IR_MAX_DURATION)
707 v = IR_MAX_DURATION;
708
709 init_ir_raw_event(&p->ir_core_data);
710 p->ir_core_data.pulse = u;
711 p->ir_core_data.duration = v;
712 p->ir_core_data.timeout = w;
713
714 v4l2_dbg(2, ir_debug, sd, "rx read: %10u ns %s %s\n",
715 v, u ? "mark" : "space", w ? "(timed out)" : "");
716 if (w)
717 v4l2_dbg(2, ir_debug, sd, "rx read: end of rx\n");
718 }
719 return 0;
720}
721
722static int cx25840_ir_rx_g_parameters(struct v4l2_subdev *sd,
723 struct v4l2_subdev_ir_parameters *p)
724{
725 struct cx25840_ir_state *ir_state = to_ir_state(sd);
726
727 if (ir_state == NULL)
728 return -ENODEV;
729
730 mutex_lock(&ir_state->rx_params_lock);
731 memcpy(p, &ir_state->rx_params,
732 sizeof(struct v4l2_subdev_ir_parameters));
733 mutex_unlock(&ir_state->rx_params_lock);
734 return 0;
735}
736
737static int cx25840_ir_rx_shutdown(struct v4l2_subdev *sd)
738{
739 struct cx25840_ir_state *ir_state = to_ir_state(sd);
740 struct i2c_client *c;
741
742 if (ir_state == NULL)
743 return -ENODEV;
744
745 c = ir_state->c;
746 mutex_lock(&ir_state->rx_params_lock);
747
748 /* Disable or slow down all IR Rx circuits and counters */
749 irqenable_rx(sd, 0);
750 control_rx_enable(c, false);
751 control_rx_demodulation_enable(c, false);
752 control_rx_s_edge_detection(c, CNTRL_EDG_NONE);
753 filter_rx_s_min_width(c, 0);
754 cx25840_write4(c, CX25840_IR_RXCLK_REG, RXCLK_RCD);
755
756 ir_state->rx_params.shutdown = true;
757
758 mutex_unlock(&ir_state->rx_params_lock);
759 return 0;
760}
761
762static int cx25840_ir_rx_s_parameters(struct v4l2_subdev *sd,
763 struct v4l2_subdev_ir_parameters *p)
764{
765 struct cx25840_ir_state *ir_state = to_ir_state(sd);
766 struct i2c_client *c;
767 struct v4l2_subdev_ir_parameters *o;
768 u16 rxclk_divider;
769
770 if (ir_state == NULL)
771 return -ENODEV;
772
773 if (p->shutdown)
774 return cx25840_ir_rx_shutdown(sd);
775
776 if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
777 return -ENOSYS;
778
779 c = ir_state->c;
780 o = &ir_state->rx_params;
781
782 mutex_lock(&ir_state->rx_params_lock);
783
784 o->shutdown = p->shutdown;
785
786 p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
787 o->mode = p->mode;
788
789 p->bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec);
790 o->bytes_per_data_element = p->bytes_per_data_element;
791
792 /* Before we tweak the hardware, we have to disable the receiver */
793 irqenable_rx(sd, 0);
794 control_rx_enable(c, false);
795
796 control_rx_demodulation_enable(c, p->modulation);
797 o->modulation = p->modulation;
798
799 if (p->modulation) {
800 p->carrier_freq = rxclk_rx_s_carrier(c, p->carrier_freq,
801 &rxclk_divider);
802
803 o->carrier_freq = p->carrier_freq;
804
805 p->duty_cycle = 50;
806 o->duty_cycle = p->duty_cycle;
807
808 control_rx_s_carrier_window(c, p->carrier_freq,
809 &p->carrier_range_lower,
810 &p->carrier_range_upper);
811 o->carrier_range_lower = p->carrier_range_lower;
812 o->carrier_range_upper = p->carrier_range_upper;
813
814 p->max_pulse_width =
815 (u32) pulse_width_count_to_ns(FIFO_RXTX, rxclk_divider);
816 } else {
817 p->max_pulse_width =
818 rxclk_rx_s_max_pulse_width(c, p->max_pulse_width,
819 &rxclk_divider);
820 }
821 o->max_pulse_width = p->max_pulse_width;
822 atomic_set(&ir_state->rxclk_divider, rxclk_divider);
823
824 p->noise_filter_min_width =
825 filter_rx_s_min_width(c, p->noise_filter_min_width);
826 o->noise_filter_min_width = p->noise_filter_min_width;
827
828 p->resolution = clock_divider_to_resolution(rxclk_divider);
829 o->resolution = p->resolution;
830
831 /* FIXME - make this dependent on resolution for better performance */
832 control_rx_irq_watermark(c, RX_FIFO_HALF_FULL);
833
834 control_rx_s_edge_detection(c, CNTRL_EDG_BOTH);
835
836 o->invert_level = p->invert_level;
837 atomic_set(&ir_state->rx_invert, p->invert_level);
838
839 o->interrupt_enable = p->interrupt_enable;
840 o->enable = p->enable;
841 if (p->enable) {
842 unsigned long flags;
843
844 spin_lock_irqsave(&ir_state->rx_kfifo_lock, flags);
845 kfifo_reset(&ir_state->rx_kfifo);
846 spin_unlock_irqrestore(&ir_state->rx_kfifo_lock, flags);
847 if (p->interrupt_enable)
848 irqenable_rx(sd, IRQEN_RSE | IRQEN_RTE | IRQEN_ROE);
849 control_rx_enable(c, p->enable);
850 }
851
852 mutex_unlock(&ir_state->rx_params_lock);
853 return 0;
854}
855
856/* Transmitter */
857static int cx25840_ir_tx_write(struct v4l2_subdev *sd, u8 *buf, size_t count,
858 ssize_t *num)
859{
860 struct cx25840_ir_state *ir_state = to_ir_state(sd);
861
862 if (ir_state == NULL)
863 return -ENODEV;
864
865#if 0
866 /*
867 * FIXME - the code below is an incomplete and untested sketch of what
868 * may need to be done. The critical part is to get 4 (or 8) pulses
869 * from the tx_kfifo, or converted from ns to the proper units from the
870 * input, and push them off to the hardware Tx FIFO right away, if the
871 * HW TX fifo needs service. The rest can be pushed to the tx_kfifo in
872 * a less critical timeframe. Also watch out for overruning the
873 * tx_kfifo - don't let it happen and let the caller know not all his
874 * pulses were written.
875 */
876 u32 *ns_pulse = (u32 *) buf;
877 unsigned int n;
878 u32 fifo_pulse[FIFO_TX_DEPTH];
879 u32 mark;
880
881 /* Compute how much we can fit in the tx kfifo */
882 n = CX25840_IR_TX_KFIFO_SIZE - kfifo_len(ir_state->tx_kfifo);
883 n = min(n, (unsigned int) count);
884 n /= sizeof(u32);
885
886 /* FIXME - turn on Tx Fifo service interrupt
887 * check hardware fifo level, and other stuff
888 */
889 for (i = 0; i < n; ) {
890 for (j = 0; j < FIFO_TX_DEPTH / 2 && i < n; j++) {
891 mark = ns_pulse[i] & LEVEL_MASK;
892 fifo_pulse[j] = ns_to_pulse_width_count(
893 ns_pulse[i] &
894 ~LEVEL_MASK,
895 ir_state->txclk_divider);
896 if (mark)
897 fifo_pulse[j] &= FIFO_RXTX_LVL;
898 i++;
899 }
900 kfifo_put(ir_state->tx_kfifo, (u8 *) fifo_pulse,
901 j * sizeof(u32));
902 }
903 *num = n * sizeof(u32);
904#else
905 /* For now enable the Tx FIFO Service interrupt & pretend we did work */
906 irqenable_tx(sd, IRQEN_TSE);
907 *num = count;
908#endif
909 return 0;
910}
911
912static int cx25840_ir_tx_g_parameters(struct v4l2_subdev *sd,
913 struct v4l2_subdev_ir_parameters *p)
914{
915 struct cx25840_ir_state *ir_state = to_ir_state(sd);
916
917 if (ir_state == NULL)
918 return -ENODEV;
919
920 mutex_lock(&ir_state->tx_params_lock);
921 memcpy(p, &ir_state->tx_params,
922 sizeof(struct v4l2_subdev_ir_parameters));
923 mutex_unlock(&ir_state->tx_params_lock);
924 return 0;
925}
926
927static int cx25840_ir_tx_shutdown(struct v4l2_subdev *sd)
928{
929 struct cx25840_ir_state *ir_state = to_ir_state(sd);
930 struct i2c_client *c;
931
932 if (ir_state == NULL)
933 return -ENODEV;
934
935 c = ir_state->c;
936 mutex_lock(&ir_state->tx_params_lock);
937
938 /* Disable or slow down all IR Tx circuits and counters */
939 irqenable_tx(sd, 0);
940 control_tx_enable(c, false);
941 control_tx_modulation_enable(c, false);
942 cx25840_write4(c, CX25840_IR_TXCLK_REG, TXCLK_TCD);
943
944 ir_state->tx_params.shutdown = true;
945
946 mutex_unlock(&ir_state->tx_params_lock);
947 return 0;
948}
949
950static int cx25840_ir_tx_s_parameters(struct v4l2_subdev *sd,
951 struct v4l2_subdev_ir_parameters *p)
952{
953 struct cx25840_ir_state *ir_state = to_ir_state(sd);
954 struct i2c_client *c;
955 struct v4l2_subdev_ir_parameters *o;
956 u16 txclk_divider;
957
958 if (ir_state == NULL)
959 return -ENODEV;
960
961 if (p->shutdown)
962 return cx25840_ir_tx_shutdown(sd);
963
964 if (p->mode != V4L2_SUBDEV_IR_MODE_PULSE_WIDTH)
965 return -ENOSYS;
966
967 c = ir_state->c;
968 o = &ir_state->tx_params;
969 mutex_lock(&ir_state->tx_params_lock);
970
971 o->shutdown = p->shutdown;
972
973 p->mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH;
974 o->mode = p->mode;
975
976 p->bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec);
977 o->bytes_per_data_element = p->bytes_per_data_element;
978
979 /* Before we tweak the hardware, we have to disable the transmitter */
980 irqenable_tx(sd, 0);
981 control_tx_enable(c, false);
982
983 control_tx_modulation_enable(c, p->modulation);
984 o->modulation = p->modulation;
985
986 if (p->modulation) {
987 p->carrier_freq = txclk_tx_s_carrier(c, p->carrier_freq,
988 &txclk_divider);
989 o->carrier_freq = p->carrier_freq;
990
991 p->duty_cycle = cduty_tx_s_duty_cycle(c, p->duty_cycle);
992 o->duty_cycle = p->duty_cycle;
993
994 p->max_pulse_width =
995 (u32) pulse_width_count_to_ns(FIFO_RXTX, txclk_divider);
996 } else {
997 p->max_pulse_width =
998 txclk_tx_s_max_pulse_width(c, p->max_pulse_width,
999 &txclk_divider);
1000 }
1001 o->max_pulse_width = p->max_pulse_width;
1002 atomic_set(&ir_state->txclk_divider, txclk_divider);
1003
1004 p->resolution = clock_divider_to_resolution(txclk_divider);
1005 o->resolution = p->resolution;
1006
1007 /* FIXME - make this dependent on resolution for better performance */
1008 control_tx_irq_watermark(c, TX_FIFO_HALF_EMPTY);
1009
1010 control_tx_polarity_invert(c, p->invert_carrier_sense);
1011 o->invert_carrier_sense = p->invert_carrier_sense;
1012
1013 /*
1014 * FIXME: we don't have hardware help for IO pin level inversion
1015 * here like we have on the CX23888.
1016 * Act on this with some mix of logical inversion of data levels,
1017 * carrier polarity, and carrier duty cycle.
1018 */
1019 o->invert_level = p->invert_level;
1020
1021 o->interrupt_enable = p->interrupt_enable;
1022 o->enable = p->enable;
1023 if (p->enable) {
1024 /* reset tx_fifo here */
1025 if (p->interrupt_enable)
1026 irqenable_tx(sd, IRQEN_TSE);
1027 control_tx_enable(c, p->enable);
1028 }
1029
1030 mutex_unlock(&ir_state->tx_params_lock);
1031 return 0;
1032}
1033
1034
1035/*
1036 * V4L2 Subdevice Core Ops support
1037 */
1038int cx25840_ir_log_status(struct v4l2_subdev *sd)
1039{
1040 struct cx25840_state *state = to_state(sd);
1041 struct i2c_client *c = state->c;
1042 char *s;
1043 int i, j;
1044 u32 cntrl, txclk, rxclk, cduty, stats, irqen, filtr;
1045
1046 /* The CX23888 chip doesn't have an IR controller on the A/V core */
1047 if (is_cx23888(state))
1048 return 0;
1049
1050 cntrl = cx25840_read4(c, CX25840_IR_CNTRL_REG);
1051 txclk = cx25840_read4(c, CX25840_IR_TXCLK_REG) & TXCLK_TCD;
1052 rxclk = cx25840_read4(c, CX25840_IR_RXCLK_REG) & RXCLK_RCD;
1053 cduty = cx25840_read4(c, CX25840_IR_CDUTY_REG) & CDUTY_CDC;
1054 stats = cx25840_read4(c, CX25840_IR_STATS_REG);
1055 irqen = cx25840_read4(c, CX25840_IR_IRQEN_REG);
1056 if (is_cx23885(state) || is_cx23887(state))
1057 irqen ^= IRQEN_MSK;
1058 filtr = cx25840_read4(c, CX25840_IR_FILTR_REG) & FILTR_LPF;
1059
1060 v4l2_info(sd, "IR Receiver:\n");
1061 v4l2_info(sd, "\tEnabled: %s\n",
1062 cntrl & CNTRL_RXE ? "yes" : "no");
1063 v4l2_info(sd, "\tDemodulation from a carrier: %s\n",
1064 cntrl & CNTRL_DMD ? "enabled" : "disabled");
1065 v4l2_info(sd, "\tFIFO: %s\n",
1066 cntrl & CNTRL_RFE ? "enabled" : "disabled");
1067 switch (cntrl & CNTRL_EDG) {
1068 case CNTRL_EDG_NONE:
1069 s = "disabled";
1070 break;
1071 case CNTRL_EDG_FALL:
1072 s = "falling edge";
1073 break;
1074 case CNTRL_EDG_RISE:
1075 s = "rising edge";
1076 break;
1077 case CNTRL_EDG_BOTH:
1078 s = "rising & falling edges";
1079 break;
1080 default:
1081 s = "??? edge";
1082 break;
1083 }
1084 v4l2_info(sd, "\tPulse timers' start/stop trigger: %s\n", s);
1085 v4l2_info(sd, "\tFIFO data on pulse timer overflow: %s\n",
1086 cntrl & CNTRL_R ? "not loaded" : "overflow marker");
1087 v4l2_info(sd, "\tFIFO interrupt watermark: %s\n",
1088 cntrl & CNTRL_RIC ? "not empty" : "half full or greater");
1089 v4l2_info(sd, "\tLoopback mode: %s\n",
1090 cntrl & CNTRL_LBM ? "loopback active" : "normal receive");
1091 if (cntrl & CNTRL_DMD) {
1092 v4l2_info(sd, "\tExpected carrier (16 clocks): %u Hz\n",
1093 clock_divider_to_carrier_freq(rxclk));
1094 switch (cntrl & CNTRL_WIN) {
1095 case CNTRL_WIN_3_3:
1096 i = 3;
1097 j = 3;
1098 break;
1099 case CNTRL_WIN_4_3:
1100 i = 4;
1101 j = 3;
1102 break;
1103 case CNTRL_WIN_3_4:
1104 i = 3;
1105 j = 4;
1106 break;
1107 case CNTRL_WIN_4_4:
1108 i = 4;
1109 j = 4;
1110 break;
1111 default:
1112 i = 0;
1113 j = 0;
1114 break;
1115 }
1116 v4l2_info(sd, "\tNext carrier edge window: 16 clocks "
1117 "-%1d/+%1d, %u to %u Hz\n", i, j,
1118 clock_divider_to_freq(rxclk, 16 + j),
1119 clock_divider_to_freq(rxclk, 16 - i));
1120 }
1121 v4l2_info(sd, "\tMax measurable pulse width: %u us, %llu ns\n",
1122 pulse_width_count_to_us(FIFO_RXTX, rxclk),
1123 pulse_width_count_to_ns(FIFO_RXTX, rxclk));
1124 v4l2_info(sd, "\tLow pass filter: %s\n",
1125 filtr ? "enabled" : "disabled");
1126 if (filtr)
1127 v4l2_info(sd, "\tMin acceptable pulse width (LPF): %u us, "
1128 "%u ns\n",
1129 lpf_count_to_us(filtr),
1130 lpf_count_to_ns(filtr));
1131 v4l2_info(sd, "\tPulse width timer timed-out: %s\n",
1132 stats & STATS_RTO ? "yes" : "no");
1133 v4l2_info(sd, "\tPulse width timer time-out intr: %s\n",
1134 irqen & IRQEN_RTE ? "enabled" : "disabled");
1135 v4l2_info(sd, "\tFIFO overrun: %s\n",
1136 stats & STATS_ROR ? "yes" : "no");
1137 v4l2_info(sd, "\tFIFO overrun interrupt: %s\n",
1138 irqen & IRQEN_ROE ? "enabled" : "disabled");
1139 v4l2_info(sd, "\tBusy: %s\n",
1140 stats & STATS_RBY ? "yes" : "no");
1141 v4l2_info(sd, "\tFIFO service requested: %s\n",
1142 stats & STATS_RSR ? "yes" : "no");
1143 v4l2_info(sd, "\tFIFO service request interrupt: %s\n",
1144 irqen & IRQEN_RSE ? "enabled" : "disabled");
1145
1146 v4l2_info(sd, "IR Transmitter:\n");
1147 v4l2_info(sd, "\tEnabled: %s\n",
1148 cntrl & CNTRL_TXE ? "yes" : "no");
1149 v4l2_info(sd, "\tModulation onto a carrier: %s\n",
1150 cntrl & CNTRL_MOD ? "enabled" : "disabled");
1151 v4l2_info(sd, "\tFIFO: %s\n",
1152 cntrl & CNTRL_TFE ? "enabled" : "disabled");
1153 v4l2_info(sd, "\tFIFO interrupt watermark: %s\n",
1154 cntrl & CNTRL_TIC ? "not empty" : "half full or less");
1155 v4l2_info(sd, "\tCarrier polarity: %s\n",
1156 cntrl & CNTRL_CPL ? "space:burst mark:noburst"
1157 : "space:noburst mark:burst");
1158 if (cntrl & CNTRL_MOD) {
1159 v4l2_info(sd, "\tCarrier (16 clocks): %u Hz\n",
1160 clock_divider_to_carrier_freq(txclk));
1161 v4l2_info(sd, "\tCarrier duty cycle: %2u/16\n",
1162 cduty + 1);
1163 }
1164 v4l2_info(sd, "\tMax pulse width: %u us, %llu ns\n",
1165 pulse_width_count_to_us(FIFO_RXTX, txclk),
1166 pulse_width_count_to_ns(FIFO_RXTX, txclk));
1167 v4l2_info(sd, "\tBusy: %s\n",
1168 stats & STATS_TBY ? "yes" : "no");
1169 v4l2_info(sd, "\tFIFO service requested: %s\n",
1170 stats & STATS_TSR ? "yes" : "no");
1171 v4l2_info(sd, "\tFIFO service request interrupt: %s\n",
1172 irqen & IRQEN_TSE ? "enabled" : "disabled");
1173
1174 return 0;
1175}
1176
1177
1178const struct v4l2_subdev_ir_ops cx25840_ir_ops = {
1179 .rx_read = cx25840_ir_rx_read,
1180 .rx_g_parameters = cx25840_ir_rx_g_parameters,
1181 .rx_s_parameters = cx25840_ir_rx_s_parameters,
1182
1183 .tx_write = cx25840_ir_tx_write,
1184 .tx_g_parameters = cx25840_ir_tx_g_parameters,
1185 .tx_s_parameters = cx25840_ir_tx_s_parameters,
1186};
1187
1188
1189static const struct v4l2_subdev_ir_parameters default_rx_params = {
1190 .bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec),
1191 .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1192
1193 .enable = false,
1194 .interrupt_enable = false,
1195 .shutdown = true,
1196
1197 .modulation = true,
1198 .carrier_freq = 36000, /* 36 kHz - RC-5, and RC-6 carrier */
1199
1200 /* RC-5: 666,667 ns = 1/36 kHz * 32 cycles * 1 mark * 0.75 */
1201 /* RC-6: 333,333 ns = 1/36 kHz * 16 cycles * 1 mark * 0.75 */
1202 .noise_filter_min_width = 333333, /* ns */
1203 .carrier_range_lower = 35000,
1204 .carrier_range_upper = 37000,
1205 .invert_level = false,
1206};
1207
1208static const struct v4l2_subdev_ir_parameters default_tx_params = {
1209 .bytes_per_data_element = sizeof(union cx25840_ir_fifo_rec),
1210 .mode = V4L2_SUBDEV_IR_MODE_PULSE_WIDTH,
1211
1212 .enable = false,
1213 .interrupt_enable = false,
1214 .shutdown = true,
1215
1216 .modulation = true,
1217 .carrier_freq = 36000, /* 36 kHz - RC-5 carrier */
1218 .duty_cycle = 25, /* 25 % - RC-5 carrier */
1219 .invert_level = false,
1220 .invert_carrier_sense = false,
1221};
1222
1223int cx25840_ir_probe(struct v4l2_subdev *sd)
1224{
1225 struct cx25840_state *state = to_state(sd);
1226 struct cx25840_ir_state *ir_state;
1227 struct v4l2_subdev_ir_parameters default_params;
1228
1229 /* Only init the IR controller for the CX2388[57] AV Core for now */
1230 if (!(is_cx23885(state) || is_cx23887(state)))
1231 return 0;
1232
1233 ir_state = kzalloc(sizeof(struct cx25840_ir_state), GFP_KERNEL);
1234 if (ir_state == NULL)
1235 return -ENOMEM;
1236
1237 spin_lock_init(&ir_state->rx_kfifo_lock);
1238 if (kfifo_alloc(&ir_state->rx_kfifo,
1239 CX25840_IR_RX_KFIFO_SIZE, GFP_KERNEL)) {
1240 kfree(ir_state);
1241 return -ENOMEM;
1242 }
1243
1244 ir_state->c = state->c;
1245 state->ir_state = ir_state;
1246
1247 /* Ensure no interrupts arrive yet */
1248 if (is_cx23885(state) || is_cx23887(state))
1249 cx25840_write4(ir_state->c, CX25840_IR_IRQEN_REG, IRQEN_MSK);
1250 else
1251 cx25840_write4(ir_state->c, CX25840_IR_IRQEN_REG, 0);
1252
1253 mutex_init(&ir_state->rx_params_lock);
1254 memcpy(&default_params, &default_rx_params,
1255 sizeof(struct v4l2_subdev_ir_parameters));
1256 v4l2_subdev_call(sd, ir, rx_s_parameters, &default_params);
1257
1258 mutex_init(&ir_state->tx_params_lock);
1259 memcpy(&default_params, &default_tx_params,
1260 sizeof(struct v4l2_subdev_ir_parameters));
1261 v4l2_subdev_call(sd, ir, tx_s_parameters, &default_params);
1262
1263 return 0;
1264}
1265
1266int cx25840_ir_remove(struct v4l2_subdev *sd)
1267{
1268 struct cx25840_state *state = to_state(sd);
1269 struct cx25840_ir_state *ir_state = to_ir_state(sd);
1270
1271 if (ir_state == NULL)
1272 return -ENODEV;
1273
1274 cx25840_ir_rx_shutdown(sd);
1275 cx25840_ir_tx_shutdown(sd);
1276
1277 kfifo_free(&ir_state->rx_kfifo);
1278 kfree(ir_state);
1279 state->ir_state = NULL;
1280 return 0;
1281}
diff --git a/drivers/media/i2c/cx25840/cx25840-vbi.c b/drivers/media/i2c/cx25840/cx25840-vbi.c
new file mode 100644
index 000000000000..64a4004f8a97
--- /dev/null
+++ b/drivers/media/i2c/cx25840/cx25840-vbi.c
@@ -0,0 +1,256 @@
1/* cx25840 VBI functions
2 *
3 * This program is free software; you can redistribute it and/or
4 * modify it under the terms of the GNU General Public License
5 * as published by the Free Software Foundation; either version 2
6 * of the License, or (at your option) any later version.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
16 */
17
18
19#include <linux/videodev2.h>
20#include <linux/i2c.h>
21#include <media/v4l2-common.h>
22#include <media/cx25840.h>
23
24#include "cx25840-core.h"
25
26static int odd_parity(u8 c)
27{
28 c ^= (c >> 4);
29 c ^= (c >> 2);
30 c ^= (c >> 1);
31
32 return c & 1;
33}
34
35static int decode_vps(u8 * dst, u8 * p)
36{
37 static const u8 biphase_tbl[] = {
38 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
39 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
40 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
41 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
42 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
43 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
44 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
45 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
46 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
47 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
48 0xc3, 0x4b, 0x43, 0xc3, 0x87, 0x0f, 0x07, 0x87,
49 0x83, 0x0b, 0x03, 0x83, 0xc3, 0x4b, 0x43, 0xc3,
50 0xc1, 0x49, 0x41, 0xc1, 0x85, 0x0d, 0x05, 0x85,
51 0x81, 0x09, 0x01, 0x81, 0xc1, 0x49, 0x41, 0xc1,
52 0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
53 0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
54 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
55 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
56 0xc2, 0x4a, 0x42, 0xc2, 0x86, 0x0e, 0x06, 0x86,
57 0x82, 0x0a, 0x02, 0x82, 0xc2, 0x4a, 0x42, 0xc2,
58 0xc0, 0x48, 0x40, 0xc0, 0x84, 0x0c, 0x04, 0x84,
59 0x80, 0x08, 0x00, 0x80, 0xc0, 0x48, 0x40, 0xc0,
60 0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
61 0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
62 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
63 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
64 0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
65 0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
66 0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
67 0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
68 0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
69 0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
70 };
71
72 u8 c, err = 0;
73 int i;
74
75 for (i = 0; i < 2 * 13; i += 2) {
76 err |= biphase_tbl[p[i]] | biphase_tbl[p[i + 1]];
77 c = (biphase_tbl[p[i + 1]] & 0xf) |
78 ((biphase_tbl[p[i]] & 0xf) << 4);
79 dst[i / 2] = c;
80 }
81
82 return err & 0xf0;
83}
84
85int cx25840_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *svbi)
86{
87 struct i2c_client *client = v4l2_get_subdevdata(sd);
88 struct cx25840_state *state = to_state(sd);
89 static const u16 lcr2vbi[] = {
90 0, V4L2_SLICED_TELETEXT_B, 0, /* 1 */
91 0, V4L2_SLICED_WSS_625, 0, /* 4 */
92 V4L2_SLICED_CAPTION_525, /* 6 */
93 0, 0, V4L2_SLICED_VPS, 0, 0, /* 9 */
94 0, 0, 0, 0
95 };
96 int is_pal = !(state->std & V4L2_STD_525_60);
97 int i;
98
99 memset(svbi, 0, sizeof(*svbi));
100 /* we're done if raw VBI is active */
101 if ((cx25840_read(client, 0x404) & 0x10) == 0)
102 return 0;
103
104 if (is_pal) {
105 for (i = 7; i <= 23; i++) {
106 u8 v = cx25840_read(client, 0x424 + i - 7);
107
108 svbi->service_lines[0][i] = lcr2vbi[v >> 4];
109 svbi->service_lines[1][i] = lcr2vbi[v & 0xf];
110 svbi->service_set |= svbi->service_lines[0][i] |
111 svbi->service_lines[1][i];
112 }
113 } else {
114 for (i = 10; i <= 21; i++) {
115 u8 v = cx25840_read(client, 0x424 + i - 10);
116
117 svbi->service_lines[0][i] = lcr2vbi[v >> 4];
118 svbi->service_lines[1][i] = lcr2vbi[v & 0xf];
119 svbi->service_set |= svbi->service_lines[0][i] |
120 svbi->service_lines[1][i];
121 }
122 }
123 return 0;
124}
125
126int cx25840_s_raw_fmt(struct v4l2_subdev *sd, struct v4l2_vbi_format *fmt)
127{
128 struct i2c_client *client = v4l2_get_subdevdata(sd);
129 struct cx25840_state *state = to_state(sd);
130 int is_pal = !(state->std & V4L2_STD_525_60);
131 int vbi_offset = is_pal ? 1 : 0;
132
133 /* Setup standard */
134 cx25840_std_setup(client);
135
136 /* VBI Offset */
137 cx25840_write(client, 0x47f, vbi_offset);
138 cx25840_write(client, 0x404, 0x2e);
139 return 0;
140}
141
142int cx25840_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *svbi)
143{
144 struct i2c_client *client = v4l2_get_subdevdata(sd);
145 struct cx25840_state *state = to_state(sd);
146 int is_pal = !(state->std & V4L2_STD_525_60);
147 int vbi_offset = is_pal ? 1 : 0;
148 int i, x;
149 u8 lcr[24];
150
151 for (x = 0; x <= 23; x++)
152 lcr[x] = 0x00;
153
154 /* Setup standard */
155 cx25840_std_setup(client);
156
157 /* Sliced VBI */
158 cx25840_write(client, 0x404, 0x32); /* Ancillary data */
159 cx25840_write(client, 0x406, 0x13);
160 cx25840_write(client, 0x47f, vbi_offset);
161
162 if (is_pal) {
163 for (i = 0; i <= 6; i++)
164 svbi->service_lines[0][i] =
165 svbi->service_lines[1][i] = 0;
166 } else {
167 for (i = 0; i <= 9; i++)
168 svbi->service_lines[0][i] =
169 svbi->service_lines[1][i] = 0;
170
171 for (i = 22; i <= 23; i++)
172 svbi->service_lines[0][i] =
173 svbi->service_lines[1][i] = 0;
174 }
175
176 for (i = 7; i <= 23; i++) {
177 for (x = 0; x <= 1; x++) {
178 switch (svbi->service_lines[1-x][i]) {
179 case V4L2_SLICED_TELETEXT_B:
180 lcr[i] |= 1 << (4 * x);
181 break;
182 case V4L2_SLICED_WSS_625:
183 lcr[i] |= 4 << (4 * x);
184 break;
185 case V4L2_SLICED_CAPTION_525:
186 lcr[i] |= 6 << (4 * x);
187 break;
188 case V4L2_SLICED_VPS:
189 lcr[i] |= 9 << (4 * x);
190 break;
191 }
192 }
193 }
194
195 if (is_pal) {
196 for (x = 1, i = 0x424; i <= 0x434; i++, x++)
197 cx25840_write(client, i, lcr[6 + x]);
198 } else {
199 for (x = 1, i = 0x424; i <= 0x430; i++, x++)
200 cx25840_write(client, i, lcr[9 + x]);
201 for (i = 0x431; i <= 0x434; i++)
202 cx25840_write(client, i, 0);
203 }
204
205 cx25840_write(client, 0x43c, 0x16);
206 cx25840_write(client, 0x474, is_pal ? 0x2a : 0x22);
207 return 0;
208}
209
210int cx25840_decode_vbi_line(struct v4l2_subdev *sd, struct v4l2_decode_vbi_line *vbi)
211{
212 struct cx25840_state *state = to_state(sd);
213 u8 *p = vbi->p;
214 int id1, id2, l, err = 0;
215
216 if (p[0] || p[1] != 0xff || p[2] != 0xff ||
217 (p[3] != 0x55 && p[3] != 0x91)) {
218 vbi->line = vbi->type = 0;
219 return 0;
220 }
221
222 p += 4;
223 id1 = p[-1];
224 id2 = p[0] & 0xf;
225 l = p[2] & 0x3f;
226 l += state->vbi_line_offset;
227 p += 4;
228
229 switch (id2) {
230 case 1:
231 id2 = V4L2_SLICED_TELETEXT_B;
232 break;
233 case 4:
234 id2 = V4L2_SLICED_WSS_625;
235 break;
236 case 6:
237 id2 = V4L2_SLICED_CAPTION_525;
238 err = !odd_parity(p[0]) || !odd_parity(p[1]);
239 break;
240 case 9:
241 id2 = V4L2_SLICED_VPS;
242 if (decode_vps(p, p) != 0)
243 err = 1;
244 break;
245 default:
246 id2 = 0;
247 err = 1;
248 break;
249 }
250
251 vbi->type = err ? 0 : id2;
252 vbi->line = err ? 0 : l;
253 vbi->is_second_field = err ? 0 : (id1 == 0x55);
254 vbi->p = p;
255 return 0;
256}
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-06 10:08:28 -0400