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authorMichael Krufky <mkrufky@linuxtv.org>2008-01-01 23:58:26 -0500
committerMauro Carvalho Chehab <mchehab@infradead.org>2008-01-25 16:04:36 -0500
commit59067f7ed491ec95e6e9033e35e1ae726cff3cee (patch)
treef8ced76b07c63328a1552be35171c3ec8cddfb32 /drivers/media/dvb
parent255b5113b4ed683898a24e381155c081f03411f7 (diff)
V4L/DVB (6961): tda18271: move common code to tda18271-common.c
Move some common code to a new file to make this easier to look at. Signed-off-by: Michael Krufky <mkrufky@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'drivers/media/dvb')
-rw-r--r--drivers/media/dvb/frontends/Makefile2
-rw-r--r--drivers/media/dvb/frontends/tda18271-common.c619
-rw-r--r--drivers/media/dvb/frontends/tda18271-fe.c583
-rw-r--r--drivers/media/dvb/frontends/tda18271-priv.h19
-rw-r--r--drivers/media/dvb/frontends/tda18271-tables.c2
-rw-r--r--drivers/media/dvb/frontends/tda18271.h2
6 files changed, 641 insertions, 586 deletions
diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile
index 1c082a6a9499..16bd107ebd32 100644
--- a/drivers/media/dvb/frontends/Makefile
+++ b/drivers/media/dvb/frontends/Makefile
@@ -5,7 +5,7 @@
5EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core/ 5EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core/
6EXTRA_CFLAGS += -Idrivers/media/video/ 6EXTRA_CFLAGS += -Idrivers/media/video/
7 7
8tda18271-objs := tda18271-tables.o tda18271-fe.o 8tda18271-objs := tda18271-tables.o tda18271-common.o tda18271-fe.o
9 9
10obj-$(CONFIG_DVB_PLL) += dvb-pll.o 10obj-$(CONFIG_DVB_PLL) += dvb-pll.o
11obj-$(CONFIG_DVB_STV0299) += stv0299.o 11obj-$(CONFIG_DVB_STV0299) += stv0299.o
diff --git a/drivers/media/dvb/frontends/tda18271-common.c b/drivers/media/dvb/frontends/tda18271-common.c
new file mode 100644
index 000000000000..4adc7390ba00
--- /dev/null
+++ b/drivers/media/dvb/frontends/tda18271-common.c
@@ -0,0 +1,619 @@
1/*
2 tda18271-common.c - driver for the Philips / NXP TDA18271 silicon tuner
3
4 Copyright (C) 2007, 2008 Michael Krufky <mkrufky@linuxtv.org>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19*/
20
21#include "tda18271-priv.h"
22
23static int tda18271_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
24{
25 struct tda18271_priv *priv = fe->tuner_priv;
26 enum tda18271_i2c_gate gate;
27 int ret = 0;
28
29 switch (priv->gate) {
30 case TDA18271_GATE_DIGITAL:
31 case TDA18271_GATE_ANALOG:
32 gate = priv->gate;
33 break;
34 case TDA18271_GATE_AUTO:
35 default:
36 switch (priv->mode) {
37 case TDA18271_DIGITAL:
38 gate = TDA18271_GATE_DIGITAL;
39 break;
40 case TDA18271_ANALOG:
41 default:
42 gate = TDA18271_GATE_ANALOG;
43 break;
44 }
45 }
46
47 switch (gate) {
48 case TDA18271_GATE_ANALOG:
49 if (fe->ops.analog_ops.i2c_gate_ctrl)
50 ret = fe->ops.analog_ops.i2c_gate_ctrl(fe, enable);
51 break;
52 case TDA18271_GATE_DIGITAL:
53 if (fe->ops.i2c_gate_ctrl)
54 ret = fe->ops.i2c_gate_ctrl(fe, enable);
55 break;
56 default:
57 ret = -EINVAL;
58 break;
59 }
60
61 return ret;
62};
63
64/*---------------------------------------------------------------------*/
65
66static void tda18271_dump_regs(struct dvb_frontend *fe, int extended)
67{
68 struct tda18271_priv *priv = fe->tuner_priv;
69 unsigned char *regs = priv->tda18271_regs;
70
71 tda_reg("=== TDA18271 REG DUMP ===\n");
72 tda_reg("ID_BYTE = 0x%02x\n", 0xff & regs[R_ID]);
73 tda_reg("THERMO_BYTE = 0x%02x\n", 0xff & regs[R_TM]);
74 tda_reg("POWER_LEVEL_BYTE = 0x%02x\n", 0xff & regs[R_PL]);
75 tda_reg("EASY_PROG_BYTE_1 = 0x%02x\n", 0xff & regs[R_EP1]);
76 tda_reg("EASY_PROG_BYTE_2 = 0x%02x\n", 0xff & regs[R_EP2]);
77 tda_reg("EASY_PROG_BYTE_3 = 0x%02x\n", 0xff & regs[R_EP3]);
78 tda_reg("EASY_PROG_BYTE_4 = 0x%02x\n", 0xff & regs[R_EP4]);
79 tda_reg("EASY_PROG_BYTE_5 = 0x%02x\n", 0xff & regs[R_EP5]);
80 tda_reg("CAL_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_CPD]);
81 tda_reg("CAL_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_CD1]);
82 tda_reg("CAL_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_CD2]);
83 tda_reg("CAL_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_CD3]);
84 tda_reg("MAIN_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_MPD]);
85 tda_reg("MAIN_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_MD1]);
86 tda_reg("MAIN_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_MD2]);
87 tda_reg("MAIN_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_MD3]);
88
89 /* only dump extended regs if DBG_ADV is set */
90 if (!(tda18271_debug & DBG_ADV))
91 return;
92
93 /* W indicates write-only registers.
94 * Register dump for write-only registers shows last value written. */
95
96 tda_reg("EXTENDED_BYTE_1 = 0x%02x\n", 0xff & regs[R_EB1]);
97 tda_reg("EXTENDED_BYTE_2 = 0x%02x\n", 0xff & regs[R_EB2]);
98 tda_reg("EXTENDED_BYTE_3 = 0x%02x\n", 0xff & regs[R_EB3]);
99 tda_reg("EXTENDED_BYTE_4 = 0x%02x\n", 0xff & regs[R_EB4]);
100 tda_reg("EXTENDED_BYTE_5 = 0x%02x\n", 0xff & regs[R_EB5]);
101 tda_reg("EXTENDED_BYTE_6 = 0x%02x\n", 0xff & regs[R_EB6]);
102 tda_reg("EXTENDED_BYTE_7 = 0x%02x\n", 0xff & regs[R_EB7]);
103 tda_reg("EXTENDED_BYTE_8 = 0x%02x\n", 0xff & regs[R_EB8]);
104 tda_reg("EXTENDED_BYTE_9 W = 0x%02x\n", 0xff & regs[R_EB9]);
105 tda_reg("EXTENDED_BYTE_10 = 0x%02x\n", 0xff & regs[R_EB10]);
106 tda_reg("EXTENDED_BYTE_11 = 0x%02x\n", 0xff & regs[R_EB11]);
107 tda_reg("EXTENDED_BYTE_12 = 0x%02x\n", 0xff & regs[R_EB12]);
108 tda_reg("EXTENDED_BYTE_13 = 0x%02x\n", 0xff & regs[R_EB13]);
109 tda_reg("EXTENDED_BYTE_14 = 0x%02x\n", 0xff & regs[R_EB14]);
110 tda_reg("EXTENDED_BYTE_15 = 0x%02x\n", 0xff & regs[R_EB15]);
111 tda_reg("EXTENDED_BYTE_16 W = 0x%02x\n", 0xff & regs[R_EB16]);
112 tda_reg("EXTENDED_BYTE_17 W = 0x%02x\n", 0xff & regs[R_EB17]);
113 tda_reg("EXTENDED_BYTE_18 = 0x%02x\n", 0xff & regs[R_EB18]);
114 tda_reg("EXTENDED_BYTE_19 W = 0x%02x\n", 0xff & regs[R_EB19]);
115 tda_reg("EXTENDED_BYTE_20 W = 0x%02x\n", 0xff & regs[R_EB20]);
116 tda_reg("EXTENDED_BYTE_21 = 0x%02x\n", 0xff & regs[R_EB21]);
117 tda_reg("EXTENDED_BYTE_22 = 0x%02x\n", 0xff & regs[R_EB22]);
118 tda_reg("EXTENDED_BYTE_23 = 0x%02x\n", 0xff & regs[R_EB23]);
119}
120
121int tda18271_read_regs(struct dvb_frontend *fe)
122{
123 struct tda18271_priv *priv = fe->tuner_priv;
124 unsigned char *regs = priv->tda18271_regs;
125 unsigned char buf = 0x00;
126 int ret;
127 struct i2c_msg msg[] = {
128 { .addr = priv->i2c_addr, .flags = 0,
129 .buf = &buf, .len = 1 },
130 { .addr = priv->i2c_addr, .flags = I2C_M_RD,
131 .buf = regs, .len = 16 }
132 };
133
134 tda18271_i2c_gate_ctrl(fe, 1);
135
136 /* read all registers */
137 ret = i2c_transfer(priv->i2c_adap, msg, 2);
138
139 tda18271_i2c_gate_ctrl(fe, 0);
140
141 if (ret != 2)
142 tda_err("ERROR: i2c_transfer returned: %d\n", ret);
143
144 if (tda18271_debug & DBG_REG)
145 tda18271_dump_regs(fe, 0);
146
147 return (ret == 2 ? 0 : ret);
148}
149
150int tda18271_read_extended(struct dvb_frontend *fe)
151{
152 struct tda18271_priv *priv = fe->tuner_priv;
153 unsigned char *regs = priv->tda18271_regs;
154 unsigned char regdump[TDA18271_NUM_REGS];
155 unsigned char buf = 0x00;
156 int ret, i;
157 struct i2c_msg msg[] = {
158 { .addr = priv->i2c_addr, .flags = 0,
159 .buf = &buf, .len = 1 },
160 { .addr = priv->i2c_addr, .flags = I2C_M_RD,
161 .buf = regdump, .len = TDA18271_NUM_REGS }
162 };
163
164 tda18271_i2c_gate_ctrl(fe, 1);
165
166 /* read all registers */
167 ret = i2c_transfer(priv->i2c_adap, msg, 2);
168
169 tda18271_i2c_gate_ctrl(fe, 0);
170
171 if (ret != 2)
172 tda_err("ERROR: i2c_transfer returned: %d\n", ret);
173
174 for (i = 0; i <= TDA18271_NUM_REGS; i++) {
175 /* don't update write-only registers */
176 if ((i != R_EB9) &&
177 (i != R_EB16) &&
178 (i != R_EB17) &&
179 (i != R_EB19) &&
180 (i != R_EB20))
181 regs[i] = regdump[i];
182 }
183
184 if (tda18271_debug & DBG_REG)
185 tda18271_dump_regs(fe, 1);
186
187 return (ret == 2 ? 0 : ret);
188}
189
190int tda18271_write_regs(struct dvb_frontend *fe, int idx, int len)
191{
192 struct tda18271_priv *priv = fe->tuner_priv;
193 unsigned char *regs = priv->tda18271_regs;
194 unsigned char buf[TDA18271_NUM_REGS + 1];
195 struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0,
196 .buf = buf, .len = len + 1 };
197 int i, ret;
198
199 BUG_ON((len == 0) || (idx + len > sizeof(buf)));
200
201 buf[0] = idx;
202 for (i = 1; i <= len; i++)
203 buf[i] = regs[idx - 1 + i];
204
205 tda18271_i2c_gate_ctrl(fe, 1);
206
207 /* write registers */
208 ret = i2c_transfer(priv->i2c_adap, &msg, 1);
209
210 tda18271_i2c_gate_ctrl(fe, 0);
211
212 if (ret != 1)
213 tda_err("ERROR: i2c_transfer returned: %d\n", ret);
214
215 return (ret == 1 ? 0 : ret);
216}
217
218/*---------------------------------------------------------------------*/
219
220int tda18271_init_regs(struct dvb_frontend *fe)
221{
222 struct tda18271_priv *priv = fe->tuner_priv;
223 unsigned char *regs = priv->tda18271_regs;
224
225 tda_dbg("initializing registers for device @ %d-%04x\n",
226 i2c_adapter_id(priv->i2c_adap), priv->i2c_addr);
227
228 /* initialize registers */
229 switch (priv->id) {
230 case TDA18271HDC1:
231 regs[R_ID] = 0x83;
232 break;
233 case TDA18271HDC2:
234 regs[R_ID] = 0x84;
235 break;
236 };
237
238 regs[R_TM] = 0x08;
239 regs[R_PL] = 0x80;
240 regs[R_EP1] = 0xc6;
241 regs[R_EP2] = 0xdf;
242 regs[R_EP3] = 0x16;
243 regs[R_EP4] = 0x60;
244 regs[R_EP5] = 0x80;
245 regs[R_CPD] = 0x80;
246 regs[R_CD1] = 0x00;
247 regs[R_CD2] = 0x00;
248 regs[R_CD3] = 0x00;
249 regs[R_MPD] = 0x00;
250 regs[R_MD1] = 0x00;
251 regs[R_MD2] = 0x00;
252 regs[R_MD3] = 0x00;
253
254 switch (priv->id) {
255 case TDA18271HDC1:
256 regs[R_EB1] = 0xff;
257 break;
258 case TDA18271HDC2:
259 regs[R_EB1] = 0xfc;
260 break;
261 };
262
263 regs[R_EB2] = 0x01;
264 regs[R_EB3] = 0x84;
265 regs[R_EB4] = 0x41;
266 regs[R_EB5] = 0x01;
267 regs[R_EB6] = 0x84;
268 regs[R_EB7] = 0x40;
269 regs[R_EB8] = 0x07;
270 regs[R_EB9] = 0x00;
271 regs[R_EB10] = 0x00;
272 regs[R_EB11] = 0x96;
273
274 switch (priv->id) {
275 case TDA18271HDC1:
276 regs[R_EB12] = 0x0f;
277 break;
278 case TDA18271HDC2:
279 regs[R_EB12] = 0x33;
280 break;
281 };
282
283 regs[R_EB13] = 0xc1;
284 regs[R_EB14] = 0x00;
285 regs[R_EB15] = 0x8f;
286 regs[R_EB16] = 0x00;
287 regs[R_EB17] = 0x00;
288
289 switch (priv->id) {
290 case TDA18271HDC1:
291 regs[R_EB18] = 0x00;
292 break;
293 case TDA18271HDC2:
294 regs[R_EB18] = 0x8c;
295 break;
296 };
297
298 regs[R_EB19] = 0x00;
299 regs[R_EB20] = 0x20;
300
301 switch (priv->id) {
302 case TDA18271HDC1:
303 regs[R_EB21] = 0x33;
304 break;
305 case TDA18271HDC2:
306 regs[R_EB21] = 0xb3;
307 break;
308 };
309
310 regs[R_EB22] = 0x48;
311 regs[R_EB23] = 0xb0;
312
313 tda18271_write_regs(fe, 0x00, TDA18271_NUM_REGS);
314
315 /* setup agc1 gain */
316 regs[R_EB17] = 0x00;
317 tda18271_write_regs(fe, R_EB17, 1);
318 regs[R_EB17] = 0x03;
319 tda18271_write_regs(fe, R_EB17, 1);
320 regs[R_EB17] = 0x43;
321 tda18271_write_regs(fe, R_EB17, 1);
322 regs[R_EB17] = 0x4c;
323 tda18271_write_regs(fe, R_EB17, 1);
324
325 /* setup agc2 gain */
326 if ((priv->id) == TDA18271HDC1) {
327 regs[R_EB20] = 0xa0;
328 tda18271_write_regs(fe, R_EB20, 1);
329 regs[R_EB20] = 0xa7;
330 tda18271_write_regs(fe, R_EB20, 1);
331 regs[R_EB20] = 0xe7;
332 tda18271_write_regs(fe, R_EB20, 1);
333 regs[R_EB20] = 0xec;
334 tda18271_write_regs(fe, R_EB20, 1);
335 }
336
337 /* image rejection calibration */
338
339 /* low-band */
340 regs[R_EP3] = 0x1f;
341 regs[R_EP4] = 0x66;
342 regs[R_EP5] = 0x81;
343 regs[R_CPD] = 0xcc;
344 regs[R_CD1] = 0x6c;
345 regs[R_CD2] = 0x00;
346 regs[R_CD3] = 0x00;
347 regs[R_MPD] = 0xcd;
348 regs[R_MD1] = 0x77;
349 regs[R_MD2] = 0x08;
350 regs[R_MD3] = 0x00;
351
352 switch (priv->id) {
353 case TDA18271HDC1:
354 tda18271_write_regs(fe, R_EP3, 11);
355 break;
356 case TDA18271HDC2:
357 tda18271_write_regs(fe, R_EP3, 12);
358 break;
359 };
360
361 if ((priv->id) == TDA18271HDC2) {
362 /* main pll cp source on */
363 regs[R_EB4] = 0x61;
364 tda18271_write_regs(fe, R_EB4, 1);
365 msleep(1);
366
367 /* main pll cp source off */
368 regs[R_EB4] = 0x41;
369 tda18271_write_regs(fe, R_EB4, 1);
370 }
371
372 msleep(5); /* pll locking */
373
374 /* launch detector */
375 tda18271_write_regs(fe, R_EP1, 1);
376 msleep(5); /* wanted low measurement */
377
378 regs[R_EP5] = 0x85;
379 regs[R_CPD] = 0xcb;
380 regs[R_CD1] = 0x66;
381 regs[R_CD2] = 0x70;
382
383 tda18271_write_regs(fe, R_EP3, 7);
384 msleep(5); /* pll locking */
385
386 /* launch optimization algorithm */
387 tda18271_write_regs(fe, R_EP2, 1);
388 msleep(30); /* image low optimization completion */
389
390 /* mid-band */
391 regs[R_EP5] = 0x82;
392 regs[R_CPD] = 0xa8;
393 regs[R_CD2] = 0x00;
394 regs[R_MPD] = 0xa9;
395 regs[R_MD1] = 0x73;
396 regs[R_MD2] = 0x1a;
397
398 tda18271_write_regs(fe, R_EP3, 11);
399 msleep(5); /* pll locking */
400
401 tda18271_write_regs(fe, R_EP1, 1);
402 msleep(5); /* wanted mid measurement */
403
404 regs[R_EP5] = 0x86;
405 regs[R_CPD] = 0xa8;
406 regs[R_CD1] = 0x66;
407 regs[R_CD2] = 0xa0;
408
409 tda18271_write_regs(fe, R_EP3, 7);
410 msleep(5); /* pll locking */
411
412 /* launch optimization algorithm */
413 tda18271_write_regs(fe, R_EP2, 1);
414 msleep(30); /* image mid optimization completion */
415
416 /* high-band */
417 regs[R_EP5] = 0x83;
418 regs[R_CPD] = 0x98;
419 regs[R_CD1] = 0x65;
420 regs[R_CD2] = 0x00;
421 regs[R_MPD] = 0x99;
422 regs[R_MD1] = 0x71;
423 regs[R_MD2] = 0xcd;
424
425 tda18271_write_regs(fe, R_EP3, 11);
426 msleep(5); /* pll locking */
427
428 /* launch detector */
429 tda18271_write_regs(fe, R_EP1, 1);
430 msleep(5); /* wanted high measurement */
431
432 regs[R_EP5] = 0x87;
433 regs[R_CD1] = 0x65;
434 regs[R_CD2] = 0x50;
435
436 tda18271_write_regs(fe, R_EP3, 7);
437 msleep(5); /* pll locking */
438
439 /* launch optimization algorithm */
440 tda18271_write_regs(fe, R_EP2, 1);
441 msleep(30); /* image high optimization completion */
442
443 /* return to normal mode */
444 regs[R_EP4] = 0x64;
445 tda18271_write_regs(fe, R_EP4, 1);
446
447 /* synchronize */
448 tda18271_write_regs(fe, R_EP1, 1);
449
450 return 0;
451}
452
453/*---------------------------------------------------------------------*/
454
455int tda18271_calc_main_pll(struct dvb_frontend *fe, u32 freq)
456{
457 /* sets main post divider & divider bytes, but does not write them */
458 struct tda18271_priv *priv = fe->tuner_priv;
459 unsigned char *regs = priv->tda18271_regs;
460 u8 d, pd;
461 u32 div;
462
463 int ret = tda18271_lookup_pll_map(fe, MAIN_PLL, &freq, &pd, &d);
464 if (ret < 0)
465 goto fail;
466
467 regs[R_MPD] = (0x77 & pd);
468
469 switch (priv->mode) {
470 case TDA18271_ANALOG:
471 regs[R_MPD] &= ~0x08;
472 break;
473 case TDA18271_DIGITAL:
474 regs[R_MPD] |= 0x08;
475 break;
476 }
477
478 div = ((d * (freq / 1000)) << 7) / 125;
479
480 regs[R_MD1] = 0x7f & (div >> 16);
481 regs[R_MD2] = 0xff & (div >> 8);
482 regs[R_MD3] = 0xff & div;
483fail:
484 return ret;
485}
486
487int tda18271_calc_cal_pll(struct dvb_frontend *fe, u32 freq)
488{
489 /* sets cal post divider & divider bytes, but does not write them */
490 struct tda18271_priv *priv = fe->tuner_priv;
491 unsigned char *regs = priv->tda18271_regs;
492 u8 d, pd;
493 u32 div;
494
495 int ret = tda18271_lookup_pll_map(fe, CAL_PLL, &freq, &pd, &d);
496 if (ret < 0)
497 goto fail;
498
499 regs[R_CPD] = pd;
500
501 div = ((d * (freq / 1000)) << 7) / 125;
502
503 regs[R_CD1] = 0x7f & (div >> 16);
504 regs[R_CD2] = 0xff & (div >> 8);
505 regs[R_CD3] = 0xff & div;
506fail:
507 return ret;
508}
509
510/*---------------------------------------------------------------------*/
511
512int tda18271_calc_bp_filter(struct dvb_frontend *fe, u32 *freq)
513{
514 /* sets bp filter bits, but does not write them */
515 struct tda18271_priv *priv = fe->tuner_priv;
516 unsigned char *regs = priv->tda18271_regs;
517 u8 val;
518
519 int ret = tda18271_lookup_map(fe, BP_FILTER, freq, &val);
520 if (ret < 0)
521 goto fail;
522
523 regs[R_EP1] &= ~0x07; /* clear bp filter bits */
524 regs[R_EP1] |= (0x07 & val);
525fail:
526 return ret;
527}
528
529int tda18271_calc_km(struct dvb_frontend *fe, u32 *freq)
530{
531 /* sets K & M bits, but does not write them */
532 struct tda18271_priv *priv = fe->tuner_priv;
533 unsigned char *regs = priv->tda18271_regs;
534 u8 val;
535
536 int ret = tda18271_lookup_map(fe, RF_CAL_KMCO, freq, &val);
537 if (ret < 0)
538 goto fail;
539
540 regs[R_EB13] &= ~0x7c; /* clear k & m bits */
541 regs[R_EB13] |= (0x7c & val);
542fail:
543 return ret;
544}
545
546int tda18271_calc_rf_band(struct dvb_frontend *fe, u32 *freq)
547{
548 /* sets rf band bits, but does not write them */
549 struct tda18271_priv *priv = fe->tuner_priv;
550 unsigned char *regs = priv->tda18271_regs;
551 u8 val;
552
553 int ret = tda18271_lookup_map(fe, RF_BAND, freq, &val);
554 if (ret < 0)
555 goto fail;
556
557 regs[R_EP2] &= ~0xe0; /* clear rf band bits */
558 regs[R_EP2] |= (0xe0 & (val << 5));
559fail:
560 return ret;
561}
562
563int tda18271_calc_gain_taper(struct dvb_frontend *fe, u32 *freq)
564{
565 /* sets gain taper bits, but does not write them */
566 struct tda18271_priv *priv = fe->tuner_priv;
567 unsigned char *regs = priv->tda18271_regs;
568 u8 val;
569
570 int ret = tda18271_lookup_map(fe, GAIN_TAPER, freq, &val);
571 if (ret < 0)
572 goto fail;
573
574 regs[R_EP2] &= ~0x1f; /* clear gain taper bits */
575 regs[R_EP2] |= (0x1f & val);
576fail:
577 return ret;
578}
579
580int tda18271_calc_ir_measure(struct dvb_frontend *fe, u32 *freq)
581{
582 /* sets IR Meas bits, but does not write them */
583 struct tda18271_priv *priv = fe->tuner_priv;
584 unsigned char *regs = priv->tda18271_regs;
585 u8 val;
586
587 int ret = tda18271_lookup_map(fe, IR_MEASURE, freq, &val);
588 if (ret < 0)
589 goto fail;
590
591 regs[R_EP5] &= ~0x07;
592 regs[R_EP5] |= (0x07 & val);
593fail:
594 return ret;
595}
596
597int tda18271_calc_rf_cal(struct dvb_frontend *fe, u32 *freq)
598{
599 /* sets rf cal byte (RFC_Cprog), but does not write it */
600 struct tda18271_priv *priv = fe->tuner_priv;
601 unsigned char *regs = priv->tda18271_regs;
602 u8 val;
603
604 int ret = tda18271_lookup_map(fe, RF_CAL, freq, &val);
605 if (ret < 0)
606 goto fail;
607
608 regs[R_EB14] = val;
609fail:
610 return ret;
611}
612
613/*
614 * Overrides for Emacs so that we follow Linus's tabbing style.
615 * ---------------------------------------------------------------------------
616 * Local variables:
617 * c-basic-offset: 8
618 * End:
619 */
diff --git a/drivers/media/dvb/frontends/tda18271-fe.c b/drivers/media/dvb/frontends/tda18271-fe.c
index 4b53baf12efc..537d520de22f 100644
--- a/drivers/media/dvb/frontends/tda18271-fe.c
+++ b/drivers/media/dvb/frontends/tda18271-fe.c
@@ -1,7 +1,7 @@
1/* 1/*
2 tda18271-fe.c - driver for the Philips / NXP TDA18271 silicon tuner 2 tda18271-fe.c - driver for the Philips / NXP TDA18271 silicon tuner
3 3
4 Copyright (C) 2007 Michael Krufky (mkrufky@linuxtv.org) 4 Copyright (C) 2007, 2008 Michael Krufky <mkrufky@linuxtv.org>
5 5
6 This program is free software; you can redistribute it and/or modify 6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by 7 it under the terms of the GNU General Public License as published by
@@ -28,431 +28,6 @@ MODULE_PARM_DESC(debug, "set debug level (info=1, map=2, reg=4 (or-able))");
28 28
29/*---------------------------------------------------------------------*/ 29/*---------------------------------------------------------------------*/
30 30
31static int tda18271_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
32{
33 struct tda18271_priv *priv = fe->tuner_priv;
34 enum tda18271_i2c_gate gate;
35 int ret = 0;
36
37 switch (priv->gate) {
38 case TDA18271_GATE_DIGITAL:
39 case TDA18271_GATE_ANALOG:
40 gate = priv->gate;
41 break;
42 case TDA18271_GATE_AUTO:
43 default:
44 switch (priv->mode) {
45 case TDA18271_DIGITAL:
46 gate = TDA18271_GATE_DIGITAL;
47 break;
48 case TDA18271_ANALOG:
49 default:
50 gate = TDA18271_GATE_ANALOG;
51 break;
52 }
53 }
54
55 switch (gate) {
56 case TDA18271_GATE_ANALOG:
57 if (fe->ops.analog_ops.i2c_gate_ctrl)
58 ret = fe->ops.analog_ops.i2c_gate_ctrl(fe, enable);
59 break;
60 case TDA18271_GATE_DIGITAL:
61 if (fe->ops.i2c_gate_ctrl)
62 ret = fe->ops.i2c_gate_ctrl(fe, enable);
63 break;
64 default:
65 ret = -EINVAL;
66 break;
67 }
68
69 return ret;
70};
71
72/*---------------------------------------------------------------------*/
73
74static void tda18271_dump_regs(struct dvb_frontend *fe, int extended)
75{
76 struct tda18271_priv *priv = fe->tuner_priv;
77 unsigned char *regs = priv->tda18271_regs;
78
79 tda_reg("=== TDA18271 REG DUMP ===\n");
80 tda_reg("ID_BYTE = 0x%02x\n", 0xff & regs[R_ID]);
81 tda_reg("THERMO_BYTE = 0x%02x\n", 0xff & regs[R_TM]);
82 tda_reg("POWER_LEVEL_BYTE = 0x%02x\n", 0xff & regs[R_PL]);
83 tda_reg("EASY_PROG_BYTE_1 = 0x%02x\n", 0xff & regs[R_EP1]);
84 tda_reg("EASY_PROG_BYTE_2 = 0x%02x\n", 0xff & regs[R_EP2]);
85 tda_reg("EASY_PROG_BYTE_3 = 0x%02x\n", 0xff & regs[R_EP3]);
86 tda_reg("EASY_PROG_BYTE_4 = 0x%02x\n", 0xff & regs[R_EP4]);
87 tda_reg("EASY_PROG_BYTE_5 = 0x%02x\n", 0xff & regs[R_EP5]);
88 tda_reg("CAL_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_CPD]);
89 tda_reg("CAL_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_CD1]);
90 tda_reg("CAL_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_CD2]);
91 tda_reg("CAL_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_CD3]);
92 tda_reg("MAIN_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_MPD]);
93 tda_reg("MAIN_DIV_BYTE_1 = 0x%02x\n", 0xff & regs[R_MD1]);
94 tda_reg("MAIN_DIV_BYTE_2 = 0x%02x\n", 0xff & regs[R_MD2]);
95 tda_reg("MAIN_DIV_BYTE_3 = 0x%02x\n", 0xff & regs[R_MD3]);
96
97 /* only dump extended regs if DBG_ADV is set */
98 if (!(tda18271_debug & DBG_ADV))
99 return;
100
101 /* W indicates write-only registers.
102 * Register dump for write-only registers shows last value written. */
103
104 tda_reg("EXTENDED_BYTE_1 = 0x%02x\n", 0xff & regs[R_EB1]);
105 tda_reg("EXTENDED_BYTE_2 = 0x%02x\n", 0xff & regs[R_EB2]);
106 tda_reg("EXTENDED_BYTE_3 = 0x%02x\n", 0xff & regs[R_EB3]);
107 tda_reg("EXTENDED_BYTE_4 = 0x%02x\n", 0xff & regs[R_EB4]);
108 tda_reg("EXTENDED_BYTE_5 = 0x%02x\n", 0xff & regs[R_EB5]);
109 tda_reg("EXTENDED_BYTE_6 = 0x%02x\n", 0xff & regs[R_EB6]);
110 tda_reg("EXTENDED_BYTE_7 = 0x%02x\n", 0xff & regs[R_EB7]);
111 tda_reg("EXTENDED_BYTE_8 = 0x%02x\n", 0xff & regs[R_EB8]);
112 tda_reg("EXTENDED_BYTE_9 W = 0x%02x\n", 0xff & regs[R_EB9]);
113 tda_reg("EXTENDED_BYTE_10 = 0x%02x\n", 0xff & regs[R_EB10]);
114 tda_reg("EXTENDED_BYTE_11 = 0x%02x\n", 0xff & regs[R_EB11]);
115 tda_reg("EXTENDED_BYTE_12 = 0x%02x\n", 0xff & regs[R_EB12]);
116 tda_reg("EXTENDED_BYTE_13 = 0x%02x\n", 0xff & regs[R_EB13]);
117 tda_reg("EXTENDED_BYTE_14 = 0x%02x\n", 0xff & regs[R_EB14]);
118 tda_reg("EXTENDED_BYTE_15 = 0x%02x\n", 0xff & regs[R_EB15]);
119 tda_reg("EXTENDED_BYTE_16 W = 0x%02x\n", 0xff & regs[R_EB16]);
120 tda_reg("EXTENDED_BYTE_17 W = 0x%02x\n", 0xff & regs[R_EB17]);
121 tda_reg("EXTENDED_BYTE_18 = 0x%02x\n", 0xff & regs[R_EB18]);
122 tda_reg("EXTENDED_BYTE_19 W = 0x%02x\n", 0xff & regs[R_EB19]);
123 tda_reg("EXTENDED_BYTE_20 W = 0x%02x\n", 0xff & regs[R_EB20]);
124 tda_reg("EXTENDED_BYTE_21 = 0x%02x\n", 0xff & regs[R_EB21]);
125 tda_reg("EXTENDED_BYTE_22 = 0x%02x\n", 0xff & regs[R_EB22]);
126 tda_reg("EXTENDED_BYTE_23 = 0x%02x\n", 0xff & regs[R_EB23]);
127}
128
129static void tda18271_read_regs(struct dvb_frontend *fe)
130{
131 struct tda18271_priv *priv = fe->tuner_priv;
132 unsigned char *regs = priv->tda18271_regs;
133 unsigned char buf = 0x00;
134 int ret;
135 struct i2c_msg msg[] = {
136 { .addr = priv->i2c_addr, .flags = 0,
137 .buf = &buf, .len = 1 },
138 { .addr = priv->i2c_addr, .flags = I2C_M_RD,
139 .buf = regs, .len = 16 }
140 };
141
142 tda18271_i2c_gate_ctrl(fe, 1);
143
144 /* read all registers */
145 ret = i2c_transfer(priv->i2c_adap, msg, 2);
146
147 tda18271_i2c_gate_ctrl(fe, 0);
148
149 if (ret != 2)
150 tda_err("ERROR: i2c_transfer returned: %d\n", ret);
151
152 if (tda18271_debug & DBG_REG)
153 tda18271_dump_regs(fe, 0);
154}
155
156static void tda18271_read_extended(struct dvb_frontend *fe)
157{
158 struct tda18271_priv *priv = fe->tuner_priv;
159 unsigned char *regs = priv->tda18271_regs;
160 unsigned char regdump[TDA18271_NUM_REGS];
161 unsigned char buf = 0x00;
162 int ret, i;
163 struct i2c_msg msg[] = {
164 { .addr = priv->i2c_addr, .flags = 0,
165 .buf = &buf, .len = 1 },
166 { .addr = priv->i2c_addr, .flags = I2C_M_RD,
167 .buf = regdump, .len = TDA18271_NUM_REGS }
168 };
169
170 tda18271_i2c_gate_ctrl(fe, 1);
171
172 /* read all registers */
173 ret = i2c_transfer(priv->i2c_adap, msg, 2);
174
175 tda18271_i2c_gate_ctrl(fe, 0);
176
177 if (ret != 2)
178 tda_err("ERROR: i2c_transfer returned: %d\n", ret);
179
180 for (i = 0; i <= TDA18271_NUM_REGS; i++) {
181 /* don't update write-only registers */
182 if ((i != R_EB9) &&
183 (i != R_EB16) &&
184 (i != R_EB17) &&
185 (i != R_EB19) &&
186 (i != R_EB20))
187 regs[i] = regdump[i];
188 }
189
190 if (tda18271_debug & DBG_REG)
191 tda18271_dump_regs(fe, 1);
192}
193
194static void tda18271_write_regs(struct dvb_frontend *fe, int idx, int len)
195{
196 struct tda18271_priv *priv = fe->tuner_priv;
197 unsigned char *regs = priv->tda18271_regs;
198 unsigned char buf[TDA18271_NUM_REGS+1];
199 struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0,
200 .buf = buf, .len = len+1 };
201 int i, ret;
202
203 BUG_ON((len == 0) || (idx+len > sizeof(buf)));
204
205 buf[0] = idx;
206 for (i = 1; i <= len; i++) {
207 buf[i] = regs[idx-1+i];
208 }
209
210 tda18271_i2c_gate_ctrl(fe, 1);
211
212 /* write registers */
213 ret = i2c_transfer(priv->i2c_adap, &msg, 1);
214
215 tda18271_i2c_gate_ctrl(fe, 0);
216
217 if (ret != 1)
218 tda_err("ERROR: i2c_transfer returned: %d\n", ret);
219}
220
221/*---------------------------------------------------------------------*/
222
223static int tda18271_init_regs(struct dvb_frontend *fe)
224{
225 struct tda18271_priv *priv = fe->tuner_priv;
226 unsigned char *regs = priv->tda18271_regs;
227
228 tda_dbg("initializing registers for device @ %d-%04x\n",
229 i2c_adapter_id(priv->i2c_adap), priv->i2c_addr);
230
231 /* initialize registers */
232 switch (priv->id) {
233 case TDA18271HDC1:
234 regs[R_ID] = 0x83;
235 break;
236 case TDA18271HDC2:
237 regs[R_ID] = 0x84;
238 break;
239 };
240
241 regs[R_TM] = 0x08;
242 regs[R_PL] = 0x80;
243 regs[R_EP1] = 0xc6;
244 regs[R_EP2] = 0xdf;
245 regs[R_EP3] = 0x16;
246 regs[R_EP4] = 0x60;
247 regs[R_EP5] = 0x80;
248 regs[R_CPD] = 0x80;
249 regs[R_CD1] = 0x00;
250 regs[R_CD2] = 0x00;
251 regs[R_CD3] = 0x00;
252 regs[R_MPD] = 0x00;
253 regs[R_MD1] = 0x00;
254 regs[R_MD2] = 0x00;
255 regs[R_MD3] = 0x00;
256
257 switch (priv->id) {
258 case TDA18271HDC1:
259 regs[R_EB1] = 0xff;
260 break;
261 case TDA18271HDC2:
262 regs[R_EB1] = 0xfc;
263 break;
264 };
265
266 regs[R_EB2] = 0x01;
267 regs[R_EB3] = 0x84;
268 regs[R_EB4] = 0x41;
269 regs[R_EB5] = 0x01;
270 regs[R_EB6] = 0x84;
271 regs[R_EB7] = 0x40;
272 regs[R_EB8] = 0x07;
273 regs[R_EB9] = 0x00;
274 regs[R_EB10] = 0x00;
275 regs[R_EB11] = 0x96;
276
277 switch (priv->id) {
278 case TDA18271HDC1:
279 regs[R_EB12] = 0x0f;
280 break;
281 case TDA18271HDC2:
282 regs[R_EB12] = 0x33;
283 break;
284 };
285
286 regs[R_EB13] = 0xc1;
287 regs[R_EB14] = 0x00;
288 regs[R_EB15] = 0x8f;
289 regs[R_EB16] = 0x00;
290 regs[R_EB17] = 0x00;
291
292 switch (priv->id) {
293 case TDA18271HDC1:
294 regs[R_EB18] = 0x00;
295 break;
296 case TDA18271HDC2:
297 regs[R_EB18] = 0x8c;
298 break;
299 };
300
301 regs[R_EB19] = 0x00;
302 regs[R_EB20] = 0x20;
303
304 switch (priv->id) {
305 case TDA18271HDC1:
306 regs[R_EB21] = 0x33;
307 break;
308 case TDA18271HDC2:
309 regs[R_EB21] = 0xb3;
310 break;
311 };
312
313 regs[R_EB22] = 0x48;
314 regs[R_EB23] = 0xb0;
315
316 tda18271_write_regs(fe, 0x00, TDA18271_NUM_REGS);
317
318 /* setup agc1 gain */
319 regs[R_EB17] = 0x00;
320 tda18271_write_regs(fe, R_EB17, 1);
321 regs[R_EB17] = 0x03;
322 tda18271_write_regs(fe, R_EB17, 1);
323 regs[R_EB17] = 0x43;
324 tda18271_write_regs(fe, R_EB17, 1);
325 regs[R_EB17] = 0x4c;
326 tda18271_write_regs(fe, R_EB17, 1);
327
328 /* setup agc2 gain */
329 if ((priv->id) == TDA18271HDC1) {
330 regs[R_EB20] = 0xa0;
331 tda18271_write_regs(fe, R_EB20, 1);
332 regs[R_EB20] = 0xa7;
333 tda18271_write_regs(fe, R_EB20, 1);
334 regs[R_EB20] = 0xe7;
335 tda18271_write_regs(fe, R_EB20, 1);
336 regs[R_EB20] = 0xec;
337 tda18271_write_regs(fe, R_EB20, 1);
338 }
339
340 /* image rejection calibration */
341
342 /* low-band */
343 regs[R_EP3] = 0x1f;
344 regs[R_EP4] = 0x66;
345 regs[R_EP5] = 0x81;
346 regs[R_CPD] = 0xcc;
347 regs[R_CD1] = 0x6c;
348 regs[R_CD2] = 0x00;
349 regs[R_CD3] = 0x00;
350 regs[R_MPD] = 0xcd;
351 regs[R_MD1] = 0x77;
352 regs[R_MD2] = 0x08;
353 regs[R_MD3] = 0x00;
354
355 switch (priv->id) {
356 case TDA18271HDC1:
357 tda18271_write_regs(fe, R_EP3, 11);
358 break;
359 case TDA18271HDC2:
360 tda18271_write_regs(fe, R_EP3, 12);
361 break;
362 };
363
364 if ((priv->id) == TDA18271HDC2) {
365 /* main pll cp source on */
366 regs[R_EB4] = 0x61;
367 tda18271_write_regs(fe, R_EB4, 1);
368 msleep(1);
369
370 /* main pll cp source off */
371 regs[R_EB4] = 0x41;
372 tda18271_write_regs(fe, R_EB4, 1);
373 }
374
375 msleep(5); /* pll locking */
376
377 /* launch detector */
378 tda18271_write_regs(fe, R_EP1, 1);
379 msleep(5); /* wanted low measurement */
380
381 regs[R_EP5] = 0x85;
382 regs[R_CPD] = 0xcb;
383 regs[R_CD1] = 0x66;
384 regs[R_CD2] = 0x70;
385
386 tda18271_write_regs(fe, R_EP3, 7);
387 msleep(5); /* pll locking */
388
389 /* launch optimization algorithm */
390 tda18271_write_regs(fe, R_EP2, 1);
391 msleep(30); /* image low optimization completion */
392
393 /* mid-band */
394 regs[R_EP5] = 0x82;
395 regs[R_CPD] = 0xa8;
396 regs[R_CD2] = 0x00;
397 regs[R_MPD] = 0xa9;
398 regs[R_MD1] = 0x73;
399 regs[R_MD2] = 0x1a;
400
401 tda18271_write_regs(fe, R_EP3, 11);
402 msleep(5); /* pll locking */
403
404 tda18271_write_regs(fe, R_EP1, 1);
405 msleep(5); /* wanted mid measurement */
406
407 regs[R_EP5] = 0x86;
408 regs[R_CPD] = 0xa8;
409 regs[R_CD1] = 0x66;
410 regs[R_CD2] = 0xa0;
411
412 tda18271_write_regs(fe, R_EP3, 7);
413 msleep(5); /* pll locking */
414
415 /* launch optimization algorithm */
416 tda18271_write_regs(fe, R_EP2, 1);
417 msleep(30); /* image mid optimization completion */
418
419 /* high-band */
420 regs[R_EP5] = 0x83;
421 regs[R_CPD] = 0x98;
422 regs[R_CD1] = 0x65;
423 regs[R_CD2] = 0x00;
424 regs[R_MPD] = 0x99;
425 regs[R_MD1] = 0x71;
426 regs[R_MD2] = 0xcd;
427
428 tda18271_write_regs(fe, R_EP3, 11);
429 msleep(5); /* pll locking */
430
431 /* launch detector */
432 tda18271_write_regs(fe, R_EP1, 1);
433 msleep(5); /* wanted high measurement */
434
435 regs[R_EP5] = 0x87;
436 regs[R_CD1] = 0x65;
437 regs[R_CD2] = 0x50;
438
439 tda18271_write_regs(fe, R_EP3, 7);
440 msleep(5); /* pll locking */
441
442 /* launch optimization algorithm */
443 tda18271_write_regs(fe, R_EP2, 1);
444 msleep(30); /* image high optimization completion */
445
446 /* return to normal mode */
447 regs[R_EP4] = 0x64;
448 tda18271_write_regs(fe, R_EP4, 1);
449
450 /* synchronize */
451 tda18271_write_regs(fe, R_EP1, 1);
452
453 return 0;
454}
455
456static int tda18271_init(struct dvb_frontend *fe) 31static int tda18271_init(struct dvb_frontend *fe)
457{ 32{
458 struct tda18271_priv *priv = fe->tuner_priv; 33 struct tda18271_priv *priv = fe->tuner_priv;
@@ -467,162 +42,6 @@ static int tda18271_init(struct dvb_frontend *fe)
467 return 0; 42 return 0;
468} 43}
469 44
470static int tda18271_calc_main_pll(struct dvb_frontend *fe, u32 freq)
471{
472 /* Sets Main Post-Divider & Divider bytes, but does not write them */
473 struct tda18271_priv *priv = fe->tuner_priv;
474 unsigned char *regs = priv->tda18271_regs;
475 u8 d, pd;
476 u32 div;
477
478 int ret = tda18271_lookup_pll_map(fe, MAIN_PLL, &freq, &pd, &d);
479 if (ret < 0)
480 goto fail;
481
482 regs[R_MPD] = (0x77 & pd);
483
484 switch (priv->mode) {
485 case TDA18271_ANALOG:
486 regs[R_MPD] &= ~0x08;
487 break;
488 case TDA18271_DIGITAL:
489 regs[R_MPD] |= 0x08;
490 break;
491 }
492
493 div = ((d * (freq / 1000)) << 7) / 125;
494
495 regs[R_MD1] = 0x7f & (div >> 16);
496 regs[R_MD2] = 0xff & (div >> 8);
497 regs[R_MD3] = 0xff & div;
498fail:
499 return ret;
500}
501
502static int tda18271_calc_cal_pll(struct dvb_frontend *fe, u32 freq)
503{
504 /* Sets Cal Post-Divider & Divider bytes, but does not write them */
505 struct tda18271_priv *priv = fe->tuner_priv;
506 unsigned char *regs = priv->tda18271_regs;
507 u8 d, pd;
508 u32 div;
509
510 int ret = tda18271_lookup_pll_map(fe, CAL_PLL, &freq, &pd, &d);
511 if (ret < 0)
512 goto fail;
513
514 regs[R_CPD] = pd;
515
516 div = ((d * (freq / 1000)) << 7) / 125;
517
518 regs[R_CD1] = 0x7f & (div >> 16);
519 regs[R_CD2] = 0xff & (div >> 8);
520 regs[R_CD3] = 0xff & div;
521fail:
522 return ret;
523}
524
525static int tda18271_calc_bp_filter(struct dvb_frontend *fe, u32 *freq)
526{
527 /* Sets BP filter bits, but does not write them */
528 struct tda18271_priv *priv = fe->tuner_priv;
529 unsigned char *regs = priv->tda18271_regs;
530 u8 val;
531
532 int ret = tda18271_lookup_map(fe, BP_FILTER, freq, &val);
533 if (ret < 0)
534 goto fail;
535
536 regs[R_EP1] &= ~0x07; /* clear bp filter bits */
537 regs[R_EP1] |= (0x07 & val);
538fail:
539 return ret;
540}
541
542static int tda18271_calc_km(struct dvb_frontend *fe, u32 *freq)
543{
544 /* Sets K & M bits, but does not write them */
545 struct tda18271_priv *priv = fe->tuner_priv;
546 unsigned char *regs = priv->tda18271_regs;
547 u8 val;
548
549 int ret = tda18271_lookup_map(fe, RF_CAL_KMCO, freq, &val);
550 if (ret < 0)
551 goto fail;
552
553 regs[R_EB13] &= ~0x7c; /* clear k & m bits */
554 regs[R_EB13] |= (0x7c & val);
555fail:
556 return ret;
557}
558
559static int tda18271_calc_rf_band(struct dvb_frontend *fe, u32 *freq)
560{
561 /* Sets RF Band bits, but does not write them */
562 struct tda18271_priv *priv = fe->tuner_priv;
563 unsigned char *regs = priv->tda18271_regs;
564 u8 val;
565
566 int ret = tda18271_lookup_map(fe, RF_BAND, freq, &val);
567 if (ret < 0)
568 goto fail;
569
570 regs[R_EP2] &= ~0xe0; /* clear rf band bits */
571 regs[R_EP2] |= (0xe0 & (val << 5));
572fail:
573 return ret;
574}
575
576static int tda18271_calc_gain_taper(struct dvb_frontend *fe, u32 *freq)
577{
578 /* Sets Gain Taper bits, but does not write them */
579 struct tda18271_priv *priv = fe->tuner_priv;
580 unsigned char *regs = priv->tda18271_regs;
581 u8 val;
582
583 int ret = tda18271_lookup_map(fe, GAIN_TAPER, freq, &val);
584 if (ret < 0)
585 goto fail;
586
587 regs[R_EP2] &= ~0x1f; /* clear gain taper bits */
588 regs[R_EP2] |= (0x1f & val);
589fail:
590 return ret;
591}
592
593static int tda18271_calc_ir_measure(struct dvb_frontend *fe, u32 *freq)
594{
595 /* Sets IR Meas bits, but does not write them */
596 struct tda18271_priv *priv = fe->tuner_priv;
597 unsigned char *regs = priv->tda18271_regs;
598 u8 val;
599
600 int ret = tda18271_lookup_map(fe, IR_MEASURE, freq, &val);
601 if (ret < 0)
602 goto fail;
603
604 regs[R_EP5] &= ~0x07;
605 regs[R_EP5] |= (0x07 & val);
606fail:
607 return ret;
608}
609
610static int tda18271_calc_rf_cal(struct dvb_frontend *fe, u32 *freq)
611{
612 /* Sets RF Cal bits, but does not write them */
613 struct tda18271_priv *priv = fe->tuner_priv;
614 unsigned char *regs = priv->tda18271_regs;
615 u8 val;
616
617 int ret = tda18271_lookup_map(fe, RF_CAL, freq, &val);
618 if (ret < 0)
619 goto fail;
620
621 regs[R_EB14] = val;
622fail:
623 return ret;
624}
625
626/* ------------------------------------------------------------------ */ 45/* ------------------------------------------------------------------ */
627 46
628static int tda18271_channel_configuration(struct dvb_frontend *fe, 47static int tda18271_channel_configuration(struct dvb_frontend *fe,
diff --git a/drivers/media/dvb/frontends/tda18271-priv.h b/drivers/media/dvb/frontends/tda18271-priv.h
index 8552c6ae0d1f..deb375ea253e 100644
--- a/drivers/media/dvb/frontends/tda18271-priv.h
+++ b/drivers/media/dvb/frontends/tda18271-priv.h
@@ -1,7 +1,7 @@
1/* 1/*
2 tda18271-priv.h - private header for the NXP TDA18271 silicon tuner 2 tda18271-priv.h - private header for the NXP TDA18271 silicon tuner
3 3
4 Copyright (C) 2007 Michael Krufky (mkrufky@linuxtv.org) 4 Copyright (C) 2007, 2008 Michael Krufky <mkrufky@linuxtv.org>
5 5
6 This program is free software; you can redistribute it and/or modify 6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by 7 it under the terms of the GNU General Public License as published by
@@ -196,6 +196,23 @@ extern int tda18271_lookup_cid_target(struct dvb_frontend *fe,
196 196
197extern int tda18271_assign_map_layout(struct dvb_frontend *fe); 197extern int tda18271_assign_map_layout(struct dvb_frontend *fe);
198 198
199/*---------------------------------------------------------------------*/
200
201extern int tda18271_read_regs(struct dvb_frontend *fe);
202extern int tda18271_read_extended(struct dvb_frontend *fe);
203extern int tda18271_write_regs(struct dvb_frontend *fe, int idx, int len);
204extern int tda18271_init_regs(struct dvb_frontend *fe);
205
206extern int tda18271_calc_main_pll(struct dvb_frontend *fe, u32 freq);
207extern int tda18271_calc_cal_pll(struct dvb_frontend *fe, u32 freq);
208
209extern int tda18271_calc_bp_filter(struct dvb_frontend *fe, u32 *freq);
210extern int tda18271_calc_km(struct dvb_frontend *fe, u32 *freq);
211extern int tda18271_calc_rf_band(struct dvb_frontend *fe, u32 *freq);
212extern int tda18271_calc_gain_taper(struct dvb_frontend *fe, u32 *freq);
213extern int tda18271_calc_ir_measure(struct dvb_frontend *fe, u32 *freq);
214extern int tda18271_calc_rf_cal(struct dvb_frontend *fe, u32 *freq);
215
199#endif /* __TDA18271_PRIV_H__ */ 216#endif /* __TDA18271_PRIV_H__ */
200 217
201/* 218/*
diff --git a/drivers/media/dvb/frontends/tda18271-tables.c b/drivers/media/dvb/frontends/tda18271-tables.c
index 3042e5c873ef..46f1d4ddda34 100644
--- a/drivers/media/dvb/frontends/tda18271-tables.c
+++ b/drivers/media/dvb/frontends/tda18271-tables.c
@@ -1,7 +1,7 @@
1/* 1/*
2 tda18271-tables.c - driver for the Philips / NXP TDA18271 silicon tuner 2 tda18271-tables.c - driver for the Philips / NXP TDA18271 silicon tuner
3 3
4 Copyright (C) 2007 Michael Krufky (mkrufky@linuxtv.org) 4 Copyright (C) 2007, 2008 Michael Krufky <mkrufky@linuxtv.org>
5 5
6 This program is free software; you can redistribute it and/or modify 6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by 7 it under the terms of the GNU General Public License as published by
diff --git a/drivers/media/dvb/frontends/tda18271.h b/drivers/media/dvb/frontends/tda18271.h
index b98a9331c590..f53568103311 100644
--- a/drivers/media/dvb/frontends/tda18271.h
+++ b/drivers/media/dvb/frontends/tda18271.h
@@ -1,7 +1,7 @@
1/* 1/*
2 tda18271.h - header for the Philips / NXP TDA18271 silicon tuner 2 tda18271.h - header for the Philips / NXP TDA18271 silicon tuner
3 3
4 Copyright (C) 2007 Michael Krufky (mkrufky@linuxtv.org) 4 Copyright (C) 2007, 2008 Michael Krufky <mkrufky@linuxtv.org>
5 5
6 This program is free software; you can redistribute it and/or modify 6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by 7 it under the terms of the GNU General Public License as published by
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-03 12:16:46 -0500