[media] drxd: don't re-define u8/u16/u32 types

Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>

2 files changed, 73 insertions, 76 deletions

diff --git a/drivers/media/dvb/frontends/drxd_firm.c b/drivers/media/dvb/frontends/drxd_firm.c
index 9453929d0d1c..2949bde426b2 100644
--- a/drivers/media/dvb/frontends/drxd_firm.c
+++ b/drivers/media/dvb/frontends/drxd_firm.c
@@ -46,7 +46,7 @@
 #define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
 #define HI_TR_FUNC_SIZE 9       /* size of this function in instruction words */
 
-u8_t DRXD_InitAtomicRead[] = {
+u8 DRXD_InitAtomicRead[] = {
         WRBLOCK(HI_TR_FUNC_ADDR, HI_TR_FUNC_SIZE),
         0x26, 0x00,             /* 0         -> ring.rdy;           */
         0x60, 0x04,             /* r0rami.dt -> ring.xba;           */
@@ -67,7 +67,7 @@ u8_t DRXD_InitAtomicRead[] = {
 #define HI_RST_FUNC_SIZE 54     /* size of this function in instruction words */
 
 /* D0 Version */
-u8_t DRXD_HiI2cPatch_1[] = {
+u8 DRXD_HiI2cPatch_1[] = {
         WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
         0xC8, 0x07, 0x01, 0x00, /* MASK      -> reg0.dt;                        */
         0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
@@ -114,13 +114,13 @@ u8_t DRXD_HiI2cPatch_1[] = {
         0xF8, 0x07, 0x2F, 0x00, /* 0x2F      -> jumps.ad;                       */
 
         WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
-             (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
+             (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
         WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
-             (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
+             (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
         WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
-             (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
+             (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
         WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
-             (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
+             (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
 
         /* Force quick and dirty reset */
         WR16(B_HI_CT_REG_COMM_STATE__A, 0),
@@ -128,7 +128,7 @@ u8_t DRXD_HiI2cPatch_1[] = {
 };
 
 /* D0,D1 Version */
-u8_t DRXD_HiI2cPatch_3[] = {
+u8 DRXD_HiI2cPatch_3[] = {
         WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
         0xC8, 0x07, 0x03, 0x00, /* MASK      -> reg0.dt;                        */
         0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
@@ -175,20 +175,20 @@ u8_t DRXD_HiI2cPatch_3[] = {
         0xF8, 0x07, 0x2F, 0x00, /* 0x2F      -> jumps.ad;                       */
 
         WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
-             (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
+             (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
         WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
-             (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
+             (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
         WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
-             (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
+             (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
         WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
-             (u16_t) (HI_RST_FUNC_ADDR & 0x3FF)),
+             (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
 
         /* Force quick and dirty reset */
         WR16(B_HI_CT_REG_COMM_STATE__A, 0),
         END_OF_TABLE
 };
 
-u8_t DRXD_ResetCEFR[] = {
+u8 DRXD_ResetCEFR[] = {
         WRBLOCK(CE_REG_FR_TREAL00__A, 57),
         0x52, 0x00,             /* CE_REG_FR_TREAL00__A */
         0x00, 0x00,             /* CE_REG_FR_TIMAG00__A */
@@ -255,7 +255,7 @@ u8_t DRXD_ResetCEFR[] = {
         END_OF_TABLE
 };
 
-u8_t DRXD_InitFEA2_1[] = {
+u8 DRXD_InitFEA2_1[] = {
         WRBLOCK(FE_AD_REG_PD__A, 3),
         0x00, 0x00,             /* FE_AD_REG_PD__A          */
         0x01, 0x00,             /* FE_AD_REG_INVEXT__A      */
@@ -341,7 +341,7 @@ u8_t DRXD_InitFEA2_1[] = {
 /*   WR16(FE_AG_REG_AG_AGC_SIO__A,  (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/
 /*   WR16(FE_AG_REG_AG_PWD__A        ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
 
-u8_t DRXD_InitFEA2_2[] = {
+u8 DRXD_InitFEA2_2[] = {
         WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010),
         WR16(FE_AG_REG_FGM_WRI__A, 48),
         /* Activate measurement, activate scale */
@@ -359,7 +359,7 @@ u8_t DRXD_InitFEA2_2[] = {
         END_OF_TABLE
 };
 
-u8_t DRXD_InitFEB1_1[] = {
+u8 DRXD_InitFEB1_1[] = {
         WR16(B_FE_AD_REG_PD__A, 0x0000),
         WR16(B_FE_AD_REG_CLKNEG__A, 0x0000),
         WR16(B_FE_AG_REG_BGC_FGC_WRI__A, 0x0000),
@@ -382,7 +382,7 @@ u8_t DRXD_InitFEB1_1[] = {
                                                                              /*   WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005 */
 /*   WR16(B_FE_AG_REG_AG_PWD__A    ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
 
-u8_t DRXD_InitFEB1_2[] = {
+u8 DRXD_InitFEB1_2[] = {
         WR16(B_FE_COMM_EXEC__A, 0x0001),
 
         /* RF-AGC setup */
@@ -404,7 +404,7 @@ u8_t DRXD_InitFEB1_2[] = {
         END_OF_TABLE
 };
 
-u8_t DRXD_InitCPA2[] = {
+u8 DRXD_InitCPA2[] = {
         WRBLOCK(CP_REG_BR_SPL_OFFSET__A, 2),
         0x07, 0x00,             /* CP_REG_BR_SPL_OFFSET__A  */
         0x0A, 0x00,             /* CP_REG_BR_STR_DEL__A     */
@@ -434,13 +434,13 @@ u8_t DRXD_InitCPA2[] = {
         END_OF_TABLE
 };
 
-u8_t DRXD_InitCPB1[] = {
+u8 DRXD_InitCPB1[] = {
         WR16(B_CP_REG_BR_SPL_OFFSET__A, 0x0008),
         WR16(B_CP_COMM_EXEC__A, 0x0001),
         END_OF_TABLE
 };
 
-u8_t DRXD_InitCEA2[] = {
+u8 DRXD_InitCEA2[] = {
         WRBLOCK(CE_REG_AVG_POW__A, 4),
         0x62, 0x00,             /* CE_REG_AVG_POW__A        */
         0x78, 0x00,             /* CE_REG_MAX_POW__A        */
@@ -483,14 +483,14 @@ u8_t DRXD_InitCEA2[] = {
         END_OF_TABLE
 };
 
-u8_t DRXD_InitCEB1[] = {
+u8 DRXD_InitCEB1[] = {
         WR16(B_CE_REG_TI_PHN_ENABLE__A, 0x0001),
         WR16(B_CE_REG_FR_PM_SET__A, 0x000D),
 
         END_OF_TABLE
 };
 
-u8_t DRXD_InitEQA2[] = {
+u8 DRXD_InitEQA2[] = {
         WRBLOCK(EQ_REG_OT_QNT_THRES0__A, 4),
         0x1E, 0x00,             /* EQ_REG_OT_QNT_THRES0__A        */
         0x1F, 0x00,             /* EQ_REG_OT_QNT_THRES1__A        */
@@ -499,18 +499,18 @@ u8_t DRXD_InitEQA2[] = {
 
         WR16(EQ_REG_TD_REQ_SMB_CNT__A, 0x0200),
         WR16(EQ_REG_IS_CLIP_EXP__A, 0x001F),
-        WR16(EQ_REG_SN_OFFSET__A, (u16_t) (-7)),
+        WR16(EQ_REG_SN_OFFSET__A, (u16) (-7)),
         WR16(EQ_REG_RC_SEL_CAR__A, 0x0002),
         WR16(EQ_REG_COMM_EXEC__A, 0x0001),
         END_OF_TABLE
 };
 
-u8_t DRXD_InitEQB1[] = {
+u8 DRXD_InitEQB1[] = {
         WR16(B_EQ_REG_COMM_EXEC__A, 0x0001),
         END_OF_TABLE
 };
 
-u8_t DRXD_ResetECRAM[] = {
+u8 DRXD_ResetECRAM[] = {
         /* Reset packet sync bytes in EC_VD ram */
         WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
         WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
@@ -530,7 +530,7 @@ u8_t DRXD_ResetECRAM[] = {
         END_OF_TABLE
 };
 
-u8_t DRXD_InitECA2[] = {
+u8 DRXD_InitECA2[] = {
         WRBLOCK(EC_SB_REG_CSI_HI__A, 6),
         0x1F, 0x00,             /* EC_SB_REG_CSI_HI__A            */
         0x1E, 0x00,             /* EC_SB_REG_CSI_LO__A            */
@@ -616,7 +616,7 @@ u8_t DRXD_InitECA2[] = {
         END_OF_TABLE
 };
 
-u8_t DRXD_InitECB1[] = {
+u8 DRXD_InitECB1[] = {
         WR16(B_EC_SB_REG_CSI_OFS0__A, 0x0001),
         WR16(B_EC_SB_REG_CSI_OFS1__A, 0x0001),
         WR16(B_EC_SB_REG_CSI_OFS2__A, 0x0001),
@@ -671,7 +671,7 @@ u8_t DRXD_InitECB1[] = {
         END_OF_TABLE
 };
 
-u8_t DRXD_ResetECA2[] = {
+u8 DRXD_ResetECA2[] = {
 
         WR16(EC_OC_REG_COMM_EXEC__A, 0x0000),
         WR16(EC_OD_REG_COMM_EXEC__A, 0x0000),
@@ -742,7 +742,7 @@ u8_t DRXD_ResetECA2[] = {
         END_OF_TABLE
 };
 
-u8_t DRXD_InitSC[] = {
+u8 DRXD_InitSC[] = {
         WR16(SC_COMM_EXEC__A, 0),
         WR16(SC_COMM_STATE__A, 0),
 
@@ -756,7 +756,7 @@ u8_t DRXD_InitSC[] = {
 
 /* Diversity settings */
 
-u8_t DRXD_InitDiversityFront[] = {
+u8 DRXD_InitDiversityFront[] = {
         /* Start demod ********* RF in , diversity out **************************** */
         WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
              B_SC_RA_RAM_CONFIG_FREQSCAN__M),
@@ -793,7 +793,7 @@ u8_t DRXD_InitDiversityFront[] = {
         END_OF_TABLE
 };
 
-u8_t DRXD_InitDiversityEnd[] = {
+u8 DRXD_InitDiversityEnd[] = {
         /* End demod *********** combining RF in and diversity in, MPEG TS out **** */
         /* disable near/far; switch on timing slave mode */
         WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
@@ -835,7 +835,7 @@ u8_t DRXD_InitDiversityEnd[] = {
         END_OF_TABLE
 };
 
-u8_t DRXD_DisableDiversity[] = {
+u8 DRXD_DisableDiversity[] = {
         WR16(B_SC_RA_RAM_LC_ABS_2K__A, B_SC_RA_RAM_LC_ABS_2K__PRE),
         WR16(B_SC_RA_RAM_LC_ABS_8K__A, B_SC_RA_RAM_LC_ABS_8K__PRE),
         WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A,
@@ -876,7 +876,7 @@ u8_t DRXD_DisableDiversity[] = {
         END_OF_TABLE
 };
 
-u8_t DRXD_StartDiversityFront[] = {
+u8 DRXD_StartDiversityFront[] = {
         /* Start demod, RF in and diversity out, no combining */
         WR16(B_FE_CF_REG_IMP_VAL__A, 0x0),
         WR16(B_FE_AD_REG_FDB_IN__A, 0x0),
@@ -890,7 +890,7 @@ u8_t DRXD_StartDiversityFront[] = {
         END_OF_TABLE
 };
 
-u8_t DRXD_StartDiversityEnd[] = {
+u8 DRXD_StartDiversityEnd[] = {
         /* End demod, combining RF in and diversity in, MPEG TS out */
         WR16(B_FE_CF_REG_IMP_VAL__A, 0x0),      /* disable impulse noise cruncher */
         WR16(B_FE_AD_REG_INVEXT__A, 0x0),       /* clock inversion (for sohard board) */
@@ -903,7 +903,7 @@ u8_t DRXD_StartDiversityEnd[] = {
         END_OF_TABLE
 };
 
-u8_t DRXD_DiversityDelay8MHZ[] = {
+u8 DRXD_DiversityDelay8MHZ[] = {
         WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1150 - 50),
         WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1100 - 50),
         WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 1000 - 50),
@@ -915,7 +915,7 @@ u8_t DRXD_DiversityDelay8MHZ[] = {
         END_OF_TABLE
 };
 
-u8_t DRXD_DiversityDelay6MHZ[] =        /* also used ok for 7 MHz */
+u8 DRXD_DiversityDelay6MHZ[] =  /* also used ok for 7 MHz */
 {
         WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1100 - 50),
         WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1000 - 50),
diff --git a/drivers/media/dvb/frontends/drxd_firm.h b/drivers/media/dvb/frontends/drxd_firm.h
index 367930a11426..41597e89941c 100644
--- a/drivers/media/dvb/frontends/drxd_firm.h
+++ b/drivers/media/dvb/frontends/drxd_firm.h
@@ -24,12 +24,9 @@
 #ifndef _DRXD_FIRM_H_
 #define _DRXD_FIRM_H_
 
+#include <linux/types.h>
 #include "drxd_map_firm.h"
 
-typedef unsigned char u8_t;
-typedef unsigned short u16_t;
-typedef unsigned long u32_t;
-
 #define VERSION_MAJOR 1
 #define VERSION_MINOR 4
 #define VERSION_PATCH 23
@@ -77,42 +74,42 @@ typedef unsigned long u32_t;
 #define DIFF_TARGET           (4)
 #define DIFF_MARGIN           (1)
 
-extern u8_t DRXD_InitAtomicRead[];
-extern u8_t DRXD_HiI2cPatch_1[];
-extern u8_t DRXD_HiI2cPatch_3[];
-
-extern u8_t DRXD_InitSC[];
-
-extern u8_t DRXD_ResetCEFR[];
-extern u8_t DRXD_InitFEA2_1[];
-extern u8_t DRXD_InitFEA2_2[];
-extern u8_t DRXD_InitCPA2[];
-extern u8_t DRXD_InitCEA2[];
-extern u8_t DRXD_InitEQA2[];
-extern u8_t DRXD_InitECA2[];
-extern u8_t DRXD_ResetECA2[];
-extern u8_t DRXD_ResetECRAM[];
-
-extern u8_t DRXD_A2_microcode[];
-extern u32_t DRXD_A2_microcode_length;
-
-extern u8_t DRXD_InitFEB1_1[];
-extern u8_t DRXD_InitFEB1_2[];
-extern u8_t DRXD_InitCPB1[];
-extern u8_t DRXD_InitCEB1[];
-extern u8_t DRXD_InitEQB1[];
-extern u8_t DRXD_InitECB1[];
-
-extern u8_t DRXD_InitDiversityFront[];
-extern u8_t DRXD_InitDiversityEnd[];
-extern u8_t DRXD_DisableDiversity[];
-extern u8_t DRXD_StartDiversityFront[];
-extern u8_t DRXD_StartDiversityEnd[];
-
-extern u8_t DRXD_DiversityDelay8MHZ[];
-extern u8_t DRXD_DiversityDelay6MHZ[];
-
-extern u8_t DRXD_B1_microcode[];
-extern u32_t DRXD_B1_microcode_length;
+extern u8 DRXD_InitAtomicRead[];
+extern u8 DRXD_HiI2cPatch_1[];
+extern u8 DRXD_HiI2cPatch_3[];
+
+extern u8 DRXD_InitSC[];
+
+extern u8 DRXD_ResetCEFR[];
+extern u8 DRXD_InitFEA2_1[];
+extern u8 DRXD_InitFEA2_2[];
+extern u8 DRXD_InitCPA2[];
+extern u8 DRXD_InitCEA2[];
+extern u8 DRXD_InitEQA2[];
+extern u8 DRXD_InitECA2[];
+extern u8 DRXD_ResetECA2[];
+extern u8 DRXD_ResetECRAM[];
+
+extern u8 DRXD_A2_microcode[];
+extern u32 DRXD_A2_microcode_length;
+
+extern u8 DRXD_InitFEB1_1[];
+extern u8 DRXD_InitFEB1_2[];
+extern u8 DRXD_InitCPB1[];
+extern u8 DRXD_InitCEB1[];
+extern u8 DRXD_InitEQB1[];
+extern u8 DRXD_InitECB1[];
+
+extern u8 DRXD_InitDiversityFront[];
+extern u8 DRXD_InitDiversityEnd[];
+extern u8 DRXD_DisableDiversity[];
+extern u8 DRXD_StartDiversityFront[];
+extern u8 DRXD_StartDiversityEnd[];
+
+extern u8 DRXD_DiversityDelay8MHZ[];
+extern u8 DRXD_DiversityDelay6MHZ[];
+
+extern u8 DRXD_B1_microcode[];
+extern u32 DRXD_B1_microcode_length;
 
 #endif