diff options
author | Hartmut Hackmann <hartmut.hackmann@t-online.de> | 2006-01-09 12:25:04 -0500 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@brturbo.com.br> | 2006-01-09 12:25:04 -0500 |
commit | 8a8e9c281de5dd63cdcbbafc0252fe0d8c758294 (patch) | |
tree | 138241c0891713736dc45615dbbef981858e2a0f /drivers/media/dvb | |
parent | d3707add6158803b6463292178cd1a041857b91b (diff) |
DVB (2421): Fixed oddities at firmware download
- Fixed oddities at firmware download
- more tolerant vs crystal frequency offset
- lower sampling clock
Signed-off-by: Hartmut Hackmann <hartmut.hackmann@t-online.de>
Signed-off-by: Mauro Carvalho Chehab <mchehab@brturbo.com.br>
Diffstat (limited to 'drivers/media/dvb')
-rw-r--r-- | drivers/media/dvb/frontends/tda1004x.c | 138 |
1 files changed, 90 insertions, 48 deletions
diff --git a/drivers/media/dvb/frontends/tda1004x.c b/drivers/media/dvb/frontends/tda1004x.c index dd02aff467fe..c6ae5bfae5b1 100644 --- a/drivers/media/dvb/frontends/tda1004x.c +++ b/drivers/media/dvb/frontends/tda1004x.c | |||
@@ -271,32 +271,57 @@ static int tda10045h_set_bandwidth(struct tda1004x_state *state, | |||
271 | static int tda10046h_set_bandwidth(struct tda1004x_state *state, | 271 | static int tda10046h_set_bandwidth(struct tda1004x_state *state, |
272 | fe_bandwidth_t bandwidth) | 272 | fe_bandwidth_t bandwidth) |
273 | { | 273 | { |
274 | static u8 bandwidth_6mhz[] = { 0x80, 0x15, 0xfe, 0xab, 0x8e }; | 274 | static u8 bandwidth_6mhz_53M[] = { 0x7b, 0x2e, 0x11, 0xf0, 0xd2 }; |
275 | static u8 bandwidth_7mhz[] = { 0x6e, 0x02, 0x53, 0xc8, 0x25 }; | 275 | static u8 bandwidth_7mhz_53M[] = { 0x6a, 0x02, 0x6a, 0x43, 0x9f }; |
276 | static u8 bandwidth_8mhz[] = { 0x60, 0x12, 0xa8, 0xe4, 0xbd }; | 276 | static u8 bandwidth_8mhz_53M[] = { 0x5c, 0x32, 0xc2, 0x96, 0x6d }; |
277 | 277 | ||
278 | static u8 bandwidth_6mhz_48M[] = { 0x70, 0x02, 0x49, 0x24, 0x92 }; | ||
279 | static u8 bandwidth_7mhz_48M[] = { 0x60, 0x02, 0xaa, 0xaa, 0xab }; | ||
280 | static u8 bandwidth_8mhz_48M[] = { 0x54, 0x03, 0x0c, 0x30, 0xc3 }; | ||
281 | int tda10046_clk53m; | ||
282 | |||
283 | if ((state->config->if_freq == TDA10046_FREQ_045) || | ||
284 | (state->config->if_freq == TDA10046_FREQ_052)) | ||
285 | tda10046_clk53m = 0; | ||
286 | else | ||
287 | tda10046_clk53m = 1; | ||
278 | switch (bandwidth) { | 288 | switch (bandwidth) { |
279 | case BANDWIDTH_6_MHZ: | 289 | case BANDWIDTH_6_MHZ: |
280 | tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz, sizeof(bandwidth_6mhz)); | 290 | if (tda10046_clk53m) |
291 | tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_53M, | ||
292 | sizeof(bandwidth_6mhz_53M)); | ||
293 | else | ||
294 | tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz_48M, | ||
295 | sizeof(bandwidth_6mhz_48M)); | ||
281 | if (state->config->if_freq == TDA10046_FREQ_045) { | 296 | if (state->config->if_freq == TDA10046_FREQ_045) { |
282 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x09); | 297 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a); |
283 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x4f); | 298 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xab); |
284 | } | 299 | } |
285 | break; | 300 | break; |
286 | 301 | ||
287 | case BANDWIDTH_7_MHZ: | 302 | case BANDWIDTH_7_MHZ: |
288 | tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz, sizeof(bandwidth_7mhz)); | 303 | if (tda10046_clk53m) |
304 | tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_53M, | ||
305 | sizeof(bandwidth_7mhz_53M)); | ||
306 | else | ||
307 | tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz_48M, | ||
308 | sizeof(bandwidth_7mhz_48M)); | ||
289 | if (state->config->if_freq == TDA10046_FREQ_045) { | 309 | if (state->config->if_freq == TDA10046_FREQ_045) { |
290 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0a); | 310 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c); |
291 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x79); | 311 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00); |
292 | } | 312 | } |
293 | break; | 313 | break; |
294 | 314 | ||
295 | case BANDWIDTH_8_MHZ: | 315 | case BANDWIDTH_8_MHZ: |
296 | tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz, sizeof(bandwidth_8mhz)); | 316 | if (tda10046_clk53m) |
317 | tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_53M, | ||
318 | sizeof(bandwidth_8mhz_53M)); | ||
319 | else | ||
320 | tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz_48M, | ||
321 | sizeof(bandwidth_8mhz_48M)); | ||
297 | if (state->config->if_freq == TDA10046_FREQ_045) { | 322 | if (state->config->if_freq == TDA10046_FREQ_045) { |
298 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0b); | 323 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d); |
299 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xa3); | 324 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x55); |
300 | } | 325 | } |
301 | break; | 326 | break; |
302 | 327 | ||
@@ -418,9 +443,22 @@ static int tda10045_fwupload(struct dvb_frontend* fe) | |||
418 | static void tda10046_init_plls(struct dvb_frontend* fe) | 443 | static void tda10046_init_plls(struct dvb_frontend* fe) |
419 | { | 444 | { |
420 | struct tda1004x_state* state = fe->demodulator_priv; | 445 | struct tda1004x_state* state = fe->demodulator_priv; |
446 | int tda10046_clk53m; | ||
447 | |||
448 | if ((state->config->if_freq == TDA10046_FREQ_045) || | ||
449 | (state->config->if_freq == TDA10046_FREQ_052)) | ||
450 | tda10046_clk53m = 0; | ||
451 | else | ||
452 | tda10046_clk53m = 1; | ||
421 | 453 | ||
422 | tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0); | 454 | tda1004x_write_byteI(state, TDA10046H_CONFPLL1, 0xf0); |
423 | tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x0a); // PLL M = 10 | 455 | if(tda10046_clk53m) { |
456 | printk(KERN_INFO "tda1004x: setting up plls for 53MHz sampling clock\n"); | ||
457 | tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x08); // PLL M = 8 | ||
458 | } else { | ||
459 | printk(KERN_INFO "tda1004x: setting up plls for 48MHz sampling clock\n"); | ||
460 | tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 0x03); // PLL M = 3 | ||
461 | } | ||
424 | if (state->config->xtal_freq == TDA10046_XTAL_4M ) { | 462 | if (state->config->xtal_freq == TDA10046_XTAL_4M ) { |
425 | dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __FUNCTION__); | 463 | dprintk("%s: setting up PLLs for a 4 MHz Xtal\n", __FUNCTION__); |
426 | tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0 | 464 | tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0 |
@@ -428,26 +466,32 @@ static void tda10046_init_plls(struct dvb_frontend* fe) | |||
428 | dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __FUNCTION__); | 466 | dprintk("%s: setting up PLLs for a 16 MHz Xtal\n", __FUNCTION__); |
429 | tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3 | 467 | tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 3); // PLL P = 0, N = 3 |
430 | } | 468 | } |
431 | tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 99); | 469 | if(tda10046_clk53m) |
470 | tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x67); | ||
471 | else | ||
472 | tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 0x72); | ||
473 | /* Note clock frequency is handled implicitly */ | ||
432 | switch (state->config->if_freq) { | 474 | switch (state->config->if_freq) { |
433 | case TDA10046_FREQ_3617: | ||
434 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4); | ||
435 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x2c); | ||
436 | break; | ||
437 | case TDA10046_FREQ_3613: | ||
438 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4); | ||
439 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x13); | ||
440 | break; | ||
441 | case TDA10046_FREQ_045: | 475 | case TDA10046_FREQ_045: |
442 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0b); | 476 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c); |
443 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xa3); | 477 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x00); |
444 | break; | 478 | break; |
445 | case TDA10046_FREQ_052: | 479 | case TDA10046_FREQ_052: |
446 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0c); | 480 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0x0d); |
447 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x06); | 481 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0xc7); |
482 | break; | ||
483 | case TDA10046_FREQ_3617: | ||
484 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7); | ||
485 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x59); | ||
486 | break; | ||
487 | case TDA10046_FREQ_3613: | ||
488 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd7); | ||
489 | tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x3f); | ||
448 | break; | 490 | break; |
449 | } | 491 | } |
450 | tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz | 492 | tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz |
493 | /* let the PLLs settle */ | ||
494 | msleep(120); | ||
451 | } | 495 | } |
452 | 496 | ||
453 | static int tda10046_fwupload(struct dvb_frontend* fe) | 497 | static int tda10046_fwupload(struct dvb_frontend* fe) |
@@ -462,13 +506,13 @@ static int tda10046_fwupload(struct dvb_frontend* fe) | |||
462 | /* let the clocks recover from sleep */ | 506 | /* let the clocks recover from sleep */ |
463 | msleep(5); | 507 | msleep(5); |
464 | 508 | ||
509 | /* The PLLs need to be reprogrammed after sleep */ | ||
510 | tda10046_init_plls(fe); | ||
511 | |||
465 | /* don't re-upload unless necessary */ | 512 | /* don't re-upload unless necessary */ |
466 | if (tda1004x_check_upload_ok(state) == 0) | 513 | if (tda1004x_check_upload_ok(state) == 0) |
467 | return 0; | 514 | return 0; |
468 | 515 | ||
469 | /* set parameters */ | ||
470 | tda10046_init_plls(fe); | ||
471 | |||
472 | if (state->config->request_firmware != NULL) { | 516 | if (state->config->request_firmware != NULL) { |
473 | /* request the firmware, this will block until someone uploads it */ | 517 | /* request the firmware, this will block until someone uploads it */ |
474 | printk(KERN_INFO "tda1004x: waiting for firmware upload...\n"); | 518 | printk(KERN_INFO "tda1004x: waiting for firmware upload...\n"); |
@@ -484,7 +528,6 @@ static int tda10046_fwupload(struct dvb_frontend* fe) | |||
484 | return ret; | 528 | return ret; |
485 | } else { | 529 | } else { |
486 | /* boot from firmware eeprom */ | 530 | /* boot from firmware eeprom */ |
487 | /* Hac Note: we might need to do some GPIO Magic here */ | ||
488 | printk(KERN_INFO "tda1004x: booting from eeprom\n"); | 531 | printk(KERN_INFO "tda1004x: booting from eeprom\n"); |
489 | tda1004x_write_mask(state, TDA1004X_CONFC4, 4, 4); | 532 | tda1004x_write_mask(state, TDA1004X_CONFC4, 4, 4); |
490 | msleep(300); | 533 | msleep(300); |
@@ -606,10 +649,9 @@ static int tda10046_init(struct dvb_frontend* fe) | |||
606 | 649 | ||
607 | // tda setup | 650 | // tda setup |
608 | tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer | 651 | tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer |
609 | tda1004x_write_byteI(state, TDA1004X_AUTO, 7); // select HP stream | 652 | tda1004x_write_byteI(state, TDA1004X_AUTO, 0x87); // 100 ppm crystal, select HP stream |
610 | tda1004x_write_byteI(state, TDA1004X_CONFC1, 8); // disable pulse killer | 653 | tda1004x_write_byteI(state, TDA1004X_CONFC1, 8); // disable pulse killer |
611 | 654 | ||
612 | tda10046_init_plls(fe); | ||
613 | switch (state->config->agc_config) { | 655 | switch (state->config->agc_config) { |
614 | case TDA10046_AGC_DEFAULT: | 656 | case TDA10046_AGC_DEFAULT: |
615 | tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup | 657 | tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x00); // AGC setup |
@@ -626,25 +668,22 @@ static int tda10046_init(struct dvb_frontend* fe) | |||
626 | case TDA10046_AGC_TDA827X: | 668 | case TDA10046_AGC_TDA827X: |
627 | tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup | 669 | tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0x02); // AGC setup |
628 | tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold | 670 | tda1004x_write_byteI(state, TDA10046H_AGC_THR, 0x70); // AGC Threshold |
629 | tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x0E); // Gain Renormalize | 671 | tda1004x_write_byteI(state, TDA10046H_AGC_RENORM, 0x08); // Gain Renormalize |
630 | tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x60); // set AGC polarities | 672 | tda1004x_write_byteI(state, TDA10046H_CONF_POLARITY, 0x6a); // set AGC polarities |
631 | break; | 673 | break; |
632 | } | 674 | } |
675 | tda1004x_write_byteI(state, TDA1004X_CONFADC2, 0x38); | ||
633 | tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0x61); // Turn both AGC outputs on | 676 | tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE1, 0x61); // Turn both AGC outputs on |
634 | tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // } | 677 | tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0); // } |
635 | tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values | 678 | tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values |
636 | tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // } | 679 | tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0); // } |
637 | tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // } | 680 | tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff); // } |
638 | tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 1); // IF gain 2, TUN gain 1 | 681 | tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 0x12); // IF gain 2, TUN gain 1 |
639 | tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits | 682 | tda1004x_write_byteI(state, TDA10046H_CVBER_CTRL, 0x1a); // 10^6 VBER measurement bits |
640 | tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config | 683 | tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config |
641 | tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config | 684 | tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0xc0); // MPEG2 interface config |
642 | tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7); | 685 | tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7); |
643 | 686 | ||
644 | tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0xe1); // tristate setup | ||
645 | tda1004x_write_byteI(state, TDA10046H_GPIO_OUT_SEL, 0xcc); // GPIO output config | ||
646 | tda1004x_write_byteI(state, TDA10046H_GPIO_SELECT, 8); // GPIO select | ||
647 | |||
648 | state->initialised = 1; | 687 | state->initialised = 1; |
649 | return 0; | 688 | return 0; |
650 | } | 689 | } |
@@ -686,9 +725,9 @@ static int tda1004x_set_fe(struct dvb_frontend* fe, | |||
686 | 725 | ||
687 | // Set standard params.. or put them to auto | 726 | // Set standard params.. or put them to auto |
688 | if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) || | 727 | if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) || |
689 | (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) || | 728 | (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) || |
690 | (fe_params->u.ofdm.constellation == QAM_AUTO) || | 729 | (fe_params->u.ofdm.constellation == QAM_AUTO) || |
691 | (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) { | 730 | (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) { |
692 | tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto | 731 | tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto |
693 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits | 732 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits |
694 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits | 733 | tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits |
@@ -851,6 +890,7 @@ static int tda1004x_set_fe(struct dvb_frontend* fe, | |||
851 | static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params) | 890 | static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params) |
852 | { | 891 | { |
853 | struct tda1004x_state* state = fe->demodulator_priv; | 892 | struct tda1004x_state* state = fe->demodulator_priv; |
893 | |||
854 | dprintk("%s\n", __FUNCTION__); | 894 | dprintk("%s\n", __FUNCTION__); |
855 | 895 | ||
856 | // inversion status | 896 | // inversion status |
@@ -875,16 +915,18 @@ static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_paramete | |||
875 | break; | 915 | break; |
876 | } | 916 | } |
877 | break; | 917 | break; |
878 | |||
879 | case TDA1004X_DEMOD_TDA10046: | 918 | case TDA1004X_DEMOD_TDA10046: |
880 | switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) { | 919 | switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) { |
881 | case 0x60: | 920 | case 0x5c: |
921 | case 0x54: | ||
882 | fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ; | 922 | fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ; |
883 | break; | 923 | break; |
884 | case 0x6e: | 924 | case 0x6a: |
925 | case 0x60: | ||
885 | fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ; | 926 | fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ; |
886 | break; | 927 | break; |
887 | case 0x80: | 928 | case 0x7b: |
929 | case 0x70: | ||
888 | fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ; | 930 | fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ; |
889 | break; | 931 | break; |
890 | } | 932 | } |