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authorOliver Endriss <o.endriss@gmx.de>2008-04-20 19:41:42 -0400
committerMauro Carvalho Chehab <mchehab@infradead.org>2008-04-24 13:09:45 -0400
commit94ad6de7051a9eb6beda096144c5b409538eab86 (patch)
tree1fc49f4ba23895e4497a138bcced834d74b73b1d /drivers/media/dvb
parenta095be4b030cd7eb5ac2a7dcb86e803db149a8db (diff)
V4L/DVB (7660): bsbe1: Use settings recommended by the manufacturer
Reworked the BSBE1 tuner support in bsbe1.h to follow the ALPS-recommended parameters more closely. Tested with BSBE1-based Activy cards and TT DVB-S rev 2.3. Signed-off-by: Oliver Endriss <o.endriss@gmx.de> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
Diffstat (limited to 'drivers/media/dvb')
-rw-r--r--drivers/media/dvb/frontends/bsbe1.h58
1 files changed, 19 insertions, 39 deletions
diff --git a/drivers/media/dvb/frontends/bsbe1.h b/drivers/media/dvb/frontends/bsbe1.h
index d8f65738e5d2..5e431ebd089b 100644
--- a/drivers/media/dvb/frontends/bsbe1.h
+++ b/drivers/media/dvb/frontends/bsbe1.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * bsbe1.h - ALPS BSBE1 tuner support (moved from av7110.c) 2 * bsbe1.h - ALPS BSBE1 tuner support
3 * 3 *
4 * This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License 5 * modify it under the terms of the GNU General Public License
@@ -26,44 +26,24 @@
26#define BSBE1_H 26#define BSBE1_H
27 27
28static u8 alps_bsbe1_inittab[] = { 28static u8 alps_bsbe1_inittab[] = {
29 0x01, 0x15, 29 0x01, 0x15, /* XTAL = 4MHz, VCO = 352 MHz */
30 0x02, 0x30, 30 0x02, 0x30, /* MCLK = 88 MHz */
31 0x03, 0x00, 31 0x03, 0x00, /* ACR output 0 */
32 0x04, 0x7d, /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */ 32 0x04, 0x7d, /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */
33 0x05, 0x35, /* I2CT = 0, SCLT = 1, SDAT = 1 */ 33 0x05, 0x05, /* I2CT = 0, SCLT = 1, SDAT = 1 */
34 0x06, 0x40, /* DAC not used, set to high impendance mode */ 34 0x06, 0x00, /* DAC output 0 */
35 0x07, 0x00, /* DAC LSB */
36 0x08, 0x40, /* DiSEqC off, LNB power on OP2/LOCK pin on */ 35 0x08, 0x40, /* DiSEqC off, LNB power on OP2/LOCK pin on */
37 0x09, 0x00, /* FIFO */ 36 0x09, 0x00, /* FIFO */
38 0x0c, 0x51, /* OP1 ctl = Normal, OP1 val = 1 (LNB Power ON) */ 37 0x0c, 0x51, /* OP1/OP0 normal, val = 1 (LNB power on) */
39 0x0d, 0x82, /* DC offset compensation = ON, beta_agc1 = 2 */ 38 0x0d, 0x82, /* DC offset compensation = on, beta_agc1 = 2 */
40 0x0e, 0x23, /* alpha_tmg = 2, beta_tmg = 3 */ 39 0x0f, 0x92, /* AGC1R */
41 0x10, 0x3f, // AGC2 0x3d 40 0x10, 0x34, /* AGC2O */
42 0x11, 0x84, 41 0x11, 0x84, /* TLSR */
43 0x12, 0xb9, 42 0x12, 0xb9, /* CFD */
44 0x15, 0xc9, // lock detector threshold 43 0x15, 0xc9, /* lock detector threshold */
45 0x16, 0x00, 44 0x28, 0x00, /* out imp: normal, type: parallel, FEC mode: QPSK */
46 0x17, 0x00, 45 0x33, 0xfc, /* RS control */
47 0x18, 0x00, 46 0x34, 0x93, /* count viterbi bit errors per 2E18 bytes */
48 0x19, 0x00,
49 0x1a, 0x00,
50 0x1f, 0x50,
51 0x20, 0x00,
52 0x21, 0x00,
53 0x22, 0x00,
54 0x23, 0x00,
55 0x28, 0x00, // out imp: normal out type: parallel FEC mode:0
56 0x29, 0x1e, // 1/2 threshold
57 0x2a, 0x14, // 2/3 threshold
58 0x2b, 0x0f, // 3/4 threshold
59 0x2c, 0x09, // 5/6 threshold
60 0x2d, 0x05, // 7/8 threshold
61 0x2e, 0x01,
62 0x31, 0x1f, // test all FECs
63 0x32, 0x19, // viterbi and synchro search
64 0x33, 0xfc, // rs control
65 0x34, 0x93, // error control
66 0x0f, 0x92,
67 0xff, 0xff 47 0xff, 0xff
68}; 48};
69 49
@@ -100,11 +80,11 @@ static int alps_bsbe1_tuner_set_params(struct dvb_frontend* fe, struct dvb_front
100 if ((params->frequency < 950000) || (params->frequency > 2150000)) 80 if ((params->frequency < 950000) || (params->frequency > 2150000))
101 return -EINVAL; 81 return -EINVAL;
102 82
103 div = (params->frequency + (125 - 1)) / 125; // round correctly 83 div = params->frequency / 1000;
104 data[0] = (div >> 8) & 0x7f; 84 data[0] = (div >> 8) & 0x7f;
105 data[1] = div & 0xff; 85 data[1] = div & 0xff;
106 data[2] = 0x80 | ((div & 0x18000) >> 10) | 4; 86 data[2] = 0x80 | ((div & 0x18000) >> 10) | 0x1;
107 data[3] = (params->frequency > 1530000) ? 0xE0 : 0xE4; 87 data[3] = 0xe0;
108 88
109 if (fe->ops.i2c_gate_ctrl) 89 if (fe->ops.i2c_gate_ctrl)
110 fe->ops.i2c_gate_ctrl(fe, 1); 90 fe->ops.i2c_gate_ctrl(fe, 1);