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authorOlivier Grenie <olivier.grenie@dibcom.fr>2011-01-04 02:27:11 -0500
committerMauro Carvalho Chehab <mchehab@redhat.com>2011-03-21 19:31:41 -0400
commit28fafca78797be701208c0880ec1c79ffa267f9d (patch)
tree3b2d679e6f58e680d6a4d400b5473db74e80da66 /drivers/media/dvb
parentb994d19268756b640ccc76f0b0d47ee13c0f8af9 (diff)
[media] DiB0090: misc improvements
This patch adds several performance improvements and prepares the usage of firmware-based devices. Signed-off-by: Olivier Grenie <olivier.grenie@dibcom.fr> Signed-off-by: Patrick Boettcher <patrick.boettcher@dibcom.fr> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/dvb')
-rw-r--r--drivers/media/dvb/frontends/dib0090.c1650
-rw-r--r--drivers/media/dvb/frontends/dib0090.h31
2 files changed, 1346 insertions, 335 deletions
diff --git a/drivers/media/dvb/frontends/dib0090.c b/drivers/media/dvb/frontends/dib0090.c
index 65240b7801e8..0e87a0bdf7ab 100644
--- a/drivers/media/dvb/frontends/dib0090.c
+++ b/drivers/media/dvb/frontends/dib0090.c
@@ -45,6 +45,7 @@ MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
45 } \ 45 } \
46} while (0) 46} while (0)
47 47
48#define CONFIG_SYS_DVBT
48#define CONFIG_SYS_ISDBT 49#define CONFIG_SYS_ISDBT
49#define CONFIG_BAND_CBAND 50#define CONFIG_BAND_CBAND
50#define CONFIG_BAND_VHF 51#define CONFIG_BAND_VHF
@@ -76,6 +77,34 @@ MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
76#define EN_SBD 0x44E9 77#define EN_SBD 0x44E9
77#define EN_CAB 0x88E9 78#define EN_CAB 0x88E9
78 79
80/* Calibration defines */
81#define DC_CAL 0x1
82#define WBD_CAL 0x2
83#define TEMP_CAL 0x4
84#define CAPTRIM_CAL 0x8
85
86#define KROSUS_PLL_LOCKED 0x800
87#define KROSUS 0x2
88
89/* Use those defines to identify SOC version */
90#define SOC 0x02
91#define SOC_7090_P1G_11R1 0x82
92#define SOC_7090_P1G_21R1 0x8a
93#define SOC_8090_P1G_11R1 0x86
94#define SOC_8090_P1G_21R1 0x8e
95
96/* else use thos ones to check */
97#define P1A_B 0x0
98#define P1C 0x1
99#define P1D_E_F 0x3
100#define P1G 0x7
101#define P1G_21R2 0xf
102
103#define MP001 0x1 /* Single 9090/8096 */
104#define MP005 0x4 /* Single Sband */
105#define MP008 0x6 /* Dual diversity VHF-UHF-LBAND */
106#define MP009 0x7 /* Dual diversity 29098 CBAND-UHF-LBAND-SBAND */
107
79#define pgm_read_word(w) (*w) 108#define pgm_read_word(w) (*w)
80 109
81struct dc_calibration; 110struct dc_calibration;
@@ -84,7 +113,7 @@ struct dib0090_tuning {
84 u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */ 113 u32 max_freq; /* for every frequency less than or equal to that field: this information is correct */
85 u8 switch_trim; 114 u8 switch_trim;
86 u8 lna_tune; 115 u8 lna_tune;
87 u8 lna_bias; 116 u16 lna_bias;
88 u16 v2i; 117 u16 v2i;
89 u16 mix; 118 u16 mix;
90 u16 load; 119 u16 load;
@@ -99,13 +128,19 @@ struct dib0090_pll {
99 u8 topresc; 128 u8 topresc;
100}; 129};
101 130
131struct dib0090_identity {
132 u8 version;
133 u8 product;
134 u8 p1g;
135 u8 in_soc;
136};
137
102struct dib0090_state { 138struct dib0090_state {
103 struct i2c_adapter *i2c; 139 struct i2c_adapter *i2c;
104 struct dvb_frontend *fe; 140 struct dvb_frontend *fe;
105 const struct dib0090_config *config; 141 const struct dib0090_config *config;
106 142
107 u8 current_band; 143 u8 current_band;
108 u16 revision;
109 enum frontend_tune_state tune_state; 144 enum frontend_tune_state tune_state;
110 u32 current_rf; 145 u32 current_rf;
111 146
@@ -143,15 +178,34 @@ struct dib0090_state {
143 u8 tuner_is_tuned; 178 u8 tuner_is_tuned;
144 u8 agc_freeze; 179 u8 agc_freeze;
145 180
146 u8 reset; 181 struct dib0090_identity identity;
182
183 u32 rf_request;
184 u8 current_standard;
185
186 u8 calibrate;
187 u32 rest;
188 u16 bias;
189 s16 temperature;
190
191 u8 wbd_calibration_gain;
192 const struct dib0090_wbd_slope *current_wbd_table;
193 u16 wbdmux;
194};
195
196struct dib0090_fw_state {
197 struct i2c_adapter *i2c;
198 struct dvb_frontend *fe;
199 struct dib0090_identity identity;
200 const struct dib0090_config *config;
147}; 201};
148 202
149static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg) 203static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg)
150{ 204{
151 u8 b[2]; 205 u8 b[2];
152 struct i2c_msg msg[2] = { 206 struct i2c_msg msg[2] = {
153 {.addr = state->config->i2c_address, .flags = 0, .buf = &reg, .len = 1}, 207 {.addr = state->config->i2c_address,.flags = 0,.buf = &reg,.len = 1},
154 {.addr = state->config->i2c_address, .flags = I2C_M_RD, .buf = b, .len = 2}, 208 {.addr = state->config->i2c_address,.flags = I2C_M_RD,.buf = b,.len = 2},
155 }; 209 };
156 if (i2c_transfer(state->i2c, msg, 2) != 2) { 210 if (i2c_transfer(state->i2c, msg, 2) != 2) {
157 printk(KERN_WARNING "DiB0090 I2C read failed\n"); 211 printk(KERN_WARNING "DiB0090 I2C read failed\n");
@@ -163,7 +217,29 @@ static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg)
163static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val) 217static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val)
164{ 218{
165 u8 b[3] = { reg & 0xff, val >> 8, val & 0xff }; 219 u8 b[3] = { reg & 0xff, val >> 8, val & 0xff };
166 struct i2c_msg msg = {.addr = state->config->i2c_address, .flags = 0, .buf = b, .len = 3 }; 220 struct i2c_msg msg = {.addr = state->config->i2c_address,.flags = 0,.buf = b,.len = 3 };
221 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
222 printk(KERN_WARNING "DiB0090 I2C write failed\n");
223 return -EREMOTEIO;
224 }
225 return 0;
226}
227
228static u16 dib0090_fw_read_reg(struct dib0090_fw_state *state, u8 reg)
229{
230 u8 b[2];
231 struct i2c_msg msg = {.addr = reg,.flags = I2C_M_RD,.buf = b,.len = 2 };
232 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
233 printk(KERN_WARNING "DiB0090 I2C read failed\n");
234 return 0;
235 }
236 return (b[0] << 8) | b[1];
237}
238
239static int dib0090_fw_write_reg(struct dib0090_fw_state *state, u8 reg, u16 val)
240{
241 u8 b[2] = { val >> 8, val & 0xff };
242 struct i2c_msg msg = {.addr = reg,.flags = 0,.buf = b,.len = 2 };
167 if (i2c_transfer(state->i2c, &msg, 1) != 1) { 243 if (i2c_transfer(state->i2c, &msg, 1) != 1) {
168 printk(KERN_WARNING "DiB0090 I2C write failed\n"); 244 printk(KERN_WARNING "DiB0090 I2C write failed\n");
169 return -EREMOTEIO; 245 return -EREMOTEIO;
@@ -183,89 +259,329 @@ static void dib0090_write_regs(struct dib0090_state *state, u8 r, const u16 * b,
183 } while (--c); 259 } while (--c);
184} 260}
185 261
186static u16 dib0090_identify(struct dvb_frontend *fe) 262static int dib0090_identify(struct dvb_frontend *fe)
187{ 263{
188 struct dib0090_state *state = fe->tuner_priv; 264 struct dib0090_state *state = fe->tuner_priv;
189 u16 v; 265 u16 v;
266 struct dib0090_identity *identity = &state->identity;
190 267
191 v = dib0090_read_reg(state, 0x1a); 268 v = dib0090_read_reg(state, 0x1a);
192 269
193#ifdef FIRMWARE_FIREFLY 270 identity->p1g = 0;
194 /* pll is not locked locked */ 271 identity->in_soc = 0;
195 if (!(v & 0x800)) 272
196 dprintk("FE%d : Identification : pll is not yet locked", fe->id); 273 dprintk("Tuner identification (Version = 0x%04x)", v);
197#endif
198 274
199 /* without PLL lock info */ 275 /* without PLL lock info */
200 v &= 0x3ff; 276 v &= ~KROSUS_PLL_LOCKED;
201 dprintk("P/V: %04x:", v);
202 277
203 if ((v >> 8) & 0xf) 278 identity->version = v & 0xff;
204 dprintk("FE%d : Product ID = 0x%x : KROSUS", fe->id, (v >> 8) & 0xf); 279 identity->product = (v >> 8) & 0xf;
205 else 280
206 return 0xff; 281 if (identity->product != KROSUS)
207 282 goto identification_error;
208 v &= 0xff; 283
209 if (((v >> 5) & 0x7) == 0x1) 284 if ((identity->version & 0x3) == SOC) {
210 dprintk("FE%d : MP001 : 9090/8096", fe->id); 285 identity->in_soc = 1;
211 else if (((v >> 5) & 0x7) == 0x4) 286 switch (identity->version) {
212 dprintk("FE%d : MP005 : Single Sband", fe->id); 287 case SOC_8090_P1G_11R1:
213 else if (((v >> 5) & 0x7) == 0x6) 288 dprintk("SOC 8090 P1-G11R1 Has been detected");
214 dprintk("FE%d : MP008 : diversity VHF-UHF-LBAND", fe->id); 289 identity->p1g = 1;
215 else if (((v >> 5) & 0x7) == 0x7) 290 break;
216 dprintk("FE%d : MP009 : diversity 29098 CBAND-UHF-LBAND-SBAND", fe->id); 291 case SOC_8090_P1G_21R1:
217 else 292 dprintk("SOC 8090 P1-G21R1 Has been detected");
218 return 0xff; 293 identity->p1g = 1;
219 294 break;
220 /* revision only */ 295 case SOC_7090_P1G_11R1:
221 if ((v & 0x1f) == 0x3) 296 dprintk("SOC 7090 P1-G11R1 Has been detected");
222 dprintk("FE%d : P1-D/E/F detected", fe->id); 297 identity->p1g = 1;
223 else if ((v & 0x1f) == 0x1) 298 break;
224 dprintk("FE%d : P1C detected", fe->id); 299 case SOC_7090_P1G_21R1:
225 else if ((v & 0x1f) == 0x0) { 300 dprintk("SOC 7090 P1-G21R1 Has been detected");
226#ifdef CONFIG_TUNER_DIB0090_P1B_SUPPORT 301 identity->p1g = 1;
227 dprintk("FE%d : P1-A/B detected: using previous driver - support will be removed soon", fe->id); 302 break;
228 dib0090_p1b_register(fe); 303 default:
229#else 304 goto identification_error;
230 dprintk("FE%d : P1-A/B detected: driver is deactivated - not available", fe->id); 305 }
231 return 0xff; 306 } else {
232#endif 307 switch ((identity->version >> 5) & 0x7) {
308 case MP001:
309 dprintk("MP001 : 9090/8096");
310 break;
311 case MP005:
312 dprintk("MP005 : Single Sband");
313 break;
314 case MP008:
315 dprintk("MP008 : diversity VHF-UHF-LBAND");
316 break;
317 case MP009:
318 dprintk("MP009 : diversity 29098 CBAND-UHF-LBAND-SBAND");
319 break;
320 default:
321 goto identification_error;
322 }
323
324 switch (identity->version & 0x1f) {
325 case P1G_21R2:
326 dprintk("P1G_21R2 detected");
327 identity->p1g = 1;
328 break;
329 case P1G:
330 dprintk("P1G detected");
331 identity->p1g = 1;
332 break;
333 case P1D_E_F:
334 dprintk("P1D/E/F detected");
335 break;
336 case P1C:
337 dprintk("P1C detected");
338 break;
339 case P1A_B:
340 dprintk("P1-A/B detected: driver is deactivated - not available");
341 goto identification_error;
342 break;
343 default:
344 goto identification_error;
345 }
233 } 346 }
234 347
235 return v; 348 return 0;
349
350 identification_error:
351 return -EIO;
352}
353
354static int dib0090_fw_identify(struct dvb_frontend *fe)
355{
356 struct dib0090_fw_state *state = fe->tuner_priv;
357 struct dib0090_identity *identity = &state->identity;
358
359 u16 v = dib0090_fw_read_reg(state, 0x1a);
360 identity->p1g = 0;
361 identity->in_soc = 0;
362
363 dprintk("FE: Tuner identification (Version = 0x%04x)", v);
364
365 /* without PLL lock info */
366 v &= ~KROSUS_PLL_LOCKED;
367
368 identity->version = v & 0xff;
369 identity->product = (v >> 8) & 0xf;
370
371 if (identity->product != KROSUS)
372 goto identification_error;
373
374 //From the SOC the version definition has changed
375
376 if ((identity->version & 0x3) == SOC) {
377 identity->in_soc = 1;
378 switch (identity->version) {
379 case SOC_8090_P1G_11R1:
380 dprintk("SOC 8090 P1-G11R1 Has been detected");
381 identity->p1g = 1;
382 break;
383 case SOC_8090_P1G_21R1:
384 dprintk("SOC 8090 P1-G21R1 Has been detected");
385 identity->p1g = 1;
386 break;
387 case SOC_7090_P1G_11R1:
388 dprintk("SOC 7090 P1-G11R1 Has been detected");
389 identity->p1g = 1;
390 break;
391 case SOC_7090_P1G_21R1:
392 dprintk("SOC 7090 P1-G21R1 Has been detected");
393 identity->p1g = 1;
394 break;
395 default:
396 goto identification_error;
397 }
398 } else {
399 switch ((identity->version >> 5) & 0x7) {
400 case MP001:
401 dprintk("MP001 : 9090/8096");
402 break;
403 case MP005:
404 dprintk("MP005 : Single Sband");
405 break;
406 case MP008:
407 dprintk("MP008 : diversity VHF-UHF-LBAND");
408 break;
409 case MP009:
410 dprintk("MP009 : diversity 29098 CBAND-UHF-LBAND-SBAND");
411 break;
412 default:
413 goto identification_error;
414 }
415
416 switch (identity->version & 0x1f) {
417 case P1G_21R2:
418 dprintk("P1G_21R2 detected");
419 identity->p1g = 1;
420 break;
421 case P1G:
422 dprintk("P1G detected");
423 identity->p1g = 1;
424 break;
425 case P1D_E_F:
426 dprintk("P1D/E/F detected");
427 break;
428 case P1C:
429 dprintk("P1C detected");
430 break;
431 case P1A_B:
432 dprintk("P1-A/B detected: driver is deactivated - not available");
433 goto identification_error;
434 break;
435 default:
436 goto identification_error;
437 }
438 }
439
440 return 0;
441
442 identification_error:
443 return -EIO;;
236} 444}
237 445
238static void dib0090_reset_digital(struct dvb_frontend *fe, const struct dib0090_config *cfg) 446static void dib0090_reset_digital(struct dvb_frontend *fe, const struct dib0090_config *cfg)
239{ 447{
240 struct dib0090_state *state = fe->tuner_priv; 448 struct dib0090_state *state = fe->tuner_priv;
449 u16 PllCfg, i, v;
241 450
242 HARD_RESET(state); 451 HARD_RESET(state);
243 452
244 dib0090_write_reg(state, 0x24, EN_PLL); 453 dib0090_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL);
245 dib0090_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */ 454 dib0090_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */
246 455
247 /* adcClkOutRatio=8->7, release reset */ 456 if (!cfg->in_soc) {
248 dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (0 << 4) | 0); 457 /* adcClkOutRatio=8->7, release reset */
458 dib0090_write_reg(state, 0x20, ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (0 << 4) | 0);
459 if (cfg->clkoutdrive != 0)
460 dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | (0 << 8)
461 | (cfg->clkoutdrive << 5) | (cfg->clkouttobamse << 4) | (0 << 2) | (0));
462 else
463 dib0090_write_reg(state, 0x23, (0 << 15) | ((!cfg->analog_output) << 14) | (2 << 10) | (1 << 9) | (0 << 8)
464 | (7 << 5) | (cfg->clkouttobamse << 4) | (0 << 2) | (0));
465 }
466
467 /* Read Pll current config * */
468 PllCfg = dib0090_read_reg(state, 0x21);
469
470 /** Reconfigure PLL if current setting is different from default setting **/
471 if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && (!cfg->in_soc)
472 && !cfg->io.pll_bypass) {
473
474 /* Set Bypass mode */
475 PllCfg |= (1 << 15);
476 dib0090_write_reg(state, 0x21, PllCfg);
477
478 /* Set Reset Pll */
479 PllCfg &= ~(1 << 13);
480 dib0090_write_reg(state, 0x21, PllCfg);
481
482 /*** Set new Pll configuration in bypass and reset state ***/
483 PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv);
484 dib0090_write_reg(state, 0x21, PllCfg);
485
486 /* Remove Reset Pll */
487 PllCfg |= (1 << 13);
488 dib0090_write_reg(state, 0x21, PllCfg);
489
490 /*** Wait for PLL lock ***/
491 i = 100;
492 do {
493 v = !!(dib0090_read_reg(state, 0x1a) & 0x800);
494 if (v)
495 break;
496 } while (--i);
497
498 if (i == 0) {
499 dprintk("Pll: Unable to lock Pll");
500 return;
501 }
502
503 /* Finally Remove Bypass mode */
504 PllCfg &= ~(1 << 15);
505 dib0090_write_reg(state, 0x21, PllCfg);
506 }
507
508 if (cfg->io.pll_bypass) {
509 PllCfg |= (cfg->io.pll_bypass << 15);
510 dib0090_write_reg(state, 0x21, PllCfg);
511 }
512}
513
514static int dib0090_fw_reset_digital(struct dvb_frontend *fe, const struct dib0090_config *cfg)
515{
516 struct dib0090_fw_state *state = fe->tuner_priv;
517 u16 PllCfg;
518 u16 v;
519 int i;
520
521 dprintk("fw reset digital");
522 HARD_RESET(state);
523
524 dib0090_fw_write_reg(state, 0x24, EN_PLL | EN_CRYSTAL);
525 dib0090_fw_write_reg(state, 0x1b, EN_DIGCLK | EN_PLL | EN_CRYSTAL); /* PLL, DIG_CLK and CRYSTAL remain */
526
527 dib0090_fw_write_reg(state, 0x20,
528 ((cfg->io.adc_clock_ratio - 1) << 11) | (0 << 10) | (1 << 9) | (1 << 8) | (cfg->data_tx_drv << 4) | cfg->ls_cfg_pad_drv);
529
530 v = (0 << 15) | ((!cfg->analog_output) << 14) | (1 << 9) | (0 << 8) | (cfg->clkouttobamse << 4) | (0 << 2) | (0);
249 if (cfg->clkoutdrive != 0) 531 if (cfg->clkoutdrive != 0)
250 dib0090_write_reg(state, 0x23, 532 v |= cfg->clkoutdrive << 5;
251 (0 << 15) | ((!cfg->analog_output) << 14) | (1 << 10) | (1 << 9) | (0 << 8) | (cfg->clkoutdrive << 5) | (cfg->
252 clkouttobamse
253 << 4) | (0
254 <<
255 2)
256 | (0));
257 else 533 else
258 dib0090_write_reg(state, 0x23, 534 v |= 7 << 5;
259 (0 << 15) | ((!cfg->analog_output) << 14) | (1 << 10) | (1 << 9) | (0 << 8) | (7 << 5) | (cfg-> 535
260 clkouttobamse << 4) | (0 536 v |= 2 << 10;
261 << 537 dib0090_fw_write_reg(state, 0x23, v);
262 2) 538
263 | (0)); 539 /* Read Pll current config * */
540 PllCfg = dib0090_fw_read_reg(state, 0x21);
541
542 /** Reconfigure PLL if current setting is different from default setting **/
543 if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && !cfg->io.pll_bypass) {
264 544
265 /* enable pll, de-activate reset, ratio: 2/1 = 60MHz */ 545 /* Set Bypass mode */
266 dib0090_write_reg(state, 0x21, 546 PllCfg |= (1 << 15);
267 (cfg->io.pll_bypass << 15) | (1 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)); 547 dib0090_fw_write_reg(state, 0x21, PllCfg);
268 548
549 /* Set Reset Pll */
550 PllCfg &= ~(1 << 13);
551 dib0090_fw_write_reg(state, 0x21, PllCfg);
552
553 /*** Set new Pll configuration in bypass and reset state ***/
554 PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv);
555 dib0090_fw_write_reg(state, 0x21, PllCfg);
556
557 /* Remove Reset Pll */
558 PllCfg |= (1 << 13);
559 dib0090_fw_write_reg(state, 0x21, PllCfg);
560
561 /*** Wait for PLL lock ***/
562 i = 100;
563 do {
564 v = !!(dib0090_fw_read_reg(state, 0x1a) & 0x800);
565 if (v)
566 break;
567 } while (--i);
568
569 if (i == 0) {
570 dprintk("Pll: Unable to lock Pll");
571 return -EIO;
572 }
573
574 /* Finally Remove Bypass mode */
575 PllCfg &= ~(1 << 15);
576 dib0090_fw_write_reg(state, 0x21, PllCfg);
577 }
578
579 if (cfg->io.pll_bypass) {
580 PllCfg |= (cfg->io.pll_bypass << 15);
581 dib0090_fw_write_reg(state, 0x21, PllCfg);
582 }
583
584 return dib0090_fw_identify(fe);
269} 585}
270 586
271static int dib0090_wakeup(struct dvb_frontend *fe) 587static int dib0090_wakeup(struct dvb_frontend *fe)
@@ -273,6 +589,9 @@ static int dib0090_wakeup(struct dvb_frontend *fe)
273 struct dib0090_state *state = fe->tuner_priv; 589 struct dib0090_state *state = fe->tuner_priv;
274 if (state->config->sleep) 590 if (state->config->sleep)
275 state->config->sleep(fe, 0); 591 state->config->sleep(fe, 0);
592
593 /* enable dataTX in case we have been restarted in the wrong moment */
594 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
276 return 0; 595 return 0;
277} 596}
278 597
@@ -292,8 +611,75 @@ void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast)
292 else 611 else
293 dib0090_write_reg(state, 0x04, 1); 612 dib0090_write_reg(state, 0x04, 1);
294} 613}
614
295EXPORT_SYMBOL(dib0090_dcc_freq); 615EXPORT_SYMBOL(dib0090_dcc_freq);
296 616
617static const u16 bb_ramp_pwm_normal_socs[] = {
618 550, /* max BB gain in 10th of dB */
619 (1 << 9) | 8, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> BB_RAMP2 */
620 440,
621 (4 << 9) | 0, /* BB_RAMP3 = 26dB */
622 (0 << 9) | 208, /* BB_RAMP4 */
623 (4 << 9) | 208, /* BB_RAMP5 = 29dB */
624 (0 << 9) | 440, /* BB_RAMP6 */
625};
626
627static const u16 rf_ramp_pwm_cband_7090[] = {
628 280, /* max RF gain in 10th of dB */
629 18, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
630 504, /* ramp_max = maximum X used on the ramp */
631 (29 << 10) | 364, /* RF_RAMP5, LNA 1 = 8dB */
632 (0 << 10) | 504, /* RF_RAMP6, LNA 1 */
633 (60 << 10) | 228, /* RF_RAMP7, LNA 2 = 7.7dB */
634 (0 << 10) | 364, /* RF_RAMP8, LNA 2 */
635 (34 << 10) | 109, /* GAIN_4_1, LNA 3 = 6.8dB */
636 (0 << 10) | 228, /* GAIN_4_2, LNA 3 */
637 (37 << 10) | 0, /* RF_RAMP3, LNA 4 = 6.2dB */
638 (0 << 10) | 109, /* RF_RAMP4, LNA 4 */
639};
640
641static const u16 rf_ramp_pwm_cband_8090[] = {
642 345, /* max RF gain in 10th of dB */
643 29, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
644 1000, /* ramp_max = maximum X used on the ramp */
645 (35 << 10) | 772, /* RF_RAMP3, LNA 1 = 8dB */
646 (0 << 10) | 1000, /* RF_RAMP4, LNA 1 */
647 (58 << 10) | 496, /* RF_RAMP5, LNA 2 = 9.5dB */
648 (0 << 10) | 772, /* RF_RAMP6, LNA 2 */
649 (27 << 10) | 200, /* RF_RAMP7, LNA 3 = 10.5dB */
650 (0 << 10) | 496, /* RF_RAMP8, LNA 3 */
651 (40 << 10) | 0, /* GAIN_4_1, LNA 4 = 7dB */
652 (0 << 10) | 200, /* GAIN_4_2, LNA 4 */
653};
654
655static const u16 rf_ramp_pwm_uhf_7090[] = {
656 407, /* max RF gain in 10th of dB */
657 13, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
658 529, /* ramp_max = maximum X used on the ramp */
659 (23 << 10) | 0, /* RF_RAMP3, LNA 1 = 14.7dB */
660 (0 << 10) | 176, /* RF_RAMP4, LNA 1 */
661 (63 << 10) | 400, /* RF_RAMP5, LNA 2 = 8dB */
662 (0 << 10) | 529, /* RF_RAMP6, LNA 2 */
663 (48 << 10) | 316, /* RF_RAMP7, LNA 3 = 6.8dB */
664 (0 << 10) | 400, /* RF_RAMP8, LNA 3 */
665 (29 << 10) | 176, /* GAIN_4_1, LNA 4 = 11.5dB */
666 (0 << 10) | 316, /* GAIN_4_2, LNA 4 */
667};
668
669static const u16 rf_ramp_pwm_uhf_8090[] = {
670 388, /* max RF gain in 10th of dB */
671 26, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> RF_RAMP2 */
672 1008, /* ramp_max = maximum X used on the ramp */
673 (11 << 10) | 0, /* RF_RAMP3, LNA 1 = 14.7dB */
674 (0 << 10) | 369, /* RF_RAMP4, LNA 1 */
675 (41 << 10) | 809, /* RF_RAMP5, LNA 2 = 8dB */
676 (0 << 10) | 1008, /* RF_RAMP6, LNA 2 */
677 (27 << 10) | 659, /* RF_RAMP7, LNA 3 = 6dB */
678 (0 << 10) | 809, /* RF_RAMP8, LNA 3 */
679 (14 << 10) | 369, /* GAIN_4_1, LNA 4 = 11.5dB */
680 (0 << 10) | 659, /* GAIN_4_2, LNA 4 */
681};
682
297static const u16 rf_ramp_pwm_cband[] = { 683static const u16 rf_ramp_pwm_cband[] = {
298 0, /* max RF gain in 10th of dB */ 684 0, /* max RF gain in 10th of dB */
299 0, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x2b */ 685 0, /* ramp_slope = 1dB of gain -> clock_ticks_per_db = clk_khz / ramp_slope -> 0x2b */
@@ -326,6 +712,16 @@ static const u16 rf_ramp_uhf[] = {
326 0, 0, 127, /* CBAND : 0.0 dB */ 712 0, 0, 127, /* CBAND : 0.0 dB */
327}; 713};
328 714
715static const u16 rf_ramp_cband_broadmatching[] = /* for p1G only */
716{
717 314, /* Calibrated at 200MHz order has been changed g4-g3-g2-g1 */
718 84, 314, 127, /* LNA1 */
719 80, 230, 255, /* LNA2 */
720 80, 150, 127, /* LNA3 It was measured 12dB, do not lock if 120 */
721 70, 70, 127, /* LNA4 */
722 0, 0, 127, /* CBAND */
723};
724
329static const u16 rf_ramp_cband[] = { 725static const u16 rf_ramp_cband[] = {
330 332, /* max RF gain in 10th of dB */ 726 332, /* max RF gain in 10th of dB */
331 132, 252, 127, /* LNA1, dB */ 727 132, 252, 127, /* LNA1, dB */
@@ -380,8 +776,8 @@ static const u16 bb_ramp_pwm_normal[] = {
380}; 776};
381 777
382struct slope { 778struct slope {
383 int16_t range; 779 s16 range;
384 int16_t slope; 780 s16 slope;
385}; 781};
386static u16 slopes_to_scale(const struct slope *slopes, u8 num, s16 val) 782static u16 slopes_to_scale(const struct slope *slopes, u8 num, s16 val)
387{ 783{
@@ -597,19 +993,40 @@ void dib0090_pwm_gain_reset(struct dvb_frontend *fe)
597#endif 993#endif
598#ifdef CONFIG_BAND_CBAND 994#ifdef CONFIG_BAND_CBAND
599 if (state->current_band == BAND_CBAND) { 995 if (state->current_band == BAND_CBAND) {
600 dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband); 996 if (state->identity.in_soc) {
601 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal); 997 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal_socs);
998 if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
999 dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband_8090);
1000 else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1)
1001 dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband_7090);
1002 } else {
1003 dib0090_set_rframp_pwm(state, rf_ramp_pwm_cband);
1004 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
1005 }
602 } else 1006 } else
603#endif 1007#endif
604#ifdef CONFIG_BAND_VHF 1008#ifdef CONFIG_BAND_VHF
605 if (state->current_band == BAND_VHF) { 1009 if (state->current_band == BAND_VHF) {
606 dib0090_set_rframp_pwm(state, rf_ramp_pwm_vhf); 1010 if (state->identity.in_soc) {
607 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal); 1011 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal_socs);
1012 //dib0090_set_rframp_pwm(state, rf_ramp_pwm_vhf_socs); /* TODO */
1013 } else {
1014 dib0090_set_rframp_pwm(state, rf_ramp_pwm_vhf);
1015 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
1016 }
608 } else 1017 } else
609#endif 1018#endif
610 { 1019 {
611 dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf); 1020 if (state->identity.in_soc) {
612 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal); 1021 if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
1022 dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf_8090);
1023 else if (state->identity.version == SOC_7090_P1G_11R1 || state->identity.version == SOC_7090_P1G_21R1)
1024 dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf_7090);
1025 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal_socs);
1026 } else {
1027 dib0090_set_rframp_pwm(state, rf_ramp_pwm_uhf);
1028 dib0090_set_bbramp_pwm(state, bb_ramp_pwm_normal);
1029 }
613 } 1030 }
614 1031
615 if (state->rf_ramp[0] != 0) 1032 if (state->rf_ramp[0] != 0)
@@ -617,11 +1034,22 @@ void dib0090_pwm_gain_reset(struct dvb_frontend *fe)
617 else 1034 else
618 dib0090_write_reg(state, 0x32, (0 << 11)); 1035 dib0090_write_reg(state, 0x32, (0 << 11));
619 1036
1037 dib0090_write_reg(state, 0x04, 0x01);
620 dib0090_write_reg(state, 0x39, (1 << 10)); 1038 dib0090_write_reg(state, 0x39, (1 << 10));
621 } 1039 }
622} 1040}
1041
623EXPORT_SYMBOL(dib0090_pwm_gain_reset); 1042EXPORT_SYMBOL(dib0090_pwm_gain_reset);
624 1043
1044static u32 dib0090_get_slow_adc_val(struct dib0090_state *state)
1045{
1046 u16 adc_val = dib0090_read_reg(state, 0x1d);
1047 if (state->identity.in_soc) {
1048 adc_val >>= 2;
1049 }
1050 return adc_val;
1051}
1052
625int dib0090_gain_control(struct dvb_frontend *fe) 1053int dib0090_gain_control(struct dvb_frontend *fe)
626{ 1054{
627 struct dib0090_state *state = fe->tuner_priv; 1055 struct dib0090_state *state = fe->tuner_priv;
@@ -643,18 +1071,21 @@ int dib0090_gain_control(struct dvb_frontend *fe)
643 } else 1071 } else
644#endif 1072#endif
645#ifdef CONFIG_BAND_VHF 1073#ifdef CONFIG_BAND_VHF
646 if (state->current_band == BAND_VHF) { 1074 if (state->current_band == BAND_VHF && !state->identity.p1g) {
647 dib0090_set_rframp(state, rf_ramp_vhf); 1075 dib0090_set_rframp(state, rf_ramp_vhf);
648 dib0090_set_bbramp(state, bb_ramp_boost); 1076 dib0090_set_bbramp(state, bb_ramp_boost);
649 } else 1077 } else
650#endif 1078#endif
651#ifdef CONFIG_BAND_CBAND 1079#ifdef CONFIG_BAND_CBAND
652 if (state->current_band == BAND_CBAND) { 1080 if (state->current_band == BAND_CBAND && !state->identity.p1g) {
653 dib0090_set_rframp(state, rf_ramp_cband); 1081 dib0090_set_rframp(state, rf_ramp_cband);
654 dib0090_set_bbramp(state, bb_ramp_boost); 1082 dib0090_set_bbramp(state, bb_ramp_boost);
655 } else 1083 } else
656#endif 1084#endif
657 { 1085 if ((state->current_band == BAND_CBAND || state->current_band == BAND_VHF) && state->identity.p1g) {
1086 dib0090_set_rframp(state, rf_ramp_cband_broadmatching);
1087 dib0090_set_bbramp(state, bb_ramp_boost);
1088 } else {
658 dib0090_set_rframp(state, rf_ramp_uhf); 1089 dib0090_set_rframp(state, rf_ramp_uhf);
659 dib0090_set_bbramp(state, bb_ramp_boost); 1090 dib0090_set_bbramp(state, bb_ramp_boost);
660 } 1091 }
@@ -669,17 +1100,25 @@ int dib0090_gain_control(struct dvb_frontend *fe)
669 1100
670 *tune_state = CT_AGC_STEP_0; 1101 *tune_state = CT_AGC_STEP_0;
671 } else if (!state->agc_freeze) { 1102 } else if (!state->agc_freeze) {
672 s16 wbd; 1103 s16 wbd = 0, i, cnt;
673 1104
674 int adc; 1105 int adc;
675 wbd_val = dib0090_read_reg(state, 0x1d); 1106 wbd_val = dib0090_get_slow_adc_val(state);
676 1107
677 /* read and calc the wbd power */ 1108 if (*tune_state == CT_AGC_STEP_0)
678 wbd = dib0090_wbd_to_db(state, wbd_val); 1109 cnt = 5;
1110 else
1111 cnt = 1;
1112
1113 for (i = 0; i < cnt; i++) {
1114 wbd_val = dib0090_get_slow_adc_val(state);
1115 wbd += dib0090_wbd_to_db(state, wbd_val);
1116 }
1117 wbd /= cnt;
679 wbd_error = state->wbd_target - wbd; 1118 wbd_error = state->wbd_target - wbd;
680 1119
681 if (*tune_state == CT_AGC_STEP_0) { 1120 if (*tune_state == CT_AGC_STEP_0) {
682 if (wbd_error < 0 && state->rf_gain_limit > 0) { 1121 if (wbd_error < 0 && state->rf_gain_limit > 0 && !state->identity.p1g) {
683#ifdef CONFIG_BAND_CBAND 1122#ifdef CONFIG_BAND_CBAND
684 /* in case of CBAND tune reduce first the lt_gain2 before adjusting the RF gain */ 1123 /* in case of CBAND tune reduce first the lt_gain2 before adjusting the RF gain */
685 u8 ltg2 = (state->rf_lt_def >> 10) & 0x7; 1124 u8 ltg2 = (state->rf_lt_def >> 10) & 0x7;
@@ -700,39 +1139,39 @@ int dib0090_gain_control(struct dvb_frontend *fe)
700 adc_error = (s16) (((s32) ADC_TARGET) - adc); 1139 adc_error = (s16) (((s32) ADC_TARGET) - adc);
701#ifdef CONFIG_STANDARD_DAB 1140#ifdef CONFIG_STANDARD_DAB
702 if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB) 1141 if (state->fe->dtv_property_cache.delivery_system == STANDARD_DAB)
703 adc_error += 130; 1142 adc_error -= 10;
704#endif 1143#endif
705#ifdef CONFIG_STANDARD_DVBT 1144#ifdef CONFIG_STANDARD_DVBT
706 if (state->fe->dtv_property_cache.delivery_system == STANDARD_DVBT && 1145 if (state->fe->dtv_property_cache.delivery_system == STANDARD_DVBT &&
707 (state->fe->dtv_property_cache.modulation == QAM_64 || state->fe->dtv_property_cache.modulation == QAM_16)) 1146 (state->fe->dtv_property_cache.modulation == QAM_64 || state->fe->dtv_property_cache.modulation == QAM_16))
708 adc_error += 60; 1147 adc_error += 60;
709#endif 1148#endif
710#ifdef CONFIG_SYS_ISDBT 1149#ifdef CONFIG_SYS_ISDBT
711 if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) && (((state->fe->dtv_property_cache.layer[0].segment_count > 1150 if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT) && (((state->fe->dtv_property_cache.layer[0].segment_count >
712 0) 1151 0)
713 && 1152 &&
714 ((state->fe->dtv_property_cache.layer[0].modulation == 1153 ((state->fe->dtv_property_cache.layer[0].modulation ==
715 QAM_64) 1154 QAM_64)
716 || (state->fe->dtv_property_cache.layer[0]. 1155 || (state->fe->dtv_property_cache.
717 modulation == QAM_16))) 1156 layer[0].modulation == QAM_16)))
718 || 1157 ||
719 ((state->fe->dtv_property_cache.layer[1].segment_count > 1158 ((state->fe->dtv_property_cache.layer[1].segment_count >
720 0) 1159 0)
721 && 1160 &&
722 ((state->fe->dtv_property_cache.layer[1].modulation == 1161 ((state->fe->dtv_property_cache.layer[1].modulation ==
723 QAM_64) 1162 QAM_64)
724 || (state->fe->dtv_property_cache.layer[1]. 1163 || (state->fe->dtv_property_cache.
725 modulation == QAM_16))) 1164 layer[1].modulation == QAM_16)))
726 || 1165 ||
727 ((state->fe->dtv_property_cache.layer[2].segment_count > 1166 ((state->fe->dtv_property_cache.layer[2].segment_count >
728 0) 1167 0)
729 && 1168 &&
730 ((state->fe->dtv_property_cache.layer[2].modulation == 1169 ((state->fe->dtv_property_cache.layer[2].modulation ==
731 QAM_64) 1170 QAM_64)
732 || (state->fe->dtv_property_cache.layer[2]. 1171 || (state->fe->dtv_property_cache.
733 modulation == QAM_16))) 1172 layer[2].modulation == QAM_16)))
734 ) 1173 )
735 ) 1174 )
736 adc_error += 60; 1175 adc_error += 60;
737#endif 1176#endif
738 1177
@@ -760,9 +1199,9 @@ int dib0090_gain_control(struct dvb_frontend *fe)
760 } 1199 }
761#ifdef DEBUG_AGC 1200#ifdef DEBUG_AGC
762 dprintk 1201 dprintk
763 ("FE: %d, tune state %d, ADC = %3ddB (ADC err %3d) WBD %3ddB (WBD err %3d, WBD val SADC: %4d), RFGainLimit (TOP): %3d, signal: %3ddBm", 1202 ("tune state %d, ADC = %3ddB (ADC err %3d) WBD %3ddB (WBD err %3d, WBD val SADC: %4d), RFGainLimit (TOP): %3d, signal: %3ddBm",
764 (u32) fe->id, (u32) *tune_state, (u32) adc, (u32) adc_error, (u32) wbd, (u32) wbd_error, (u32) wbd_val, 1203 (u32) * tune_state, (u32) adc, (u32) adc_error, (u32) wbd, (u32) wbd_error, (u32) wbd_val,
765 (u32) state->rf_gain_limit >> WBD_ALPHA, (s32) 200 + adc - (state->current_gain >> GAIN_ALPHA)); 1204 (u32) state->rf_gain_limit >> WBD_ALPHA, (s32) 200 + adc - (state->current_gain >> GAIN_ALPHA));
766#endif 1205#endif
767 } 1206 }
768 1207
@@ -771,6 +1210,7 @@ int dib0090_gain_control(struct dvb_frontend *fe)
771 dib0090_gain_apply(state, adc_error, wbd_error, apply_gain_immediatly); 1210 dib0090_gain_apply(state, adc_error, wbd_error, apply_gain_immediatly);
772 return ret; 1211 return ret;
773} 1212}
1213
774EXPORT_SYMBOL(dib0090_gain_control); 1214EXPORT_SYMBOL(dib0090_gain_control);
775 1215
776void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt) 1216void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 * rf_gain_limit, u16 * rflt)
@@ -785,13 +1225,53 @@ void dib0090_get_current_gain(struct dvb_frontend *fe, u16 * rf, u16 * bb, u16 *
785 if (rflt) 1225 if (rflt)
786 *rflt = (state->rf_lt_def >> 10) & 0x7; 1226 *rflt = (state->rf_lt_def >> 10) & 0x7;
787} 1227}
1228
788EXPORT_SYMBOL(dib0090_get_current_gain); 1229EXPORT_SYMBOL(dib0090_get_current_gain);
789 1230
790u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner) 1231u16 dib0090_get_wbd_offset(struct dvb_frontend *fe)
791{ 1232{
792 struct dib0090_state *st = tuner->tuner_priv; 1233 struct dib0090_state *state = fe->tuner_priv;
793 return st->wbd_offset; 1234 u32 f_MHz = state->fe->dtv_property_cache.frequency / 1000000;
1235 s32 current_temp = state->temperature;
1236 s32 wbd_thot, wbd_tcold;
1237 const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
1238
1239 while (f_MHz > wbd->max_freq)
1240 wbd++;
1241
1242 dprintk("using wbd-table-entry with max freq %d", wbd->max_freq);
1243
1244 if (current_temp < 0)
1245 current_temp = 0;
1246 if (current_temp > 128)
1247 current_temp = 128;
1248
1249 //What Wbd gain to apply for this range of frequency
1250 state->wbdmux &= ~(7 << 13);
1251 if (wbd->wbd_gain != 0)
1252 state->wbdmux |= (wbd->wbd_gain << 13);
1253 else
1254 state->wbdmux |= (4 << 13); // 4 is the default WBD gain
1255
1256 dib0090_write_reg(state, 0x10, state->wbdmux);
1257
1258 //All the curves are linear with slope*f/64+offset
1259 wbd_thot = wbd->offset_hot - (((u32) wbd->slope_hot * f_MHz) >> 6);
1260 wbd_tcold = wbd->offset_cold - (((u32) wbd->slope_cold * f_MHz) >> 6);
1261
1262 // Iet assumes that thot-tcold = 130 equiv 128, current temperature ref is -30deg
1263
1264 wbd_tcold += ((wbd_thot - wbd_tcold) * current_temp) >> 7;
1265
1266 //for (offset = 0; offset < 1000; offset += 4)
1267 // dbgp("offset = %d -> %d\n", offset, dib0090_wbd_to_db(state, offset));
1268 state->wbd_target = dib0090_wbd_to_db(state, state->wbd_offset + wbd_tcold); // get the value in dBm from the offset
1269 dprintk("wbd-target: %d dB", (u32) state->wbd_target);
1270 dprintk("wbd offset applied is %d", wbd_tcold);
1271
1272 return state->wbd_offset + wbd_tcold;
794} 1273}
1274
795EXPORT_SYMBOL(dib0090_get_wbd_offset); 1275EXPORT_SYMBOL(dib0090_get_wbd_offset);
796 1276
797static const u16 dib0090_defaults[] = { 1277static const u16 dib0090_defaults[] = {
@@ -801,7 +1281,7 @@ static const u16 dib0090_defaults[] = {
801 0x99a0, 1281 0x99a0,
802 0x6008, 1282 0x6008,
803 0x0000, 1283 0x0000,
804 0x8acb, 1284 0x8bcb,
805 0x0000, 1285 0x0000,
806 0x0405, 1286 0x0405,
807 0x0000, 1287 0x0000,
@@ -829,8 +1309,6 @@ static const u16 dib0090_defaults[] = {
829 1, 0x39, 1309 1, 0x39,
830 0x0000, 1310 0x0000,
831 1311
832 1, 0x1b,
833 EN_IQADC | EN_BB | EN_BIAS | EN_DIGCLK | EN_PLL | EN_CRYSTAL,
834 2, 0x1e, 1312 2, 0x1e,
835 0x07FF, 1313 0x07FF,
836 0x0007, 1314 0x0007,
@@ -844,50 +1322,126 @@ static const u16 dib0090_defaults[] = {
844 0 1322 0
845}; 1323};
846 1324
847static int dib0090_reset(struct dvb_frontend *fe) 1325static const u16 dib0090_p1g_additionnal_defaults[] = {
848{ 1326 // additionnal INITIALISATION for p1g to be written after dib0090_defaults
849 struct dib0090_state *state = fe->tuner_priv; 1327 1, 0x05,
850 u16 l, r, *n; 1328 0xabcd,
851 1329
852 dib0090_reset_digital(fe, state->config); 1330 1, 0x11,
853 state->revision = dib0090_identify(fe); 1331 0x00b4,
854
855 /* Revision definition */
856 if (state->revision == 0xff)
857 return -EINVAL;
858#ifdef EFUSE
859 else if ((state->revision & 0x1f) >= 3) /* Update the efuse : Only available for KROSUS > P1C */
860 dib0090_set_EFUSE(state);
861#endif
862 1332
863#ifdef CONFIG_TUNER_DIB0090_P1B_SUPPORT 1333 1, 0x1c,
864 if (!(state->revision & 0x1)) /* it is P1B - reset is already done */ 1334 0xfffd,
865 return 0; 1335
866#endif 1336 1, 0x40,
1337 0x108,
1338 0
1339};
1340
1341static void dib0090_set_default_config(struct dib0090_state *state, const u16 * n)
1342{
1343 u16 l, r;
867 1344
868 /* Upload the default values */
869 n = (u16 *) dib0090_defaults;
870 l = pgm_read_word(n++); 1345 l = pgm_read_word(n++);
871 while (l) { 1346 while (l) {
872 r = pgm_read_word(n++); 1347 r = pgm_read_word(n++);
873 do { 1348 do {
874 /* DEBUG_TUNER */
875 /* dprintk("%d, %d, %d", l, r, pgm_read_word(n)); */
876 dib0090_write_reg(state, r, pgm_read_word(n++)); 1349 dib0090_write_reg(state, r, pgm_read_word(n++));
877 r++; 1350 r++;
878 } while (--l); 1351 } while (--l);
879 l = pgm_read_word(n++); 1352 l = pgm_read_word(n++);
880 } 1353 }
1354}
1355
1356#define CAP_VALUE_MIN (u8) 9
1357#define CAP_VALUE_MAX (u8) 40
1358#define HR_MIN (u8) 25
1359#define HR_MAX (u8) 40
1360#define POLY_MIN (u8) 0
1361#define POLY_MAX (u8) 8
1362
1363void dib0090_set_EFUSE(struct dib0090_state *state)
1364{
1365 u8 c,h,n;
1366 u16 e2,e4;
1367 u16 cal;
1368
1369 e2=dib0090_read_reg(state,0x26);
1370 e4=dib0090_read_reg(state,0x28);
1371
1372 if ((state->identity.version == P1D_E_F) || // All P1F uses the internal calibration
1373 (state->identity.version == P1G) || (e2 == 0xffff)) { //W0090G11R1 and W0090G11R1-D : We will find the calibration Value of the Baseband
1374
1375 dib0090_write_reg(state,0x22,0x10); //Start the Calib
1376 cal = (dib0090_read_reg(state,0x22)>>6) & 0x3ff;
1377
1378 if ((cal<670) || (cal==1023)) //Cal at 800 would give too high value for the n
1379 cal=850; //Recenter the n to 32
1380 n = 165 - ((cal * 10)>>6) ;
1381 e2 = e4 = (3<<12) | (34<<6) | (n);
1382 }
1383
1384 if (e2!=e4) {
1385 e2 &= e4; /* Remove the redundancy */
1386 }
1387
1388 if (e2 != 0xffff) {
1389 c = e2 & 0x3f;
1390 n = (e2 >> 12) & 0xf;
1391 h= (e2 >> 6) & 0x3f;
1392
1393 if ((c >= CAP_VALUE_MAX) || (c <= CAP_VALUE_MIN))
1394 c=32;
1395 if ((h >= HR_MAX) || (h <= HR_MIN))
1396 h=34;
1397 if ((n >= POLY_MAX) || (n <= POLY_MIN))
1398 n=3;
1399
1400 dib0090_write_reg(state,0x13, (h << 10)) ;
1401 e2 = (n<<11) | ((h>>2)<<6) | (c);
1402 dib0090_write_reg(state,0x2, e2) ; /* Load the BB_2 */
1403 }
1404}
1405
1406static int dib0090_reset(struct dvb_frontend *fe)
1407{
1408 struct dib0090_state *state = fe->tuner_priv;
1409
1410 dib0090_reset_digital(fe, state->config);
1411 if (dib0090_identify(fe) < 0)
1412 return -EIO;
1413
1414#ifdef CONFIG_TUNER_DIB0090_P1B_SUPPORT
1415 if (!(state->identity.version & 0x1)) /* it is P1B - reset is already done */
1416 return 0;
1417#endif
1418
1419 if (!state->identity.in_soc) {
1420 if ((dib0090_read_reg(state, 0x1a) >> 5) & 0x2)
1421 dib0090_write_reg(state, 0x1b, (EN_IQADC | EN_BB | EN_BIAS | EN_DIGCLK | EN_PLL | EN_CRYSTAL));
1422 else
1423 dib0090_write_reg(state, 0x1b, (EN_DIGCLK | EN_PLL | EN_CRYSTAL));
1424 }
1425
1426 dib0090_set_default_config(state, dib0090_defaults);
1427
1428 if (state->identity.in_soc)
1429 dib0090_write_reg(state, 0x18, 0x2910); /* charge pump current = 0 */
1430
1431 if (state->identity.p1g)
1432 dib0090_set_default_config(state, dib0090_p1g_additionnal_defaults);
1433
1434 if (((state->identity.version & 0x1f) >= P1D_E_F) || (state->identity.in_soc)) /* Update the efuse : Only available for KROSUS > P1C and SOC as well*/
1435 dib0090_set_EFUSE(state);
881 1436
882 /* Congigure in function of the crystal */ 1437 /* Congigure in function of the crystal */
883 if (state->config->io.clock_khz >= 24000) 1438 if (state->config->io.clock_khz >= 24000)
884 l = 1; 1439 dib0090_write_reg(state, 0x14, 1);
885 else 1440 else
886 l = 2; 1441 dib0090_write_reg(state, 0x14, 2);
887 dib0090_write_reg(state, 0x14, l);
888 dprintk("Pll lock : %d", (dib0090_read_reg(state, 0x1a) >> 11) & 0x1); 1442 dprintk("Pll lock : %d", (dib0090_read_reg(state, 0x1a) >> 11) & 0x1);
889 1443
890 state->reset = 3; /* enable iq-offset-calibration and wbd-calibration when tuning next time */ 1444 state->calibrate = DC_CAL | WBD_CAL | TEMP_CAL; /* enable iq-offset-calibration and wbd-calibration when tuning next time */
891 1445
892 return 0; 1446 return 0;
893} 1447}
@@ -927,11 +1481,11 @@ static int dib0090_get_offset(struct dib0090_state *state, enum frontend_tune_st
927} 1481}
928 1482
929struct dc_calibration { 1483struct dc_calibration {
930 uint8_t addr; 1484 u8 addr;
931 uint8_t offset; 1485 u8 offset;
932 uint8_t pga:1; 1486 u8 pga:1;
933 uint16_t bb1; 1487 u16 bb1;
934 uint8_t i:1; 1488 u8 i:1;
935}; 1489};
936 1490
937static const struct dc_calibration dc_table[] = { 1491static const struct dc_calibration dc_table[] = {
@@ -944,6 +1498,17 @@ static const struct dc_calibration dc_table[] = {
944 {0}, 1498 {0},
945}; 1499};
946 1500
1501static const struct dc_calibration dc_p1g_table[] = {
1502 /* Step1 BB gain1= 26 with boost 1, gain 2 = 0 */
1503 /* addr ; trim reg offset ; pga ; CTRL_BB1 value ; i or q */
1504 {0x06, 5, 1, (1 << 13) | (0 << 8) | (15 << 3), 1}, // offset_trim2_i_chann 0 0 5 0 0 1 6 9 5
1505 {0x07, 11, 1, (1 << 13) | (0 << 8) | (15 << 3), 0}, // offset_trim2_q_chann 0 0 5 0 0 1 7 15 11
1506 /* Step 2 BB gain 1 = 26 with boost = 1 & gain 2 = 29 */
1507 {0x06, 0, 0, (1 << 13) | (29 << 8) | (15 << 3), 1}, // offset_trim1_i_chann 0 0 5 0 0 1 6 4 0
1508 {0x06, 10, 0, (1 << 13) | (29 << 8) | (15 << 3), 0}, // offset_trim1_q_chann 0 0 5 0 0 1 6 14 10
1509 {0},
1510};
1511
947static void dib0090_set_trim(struct dib0090_state *state) 1512static void dib0090_set_trim(struct dib0090_state *state)
948{ 1513{
949 u16 *val; 1514 u16 *val;
@@ -962,41 +1527,45 @@ static void dib0090_set_trim(struct dib0090_state *state)
962static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state) 1527static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state)
963{ 1528{
964 int ret = 0; 1529 int ret = 0;
1530 u16 reg;
965 1531
966 switch (*tune_state) { 1532 switch (*tune_state) {
967
968 case CT_TUNER_START: 1533 case CT_TUNER_START:
969 /* init */ 1534 dprintk("Start DC offset calibration");
970 dprintk("Internal DC calibration");
971
972 /* the LNA is off */
973 dib0090_write_reg(state, 0x24, 0x02ed);
974 1535
975 /* force vcm2 = 0.8V */ 1536 /* force vcm2 = 0.8V */
976 state->bb6 = 0; 1537 state->bb6 = 0;
977 state->bb7 = 0x040d; 1538 state->bb7 = 0x040d;
978 1539
1540 /* the LNA AND LO are off */
1541 reg = dib0090_read_reg(state, 0x24) & 0x0ffb; /* shutdown lna and lo */
1542 dib0090_write_reg(state, 0x24, reg);
1543
1544 state->wbdmux = dib0090_read_reg(state, 0x10);
1545 dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x7 << 3) | 0x3); // connect BB, disable WDB enable*
1546 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14)); //Discard the DataTX
1547
979 state->dc = dc_table; 1548 state->dc = dc_table;
980 1549
1550 if (state->identity.p1g)
1551 state->dc = dc_p1g_table;
981 *tune_state = CT_TUNER_STEP_0; 1552 *tune_state = CT_TUNER_STEP_0;
982 1553
983 /* fall through */ 1554 /* fall through */
984 1555
985 case CT_TUNER_STEP_0: 1556 case CT_TUNER_STEP_0:
1557 dprintk("Sart/continue DC calibration for %s path", (state->dc->i == 1) ? "I" : "Q");
986 dib0090_write_reg(state, 0x01, state->dc->bb1); 1558 dib0090_write_reg(state, 0x01, state->dc->bb1);
987 dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7)); 1559 dib0090_write_reg(state, 0x07, state->bb7 | (state->dc->i << 7));
988 1560
989 state->step = 0; 1561 state->step = 0;
990
991 state->min_adc_diff = 1023; 1562 state->min_adc_diff = 1023;
992
993 *tune_state = CT_TUNER_STEP_1; 1563 *tune_state = CT_TUNER_STEP_1;
994 ret = 50; 1564 ret = 50;
995 break; 1565 break;
996 1566
997 case CT_TUNER_STEP_1: 1567 case CT_TUNER_STEP_1:
998 dib0090_set_trim(state); 1568 dib0090_set_trim(state);
999
1000 *tune_state = CT_TUNER_STEP_2; 1569 *tune_state = CT_TUNER_STEP_2;
1001 break; 1570 break;
1002 1571
@@ -1007,7 +1576,13 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front
1007 break; 1576 break;
1008 1577
1009 case CT_TUNER_STEP_5: /* found an offset */ 1578 case CT_TUNER_STEP_5: /* found an offset */
1010 dprintk("FE%d: IQC read=%d, current=%x", state->fe->id, (u32) state->adc_diff, state->step); 1579 dprintk("adc_diff = %d, current step= %d", (u32) state->adc_diff, state->step);
1580 if (state->step == 0 && state->adc_diff < 0) {
1581 state->min_adc_diff = -1023;
1582 dprintk("Change of sign of the minimum adc diff");
1583 }
1584
1585 dprintk("adc_diff = %d, min_adc_diff = %d current_step = %d", state->adc_diff, state->min_adc_diff, state->step);
1011 1586
1012 /* first turn for this frequency */ 1587 /* first turn for this frequency */
1013 if (state->step == 0) { 1588 if (state->step == 0) {
@@ -1017,20 +1592,21 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front
1017 state->step = 0x10; 1592 state->step = 0x10;
1018 } 1593 }
1019 1594
1020 state->adc_diff = ABS(state->adc_diff); 1595 /* Look for a change of Sign in the Adc_diff.min_adc_diff is used to STORE the setp N-1 */
1021 1596 if ((state->adc_diff & 0x8000) == (state->min_adc_diff & 0x8000) && steps(state->step) < 15) {
1022 if (state->adc_diff < state->min_adc_diff && steps(state->step) < 15) { /* stop search when the delta to 0 is increasing */ 1597 /* stop search when the delta the sign is changing and Steps =15 and Step=0 is force for continuance */
1023 state->step++; 1598 state->step++;
1024 state->min_adc_diff = state->adc_diff; 1599 state->min_adc_diff = state->adc_diff; //min is used as N-1
1025 *tune_state = CT_TUNER_STEP_1; 1600 *tune_state = CT_TUNER_STEP_1;
1026 } else { 1601 } else {
1027
1028 /* the minimum was what we have seen in the step before */ 1602 /* the minimum was what we have seen in the step before */
1029 state->step--; 1603 if (ABS(state->adc_diff) > ABS(state->min_adc_diff)) { //Come back to the previous state since the delta was better
1030 dib0090_set_trim(state); 1604 dprintk("Since adc_diff N = %d > adc_diff step N-1 = %d, Come back one step", state->adc_diff, state->min_adc_diff);
1605 state->step--;
1606 }
1031 1607
1032 dprintk("FE%d: BB Offset Cal, BBreg=%hd,Offset=%hd,Value Set=%hd", state->fe->id, state->dc->addr, state->adc_diff, 1608 dib0090_set_trim(state);
1033 state->step); 1609 dprintk("BB Offset Cal, BBreg=%hd,Offset=%hd,Value Set=%hd", state->dc->addr, state->adc_diff, state->step);
1034 1610
1035 state->dc++; 1611 state->dc++;
1036 if (state->dc->addr == 0) /* done */ 1612 if (state->dc->addr == 0) /* done */
@@ -1042,10 +1618,10 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front
1042 break; 1618 break;
1043 1619
1044 case CT_TUNER_STEP_6: 1620 case CT_TUNER_STEP_6:
1045 dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008); 1621 dib0090_write_reg(state, 0x07, state->bb7 & ~0x0008); //Force the test bus to be off
1046 dib0090_write_reg(state, 0x1f, 0x7); 1622 dib0090_write_reg(state, 0x1f, 0x7);
1047 *tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */ 1623 *tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */
1048 state->reset &= ~0x1; 1624 state->calibrate &= ~DC_CAL;
1049 default: 1625 default:
1050 break; 1626 break;
1051 } 1627 }
@@ -1054,21 +1630,43 @@ static int dib0090_dc_offset_calibration(struct dib0090_state *state, enum front
1054 1630
1055static int dib0090_wbd_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state) 1631static int dib0090_wbd_calibration(struct dib0090_state *state, enum frontend_tune_state *tune_state)
1056{ 1632{
1633 u8 wbd_gain;
1634 const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
1635
1057 switch (*tune_state) { 1636 switch (*tune_state) {
1058 case CT_TUNER_START: 1637 case CT_TUNER_START:
1059 /* WBD-mode=log, Bias=2, Gain=6, Testmode=1, en=1, WBDMUX=1 */ 1638 while (state->current_rf / 1000 > wbd->max_freq)
1060 dib0090_write_reg(state, 0x10, 0xdb09 | (1 << 10)); 1639 wbd++;
1061 dib0090_write_reg(state, 0x24, EN_UHF & 0x0fff); 1640 if (wbd->wbd_gain != 0)
1641 wbd_gain = wbd->wbd_gain;
1642 else {
1643 wbd_gain = 4;
1644#if defined(CONFIG_BAND_LBAND) || defined(CONFIG_BAND_SBAND)
1645 if ((state->current_band == BAND_LBAND) || (state->current_band == BAND_SBAND))
1646 wbd_gain = 2;
1647#endif
1648 }
1062 1649
1650 if (wbd_gain == state->wbd_calibration_gain) { /* the WBD calibration has already been done */
1651 *tune_state = CT_TUNER_START;
1652 state->calibrate &= ~WBD_CAL;
1653 return 0;
1654 }
1655
1656 dib0090_write_reg(state, 0x10, 0x1b81 | (1 << 10) | (wbd_gain << 13) | (1 << 3)); // Force: WBD enable,gain to 4, mux to WBD
1657
1658 dib0090_write_reg(state, 0x24, ((EN_UHF & 0x0fff) | (1 << 1))); //Discard all LNA but crystal !!!
1063 *tune_state = CT_TUNER_STEP_0; 1659 *tune_state = CT_TUNER_STEP_0;
1660 state->wbd_calibration_gain = wbd_gain;
1064 return 90; /* wait for the WBDMUX to switch and for the ADC to sample */ 1661 return 90; /* wait for the WBDMUX to switch and for the ADC to sample */
1662
1065 case CT_TUNER_STEP_0: 1663 case CT_TUNER_STEP_0:
1066 state->wbd_offset = dib0090_read_reg(state, 0x1d); 1664 state->wbd_offset = dib0090_get_slow_adc_val(state);
1067 dprintk("WBD calibration offset = %d", state->wbd_offset); 1665 dprintk("WBD calibration offset = %d", state->wbd_offset);
1068
1069 *tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */ 1666 *tune_state = CT_TUNER_START; /* reset done -> real tuning can now begin */
1070 state->reset &= ~0x2; 1667 state->calibrate &= ~WBD_CAL;
1071 break; 1668 break;
1669
1072 default: 1670 default:
1073 break; 1671 break;
1074 } 1672 }
@@ -1092,6 +1690,15 @@ static void dib0090_set_bandwidth(struct dib0090_state *state)
1092 state->bb_1_def |= tmp; 1690 state->bb_1_def |= tmp;
1093 1691
1094 dib0090_write_reg(state, 0x01, state->bb_1_def); /* be sure that we have the right bb-filter */ 1692 dib0090_write_reg(state, 0x01, state->bb_1_def); /* be sure that we have the right bb-filter */
1693
1694 dib0090_write_reg(state, 0x03, 0x6008); /* = 0x6008 : vcm3_trim = 1 ; filter2_gm1_trim = 8 ; filter2_cutoff_freq = 0 */
1695 dib0090_write_reg(state, 0x04, 0x1); /* 0 = 1KHz ; 1 = 50Hz ; 2 = 150Hz ; 3 = 50KHz ; 4 = servo fast */
1696 if (state->identity.in_soc) {
1697 dib0090_write_reg(state, 0x05, 0x9bcf); /* attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 1 ; nc = 11 ; ext_gm_trim = 1 ; obuf_ibias_trim = 4 ; filter13_gm2_ibias_t = 15 */
1698 } else {
1699 dib0090_write_reg(state, 0x02, (5 << 11) | (8 << 6) | (22 & 0x3f)); /* 22 = cap_value */
1700 dib0090_write_reg(state, 0x05, 0xabcd); /* = 0xabcd : attenuator_ibias_tri = 2 ; input_stage_ibias_tr = 2 ; nc = 11 ; ext_gm_trim = 1 ; obuf_ibias_trim = 4 ; filter13_gm2_ibias_t = 13 */
1701 }
1095} 1702}
1096 1703
1097static const struct dib0090_pll dib0090_pll_table[] = { 1704static const struct dib0090_pll dib0090_pll_table[] = {
@@ -1180,6 +1787,266 @@ static const struct dib0090_tuning dib0090_tuning_table[] = {
1180#endif 1787#endif
1181}; 1788};
1182 1789
1790static const struct dib0090_tuning dib0090_p1g_tuning_table[] = {
1791 //max_freq, switch_trim, lna_tune, lna_bias, v2i, mix, load, tuner_enable;
1792#ifdef CONFIG_BAND_CBAND
1793 {170000, 4, 1, 0x820f, 0x300, 0x2d22, 0x82cb, EN_CAB}, // FM EN_CAB
1794#endif
1795#ifdef CONFIG_BAND_VHF
1796 {184000, 1, 1, 15, 0x300, 0x4d12, 0xb94e, EN_VHF}, // VHF EN_VHF
1797 {227000, 1, 3, 15, 0x300, 0x4d12, 0xb94e, EN_VHF}, // VHF EN_VHF
1798 {380000, 1, 7, 15, 0x300, 0x4d12, 0xb94e, EN_VHF}, // VHF EN_VHF
1799#endif
1800#ifdef CONFIG_BAND_UHF
1801 {510000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
1802 {540000, 2, 1, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
1803 {600000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
1804 {630000, 2, 4, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
1805 {680000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
1806 {720000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
1807 {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
1808#endif
1809#ifdef CONFIG_BAND_LBAND
1810 {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD}, // LBD EN_LBD
1811 {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD}, // LBD EN_LBD
1812 {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD}, // LBD EN_LBD
1813#endif
1814#ifdef CONFIG_BAND_SBAND
1815 {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD}, // SBD EN_SBD
1816 {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD}, // SBD EN_SBD
1817#endif
1818};
1819
1820static const struct dib0090_pll dib0090_p1g_pll_table[] = {
1821#ifdef CONFIG_BAND_CBAND
1822 {57000, 0, 11, 48, 6}, // CAB
1823 {70000, 1, 11, 48, 6}, // CAB
1824 {86000, 0, 10, 32, 4}, // CAB
1825 {105000, 1, 10, 32, 4}, // FM
1826 {115000, 0, 9, 24, 6}, // FM
1827 {140000, 1, 9, 24, 6}, // MID FM VHF
1828 {170000, 0, 8, 16, 4}, // MID FM VHF
1829#endif
1830#ifdef CONFIG_BAND_VHF
1831 {200000, 1, 8, 16, 4}, // VHF
1832 {230000, 0, 7, 12, 6}, // VHF
1833 {280000, 1, 7, 12, 6}, // MID VHF UHF
1834 {340000, 0, 6, 8, 4}, // MID VHF UHF
1835 {380000, 1, 6, 8, 4}, // MID VHF UHF
1836 {455000, 0, 5, 6, 6}, // MID VHF UHF
1837#endif
1838#ifdef CONFIG_BAND_UHF
1839 {580000, 1, 5, 6, 6}, // UHF
1840 {680000, 0, 4, 4, 4}, // UHF
1841 {860000, 1, 4, 4, 4}, // UHF
1842#endif
1843#ifdef CONFIG_BAND_LBAND
1844 {1800000, 1, 2, 2, 4}, // LBD
1845#endif
1846#ifdef CONFIG_BAND_SBAND
1847 {2900000, 0, 1, 1, 6}, // SBD
1848#endif
1849};
1850
1851static const struct dib0090_tuning dib0090_p1g_tuning_table_fm_vhf_on_cband[] = {
1852 //max_freq, switch_trim, lna_tune, lna_bias, v2i, mix, load, tuner_enable;
1853#ifdef CONFIG_BAND_CBAND
1854 {184000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB}, // FM EN_CAB // 0x8190 Good perf but higher current //0x4187 Low current
1855 {227000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB}, // FM EN_CAB
1856 {380000, 4, 3, 0x4187, 0x2c0, 0x2d22, 0x81cb, EN_CAB}, // FM EN_CAB
1857#endif
1858#ifdef CONFIG_BAND_UHF
1859 {520000, 2, 0, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
1860 {550000, 2, 2, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
1861 {650000, 2, 3, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
1862 {750000, 2, 5, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
1863 {850000, 2, 6, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
1864 {900000, 2, 7, 15, 0x300, 0x1d12, 0xb9ce, EN_UHF}, // UHF
1865#endif
1866#ifdef CONFIG_BAND_LBAND
1867 {1500000, 4, 0, 20, 0x300, 0x1912, 0x82c9, EN_LBD}, // LBD EN_LBD
1868 {1600000, 4, 1, 20, 0x300, 0x1912, 0x82c9, EN_LBD}, // LBD EN_LBD
1869 {1800000, 4, 3, 20, 0x300, 0x1912, 0x82c9, EN_LBD}, // LBD EN_LBD
1870#endif
1871#ifdef CONFIG_BAND_SBAND
1872 {2300000, 1, 4, 20, 0x300, 0x2d2A, 0x82c7, EN_SBD}, // SBD EN_SBD
1873 {2900000, 1, 7, 20, 0x280, 0x2deb, 0x8347, EN_SBD}, // SBD EN_SBD
1874#endif
1875};
1876
1877static const struct dib0090_tuning dib0090_tuning_table_cband_7090[] = {
1878 //max_freq, switch_trim, lna_tune, lna_bias, v2i, mix, load, tuner_enable;
1879#ifdef CONFIG_BAND_CBAND
1880 //{ 184000, 4, 3, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB }, // 0x81ce 0x8190 Good perf but higher current //0x4187 Low current
1881 {300000, 4, 3, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
1882 {380000, 4, 10, 0x018F, 0x2c0, 0x2d22, 0xb9ce, EN_CAB}, //0x4187
1883 {570000, 4, 10, 0x8190, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
1884 {858000, 4, 5, 0x8190, 0x2c0, 0x2d22, 0xb9ce, EN_CAB},
1885#endif
1886};
1887
1888static int dib0090_captrim_search(struct dib0090_state *state, enum frontend_tune_state *tune_state)
1889{
1890 int ret = 0;
1891 u16 lo4 = 0xe900;
1892
1893 s16 adc_target;
1894 u16 adc;
1895 s8 step_sign;
1896 u8 force_soft_search = 0;
1897
1898 if (state->identity.version == SOC_8090_P1G_11R1 || state->identity.version == SOC_8090_P1G_21R1)
1899 force_soft_search = 1;
1900
1901 if (*tune_state == CT_TUNER_START) {
1902 dprintk("Start Captrim search : %s", (force_soft_search == 1) ? "FORCE SOFT SEARCH" : "AUTO");
1903 dib0090_write_reg(state, 0x10, 0x2B1);
1904 dib0090_write_reg(state, 0x1e, 0x0032);
1905
1906 if (!state->tuner_is_tuned) {
1907 /* prepare a complete captrim */
1908 if (!state->identity.p1g || force_soft_search)
1909 state->step = state->captrim = state->fcaptrim = 64;
1910
1911 state->current_rf = state->rf_request;
1912 } else { /* we are already tuned to this frequency - the configuration is correct */
1913 if (!state->identity.p1g || force_soft_search) {
1914 /* do a minimal captrim even if the frequency has not changed */
1915 state->step = 4;
1916 state->captrim = state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7f;
1917 }
1918 }
1919 state->adc_diff = 3000; // start with a unreachable high number : only set for KROSUS < P1G */
1920 *tune_state = CT_TUNER_STEP_0;
1921
1922 } else if (*tune_state == CT_TUNER_STEP_0) {
1923 if (state->identity.p1g && !force_soft_search) {
1924 // 30MHz => Code 15 for the ration => 128us to lock. Giving approximately
1925 u8 ratio = 31; // (state->config->io.clock_khz / 1024 + 1) & 0x1f;
1926
1927 dib0090_write_reg(state, 0x40, (3 << 7) | (ratio << 2) | (1 << 1) | 1);
1928 dib0090_read_reg(state, 0x40);
1929 //dib0090_write_reg(state, 0x40, (3<<7) | ((((state->config->io.clock_khz >> 11)+1) & 0x1f)<<2) | (1<<1) | 1);
1930 ret = 50;
1931 } else {
1932 state->step /= 2;
1933 dib0090_write_reg(state, 0x18, lo4 | state->captrim);
1934
1935 if (state->identity.in_soc)
1936 ret = 25;
1937 }
1938 *tune_state = CT_TUNER_STEP_1;
1939
1940 } else if (*tune_state == CT_TUNER_STEP_1) {
1941 if (state->identity.p1g && !force_soft_search) {
1942 dib0090_write_reg(state, 0x40, 0x18c | (0 << 1) | 0);
1943 dib0090_read_reg(state, 0x40);
1944
1945 state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7F;
1946 dprintk("***Final Captrim= 0x%x", state->fcaptrim);
1947 *tune_state = CT_TUNER_STEP_3;
1948
1949 } else {
1950 /* MERGE for all krosus before P1G */
1951 adc = dib0090_get_slow_adc_val(state);
1952 dprintk("CAPTRIM=%d; ADC = %d (ADC) & %dmV", (u32) state->captrim, (u32) adc, (u32) (adc) * (u32) 1800 / (u32) 1024);
1953
1954 if (state->rest == 0 || state->identity.in_soc) { /* Just for 8090P SOCS where auto captrim HW bug : TO CHECK IN ACI for SOCS !!! if 400 for 8090p SOC => tune issue !!! */
1955 adc_target = 200;
1956 } else
1957 adc_target = 400;
1958
1959 if (adc >= adc_target) {
1960 adc -= adc_target;
1961 step_sign = -1;
1962 } else {
1963 adc = adc_target - adc;
1964 step_sign = 1;
1965 }
1966
1967 if (adc < state->adc_diff) {
1968 dprintk("CAPTRIM=%d is closer to target (%d/%d)", (u32) state->captrim, (u32) adc, (u32) state->adc_diff);
1969 state->adc_diff = adc;
1970 state->fcaptrim = state->captrim;
1971 //we could break here, to save time, if we reached a close-enough value
1972 //e.g.: if (state->adc_diff < 20)
1973 //break;
1974 }
1975
1976 state->captrim += step_sign * state->step;
1977 if (state->step >= 1)
1978 *tune_state = CT_TUNER_STEP_0;
1979 else
1980 *tune_state = CT_TUNER_STEP_2;
1981
1982 ret = 25; //LOLO changed from 15
1983 }
1984 } else if (*tune_state == CT_TUNER_STEP_2) { /* this step is only used by krosus < P1G */
1985 /*write the final cptrim config */
1986 dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim);
1987
1988 *tune_state = CT_TUNER_STEP_3;
1989
1990 } else if (*tune_state == CT_TUNER_STEP_3) {
1991 state->calibrate &= ~CAPTRIM_CAL;
1992 *tune_state = CT_TUNER_STEP_0;
1993 }
1994
1995 return ret;
1996}
1997
1998static int dib0090_get_temperature(struct dib0090_state *state, enum frontend_tune_state *tune_state)
1999{
2000 int ret = 15;
2001 s16 val;
2002
2003 //The assumption is that the AGC is not active
2004 switch (*tune_state) {
2005 case CT_TUNER_START:
2006 state->wbdmux = dib0090_read_reg(state, 0x10);
2007 dib0090_write_reg(state, 0x10, (state->wbdmux & ~(0xff << 3)) | (0x8 << 3)); //Move to the bias and clear the wbd enable
2008
2009 state->bias = dib0090_read_reg(state, 0x13);
2010 dib0090_write_reg(state, 0x13, state->bias | (0x3 << 8)); //Move to the Ref
2011
2012 *tune_state = CT_TUNER_STEP_0;
2013 /* wait for the WBDMUX to switch and for the ADC to sample */
2014 break;
2015
2016 case CT_TUNER_STEP_0:
2017 state->adc_diff = dib0090_get_slow_adc_val(state); // Get the value for the Ref
2018 dib0090_write_reg(state, 0x13, (state->bias & ~(0x3 << 8)) | (0x2 << 8)); //Move to the Ptat
2019 *tune_state = CT_TUNER_STEP_1;
2020 break;
2021
2022 case CT_TUNER_STEP_1:
2023 val = dib0090_get_slow_adc_val(state); // Get the value for the Ptat
2024 state->temperature = ((s16) ((val - state->adc_diff) * 180) >> 8) + 55; // +55 is defined as = -30deg
2025
2026 dprintk("temperature: %d C", state->temperature - 30);
2027
2028 *tune_state = CT_TUNER_STEP_2;
2029 break;
2030
2031 case CT_TUNER_STEP_2:
2032 //Reload the start values.
2033 dib0090_write_reg(state, 0x13, state->bias);
2034 dib0090_write_reg(state, 0x10, state->wbdmux); /* write back original WBDMUX */
2035
2036 *tune_state = CT_TUNER_START;
2037 state->calibrate &= ~TEMP_CAL;
2038 if (state->config->analog_output == 0)
2039 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14)); //Set the DataTX
2040
2041 break;
2042
2043 default:
2044 ret = 0;
2045 break;
2046 }
2047 return ret;
2048}
2049
1183#define WBD 0x781 /* 1 1 1 1 0000 0 0 1 */ 2050#define WBD 0x781 /* 1 1 1 1 0000 0 0 1 */
1184static int dib0090_tune(struct dvb_frontend *fe) 2051static int dib0090_tune(struct dvb_frontend *fe)
1185{ 2052{
@@ -1188,91 +2055,139 @@ static int dib0090_tune(struct dvb_frontend *fe)
1188 const struct dib0090_pll *pll = state->current_pll_table_index; 2055 const struct dib0090_pll *pll = state->current_pll_table_index;
1189 enum frontend_tune_state *tune_state = &state->tune_state; 2056 enum frontend_tune_state *tune_state = &state->tune_state;
1190 2057
1191 u32 rf; 2058 u16 lo5, lo6, Den, tmp;
1192 u16 lo4 = 0xe900, lo5, lo6, Den;
1193 u32 FBDiv, Rest, FREF, VCOF_kHz = 0; 2059 u32 FBDiv, Rest, FREF, VCOF_kHz = 0;
1194 u16 tmp, adc;
1195 int8_t step_sign;
1196 int ret = 10; /* 1ms is the default delay most of the time */ 2060 int ret = 10; /* 1ms is the default delay most of the time */
1197 u8 c, i; 2061 u8 c, i;
1198 2062
1199 state->current_band = (u8) BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000); 2063 /************************* VCO ***************************/
1200 rf = fe->dtv_property_cache.frequency / 1000 + (state->current_band ==
1201 BAND_UHF ? state->config->freq_offset_khz_uhf : state->config->freq_offset_khz_vhf);
1202 /* in any case we first need to do a reset if needed */
1203 if (state->reset & 0x1)
1204 return dib0090_dc_offset_calibration(state, tune_state);
1205 else if (state->reset & 0x2)
1206 return dib0090_wbd_calibration(state, tune_state);
1207
1208 /************************* VCO ***************************/
1209 /* Default values for FG */ 2064 /* Default values for FG */
1210 /* from these are needed : */ 2065 /* from these are needed : */
1211 /* Cp,HFdiv,VCOband,SD,Num,Den,FB and REFDiv */ 2066 /* Cp,HFdiv,VCOband,SD,Num,Den,FB and REFDiv */
1212 2067
1213#ifdef CONFIG_SYS_ISDBT 2068 /* in any case we first need to do a calibration if needed */
1214 if (state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1) 2069 if (*tune_state == CT_TUNER_START) {
1215 rf += 850; 2070 /* deactivate DataTX before some calibrations */
1216#endif 2071 if (state->calibrate & (DC_CAL | TEMP_CAL | WBD_CAL))
2072 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) & ~(1 << 14));
2073 else /* Activate DataTX in case a calibration has been done before */ if (state->config->analog_output == 0)
2074 dib0090_write_reg(state, 0x23, dib0090_read_reg(state, 0x23) | (1 << 14));
2075 }
1217 2076
1218 if (state->current_rf != rf) { 2077 if (state->calibrate & DC_CAL)
1219 state->tuner_is_tuned = 0; 2078 return dib0090_dc_offset_calibration(state, tune_state);
2079 else if (state->calibrate & WBD_CAL) {
2080 if (state->current_rf == 0) {
2081 state->current_rf = state->fe->dtv_property_cache.frequency / 1000;
2082 }
2083 return dib0090_wbd_calibration(state, tune_state);
2084 } else if (state->calibrate & TEMP_CAL)
2085 return dib0090_get_temperature(state, tune_state);
2086 else if (state->calibrate & CAPTRIM_CAL)
2087 return dib0090_captrim_search(state, tune_state);
1220 2088
1221 tune = dib0090_tuning_table; 2089 if (*tune_state == CT_TUNER_START) {
2090 /* if soc and AGC pwm control, disengage mux to be able to R/W access to 0x01 register to set the right filter (cutoff_freq_select) during the tune sequence, otherwise, SOC SERPAR error when accessing to 0x01 */
2091 if (state->config->use_pwm_agc && state->identity.in_soc) {
2092 tmp = dib0090_read_reg(state, 0x39);
2093 if ((tmp >> 10) & 0x1)
2094 dib0090_write_reg(state, 0x39, tmp & ~(1 << 10)); // disengage mux : en_mux_bb1 = 0
2095 }
1222 2096
1223 tmp = (state->revision >> 5) & 0x7; 2097 state->current_band = (u8) BAND_OF_FREQUENCY(state->fe->dtv_property_cache.frequency / 1000);
1224 if (tmp == 0x4 || tmp == 0x7) { 2098 state->rf_request =
1225 /* CBAND tuner version for VHF */ 2099 state->fe->dtv_property_cache.frequency / 1000 + (state->current_band ==
1226 if (state->current_band == BAND_FM || state->current_band == BAND_VHF) { 2100 BAND_UHF ? state->config->freq_offset_khz_uhf : state->config->
1227 /* Force CBAND */ 2101 freq_offset_khz_vhf);
1228 state->current_band = BAND_CBAND; 2102
1229 tune = dib0090_tuning_table_fm_vhf_on_cband; 2103 /* in ISDB-T 1seg we shift tuning frequency */
2104 if ((state->fe->dtv_property_cache.delivery_system == SYS_ISDBT && state->fe->dtv_property_cache.isdbt_sb_mode == 1
2105 && state->fe->dtv_property_cache.isdbt_partial_reception == 0)) {
2106 const struct dib0090_low_if_offset_table *LUT_offset = state->config->low_if;
2107 u8 found_offset = 0;
2108 u32 margin_khz = 100;
2109
2110 if (LUT_offset != NULL) {
2111 while (LUT_offset->RF_freq != 0xffff) {
2112 if (((state->rf_request > (LUT_offset->RF_freq - margin_khz))
2113 && (state->rf_request < (LUT_offset->RF_freq + margin_khz)))
2114 && LUT_offset->std == state->fe->dtv_property_cache.delivery_system) {
2115 state->rf_request += LUT_offset->offset_khz;
2116 found_offset = 1;
2117 break;
2118 }
2119 LUT_offset++;
2120 }
1230 } 2121 }
2122
2123 if (found_offset == 0)
2124 state->rf_request += 400;
1231 } 2125 }
2126 if (state->current_rf != state->rf_request || (state->current_standard != state->fe->dtv_property_cache.delivery_system)) {
2127 state->tuner_is_tuned = 0;
2128 state->current_rf = 0;
2129 state->current_standard = 0;
1232 2130
1233 pll = dib0090_pll_table; 2131 tune = dib0090_tuning_table;
1234 /* Look for the interval */ 2132 if (state->identity.p1g)
1235 while (rf > tune->max_freq) 2133 tune = dib0090_p1g_tuning_table;
1236 tune++;
1237 while (rf > pll->max_freq)
1238 pll++;
1239 state->current_tune_table_index = tune;
1240 state->current_pll_table_index = pll;
1241 }
1242 2134
1243 if (*tune_state == CT_TUNER_START) { 2135 tmp = (state->identity.version >> 5) & 0x7;
1244 2136
1245 if (state->tuner_is_tuned == 0) 2137 if (state->identity.in_soc) {
1246 state->current_rf = 0; 2138 if (state->config->force_cband_input) { /* Use the CBAND input for all band */
2139 if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAND_VHF
2140 || state->current_band & BAND_UHF) {
2141 state->current_band = BAND_CBAND;
2142 tune = dib0090_tuning_table_cband_7090;
2143 }
2144 } else { /* Use the CBAND input for all band under UHF */
2145 if (state->current_band & BAND_CBAND || state->current_band & BAND_FM || state->current_band & BAND_VHF) {
2146 state->current_band = BAND_CBAND;
2147 tune = dib0090_tuning_table_cband_7090;
2148 }
2149 }
2150 } else
2151 if (tmp == 0x4 || tmp == 0x7) {
2152 /* CBAND tuner version for VHF */
2153 if (state->current_band == BAND_FM || state->current_band == BAND_CBAND || state->current_band == BAND_VHF) {
2154 state->current_band = BAND_CBAND; /* Force CBAND */
2155
2156 tune = dib0090_tuning_table_fm_vhf_on_cband;
2157 if (state->identity.p1g)
2158 tune = dib0090_p1g_tuning_table_fm_vhf_on_cband;
2159 }
2160 }
1247 2161
1248 if (state->current_rf != rf) { 2162 pll = dib0090_pll_table;
2163 if (state->identity.p1g)
2164 pll = dib0090_p1g_pll_table;
1249 2165
1250 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim)); 2166 /* Look for the interval */
2167 while (state->rf_request > tune->max_freq)
2168 tune++;
2169 while (state->rf_request > pll->max_freq)
2170 pll++;
1251 2171
1252 /* external loop filter, otherwise: 2172 state->current_tune_table_index = tune;
1253 * lo5 = (0 << 15) | (0 << 12) | (0 << 11) | (3 << 9) | (4 << 6) | (3 << 4) | 4; 2173 state->current_pll_table_index = pll;
1254 * lo6 = 0x0e34 */
1255 if (pll->vco_band)
1256 lo5 = 0x049e;
1257 else if (state->config->analog_output)
1258 lo5 = 0x041d;
1259 else
1260 lo5 = 0x041c;
1261 2174
1262 lo5 |= (pll->hfdiv_code << 11) | (pll->vco_band << 7); /* bit 15 is the split to the slave, we do not do it here */ 2175 // select internal switch
1263 2176 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->switch_trim));
1264 if (!state->config->io.pll_int_loop_filt)
1265 lo6 = 0xff28;
1266 else
1267 lo6 = (state->config->io.pll_int_loop_filt << 3);
1268 2177
1269 VCOF_kHz = (pll->hfdiv * rf) * 2; 2178 // Find the VCO frequency in MHz
2179 VCOF_kHz = (pll->hfdiv * state->rf_request) * 2;
1270 2180
1271 FREF = state->config->io.clock_khz; 2181 FREF = state->config->io.clock_khz; // REFDIV is 1FREF Has to be as Close as possible to 10MHz
2182 if (state->config->fref_clock_ratio != 0)
2183 FREF /= state->config->fref_clock_ratio;
1272 2184
2185 // Determine the FB divider
2186 // The reference is 10MHz, Therefore the FBdivider is on the first digits
1273 FBDiv = (VCOF_kHz / pll->topresc / FREF); 2187 FBDiv = (VCOF_kHz / pll->topresc / FREF);
1274 Rest = (VCOF_kHz / pll->topresc) - FBDiv * FREF; 2188 Rest = (VCOF_kHz / pll->topresc) - FBDiv * FREF; //in kHz
1275 2189
2190 // Avoid Spurs in the loopfilter bandwidth
1276 if (Rest < LPF) 2191 if (Rest < LPF)
1277 Rest = 0; 2192 Rest = 0;
1278 else if (Rest < 2 * LPF) 2193 else if (Rest < 2 * LPF)
@@ -1280,147 +2195,155 @@ static int dib0090_tune(struct dvb_frontend *fe)
1280 else if (Rest > (FREF - LPF)) { 2195 else if (Rest > (FREF - LPF)) {
1281 Rest = 0; 2196 Rest = 0;
1282 FBDiv += 1; 2197 FBDiv += 1;
1283 } else if (Rest > (FREF - 2 * LPF)) 2198 } //Go to the next FB
2199 else if (Rest > (FREF - 2 * LPF))
1284 Rest = FREF - 2 * LPF; 2200 Rest = FREF - 2 * LPF;
1285 Rest = (Rest * 6528) / (FREF / 10); 2201 Rest = (Rest * 6528) / (FREF / 10);
2202 state->rest = Rest;
1286 2203
1287 Den = 1; 2204 /* external loop filter, otherwise:
2205 * lo5 = (0 << 15) | (0 << 12) | (0 << 11) | (3 << 9) | (4 << 6) | (3 << 4) | 4;
2206 * lo6 = 0x0e34 */
2207
2208 if (Rest == 0) {
2209 if (pll->vco_band)
2210 lo5 = 0x049f;
2211 //else if (state->config->analog_output)
2212 // lo5 = 0x041f;
2213 else
2214 lo5 = 0x041f;
2215 } else {
2216 if (pll->vco_band)
2217 lo5 = 0x049e;
2218 else if (state->config->analog_output)
2219 lo5 = 0x041d;
2220 else
2221 lo5 = 0x041c;
2222 }
2223
2224 if (state->identity.p1g) { /* Bias is done automatically in P1G */
2225 if (state->identity.in_soc) {
2226 if (state->identity.version == SOC_8090_P1G_11R1)
2227 lo5 = 0x46f;
2228 else
2229 lo5 = 0x42f;
2230 } else
2231 lo5 = 0x42c; //BIAS Lo set to 4 by default in case of the Captrim search does not take care of the VCO Bias
2232 }
2233
2234 lo5 |= (pll->hfdiv_code << 11) | (pll->vco_band << 7); /* bit 15 is the split to the slave, we do not do it here */
2235
2236 //Internal loop filter set...
2237 if (!state->config->io.pll_int_loop_filt) {
2238 if (state->identity.in_soc)
2239 lo6 = 0xff98;
2240 else if (state->identity.p1g || (Rest == 0))
2241 lo6 = 0xfff8;
2242 else
2243 lo6 = 0xff28;
2244 } else
2245 lo6 = (state->config->io.pll_int_loop_filt << 3); // take the loop filter value given by the layout
2246 //dprintk("lo6 = 0x%04x", (u32)lo6);
1288 2247
1289 dprintk(" ***** ******* Rest value = %d", Rest); 2248 Den = 1;
1290 2249
1291 if (Rest > 0) { 2250 if (Rest > 0) {
1292 if (state->config->analog_output) 2251 if (state->config->analog_output)
1293 lo6 |= (1 << 2) | 2; 2252 lo6 |= (1 << 2) | 2; //SigmaDelta and Dither
1294 else 2253 else {
1295 lo6 |= (1 << 2) | 1; 2254 if (state->identity.in_soc)
2255 lo6 |= (1 << 2) | 2; //SigmaDelta and Dither
2256 else
2257 lo6 |= (1 << 2) | 2; //SigmaDelta and Dither
2258 }
1296 Den = 255; 2259 Den = 255;
1297 } 2260 }
1298#ifdef CONFIG_BAND_SBAND 2261 // Now we have to define the Num and Denum
1299 if (state->current_band == BAND_SBAND) 2262 // LO1 gets the FBdiv
1300 lo6 &= 0xfffb;
1301#endif
1302
1303 dib0090_write_reg(state, 0x15, (u16) FBDiv); 2263 dib0090_write_reg(state, 0x15, (u16) FBDiv);
1304 2264 // LO2 gets the REFDiv
1305 dib0090_write_reg(state, 0x16, (Den << 8) | 1); 2265 if (state->config->fref_clock_ratio != 0)
1306 2266 dib0090_write_reg(state, 0x16, (Den << 8) | state->config->fref_clock_ratio);
2267 else
2268 dib0090_write_reg(state, 0x16, (Den << 8) | 1);
2269 // LO3 for the Numerator
1307 dib0090_write_reg(state, 0x17, (u16) Rest); 2270 dib0090_write_reg(state, 0x17, (u16) Rest);
1308 2271 // VCO and HF DIV
1309 dib0090_write_reg(state, 0x19, lo5); 2272 dib0090_write_reg(state, 0x19, lo5);
1310 2273 // SIGMA Delta
1311 dib0090_write_reg(state, 0x1c, lo6); 2274 dib0090_write_reg(state, 0x1c, lo6);
1312 2275
2276 // Check if the 0090 is analogged configured
2277 //Disable ADC and DigPLL =0xFF9F, 0xffbf for test purposes.
2278 //Enable The Outputs of the BB on DATA_Tx
1313 lo6 = tune->tuner_enable; 2279 lo6 = tune->tuner_enable;
1314 if (state->config->analog_output) 2280 if (state->config->analog_output)
1315 lo6 = (lo6 & 0xff9f) | 0x2; 2281 lo6 = (lo6 & 0xff9f) | 0x2;
1316 2282
1317 dib0090_write_reg(state, 0x24, lo6 | EN_LO 2283 dib0090_write_reg(state, 0x24, lo6 | EN_LO | state->config->use_pwm_agc * EN_CRYSTAL);
1318#ifdef CONFIG_DIB0090_USE_PWM_AGC
1319 | state->config->use_pwm_agc * EN_CRYSTAL
1320#endif
1321 );
1322
1323 state->current_rf = rf;
1324 2284
1325 /* prepare a complete captrim */
1326 state->step = state->captrim = state->fcaptrim = 64;
1327
1328 } else { /* we are already tuned to this frequency - the configuration is correct */
1329
1330 /* do a minimal captrim even if the frequency has not changed */
1331 state->step = 4;
1332 state->captrim = state->fcaptrim = dib0090_read_reg(state, 0x18) & 0x7f;
1333 } 2285 }
1334 state->adc_diff = 3000;
1335 2286
1336 dib0090_write_reg(state, 0x10, 0x2B1); 2287 state->current_rf = state->rf_request;
1337 2288 state->current_standard = state->fe->dtv_property_cache.delivery_system;
1338 dib0090_write_reg(state, 0x1e, 0x0032);
1339 2289
1340 ret = 20; 2290 ret = 20;
1341 *tune_state = CT_TUNER_STEP_1; 2291 state->calibrate = CAPTRIM_CAL; /* captrim serach now */
1342 } else if (*tune_state == CT_TUNER_STEP_0) { 2292 }
1343 /* nothing */
1344 } else if (*tune_state == CT_TUNER_STEP_1) {
1345 state->step /= 2;
1346 dib0090_write_reg(state, 0x18, lo4 | state->captrim);
1347 *tune_state = CT_TUNER_STEP_2;
1348 } else if (*tune_state == CT_TUNER_STEP_2) {
1349
1350 adc = dib0090_read_reg(state, 0x1d);
1351 dprintk("FE %d CAPTRIM=%d; ADC = %d (ADC) & %dmV", (u32) fe->id, (u32) state->captrim, (u32) adc,
1352 (u32) (adc) * (u32) 1800 / (u32) 1024);
1353
1354 if (adc >= 400) {
1355 adc -= 400;
1356 step_sign = -1;
1357 } else {
1358 adc = 400 - adc;
1359 step_sign = 1;
1360 }
1361 2293
1362 if (adc < state->adc_diff) { 2294 else if (*tune_state == CT_TUNER_STEP_0) { /* Warning : because of captrim cal, if you change this step, change it also in _cal.c file because it is the step following captrim cal state machine */
1363 dprintk("FE %d CAPTRIM=%d is closer to target (%d/%d)", (u32) fe->id, (u32) state->captrim, (u32) adc, (u32) state->adc_diff); 2295 const struct dib0090_wbd_slope *wbd = state->current_wbd_table;
1364 state->adc_diff = adc;
1365 state->fcaptrim = state->captrim;
1366 2296
1367 } 2297// if(!state->identity.p1g) {
2298 while (state->current_rf / 1000 > wbd->max_freq)
2299 wbd++;
2300// }
1368 2301
1369 state->captrim += step_sign * state->step; 2302 dib0090_write_reg(state, 0x1e, 0x07ff);
1370 if (state->step >= 1) 2303 dprintk("Final Captrim: %d", (u32) state->fcaptrim);
1371 *tune_state = CT_TUNER_STEP_1; 2304 dprintk("HFDIV code: %d", (u32) pll->hfdiv_code);
1372 else 2305 dprintk("VCO = %d", (u32) pll->vco_band);
1373 *tune_state = CT_TUNER_STEP_3; 2306 dprintk("VCOF in kHz: %d ((%d*%d) << 1))", (u32) ((pll->hfdiv * state->rf_request) * 2), (u32) pll->hfdiv, (u32) state->rf_request);
2307 dprintk("REFDIV: %d, FREF: %d", (u32) 1, (u32) state->config->io.clock_khz);
2308 dprintk("FBDIV: %d, Rest: %d", (u32) dib0090_read_reg(state, 0x15), (u32) dib0090_read_reg(state, 0x17));
2309 dprintk("Num: %d, Den: %d, SD: %d", (u32) dib0090_read_reg(state, 0x17), (u32) (dib0090_read_reg(state, 0x16) >> 8),
2310 (u32) dib0090_read_reg(state, 0x1c) & 0x3);
1374 2311
1375 ret = 15; 2312#define WBD 0x781 /* 1 1 1 1 0000 0 0 1 */
1376 } else if (*tune_state == CT_TUNER_STEP_3) { 2313 c = 4;
1377 /*write the final cptrim config */ 2314 i = 3; //wbdmux_bias
1378 dib0090_write_reg(state, 0x18, lo4 | state->fcaptrim);
1379 2315
1380#ifdef CONFIG_TUNER_DIB0090_CAPTRIM_MEMORY 2316 if (wbd->wbd_gain != 0) //&& !state->identity.p1g)
1381 state->memory[state->memory_index].cap = state->fcaptrim; 2317 c = wbd->wbd_gain;
1382#endif
1383 2318
1384 *tune_state = CT_TUNER_STEP_4; 2319 //Store wideband mux register.
1385 } else if (*tune_state == CT_TUNER_STEP_4) { 2320 state->wbdmux = (c << 13) | (i << 11) | (WBD | (state->config->use_pwm_agc << 1));
1386 dib0090_write_reg(state, 0x1e, 0x07ff); 2321 dib0090_write_reg(state, 0x10, state->wbdmux);
1387 2322
1388 dprintk("FE %d Final Captrim: %d", (u32) fe->id, (u32) state->fcaptrim); 2323 if ((tune->tuner_enable == EN_CAB) && state->identity.p1g) {
1389 dprintk("FE %d HFDIV code: %d", (u32) fe->id, (u32) pll->hfdiv_code); 2324 dprintk("P1G : The cable band is selected and lna_tune = %d", tune->lna_tune);
1390 dprintk("FE %d VCO = %d", (u32) fe->id, (u32) pll->vco_band); 2325 dib0090_write_reg(state, 0x09, tune->lna_bias);
1391 dprintk("FE %d VCOF in kHz: %d ((%d*%d) << 1))", (u32) fe->id, (u32) ((pll->hfdiv * rf) * 2), (u32) pll->hfdiv, (u32) rf); 2326 dib0090_write_reg(state, 0x0b, 0xb800 | (tune->lna_tune << 6) | (tune->switch_trim));
1392 dprintk("FE %d REFDIV: %d, FREF: %d", (u32) fe->id, (u32) 1, (u32) state->config->io.clock_khz); 2327 } else
1393 dprintk("FE %d FBDIV: %d, Rest: %d", (u32) fe->id, (u32) dib0090_read_reg(state, 0x15), (u32) dib0090_read_reg(state, 0x17)); 2328 dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | tune->lna_bias);
1394 dprintk("FE %d Num: %d, Den: %d, SD: %d", (u32) fe->id, (u32) dib0090_read_reg(state, 0x17),
1395 (u32) (dib0090_read_reg(state, 0x16) >> 8), (u32) dib0090_read_reg(state, 0x1c) & 0x3);
1396 2329
1397 c = 4;
1398 i = 3;
1399#if defined(CONFIG_BAND_LBAND) || defined(CONFIG_BAND_SBAND)
1400 if ((state->current_band == BAND_LBAND) || (state->current_band == BAND_SBAND)) {
1401 c = 2;
1402 i = 2;
1403 }
1404#endif
1405 dib0090_write_reg(state, 0x10, (c << 13) | (i << 11) | (WBD
1406#ifdef CONFIG_DIB0090_USE_PWM_AGC
1407 | (state->config->use_pwm_agc << 1)
1408#endif
1409 ));
1410 dib0090_write_reg(state, 0x09, (tune->lna_tune << 5) | (tune->lna_bias << 0));
1411 dib0090_write_reg(state, 0x0c, tune->v2i); 2330 dib0090_write_reg(state, 0x0c, tune->v2i);
1412 dib0090_write_reg(state, 0x0d, tune->mix); 2331 dib0090_write_reg(state, 0x0d, tune->mix);
1413 dib0090_write_reg(state, 0x0e, tune->load); 2332 dib0090_write_reg(state, 0x0e, tune->load);
2333 *tune_state = CT_TUNER_STEP_1;
1414 2334
1415 *tune_state = CT_TUNER_STEP_5; 2335 } else if (*tune_state == CT_TUNER_STEP_1) {
1416 } else if (*tune_state == CT_TUNER_STEP_5) {
1417
1418 /* initialize the lt gain register */ 2336 /* initialize the lt gain register */
1419 state->rf_lt_def = 0x7c00; 2337 state->rf_lt_def = 0x7c00;
1420 dib0090_write_reg(state, 0x0f, state->rf_lt_def); 2338 // dib0090_write_reg(state, 0x0f, state->rf_lt_def);
1421 2339
1422 dib0090_set_bandwidth(state); 2340 dib0090_set_bandwidth(state);
1423 state->tuner_is_tuned = 1; 2341 state->tuner_is_tuned = 1;
2342
2343// if(!state->identity.p1g)
2344 state->calibrate |= WBD_CAL; // TODO: only do the WBD calibration for new tune
2345//
2346 state->calibrate |= TEMP_CAL; // Force the Temperature to be remesured at next TUNE.
1424 *tune_state = CT_TUNER_STOP; 2347 *tune_state = CT_TUNER_STOP;
1425 } else 2348 } else
1426 ret = FE_CALLBACK_TIME_NEVER; 2349 ret = FE_CALLBACK_TIME_NEVER;
@@ -1440,6 +2363,7 @@ enum frontend_tune_state dib0090_get_tune_state(struct dvb_frontend *fe)
1440 2363
1441 return state->tune_state; 2364 return state->tune_state;
1442} 2365}
2366
1443EXPORT_SYMBOL(dib0090_get_tune_state); 2367EXPORT_SYMBOL(dib0090_get_tune_state);
1444 2368
1445int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state) 2369int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tune_state)
@@ -1449,6 +2373,7 @@ int dib0090_set_tune_state(struct dvb_frontend *fe, enum frontend_tune_state tun
1449 state->tune_state = tune_state; 2373 state->tune_state = tune_state;
1450 return 0; 2374 return 0;
1451} 2375}
2376
1452EXPORT_SYMBOL(dib0090_set_tune_state); 2377EXPORT_SYMBOL(dib0090_set_tune_state);
1453 2378
1454static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency) 2379static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency)
@@ -1462,7 +2387,7 @@ static int dib0090_get_frequency(struct dvb_frontend *fe, u32 * frequency)
1462static int dib0090_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *p) 2387static int dib0090_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *p)
1463{ 2388{
1464 struct dib0090_state *state = fe->tuner_priv; 2389 struct dib0090_state *state = fe->tuner_priv;
1465 uint32_t ret; 2390 u32 ret;
1466 2391
1467 state->tune_state = CT_TUNER_START; 2392 state->tune_state = CT_TUNER_START;
1468 2393
@@ -1492,6 +2417,29 @@ static const struct dvb_tuner_ops dib0090_ops = {
1492 .get_frequency = dib0090_get_frequency, 2417 .get_frequency = dib0090_get_frequency,
1493}; 2418};
1494 2419
2420static const struct dvb_tuner_ops dib0090_fw_ops = {
2421 .info = {
2422 .name = "DiBcom DiB0090",
2423 .frequency_min = 45000000,
2424 .frequency_max = 860000000,
2425 .frequency_step = 1000,
2426 },
2427 .release = dib0090_release,
2428
2429 .init = NULL,
2430 .sleep = NULL,
2431 .set_params = NULL,
2432 .get_frequency = NULL,
2433};
2434
2435static const struct dib0090_wbd_slope dib0090_wbd_table_default[] = {
2436 {470, 0, 250, 0, 100, 4},
2437 {860, 51, 866, 21, 375, 4},
2438 {1700, 0, 800, 0, 850, 4}, //LBAND Predefinition , to calibrate
2439 {2900, 0, 250, 0, 100, 6}, //SBAND Predefinition , NOT tested Yet
2440 {0xFFFF, 0, 0, 0, 0, 0},
2441};
2442
1495struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config) 2443struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config)
1496{ 2444{
1497 struct dib0090_state *st = kzalloc(sizeof(struct dib0090_state), GFP_KERNEL); 2445 struct dib0090_state *st = kzalloc(sizeof(struct dib0090_state), GFP_KERNEL);
@@ -1503,6 +2451,11 @@ struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapte
1503 st->fe = fe; 2451 st->fe = fe;
1504 fe->tuner_priv = st; 2452 fe->tuner_priv = st;
1505 2453
2454 if (config->wbd == NULL)
2455 st->current_wbd_table = dib0090_wbd_table_default;
2456 else
2457 st->current_wbd_table = config->wbd;
2458
1506 if (dib0090_reset(fe) != 0) 2459 if (dib0090_reset(fe) != 0)
1507 goto free_mem; 2460 goto free_mem;
1508 2461
@@ -1515,8 +2468,35 @@ struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapte
1515 fe->tuner_priv = NULL; 2468 fe->tuner_priv = NULL;
1516 return NULL; 2469 return NULL;
1517} 2470}
2471
1518EXPORT_SYMBOL(dib0090_register); 2472EXPORT_SYMBOL(dib0090_register);
1519 2473
2474struct dvb_frontend *dib0090_fw_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config)
2475{
2476 struct dib0090_fw_state *st = kzalloc(sizeof(struct dib0090_fw_state), GFP_KERNEL);
2477 if (st == NULL)
2478 return NULL;
2479
2480 st->config = config;
2481 st->i2c = i2c;
2482 st->fe = fe;
2483 fe->tuner_priv = st;
2484
2485 if (dib0090_fw_reset_digital(fe, st->config) != 0)
2486 goto free_mem;
2487
2488 dprintk("DiB0090 FW: successfully identified");
2489 memcpy(&fe->ops.tuner_ops, &dib0090_fw_ops, sizeof(struct dvb_tuner_ops));
2490
2491 return fe;
2492 free_mem:
2493 kfree(st);
2494 fe->tuner_priv = NULL;
2495 return NULL;
2496}
2497
2498EXPORT_SYMBOL(dib0090_fw_register);
2499
1520MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>"); 2500MODULE_AUTHOR("Patrick Boettcher <pboettcher@dibcom.fr>");
1521MODULE_AUTHOR("Olivier Grenie <olivier.grenie@dibcom.fr>"); 2501MODULE_AUTHOR("Olivier Grenie <olivier.grenie@dibcom.fr>");
1522MODULE_DESCRIPTION("Driver for the DiBcom 0090 base-band RF Tuner"); 2502MODULE_DESCRIPTION("Driver for the DiBcom 0090 base-band RF Tuner");
diff --git a/drivers/media/dvb/frontends/dib0090.h b/drivers/media/dvb/frontends/dib0090.h
index aa7711e88776..13d85244ec16 100644
--- a/drivers/media/dvb/frontends/dib0090.h
+++ b/drivers/media/dvb/frontends/dib0090.h
@@ -27,6 +27,21 @@ struct dib0090_io_config {
27 u16 pll_int_loop_filt; 27 u16 pll_int_loop_filt;
28}; 28};
29 29
30struct dib0090_wbd_slope {
31 u16 max_freq; /* for every frequency less than or equal to that field: this information is correct */
32 u16 slope_cold;
33 u16 offset_cold;
34 u16 slope_hot;
35 u16 offset_hot;
36 u8 wbd_gain;
37};
38
39struct dib0090_low_if_offset_table {
40 int std;
41 u32 RF_freq;
42 s32 offset_khz;
43};
44
30struct dib0090_config { 45struct dib0090_config {
31 struct dib0090_io_config io; 46 struct dib0090_io_config io;
32 int (*reset) (struct dvb_frontend *, int); 47 int (*reset) (struct dvb_frontend *, int);
@@ -47,10 +62,20 @@ struct dib0090_config {
47 u16 wbd_cband_offset; 62 u16 wbd_cband_offset;
48 u8 use_pwm_agc; 63 u8 use_pwm_agc;
49 u8 clkoutdrive; 64 u8 clkoutdrive;
65
66 u8 ls_cfg_pad_drv;
67 u8 data_tx_drv;
68
69 u8 in_soc;
70 const struct dib0090_low_if_offset_table *low_if;
71 u8 fref_clock_ratio;
72 u16 force_cband_input;
73 struct dib0090_wbd_slope *wbd;
50}; 74};
51 75
52#if defined(CONFIG_DVB_TUNER_DIB0090) || (defined(CONFIG_DVB_TUNER_DIB0090_MODULE) && defined(MODULE)) 76#if defined(CONFIG_DVB_TUNER_DIB0090) || (defined(CONFIG_DVB_TUNER_DIB0090_MODULE) && defined(MODULE))
53extern struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config); 77extern struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config);
78extern struct dvb_frontend *dib0090_fw_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, const struct dib0090_config *config);
54extern void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast); 79extern void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast);
55extern void dib0090_pwm_gain_reset(struct dvb_frontend *fe); 80extern void dib0090_pwm_gain_reset(struct dvb_frontend *fe);
56extern u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner); 81extern u16 dib0090_get_wbd_offset(struct dvb_frontend *tuner);
@@ -65,6 +90,12 @@ static inline struct dvb_frontend *dib0090_register(struct dvb_frontend *fe, str
65 return NULL; 90 return NULL;
66} 91}
67 92
93static inline struct dvb_frontend *dib0090_fw_register(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct dib0090_config *config)
94{
95 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
96 return NULL;
97}
98
68static inline void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast) 99static inline void dib0090_dcc_freq(struct dvb_frontend *fe, u8 fast)
69{ 100{
70 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__); 101 printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-16 08:33:58 -0500