diff options
author | Guillaume Audirac <guillaume.audirac@webag.fr> | 2010-05-06 08:07:04 -0400 |
---|---|---|
committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2010-08-02 14:35:39 -0400 |
commit | 82751f56791918f205e11ed78d139f043ed3e458 (patch) | |
tree | 3fcd186ac35a4edf9bd264c2d0a36cc8f35cf88c /drivers/media/dvb | |
parent | 10ea89d03f9850bbfbc9969f5ec79eae879b614f (diff) |
V4L/DVB: tda10048: clear the uncorrected packet registers when saturated
Use the register CLUNC to reset the CPTU registers (LSB & MSB) when they
saturate at 0xFFFF. Fixes as well a few register typos.
Signed-off-by: Guillaume Audirac <guillaume.audirac@webag.fr>
Signed-off-by: Steven Toth <stoth@kernellabs.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/dvb')
-rw-r--r-- | drivers/media/dvb/frontends/tda10048.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/drivers/media/dvb/frontends/tda10048.c b/drivers/media/dvb/frontends/tda10048.c index 9a0ba30ebb79..93f6a75c238e 100644 --- a/drivers/media/dvb/frontends/tda10048.c +++ b/drivers/media/dvb/frontends/tda10048.c | |||
@@ -50,8 +50,8 @@ | |||
50 | #define TDA10048_CONF_C4_1 0x1E | 50 | #define TDA10048_CONF_C4_1 0x1E |
51 | #define TDA10048_CONF_C4_2 0x1F | 51 | #define TDA10048_CONF_C4_2 0x1F |
52 | #define TDA10048_CODE_IN_RAM 0x20 | 52 | #define TDA10048_CODE_IN_RAM 0x20 |
53 | #define TDA10048_CHANNEL_INFO_1_R 0x22 | 53 | #define TDA10048_CHANNEL_INFO1_R 0x22 |
54 | #define TDA10048_CHANNEL_INFO_2_R 0x23 | 54 | #define TDA10048_CHANNEL_INFO2_R 0x23 |
55 | #define TDA10048_CHANNEL_INFO1 0x24 | 55 | #define TDA10048_CHANNEL_INFO1 0x24 |
56 | #define TDA10048_CHANNEL_INFO2 0x25 | 56 | #define TDA10048_CHANNEL_INFO2 0x25 |
57 | #define TDA10048_TIME_ERROR_R 0x26 | 57 | #define TDA10048_TIME_ERROR_R 0x26 |
@@ -64,8 +64,8 @@ | |||
64 | #define TDA10048_IT_STAT 0x32 | 64 | #define TDA10048_IT_STAT 0x32 |
65 | #define TDA10048_DSP_AD_LSB 0x3C | 65 | #define TDA10048_DSP_AD_LSB 0x3C |
66 | #define TDA10048_DSP_AD_MSB 0x3D | 66 | #define TDA10048_DSP_AD_MSB 0x3D |
67 | #define TDA10048_DSP_REF_LSB 0x3E | 67 | #define TDA10048_DSP_REG_LSB 0x3E |
68 | #define TDA10048_DSP_REF_MSB 0x3F | 68 | #define TDA10048_DSP_REG_MSB 0x3F |
69 | #define TDA10048_CONF_TRISTATE1 0x44 | 69 | #define TDA10048_CONF_TRISTATE1 0x44 |
70 | #define TDA10048_CONF_TRISTATE2 0x45 | 70 | #define TDA10048_CONF_TRISTATE2 0x45 |
71 | #define TDA10048_CONF_POLARITY 0x46 | 71 | #define TDA10048_CONF_POLARITY 0x46 |
@@ -1033,6 +1033,9 @@ static int tda10048_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) | |||
1033 | 1033 | ||
1034 | *ucblocks = tda10048_readreg(state, TDA10048_UNCOR_CPT_MSB) << 8 | | 1034 | *ucblocks = tda10048_readreg(state, TDA10048_UNCOR_CPT_MSB) << 8 | |
1035 | tda10048_readreg(state, TDA10048_UNCOR_CPT_LSB); | 1035 | tda10048_readreg(state, TDA10048_UNCOR_CPT_LSB); |
1036 | /* clear the uncorrected TS packets counter when saturated */ | ||
1037 | if (*ucblocks == 0xFFFF) | ||
1038 | tda10048_writereg(state, TDA10048_UNCOR_CTRL, 0x80); | ||
1036 | 1039 | ||
1037 | return 0; | 1040 | return 0; |
1038 | } | 1041 | } |