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authorMarko Schluessler <marco@lordzodiac.de>2008-10-23 17:16:40 -0400
committerMauro Carvalho Chehab <mchehab@redhat.com>2008-12-29 14:53:16 -0500
commit9e0dc6606a4f26a70cede6bf181cbff21f4c5477 (patch)
tree302e093dd0b14aa6d2b8278598509842e0547106 /drivers/media/dvb/ttpci/budget-ci.c
parentc7d85a2debb07af67c4915c972a352b68cda9022 (diff)
V4L/DVB (9398): Initial support for the Technotrend TT S2 3200
Signed-off-by: Marko Schluessler <marco@lordzodiac.de> Signed-off-by: Manu Abraham <manu@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/dvb/ttpci/budget-ci.c')
-rw-r--r--drivers/media/dvb/ttpci/budget-ci.c511
1 files changed, 511 insertions, 0 deletions
diff --git a/drivers/media/dvb/ttpci/budget-ci.c b/drivers/media/dvb/ttpci/budget-ci.c
index 0a5aad45435d..d179095bc27d 100644
--- a/drivers/media/dvb/ttpci/budget-ci.c
+++ b/drivers/media/dvb/ttpci/budget-ci.c
@@ -43,6 +43,9 @@
43#include "stv0299.h" 43#include "stv0299.h"
44#include "stv0297.h" 44#include "stv0297.h"
45#include "tda1004x.h" 45#include "tda1004x.h"
46#include "stb0899_drv.h"
47#include "stb0899_reg.h"
48#include "stb6100.h"
46#include "lnbp21.h" 49#include "lnbp21.h"
47#include "bsbe1.h" 50#include "bsbe1.h"
48#include "bsru6.h" 51#include "bsru6.h"
@@ -1071,7 +1074,493 @@ static struct tda10023_config tda10023_config = {
1071 .deltaf = 0xa511, 1074 .deltaf = 0xa511,
1072}; 1075};
1073 1076
1077/* TT S2-3200 DVB-S (STB0899) Inittab */
1078static const struct stb0899_s1_reg tt3200_stb0899_s1_init_1[] = {
1079
1080// 0x0000000b , /* SYSREG */
1081 { STB0899_DEV_ID , 0x81 },
1082 { STB0899_DISCNTRL1 , 0x32 },
1083 { STB0899_DISCNTRL2 , 0x80 },
1084 { STB0899_DISRX_ST0 , 0x04 },
1085 { STB0899_DISRX_ST1 , 0x00 },
1086 { STB0899_DISPARITY , 0x00 },
1087 { STB0899_DISFIFO , 0x00 },
1088 { STB0899_DISSTATUS , 0x20 },
1089 { STB0899_DISF22 , 0x8c },
1090 { STB0899_DISF22RX , 0x9a },
1091 //SYSREG ?
1092 { STB0899_ACRPRESC , 0x11 },
1093 { STB0899_ACRDIV1 , 0x0a },
1094 { STB0899_ACRDIV2 , 0x05 },
1095 { STB0899_DACR1 , 0x00 },
1096 { STB0899_DACR2 , 0x00 },
1097 { STB0899_OUTCFG , 0x00 },
1098 { STB0899_MODECFG , 0x00 },
1099 { STB0899_IRQSTATUS_3 , 0x30 },
1100 { STB0899_IRQSTATUS_2 , 0x00 },
1101 { STB0899_IRQSTATUS_1 , 0x00 },
1102 { STB0899_IRQSTATUS_0 , 0x00 },
1103 { STB0899_IRQMSK_3 , 0xf3 },
1104 { STB0899_IRQMSK_2 , 0xfc },
1105 { STB0899_IRQMSK_1 , 0xff },
1106 { STB0899_IRQMSK_0 , 0xff },
1107 { STB0899_IRQCFG , 0x00 },
1108 { STB0899_I2CCFG , 0x88 },
1109 { STB0899_I2CRPT , 0x5c },
1110 { STB0899_IOPVALUE5 , 0x00 },
1111 { STB0899_IOPVALUE4 , 0x20 },
1112 { STB0899_IOPVALUE3 , 0xc9 },
1113 { STB0899_IOPVALUE2 , 0x90 },
1114 { STB0899_IOPVALUE1 , 0x40 },
1115 { STB0899_IOPVALUE0 , 0x00 },
1116 { STB0899_GPIO00CFG , 0x82 },
1117 { STB0899_GPIO01CFG , 0x82 },
1118 { STB0899_GPIO02CFG , 0x82 },
1119 { STB0899_GPIO03CFG , 0x82 },
1120 { STB0899_GPIO04CFG , 0x82 },
1121 { STB0899_GPIO05CFG , 0x82 },
1122 { STB0899_GPIO06CFG , 0x82 },
1123 { STB0899_GPIO07CFG , 0x82 },
1124 { STB0899_GPIO08CFG , 0x82 },
1125 { STB0899_GPIO09CFG , 0x82 },
1126 { STB0899_GPIO10CFG , 0x82 },
1127 { STB0899_GPIO11CFG , 0x82 },
1128 { STB0899_GPIO12CFG , 0x82 },
1129 { STB0899_GPIO13CFG , 0x82 },
1130 { STB0899_GPIO14CFG , 0x82 },
1131 { STB0899_GPIO15CFG , 0x82 },
1132 { STB0899_GPIO16CFG , 0x82 },
1133 { STB0899_GPIO17CFG , 0x82 },
1134 { STB0899_GPIO18CFG , 0x82 },
1135 { STB0899_GPIO19CFG , 0x82 },
1136 { STB0899_GPIO20CFG , 0x82 },
1137 { STB0899_SDATCFG , 0xb8 },
1138 { STB0899_SCLTCFG , 0xba },
1139 { STB0899_AGCRFCFG , 0x1c }, // 0x11
1140 { STB0899_GPIO22 , 0x82 }, // AGCBB2CFG
1141 { STB0899_GPIO21 , 0x91 }, // AGCBB1CFG
1142 { STB0899_DIRCLKCFG , 0x82 },
1143 { STB0899_CLKOUT27CFG , 0x7e },
1144 { STB0899_STDBYCFG , 0x82 },
1145 { STB0899_CS0CFG , 0x82 },
1146 { STB0899_CS1CFG , 0x82 },
1147 { STB0899_DISEQCOCFG , 0x20 },
1148 { STB0899_GPIO32CFG , 0x82 },
1149 { STB0899_GPIO33CFG , 0x82 },
1150 { STB0899_GPIO34CFG , 0x82 },
1151 { STB0899_GPIO35CFG , 0x82 },
1152 { STB0899_GPIO36CFG , 0x82 },
1153 { STB0899_GPIO37CFG , 0x82 },
1154 { STB0899_GPIO38CFG , 0x82 },
1155 { STB0899_GPIO39CFG , 0x82 },
1156 { STB0899_NCOARSE , 0x15 }, // 0x15 = 27 Mhz Clock, F/3 = 198MHz, F/6 = 99MHz
1157 { STB0899_SYNTCTRL , 0x02 }, // 0x00 = CLK from CLKI, 0x02 = CLK from XTALI
1158 { STB0899_FILTCTRL , 0x00 },
1159 { STB0899_SYSCTRL , 0x00 },
1160 { STB0899_STOPCLK1 , 0x20 },
1161 { STB0899_STOPCLK2 , 0x00 },
1162 { STB0899_INTBUFSTATUS , 0x00 },
1163 { STB0899_INTBUFCTRL , 0x0a },
1164 { 0xffff , 0xff },
1165};
1166
1167static const struct stb0899_s2_reg tt3200_stb0899_s2_init_2[] = {
1168
1169 { STB0899_OFF0_DMD_STATUS , STB0899_BASE_DMD_STATUS , 0x00000103 }, /* DMDSTATUS */
1170 { STB0899_OFF0_CRL_FREQ , STB0899_BASE_CRL_FREQ , 0x3ed1da56 }, /* CRLFREQ */
1171 { STB0899_OFF0_BTR_FREQ , STB0899_BASE_BTR_FREQ , 0x00004000 }, /* BTRFREQ */
1172 { STB0899_OFF0_IF_AGC_GAIN , STB0899_BASE_IF_AGC_GAIN , 0x00002ade }, /* IFAGCGAIN */
1173 { STB0899_OFF0_BB_AGC_GAIN , STB0899_BASE_BB_AGC_GAIN , 0x000001bc }, /* BBAGCGAIN */
1174 { STB0899_OFF0_DC_OFFSET , STB0899_BASE_DC_OFFSET , 0x00000200 }, /* DCOFFSET */
1175 { STB0899_OFF0_DMD_CNTRL , STB0899_BASE_DMD_CNTRL , 0x0000000f }, /* DMDCNTRL */
1176
1177 { STB0899_OFF0_IF_AGC_CNTRL , STB0899_BASE_IF_AGC_CNTRL , 0x03fb4a20 }, /* IFAGCCNTRL */
1178 { STB0899_OFF0_BB_AGC_CNTRL , STB0899_BASE_BB_AGC_CNTRL , 0x00200c97 }, /* BBAGCCNTRL */
1179
1180 { STB0899_OFF0_CRL_CNTRL , STB0899_BASE_CRL_CNTRL , 0x00000016 }, /* CRLCNTRL */
1181 { STB0899_OFF0_CRL_PHS_INIT , STB0899_BASE_CRL_PHS_INIT , 0x00000000 }, /* CRLPHSINIT */
1182 { STB0899_OFF0_CRL_FREQ_INIT , STB0899_BASE_CRL_FREQ_INIT , 0x00000000 }, /* CRLFREQINIT */
1183 { STB0899_OFF0_CRL_LOOP_GAIN , STB0899_BASE_CRL_LOOP_GAIN , 0x00000000 }, /* CRLLOOPGAIN */
1184 { STB0899_OFF0_CRL_NOM_FREQ , STB0899_BASE_CRL_NOM_FREQ , 0x3ed097b6 }, /* CRLNOMFREQ */
1185 { STB0899_OFF0_CRL_SWP_RATE , STB0899_BASE_CRL_SWP_RATE , 0x00000000 }, /* CRLSWPRATE */
1186 { STB0899_OFF0_CRL_MAX_SWP , STB0899_BASE_CRL_MAX_SWP , 0x00000000 }, /* CRLMAXSWP */
1187 { STB0899_OFF0_CRL_LK_CNTRL , STB0899_BASE_CRL_LK_CNTRL , 0x0f6cdc01 }, /* CRLLKCNTRL */
1188 { STB0899_OFF0_DECIM_CNTRL , STB0899_BASE_DECIM_CNTRL , 0x00000000 }, /* DECIMCNTRL */
1189 { STB0899_OFF0_BTR_CNTRL , STB0899_BASE_BTR_CNTRL , 0x00003993 }, /* BTRCNTRL */
1190 { STB0899_OFF0_BTR_LOOP_GAIN , STB0899_BASE_BTR_LOOP_GAIN , 0x000d3c6f }, /* BTRLOOPGAIN */
1191 { STB0899_OFF0_BTR_PHS_INIT , STB0899_BASE_BTR_PHS_INIT , 0x00000000 }, /* BTRPHSINIT */
1192 { STB0899_OFF0_BTR_FREQ_INIT , STB0899_BASE_BTR_FREQ_INIT , 0x00000000 }, /* BTRFREQINIT */
1193 { STB0899_OFF0_BTR_NOM_FREQ , STB0899_BASE_BTR_NOM_FREQ , 0x0238e38e }, /* BTRNOMFREQ */
1194 { STB0899_OFF0_BTR_LK_CNTRL , STB0899_BASE_BTR_LK_CNTRL , 0x00000000 }, /* BTRLKCNTRL */
1195 { STB0899_OFF0_DECN_CNTRL , STB0899_BASE_DECN_CNTRL , 0x00000000 }, /* DECNCNTRL */
1196 { STB0899_OFF0_TP_CNTRL , STB0899_BASE_TP_CNTRL , 0x00000000 }, /* TPCNTRL */
1197 { STB0899_OFF0_TP_BUF_STATUS , STB0899_BASE_TP_BUF_STATUS , 0x00000000 }, /* TPBUFSTATUS */
1198 { STB0899_OFF0_DC_ESTIM , STB0899_BASE_DC_ESTIM , 0x00000000 }, /* DCESTIM */
1199 { STB0899_OFF0_FLL_CNTRL , STB0899_BASE_FLL_CNTRL , 0x00000000 }, /* FLLCNTRL */
1200 { STB0899_OFF0_FLL_FREQ_WD , STB0899_BASE_FLL_FREQ_WD , 0x40070000 }, /* FLLFREQWD */
1201 { STB0899_OFF0_ANTI_ALIAS_SEL , STB0899_BASE_ANTI_ALIAS_SEL , 0x00000001 }, /* ANTIALIASSEL */
1202 { STB0899_OFF0_RRC_ALPHA , STB0899_BASE_RRC_ALPHA , 0x00000002 }, /* RRCALPHA */
1203 { STB0899_OFF0_DC_ADAPT_LSHFT , STB0899_BASE_DC_ADAPT_LSHFT , 0x00000000 }, /* DCADAPTISHFT */
1204 { STB0899_OFF0_IMB_OFFSET , STB0899_BASE_IMB_OFFSET , 0x0000fe01 }, /* IMBOFFSET */
1205 { STB0899_OFF0_IMB_ESTIMATE , STB0899_BASE_IMB_ESTIMATE , 0x00000000 }, /* IMBESTIMATE */
1206 { STB0899_OFF0_IMB_CNTRL , STB0899_BASE_IMB_CNTRL , 0x00000001 }, /* IMBCNTRL */
1207 { STB0899_OFF0_IF_AGC_CNTRL2 , STB0899_BASE_IF_AGC_CNTRL2 , 0x00005007 }, /* IFAGCCNTRL2 */
1208 { STB0899_OFF0_DMD_CNTRL2 , STB0899_BASE_DMD_CNTRL2 , 0x00000002 }, /* DMDCNTRL2 */
1209 { STB0899_OFF0_TP_BUFFER , STB0899_BASE_TP_BUFFER , 0x00000000 }, /* TPBUFFER */
1210 { STB0899_OFF0_TP_BUFFER1 , STB0899_BASE_TP_BUFFER1 , 0x00000000 }, /* TPBUFFER1 */
1211 { STB0899_OFF0_TP_BUFFER2 , STB0899_BASE_TP_BUFFER2 , 0x00000000 }, /* TPBUFFER2 */
1212 { STB0899_OFF0_TP_BUFFER3 , STB0899_BASE_TP_BUFFER3 , 0x00000000 }, /* TPBUFFER3 */
1213 { STB0899_OFF0_TP_BUFFER4 , STB0899_BASE_TP_BUFFER4 , 0x00000000 }, /* TPBUFFER4 */
1214 { STB0899_OFF0_TP_BUFFER5 , STB0899_BASE_TP_BUFFER5 , 0x00000000 }, /* TPBUFFER5 */
1215 { STB0899_OFF0_TP_BUFFER6 , STB0899_BASE_TP_BUFFER6 , 0x00000000 }, /* TPBUFFER6 */
1216 { STB0899_OFF0_TP_BUFFER7 , STB0899_BASE_TP_BUFFER7 , 0x00000000 }, /* TPBUFFER7 */
1217 { STB0899_OFF0_TP_BUFFER8 , STB0899_BASE_TP_BUFFER8 , 0x00000000 }, /* TPBUFFER8 */
1218 { STB0899_OFF0_TP_BUFFER9 , STB0899_BASE_TP_BUFFER9 , 0x00000000 }, /* TPBUFFER9 */
1219 { STB0899_OFF0_TP_BUFFER10 , STB0899_BASE_TP_BUFFER10 , 0x00000000 }, /* TPBUFFER10 */
1220 { STB0899_OFF0_TP_BUFFER11 , STB0899_BASE_TP_BUFFER11 , 0x00000000 }, /* TPBUFFER11 */
1221 { STB0899_OFF0_TP_BUFFER12 , STB0899_BASE_TP_BUFFER12 , 0x00000000 }, /* TPBUFFER12 */
1222 { STB0899_OFF0_TP_BUFFER13 , STB0899_BASE_TP_BUFFER13 , 0x00000000 }, /* TPBUFFER13 */
1223 { STB0899_OFF0_TP_BUFFER14 , STB0899_BASE_TP_BUFFER14 , 0x00000000 }, /* TPBUFFER14 */
1224 { STB0899_OFF0_TP_BUFFER15 , STB0899_BASE_TP_BUFFER15 , 0x00000000 }, /* TPBUFFER15 */
1225 { STB0899_OFF0_TP_BUFFER16 , STB0899_BASE_TP_BUFFER16 , 0x0000ff00 }, /* TPBUFFER16 */
1226 { STB0899_OFF0_TP_BUFFER17 , STB0899_BASE_TP_BUFFER17 , 0x00000100 }, /* TPBUFFER17 */
1227 { STB0899_OFF0_TP_BUFFER18 , STB0899_BASE_TP_BUFFER18 , 0x0000fe01 }, /* TPBUFFER18 */
1228 { STB0899_OFF0_TP_BUFFER19 , STB0899_BASE_TP_BUFFER19 , 0x000004fe }, /* TPBUFFER19 */
1229 { STB0899_OFF0_TP_BUFFER20 , STB0899_BASE_TP_BUFFER20 , 0x0000cfe7 }, /* TPBUFFER20 */
1230 { STB0899_OFF0_TP_BUFFER21 , STB0899_BASE_TP_BUFFER21 , 0x0000bec6 }, /* TPBUFFER21 */
1231 { STB0899_OFF0_TP_BUFFER22 , STB0899_BASE_TP_BUFFER22 , 0x0000c2bf }, /* TPBUFFER22 */
1232 { STB0899_OFF0_TP_BUFFER23 , STB0899_BASE_TP_BUFFER23 , 0x0000c1c1 }, /* TPBUFFER23 */
1233 { STB0899_OFF0_TP_BUFFER24 , STB0899_BASE_TP_BUFFER24 , 0x0000c1c1 }, /* TPBUFFER24 */
1234 { STB0899_OFF0_TP_BUFFER25 , STB0899_BASE_TP_BUFFER25 , 0x0000c1c1 }, /* TPBUFFER25 */
1235 { STB0899_OFF0_TP_BUFFER26 , STB0899_BASE_TP_BUFFER26 , 0x0000c1c1 }, /* TPBUFFER26 */
1236 { STB0899_OFF0_TP_BUFFER27 , STB0899_BASE_TP_BUFFER27 , 0x0000c1c0 }, /* TPBUFFER27 */
1237 { STB0899_OFF0_TP_BUFFER28 , STB0899_BASE_TP_BUFFER28 , 0x0000c0c0 }, /* TPBUFFER28 */
1238 { STB0899_OFF0_TP_BUFFER29 , STB0899_BASE_TP_BUFFER29 , 0x0000c1c1 }, /* TPBUFFER29 */
1239 { STB0899_OFF0_TP_BUFFER30 , STB0899_BASE_TP_BUFFER30 , 0x0000c1c1 }, /* TPBUFFER30 */
1240 { STB0899_OFF0_TP_BUFFER31 , STB0899_BASE_TP_BUFFER31 , 0x0000c0c1 }, /* TPBUFFER31 */
1241 { STB0899_OFF0_TP_BUFFER32 , STB0899_BASE_TP_BUFFER32 , 0x0000c0c1 }, /* TPBUFFER32 */
1242 { STB0899_OFF0_TP_BUFFER33 , STB0899_BASE_TP_BUFFER33 , 0x0000c1c1 }, /* TPBUFFER33 */
1243 { STB0899_OFF0_TP_BUFFER34 , STB0899_BASE_TP_BUFFER34 , 0x0000c1c1 }, /* TPBUFFER34 */
1244 { STB0899_OFF0_TP_BUFFER35 , STB0899_BASE_TP_BUFFER35 , 0x0000c0c1 }, /* TPBUFFER35 */
1245 { STB0899_OFF0_TP_BUFFER36 , STB0899_BASE_TP_BUFFER36 , 0x0000c1c1 }, /* TPBUFFER36 */
1246 { STB0899_OFF0_TP_BUFFER37 , STB0899_BASE_TP_BUFFER37 , 0x0000c0c1 }, /* TPBUFFER37 */
1247 { STB0899_OFF0_TP_BUFFER38 , STB0899_BASE_TP_BUFFER38 , 0x0000c1c1 }, /* TPBUFFER38 */
1248 { STB0899_OFF0_TP_BUFFER39 , STB0899_BASE_TP_BUFFER39 , 0x0000c0c0 }, /* TPBUFFER39 */
1249 { STB0899_OFF0_TP_BUFFER40 , STB0899_BASE_TP_BUFFER40 , 0x0000c1c0 }, /* TPBUFFER40 */
1250 { STB0899_OFF0_TP_BUFFER41 , STB0899_BASE_TP_BUFFER41 , 0x0000c1c1 }, /* TPBUFFER41 */
1251 { STB0899_OFF0_TP_BUFFER42 , STB0899_BASE_TP_BUFFER42 , 0x0000c0c0 }, /* TPBUFFER42 */
1252 { STB0899_OFF0_TP_BUFFER43 , STB0899_BASE_TP_BUFFER43 , 0x0000c1c0 }, /* TPBUFFER43 */
1253 { STB0899_OFF0_TP_BUFFER44 , STB0899_BASE_TP_BUFFER44 , 0x0000c0c1 }, /* TPBUFFER44 */
1254 { STB0899_OFF0_TP_BUFFER45 , STB0899_BASE_TP_BUFFER45 , 0x0000c1be }, /* TPBUFFER45 */
1255 { STB0899_OFF0_TP_BUFFER46 , STB0899_BASE_TP_BUFFER46 , 0x0000c1c9 }, /* TPBUFFER46 */
1256 { STB0899_OFF0_TP_BUFFER47 , STB0899_BASE_TP_BUFFER47 , 0x0000c0da }, /* TPBUFFER47 */
1257 { STB0899_OFF0_TP_BUFFER48 , STB0899_BASE_TP_BUFFER48 , 0x0000c0ba }, /* TPBUFFER48 */
1258 { STB0899_OFF0_TP_BUFFER49 , STB0899_BASE_TP_BUFFER49 , 0x0000c1c4 }, /* TPBUFFER49 */
1259 { STB0899_OFF0_TP_BUFFER50 , STB0899_BASE_TP_BUFFER50 , 0x0000c1bf }, /* TPBUFFER50 */
1260 { STB0899_OFF0_TP_BUFFER51 , STB0899_BASE_TP_BUFFER51 , 0x0000c0c1 }, /* TPBUFFER51 */
1261 { STB0899_OFF0_TP_BUFFER52 , STB0899_BASE_TP_BUFFER52 , 0x0000c1c0 }, /* TPBUFFER52 */
1262 { STB0899_OFF0_TP_BUFFER53 , STB0899_BASE_TP_BUFFER53 , 0x0000c0c1 }, /* TPBUFFER53 */
1263 { STB0899_OFF0_TP_BUFFER54 , STB0899_BASE_TP_BUFFER54 , 0x0000c1c1 }, /* TPBUFFER54 */
1264 { STB0899_OFF0_TP_BUFFER55 , STB0899_BASE_TP_BUFFER55 , 0x0000c1c1 }, /* TPBUFFER55 */
1265 { STB0899_OFF0_TP_BUFFER56 , STB0899_BASE_TP_BUFFER56 , 0x0000c1c1 }, /* TPBUFFER56 */
1266 { STB0899_OFF0_TP_BUFFER57 , STB0899_BASE_TP_BUFFER57 , 0x0000c1c1 }, /* TPBUFFER57 */
1267 { STB0899_OFF0_TP_BUFFER58 , STB0899_BASE_TP_BUFFER58 , 0x0000c1c1 }, /* TPBUFFER58 */
1268 { STB0899_OFF0_TP_BUFFER59 , STB0899_BASE_TP_BUFFER59 , 0x0000c1c1 }, /* TPBUFFER59 */
1269 { STB0899_OFF0_TP_BUFFER60 , STB0899_BASE_TP_BUFFER60 , 0x0000c1c1 }, /* TPBUFFER60 */
1270 { STB0899_OFF0_TP_BUFFER61 , STB0899_BASE_TP_BUFFER61 , 0x0000c1c1 }, /* TPBUFFER61 */
1271 { STB0899_OFF0_TP_BUFFER62 , STB0899_BASE_TP_BUFFER62 , 0x0000c1c1 }, /* TPBUFFER62 */
1272 { STB0899_OFF0_TP_BUFFER63 , STB0899_BASE_TP_BUFFER63 , 0x0000c1c0 }, /* TPBUFFER63 */
1273 { STB0899_OFF0_RESET_CNTRL , STB0899_BASE_RESET_CNTRL , 0x00000001 }, /* RESETCNTRL */
1274 { STB0899_OFF0_ACM_ENABLE , STB0899_BASE_ACM_ENABLE , 0x00005654 }, /* ACMENABLE */
1275 { STB0899_OFF0_DESCR_CNTRL , STB0899_BASE_DESCR_CNTRL , 0x00000000 }, /* DESCRCNTRL */
1276 { STB0899_OFF0_CSM_CNTRL1 , STB0899_BASE_CSM_CNTRL1 , 0x00020019 }, /* CSMCNTRL1 */
1277 { STB0899_OFF0_CSM_CNTRL2 , STB0899_BASE_CSM_CNTRL2 , 0x004b3237 }, /* CSMCNTRL2 */
1278 { STB0899_OFF0_CSM_CNTRL3 , STB0899_BASE_CSM_CNTRL3 , 0x0003dd17 }, /* CSMCNTRL3 */
1279 { STB0899_OFF0_CSM_CNTRL4 , STB0899_BASE_CSM_CNTRL4 , 0x00008008 }, /* CSMCNTRL4 */
1280 { STB0899_OFF0_UWP_CNTRL1 , STB0899_BASE_UWP_CNTRL1 , 0x002a3106 }, /* UWPCNTRL1 */
1281 { STB0899_OFF0_UWP_CNTRL2 , STB0899_BASE_UWP_CNTRL2 , 0x0006140a }, /* UWPCNTRL2 */
1282 { STB0899_OFF0_UWP_STAT1 , STB0899_BASE_UWP_STAT1 , 0x00008000 }, /* UWPSTAT1 */
1283 { STB0899_OFF0_UWP_STAT2 , STB0899_BASE_UWP_STAT2 , 0x00000000 }, /* UWPSTAT2 */
1284 { STB0899_OFF0_DMD_STAT2 , STB0899_BASE_DMD_STAT2 , 0x00000000 }, /* DMDSTAT2 */
1285 { STB0899_OFF0_FREQ_ADJ_SCALE , STB0899_BASE_FREQ_ADJ_SCALE , 0x00000471 }, /* FREQADJSCALE */
1286 { STB0899_OFF0_UWP_CNTRL3 , STB0899_BASE_UWP_CNTRL3 , 0x017b0465 }, /* UWPCNTRL3 */
1287 { STB0899_OFF0_SYM_CLK_SEL , STB0899_BASE_SYM_CLK_SEL , 0x00000002 }, /* SYMCLKSEL */
1288 { STB0899_OFF0_SOF_SRCH_TO , STB0899_BASE_SOF_SRCH_TO , 0x00196464 }, /* SOFSRCHTO */
1289 { STB0899_OFF0_ACQ_CNTRL1 , STB0899_BASE_ACQ_CNTRL1 , 0x00000603 }, /* ACQCNTRL1 */
1290 { STB0899_OFF0_ACQ_CNTRL2 , STB0899_BASE_ACQ_CNTRL2 , 0x02046666 }, /* ACQCNTRL2 */
1291 { STB0899_OFF0_ACQ_CNTRL3 , STB0899_BASE_ACQ_CNTRL3 , 0x10046583 }, /* ACQCNTRL3 */
1292 { STB0899_OFF0_FE_SETTLE , STB0899_BASE_FE_SETTLE , 0x00010404 }, /* FESETTLE */
1293 { STB0899_OFF0_AC_DWELL , STB0899_BASE_AC_DWELL , 0x0002aa8a }, /* ACDWELL */
1294 { STB0899_OFF0_ACQUIRE_TRIG , STB0899_BASE_ACQUIRE_TRIG , 0x00000000 }, /* ACQUIRETRIG */
1295 { STB0899_OFF0_LOCK_LOST , STB0899_BASE_LOCK_LOST , 0x00000001 }, /* LOCKLOST */
1296 { STB0899_OFF0_ACQ_STAT1 , STB0899_BASE_ACQ_STAT1 , 0x00000500 }, /* ACQSTAT1 */
1297 { STB0899_OFF0_ACQ_TIMEOUT , STB0899_BASE_ACQ_TIMEOUT , 0x0028a0a0 }, /* ACQTIMEOUT */
1298 { STB0899_OFF0_ACQ_TIME , STB0899_BASE_ACQ_TIME , 0x00000000 }, /* ACQTIME */
1299 { STB0899_OFF0_FINAL_AGC_CNTRL , STB0899_BASE_FINAL_AGC_CNTRL , 0x00800c17 }, /* FINALAGCCNTRL*/
1300 { STB0899_OFF0_FINAL_AGC_GAIN , STB0899_BASE_FINAL_AGC_GAIN , 0x00000000 }, /* FINALAGCCGAIN*/
1301 { STB0899_OFF0_EQUALIZER_INIT , STB0899_BASE_EQUALIZER_INIT , 0x00000000 }, /* EQUILIZERINIT*/
1302 { STB0899_OFF0_EQ_CNTRL , STB0899_BASE_EQ_CNTRL , 0x00054802 }, /* EQCNTL */
1303 { STB0899_OFF0_EQ_I_INIT_COEFF_0, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF0 */
1304 { STB0899_OFF1_EQ_I_INIT_COEFF_1, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF1 */
1305 { STB0899_OFF2_EQ_I_INIT_COEFF_2, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF2 */
1306 { STB0899_OFF3_EQ_I_INIT_COEFF_3, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF3 */
1307 { STB0899_OFF4_EQ_I_INIT_COEFF_4, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF4 */
1308 { STB0899_OFF5_EQ_I_INIT_COEFF_5, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000400 }, /* EQIINITCOEFF5 */
1309 { STB0899_OFF6_EQ_I_INIT_COEFF_6, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF6 */
1310 { STB0899_OFF7_EQ_I_INIT_COEFF_7, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF7 */
1311 { STB0899_OFF8_EQ_I_INIT_COEFF_8, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF8 */
1312 { STB0899_OFF9_EQ_I_INIT_COEFF_9, STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF9 */
1313 { STB0899_OFFa_EQ_I_INIT_COEFF_10,STB0899_BASE_EQ_I_INIT_COEFF_N, 0x00000000 }, /* EQIINITCOEFF10*/
1314 { STB0899_OFF0_EQ_Q_INIT_COEFF_0, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF0 */
1315 { STB0899_OFF1_EQ_Q_INIT_COEFF_1, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF1 */
1316 { STB0899_OFF2_EQ_Q_INIT_COEFF_2, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF2 */
1317 { STB0899_OFF3_EQ_Q_INIT_COEFF_3, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF3 */
1318 { STB0899_OFF4_EQ_Q_INIT_COEFF_4, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF4 */
1319 { STB0899_OFF5_EQ_Q_INIT_COEFF_5, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF5 */
1320 { STB0899_OFF6_EQ_Q_INIT_COEFF_6, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF6 */
1321 { STB0899_OFF7_EQ_Q_INIT_COEFF_7, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF7 */
1322 { STB0899_OFF8_EQ_Q_INIT_COEFF_8, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF8 */
1323 { STB0899_OFF9_EQ_Q_INIT_COEFF_9, STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF9 */
1324 { STB0899_OFFa_EQ_Q_INIT_COEFF_10,STB0899_BASE_EQ_Q_INIT_COEFF_N, 0x00000000 }, /* EQQINITCOEFF10*/
1325 { STB0899_OFF0_EQ_I_OUT_COEFF_0 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT0 */
1326 { STB0899_OFF1_EQ_I_OUT_COEFF_1 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT1 */
1327 { STB0899_OFF2_EQ_I_OUT_COEFF_2 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT2 */
1328 { STB0899_OFF3_EQ_I_OUT_COEFF_3 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT3 */
1329 { STB0899_OFF4_EQ_I_OUT_COEFF_4 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT4 */
1330 { STB0899_OFF5_EQ_I_OUT_COEFF_5 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT5 */
1331 { STB0899_OFF6_EQ_I_OUT_COEFF_6 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT6 */
1332 { STB0899_OFF7_EQ_I_OUT_COEFF_7 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT7 */
1333 { STB0899_OFF8_EQ_I_OUT_COEFF_8 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT8 */
1334 { STB0899_OFF9_EQ_I_OUT_COEFF_9 , STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT9 */
1335 { STB0899_OFFa_EQ_I_OUT_COEFF_10,STB0899_BASE_EQ_I_OUT_COEFF_N , 0x00000000 }, /* EQICOEFFSOUT10*/
1336 { STB0899_OFF0_EQ_Q_OUT_COEFF_0 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT0 */
1337 { STB0899_OFF1_EQ_Q_OUT_COEFF_1 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT1 */
1338 { STB0899_OFF2_EQ_Q_OUT_COEFF_2 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT2 */
1339 { STB0899_OFF3_EQ_Q_OUT_COEFF_3 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT3 */
1340 { STB0899_OFF4_EQ_Q_OUT_COEFF_4 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT4 */
1341 { STB0899_OFF5_EQ_Q_OUT_COEFF_5 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT5 */
1342 { STB0899_OFF6_EQ_Q_OUT_COEFF_6 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT6 */
1343 { STB0899_OFF7_EQ_Q_OUT_COEFF_7 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT7 */
1344 { STB0899_OFF8_EQ_Q_OUT_COEFF_8 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT8 */
1345 { STB0899_OFF9_EQ_Q_OUT_COEFF_9 , STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT9 */
1346 { STB0899_OFFa_EQ_Q_OUT_COEFF_10, STB0899_BASE_EQ_Q_OUT_COEFF_N , 0x00000000 }, /* EQQCOEFFSOUT10*/
1347 { 0xffff , 0xffffffff , 0xffffffff },
1348};
1074 1349
1350static const struct stb0899_s1_reg tt3200_stb0899_s1_init_3[] = {
1351 { STB0899_DEMOD , 0x00 },
1352 { STB0899_RCOMPC , 0xc9 },
1353 { STB0899_AGC1CN , 0x41 },
1354 { STB0899_AGC1REF , 0x10 },
1355 { STB0899_RTC , 0x7a },
1356 { STB0899_TMGCFG , 0x4e },
1357 { STB0899_AGC2REF , 0x34 },
1358 { STB0899_TLSR , 0x84 },
1359 { STB0899_CFD , 0xc7 },
1360 { STB0899_ACLC , 0x87 },
1361 { STB0899_BCLC , 0x94 },
1362 { STB0899_EQON , 0x41 },
1363 { STB0899_LDT , 0xdd },
1364 { STB0899_LDT2 , 0xc9 },
1365 { STB0899_EQUALREF , 0xb4 },
1366 { STB0899_TMGRAMP , 0x10 },
1367 { STB0899_TMGTHD , 0x30 },
1368 { STB0899_IDCCOMP , 0xfb },
1369 { STB0899_QDCCOMP , 0x03 },
1370 { STB0899_POWERI , 0x3b },
1371 { STB0899_POWERQ , 0x3d },
1372 { STB0899_RCOMP , 0x81 },
1373 { STB0899_AGCIQIN , 0x80 },
1374 { STB0899_AGC2I1 , 0x04 },
1375 { STB0899_AGC2I2 , 0xf5 },
1376 { STB0899_TLIR , 0x25 },
1377 { STB0899_RTF , 0x80 },
1378 { STB0899_DSTATUS , 0x00 },
1379 { STB0899_LDI , 0xca },
1380 { STB0899_CFRM , 0xf1 },
1381 { STB0899_CFRL , 0xf3 },
1382 { STB0899_NIRM , 0x2a },
1383 { STB0899_NIRL , 0x05 },
1384 { STB0899_ISYMB , 0x17 },
1385 { STB0899_QSYMB , 0xfa },
1386 { STB0899_SFRH , 0x2f },
1387 { STB0899_SFRM , 0x68 },
1388 { STB0899_SFRL , 0x40 },
1389 { STB0899_SFRUPH , 0x2f },
1390 { STB0899_SFRUPM , 0x68 },
1391 { STB0899_SFRUPL , 0x40 },
1392 { STB0899_EQUAI1 , 0xfd },
1393 { STB0899_EQUAQ1 , 0x04 },
1394 { STB0899_EQUAI2 , 0x0f },
1395 { STB0899_EQUAQ2 , 0xff },
1396 { STB0899_EQUAI3 , 0xdf },
1397 { STB0899_EQUAQ3 , 0xfa },
1398 { STB0899_EQUAI4 , 0x37 },
1399 { STB0899_EQUAQ4 , 0x0d },
1400 { STB0899_EQUAI5 , 0xbd },
1401 { STB0899_EQUAQ5 , 0xf7 },
1402 { STB0899_DSTATUS2 , 0x00 },
1403 { STB0899_VSTATUS , 0x00 },
1404 { STB0899_VERROR , 0xff },
1405 { STB0899_IQSWAP , 0x2a },
1406 { STB0899_ECNT1M , 0x00 },
1407 { STB0899_ECNT1L , 0x00 },
1408 { STB0899_ECNT2M , 0x00 },
1409 { STB0899_ECNT2L , 0x00 },
1410 { STB0899_ECNT3M , 0x00 },
1411 { STB0899_ECNT3L , 0x00 },
1412 { STB0899_FECAUTO1 , 0x06 },
1413 { STB0899_FECM , 0x01 },
1414 { STB0899_VTH12 , 0xf0 },
1415 { STB0899_VTH23 , 0xa0 },
1416 { STB0899_VTH34 , 0x78 },
1417 { STB0899_VTH56 , 0x4e },
1418 { STB0899_VTH67 , 0x48 },
1419 { STB0899_VTH78 , 0x38 },
1420 { STB0899_PRVIT , 0xff },
1421 { STB0899_VITSYNC , 0x19 },
1422 { STB0899_RSULC , 0xb1 }, // DVB = 0xb1, DSS = 0xa1
1423 { STB0899_TSULC , 0x42 },
1424 { STB0899_RSLLC , 0x40 },
1425 { STB0899_TSLPL , 0x12 },
1426 { STB0899_TSCFGH , 0x0c },
1427 { STB0899_TSCFGM , 0x00 },
1428 { STB0899_TSCFGL , 0x0c },
1429 { STB0899_TSOUT , 0x07 },
1430 { STB0899_RSSYNCDEL , 0x00 },
1431 { STB0899_TSINHDELH , 0x02 },
1432 { STB0899_TSINHDELM , 0x00 },
1433 { STB0899_TSINHDELL , 0x00 },
1434 { STB0899_TSLLSTKM , 0x00 },
1435 { STB0899_TSLLSTKL , 0x00 },
1436 { STB0899_TSULSTKM , 0x00 },
1437 { STB0899_TSULSTKL , 0xab },
1438 { STB0899_PCKLENUL , 0x00 },
1439 { STB0899_PCKLENLL , 0xcc },
1440 { STB0899_RSPCKLEN , 0xcc },
1441 { STB0899_TSSTATUS , 0x80 },
1442 { STB0899_ERRCTRL1 , 0xb6 },
1443 { STB0899_ERRCTRL2 , 0x96 },
1444 { STB0899_ERRCTRL3 , 0x89 },
1445 { STB0899_DMONMSK1 , 0x27 },
1446 { STB0899_DMONMSK0 , 0x03 },
1447 { STB0899_DEMAPVIT , 0x5c },
1448 { STB0899_PLPARM , 0x1f },
1449 { STB0899_PDELCTRL , 0x48 },
1450 { STB0899_PDELCTRL2 , 0x00 },
1451 { STB0899_BBHCTRL1 , 0x00 },
1452 { STB0899_BBHCTRL2 , 0x00 },
1453 { STB0899_HYSTTHRESH , 0x77 },
1454 { STB0899_MATCSTM , 0x00 },
1455 { STB0899_MATCSTL , 0x00 },
1456 { STB0899_UPLCSTM , 0x00 },
1457 { STB0899_UPLCSTL , 0x00 },
1458 { STB0899_DFLCSTM , 0x00 },
1459 { STB0899_DFLCSTL , 0x00 },
1460 { STB0899_SYNCCST , 0x00 },
1461 { STB0899_SYNCDCSTM , 0x00 },
1462 { STB0899_SYNCDCSTL , 0x00 },
1463 { STB0899_ISI_ENTRY , 0x00 },
1464 { STB0899_ISI_BIT_EN , 0x00 },
1465 { STB0899_MATSTRM , 0x00 },
1466 { STB0899_MATSTRL , 0x00 },
1467 { STB0899_UPLSTRM , 0x00 },
1468 { STB0899_UPLSTRL , 0x00 },
1469 { STB0899_DFLSTRM , 0x00 },
1470 { STB0899_DFLSTRL , 0x00 },
1471 { STB0899_SYNCSTR , 0x00 },
1472 { STB0899_SYNCDSTRM , 0x00 },
1473 { STB0899_SYNCDSTRL , 0x00 },
1474 { STB0899_CFGPDELSTATUS1 , 0x10 },
1475 { STB0899_CFGPDELSTATUS2 , 0x00 },
1476 { STB0899_BBFERRORM , 0x00 },
1477 { STB0899_BBFERRORL , 0x00 },
1478 { STB0899_UPKTERRORM , 0x00 },
1479 { STB0899_UPKTERRORL , 0x00 },
1480 { 0xffff , 0xff },
1481};
1482
1483static const struct stb0899_s2_reg tt3200_stb0899_s2_init_4[] = {
1484 { STB0899_OFF0_BLOCK_LNGTH , STB0899_BASE_BLOCK_LNGTH , 0x00000008 }, /* BLOCKLNGTH */
1485 { STB0899_OFF0_ROW_STR , STB0899_BASE_ROW_STR , 0x000000b4 }, /* ROWSTR */
1486 { STB0899_OFF0_BN_END_ADDR , STB0899_BASE_BN_END_ADDR , 0x000004b5 }, /* BNANDADDR */
1487 { STB0899_OFF0_CN_END_ADDR , STB0899_BASE_CN_END_ADDR , 0x00000b4b }, /* CNANDADDR */
1488 { STB0899_OFF0_INFO_LENGTH , STB0899_BASE_INFO_LENGTH , 0x00000078 }, /* INFOLENGTH */
1489 { STB0899_OFF0_BOT_ADDR , STB0899_BASE_BOT_ADDR , 0x000001e0 }, /* BOT_ADDR */
1490 { STB0899_OFF0_BCH_BLK_LN , STB0899_BASE_BCH_BLK_LN , 0x0000a8c0 }, /* BCHBLKLN */
1491 { STB0899_OFF0_BCH_T , STB0899_BASE_BCH_T , 0x0000000c }, /* BCHT */
1492 { STB0899_OFF0_CNFG_MODE , STB0899_BASE_CNFG_MODE , 0x00000001 }, /* CNFGMODE */
1493 { STB0899_OFF0_LDPC_STAT , STB0899_BASE_LDPC_STAT , 0x0000000d }, /* LDPCSTAT */
1494 { STB0899_OFF0_ITER_SCALE , STB0899_BASE_ITER_SCALE , 0x00000040 }, /* ITERSCALE */
1495 { STB0899_OFF0_INPUT_MODE , STB0899_BASE_INPUT_MODE , 0x00000000 }, /* INPUTMODE */
1496 { STB0899_OFF0_LDPCDECRST , STB0899_BASE_LDPCDECRST , 0x00000000 }, /* LDPCDECRST */
1497 { STB0899_OFF0_CLK_PER_BYTE_RW , STB0899_BASE_CLK_PER_BYTE_RW , 0x00000008 }, /* CLKPERBYTE */
1498 { STB0899_OFF0_BCH_ERRORS , STB0899_BASE_BCH_ERRORS , 0x00000000 }, /* BCHERRORS */
1499 { STB0899_OFF0_LDPC_ERRORS , STB0899_BASE_LDPC_ERRORS , 0x00000000 }, /* LDPCERRORS */
1500 { STB0899_OFF0_BCH_MODE , STB0899_BASE_BCH_MODE , 0x00000000 }, /* BCHMODE */
1501 { STB0899_OFF0_ERR_ACC_PER , STB0899_BASE_ERR_ACC_PER , 0x00000008 }, /* ERRACCPER */
1502 { STB0899_OFF0_BCH_ERR_ACC , STB0899_BASE_BCH_ERR_ACC , 0x00000000 }, /* BCHERRACC */
1503 { STB0899_OFF0_FEC_TP_SEL , STB0899_BASE_FEC_TP_SEL , 0x00000000 }, /* FECTPSEL */
1504 { 0xffff , 0xffffffff , 0xffffffff },
1505};
1506
1507static const struct stb0899_s1_reg tt3200_stb0899_s1_init_5[] = {
1508 { STB0899_TSTCK , 0x00 },
1509 { STB0899_TSTRES , 0x00 },
1510 { STB0899_TSTOUT , 0x00 },
1511 { STB0899_TSTIN , 0x00 },
1512 { STB0899_TSTSYS , 0x00 },
1513 { STB0899_TSTCHIP , 0x00 },
1514 { STB0899_TSTFREE , 0x00 },
1515 { STB0899_TSTI2C , 0x00 },
1516 { STB0899_BITSPEEDM , 0x00 },
1517 { STB0899_BITSPEEDL , 0x00 },
1518 { STB0899_TBUSBIT , 0x00 },
1519 { STB0899_TSTDIS , 0x00 },
1520 { STB0899_TSTDISRX , 0x00 },
1521 { STB0899_TSTJETON , 0x00 },
1522 { STB0899_TSTDCADJ , 0x00 },
1523 { STB0899_TSTAGC1 , 0x00 },
1524 { STB0899_TSTAGC1N , 0x00 },
1525 { STB0899_TSTPOLYPH , 0x00 },
1526 { STB0899_TSTR , 0x00 },
1527 { STB0899_TSTAGC2 , 0x00 },
1528 { STB0899_TSTCTL1 , 0x00 },
1529 { STB0899_TSTCTL2 , 0x00 },
1530 { STB0899_TSTCTL3 , 0x00 },
1531 { STB0899_TSTDEMAP , 0x00 },
1532 { STB0899_TSTDEMAP2 , 0x00 },
1533 { STB0899_TSTDEMMON , 0x00 },
1534 { STB0899_TSTRATE , 0x00 },
1535 { STB0899_TSTSELOUT , 0x00 },
1536 { STB0899_TSYNC , 0x00 },
1537 { STB0899_TSTERR , 0x00 },
1538 { STB0899_TSTRAM1 , 0x00 },
1539 { STB0899_TSTVSELOUT , 0x00 },
1540 { STB0899_TSTFORCEIN , 0x00 },
1541 { STB0899_TSTRS1 , 0x00 },
1542 { STB0899_TSTRS2 , 0x00 },
1543 { STB0899_TSTRS3 , 0x00 },
1544 { STB0899_GHOSTREG , 0x81 },
1545 { 0xffff , 0xff },
1546};
1547
1548static struct stb0899_config tt3200_config = {
1549 .init_dev = tt3200_stb0899_s1_init_1,
1550 .init_s2_demod = tt3200_stb0899_s2_init_2,
1551 .init_s1_demod = tt3200_stb0899_s1_init_3,
1552 .init_s2_fec = tt3200_stb0899_s2_init_4,
1553 .init_tst = tt3200_stb0899_s1_init_5,
1554
1555 .demod_address = 0x68,
1556
1557 .xtal_freq = 27000000,
1558 .inversion = 1,
1559};
1560
1561struct stb6100_config tt3200_stb6100_config = {
1562 .tuner_address = 0x60
1563};
1075 1564
1076static void frontend_init(struct budget_ci *budget_ci) 1565static void frontend_init(struct budget_ci *budget_ci)
1077{ 1566{
@@ -1152,6 +1641,26 @@ static void frontend_init(struct budget_ci *budget_ci)
1152 } 1641 }
1153 } 1642 }
1154 break; 1643 break;
1644
1645 case 0x1019: // TT S2-3200 PCI
1646 budget_ci->budget.dvb_frontend = stb0899_attach(&tt3200_config, &budget_ci->budget.i2c_adap);
1647 if (budget_ci->budget.dvb_frontend) {
1648 if (stb6100_attach(budget_ci->budget.dvb_frontend, &tt3200_stb6100_config, &budget_ci->budget.i2c_adap)) {
1649 if (lnbp21_attach(budget_ci->budget.dvb_frontend, &budget_ci->budget.i2c_adap, 0, 0)) {
1650 printk("%s: No LNBP21 found!\n", __FUNCTION__);
1651 if (budget_ci->budget.dvb_frontend->ops.tuner_ops.release)
1652 budget_ci->budget.dvb_frontend->ops.tuner_ops.release(budget_ci->budget.dvb_frontend);
1653 if (budget_ci->budget.dvb_frontend->ops.release)
1654 budget_ci->budget.dvb_frontend->ops.release(budget_ci->budget.dvb_frontend);
1655 budget_ci->budget.dvb_frontend = NULL;
1656 }
1657 } else {
1658 if (budget_ci->budget.dvb_frontend->ops.release)
1659 budget_ci->budget.dvb_frontend->ops.release(budget_ci->budget.dvb_frontend);
1660 }
1661 }
1662 break;
1663
1155 } 1664 }
1156 1665
1157 if (budget_ci->budget.dvb_frontend == NULL) { 1666 if (budget_ci->budget.dvb_frontend == NULL) {
@@ -1242,6 +1751,7 @@ MAKE_BUDGET_INFO(ttbt2, "TT-Budget/WinTV-NOVA-T PCI", BUDGET_TT);
1242MAKE_BUDGET_INFO(ttbtci, "TT-Budget-T-CI PCI", BUDGET_TT); 1751MAKE_BUDGET_INFO(ttbtci, "TT-Budget-T-CI PCI", BUDGET_TT);
1243MAKE_BUDGET_INFO(ttbcci, "TT-Budget-C-CI PCI", BUDGET_TT); 1752MAKE_BUDGET_INFO(ttbcci, "TT-Budget-C-CI PCI", BUDGET_TT);
1244MAKE_BUDGET_INFO(ttc1501, "TT-Budget C-1501 PCI", BUDGET_TT); 1753MAKE_BUDGET_INFO(ttc1501, "TT-Budget C-1501 PCI", BUDGET_TT);
1754MAKE_BUDGET_INFO(tt3200, "TT-Budget S2-3200 PCI", BUDGET_TT);
1245 1755
1246static struct pci_device_id pci_tbl[] = { 1756static struct pci_device_id pci_tbl[] = {
1247 MAKE_EXTENSION_PCI(ttbci, 0x13c2, 0x100c), 1757 MAKE_EXTENSION_PCI(ttbci, 0x13c2, 0x100c),
@@ -1251,6 +1761,7 @@ static struct pci_device_id pci_tbl[] = {
1251 MAKE_EXTENSION_PCI(ttbtci, 0x13c2, 0x1012), 1761 MAKE_EXTENSION_PCI(ttbtci, 0x13c2, 0x1012),
1252 MAKE_EXTENSION_PCI(ttbs2, 0x13c2, 0x1017), 1762 MAKE_EXTENSION_PCI(ttbs2, 0x13c2, 0x1017),
1253 MAKE_EXTENSION_PCI(ttc1501, 0x13c2, 0x101a), 1763 MAKE_EXTENSION_PCI(ttc1501, 0x13c2, 0x101a),
1764 MAKE_EXTENSION_PCI(tt3200, 0x13c2, 0x1019),
1254 { 1765 {
1255 .vendor = 0, 1766 .vendor = 0,
1256 } 1767 }
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-19 03:06:52 -0500