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authorRalph Metzler <rjkm@metzlerbros.de>2011-03-12 23:44:33 -0500
committerMauro Carvalho Chehab <mchehab@redhat.com>2011-05-20 06:26:16 -0400
commit126f1e61887085aa2c2cfa7644aee8295a94e1f7 (patch)
tree1c413f580c60377491f8e51d7221e25c4eb93117 /drivers/media/dvb/frontends
parent0618ece01fdedcd3e775d9d43acc2c2a661a0c54 (diff)
drx: add initial drx-d driver
These are the original drx-d sources, extracted from Ralph Metzler's GPL'd ngene driver. No modifications/cleanup have yet been made. In fact, no measures have been taken to see if the code even compiles. Signed-off-by Ralph Metzler <rjkm@metzlerbros.de> Signed-off-by: Devin Heitmueller <dheitmueller@kernellabs.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
Diffstat (limited to 'drivers/media/dvb/frontends')
-rw-r--r--drivers/media/dvb/frontends/drxd.h57
-rw-r--r--drivers/media/dvb/frontends/drxd_firm.c943
-rw-r--r--drivers/media/dvb/frontends/drxd_firm.h120
-rw-r--r--drivers/media/dvb/frontends/drxd_hard.c2831
-rw-r--r--drivers/media/dvb/frontends/drxd_map_firm.h14484
-rw-r--r--drivers/media/dvb/frontends/drxd_micro.h1498
6 files changed, 19933 insertions, 0 deletions
diff --git a/drivers/media/dvb/frontends/drxd.h b/drivers/media/dvb/frontends/drxd.h
new file mode 100644
index 000000000000..9b11dc835c44
--- /dev/null
+++ b/drivers/media/dvb/frontends/drxd.h
@@ -0,0 +1,57 @@
1/*
2 * drxd.h: DRXD DVB-T demodulator driver
3 *
4 * Copyright (C) 2005-2007 Micronas
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22 */
23
24#ifndef _DRXD_H_
25#define _DRXD_H_
26
27#include <linux/types.h>
28#include <linux/i2c.h>
29
30struct drxd_config
31{
32 u8 index;
33
34 u8 pll_address;
35 u8 pll_type;
36#define DRXD_PLL_NONE 0
37#define DRXD_PLL_DTT7520X 1
38#define DRXD_PLL_MT3X0823 2
39
40 u32 clock;
41
42 u8 demod_address;
43 u8 demoda_address;
44 u8 demod_revision;
45
46 u32 IF;
47 int (*pll_set) (void *priv, void *priv_params,
48 u8 pll_addr, u8 demoda_addr, s32 *off);
49 s16 (*osc_deviation) (void *priv, s16 dev, int flag);
50};
51
52extern
53struct dvb_frontend *drxd_attach(const struct drxd_config *config,
54 void *priv, struct i2c_adapter *i2c,
55 struct device *dev);
56extern int drxd_config_i2c(struct dvb_frontend *, int);
57#endif
diff --git a/drivers/media/dvb/frontends/drxd_firm.c b/drivers/media/dvb/frontends/drxd_firm.c
new file mode 100644
index 000000000000..b27e928b94c1
--- /dev/null
+++ b/drivers/media/dvb/frontends/drxd_firm.c
@@ -0,0 +1,943 @@
1/*
2 * drxd_firm.c : DRXD firmware tables
3 *
4 * Copyright (C) 2006-2007 Micronas
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22 */
23
24/* TODO: generate this file with a script from a settings file */
25
26/* Contains A2 firmware version: 1.4.2
27 * Contains B1 firmware version: 3.3.33
28 * Contains settings from driver 1.4.23
29*/
30
31#include "drxd_firm.h"
32
33#define ADDRESS(x) ((x) & 0xFF), (((x)>>8) & 0xFF), (((x)>>16) & 0xFF), (((x)>>24) & 0xFF)
34#define LENGTH(x) ((x) & 0xFF), (((x)>>8) & 0xFF)
35
36/* Is written via block write, must be little endian */
37#define DATA16(x) ((x) & 0xFF), (((x)>>8) & 0xFF)
38
39#define WRBLOCK(a,l) ADDRESS(a),LENGTH(l)
40#define WR16(a,d) ADDRESS(a),LENGTH(1),DATA16(d)
41
42#define END_OF_TABLE 0xFF,0xFF,0xFF,0xFF
43
44/* HI firmware patches */
45
46#define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
47#define HI_TR_FUNC_SIZE 9 /* size of this function in instruction words */
48
49u8_t DRXD_InitAtomicRead[] =
50{
51 WRBLOCK(HI_TR_FUNC_ADDR,HI_TR_FUNC_SIZE),
52 0x26, 0x00, /* 0 -> ring.rdy; */
53 0x60, 0x04, /* r0rami.dt -> ring.xba; */
54 0x61, 0x04, /* r0rami.dt -> ring.xad; */
55 0xE3, 0x07, /* HI_RA_RAM_USR_BEGIN -> ring.iad; */
56 0x40, 0x00, /* (long immediate) */
57 0x64, 0x04, /* r0rami.dt -> ring.len; */
58 0x65, 0x04, /* r0rami.dt -> ring.ctl; */
59 0x26, 0x00, /* 0 -> ring.rdy; */
60 0x38, 0x00, /* 0 -> jumps.ad; */
61 END_OF_TABLE
62};
63
64/* Pins D0 and D1 of the parallel MPEG output can be used
65 to set the I2C address of a device. */
66
67#define HI_RST_FUNC_ADDR ( HI_IF_RAM_USR_BEGIN__A + HI_TR_FUNC_SIZE)
68#define HI_RST_FUNC_SIZE 54 /* size of this function in instruction words */
69
70/* D0 Version */
71u8_t DRXD_HiI2cPatch_1[] =
72{
73 WRBLOCK(HI_RST_FUNC_ADDR,HI_RST_FUNC_SIZE),
74 0xC8, 0x07, 0x01, 0x00, /* MASK -> reg0.dt; */
75 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
76 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
77 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */
78 0x23, 0x00, /* &data -> ring.iad; */
79 0x24, 0x00, /* 0 -> ring.len; */
80 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
81 0x26, 0x00, /* 0 -> ring.rdy; */
82 0x42, 0x00, /* &data+1 -> w0ram.ad; */
83 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */
84 0x63, 0x00, /* &data+1 -> ring.iad; */
85 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
86 0x26, 0x00, /* 0 -> ring.rdy; */
87 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */
88 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
89 0x26, 0x00, /* 0 -> ring.rdy; */
90 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
91 0x23, 0x00, /* &data -> ring.iad; */
92 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
93 0x26, 0x00, /* 0 -> ring.rdy; */
94 0x42, 0x00, /* &data+1 -> w0ram.ad; */
95 0x0F, 0x04, /* r0ram.dt -> and.op; */
96 0x1C, 0x06, /* reg0.dt -> and.tr; */
97 0xCF, 0x04, /* and.rs -> add.op; */
98 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */
99 0xD0, 0x04, /* add.rs -> add.tr; */
100 0xC8, 0x04, /* add.rs -> reg0.dt; */
101 0x60, 0x00, /* reg0.dt -> w0ram.dt; */
102 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */
103 0x01, 0x00, /* 0 -> w0rami.dt; */
104 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
105 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */
106 0x01, 0x00, /* 0 -> w0rami.dt; */
107 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
108 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */
109 0x01, 0x00, /* 0 -> w0rami.dt; */
110 0x01, 0x00, /* 0 -> w0rami.dt; */
111 0x01, 0x00, /* 0 -> w0rami.dt; */
112 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */
113 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
114 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */
115 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
116 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */
117
118 WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*0)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
119 WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*1)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
120 WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*2)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
121 WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*3)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
122
123 /* Force quick and dirty reset */
124 WR16(B_HI_CT_REG_COMM_STATE__A,0),
125 END_OF_TABLE
126};
127
128/* D0,D1 Version */
129u8_t DRXD_HiI2cPatch_3[] =
130{
131 WRBLOCK(HI_RST_FUNC_ADDR,HI_RST_FUNC_SIZE),
132 0xC8, 0x07, 0x03, 0x00, /* MASK -> reg0.dt; */
133 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
134 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
135 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */
136 0x23, 0x00, /* &data -> ring.iad; */
137 0x24, 0x00, /* 0 -> ring.len; */
138 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
139 0x26, 0x00, /* 0 -> ring.rdy; */
140 0x42, 0x00, /* &data+1 -> w0ram.ad; */
141 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */
142 0x63, 0x00, /* &data+1 -> ring.iad; */
143 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
144 0x26, 0x00, /* 0 -> ring.rdy; */
145 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */
146 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
147 0x26, 0x00, /* 0 -> ring.rdy; */
148 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
149 0x23, 0x00, /* &data -> ring.iad; */
150 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
151 0x26, 0x00, /* 0 -> ring.rdy; */
152 0x42, 0x00, /* &data+1 -> w0ram.ad; */
153 0x0F, 0x04, /* r0ram.dt -> and.op; */
154 0x1C, 0x06, /* reg0.dt -> and.tr; */
155 0xCF, 0x04, /* and.rs -> add.op; */
156 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */
157 0xD0, 0x04, /* add.rs -> add.tr; */
158 0xC8, 0x04, /* add.rs -> reg0.dt; */
159 0x60, 0x00, /* reg0.dt -> w0ram.dt; */
160 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */
161 0x01, 0x00, /* 0 -> w0rami.dt; */
162 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
163 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */
164 0x01, 0x00, /* 0 -> w0rami.dt; */
165 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
166 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */
167 0x01, 0x00, /* 0 -> w0rami.dt; */
168 0x01, 0x00, /* 0 -> w0rami.dt; */
169 0x01, 0x00, /* 0 -> w0rami.dt; */
170 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */
171 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
172 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */
173 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
174 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */
175
176 WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*0)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
177 WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*1)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
178 WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*2)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
179 WR16((B_HI_IF_RAM_TRP_BPT0__AX+((2*3)+1)),(u16_t)(HI_RST_FUNC_ADDR & 0x3FF)),
180
181 /* Force quick and dirty reset */
182 WR16(B_HI_CT_REG_COMM_STATE__A,0),
183 END_OF_TABLE
184};
185
186u8_t DRXD_ResetCEFR[] =
187{
188 WRBLOCK(CE_REG_FR_TREAL00__A, 57),
189 0x52,0x00, /* CE_REG_FR_TREAL00__A */
190 0x00,0x00, /* CE_REG_FR_TIMAG00__A */
191 0x52,0x00, /* CE_REG_FR_TREAL01__A */
192 0x00,0x00, /* CE_REG_FR_TIMAG01__A */
193 0x52,0x00, /* CE_REG_FR_TREAL02__A */
194 0x00,0x00, /* CE_REG_FR_TIMAG02__A */
195 0x52,0x00, /* CE_REG_FR_TREAL03__A */
196 0x00,0x00, /* CE_REG_FR_TIMAG03__A */
197 0x52,0x00, /* CE_REG_FR_TREAL04__A */
198 0x00,0x00, /* CE_REG_FR_TIMAG04__A */
199 0x52,0x00, /* CE_REG_FR_TREAL05__A */
200 0x00,0x00, /* CE_REG_FR_TIMAG05__A */
201 0x52,0x00, /* CE_REG_FR_TREAL06__A */
202 0x00,0x00, /* CE_REG_FR_TIMAG06__A */
203 0x52,0x00, /* CE_REG_FR_TREAL07__A */
204 0x00,0x00, /* CE_REG_FR_TIMAG07__A */
205 0x52,0x00, /* CE_REG_FR_TREAL08__A */
206 0x00,0x00, /* CE_REG_FR_TIMAG08__A */
207 0x52,0x00, /* CE_REG_FR_TREAL09__A */
208 0x00,0x00, /* CE_REG_FR_TIMAG09__A */
209 0x52,0x00, /* CE_REG_FR_TREAL10__A */
210 0x00,0x00, /* CE_REG_FR_TIMAG10__A */
211 0x52,0x00, /* CE_REG_FR_TREAL11__A */
212 0x00,0x00, /* CE_REG_FR_TIMAG11__A */
213
214 0x52,0x00, /* CE_REG_FR_MID_TAP__A */
215
216 0x0B,0x00, /* CE_REG_FR_SQS_G00__A */
217 0x0B,0x00, /* CE_REG_FR_SQS_G01__A */
218 0x0B,0x00, /* CE_REG_FR_SQS_G02__A */
219 0x0B,0x00, /* CE_REG_FR_SQS_G03__A */
220 0x0B,0x00, /* CE_REG_FR_SQS_G04__A */
221 0x0B,0x00, /* CE_REG_FR_SQS_G05__A */
222 0x0B,0x00, /* CE_REG_FR_SQS_G06__A */
223 0x0B,0x00, /* CE_REG_FR_SQS_G07__A */
224 0x0B,0x00, /* CE_REG_FR_SQS_G08__A */
225 0x0B,0x00, /* CE_REG_FR_SQS_G09__A */
226 0x0B,0x00, /* CE_REG_FR_SQS_G10__A */
227 0x0B,0x00, /* CE_REG_FR_SQS_G11__A */
228 0x0B,0x00, /* CE_REG_FR_SQS_G12__A */
229
230 0xFF,0x01, /* CE_REG_FR_RIO_G00__A */
231 0x90,0x01, /* CE_REG_FR_RIO_G01__A */
232 0x0B,0x01, /* CE_REG_FR_RIO_G02__A */
233 0xC8,0x00, /* CE_REG_FR_RIO_G03__A */
234 0xA0,0x00, /* CE_REG_FR_RIO_G04__A */
235 0x85,0x00, /* CE_REG_FR_RIO_G05__A */
236 0x72,0x00, /* CE_REG_FR_RIO_G06__A */
237 0x64,0x00, /* CE_REG_FR_RIO_G07__A */
238 0x59,0x00, /* CE_REG_FR_RIO_G08__A */
239 0x50,0x00, /* CE_REG_FR_RIO_G09__A */
240 0x49,0x00, /* CE_REG_FR_RIO_G10__A */
241
242 0x10,0x00, /* CE_REG_FR_MODE__A */
243 0x78,0x00, /* CE_REG_FR_SQS_TRH__A */
244 0x00,0x00, /* CE_REG_FR_RIO_GAIN__A */
245 0x00,0x02, /* CE_REG_FR_BYPASS__A */
246 0x0D,0x00, /* CE_REG_FR_PM_SET__A */
247 0x07,0x00, /* CE_REG_FR_ERR_SH__A */
248 0x04,0x00, /* CE_REG_FR_MAN_SH__A */
249 0x06,0x00, /* CE_REG_FR_TAP_SH__A */
250
251 END_OF_TABLE
252};
253
254
255u8_t DRXD_InitFEA2_1[] =
256{
257 WRBLOCK(FE_AD_REG_PD__A , 3),
258 0x00,0x00, /* FE_AD_REG_PD__A */
259 0x01,0x00, /* FE_AD_REG_INVEXT__A */
260 0x00,0x00, /* FE_AD_REG_CLKNEG__A */
261
262 WRBLOCK(FE_AG_REG_DCE_AUR_CNT__A , 2),
263 0x10,0x00, /* FE_AG_REG_DCE_AUR_CNT__A */
264 0x10,0x00, /* FE_AG_REG_DCE_RUR_CNT__A */
265
266 WRBLOCK(FE_AG_REG_ACE_AUR_CNT__A , 2),
267 0x0E,0x00, /* FE_AG_REG_ACE_AUR_CNT__A */
268 0x00,0x00, /* FE_AG_REG_ACE_RUR_CNT__A */
269
270 WRBLOCK(FE_AG_REG_EGC_FLA_RGN__A , 5),
271 0x04,0x00, /* FE_AG_REG_EGC_FLA_RGN__A */
272 0x1F,0x00, /* FE_AG_REG_EGC_SLO_RGN__A */
273 0x00,0x00, /* FE_AG_REG_EGC_JMP_PSN__A */
274 0x00,0x00, /* FE_AG_REG_EGC_FLA_INC__A */
275 0x00,0x00, /* FE_AG_REG_EGC_FLA_DEC__A */
276
277 WRBLOCK(FE_AG_REG_GC1_AGC_MAX__A , 2),
278 0xFF,0x01, /* FE_AG_REG_GC1_AGC_MAX__A */
279 0x00,0xFE, /* FE_AG_REG_GC1_AGC_MIN__A */
280
281 WRBLOCK(FE_AG_REG_IND_WIN__A , 29),
282 0x00,0x00, /* FE_AG_REG_IND_WIN__A */
283 0x05,0x00, /* FE_AG_REG_IND_THD_LOL__A */
284 0x0F,0x00, /* FE_AG_REG_IND_THD_HIL__A */
285 0x00,0x00, /* FE_AG_REG_IND_DEL__A don't care */
286 0x1E,0x00, /* FE_AG_REG_IND_PD1_WRI__A */
287 0x0C,0x00, /* FE_AG_REG_PDA_AUR_CNT__A */
288 0x00,0x00, /* FE_AG_REG_PDA_RUR_CNT__A */
289 0x00,0x00, /* FE_AG_REG_PDA_AVE_DAT__A don't care */
290 0x00,0x00, /* FE_AG_REG_PDC_RUR_CNT__A */
291 0x01,0x00, /* FE_AG_REG_PDC_SET_LVL__A */
292 0x02,0x00, /* FE_AG_REG_PDC_FLA_RGN__A */
293 0x00,0x00, /* FE_AG_REG_PDC_JMP_PSN__A don't care */
294 0xFF,0xFF, /* FE_AG_REG_PDC_FLA_STP__A */
295 0xFF,0xFF, /* FE_AG_REG_PDC_SLO_STP__A */
296 0x00,0x1F, /* FE_AG_REG_PDC_PD2_WRI__A don't care */
297 0x00,0x00, /* FE_AG_REG_PDC_MAP_DAT__A don't care */
298 0x02,0x00, /* FE_AG_REG_PDC_MAX__A */
299 0x0C,0x00, /* FE_AG_REG_TGA_AUR_CNT__A */
300 0x00,0x00, /* FE_AG_REG_TGA_RUR_CNT__A */
301 0x00,0x00, /* FE_AG_REG_TGA_AVE_DAT__A don't care */
302 0x00,0x00, /* FE_AG_REG_TGC_RUR_CNT__A */
303 0x22,0x00, /* FE_AG_REG_TGC_SET_LVL__A */
304 0x15,0x00, /* FE_AG_REG_TGC_FLA_RGN__A */
305 0x00,0x00, /* FE_AG_REG_TGC_JMP_PSN__A don't care */
306 0x01,0x00, /* FE_AG_REG_TGC_FLA_STP__A */
307 0x0A,0x00, /* FE_AG_REG_TGC_SLO_STP__A */
308 0x00,0x00, /* FE_AG_REG_TGC_MAP_DAT__A don't care */
309 0x10,0x00, /* FE_AG_REG_FGA_AUR_CNT__A */
310 0x10,0x00, /* FE_AG_REG_FGA_RUR_CNT__A */
311
312 WRBLOCK(FE_AG_REG_BGC_FGC_WRI__A , 2),
313 0x00,0x00, /* FE_AG_REG_BGC_FGC_WRI__A */
314 0x00,0x00, /* FE_AG_REG_BGC_CGC_WRI__A */
315
316 WRBLOCK(FE_FD_REG_SCL__A , 3),
317 0x05,0x00, /* FE_FD_REG_SCL__A */
318 0x03,0x00, /* FE_FD_REG_MAX_LEV__A */
319 0x05,0x00, /* FE_FD_REG_NR__A */
320
321 WRBLOCK(FE_CF_REG_SCL__A , 5),
322 0x16,0x00, /* FE_CF_REG_SCL__A */
323 0x04,0x00, /* FE_CF_REG_MAX_LEV__A */
324 0x06,0x00, /* FE_CF_REG_NR__A */
325 0x00,0x00, /* FE_CF_REG_IMP_VAL__A */
326 0x01,0x00, /* FE_CF_REG_MEAS_VAL__A */
327
328 WRBLOCK(FE_CU_REG_FRM_CNT_RST__A , 2),
329 0x00,0x08, /* FE_CU_REG_FRM_CNT_RST__A */
330 0x00,0x00, /* FE_CU_REG_FRM_CNT_STR__A */
331
332 END_OF_TABLE
333};
334
335 /* with PGA */
336/* WR16COND( DRXD_WITH_PGA, FE_AG_REG_AG_PGA_MODE__A , 0x0004), */
337 /* without PGA */
338/* WR16COND( DRXD_WITHOUT_PGA, FE_AG_REG_AG_PGA_MODE__A , 0x0001), */
339/* WR16(FE_AG_REG_AG_AGC_SIO__A, (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/
340/* WR16(FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
341
342u8_t DRXD_InitFEA2_2[] =
343{
344 WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010),
345 WR16(FE_AG_REG_FGM_WRI__A , 48),
346 /* Activate measurement, activate scale */
347 WR16(FE_FD_REG_MEAS_VAL__A , 0x0001),
348
349 WR16(FE_CU_REG_COMM_EXEC__A, 0x0001),
350 WR16(FE_CF_REG_COMM_EXEC__A, 0x0001),
351 WR16(FE_IF_REG_COMM_EXEC__A, 0x0001),
352 WR16(FE_FD_REG_COMM_EXEC__A, 0x0001),
353 WR16(FE_FS_REG_COMM_EXEC__A, 0x0001),
354 WR16(FE_AD_REG_COMM_EXEC__A , 0x0001),
355 WR16(FE_AG_REG_COMM_EXEC__A , 0x0001),
356 WR16(FE_AG_REG_AG_MODE_LOP__A , 0x895E),
357
358 END_OF_TABLE
359};
360
361u8_t DRXD_InitFEB1_1[] =
362{
363 WR16(B_FE_AD_REG_PD__A ,0x0000 ),
364 WR16(B_FE_AD_REG_CLKNEG__A ,0x0000 ),
365 WR16(B_FE_AG_REG_BGC_FGC_WRI__A ,0x0000 ),
366 WR16(B_FE_AG_REG_BGC_CGC_WRI__A ,0x0000 ),
367 WR16(B_FE_AG_REG_AG_MODE_LOP__A ,0x000a ),
368 WR16(B_FE_AG_REG_IND_PD1_WRI__A ,35 ),
369 WR16(B_FE_AG_REG_IND_WIN__A ,0 ),
370 WR16(B_FE_AG_REG_IND_THD_LOL__A ,8 ),
371 WR16(B_FE_AG_REG_IND_THD_HIL__A ,8 ),
372 WR16(B_FE_CF_REG_IMP_VAL__A ,1 ),
373 WR16(B_FE_AG_REG_EGC_FLA_RGN__A ,7 ),
374 END_OF_TABLE
375};
376 /* with PGA */
377/* WR16(B_FE_AG_REG_AG_PGA_MODE__A , 0x0000, 0x0000); */
378 /* without PGA */
379/* WR16(B_FE_AG_REG_AG_PGA_MODE__A ,
380 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);*/
381/* WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005*/
382/* WR16(B_FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
383
384u8_t DRXD_InitFEB1_2[] =
385{
386 WR16(B_FE_COMM_EXEC__A ,0x0001 ),
387
388 /* RF-AGC setup */
389 WR16(B_FE_AG_REG_PDA_AUR_CNT__A , 0x0C ),
390 WR16(B_FE_AG_REG_PDC_SET_LVL__A , 0x01 ),
391 WR16(B_FE_AG_REG_PDC_FLA_RGN__A , 0x02 ),
392 WR16(B_FE_AG_REG_PDC_FLA_STP__A , 0xFFFF ),
393 WR16(B_FE_AG_REG_PDC_SLO_STP__A , 0xFFFF ),
394 WR16(B_FE_AG_REG_PDC_MAX__A , 0x02 ),
395 WR16(B_FE_AG_REG_TGA_AUR_CNT__A , 0x0C ),
396 WR16(B_FE_AG_REG_TGC_SET_LVL__A , 0x22 ),
397 WR16(B_FE_AG_REG_TGC_FLA_RGN__A , 0x15 ),
398 WR16(B_FE_AG_REG_TGC_FLA_STP__A , 0x01 ),
399 WR16(B_FE_AG_REG_TGC_SLO_STP__A , 0x0A ),
400
401 WR16(B_FE_CU_REG_DIV_NFC_CLP__A , 0 ),
402 WR16(B_FE_CU_REG_CTR_NFC_OCR__A , 25000 ),
403 WR16(B_FE_CU_REG_CTR_NFC_ICR__A , 1 ),
404 END_OF_TABLE
405};
406
407u8_t DRXD_InitCPA2[] =
408{
409 WRBLOCK(CP_REG_BR_SPL_OFFSET__A , 2),
410 0x07,0x00, /* CP_REG_BR_SPL_OFFSET__A */
411 0x0A,0x00, /* CP_REG_BR_STR_DEL__A */
412
413 WRBLOCK(CP_REG_RT_ANG_INC0__A , 4),
414 0x00,0x00, /* CP_REG_RT_ANG_INC0__A */
415 0x00,0x00, /* CP_REG_RT_ANG_INC1__A */
416 0x03,0x00, /* CP_REG_RT_DETECT_ENA__A */
417 0x03,0x00, /* CP_REG_RT_DETECT_TRH__A */
418
419 WRBLOCK(CP_REG_AC_NEXP_OFFS__A , 5),
420 0x32,0x00, /* CP_REG_AC_NEXP_OFFS__A */
421 0x62,0x00, /* CP_REG_AC_AVER_POW__A */
422 0x82,0x00, /* CP_REG_AC_MAX_POW__A */
423 0x26,0x00, /* CP_REG_AC_WEIGHT_MAN__A */
424 0x0F,0x00, /* CP_REG_AC_WEIGHT_EXP__A */
425
426 WRBLOCK(CP_REG_AC_AMP_MODE__A ,2),
427 0x02,0x00, /* CP_REG_AC_AMP_MODE__A */
428 0x01,0x00, /* CP_REG_AC_AMP_FIX__A */
429
430 WR16(CP_REG_INTERVAL__A , 0x0005 ),
431 WR16(CP_REG_RT_EXP_MARG__A , 0x0004 ),
432 WR16(CP_REG_AC_ANG_MODE__A , 0x0003 ),
433
434 WR16(CP_REG_COMM_EXEC__A , 0x0001 ),
435 END_OF_TABLE
436};
437
438u8_t DRXD_InitCPB1[] =
439{
440 WR16(B_CP_REG_BR_SPL_OFFSET__A ,0x0008 ),
441 WR16(B_CP_COMM_EXEC__A ,0x0001 ),
442 END_OF_TABLE
443};
444
445
446u8_t DRXD_InitCEA2[] =
447{
448 WRBLOCK(CE_REG_AVG_POW__A , 4),
449 0x62,0x00, /* CE_REG_AVG_POW__A */
450 0x78,0x00, /* CE_REG_MAX_POW__A */
451 0x62,0x00, /* CE_REG_ATT__A */
452 0x17,0x00, /* CE_REG_NRED__A */
453
454 WRBLOCK(CE_REG_NE_ERR_SELECT__A , 2),
455 0x07,0x00, /* CE_REG_NE_ERR_SELECT__A */
456 0xEB,0xFF, /* CE_REG_NE_TD_CAL__A */
457
458 WRBLOCK(CE_REG_NE_MIXAVG__A , 2),
459 0x06,0x00, /* CE_REG_NE_MIXAVG__A */
460 0x00,0x00, /* CE_REG_NE_NUPD_OFS__A */
461
462 WRBLOCK(CE_REG_PE_NEXP_OFFS__A , 2),
463 0x00,0x00, /* CE_REG_PE_NEXP_OFFS__A */
464 0x00,0x00, /* CE_REG_PE_TIMESHIFT__A */
465
466 WRBLOCK(CE_REG_TP_A0_TAP_NEW__A , 3),
467 0x00,0x01, /* CE_REG_TP_A0_TAP_NEW__A */
468 0x01,0x00, /* CE_REG_TP_A0_TAP_NEW_VALID__A */
469 0x0E,0x00, /* CE_REG_TP_A0_MU_LMS_STEP__A */
470
471 WRBLOCK(CE_REG_TP_A1_TAP_NEW__A , 3),
472 0x00,0x00, /* CE_REG_TP_A1_TAP_NEW__A */
473 0x01,0x00, /* CE_REG_TP_A1_TAP_NEW_VALID__A */
474 0x0A,0x00, /* CE_REG_TP_A1_MU_LMS_STEP__A */
475
476 WRBLOCK(CE_REG_FI_SHT_INCR__A , 2),
477 0x12,0x00, /* CE_REG_FI_SHT_INCR__A */
478 0x0C,0x00, /* CE_REG_FI_EXP_NORM__A */
479
480 WRBLOCK(CE_REG_IR_INPUTSEL__A , 3),
481 0x00,0x00, /* CE_REG_IR_INPUTSEL__A */
482 0x00,0x00, /* CE_REG_IR_STARTPOS__A */
483 0xFF,0x00, /* CE_REG_IR_NEXP_THRES__A */
484
485
486 WR16(CE_REG_TI_NEXP_OFFS__A ,0x0000),
487
488 END_OF_TABLE
489};
490
491u8_t DRXD_InitCEB1[] =
492{
493 WR16(B_CE_REG_TI_PHN_ENABLE__A ,0x0001),
494 WR16(B_CE_REG_FR_PM_SET__A ,0x000D),
495
496 END_OF_TABLE
497};
498
499u8_t DRXD_InitEQA2[] =
500{
501 WRBLOCK(EQ_REG_OT_QNT_THRES0__A , 4),
502 0x1E,0x00, /* EQ_REG_OT_QNT_THRES0__A */
503 0x1F,0x00, /* EQ_REG_OT_QNT_THRES1__A */
504 0x06,0x00, /* EQ_REG_OT_CSI_STEP__A */
505 0x02,0x00, /* EQ_REG_OT_CSI_OFFSET__A */
506
507 WR16(EQ_REG_TD_REQ_SMB_CNT__A ,0x0200 ),
508 WR16(EQ_REG_IS_CLIP_EXP__A ,0x001F ),
509 WR16(EQ_REG_SN_OFFSET__A ,(u16_t)(-7) ),
510 WR16(EQ_REG_RC_SEL_CAR__A ,0x0002 ),
511 WR16(EQ_REG_COMM_EXEC__A ,0x0001 ),
512 END_OF_TABLE
513};
514
515u8_t DRXD_InitEQB1[] =
516{
517 WR16(B_EQ_REG_COMM_EXEC__A ,0x0001 ),
518 END_OF_TABLE
519};
520
521u8_t DRXD_ResetECRAM[] =
522{
523 /* Reset packet sync bytes in EC_VD ram */
524 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 0*17) , 0x0000 ),
525 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 1*17) , 0x0000 ),
526 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 2*17) , 0x0000 ),
527 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 3*17) , 0x0000 ),
528 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 4*17) , 0x0000 ),
529 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 5*17) , 0x0000 ),
530 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 6*17) , 0x0000 ),
531 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 7*17) , 0x0000 ),
532 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 8*17) , 0x0000 ),
533 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 9*17) , 0x0000 ),
534 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10*17) , 0x0000 ),
535
536 /* Reset packet sync bytes in EC_RS ram */
537 WR16(EC_RS_EC_RAM__A , 0x0000 ),
538 WR16(EC_RS_EC_RAM__A + 204 , 0x0000 ),
539 END_OF_TABLE
540};
541
542u8_t DRXD_InitECA2[] =
543{
544 WRBLOCK( EC_SB_REG_CSI_HI__A , 6),
545 0x1F,0x00, /* EC_SB_REG_CSI_HI__A */
546 0x1E,0x00, /* EC_SB_REG_CSI_LO__A */
547 0x01,0x00, /* EC_SB_REG_SMB_TGL__A */
548 0x7F,0x00, /* EC_SB_REG_SNR_HI__A */
549 0x7F,0x00, /* EC_SB_REG_SNR_MID__A */
550 0x7F,0x00, /* EC_SB_REG_SNR_LO__A */
551
552 WRBLOCK( EC_RS_REG_REQ_PCK_CNT__A , 2),
553 0x00,0x10, /* EC_RS_REG_REQ_PCK_CNT__A */
554 DATA16(EC_RS_REG_VAL_PCK), /* EC_RS_REG_VAL__A */
555
556 WRBLOCK( EC_OC_REG_TMD_TOP_MODE__A , 5),
557 0x03,0x00, /* EC_OC_REG_TMD_TOP_MODE__A */
558 0xF4,0x01, /* EC_OC_REG_TMD_TOP_CNT__A */
559 0xC0,0x03, /* EC_OC_REG_TMD_HIL_MAR__A */
560 0x40,0x00, /* EC_OC_REG_TMD_LOL_MAR__A */
561 0x03,0x00, /* EC_OC_REG_TMD_CUR_CNT__A */
562
563 WRBLOCK( EC_OC_REG_AVR_ASH_CNT__A , 2),
564 0x06,0x00, /* EC_OC_REG_AVR_ASH_CNT__A */
565 0x02,0x00, /* EC_OC_REG_AVR_BSH_CNT__A */
566
567 WRBLOCK( EC_OC_REG_RCN_MODE__A , 7),
568 0x07,0x00, /* EC_OC_REG_RCN_MODE__A */
569 0x00,0x00, /* EC_OC_REG_RCN_CRA_LOP__A */
570 0xc0,0x00, /* EC_OC_REG_RCN_CRA_HIP__A */
571 0x00,0x10, /* EC_OC_REG_RCN_CST_LOP__A */
572 0x00,0x00, /* EC_OC_REG_RCN_CST_HIP__A */
573 0xFF,0x01, /* EC_OC_REG_RCN_SET_LVL__A */
574 0x0D,0x00, /* EC_OC_REG_RCN_GAI_LVL__A */
575
576 WRBLOCK( EC_OC_REG_RCN_CLP_LOP__A , 2),
577 0x00,0x00, /* EC_OC_REG_RCN_CLP_LOP__A */
578 0xC0,0x00, /* EC_OC_REG_RCN_CLP_HIP__A */
579
580 WR16(EC_SB_REG_CSI_OFS__A , 0x0001 ),
581 WR16(EC_VD_REG_FORCE__A , 0x0002 ),
582 WR16(EC_VD_REG_REQ_SMB_CNT__A , 0x0001 ),
583 WR16(EC_VD_REG_RLK_ENA__A , 0x0001 ),
584 WR16(EC_OD_REG_SYNC__A , 0x0664 ),
585 WR16(EC_OC_REG_OC_MON_SIO__A , 0x0000 ),
586 WR16(EC_OC_REG_SNC_ISC_LVL__A , 0x0D0C ),
587 /* Output zero on monitorbus pads, power saving */
588 WR16(EC_OC_REG_OCR_MON_UOS__A ,
589 ( EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE |
590 EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE |
591 EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE |
592 EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE |
593 EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE |
594 EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE |
595 EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE |
596 EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE |
597 EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE |
598 EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE |
599 EC_OC_REG_OCR_MON_UOS_VAL_ENABLE |
600 EC_OC_REG_OCR_MON_UOS_CLK_ENABLE ) ),
601 WR16(EC_OC_REG_OCR_MON_WRI__A,
602 EC_OC_REG_OCR_MON_WRI_INIT ),
603
604/* CHK_ERROR(ResetECRAM(demod)); */
605 /* Reset packet sync bytes in EC_VD ram */
606 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 0*17) , 0x0000 ),
607 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 1*17) , 0x0000 ),
608 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 2*17) , 0x0000 ),
609 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 3*17) , 0x0000 ),
610 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 4*17) , 0x0000 ),
611 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 5*17) , 0x0000 ),
612 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 6*17) , 0x0000 ),
613 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 7*17) , 0x0000 ),
614 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 8*17) , 0x0000 ),
615 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 9*17) , 0x0000 ),
616 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10*17) , 0x0000 ),
617
618 /* Reset packet sync bytes in EC_RS ram */
619 WR16(EC_RS_EC_RAM__A , 0x0000 ),
620 WR16(EC_RS_EC_RAM__A + 204 , 0x0000 ),
621
622 WR16(EC_SB_REG_COMM_EXEC__A , 0x0001 ),
623 WR16(EC_VD_REG_COMM_EXEC__A , 0x0001 ),
624 WR16(EC_OD_REG_COMM_EXEC__A , 0x0001 ),
625 WR16(EC_RS_REG_COMM_EXEC__A , 0x0001 ),
626 END_OF_TABLE
627};
628
629u8_t DRXD_InitECB1[] =
630{
631 WR16(B_EC_SB_REG_CSI_OFS0__A ,0x0001 ),
632 WR16(B_EC_SB_REG_CSI_OFS1__A ,0x0001 ),
633 WR16(B_EC_SB_REG_CSI_OFS2__A ,0x0001 ),
634 WR16(B_EC_SB_REG_CSI_LO__A ,0x000c ),
635 WR16(B_EC_SB_REG_CSI_HI__A ,0x0018 ),
636 WR16(B_EC_SB_REG_SNR_HI__A ,0x007f ),
637 WR16(B_EC_SB_REG_SNR_MID__A ,0x007f ),
638 WR16(B_EC_SB_REG_SNR_LO__A ,0x007f ),
639
640 WR16(B_EC_OC_REG_DTO_CLKMODE__A ,0x0002 ),
641 WR16(B_EC_OC_REG_DTO_PER__A ,0x0006 ),
642 WR16(B_EC_OC_REG_DTO_BUR__A ,0x0001 ),
643 WR16(B_EC_OC_REG_RCR_CLKMODE__A ,0x0000 ),
644 WR16(B_EC_OC_REG_RCN_GAI_LVL__A ,0x000D ),
645 WR16(B_EC_OC_REG_OC_MPG_SIO__A ,0x0000 ),
646
647 /* Needed because shadow registers do not have correct default value */
648 WR16(B_EC_OC_REG_RCN_CST_LOP__A ,0x1000 ),
649 WR16(B_EC_OC_REG_RCN_CST_HIP__A ,0x0000 ),
650 WR16(B_EC_OC_REG_RCN_CRA_LOP__A ,0x0000 ),
651 WR16(B_EC_OC_REG_RCN_CRA_HIP__A ,0x00C0 ),
652 WR16(B_EC_OC_REG_RCN_CLP_LOP__A ,0x0000 ),
653 WR16(B_EC_OC_REG_RCN_CLP_HIP__A ,0x00C0 ),
654 WR16(B_EC_OC_REG_DTO_INC_LOP__A ,0x0000 ),
655 WR16(B_EC_OC_REG_DTO_INC_HIP__A ,0x00C0 ),
656
657 WR16(B_EC_OD_REG_SYNC__A ,0x0664 ),
658 WR16(B_EC_RS_REG_REQ_PCK_CNT__A ,0x1000 ),
659
660/* CHK_ERROR(ResetECRAM(demod)); */
661 /* Reset packet sync bytes in EC_VD ram */
662 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 0*17) , 0x0000 ),
663 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 1*17) , 0x0000 ),
664 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 2*17) , 0x0000 ),
665 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 3*17) , 0x0000 ),
666 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 4*17) , 0x0000 ),
667 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 5*17) , 0x0000 ),
668 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 6*17) , 0x0000 ),
669 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 7*17) , 0x0000 ),
670 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 8*17) , 0x0000 ),
671 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 9*17) , 0x0000 ),
672 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10*17) , 0x0000 ),
673
674 /* Reset packet sync bytes in EC_RS ram */
675 WR16(EC_RS_EC_RAM__A , 0x0000 ),
676 WR16(EC_RS_EC_RAM__A + 204 , 0x0000 ),
677
678 WR16(B_EC_SB_REG_COMM_EXEC__A , 0x0001 ),
679 WR16(B_EC_VD_REG_COMM_EXEC__A , 0x0001 ),
680 WR16(B_EC_OD_REG_COMM_EXEC__A , 0x0001 ),
681 WR16(B_EC_RS_REG_COMM_EXEC__A , 0x0001 ),
682 END_OF_TABLE
683};
684
685u8_t DRXD_ResetECA2[] =
686{
687
688 WR16(EC_OC_REG_COMM_EXEC__A , 0x0000 ),
689 WR16(EC_OD_REG_COMM_EXEC__A , 0x0000 ),
690
691 WRBLOCK( EC_OC_REG_TMD_TOP_MODE__A , 5),
692 0x03,0x00, /* EC_OC_REG_TMD_TOP_MODE__A */
693 0xF4,0x01, /* EC_OC_REG_TMD_TOP_CNT__A */
694 0xC0,0x03, /* EC_OC_REG_TMD_HIL_MAR__A */
695 0x40,0x00, /* EC_OC_REG_TMD_LOL_MAR__A */
696 0x03,0x00, /* EC_OC_REG_TMD_CUR_CNT__A */
697
698 WRBLOCK( EC_OC_REG_AVR_ASH_CNT__A , 2),
699 0x06,0x00, /* EC_OC_REG_AVR_ASH_CNT__A */
700 0x02,0x00, /* EC_OC_REG_AVR_BSH_CNT__A */
701
702 WRBLOCK( EC_OC_REG_RCN_MODE__A , 7),
703 0x07,0x00, /* EC_OC_REG_RCN_MODE__A */
704 0x00,0x00, /* EC_OC_REG_RCN_CRA_LOP__A */
705 0xc0,0x00, /* EC_OC_REG_RCN_CRA_HIP__A */
706 0x00,0x10, /* EC_OC_REG_RCN_CST_LOP__A */
707 0x00,0x00, /* EC_OC_REG_RCN_CST_HIP__A */
708 0xFF,0x01, /* EC_OC_REG_RCN_SET_LVL__A */
709 0x0D,0x00, /* EC_OC_REG_RCN_GAI_LVL__A */
710
711 WRBLOCK( EC_OC_REG_RCN_CLP_LOP__A , 2),
712 0x00,0x00, /* EC_OC_REG_RCN_CLP_LOP__A */
713 0xC0,0x00, /* EC_OC_REG_RCN_CLP_HIP__A */
714
715 WR16(EC_OD_REG_SYNC__A , 0x0664 ),
716 WR16(EC_OC_REG_OC_MON_SIO__A , 0x0000 ),
717 WR16(EC_OC_REG_SNC_ISC_LVL__A , 0x0D0C ),
718 /* Output zero on monitorbus pads, power saving */
719 WR16(EC_OC_REG_OCR_MON_UOS__A ,
720 ( EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE |
721 EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE |
722 EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE |
723 EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE |
724 EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE |
725 EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE |
726 EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE |
727 EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE |
728 EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE |
729 EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE |
730 EC_OC_REG_OCR_MON_UOS_VAL_ENABLE |
731 EC_OC_REG_OCR_MON_UOS_CLK_ENABLE ) ),
732 WR16(EC_OC_REG_OCR_MON_WRI__A,
733 EC_OC_REG_OCR_MON_WRI_INIT ),
734
735/* CHK_ERROR(ResetECRAM(demod)); */
736 /* Reset packet sync bytes in EC_VD ram */
737 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 0*17) , 0x0000 ),
738 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 1*17) , 0x0000 ),
739 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 2*17) , 0x0000 ),
740 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 3*17) , 0x0000 ),
741 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 4*17) , 0x0000 ),
742 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 5*17) , 0x0000 ),
743 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 6*17) , 0x0000 ),
744 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 7*17) , 0x0000 ),
745 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 8*17) , 0x0000 ),
746 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + ( 9*17) , 0x0000 ),
747 WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10*17) , 0x0000 ),
748
749 /* Reset packet sync bytes in EC_RS ram */
750 WR16(EC_RS_EC_RAM__A , 0x0000 ),
751 WR16(EC_RS_EC_RAM__A + 204 , 0x0000 ),
752
753 WR16(EC_OD_REG_COMM_EXEC__A , 0x0001 ),
754 END_OF_TABLE
755};
756
757u8_t DRXD_InitSC[] =
758{
759 WR16(SC_COMM_EXEC__A, 0 ),
760 WR16(SC_COMM_STATE__A, 0 ),
761
762#ifdef COMPILE_FOR_QT
763 WR16(SC_RA_RAM_BE_OPT_DELAY__A, 0x100 ),
764#endif
765
766 /* SC is not started, this is done in SetChannels() */
767 END_OF_TABLE
768};
769
770/* Diversity settings */
771
772u8_t DRXD_InitDiversityFront[] =
773{
774 /* Start demod ********* RF in , diversity out *****************************/
775 WR16( B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
776 B_SC_RA_RAM_CONFIG_FREQSCAN__M ),
777
778 WR16( B_SC_RA_RAM_LC_ABS_2K__A, 0x7),
779 WR16( B_SC_RA_RAM_LC_ABS_8K__A, 0x7),
780 WR16( B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K ),
781 WR16( B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1<<(11-IRLEN_COARSE_8K) ),
782 WR16( B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1<<(17-IRLEN_COARSE_8K) ),
783 WR16( B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K ),
784 WR16( B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1<<(11-IRLEN_FINE_8K) ),
785 WR16( B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1<<(17-IRLEN_FINE_8K) ),
786
787 WR16( B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K ),
788 WR16( B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1<<(11-IRLEN_COARSE_2K) ),
789 WR16( B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1<<(17-IRLEN_COARSE_2K) ),
790 WR16( B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K ),
791 WR16( B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1<<(11-IRLEN_FINE_2K) ),
792 WR16( B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1<<(17-IRLEN_FINE_2K) ),
793
794 WR16( B_LC_RA_RAM_FILTER_CRMM_A__A, 7),
795 WR16( B_LC_RA_RAM_FILTER_CRMM_B__A, 4),
796 WR16( B_LC_RA_RAM_FILTER_SRMM_A__A, 7),
797 WR16( B_LC_RA_RAM_FILTER_SRMM_B__A, 4),
798 WR16( B_LC_RA_RAM_FILTER_SYM_SET__A, 500),
799
800 WR16( B_CC_REG_DIVERSITY__A, 0x0001 ),
801 WR16( B_EC_OC_REG_OC_MODE_HIP__A, 0x0010 ),
802 WR16( B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE |
803 B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE |
804 B_EQ_REG_RC_SEL_CAR_MEAS_B_CE ),
805
806
807 /* 0x2a ),*/ /* CE to PASS mux */
808
809 END_OF_TABLE
810};
811
812u8_t DRXD_InitDiversityEnd[] =
813{
814 /* End demod *********** combining RF in and diversity in, MPEG TS out *****/
815 /* disable near/far; switch on timing slave mode */
816 WR16( B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
817 B_SC_RA_RAM_CONFIG_FREQSCAN__M |
818 B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M |
819 B_SC_RA_RAM_CONFIG_SLAVE__M |
820 B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M
821/* MV from CtrlDiversity */
822 ),
823#ifdef DRXDDIV_SRMM_SLAVING
824 WR16( SC_RA_RAM_LC_ABS_2K__A, 0x3c7),
825 WR16( SC_RA_RAM_LC_ABS_8K__A, 0x3c7),
826#else
827 WR16( SC_RA_RAM_LC_ABS_2K__A, 0x7),
828 WR16( SC_RA_RAM_LC_ABS_8K__A, 0x7),
829#endif
830
831 WR16( B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K ),
832 WR16( B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1<<(11-IRLEN_COARSE_8K) ),
833 WR16( B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1<<(17-IRLEN_COARSE_8K) ),
834 WR16( B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K ),
835 WR16( B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1<<(11-IRLEN_FINE_8K) ),
836 WR16( B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1<<(17-IRLEN_FINE_8K) ),
837
838 WR16( B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K ),
839 WR16( B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1<<(11-IRLEN_COARSE_2K) ),
840 WR16( B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1<<(17-IRLEN_COARSE_2K) ),
841 WR16( B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K ),
842 WR16( B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1<<(11-IRLEN_FINE_2K) ),
843 WR16( B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1<<(17-IRLEN_FINE_2K) ),
844
845 WR16( B_LC_RA_RAM_FILTER_CRMM_A__A, 7),
846 WR16( B_LC_RA_RAM_FILTER_CRMM_B__A, 4),
847 WR16( B_LC_RA_RAM_FILTER_SRMM_A__A, 7),
848 WR16( B_LC_RA_RAM_FILTER_SRMM_B__A, 4),
849 WR16( B_LC_RA_RAM_FILTER_SYM_SET__A, 500),
850
851 WR16( B_CC_REG_DIVERSITY__A, 0x0001 ),
852 END_OF_TABLE
853};
854
855u8_t DRXD_DisableDiversity[] =
856{
857 WR16( B_SC_RA_RAM_LC_ABS_2K__A, B_SC_RA_RAM_LC_ABS_2K__PRE),
858 WR16( B_SC_RA_RAM_LC_ABS_8K__A, B_SC_RA_RAM_LC_ABS_8K__PRE),
859 WR16( B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE ),
860 WR16( B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE ),
861 WR16( B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE ),
862 WR16( B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE ),
863 WR16( B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE ),
864 WR16( B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE ),
865
866 WR16( B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE ),
867 WR16( B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE ),
868 WR16( B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE ),
869 WR16( B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE ),
870 WR16( B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE ),
871 WR16( B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE ),
872
873 WR16( B_LC_RA_RAM_FILTER_CRMM_A__A, B_LC_RA_RAM_FILTER_CRMM_A__PRE),
874 WR16( B_LC_RA_RAM_FILTER_CRMM_B__A, B_LC_RA_RAM_FILTER_CRMM_B__PRE),
875 WR16( B_LC_RA_RAM_FILTER_SRMM_A__A, B_LC_RA_RAM_FILTER_SRMM_A__PRE),
876 WR16( B_LC_RA_RAM_FILTER_SRMM_B__A, B_LC_RA_RAM_FILTER_SRMM_B__PRE),
877 WR16( B_LC_RA_RAM_FILTER_SYM_SET__A, B_LC_RA_RAM_FILTER_SYM_SET__PRE),
878
879
880 WR16( B_CC_REG_DIVERSITY__A, 0x0000 ),
881 WR16( B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_INIT ), /* combining disabled*/
882
883 END_OF_TABLE
884};
885
886u8_t DRXD_StartDiversityFront[] =
887{
888 /* Start demod, RF in and diversity out, no combining */
889 WR16( B_FE_CF_REG_IMP_VAL__A, 0x0 ),
890 WR16( B_FE_AD_REG_FDB_IN__A, 0x0 ),
891 WR16( B_FE_AD_REG_INVEXT__A, 0x0 ),
892 WR16( B_EQ_REG_COMM_MB__A, 0x12 ), /* EQ to MB out */
893 WR16( B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE | /* CE to PASS mux */
894 B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE |
895 B_EQ_REG_RC_SEL_CAR_MEAS_B_CE ),
896
897 WR16( SC_RA_RAM_ECHO_SHIFT_LIM__A, 2 ),
898
899 END_OF_TABLE
900};
901
902u8_t DRXD_StartDiversityEnd[] =
903{
904 /* End demod, combining RF in and diversity in, MPEG TS out */
905 WR16( B_FE_CF_REG_IMP_VAL__A, 0x0 ), /* disable impulse noise cruncher */
906 WR16( B_FE_AD_REG_INVEXT__A, 0x0 ), /* clock inversion (for sohard board) */
907 WR16( B_CP_REG_BR_STR_DEL__A, 10 ), /* apperently no mb delay matching is best */
908
909 WR16( B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_DIV_ON | /* org = 0x81 combining enabled */
910 B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
911 B_EQ_REG_RC_SEL_CAR_PASS_A_CC |
912 B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC ),
913
914 END_OF_TABLE
915};
916
917u8_t DRXD_DiversityDelay8MHZ[] =
918{
919 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1150 - 50 ),
920 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1100 - 50 ),
921 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A , 1000 - 50 ),
922 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A , 800 - 50 ),
923 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5420 - 50 ),
924 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5200 - 50 ),
925 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A , 4800 - 50 ),
926 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A , 4000 - 50 ),
927 END_OF_TABLE
928};
929
930u8_t DRXD_DiversityDelay6MHZ[] = /* also used ok for 7 MHz */
931{
932 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1100 - 50 ),
933 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1000 - 50 ),
934 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A , 900 - 50 ),
935 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A , 600 - 50 ),
936 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5300 - 50 ),
937 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5000 - 50 ),
938 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A , 4500 - 50 ),
939 WR16( B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A , 3500 - 50 ),
940 END_OF_TABLE
941};
942
943#include "drxd_micro.h"
diff --git a/drivers/media/dvb/frontends/drxd_firm.h b/drivers/media/dvb/frontends/drxd_firm.h
new file mode 100644
index 000000000000..fa704cbf7664
--- /dev/null
+++ b/drivers/media/dvb/frontends/drxd_firm.h
@@ -0,0 +1,120 @@
1/*
2 * drxd_firm.h
3 *
4 * Copyright (C) 2006-2007 Micronas
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22 */
23
24#ifndef _DRXD_FIRM_H_
25#define _DRXD_FIRM_H_
26
27#include "drxd_map_firm.h"
28
29typedef unsigned char u8_t;
30typedef unsigned short u16_t;
31typedef unsigned long u32_t;
32
33#define VERSION_MAJOR 1
34#define VERSION_MINOR 4
35#define VERSION_PATCH 23
36
37#define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
38
39#define DRXD_MAX_RETRIES (1000)
40#define HI_I2C_DELAY 84
41#define HI_I2C_BRIDGE_DELAY 750
42
43#define EQ_TD_TPS_PWR_UNKNOWN 0x00C0 /* Unknown configurations */
44#define EQ_TD_TPS_PWR_QPSK 0x016a
45#define EQ_TD_TPS_PWR_QAM16_ALPHAN 0x0195
46#define EQ_TD_TPS_PWR_QAM16_ALPHA1 0x0195
47#define EQ_TD_TPS_PWR_QAM16_ALPHA2 0x011E
48#define EQ_TD_TPS_PWR_QAM16_ALPHA4 0x01CE
49#define EQ_TD_TPS_PWR_QAM64_ALPHAN 0x019F
50#define EQ_TD_TPS_PWR_QAM64_ALPHA1 0x019F
51#define EQ_TD_TPS_PWR_QAM64_ALPHA2 0x00F8
52#define EQ_TD_TPS_PWR_QAM64_ALPHA4 0x014D
53
54#define DRXD_DEF_AG_PWD_CONSUMER 0x000E
55#define DRXD_DEF_AG_PWD_PRO 0x0000
56#define DRXD_DEF_AG_AGC_SIO 0x0000
57
58#define DRXD_FE_CTRL_MAX 1023
59
60#define DRXD_OSCDEV_DO_SCAN (16)
61
62#define DRXD_OSCDEV_DONT_SCAN (0)
63
64#define DRXD_OSCDEV_STEP (275)
65
66#define DRXD_SCAN_TIMEOUT (650)
67
68
69#define DRXD_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
70#define DRXD_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
71#define DRXD_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
72
73#define IRLEN_COARSE_8K (10)
74#define IRLEN_FINE_8K (10)
75#define IRLEN_COARSE_2K (7)
76#define IRLEN_FINE_2K (9)
77#define DIFF_INVALID (511)
78#define DIFF_TARGET (4)
79#define DIFF_MARGIN (1)
80
81
82extern u8_t DRXD_InitAtomicRead[];
83extern u8_t DRXD_HiI2cPatch_1[];
84extern u8_t DRXD_HiI2cPatch_3[];
85
86extern u8_t DRXD_InitSC[];
87
88extern u8_t DRXD_ResetCEFR[];
89extern u8_t DRXD_InitFEA2_1[];
90extern u8_t DRXD_InitFEA2_2[];
91extern u8_t DRXD_InitCPA2[];
92extern u8_t DRXD_InitCEA2[];
93extern u8_t DRXD_InitEQA2[];
94extern u8_t DRXD_InitECA2[];
95extern u8_t DRXD_ResetECA2[];
96extern u8_t DRXD_ResetECRAM[];
97
98extern u8_t DRXD_A2_microcode[];
99extern u32_t DRXD_A2_microcode_length;
100
101extern u8_t DRXD_InitFEB1_1[];
102extern u8_t DRXD_InitFEB1_2[];
103extern u8_t DRXD_InitCPB1[];
104extern u8_t DRXD_InitCEB1[];
105extern u8_t DRXD_InitEQB1[];
106extern u8_t DRXD_InitECB1[];
107
108extern u8_t DRXD_InitDiversityFront[];
109extern u8_t DRXD_InitDiversityEnd[];
110extern u8_t DRXD_DisableDiversity[];
111extern u8_t DRXD_StartDiversityFront[];
112extern u8_t DRXD_StartDiversityEnd[];
113
114extern u8_t DRXD_DiversityDelay8MHZ[];
115extern u8_t DRXD_DiversityDelay6MHZ[];
116
117extern u8_t DRXD_B1_microcode[];
118extern u32_t DRXD_B1_microcode_length;
119
120#endif
diff --git a/drivers/media/dvb/frontends/drxd_hard.c b/drivers/media/dvb/frontends/drxd_hard.c
new file mode 100644
index 000000000000..c4835b32e6d9
--- /dev/null
+++ b/drivers/media/dvb/frontends/drxd_hard.c
@@ -0,0 +1,2831 @@
1/*
2 * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1
3 *
4 * Copyright (C) 2003-2007 Micronas
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22 */
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/init.h>
28#include <linux/delay.h>
29#include <linux/firmware.h>
30#include <linux/i2c.h>
31#include <linux/version.h>
32#include <asm/div64.h>
33
34#include "dvb_frontend.h"
35#include "drxd.h"
36#include "drxd_firm.h"
37
38#define CHK_ERROR(s) if( (status = s)<0 ) break
39#define CHUNK_SIZE 48
40
41#define DRX_I2C_RMW 0x10
42#define DRX_I2C_BROADCAST 0x20
43#define DRX_I2C_CLEARCRC 0x80
44#define DRX_I2C_SINGLE_MASTER 0xC0
45#define DRX_I2C_MODEFLAGS 0xC0
46#define DRX_I2C_FLAGS 0xF0
47
48#ifndef SIZEOF_ARRAY
49#define SIZEOF_ARRAY(array) (sizeof((array))/sizeof((array)[0]))
50#endif
51
52#define DEFAULT_LOCK_TIMEOUT 1100
53
54#define DRX_CHANNEL_AUTO 0
55#define DRX_CHANNEL_HIGH 1
56#define DRX_CHANNEL_LOW 2
57
58#define DRX_LOCK_MPEG 1
59#define DRX_LOCK_FEC 2
60#define DRX_LOCK_DEMOD 4
61
62
63/****************************************************************************/
64
65enum CSCDState {
66 CSCD_INIT = 0,
67 CSCD_SET,
68 CSCD_SAVED
69};
70
71enum CDrxdState {
72 DRXD_UNINITIALIZED = 0,
73 DRXD_STOPPED,
74 DRXD_STARTED
75};
76
77enum AGC_CTRL_MODE {
78 AGC_CTRL_AUTO = 0,
79 AGC_CTRL_USER,
80 AGC_CTRL_OFF
81};
82
83enum OperationMode {
84 OM_Default,
85 OM_DVBT_Diversity_Front,
86 OM_DVBT_Diversity_End
87};
88
89struct SCfgAgc {
90 enum AGC_CTRL_MODE ctrlMode;
91 u16 outputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
92 u16 settleLevel; /* range [0, ... , 1023], 1/n of fullscale range */
93 u16 minOutputLevel;/* range [0, ... , 1023], 1/n of fullscale range */
94 u16 maxOutputLevel;/* range [0, ... , 1023], 1/n of fullscale range */
95 u16 speed; /* range [0, ... , 1023], 1/n of fullscale range */
96
97 u16 R1;
98 u16 R2;
99 u16 R3;
100};
101
102struct SNoiseCal {
103 int cpOpt;
104 u16 cpNexpOfs;
105 u16 tdCal2k;
106 u16 tdCal8k;
107};
108
109enum app_env {
110 APPENV_STATIC = 0,
111 APPENV_PORTABLE = 1,
112 APPENV_MOBILE = 2
113};
114
115enum EIFFilter {
116 IFFILTER_SAW = 0,
117 IFFILTER_DISCRETE = 1
118};
119
120struct drxd_state {
121 struct dvb_frontend frontend;
122 struct dvb_frontend_ops ops;
123 struct dvb_frontend_parameters param;
124
125 const struct firmware *fw;
126 struct device *dev;
127
128 struct i2c_adapter *i2c;
129 void *priv;
130 struct drxd_config config;
131
132 int i2c_access;
133 int init_done;
134 struct semaphore mutex;
135
136 u8 chip_adr;
137 u16 hi_cfg_timing_div;
138 u16 hi_cfg_bridge_delay;
139 u16 hi_cfg_wakeup_key;
140 u16 hi_cfg_ctrl;
141
142 u16 intermediate_freq;
143 u16 osc_clock_freq;
144
145 enum CSCDState cscd_state;
146 enum CDrxdState drxd_state;
147
148 u16 sys_clock_freq;
149 s16 osc_clock_deviation;
150 u16 expected_sys_clock_freq;
151
152 u16 insert_rs_byte;
153 u16 enable_parallel;
154
155 int operation_mode;
156
157 struct SCfgAgc if_agc_cfg;
158 struct SCfgAgc rf_agc_cfg;
159
160 struct SNoiseCal noise_cal;
161
162 u32 fe_fs_add_incr;
163 u32 org_fe_fs_add_incr;
164 u16 current_fe_if_incr;
165
166 u16 m_FeAgRegAgPwd;
167 u16 m_FeAgRegAgAgcSio;
168
169 u16 m_EcOcRegOcModeLop;
170 u16 m_EcOcRegSncSncLvl;
171 u8 *m_InitAtomicRead;
172 u8 *m_HiI2cPatch;
173
174 u8 *m_ResetCEFR;
175 u8 *m_InitFE_1;
176 u8 *m_InitFE_2;
177 u8 *m_InitCP;
178 u8 *m_InitCE;
179 u8 *m_InitEQ;
180 u8 *m_InitSC;
181 u8 *m_InitEC;
182 u8 *m_ResetECRAM;
183 u8 *m_InitDiversityFront;
184 u8 *m_InitDiversityEnd;
185 u8 *m_DisableDiversity;
186 u8 *m_StartDiversityFront;
187 u8 *m_StartDiversityEnd;
188
189 u8 *m_DiversityDelay8MHZ;
190 u8 *m_DiversityDelay6MHZ;
191
192 u8 *microcode;
193 u32 microcode_length;
194
195 int type_A;
196 int PGA;
197 int diversity;
198 int tuner_mirrors;
199
200 enum app_env app_env_default;
201 enum app_env app_env_diversity;
202
203};
204
205
206/****************************************************************************/
207/* I2C **********************************************************************/
208/****************************************************************************/
209
210static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 *data, int len)
211{
212 struct i2c_msg msg = { .addr=adr, .flags=0, .buf=data, .len=len };
213
214 if (i2c_transfer(adap, &msg, 1) != 1)
215 return -1;
216 return 0;
217}
218
219static int i2c_read(struct i2c_adapter *adap,
220 u8 adr, u8 *msg, int len, u8 *answ, int alen)
221{
222 struct i2c_msg msgs[2] = { { .addr=adr, .flags=0,
223 .buf=msg, .len=len },
224 { .addr=adr, .flags=I2C_M_RD,
225 .buf=answ, .len=alen } };
226 if (i2c_transfer(adap, msgs, 2) != 2)
227 return -1;
228 return 0;
229}
230
231inline u32 MulDiv32(u32 a, u32 b, u32 c)
232{
233 u64 tmp64;
234
235 tmp64=(u64)a*(u64)b;
236 do_div(tmp64, c);
237
238 return (u32) tmp64;
239}
240
241static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags)
242{
243 u8 adr=state->config.demod_address;
244 u8 mm1[4]={reg&0xff, (reg>>16)&0xff,
245 flags|((reg>>24)&0xff), (reg>>8)&0xff};
246 u8 mm2[2];
247 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2)<0)
248 return -1;
249 if (data)
250 *data=mm2[0]|(mm2[1]<<8);
251 return mm2[0]|(mm2[1]<<8);
252}
253
254static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags)
255{
256 u8 adr=state->config.demod_address;
257 u8 mm1[4]={reg&0xff, (reg>>16)&0xff,
258 flags|((reg>>24)&0xff), (reg>>8)&0xff};
259 u8 mm2[4];
260
261 if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4)<0)
262 return -1;
263 if (data)
264 *data=mm2[0]|(mm2[1]<<8)|(mm2[2]<<16)|(mm2[3]<<24);
265 return 0;
266}
267
268static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags)
269{
270 u8 adr=state->config.demod_address;
271 u8 mm[6]={ reg&0xff, (reg>>16)&0xff,
272 flags|((reg>>24)&0xff), (reg>>8)&0xff,
273 data&0xff, (data>>8)&0xff };
274
275 if (i2c_write(state->i2c, adr, mm, 6)<0)
276 return -1;
277 return 0;
278}
279
280static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags)
281{
282 u8 adr=state->config.demod_address;
283 u8 mm[8]={ reg&0xff, (reg>>16)&0xff,
284 flags|((reg>>24)&0xff), (reg>>8)&0xff,
285 data&0xff, (data>>8)&0xff,
286 (data>>16)&0xff, (data>>24)&0xff };
287
288 if (i2c_write(state->i2c, adr, mm, 8)<0)
289 return -1;
290 return 0;
291}
292
293static int write_chunk(struct drxd_state *state,
294 u32 reg, u8 *data, u32 len, u8 flags)
295{
296 u8 adr=state->config.demod_address;
297 u8 mm[CHUNK_SIZE+4]={ reg&0xff, (reg>>16)&0xff,
298 flags|((reg>>24)&0xff), (reg>>8)&0xff };
299 int i;
300
301 for (i=0; i<len; i++)
302 mm[4+i]=data[i];
303 if (i2c_write(state->i2c, adr, mm, 4+len)<0) {
304 printk("error in write_chunk\n");
305 return -1;
306 }
307 return 0;
308}
309
310static int WriteBlock(struct drxd_state *state,
311 u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags)
312{
313 while(BlockSize > 0) {
314 u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize;
315
316 if (write_chunk(state, Address, pBlock, Chunk, Flags)<0)
317 return -1;
318 pBlock += Chunk;
319 Address += (Chunk >> 1);
320 BlockSize -= Chunk;
321 }
322 return 0;
323}
324
325static int WriteTable(struct drxd_state *state, u8 *pTable)
326{
327 int status = 0;
328
329 if( pTable == NULL )
330 return 0;
331
332 while(!status) {
333 u16 Length;
334 u32 Address = pTable[0]|(pTable[1]<<8)|
335 (pTable[2]<<16)|(pTable[3]<<24);
336
337 if (Address==0xFFFFFFFF)
338 break;
339 pTable += sizeof(u32);
340
341 Length = pTable[0]|(pTable[1]<<8);
342 pTable += sizeof(u16);
343 if (!Length)
344 break;
345 status = WriteBlock(state, Address, Length*2, pTable, 0);
346 pTable += (Length*2);
347 }
348 return status;
349}
350
351
352/****************************************************************************/
353/****************************************************************************/
354/****************************************************************************/
355
356static int ResetCEFR(struct drxd_state *state)
357{
358 return WriteTable(state, state->m_ResetCEFR);
359}
360
361static int InitCP(struct drxd_state *state)
362{
363 return WriteTable(state, state->m_InitCP);
364}
365
366static int InitCE(struct drxd_state *state)
367{
368 int status;
369 enum app_env AppEnv = state->app_env_default;
370
371 do {
372 CHK_ERROR(WriteTable(state, state->m_InitCE));
373
374 if (state->operation_mode == OM_DVBT_Diversity_Front ||
375 state->operation_mode == OM_DVBT_Diversity_End ) {
376 AppEnv = state->app_env_diversity;
377 }
378 if ( AppEnv == APPENV_STATIC ) {
379 CHK_ERROR(Write16(state,CE_REG_TAPSET__A, 0x0000,0));
380 } else if( AppEnv == APPENV_PORTABLE ) {
381 CHK_ERROR(Write16(state,CE_REG_TAPSET__A, 0x0001,0));
382 } else if( AppEnv == APPENV_MOBILE && state->type_A ) {
383 CHK_ERROR(Write16(state,CE_REG_TAPSET__A, 0x0002,0));
384 } else if( AppEnv == APPENV_MOBILE && !state->type_A ) {
385 CHK_ERROR(Write16(state,CE_REG_TAPSET__A, 0x0006,0));
386 }
387
388 /* start ce */
389 CHK_ERROR(Write16(state,B_CE_REG_COMM_EXEC__A,0x0001,0));
390 } while(0);
391 return status;
392}
393
394static int StopOC(struct drxd_state *state)
395{
396 int status = 0;
397 u16 ocSyncLvl = 0;
398 u16 ocModeLop = state->m_EcOcRegOcModeLop;
399 u16 dtoIncLop = 0;
400 u16 dtoIncHip = 0;
401
402 do {
403 /* Store output configuration */
404 CHK_ERROR(Read16(state, EC_OC_REG_SNC_ISC_LVL__A,
405 &ocSyncLvl, 0));;
406 /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A,
407 &ocModeLop)); */
408 state->m_EcOcRegSncSncLvl = ocSyncLvl;
409 /* m_EcOcRegOcModeLop = ocModeLop; */
410
411 /* Flush FIFO (byte-boundary) at fixed rate */
412 CHK_ERROR(Read16(state, EC_OC_REG_RCN_MAP_LOP__A,
413 &dtoIncLop,0 ));
414 CHK_ERROR(Read16(state, EC_OC_REG_RCN_MAP_HIP__A,
415 &dtoIncHip,0 ));
416 CHK_ERROR(Write16(state, EC_OC_REG_DTO_INC_LOP__A,
417 dtoIncLop,0 ));
418 CHK_ERROR(Write16(state, EC_OC_REG_DTO_INC_HIP__A,
419 dtoIncHip,0 ));
420 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M);
421 ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC;
422 CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A,
423 ocModeLop,0 ));
424 CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A,
425 EC_OC_REG_COMM_EXEC_CTL_HOLD,0 ));
426
427 msleep(1);
428 /* Output pins to '0' */
429 CHK_ERROR(Write16(state, EC_OC_REG_OCR_MPG_UOS__A,
430 EC_OC_REG_OCR_MPG_UOS__M,0 ));
431
432 /* Force the OC out of sync */
433 ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M);
434 CHK_ERROR(Write16(state, EC_OC_REG_SNC_ISC_LVL__A,
435 ocSyncLvl,0 ));
436 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M);
437 ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE;
438 ocModeLop |= 0x2; /* Magically-out-of-sync */
439 CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A,
440 ocModeLop,0 ));
441 CHK_ERROR(Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0,0 ));
442 CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A,
443 EC_OC_REG_COMM_EXEC_CTL_ACTIVE,0 ));
444 } while(0);
445
446 return status;
447}
448
449static int StartOC(struct drxd_state *state)
450{
451 int status=0;
452
453 do {
454 /* Stop OC */
455 CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A,
456 EC_OC_REG_COMM_EXEC_CTL_HOLD,0 ));
457
458 /* Restore output configuration */
459 CHK_ERROR(Write16(state, EC_OC_REG_SNC_ISC_LVL__A,
460 state->m_EcOcRegSncSncLvl,0 ));
461 CHK_ERROR(Write16(state, EC_OC_REG_OC_MODE_LOP__A,
462 state->m_EcOcRegOcModeLop,0 ));
463
464 /* Output pins active again */
465 CHK_ERROR(Write16(state, EC_OC_REG_OCR_MPG_UOS__A,
466 EC_OC_REG_OCR_MPG_UOS_INIT,0 ));
467
468 /* Start OC */
469 CHK_ERROR(Write16(state, EC_OC_REG_COMM_EXEC__A,
470 EC_OC_REG_COMM_EXEC_CTL_ACTIVE,0 ));
471 } while(0);
472 return status;
473}
474
475static int InitEQ(struct drxd_state *state)
476{
477 return WriteTable(state, state->m_InitEQ);
478}
479
480static int InitEC(struct drxd_state *state)
481{
482 return WriteTable(state, state->m_InitEC);
483}
484
485static int InitSC(struct drxd_state *state)
486{
487 return WriteTable(state, state->m_InitSC);
488}
489
490static int InitAtomicRead(struct drxd_state *state)
491{
492 return WriteTable(state, state->m_InitAtomicRead);
493}
494
495static int CorrectSysClockDeviation(struct drxd_state *state);
496
497static int DRX_GetLockStatus(struct drxd_state *state, u32 *pLockStatus)
498{
499 u16 ScRaRamLock = 0;
500 const u16 mpeg_lock_mask = ( SC_RA_RAM_LOCK_MPEG__M |
501 SC_RA_RAM_LOCK_FEC__M |
502 SC_RA_RAM_LOCK_DEMOD__M );
503 const u16 fec_lock_mask = ( SC_RA_RAM_LOCK_FEC__M |
504 SC_RA_RAM_LOCK_DEMOD__M );
505 const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M ;
506
507 int status;
508
509 *pLockStatus=0;
510
511 status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000 );
512 if(status<0) {
513 printk("Can't read SC_RA_RAM_LOCK__A status = %08x\n",
514 status);
515 return status;
516 }
517
518 if( state->drxd_state != DRXD_STARTED )
519 return 0;
520
521 if ( (ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask ) {
522 *pLockStatus|=DRX_LOCK_MPEG;
523 CorrectSysClockDeviation(state);
524 }
525
526 if ( (ScRaRamLock & fec_lock_mask) == fec_lock_mask )
527 *pLockStatus|=DRX_LOCK_FEC;
528
529 if ( (ScRaRamLock & demod_lock_mask) == demod_lock_mask )
530 *pLockStatus|=DRX_LOCK_DEMOD;
531 return 0;
532}
533
534/****************************************************************************/
535
536static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
537{
538 int status;
539
540 if( cfg->outputLevel > DRXD_FE_CTRL_MAX )
541 return -1;
542
543 if( cfg->ctrlMode == AGC_CTRL_USER ) {
544 do {
545 u16 FeAgRegPm1AgcWri;
546 u16 FeAgRegAgModeLop;
547
548 CHK_ERROR(Read16(state,FE_AG_REG_AG_MODE_LOP__A,
549 &FeAgRegAgModeLop,0));
550 FeAgRegAgModeLop &=
551 (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
552 FeAgRegAgModeLop |=
553 FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
554 CHK_ERROR(Write16(state,FE_AG_REG_AG_MODE_LOP__A,
555 FeAgRegAgModeLop,0));
556
557 FeAgRegPm1AgcWri = (u16)(cfg->outputLevel &
558 FE_AG_REG_PM1_AGC_WRI__M);
559 CHK_ERROR(Write16(state,FE_AG_REG_PM1_AGC_WRI__A,
560 FeAgRegPm1AgcWri,0));
561 }
562 while(0);
563 } else if( cfg->ctrlMode == AGC_CTRL_AUTO ) {
564 if ( ( (cfg->maxOutputLevel) < (cfg->minOutputLevel) ) ||
565 ( (cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX ) ||
566 ( (cfg->speed) > DRXD_FE_CTRL_MAX ) ||
567 ( (cfg->settleLevel) > DRXD_FE_CTRL_MAX )
568 )
569 return (-1);
570 do {
571 u16 FeAgRegAgModeLop;
572 u16 FeAgRegEgcSetLvl;
573 u16 slope, offset;
574
575 /* == Mode == */
576
577 CHK_ERROR(Read16(state,FE_AG_REG_AG_MODE_LOP__A,
578 &FeAgRegAgModeLop,0));
579 FeAgRegAgModeLop &=
580 (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
581 FeAgRegAgModeLop |=
582 FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC;
583 CHK_ERROR(Write16(state,FE_AG_REG_AG_MODE_LOP__A,
584 FeAgRegAgModeLop,0));
585
586 /* == Settle level == */
587
588 FeAgRegEgcSetLvl = (u16)(( cfg->settleLevel >> 1 ) &
589 FE_AG_REG_EGC_SET_LVL__M );
590 CHK_ERROR(Write16(state,FE_AG_REG_EGC_SET_LVL__A,
591 FeAgRegEgcSetLvl,0));
592
593 /* == Min/Max == */
594
595 slope = (u16)(( cfg->maxOutputLevel -
596 cfg->minOutputLevel )/2);
597 offset = (u16)(( cfg->maxOutputLevel +
598 cfg->minOutputLevel )/2 - 511);
599
600 CHK_ERROR(Write16(state,FE_AG_REG_GC1_AGC_RIC__A,
601 slope,0));
602 CHK_ERROR(Write16(state,FE_AG_REG_GC1_AGC_OFF__A,
603 offset,0));
604
605 /* == Speed == */
606 {
607 const u16 maxRur = 8;
608 const u16 slowIncrDecLUT[]={ 3, 4, 4, 5, 6 };
609 const u16 fastIncrDecLUT[]={ 14, 15, 15, 16,
610 17, 18, 18, 19,
611 20, 21, 22, 23,
612 24, 26, 27, 28,
613 29, 31};
614
615 u16 fineSteps = (DRXD_FE_CTRL_MAX+1)/
616 (maxRur+1);
617 u16 fineSpeed = (u16)(cfg->speed -
618 ((cfg->speed/
619 fineSteps)*
620 fineSteps));
621 u16 invRurCount= (u16)(cfg->speed /
622 fineSteps);
623 u16 rurCount;
624 if ( invRurCount > maxRur )
625 {
626 rurCount = 0;
627 fineSpeed += fineSteps;
628 } else {
629 rurCount = maxRur - invRurCount;
630 }
631
632 /*
633 fastInc = default *
634 (2^(fineSpeed/fineSteps))
635 => range[default...2*default>
636 slowInc = default *
637 (2^(fineSpeed/fineSteps))
638 */
639 {
640 u16 fastIncrDec =
641 fastIncrDecLUT[fineSpeed/
642 ((fineSteps/
643 (14+1))+1) ];
644 u16 slowIncrDec = slowIncrDecLUT[
645 fineSpeed/(fineSteps/(3+1)) ];
646
647 CHK_ERROR(Write16(state,
648 FE_AG_REG_EGC_RUR_CNT__A,
649 rurCount, 0));
650 CHK_ERROR(Write16(state,
651 FE_AG_REG_EGC_FAS_INC__A,
652 fastIncrDec, 0));
653 CHK_ERROR(Write16(state,
654 FE_AG_REG_EGC_FAS_DEC__A,
655 fastIncrDec, 0));
656 CHK_ERROR(Write16(state,
657 FE_AG_REG_EGC_SLO_INC__A,
658 slowIncrDec, 0));
659 CHK_ERROR(Write16(state,
660 FE_AG_REG_EGC_SLO_DEC__A,
661 slowIncrDec, 0));
662 }
663 }
664 } while(0);
665
666 } else {
667 /* No OFF mode for IF control */
668 return (-1);
669 }
670 return status;
671}
672
673
674static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
675{
676 int status = 0;
677
678 if( cfg->outputLevel > DRXD_FE_CTRL_MAX )
679 return -1;
680
681 if( cfg->ctrlMode == AGC_CTRL_USER ) {
682 do {
683 u16 AgModeLop=0;
684 u16 level = ( cfg->outputLevel );
685
686 if (level == DRXD_FE_CTRL_MAX )
687 level++;
688
689 CHK_ERROR( Write16(state,FE_AG_REG_PM2_AGC_WRI__A,
690 level, 0x0000 ));
691
692 /*==== Mode ====*/
693
694 /* Powerdown PD2, WRI source */
695 state->m_FeAgRegAgPwd &=
696 ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
697 state->m_FeAgRegAgPwd |=
698 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
699 CHK_ERROR( Write16(state,FE_AG_REG_AG_PWD__A,
700 state->m_FeAgRegAgPwd,0x0000 ));
701
702 CHK_ERROR( Read16(state,FE_AG_REG_AG_MODE_LOP__A,
703 &AgModeLop,0x0000 ));
704 AgModeLop &= (~( FE_AG_REG_AG_MODE_LOP_MODE_5__M |
705 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
706 AgModeLop |= ( FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
707 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC );
708 CHK_ERROR( Write16(state,FE_AG_REG_AG_MODE_LOP__A,
709 AgModeLop,0x0000 ));
710
711
712 /* enable AGC2 pin */
713 {
714 u16 FeAgRegAgAgcSio = 0;
715 CHK_ERROR( Read16(state,
716 FE_AG_REG_AG_AGC_SIO__A,
717 &FeAgRegAgAgcSio, 0x0000 ));
718 FeAgRegAgAgcSio &=
719 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
720 FeAgRegAgAgcSio |=
721 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
722 CHK_ERROR( Write16(state,
723 FE_AG_REG_AG_AGC_SIO__A,
724 FeAgRegAgAgcSio, 0x0000 ));
725 }
726
727 } while(0);
728 } else if( cfg->ctrlMode == AGC_CTRL_AUTO ) {
729 u16 AgModeLop=0;
730
731 do {
732 u16 level;
733 /* Automatic control */
734 /* Powerup PD2, AGC2 as output, TGC source */
735 (state->m_FeAgRegAgPwd) &=
736 ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
737 (state->m_FeAgRegAgPwd) |=
738 FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
739 CHK_ERROR(Write16(state,FE_AG_REG_AG_PWD__A,
740 (state->m_FeAgRegAgPwd),0x0000 ));
741
742 CHK_ERROR(Read16(state,FE_AG_REG_AG_MODE_LOP__A,
743 &AgModeLop,0x0000 ));
744 AgModeLop &= (~( FE_AG_REG_AG_MODE_LOP_MODE_5__M |
745 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
746 AgModeLop |= ( FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
747 FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC );
748 CHK_ERROR(Write16(state,
749 FE_AG_REG_AG_MODE_LOP__A,
750 AgModeLop, 0x0000 ));
751 /* Settle level */
752 level = ( (( cfg->settleLevel )>>4) &
753 FE_AG_REG_TGC_SET_LVL__M );
754 CHK_ERROR(Write16(state,
755 FE_AG_REG_TGC_SET_LVL__A,
756 level,0x0000 ));
757
758 /* Min/max: don't care */
759
760 /* Speed: TODO */
761
762 /* enable AGC2 pin */
763 {
764 u16 FeAgRegAgAgcSio = 0;
765 CHK_ERROR( Read16(state,
766 FE_AG_REG_AG_AGC_SIO__A,
767 &FeAgRegAgAgcSio, 0x0000 ));
768 FeAgRegAgAgcSio &=
769 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
770 FeAgRegAgAgcSio |=
771 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
772 CHK_ERROR( Write16(state,
773 FE_AG_REG_AG_AGC_SIO__A,
774 FeAgRegAgAgcSio, 0x0000 ));
775 }
776
777 } while(0);
778 } else {
779 u16 AgModeLop=0;
780
781 do {
782 /* No RF AGC control */
783 /* Powerdown PD2, AGC2 as output, WRI source */
784 (state->m_FeAgRegAgPwd) &=
785 ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
786 (state->m_FeAgRegAgPwd) |=
787 FE_AG_REG_AG_PWD_PWD_PD2_ENABLE;
788 CHK_ERROR(Write16(state,
789 FE_AG_REG_AG_PWD__A,
790 (state->m_FeAgRegAgPwd),0x0000 ));
791
792 CHK_ERROR(Read16(state,
793 FE_AG_REG_AG_MODE_LOP__A,
794 &AgModeLop,0x0000 ));
795 AgModeLop &= (~( FE_AG_REG_AG_MODE_LOP_MODE_5__M |
796 FE_AG_REG_AG_MODE_LOP_MODE_E__M));
797 AgModeLop |= ( FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
798 FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC );
799 CHK_ERROR(Write16(state,
800 FE_AG_REG_AG_MODE_LOP__A,
801 AgModeLop,0x0000 ));
802
803 /* set FeAgRegAgAgcSio AGC2 (RF) as input */
804 {
805 u16 FeAgRegAgAgcSio = 0;
806 CHK_ERROR( Read16(state,
807 FE_AG_REG_AG_AGC_SIO__A,
808 &FeAgRegAgAgcSio, 0x0000 ));
809 FeAgRegAgAgcSio &=
810 ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
811 FeAgRegAgAgcSio |=
812 FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT;
813 CHK_ERROR( Write16(state,
814 FE_AG_REG_AG_AGC_SIO__A,
815 FeAgRegAgAgcSio, 0x0000 ));
816 }
817 } while(0);
818 }
819 return status;
820}
821
822static int ReadIFAgc(struct drxd_state *state, u32 *pValue)
823{
824 int status = 0;
825
826 *pValue = 0;
827 if( state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF ) {
828 u16 Value;
829 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A,&Value,0);
830 Value &= FE_AG_REG_GC1_AGC_DAT__M;
831 if(status>=0) {
832 /* 3.3V
833 |
834 R1
835 |
836 Vin - R3 - * -- Vout
837 |
838 R2
839 |
840 GND
841 */
842 u32 R1 = state->if_agc_cfg.R1;
843 u32 R2 = state->if_agc_cfg.R2;
844 u32 R3 = state->if_agc_cfg.R3;
845
846 u32 Vmax = (3300 * R2) / ( R1 + R2 );
847 u32 Rpar = ( R2 * R3 ) / ( R3 + R2 );
848 u32 Vmin = (3300 * Rpar ) / ( R1 + Rpar );
849 u32 Vout = Vmin + (( Vmax - Vmin ) * Value) / 1024;
850
851 *pValue = Vout;
852 }
853 }
854 return status;
855}
856
857static int DownloadMicrocode(struct drxd_state *state,
858 const u8 *pMCImage, u32 Length)
859{
860 u8 *pSrc;
861 u16 Flags;
862 u32 Address;
863 u16 nBlocks;
864 u16 BlockSize;
865 u16 BlockCRC;
866 u32 offset=0;
867 int i, status=0;
868
869 pSrc=(u8 *) pMCImage;
870 Flags = (pSrc[0] << 8) | pSrc[1];
871 pSrc += sizeof(u16); offset += sizeof(u16);
872 nBlocks = (pSrc[0] << 8) | pSrc[1];
873 pSrc += sizeof(u16); offset += sizeof(u16);
874
875 for(i=0; i<nBlocks; i++ ) {
876 Address=(pSrc[0] << 24) | (pSrc[1] << 16) |
877 (pSrc[2] << 8) | pSrc[3];
878 pSrc += sizeof(u32); offset += sizeof(u32);
879
880 BlockSize = ( (pSrc[0] << 8) | pSrc[1] ) * sizeof(u16);
881 pSrc += sizeof(u16); offset += sizeof(u16);
882
883 Flags = (pSrc[0] << 8) | pSrc[1];
884 pSrc += sizeof(u16); offset += sizeof(u16);
885
886 BlockCRC = (pSrc[0] << 8) | pSrc[1];
887 pSrc += sizeof(u16); offset += sizeof(u16);
888
889 status = WriteBlock(state,Address,BlockSize,
890 pSrc,DRX_I2C_CLEARCRC);
891 if (status<0)
892 break;
893 pSrc += BlockSize;
894 offset += BlockSize;
895 }
896
897 return status;
898}
899
900static int HI_Command(struct drxd_state *state, u16 cmd, u16 *pResult)
901{
902 u32 nrRetries = 0;
903 u16 waitCmd;
904 int status;
905
906 if ((status=Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0))<0)
907 return status;
908
909 do {
910 nrRetries+=1;
911 if (nrRetries>DRXD_MAX_RETRIES) {
912 status=-1;
913 break;
914 };
915 status=Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0);
916 } while (waitCmd!=0);
917
918 if (status>=0)
919 status=Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0);
920 return status;
921}
922
923static int HI_CfgCommand(struct drxd_state *state)
924{
925 int status=0;
926
927 down(&state->mutex);
928 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A,
929 HI_RA_RAM_SRV_RST_KEY_ACT, 0);
930 Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0);
931 Write16(state, HI_RA_RAM_SRV_CFG_BDL__A,
932 state->hi_cfg_bridge_delay, 0);
933 Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0);
934 Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0);
935
936 Write16(state, HI_RA_RAM_SRV_CFG_KEY__A,
937 HI_RA_RAM_SRV_RST_KEY_ACT, 0);
938
939 if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)==
940 HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)
941 status=Write16(state, HI_RA_RAM_SRV_CMD__A,
942 HI_RA_RAM_SRV_CMD_CONFIG, 0);
943 else
944 status=HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, 0);
945 up(&state->mutex);
946 return status;
947}
948
949static int InitHI(struct drxd_state *state)
950{
951 state->hi_cfg_wakeup_key = (state->chip_adr);
952 /* port/bridge/power down ctrl */
953 state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON;
954 return HI_CfgCommand(state);
955}
956
957static int HI_ResetCommand(struct drxd_state *state)
958{
959 int status;
960
961 down(&state->mutex);
962 status=Write16(state, HI_RA_RAM_SRV_RST_KEY__A,
963 HI_RA_RAM_SRV_RST_KEY_ACT, 0);
964 if (status==0)
965 status=HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, 0);
966 up(&state->mutex);
967 msleep(1);
968 return status;
969}
970
971static int DRX_ConfigureI2CBridge(struct drxd_state *state,
972 int bEnableBridge)
973{
974 state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M);
975 if ( bEnableBridge )
976 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON;
977 else
978 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF;
979
980 return HI_CfgCommand(state);
981}
982
983#define HI_TR_WRITE 0x9
984#define HI_TR_READ 0xA
985#define HI_TR_READ_WRITE 0xB
986#define HI_TR_BROADCAST 0x4
987
988#if 0
989static int AtomicReadBlock(struct drxd_state *state,
990 u32 Addr, u16 DataSize, u8 *pData, u8 Flags)
991{
992 int status;
993 int i=0;
994
995 /* Parameter check */
996 if ( (!pData) || ( (DataSize & 1)!=0 ) )
997 return -1;
998
999 down(&state->mutex);
1000
1001 do {
1002 /* Instruct HI to read n bytes */
1003 /* TODO use proper names forthese egisters */
1004 CHK_ERROR( Write16(state,HI_RA_RAM_SRV_CFG_KEY__A,
1005 (HI_TR_FUNC_ADDR & 0xFFFF), 0));
1006 CHK_ERROR( Write16(state,HI_RA_RAM_SRV_CFG_DIV__A,
1007 (u16)(Addr >> 16), 0));
1008 CHK_ERROR( Write16(state,HI_RA_RAM_SRV_CFG_BDL__A,
1009 (u16)(Addr & 0xFFFF), 0));
1010 CHK_ERROR( Write16(state,HI_RA_RAM_SRV_CFG_WUP__A,
1011 (u16)((DataSize/2) - 1), 0));
1012 CHK_ERROR( Write16(state,HI_RA_RAM_SRV_CFG_ACT__A,
1013 HI_TR_READ, 0));
1014
1015 CHK_ERROR( HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE,0));
1016
1017 } while(0);
1018
1019 if (status>=0) {
1020 for (i = 0; i < (DataSize/2); i += 1) {
1021 u16 word;
1022
1023 status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1024 &word, 0);
1025 if( status<0)
1026 break;
1027 pData[2*i] = (u8) (word & 0xFF);
1028 pData[(2*i) + 1] = (u8) (word >> 8 );
1029 }
1030 }
1031 up(&state->mutex);
1032 return status;
1033}
1034
1035static int AtomicReadReg32(struct drxd_state *state,
1036 u32 Addr, u32 *pData, u8 Flags)
1037{
1038 u8 buf[sizeof (u32)];
1039 int status;
1040
1041 if (!pData)
1042 return -1;
1043 status=AtomicReadBlock(state, Addr, sizeof (u32), buf, Flags);
1044 *pData = (((u32) buf[0]) << 0) +
1045 (((u32) buf[1]) << 8) +
1046 (((u32) buf[2]) << 16) +
1047 (((u32) buf[3]) << 24);
1048 return status;
1049}
1050#endif
1051
1052static int StopAllProcessors(struct drxd_state *state)
1053{
1054 return Write16(state, HI_COMM_EXEC__A,
1055 SC_COMM_EXEC_CTL_STOP, DRX_I2C_BROADCAST);
1056}
1057
1058static int EnableAndResetMB(struct drxd_state *state)
1059{
1060 if (state->type_A) {
1061 /* disable? monitor bus observe @ EC_OC */
1062 Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000);
1063 }
1064
1065 /* do inverse broadcast, followed by explicit write to HI */
1066 Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST);
1067 Write16(state, HI_COMM_MB__A, 0x0000, 0x0000);
1068 return 0;
1069}
1070
1071static int InitCC(struct drxd_state *state)
1072{
1073 if (state->osc_clock_freq == 0 ||
1074 state->osc_clock_freq > 20000 ||
1075 (state->osc_clock_freq % 4000 ) != 0 ) {
1076 printk("invalid osc frequency %d\n", state->osc_clock_freq);
1077 return -1;
1078 }
1079
1080 Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0);
1081 Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL |
1082 CC_REG_PLL_MODE_PUMP_CUR_12, 0);
1083 Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq/4000, 0);
1084 Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0);
1085 Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0);
1086
1087 return 0;
1088}
1089
1090static int ResetECOD(struct drxd_state *state)
1091{
1092 int status = 0;
1093
1094 if(state->type_A )
1095 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0);
1096 else
1097 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0);
1098
1099 if (!(status<0))
1100 status = WriteTable(state, state->m_ResetECRAM);
1101 if (!(status<0))
1102 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0);
1103 return status;
1104}
1105
1106
1107/* Configure PGA switch */
1108
1109static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
1110{
1111 int status;
1112 u16 AgModeLop = 0;
1113 u16 AgModeHip = 0;
1114 do {
1115 if ( pgaSwitch ) {
1116 /* PGA on */
1117 /* fine gain */
1118 CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_LOP__A,
1119 &AgModeLop, 0x0000));
1120 AgModeLop&=(~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1121 AgModeLop|= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC;
1122 CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_LOP__A,
1123 AgModeLop, 0x0000));
1124
1125 /* coarse gain */
1126 CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_HIP__A,
1127 &AgModeHip, 0x0000));
1128 AgModeHip&=(~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1129 AgModeHip|= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC ;
1130 CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_HIP__A,
1131 AgModeHip, 0x0000));
1132
1133 /* enable fine and coarse gain, enable AAF,
1134 no ext resistor */
1135 CHK_ERROR(Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
1136 B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN,
1137 0x0000));
1138 } else {
1139 /* PGA off, bypass */
1140
1141 /* fine gain */
1142 CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_LOP__A,
1143 &AgModeLop, 0x0000));
1144 AgModeLop&=(~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1145 AgModeLop|= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC ;
1146 CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_LOP__A,
1147 AgModeLop, 0x0000));
1148
1149 /* coarse gain */
1150 CHK_ERROR(Read16(state, B_FE_AG_REG_AG_MODE_HIP__A,
1151 &AgModeHip, 0x0000));
1152 AgModeHip&=(~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1153 AgModeHip|= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC ;
1154 CHK_ERROR(Write16(state, B_FE_AG_REG_AG_MODE_HIP__A,
1155 AgModeHip, 0x0000));
1156
1157 /* disable fine and coarse gain, enable AAF,
1158 no ext resistor */
1159 CHK_ERROR(Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
1160 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1161 0x0000));
1162 }
1163 }
1164 while(0);
1165 return status;
1166}
1167
1168static int InitFE(struct drxd_state *state)
1169{
1170 int status;
1171
1172 do
1173 {
1174 CHK_ERROR( WriteTable(state, state->m_InitFE_1));
1175
1176 if( state->type_A ) {
1177 status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
1178 FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0);
1179 } else {
1180 if (state->PGA)
1181 status = SetCfgPga(state, 0);
1182 else
1183 status =
1184 Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
1185 B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0);
1186 }
1187
1188 if (status<0) break;
1189 CHK_ERROR( Write16( state, FE_AG_REG_AG_AGC_SIO__A,
1190 state->m_FeAgRegAgAgcSio, 0x0000));
1191 CHK_ERROR( Write16( state, FE_AG_REG_AG_PWD__A,state->m_FeAgRegAgPwd,
1192 0x0000));
1193
1194 CHK_ERROR( WriteTable(state, state->m_InitFE_2));
1195
1196
1197 } while(0);
1198
1199 return status;
1200}
1201
1202static int InitFT(struct drxd_state *state)
1203{
1204 /*
1205 norm OFFSET, MB says =2 voor 8K en =3 voor 2K waarschijnlijk
1206 SC stuff
1207 */
1208 return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000 );
1209}
1210
1211static int SC_WaitForReady(struct drxd_state *state)
1212{
1213 u16 curCmd;
1214 int i;
1215
1216 for(i = 0; i < DRXD_MAX_RETRIES; i += 1 )
1217 {
1218 int status = Read16(state, SC_RA_RAM_CMD__A,&curCmd,0);
1219 if (status==0 || curCmd == 0 )
1220 return status;
1221 }
1222 return -1;
1223}
1224
1225static int SC_SendCommand(struct drxd_state *state, u16 cmd)
1226{
1227 int status=0;
1228 u16 errCode;
1229
1230 Write16(state, SC_RA_RAM_CMD__A,cmd,0);
1231 SC_WaitForReady(state);
1232
1233 Read16(state, SC_RA_RAM_CMD_ADDR__A,&errCode,0);
1234
1235 if( errCode == 0xFFFF )
1236 {
1237 printk("Command Error\n");
1238 status = -1;
1239 }
1240
1241 return status;
1242}
1243
1244static int SC_ProcStartCommand(struct drxd_state *state,
1245 u16 subCmd,u16 param0,u16 param1)
1246{
1247 int status=0;
1248 u16 scExec;
1249
1250 down(&state->mutex);
1251 do {
1252 Read16(state, SC_COMM_EXEC__A, &scExec, 0);
1253 if (scExec != 1) {
1254 status=-1;
1255 break;
1256 }
1257 SC_WaitForReady(state);
1258 Write16(state, SC_RA_RAM_CMD_ADDR__A,subCmd,0);
1259 Write16(state, SC_RA_RAM_PARAM1__A,param1,0);
1260 Write16(state, SC_RA_RAM_PARAM0__A,param0,0);
1261
1262 SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START);
1263 } while(0);
1264 up(&state->mutex);
1265 return status;
1266}
1267
1268
1269static int SC_SetPrefParamCommand(struct drxd_state *state,
1270 u16 subCmd,u16 param0,u16 param1)
1271{
1272 int status;
1273
1274 down(&state->mutex);
1275 do {
1276 CHK_ERROR( SC_WaitForReady(state) );
1277 CHK_ERROR( Write16(state,SC_RA_RAM_CMD_ADDR__A,subCmd,0) );
1278 CHK_ERROR( Write16(state,SC_RA_RAM_PARAM1__A,param1,0) );
1279 CHK_ERROR( Write16(state,SC_RA_RAM_PARAM0__A,param0,0) );
1280
1281 CHK_ERROR( SC_SendCommand(state,
1282 SC_RA_RAM_CMD_SET_PREF_PARAM) );
1283 } while(0);
1284 up(&state->mutex);
1285 return status;
1286}
1287
1288#if 0
1289static int SC_GetOpParamCommand(struct drxd_state *state, u16 *result)
1290{
1291 int status=0;
1292
1293 down(&state->mutex);
1294 do {
1295 CHK_ERROR( SC_WaitForReady(state) );
1296 CHK_ERROR( SC_SendCommand(state,
1297 SC_RA_RAM_CMD_GET_OP_PARAM) );
1298 CHK_ERROR( Read16(state, SC_RA_RAM_PARAM0__A,result, 0 ) );
1299 } while(0);
1300 up(&state->mutex);
1301 return status;
1302}
1303#endif
1304
1305static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
1306{
1307 int status;
1308
1309 do {
1310 u16 EcOcRegIprInvMpg = 0;
1311 u16 EcOcRegOcModeLop = 0;
1312 u16 EcOcRegOcModeHip = 0;
1313 u16 EcOcRegOcMpgSio = 0;
1314
1315 /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A,
1316 &EcOcRegOcModeLop, 0));*/
1317
1318 if( state->operation_mode == OM_DVBT_Diversity_Front )
1319 {
1320 if ( bEnableOutput )
1321 {
1322 EcOcRegOcModeHip |=
1323 B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR;
1324 }
1325 else
1326 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1327 EcOcRegOcModeLop |=
1328 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1329 }
1330 else
1331 {
1332 EcOcRegOcModeLop = state->m_EcOcRegOcModeLop;
1333
1334 if (bEnableOutput)
1335 EcOcRegOcMpgSio &=
1336 (~(EC_OC_REG_OC_MPG_SIO__M));
1337 else
1338 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1339
1340 /* Don't Insert RS Byte */
1341 if( state->insert_rs_byte )
1342 {
1343 EcOcRegOcModeLop &=
1344 (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M));
1345 EcOcRegOcModeHip &=
1346 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1347 EcOcRegOcModeHip |=
1348 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE;
1349 } else {
1350 EcOcRegOcModeLop |=
1351 EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1352 EcOcRegOcModeHip &=
1353 (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1354 EcOcRegOcModeHip |=
1355 EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE;
1356 }
1357
1358 /* Mode = Parallel */
1359 if( state->enable_parallel )
1360 EcOcRegOcModeLop &=
1361 (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M));
1362 else
1363 EcOcRegOcModeLop |=
1364 EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL;
1365 }
1366 /* Invert Data */
1367 /* EcOcRegIprInvMpg |= 0x00FF; */
1368 EcOcRegIprInvMpg &= (~(0x00FF));
1369
1370 /* Invert Error ( we don't use the pin ) */
1371 /* EcOcRegIprInvMpg |= 0x0100; */
1372 EcOcRegIprInvMpg &= (~(0x0100));
1373
1374 /* Invert Start ( we don't use the pin ) */
1375 /* EcOcRegIprInvMpg |= 0x0200; */
1376 EcOcRegIprInvMpg &= (~(0x0200));
1377
1378 /* Invert Valid ( we don't use the pin ) */
1379 /* EcOcRegIprInvMpg |= 0x0400; */
1380 EcOcRegIprInvMpg &= (~(0x0400));
1381
1382 /* Invert Clock */
1383 /* EcOcRegIprInvMpg |= 0x0800; */
1384 EcOcRegIprInvMpg &= (~(0x0800));
1385
1386 /* EcOcRegOcModeLop =0x05; */
1387 CHK_ERROR( Write16(state, EC_OC_REG_IPR_INV_MPG__A,
1388 EcOcRegIprInvMpg, 0));
1389 CHK_ERROR( Write16(state, EC_OC_REG_OC_MODE_LOP__A,
1390 EcOcRegOcModeLop, 0) );
1391 CHK_ERROR( Write16(state, EC_OC_REG_OC_MODE_HIP__A,
1392 EcOcRegOcModeHip, 0x0000 ) );
1393 CHK_ERROR( Write16(state, EC_OC_REG_OC_MPG_SIO__A,
1394 EcOcRegOcMpgSio, 0) );
1395 } while(0);
1396 return status;
1397}
1398
1399static int SetDeviceTypeId(struct drxd_state *state)
1400{
1401 int status = 0;
1402 u16 deviceId = 0 ;
1403
1404 do {
1405 CHK_ERROR(Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0));
1406 /* TODO: why twice? */
1407 CHK_ERROR(Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0));
1408 printk( "drxd: deviceId = %04x\n",deviceId);
1409
1410 state->type_A = 0;
1411 state->PGA = 0;
1412 state->diversity = 0;
1413 if (deviceId == 0) { /* on A2 only 3975 available */
1414 state->type_A = 1;
1415 printk("DRX3975D-A2\n");
1416 } else {
1417 deviceId >>= 12;
1418 printk("DRX397%dD-B1\n",deviceId);
1419 switch(deviceId) {
1420 case 4:
1421 state->diversity = 1;
1422 case 3:
1423 case 7:
1424 state->PGA = 1;
1425 break;
1426 case 6:
1427 state->diversity = 1;
1428 case 5:
1429 case 8:
1430 break;
1431 default:
1432 status = -1;
1433 break;
1434 }
1435 }
1436 } while(0);
1437
1438 if (status<0)
1439 return status;
1440
1441 /* Init Table selection */
1442 state->m_InitAtomicRead = DRXD_InitAtomicRead;
1443 state->m_InitSC = DRXD_InitSC;
1444 state->m_ResetECRAM = DRXD_ResetECRAM;
1445 if (state->type_A) {
1446 state->m_ResetCEFR = DRXD_ResetCEFR;
1447 state->m_InitFE_1 = DRXD_InitFEA2_1;
1448 state->m_InitFE_2 = DRXD_InitFEA2_2;
1449 state->m_InitCP = DRXD_InitCPA2;
1450 state->m_InitCE = DRXD_InitCEA2;
1451 state->m_InitEQ = DRXD_InitEQA2;
1452 state->m_InitEC = DRXD_InitECA2;
1453 state->microcode = DRXD_A2_microcode;
1454 state->microcode_length = DRXD_A2_microcode_length;
1455 } else {
1456 state->m_ResetCEFR = NULL;
1457 state->m_InitFE_1 = DRXD_InitFEB1_1;
1458 state->m_InitFE_2 = DRXD_InitFEB1_2;
1459 state->m_InitCP = DRXD_InitCPB1;
1460 state->m_InitCE = DRXD_InitCEB1;
1461 state->m_InitEQ = DRXD_InitEQB1;
1462 state->m_InitEC = DRXD_InitECB1;
1463 state->microcode = DRXD_B1_microcode;
1464 state->microcode_length = DRXD_B1_microcode_length;
1465 }
1466 if (state->diversity) {
1467 state->m_InitDiversityFront = DRXD_InitDiversityFront;
1468 state->m_InitDiversityEnd = DRXD_InitDiversityEnd;
1469 state->m_DisableDiversity = DRXD_DisableDiversity;
1470 state->m_StartDiversityFront = DRXD_StartDiversityFront;
1471 state->m_StartDiversityEnd = DRXD_StartDiversityEnd;
1472 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ;
1473 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ;
1474 } else {
1475 state->m_InitDiversityFront = NULL;
1476 state->m_InitDiversityEnd = NULL;
1477 state->m_DisableDiversity = NULL;
1478 state->m_StartDiversityFront = NULL;
1479 state->m_StartDiversityEnd = NULL;
1480 state->m_DiversityDelay8MHZ = NULL;
1481 state->m_DiversityDelay6MHZ = NULL;
1482 }
1483
1484 return status;
1485}
1486
1487static int CorrectSysClockDeviation(struct drxd_state *state)
1488{
1489 int status;
1490 s32 incr = 0;
1491 s32 nomincr = 0;
1492 u32 bandwidth=0;
1493 u32 sysClockInHz=0;
1494 u32 sysClockFreq=0; /* in kHz */
1495 s16 oscClockDeviation;
1496 s16 Diff;
1497
1498 do {
1499 /* Retrieve bandwidth and incr, sanity check */
1500
1501 /* These accesses should be AtomicReadReg32, but that
1502 causes trouble (at least for diversity */
1503 CHK_ERROR( Read32(state, LC_RA_RAM_IFINCR_NOM_L__A,
1504 ((u32 *)&nomincr),0 ));
1505 CHK_ERROR( Read32(state, FE_IF_REG_INCR0__A,
1506 (u32 *) &incr,0 ));
1507
1508 if( state->type_A ) {
1509 if( (nomincr - incr < -500) ||
1510 (nomincr - incr > 500 ) )
1511 break;
1512 } else {
1513 if( (nomincr - incr < -2000 ) ||
1514 (nomincr - incr > 2000 ) )
1515 break;
1516 }
1517
1518 switch( state->param.u.ofdm.bandwidth )
1519 {
1520 case BANDWIDTH_8_MHZ :
1521 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
1522 break;
1523 case BANDWIDTH_7_MHZ :
1524 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
1525 break;
1526 case BANDWIDTH_6_MHZ :
1527 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
1528 break;
1529 default :
1530 return -1;
1531 break;
1532 }
1533
1534 /* Compute new sysclock value
1535 sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */
1536 incr += (1<<23);
1537 sysClockInHz = MulDiv32(incr,bandwidth,1<<21);
1538 sysClockFreq= (u32)(sysClockInHz/1000);
1539 /* rounding */
1540 if ( ( sysClockInHz%1000 ) > 500 )
1541 {
1542 sysClockFreq++;
1543 }
1544
1545 /* Compute clock deviation in ppm */
1546 oscClockDeviation = (u16) (
1547 (((s32)(sysClockFreq) -
1548 (s32)(state->expected_sys_clock_freq))*
1549 1000000L)/(s32)(state->expected_sys_clock_freq) );
1550
1551 Diff = oscClockDeviation - state->osc_clock_deviation;
1552 /*printk("sysclockdiff=%d\n", Diff);*/
1553 if( Diff >= -200 && Diff <= 200 ) {
1554 state->sys_clock_freq = (u16) sysClockFreq;
1555 if( oscClockDeviation !=
1556 state->osc_clock_deviation ) {
1557 if (state->config.osc_deviation) {
1558 state->config.osc_deviation(
1559 state->priv,
1560 oscClockDeviation, 1);
1561 state->osc_clock_deviation=
1562 oscClockDeviation;
1563 }
1564 }
1565 /* switch OFF SRMM scan in SC */
1566 CHK_ERROR( Write16( state,
1567 SC_RA_RAM_SAMPLE_RATE_COUNT__A,
1568 DRXD_OSCDEV_DONT_SCAN,0));
1569 /* overrule FE_IF internal value for
1570 proper re-locking */
1571 CHK_ERROR( Write16( state, SC_RA_RAM_IF_SAVE__AX,
1572 state->current_fe_if_incr, 0));
1573 state->cscd_state = CSCD_SAVED;
1574 }
1575 } while(0);
1576
1577 return (status);
1578}
1579
1580static int DRX_Stop(struct drxd_state *state)
1581{
1582 int status;
1583
1584 if( state->drxd_state != DRXD_STARTED )
1585 return 0;
1586
1587 do {
1588 if (state->cscd_state != CSCD_SAVED ) {
1589 u32 lock;
1590 CHK_ERROR( DRX_GetLockStatus(state, &lock));
1591 }
1592
1593 CHK_ERROR(StopOC(state));
1594
1595 state->drxd_state = DRXD_STOPPED;
1596
1597 CHK_ERROR( ConfigureMPEGOutput(state, 0) );
1598
1599 if(state->type_A ) {
1600 /* Stop relevant processors off the device */
1601 CHK_ERROR( Write16(state, EC_OD_REG_COMM_EXEC__A,
1602 0x0000, 0x0000));
1603
1604 CHK_ERROR( Write16(state, SC_COMM_EXEC__A,
1605 SC_COMM_EXEC_CTL_STOP, 0 ));
1606 CHK_ERROR( Write16(state, LC_COMM_EXEC__A,
1607 SC_COMM_EXEC_CTL_STOP, 0 ));
1608 } else {
1609 /* Stop all processors except HI & CC & FE */
1610 CHK_ERROR(Write16(state,
1611 B_SC_COMM_EXEC__A,
1612 SC_COMM_EXEC_CTL_STOP, 0 ));
1613 CHK_ERROR(Write16(state,
1614 B_LC_COMM_EXEC__A,
1615 SC_COMM_EXEC_CTL_STOP, 0 ));
1616 CHK_ERROR(Write16(state,
1617 B_FT_COMM_EXEC__A,
1618 SC_COMM_EXEC_CTL_STOP, 0 ));
1619 CHK_ERROR(Write16(state,
1620 B_CP_COMM_EXEC__A,
1621 SC_COMM_EXEC_CTL_STOP, 0 ));
1622 CHK_ERROR(Write16(state,
1623 B_CE_COMM_EXEC__A,
1624 SC_COMM_EXEC_CTL_STOP, 0 ));
1625 CHK_ERROR(Write16(state,
1626 B_EQ_COMM_EXEC__A,
1627 SC_COMM_EXEC_CTL_STOP, 0 ));
1628 CHK_ERROR(Write16(state,
1629 EC_OD_REG_COMM_EXEC__A,
1630 0x0000, 0 ));
1631 }
1632
1633 } while(0);
1634 return status;
1635}
1636
1637
1638int SetOperationMode(struct drxd_state *state, int oMode)
1639{
1640 int status;
1641
1642 do {
1643 if (state->drxd_state != DRXD_STOPPED) {
1644 status = -1;
1645 break;
1646 }
1647
1648 if (oMode == state->operation_mode) {
1649 status = 0;
1650 break;
1651 }
1652
1653 if (oMode != OM_Default && !state->diversity) {
1654 status = -1;
1655 break;
1656 }
1657
1658 switch(oMode)
1659 {
1660 case OM_DVBT_Diversity_Front:
1661 status = WriteTable(state,
1662 state->m_InitDiversityFront);
1663 break;
1664 case OM_DVBT_Diversity_End:
1665 status = WriteTable(state,
1666 state->m_InitDiversityEnd);
1667 break;
1668 case OM_Default:
1669 /* We need to check how to
1670 get DRXD out of diversity */
1671 default:
1672 status = WriteTable(state, state->m_DisableDiversity);
1673 break;
1674 }
1675 } while(0);
1676
1677 if (!status)
1678 state->operation_mode = oMode;
1679 return status;
1680}
1681
1682
1683
1684static int StartDiversity(struct drxd_state *state)
1685{
1686 int status=0;
1687 u16 rcControl;
1688
1689 do {
1690 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1691 CHK_ERROR(WriteTable(state,
1692 state->m_StartDiversityFront));
1693 } else if( state->operation_mode == OM_DVBT_Diversity_End ) {
1694 CHK_ERROR(WriteTable(state,
1695 state->m_StartDiversityEnd));
1696 if( state->param.u.ofdm.bandwidth ==
1697 BANDWIDTH_8_MHZ ) {
1698 CHK_ERROR(
1699 WriteTable(state,
1700 state->
1701 m_DiversityDelay8MHZ));
1702 } else {
1703 CHK_ERROR(
1704 WriteTable(state,
1705 state->
1706 m_DiversityDelay6MHZ));
1707 }
1708
1709 CHK_ERROR(Read16(state,
1710 B_EQ_REG_RC_SEL_CAR__A,
1711 &rcControl,0));
1712 rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M);
1713 rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON |
1714 /* combining enabled */
1715 B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
1716 B_EQ_REG_RC_SEL_CAR_PASS_A_CC |
1717 B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC;
1718 CHK_ERROR(Write16(state,
1719 B_EQ_REG_RC_SEL_CAR__A,
1720 rcControl,0));
1721 }
1722 } while(0);
1723 return status;
1724}
1725
1726
1727static int SetFrequencyShift(struct drxd_state *state,
1728 u32 offsetFreq, int channelMirrored)
1729{
1730 int negativeShift = (state->tuner_mirrors == channelMirrored);
1731
1732 /* Handle all mirroring
1733 *
1734 * Note: ADC mirroring (aliasing) is implictly handled by limiting
1735 * feFsRegAddInc to 28 bits below
1736 * (if the result before masking is more than 28 bits, this means
1737 * that the ADC is mirroring.
1738 * The masking is in fact the aliasing of the ADC)
1739 *
1740 */
1741
1742 /* Compute register value, unsigned computation */
1743 state->fe_fs_add_incr = MulDiv32( state->intermediate_freq +
1744 offsetFreq,
1745 1<<28, state->sys_clock_freq);
1746 /* Remove integer part */
1747 state->fe_fs_add_incr &= 0x0FFFFFFFL;
1748 if (negativeShift)
1749 {
1750 state->fe_fs_add_incr = ((1<<28) - state->fe_fs_add_incr);
1751 }
1752
1753 /* Save the frequency shift without tunerOffset compensation
1754 for CtrlGetChannel. */
1755 state->org_fe_fs_add_incr = MulDiv32( state->intermediate_freq,
1756 1<<28, state->sys_clock_freq);
1757 /* Remove integer part */
1758 state->org_fe_fs_add_incr &= 0x0FFFFFFFL;
1759 if (negativeShift)
1760 state->org_fe_fs_add_incr = ((1L<<28) -
1761 state->org_fe_fs_add_incr);
1762
1763 return Write32(state, FE_FS_REG_ADD_INC_LOP__A,
1764 state->fe_fs_add_incr, 0);
1765}
1766
1767static int SetCfgNoiseCalibration (struct drxd_state *state,
1768 struct SNoiseCal* noiseCal )
1769{
1770 u16 beOptEna;
1771 int status=0;
1772
1773 do {
1774 CHK_ERROR(Read16(state, SC_RA_RAM_BE_OPT_ENA__A,
1775 &beOptEna, 0));
1776 if (noiseCal->cpOpt)
1777 {
1778 beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1779 } else {
1780 beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1781 CHK_ERROR(Write16(state, CP_REG_AC_NEXP_OFFS__A,
1782 noiseCal->cpNexpOfs, 0));
1783 }
1784 CHK_ERROR(Write16(state, SC_RA_RAM_BE_OPT_ENA__A,
1785 beOptEna, 0));
1786
1787 if( !state->type_A )
1788 {
1789 CHK_ERROR(Write16( state,
1790 B_SC_RA_RAM_CO_TD_CAL_2K__A,
1791 noiseCal->tdCal2k,0));
1792 CHK_ERROR(Write16( state,
1793 B_SC_RA_RAM_CO_TD_CAL_8K__A,
1794 noiseCal->tdCal8k,0));
1795 }
1796 } while(0);
1797
1798 return status;
1799}
1800
1801static int DRX_Start(struct drxd_state *state, s32 off)
1802{
1803 struct dvb_ofdm_parameters *p = &state->param.u.ofdm;
1804 int status;
1805
1806 u16 transmissionParams = 0;
1807 u16 operationMode = 0;
1808 u16 qpskTdTpsPwr = 0;
1809 u16 qam16TdTpsPwr = 0;
1810 u16 qam64TdTpsPwr = 0;
1811 u32 feIfIncr = 0;
1812 u32 bandwidth = 0;
1813 int mirrorFreqSpect;
1814
1815 u16 qpskSnCeGain = 0;
1816 u16 qam16SnCeGain = 0;
1817 u16 qam64SnCeGain = 0;
1818 u16 qpskIsGainMan = 0;
1819 u16 qam16IsGainMan = 0;
1820 u16 qam64IsGainMan = 0;
1821 u16 qpskIsGainExp = 0;
1822 u16 qam16IsGainExp = 0;
1823 u16 qam64IsGainExp = 0;
1824 u16 bandwidthParam = 0;
1825
1826 if (off<0)
1827 off=(off-500)/1000;
1828 else
1829 off=(off+500)/1000;
1830
1831 do {
1832 if (state->drxd_state != DRXD_STOPPED)
1833 return -1;
1834 CHK_ERROR( ResetECOD(state) );
1835 if (state->type_A) {
1836 CHK_ERROR( InitSC(state) );
1837 } else {
1838 CHK_ERROR( InitFT(state) );
1839 CHK_ERROR( InitCP(state) );
1840 CHK_ERROR( InitCE(state) );
1841 CHK_ERROR( InitEQ(state) );
1842 CHK_ERROR( InitSC(state) );
1843 }
1844
1845 /* Restore current IF & RF AGC settings */
1846
1847 CHK_ERROR(SetCfgIfAgc(state, &state->if_agc_cfg ));
1848 CHK_ERROR(SetCfgRfAgc(state, &state->rf_agc_cfg ));
1849
1850 mirrorFreqSpect=( state->param.inversion==INVERSION_ON);
1851
1852 switch (p->transmission_mode) {
1853 default: /* Not set, detect it automatically */
1854 operationMode |= SC_RA_RAM_OP_AUTO_MODE__M;
1855 /* fall through , try first guess DRX_FFTMODE_8K */
1856 case TRANSMISSION_MODE_8K :
1857 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K;
1858 if (state->type_A) {
1859 CHK_ERROR( Write16(state,
1860 EC_SB_REG_TR_MODE__A,
1861 EC_SB_REG_TR_MODE_8K,
1862 0x0000 ));
1863 qpskSnCeGain = 99;
1864 qam16SnCeGain = 83;
1865 qam64SnCeGain = 67;
1866 }
1867 break;
1868 case TRANSMISSION_MODE_2K :
1869 transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K;
1870 if (state->type_A) {
1871 CHK_ERROR( Write16(state,
1872 EC_SB_REG_TR_MODE__A,
1873 EC_SB_REG_TR_MODE_2K,
1874 0x0000 ));
1875 qpskSnCeGain = 97;
1876 qam16SnCeGain = 71;
1877 qam64SnCeGain = 65;
1878 }
1879 break;
1880 }
1881
1882 switch( p->guard_interval )
1883 {
1884 case GUARD_INTERVAL_1_4:
1885 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
1886 break;
1887 case GUARD_INTERVAL_1_8:
1888 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_8;
1889 break;
1890 case GUARD_INTERVAL_1_16:
1891 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_16;
1892 break;
1893 case GUARD_INTERVAL_1_32:
1894 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32;
1895 break;
1896 default: /* Not set, detect it automatically */
1897 operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M;
1898 /* try first guess 1/4 */
1899 transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
1900 break;
1901 }
1902
1903 switch( p->hierarchy_information )
1904 {
1905 case HIERARCHY_1:
1906 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
1907 if (state->type_A) {
1908 CHK_ERROR( Write16(state, EQ_REG_OT_ALPHA__A,
1909 0x0001, 0x0000 ) );
1910 CHK_ERROR( Write16(state, EC_SB_REG_ALPHA__A,
1911 0x0001, 0x0000 ) );
1912
1913 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
1914 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1;
1915 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1;
1916
1917 qpskIsGainMan =
1918 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
1919 qam16IsGainMan =
1920 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
1921 qam64IsGainMan =
1922 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
1923
1924 qpskIsGainExp =
1925 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
1926 qam16IsGainExp =
1927 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
1928 qam64IsGainExp =
1929 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
1930 }
1931 break;
1932
1933 case HIERARCHY_2:
1934 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2;
1935 if (state->type_A) {
1936 CHK_ERROR( Write16(state, EQ_REG_OT_ALPHA__A,
1937 0x0002, 0x0000 ) );
1938 CHK_ERROR( Write16(state, EC_SB_REG_ALPHA__A,
1939 0x0002, 0x0000 ) );
1940
1941 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
1942 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2;
1943 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2;
1944
1945 qpskIsGainMan =
1946 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
1947 qam16IsGainMan =
1948 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE;
1949 qam64IsGainMan =
1950 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE;
1951
1952 qpskIsGainExp =
1953 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
1954 qam16IsGainExp =
1955 SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE;
1956 qam64IsGainExp =
1957 SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE;
1958 }
1959 break;
1960 case HIERARCHY_4:
1961 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4;
1962 if (state->type_A) {
1963 CHK_ERROR( Write16(state, EQ_REG_OT_ALPHA__A,
1964 0x0003, 0x0000 ));
1965 CHK_ERROR( Write16(state, EC_SB_REG_ALPHA__A,
1966 0x0003, 0x0000 ) );
1967
1968 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
1969 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4;
1970 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4;
1971
1972 qpskIsGainMan =
1973 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
1974 qam16IsGainMan =
1975 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE;
1976 qam64IsGainMan =
1977 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE;
1978
1979 qpskIsGainExp =
1980 SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
1981 qam16IsGainExp =
1982 SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE;
1983 qam64IsGainExp =
1984 SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE;
1985 }
1986 break;
1987 case HIERARCHY_AUTO:
1988 default:
1989 /* Not set, detect it automatically, start with none */
1990 operationMode |= SC_RA_RAM_OP_AUTO_HIER__M;
1991 transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO;
1992 if (state->type_A) {
1993 CHK_ERROR( Write16(state, EQ_REG_OT_ALPHA__A,
1994 0x0000, 0x0000 ) );
1995 CHK_ERROR( Write16(state, EC_SB_REG_ALPHA__A,
1996 0x0000, 0x0000 ) );
1997
1998 qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK;
1999 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN;
2000 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN;
2001
2002 qpskIsGainMan =
2003 SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE;
2004 qam16IsGainMan =
2005 SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
2006 qam64IsGainMan =
2007 SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
2008
2009 qpskIsGainExp =
2010 SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE;
2011 qam16IsGainExp =
2012 SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
2013 qam64IsGainExp =
2014 SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
2015 }
2016 break;
2017 }
2018 CHK_ERROR( status );
2019
2020 switch( p->constellation ) {
2021 default:
2022 operationMode |= SC_RA_RAM_OP_AUTO_CONST__M;
2023 /* fall through , try first guess
2024 DRX_CONSTELLATION_QAM64 */
2025 case QAM_64:
2026 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64;
2027 if (state->type_A) {
2028 CHK_ERROR(Write16(state, EQ_REG_OT_CONST__A,
2029 0x0002, 0x0000 ) );
2030 CHK_ERROR(Write16(state, EC_SB_REG_CONST__A,
2031 EC_SB_REG_CONST_64QAM,
2032 0x0000) );
2033 CHK_ERROR(Write16(state,
2034 EC_SB_REG_SCALE_MSB__A,
2035 0x0020, 0x0000 ) );
2036 CHK_ERROR(Write16(state,
2037 EC_SB_REG_SCALE_BIT2__A,
2038 0x0008, 0x0000 ) );
2039 CHK_ERROR(Write16(state,
2040 EC_SB_REG_SCALE_LSB__A,
2041 0x0002, 0x0000 ) );
2042
2043 CHK_ERROR(Write16(state,
2044 EQ_REG_TD_TPS_PWR_OFS__A,
2045 qam64TdTpsPwr, 0x0000 ) );
2046 CHK_ERROR( Write16(state,EQ_REG_SN_CEGAIN__A,
2047 qam64SnCeGain, 0x0000 ));
2048 CHK_ERROR( Write16(state,EQ_REG_IS_GAIN_MAN__A,
2049 qam64IsGainMan, 0x0000 ));
2050 CHK_ERROR( Write16(state,EQ_REG_IS_GAIN_EXP__A,
2051 qam64IsGainExp, 0x0000 ));
2052 }
2053 break;
2054 case QPSK :
2055 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK;
2056 if (state->type_A) {
2057 CHK_ERROR(Write16(state, EQ_REG_OT_CONST__A,
2058 0x0000, 0x0000 ) );
2059 CHK_ERROR(Write16(state, EC_SB_REG_CONST__A,
2060 EC_SB_REG_CONST_QPSK,
2061 0x0000) );
2062 CHK_ERROR(Write16(state,
2063 EC_SB_REG_SCALE_MSB__A,
2064 0x0010, 0x0000 ) );
2065 CHK_ERROR(Write16(state,
2066 EC_SB_REG_SCALE_BIT2__A,
2067 0x0000, 0x0000 ) );
2068 CHK_ERROR(Write16(state,
2069 EC_SB_REG_SCALE_LSB__A,
2070 0x0000, 0x0000 ) );
2071
2072 CHK_ERROR(Write16(state,
2073 EQ_REG_TD_TPS_PWR_OFS__A,
2074 qpskTdTpsPwr, 0x0000 ) );
2075 CHK_ERROR( Write16(state, EQ_REG_SN_CEGAIN__A,
2076 qpskSnCeGain, 0x0000 ));
2077 CHK_ERROR( Write16(state,
2078 EQ_REG_IS_GAIN_MAN__A,
2079 qpskIsGainMan, 0x0000 ));
2080 CHK_ERROR( Write16(state,
2081 EQ_REG_IS_GAIN_EXP__A,
2082 qpskIsGainExp, 0x0000 ));
2083 }
2084 break;
2085
2086 case QAM_16:
2087 transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16;
2088 if (state->type_A) {
2089 CHK_ERROR(Write16(state, EQ_REG_OT_CONST__A,
2090 0x0001, 0x0000 ) );
2091 CHK_ERROR(Write16(state, EC_SB_REG_CONST__A,
2092 EC_SB_REG_CONST_16QAM,
2093 0x0000) );
2094 CHK_ERROR(Write16(state,
2095 EC_SB_REG_SCALE_MSB__A,
2096 0x0010, 0x0000 ) );
2097 CHK_ERROR(Write16(state,
2098 EC_SB_REG_SCALE_BIT2__A,
2099 0x0004, 0x0000 ) );
2100 CHK_ERROR(Write16(state,
2101 EC_SB_REG_SCALE_LSB__A,
2102 0x0000, 0x0000 ) );
2103
2104 CHK_ERROR(Write16(state,
2105 EQ_REG_TD_TPS_PWR_OFS__A,
2106 qam16TdTpsPwr, 0x0000 ) );
2107 CHK_ERROR( Write16(state, EQ_REG_SN_CEGAIN__A,
2108 qam16SnCeGain, 0x0000 ));
2109 CHK_ERROR( Write16(state,
2110 EQ_REG_IS_GAIN_MAN__A,
2111 qam16IsGainMan, 0x0000 ));
2112 CHK_ERROR( Write16(state,
2113 EQ_REG_IS_GAIN_EXP__A,
2114 qam16IsGainExp, 0x0000 ));
2115 }
2116 break;
2117
2118 }
2119 CHK_ERROR( status );
2120
2121 switch (DRX_CHANNEL_HIGH) {
2122 default:
2123 case DRX_CHANNEL_AUTO:
2124 case DRX_CHANNEL_LOW:
2125 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO;
2126 CHK_ERROR( Write16(state, EC_SB_REG_PRIOR__A,
2127 EC_SB_REG_PRIOR_LO, 0x0000 ));
2128 break;
2129 case DRX_CHANNEL_HIGH:
2130 transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI;
2131 CHK_ERROR( Write16(state, EC_SB_REG_PRIOR__A,
2132 EC_SB_REG_PRIOR_HI, 0x0000 ));
2133 break;
2134
2135 }
2136
2137 switch( p->code_rate_HP )
2138 {
2139 case FEC_1_2:
2140 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2;
2141 if (state->type_A) {
2142 CHK_ERROR( Write16(state,
2143 EC_VD_REG_SET_CODERATE__A,
2144 EC_VD_REG_SET_CODERATE_C1_2,
2145 0x0000 ) );
2146 }
2147 break;
2148 default:
2149 operationMode |= SC_RA_RAM_OP_AUTO_RATE__M;
2150 case FEC_2_3 :
2151 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3;
2152 if (state->type_A) {
2153 CHK_ERROR( Write16(state,
2154 EC_VD_REG_SET_CODERATE__A,
2155 EC_VD_REG_SET_CODERATE_C2_3,
2156 0x0000 ) );
2157 }
2158 break;
2159 case FEC_3_4 :
2160 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4;
2161 if (state->type_A) {
2162 CHK_ERROR( Write16(state,
2163 EC_VD_REG_SET_CODERATE__A,
2164 EC_VD_REG_SET_CODERATE_C3_4,
2165 0x0000 ) );
2166 }
2167 break;
2168 case FEC_5_6 :
2169 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6;
2170 if (state->type_A) {
2171 CHK_ERROR( Write16(state,
2172 EC_VD_REG_SET_CODERATE__A,
2173 EC_VD_REG_SET_CODERATE_C5_6,
2174 0x0000 ) );
2175 }
2176 break;
2177 case FEC_7_8 :
2178 transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8;
2179 if (state->type_A) {
2180 CHK_ERROR( Write16(state,
2181 EC_VD_REG_SET_CODERATE__A,
2182 EC_VD_REG_SET_CODERATE_C7_8,
2183 0x0000 ) );
2184 }
2185 break;
2186 }
2187 CHK_ERROR( status );
2188
2189 /* First determine real bandwidth (Hz) */
2190 /* Also set delay for impulse noise cruncher (only A2) */
2191 /* Also set parameters for EC_OC fix, note
2192 EC_OC_REG_TMD_HIL_MAR is changed
2193 by SC for fix for some 8K,1/8 guard but is restored by
2194 InitEC and ResetEC
2195 functions */
2196 switch( p->bandwidth )
2197 {
2198 case BANDWIDTH_AUTO:
2199 case BANDWIDTH_8_MHZ:
2200 /* (64/7)*(8/8)*1000000 */
2201 bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
2202
2203 bandwidthParam = 0;
2204 status = Write16(state,
2205 FE_AG_REG_IND_DEL__A , 50 , 0x0000 );
2206 break;
2207 case BANDWIDTH_7_MHZ:
2208 /* (64/7)*(7/8)*1000000 */
2209 bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
2210 bandwidthParam =0x4807; /*binary:0100 1000 0000 0111 */
2211 status = Write16(state,
2212 FE_AG_REG_IND_DEL__A , 59 , 0x0000 );
2213 break;
2214 case BANDWIDTH_6_MHZ:
2215 /* (64/7)*(6/8)*1000000 */
2216 bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
2217 bandwidthParam =0x0F07; /*binary: 0000 1111 0000 0111*/
2218 status = Write16(state,
2219 FE_AG_REG_IND_DEL__A , 71 , 0x0000 );
2220 break;
2221 }
2222 CHK_ERROR( status );
2223
2224 CHK_ERROR( Write16(state,
2225 SC_RA_RAM_BAND__A, bandwidthParam, 0x0000));
2226
2227 {
2228 u16 sc_config;
2229 CHK_ERROR(Read16(state,
2230 SC_RA_RAM_CONFIG__A, &sc_config, 0));
2231
2232 /* enable SLAVE mode in 2k 1/32 to
2233 prevent timing change glitches */
2234 if ( (p->transmission_mode==TRANSMISSION_MODE_2K) &&
2235 (p->guard_interval==GUARD_INTERVAL_1_32) ) {
2236 /* enable slave */
2237 sc_config |= SC_RA_RAM_CONFIG_SLAVE__M;
2238 } else {
2239 /* disable slave */
2240 sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M;
2241 }
2242 CHK_ERROR( Write16(state,
2243 SC_RA_RAM_CONFIG__A, sc_config,0 ));
2244 }
2245
2246 CHK_ERROR( SetCfgNoiseCalibration(state, &state->noise_cal));
2247
2248 if (state->cscd_state == CSCD_INIT )
2249 {
2250 /* switch on SRMM scan in SC */
2251 CHK_ERROR( Write16(state,
2252 SC_RA_RAM_SAMPLE_RATE_COUNT__A,
2253 DRXD_OSCDEV_DO_SCAN, 0x0000 ));
2254/* CHK_ERROR( Write16( SC_RA_RAM_SAMPLE_RATE_STEP__A,
2255 DRXD_OSCDEV_STEP , 0x0000 ));*/
2256 state->cscd_state = CSCD_SET;
2257 }
2258
2259
2260 /* Now compute FE_IF_REG_INCR */
2261 /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) =>
2262 ((SysFreq / BandWidth) * (2^21) ) - (2^23)*/
2263 feIfIncr = MulDiv32(state->sys_clock_freq*1000,
2264 ( 1ULL<< 21 ), bandwidth) - (1<<23) ;
2265 CHK_ERROR( Write16(state,
2266 FE_IF_REG_INCR0__A,
2267 (u16)(feIfIncr & FE_IF_REG_INCR0__M ),
2268 0x0000) );
2269 CHK_ERROR( Write16(state,
2270 FE_IF_REG_INCR1__A,
2271 (u16)((feIfIncr >> FE_IF_REG_INCR0__W) &
2272 FE_IF_REG_INCR1__M ), 0x0000) );
2273 /* Bandwidth setting done */
2274
2275 /* Mirror & frequency offset */
2276 SetFrequencyShift(state, off, mirrorFreqSpect);
2277
2278 /* Start SC, write channel settings to SC */
2279
2280 /* Enable SC after setting all other parameters */
2281 CHK_ERROR( Write16(state, SC_COMM_STATE__A, 0, 0x0000));
2282 CHK_ERROR( Write16(state, SC_COMM_EXEC__A, 1, 0x0000));
2283
2284 /* Write SC parameter registers, operation mode */
2285#if 1
2286 operationMode =( SC_RA_RAM_OP_AUTO_MODE__M |
2287 SC_RA_RAM_OP_AUTO_GUARD__M |
2288 SC_RA_RAM_OP_AUTO_CONST__M |
2289 SC_RA_RAM_OP_AUTO_HIER__M |
2290 SC_RA_RAM_OP_AUTO_RATE__M );
2291#endif
2292 CHK_ERROR( SC_SetPrefParamCommand(state, 0x0000,
2293 transmissionParams,
2294 operationMode) );
2295
2296 /* Start correct processes to get in lock */
2297 CHK_ERROR( SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK,
2298 SC_RA_RAM_SW_EVENT_RUN_NMASK__M,
2299 SC_RA_RAM_LOCKTRACK_MIN) );
2300
2301 CHK_ERROR( StartOC(state) );
2302
2303 if( state->operation_mode != OM_Default ) {
2304 CHK_ERROR(StartDiversity(state));
2305 }
2306
2307 state->drxd_state = DRXD_STARTED;
2308 } while(0);
2309
2310 return status;
2311}
2312
2313static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
2314{
2315 u32 ulRfAgcOutputLevel = 0xffffffff;
2316 u32 ulRfAgcSettleLevel = 528; /* Optimum value for MT2060 */
2317 u32 ulRfAgcMinLevel = 0; /* Currently unused */
2318 u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */
2319 u32 ulRfAgcSpeed = 0; /* Currently unused */
2320 u32 ulRfAgcMode = 0;/*2; Off */
2321 u32 ulRfAgcR1 = 820;
2322 u32 ulRfAgcR2 = 2200;
2323 u32 ulRfAgcR3 = 150;
2324 u32 ulIfAgcMode = 0; /* Auto */
2325 u32 ulIfAgcOutputLevel = 0xffffffff;
2326 u32 ulIfAgcSettleLevel = 0xffffffff;
2327 u32 ulIfAgcMinLevel = 0xffffffff;
2328 u32 ulIfAgcMaxLevel = 0xffffffff;
2329 u32 ulIfAgcSpeed = 0xffffffff;
2330 u32 ulIfAgcR1 = 820;
2331 u32 ulIfAgcR2 = 2200;
2332 u32 ulIfAgcR3 = 150;
2333 u32 ulClock = state->config.clock;
2334 u32 ulSerialMode = 0;
2335 u32 ulEcOcRegOcModeLop = 4; /* Dynamic DTO source */
2336 u32 ulHiI2cDelay = HI_I2C_DELAY;
2337 u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY;
2338 u32 ulHiI2cPatch = 0;
2339 u32 ulEnvironment = APPENV_PORTABLE;
2340 u32 ulEnvironmentDiversity = APPENV_MOBILE;
2341 u32 ulIFFilter = IFFILTER_SAW;
2342
2343 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2344 state->if_agc_cfg.outputLevel = 0;
2345 state->if_agc_cfg.settleLevel = 140;
2346 state->if_agc_cfg.minOutputLevel = 0;
2347 state->if_agc_cfg.maxOutputLevel = 1023;
2348 state->if_agc_cfg.speed = 904;
2349
2350 if( ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX )
2351 {
2352 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER;
2353 state->if_agc_cfg.outputLevel = (u16)(ulIfAgcOutputLevel);
2354 }
2355
2356 if( ulIfAgcMode == 0 &&
2357 ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2358 ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2359 ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2360 ulIfAgcSpeed <= DRXD_FE_CTRL_MAX
2361 )
2362 {
2363 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2364 state->if_agc_cfg.settleLevel = (u16)(ulIfAgcSettleLevel);
2365 state->if_agc_cfg.minOutputLevel = (u16)(ulIfAgcMinLevel);
2366 state->if_agc_cfg.maxOutputLevel = (u16)(ulIfAgcMaxLevel);
2367 state->if_agc_cfg.speed = (u16)(ulIfAgcSpeed);
2368 }
2369
2370 state->if_agc_cfg.R1 = (u16)(ulIfAgcR1);
2371 state->if_agc_cfg.R2 = (u16)(ulIfAgcR2);
2372 state->if_agc_cfg.R3 = (u16)(ulIfAgcR3);
2373
2374 state->rf_agc_cfg.R1 = (u16)(ulRfAgcR1);
2375 state->rf_agc_cfg.R2 = (u16)(ulRfAgcR2);
2376 state->rf_agc_cfg.R3 = (u16)(ulRfAgcR3);
2377
2378 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2379 /* rest of the RFAgcCfg structure currently unused */
2380 if (ulRfAgcMode==1 && ulRfAgcOutputLevel<=DRXD_FE_CTRL_MAX) {
2381 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER;
2382 state->rf_agc_cfg.outputLevel = (u16)(ulRfAgcOutputLevel);
2383 }
2384
2385 if( ulRfAgcMode == 0 &&
2386 ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2387 ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2388 ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2389 ulRfAgcSpeed <= DRXD_FE_CTRL_MAX
2390 )
2391 {
2392 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2393 state->rf_agc_cfg.settleLevel = (u16)(ulRfAgcSettleLevel);
2394 state->rf_agc_cfg.minOutputLevel = (u16)(ulRfAgcMinLevel);
2395 state->rf_agc_cfg.maxOutputLevel = (u16)(ulRfAgcMaxLevel);
2396 state->rf_agc_cfg.speed = (u16)(ulRfAgcSpeed);
2397 }
2398
2399 if( ulRfAgcMode == 2 )
2400 {
2401 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;
2402 }
2403
2404 if (ulEnvironment <= 2)
2405 state->app_env_default = (enum app_env)
2406 (ulEnvironment);
2407 if (ulEnvironmentDiversity <= 2)
2408 state->app_env_diversity = (enum app_env)
2409 (ulEnvironmentDiversity);
2410
2411 if( ulIFFilter == IFFILTER_DISCRETE )
2412 {
2413 /* discrete filter */
2414 state->noise_cal.cpOpt = 0;
2415 state->noise_cal.cpNexpOfs = 40;
2416 state->noise_cal.tdCal2k = -40;
2417 state->noise_cal.tdCal8k = -24;
2418 } else {
2419 /* SAW filter */
2420 state->noise_cal.cpOpt = 1;
2421 state->noise_cal.cpNexpOfs = 0;
2422 state->noise_cal.tdCal2k = -21;
2423 state->noise_cal.tdCal8k = -24;
2424 }
2425 state->m_EcOcRegOcModeLop = (u16)(ulEcOcRegOcModeLop);
2426
2427 state->chip_adr = (state->config.demod_address<<1)|1;
2428 switch( ulHiI2cPatch )
2429 {
2430 case 1 : state->m_HiI2cPatch = DRXD_HiI2cPatch_1; break;
2431 case 3 : state->m_HiI2cPatch = DRXD_HiI2cPatch_3; break;
2432 default:
2433 state->m_HiI2cPatch = NULL;
2434 }
2435
2436 /* modify tuner and clock attributes */
2437 state->intermediate_freq = (u16)(IntermediateFrequency/1000);
2438 /* expected system clock frequency in kHz */
2439 state->expected_sys_clock_freq = 48000;
2440 /* real system clock frequency in kHz */
2441 state->sys_clock_freq = 48000;
2442 state->osc_clock_freq = (u16) ulClock;
2443 state->osc_clock_deviation = 0;
2444 state->cscd_state = CSCD_INIT;
2445 state->drxd_state = DRXD_UNINITIALIZED;
2446
2447 state->PGA=0;
2448 state->type_A=0;
2449 state->tuner_mirrors=0;
2450
2451 /* modify MPEG output attributes */
2452 state->insert_rs_byte = 0;
2453 state->enable_parallel = (ulSerialMode != 1);
2454
2455 /* Timing div, 250ns/Psys */
2456 /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
2457
2458 state->hi_cfg_timing_div = (u16)((state->sys_clock_freq/1000)*
2459 ulHiI2cDelay)/1000 ;
2460 /* Bridge delay, uses oscilator clock */
2461 /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
2462 state->hi_cfg_bridge_delay = (u16)((state->osc_clock_freq/1000) *
2463 ulHiI2cBridgeDelay)/1000 ;
2464
2465 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2466 /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */
2467 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2468 return 0;
2469}
2470
2471int DRXD_init(struct drxd_state *state, const u8 *fw, u32 fw_size)
2472{
2473 int status=0;
2474 u32 driverVersion;
2475
2476 if (state->init_done)
2477 return 0;
2478
2479 CDRXD(state, state->config.IF ? state->config.IF : 36000000);
2480
2481 do {
2482 state->operation_mode = OM_Default;
2483
2484 CHK_ERROR( SetDeviceTypeId(state) );
2485
2486 /* Apply I2c address patch to B1 */
2487 if( !state->type_A && state->m_HiI2cPatch != NULL )
2488 CHK_ERROR(WriteTable(state, state->m_HiI2cPatch));
2489
2490 if (state->type_A) {
2491 /* HI firmware patch for UIO readout,
2492 avoid clearing of result register */
2493 CHK_ERROR(Write16(state, 0x43012D, 0x047f, 0));
2494 }
2495
2496 CHK_ERROR( HI_ResetCommand(state));
2497
2498 CHK_ERROR(StopAllProcessors(state));
2499 CHK_ERROR(InitCC(state));
2500
2501 state->osc_clock_deviation = 0;
2502
2503 if (state->config.osc_deviation)
2504 state->osc_clock_deviation =
2505 state->config.osc_deviation(state->priv,
2506 0, 0);
2507 {
2508 /* Handle clock deviation */
2509 s32 devB;
2510 s32 devA = (s32)(state->osc_clock_deviation) *
2511 (s32)(state->expected_sys_clock_freq);
2512 /* deviation in kHz */
2513 s32 deviation = ( devA /(1000000L));
2514 /* rounding, signed */
2515 if ( devA > 0 )
2516 devB=(2);
2517 else
2518 devB=(-2);
2519 if ( (devB*(devA%1000000L)>1000000L ) )
2520 {
2521 /* add +1 or -1 */
2522 deviation += (devB/2);
2523 }
2524
2525 state->sys_clock_freq=(u16)((state->
2526 expected_sys_clock_freq)+
2527 deviation);
2528 }
2529 CHK_ERROR(InitHI(state));
2530 CHK_ERROR(InitAtomicRead(state));
2531
2532 CHK_ERROR(EnableAndResetMB(state));
2533 if (state->type_A)
2534 CHK_ERROR(ResetCEFR(state));
2535
2536 if (fw) {
2537 CHK_ERROR(DownloadMicrocode(state, fw, fw_size));
2538 } else {
2539 CHK_ERROR(DownloadMicrocode(state, state->microcode,
2540 state->microcode_length));
2541 }
2542
2543 if (state->PGA) {
2544 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO;
2545 SetCfgPga(state, 0); /* PGA = 0 dB */
2546 } else {
2547 state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2548 }
2549
2550 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2551
2552 CHK_ERROR(InitFE(state));
2553 CHK_ERROR(InitFT(state));
2554 CHK_ERROR(InitCP(state));
2555 CHK_ERROR(InitCE(state));
2556 CHK_ERROR(InitEQ(state));
2557 CHK_ERROR(InitEC(state));
2558 CHK_ERROR(InitSC(state));
2559
2560 CHK_ERROR(SetCfgIfAgc(state, &state->if_agc_cfg));
2561 CHK_ERROR(SetCfgRfAgc(state, &state->rf_agc_cfg));
2562
2563 state->cscd_state = CSCD_INIT;
2564 CHK_ERROR(Write16(state, SC_COMM_EXEC__A,
2565 SC_COMM_EXEC_CTL_STOP, 0));
2566 CHK_ERROR(Write16(state, LC_COMM_EXEC__A,
2567 SC_COMM_EXEC_CTL_STOP, 0 ));
2568
2569
2570 driverVersion = (((VERSION_MAJOR/10) << 4) +
2571 (VERSION_MAJOR%10)) << 24;
2572 driverVersion += (((VERSION_MINOR/10) << 4) +
2573 (VERSION_MINOR%10)) << 16;
2574 driverVersion += ((VERSION_PATCH/1000)<<12) +
2575 ((VERSION_PATCH/100)<<8) +
2576 ((VERSION_PATCH/10 )<< 4) +
2577 (VERSION_PATCH%10 );
2578
2579 CHK_ERROR(Write32(state, SC_RA_RAM_DRIVER_VERSION__AX,
2580 driverVersion,0 ));
2581
2582 CHK_ERROR( StopOC(state) );
2583
2584 state->drxd_state = DRXD_STOPPED;
2585 state->init_done=1;
2586 status=0;
2587 } while (0);
2588 return status;
2589}
2590
2591int DRXD_status(struct drxd_state *state, u32 *pLockStatus)
2592{
2593 DRX_GetLockStatus(state, pLockStatus);
2594
2595 /*if (*pLockStatus&DRX_LOCK_MPEG)*/
2596 if (*pLockStatus&DRX_LOCK_FEC) {
2597 ConfigureMPEGOutput(state, 1);
2598 /* Get status again, in case we have MPEG lock now */
2599 /*DRX_GetLockStatus(state, pLockStatus);*/
2600 }
2601
2602 return 0;
2603}
2604
2605/****************************************************************************/
2606/****************************************************************************/
2607/****************************************************************************/
2608
2609static int drxd_read_signal_strength(struct dvb_frontend *fe,
2610 u16 *strength)
2611{
2612 struct drxd_state *state = fe->demodulator_priv;
2613 u32 value;
2614 int res;
2615
2616 res=ReadIFAgc(state, &value);
2617 if (res<0)
2618 *strength=0;
2619 else
2620 *strength=0xffff-(value<<4);
2621 return 0;
2622}
2623
2624
2625static int drxd_read_status(struct dvb_frontend *fe, fe_status_t *status)
2626{
2627 struct drxd_state *state = fe->demodulator_priv;
2628 u32 lock;
2629
2630 DRXD_status(state, &lock);
2631 *status=0;
2632 /* No MPEG lock in V255 firmware, bug ? */
2633#if 1
2634 if (lock&DRX_LOCK_MPEG)
2635 *status|=FE_HAS_LOCK;
2636#else
2637 if (lock&DRX_LOCK_FEC)
2638 *status|=FE_HAS_LOCK;
2639#endif
2640 if (lock&DRX_LOCK_FEC)
2641 *status|=FE_HAS_VITERBI|FE_HAS_SYNC;
2642 if (lock&DRX_LOCK_DEMOD)
2643 *status|=FE_HAS_CARRIER|FE_HAS_SIGNAL;
2644
2645 return 0;
2646}
2647
2648static int drxd_init(struct dvb_frontend *fe)
2649{
2650 struct drxd_state *state=fe->demodulator_priv;
2651 int err=0;
2652
2653/* if (request_firmware(&state->fw, "drxd.fw", state->dev)<0) */
2654 return DRXD_init(state, 0, 0);
2655
2656 err=DRXD_init(state, state->fw->data, state->fw->size);
2657 release_firmware(state->fw);
2658 return err;
2659}
2660
2661int drxd_config_i2c(struct dvb_frontend *fe, int onoff)
2662{
2663 struct drxd_state *state=fe->demodulator_priv;
2664
2665 return DRX_ConfigureI2CBridge(state, onoff);
2666}
2667
2668static int drxd_get_tune_settings(struct dvb_frontend *fe,
2669 struct dvb_frontend_tune_settings *sets)
2670{
2671 sets->min_delay_ms=10000;
2672 sets->max_drift=0;
2673 sets->step_size=0;
2674 return 0;
2675}
2676
2677static int drxd_read_ber(struct dvb_frontend *fe, u32 *ber)
2678{
2679 *ber = 0;
2680 return 0;
2681}
2682
2683static int drxd_read_snr(struct dvb_frontend *fe, u16 *snr)
2684{
2685 *snr=0;
2686 return 0;
2687}
2688
2689static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
2690{
2691 *ucblocks=0;
2692 return 0;
2693}
2694
2695static int drxd_sleep(struct dvb_frontend* fe)
2696{
2697 struct drxd_state *state=fe->demodulator_priv;
2698
2699 ConfigureMPEGOutput(state, 0);
2700 return 0;
2701}
2702
2703static int drxd_get_frontend(struct dvb_frontend *fe,
2704 struct dvb_frontend_parameters *param)
2705{
2706 return 0;
2707}
2708
2709static int drxd_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
2710{
2711 return drxd_config_i2c(fe, enable);
2712}
2713
2714static int drxd_set_frontend(struct dvb_frontend *fe,
2715 struct dvb_frontend_parameters *param)
2716{
2717 struct drxd_state *state=fe->demodulator_priv;
2718 s32 off=0;
2719
2720 state->param=*param;
2721 DRX_Stop(state);
2722
2723 if (fe->ops.tuner_ops.set_params) {
2724 fe->ops.tuner_ops.set_params(fe, param);
2725 if (fe->ops.i2c_gate_ctrl)
2726 fe->ops.i2c_gate_ctrl(fe, 0);
2727 }
2728
2729 /* FIXME: move PLL drivers */
2730 if (state->config.pll_set &&
2731 state->config.pll_set(state->priv, param,
2732 state->config.pll_address,
2733 state->config.demoda_address,
2734 &off)<0) {
2735 printk("Error in pll_set\n");
2736 return -1;
2737 }
2738
2739 msleep(200);
2740
2741 return DRX_Start(state, off);
2742}
2743
2744
2745static void drxd_release(struct dvb_frontend *fe)
2746{
2747 struct drxd_state *state = fe->demodulator_priv;
2748
2749 kfree(state);
2750}
2751
2752static struct dvb_frontend_ops drxd_ops = {
2753
2754 .info = {
2755 .name = "Micronas DRXD DVB-T",
2756 .type = FE_OFDM,
2757 .frequency_min = 47125000,
2758 .frequency_max = 855250000,
2759 .frequency_stepsize = 166667,
2760 .frequency_tolerance = 0,
2761 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
2762 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
2763 FE_CAN_FEC_AUTO |
2764 FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2765 FE_CAN_QAM_AUTO |
2766 FE_CAN_TRANSMISSION_MODE_AUTO |
2767 FE_CAN_GUARD_INTERVAL_AUTO |
2768 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
2769 FE_CAN_MUTE_TS
2770 },
2771
2772 .release = drxd_release,
2773 .init = drxd_init,
2774 .sleep = drxd_sleep,
2775 .i2c_gate_ctrl = drxd_i2c_gate_ctrl,
2776
2777 .set_frontend = drxd_set_frontend,
2778 .get_frontend = drxd_get_frontend,
2779 .get_tune_settings = drxd_get_tune_settings,
2780
2781 .read_status = drxd_read_status,
2782 .read_ber = drxd_read_ber,
2783 .read_signal_strength = drxd_read_signal_strength,
2784 .read_snr = drxd_read_snr,
2785 .read_ucblocks = drxd_read_ucblocks,
2786};
2787
2788struct dvb_frontend *drxd_attach(const struct drxd_config *config,
2789 void *priv, struct i2c_adapter *i2c,
2790 struct device *dev)
2791{
2792 struct drxd_state *state = NULL;
2793
2794 state=kmalloc(sizeof(struct drxd_state), GFP_KERNEL);
2795 if (!state)
2796 return NULL;
2797 memset(state, 0, sizeof(*state));
2798
2799 memcpy(&state->ops, &drxd_ops, sizeof(struct dvb_frontend_ops));
2800 state->dev=dev;
2801 state->config=*config;
2802 state->i2c=i2c;
2803 state->priv=priv;
2804
2805 sema_init(&state->mutex, 1);
2806
2807 if (Read16(state, 0, 0, 0)<0)
2808 goto error;
2809
2810#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)
2811 state->frontend.ops=&state->ops;
2812#else
2813 memcpy(&state->frontend.ops, &drxd_ops,
2814 sizeof(struct dvb_frontend_ops));
2815#endif
2816 state->frontend.demodulator_priv=state;
2817 ConfigureMPEGOutput(state, 0);
2818 return &state->frontend;
2819
2820error:
2821 printk("drxd: not found\n");
2822 kfree(state);
2823 return NULL;
2824}
2825
2826MODULE_DESCRIPTION("DRXD driver");
2827MODULE_AUTHOR("Micronas");
2828MODULE_LICENSE("GPL");
2829
2830EXPORT_SYMBOL(drxd_attach);
2831EXPORT_SYMBOL(drxd_config_i2c);
diff --git a/drivers/media/dvb/frontends/drxd_map_firm.h b/drivers/media/dvb/frontends/drxd_map_firm.h
new file mode 100644
index 000000000000..3523cfee7479
--- /dev/null
+++ b/drivers/media/dvb/frontends/drxd_map_firm.h
@@ -0,0 +1,14484 @@
1/*
2 * drx3973d_map_firm.h
3 *
4 * Copyright (C) 2006-2007 Micronas
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 only, as published by the Free Software Foundation.
9 *
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 * 02110-1301, USA
21 * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
22 */
23
24#ifndef __DRX3973D_MAP__H__
25#define __DRX3973D_MAP__H__
26
27#ifdef __cplusplus
28extern "C" {
29#endif
30
31#define HI_SID 0x10
32
33
34
35
36
37#define HI_COMM_EXEC__A 0x400000
38#define HI_COMM_EXEC__W 3
39#define HI_COMM_EXEC__M 0x7
40#define HI_COMM_EXEC_CTL__B 0
41#define HI_COMM_EXEC_CTL__W 3
42#define HI_COMM_EXEC_CTL__M 0x7
43#define HI_COMM_EXEC_CTL_STOP 0x0
44#define HI_COMM_EXEC_CTL_ACTIVE 0x1
45#define HI_COMM_EXEC_CTL_HOLD 0x2
46#define HI_COMM_EXEC_CTL_STEP 0x3
47#define HI_COMM_EXEC_CTL_BYPASS_STOP 0x4
48#define HI_COMM_EXEC_CTL_BYPASS_HOLD 0x6
49
50#define HI_COMM_STATE__A 0x400001
51#define HI_COMM_STATE__W 16
52#define HI_COMM_STATE__M 0xFFFF
53#define HI_COMM_MB__A 0x400002
54#define HI_COMM_MB__W 16
55#define HI_COMM_MB__M 0xFFFF
56#define HI_COMM_SERVICE0__A 0x400003
57#define HI_COMM_SERVICE0__W 16
58#define HI_COMM_SERVICE0__M 0xFFFF
59#define HI_COMM_SERVICE1__A 0x400004
60#define HI_COMM_SERVICE1__W 16
61#define HI_COMM_SERVICE1__M 0xFFFF
62#define HI_COMM_INT_STA__A 0x400007
63#define HI_COMM_INT_STA__W 16
64#define HI_COMM_INT_STA__M 0xFFFF
65#define HI_COMM_INT_MSK__A 0x400008
66#define HI_COMM_INT_MSK__W 16
67#define HI_COMM_INT_MSK__M 0xFFFF
68
69
70
71
72
73
74#define HI_CT_REG_COMM_EXEC__A 0x410000
75#define HI_CT_REG_COMM_EXEC__W 3
76#define HI_CT_REG_COMM_EXEC__M 0x7
77#define HI_CT_REG_COMM_EXEC_CTL__B 0
78#define HI_CT_REG_COMM_EXEC_CTL__W 3
79#define HI_CT_REG_COMM_EXEC_CTL__M 0x7
80#define HI_CT_REG_COMM_EXEC_CTL_STOP 0x0
81#define HI_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1
82#define HI_CT_REG_COMM_EXEC_CTL_HOLD 0x2
83#define HI_CT_REG_COMM_EXEC_CTL_STEP 0x3
84
85
86#define HI_CT_REG_COMM_STATE__A 0x410001
87#define HI_CT_REG_COMM_STATE__W 10
88#define HI_CT_REG_COMM_STATE__M 0x3FF
89#define HI_CT_REG_COMM_SERVICE0__A 0x410003
90#define HI_CT_REG_COMM_SERVICE0__W 16
91#define HI_CT_REG_COMM_SERVICE0__M 0xFFFF
92#define HI_CT_REG_COMM_SERVICE1__A 0x410004
93#define HI_CT_REG_COMM_SERVICE1__W 16
94#define HI_CT_REG_COMM_SERVICE1__M 0xFFFF
95#define HI_CT_REG_COMM_SERVICE1_HI__B 0
96#define HI_CT_REG_COMM_SERVICE1_HI__W 1
97#define HI_CT_REG_COMM_SERVICE1_HI__M 0x1
98
99
100#define HI_CT_REG_COMM_INT_STA__A 0x410007
101#define HI_CT_REG_COMM_INT_STA__W 1
102#define HI_CT_REG_COMM_INT_STA__M 0x1
103#define HI_CT_REG_COMM_INT_STA_REQUEST__B 0
104#define HI_CT_REG_COMM_INT_STA_REQUEST__W 1
105#define HI_CT_REG_COMM_INT_STA_REQUEST__M 0x1
106
107
108#define HI_CT_REG_COMM_INT_MSK__A 0x410008
109#define HI_CT_REG_COMM_INT_MSK__W 1
110#define HI_CT_REG_COMM_INT_MSK__M 0x1
111#define HI_CT_REG_COMM_INT_MSK_REQUEST__B 0
112#define HI_CT_REG_COMM_INT_MSK_REQUEST__W 1
113#define HI_CT_REG_COMM_INT_MSK_REQUEST__M 0x1
114
115
116
117
118#define HI_CT_REG_CTL_STK__AX 0x410010
119#define HI_CT_REG_CTL_STK__XSZ 4
120#define HI_CT_REG_CTL_STK__W 10
121#define HI_CT_REG_CTL_STK__M 0x3FF
122
123#define HI_CT_REG_CTL_BPT_IDX__A 0x41001F
124#define HI_CT_REG_CTL_BPT_IDX__W 1
125#define HI_CT_REG_CTL_BPT_IDX__M 0x1
126
127#define HI_CT_REG_CTL_BPT__A 0x410020
128#define HI_CT_REG_CTL_BPT__W 10
129#define HI_CT_REG_CTL_BPT__M 0x3FF
130
131
132
133
134
135
136#define HI_RA_RAM_SLV0_FLG_SMM__A 0x420010
137#define HI_RA_RAM_SLV0_FLG_SMM__W 1
138#define HI_RA_RAM_SLV0_FLG_SMM__M 0x1
139#define HI_RA_RAM_SLV0_FLG_SMM_MULTI 0x0
140#define HI_RA_RAM_SLV0_FLG_SMM_SINGLE 0x1
141
142
143#define HI_RA_RAM_SLV0_DEV_ID__A 0x420011
144#define HI_RA_RAM_SLV0_DEV_ID__W 7
145#define HI_RA_RAM_SLV0_DEV_ID__M 0x7F
146
147#define HI_RA_RAM_SLV0_FLG_CRC__A 0x420012
148#define HI_RA_RAM_SLV0_FLG_CRC__W 1
149#define HI_RA_RAM_SLV0_FLG_CRC__M 0x1
150#define HI_RA_RAM_SLV0_FLG_CRC_CONTINUE 0x0
151#define HI_RA_RAM_SLV0_FLG_CRC_RESTART 0x1
152
153
154#define HI_RA_RAM_SLV0_FLG_ACC__A 0x420013
155#define HI_RA_RAM_SLV0_FLG_ACC__W 3
156#define HI_RA_RAM_SLV0_FLG_ACC__M 0x7
157#define HI_RA_RAM_SLV0_FLG_ACC_RWM__B 0
158#define HI_RA_RAM_SLV0_FLG_ACC_RWM__W 2
159#define HI_RA_RAM_SLV0_FLG_ACC_RWM__M 0x3
160#define HI_RA_RAM_SLV0_FLG_ACC_RWM_NORMAL 0x0
161#define HI_RA_RAM_SLV0_FLG_ACC_RWM_READ_WRITE 0x3
162#define HI_RA_RAM_SLV0_FLG_ACC_BRC__B 2
163#define HI_RA_RAM_SLV0_FLG_ACC_BRC__W 1
164#define HI_RA_RAM_SLV0_FLG_ACC_BRC__M 0x4
165#define HI_RA_RAM_SLV0_FLG_ACC_BRC_NORMAL 0x0
166#define HI_RA_RAM_SLV0_FLG_ACC_BRC_BROADCAST 0x4
167
168
169#define HI_RA_RAM_SLV0_STATE__A 0x420014
170#define HI_RA_RAM_SLV0_STATE__W 1
171#define HI_RA_RAM_SLV0_STATE__M 0x1
172#define HI_RA_RAM_SLV0_STATE_ADDRESS 0x0
173#define HI_RA_RAM_SLV0_STATE_DATA 0x1
174
175
176#define HI_RA_RAM_SLV0_BLK_BNK__A 0x420015
177#define HI_RA_RAM_SLV0_BLK_BNK__W 12
178#define HI_RA_RAM_SLV0_BLK_BNK__M 0xFFF
179#define HI_RA_RAM_SLV0_BLK_BNK_BNK__B 0
180#define HI_RA_RAM_SLV0_BLK_BNK_BNK__W 6
181#define HI_RA_RAM_SLV0_BLK_BNK_BNK__M 0x3F
182#define HI_RA_RAM_SLV0_BLK_BNK_BLK__B 6
183#define HI_RA_RAM_SLV0_BLK_BNK_BLK__W 6
184#define HI_RA_RAM_SLV0_BLK_BNK_BLK__M 0xFC0
185
186
187#define HI_RA_RAM_SLV0_ADDR__A 0x420016
188#define HI_RA_RAM_SLV0_ADDR__W 16
189#define HI_RA_RAM_SLV0_ADDR__M 0xFFFF
190
191#define HI_RA_RAM_SLV0_CRC__A 0x420017
192#define HI_RA_RAM_SLV0_CRC__W 16
193#define HI_RA_RAM_SLV0_CRC__M 0xFFFF
194
195#define HI_RA_RAM_SLV0_READBACK__A 0x420018
196#define HI_RA_RAM_SLV0_READBACK__W 16
197#define HI_RA_RAM_SLV0_READBACK__M 0xFFFF
198
199
200
201
202#define HI_RA_RAM_SLV1_FLG_SMM__A 0x420020
203#define HI_RA_RAM_SLV1_FLG_SMM__W 1
204#define HI_RA_RAM_SLV1_FLG_SMM__M 0x1
205#define HI_RA_RAM_SLV1_FLG_SMM_MULTI 0x0
206#define HI_RA_RAM_SLV1_FLG_SMM_SINGLE 0x1
207
208
209#define HI_RA_RAM_SLV1_DEV_ID__A 0x420021
210#define HI_RA_RAM_SLV1_DEV_ID__W 7
211#define HI_RA_RAM_SLV1_DEV_ID__M 0x7F
212
213#define HI_RA_RAM_SLV1_FLG_CRC__A 0x420022
214#define HI_RA_RAM_SLV1_FLG_CRC__W 1
215#define HI_RA_RAM_SLV1_FLG_CRC__M 0x1
216#define HI_RA_RAM_SLV1_FLG_CRC_CONTINUE 0x0
217#define HI_RA_RAM_SLV1_FLG_CRC_RESTART 0x1
218
219
220#define HI_RA_RAM_SLV1_FLG_ACC__A 0x420023
221#define HI_RA_RAM_SLV1_FLG_ACC__W 3
222#define HI_RA_RAM_SLV1_FLG_ACC__M 0x7
223#define HI_RA_RAM_SLV1_FLG_ACC_RWM__B 0
224#define HI_RA_RAM_SLV1_FLG_ACC_RWM__W 2
225#define HI_RA_RAM_SLV1_FLG_ACC_RWM__M 0x3
226#define HI_RA_RAM_SLV1_FLG_ACC_RWM_NORMAL 0x0
227#define HI_RA_RAM_SLV1_FLG_ACC_RWM_READ_WRITE 0x3
228#define HI_RA_RAM_SLV1_FLG_ACC_BRC__B 2
229#define HI_RA_RAM_SLV1_FLG_ACC_BRC__W 1
230#define HI_RA_RAM_SLV1_FLG_ACC_BRC__M 0x4
231#define HI_RA_RAM_SLV1_FLG_ACC_BRC_NORMAL 0x0
232#define HI_RA_RAM_SLV1_FLG_ACC_BRC_BROADCAST 0x4
233
234
235#define HI_RA_RAM_SLV1_STATE__A 0x420024
236#define HI_RA_RAM_SLV1_STATE__W 1
237#define HI_RA_RAM_SLV1_STATE__M 0x1
238#define HI_RA_RAM_SLV1_STATE_ADDRESS 0x0
239#define HI_RA_RAM_SLV1_STATE_DATA 0x1
240
241
242#define HI_RA_RAM_SLV1_BLK_BNK__A 0x420025
243#define HI_RA_RAM_SLV1_BLK_BNK__W 12
244#define HI_RA_RAM_SLV1_BLK_BNK__M 0xFFF
245#define HI_RA_RAM_SLV1_BLK_BNK_BNK__B 0
246#define HI_RA_RAM_SLV1_BLK_BNK_BNK__W 6
247#define HI_RA_RAM_SLV1_BLK_BNK_BNK__M 0x3F
248#define HI_RA_RAM_SLV1_BLK_BNK_BLK__B 6
249#define HI_RA_RAM_SLV1_BLK_BNK_BLK__W 6
250#define HI_RA_RAM_SLV1_BLK_BNK_BLK__M 0xFC0
251
252
253#define HI_RA_RAM_SLV1_ADDR__A 0x420026
254#define HI_RA_RAM_SLV1_ADDR__W 16
255#define HI_RA_RAM_SLV1_ADDR__M 0xFFFF
256
257#define HI_RA_RAM_SLV1_CRC__A 0x420027
258#define HI_RA_RAM_SLV1_CRC__W 16
259#define HI_RA_RAM_SLV1_CRC__M 0xFFFF
260
261#define HI_RA_RAM_SLV1_READBACK__A 0x420028
262#define HI_RA_RAM_SLV1_READBACK__W 16
263#define HI_RA_RAM_SLV1_READBACK__M 0xFFFF
264
265
266
267
268#define HI_RA_RAM_SRV_SEM__A 0x420030
269#define HI_RA_RAM_SRV_SEM__W 1
270#define HI_RA_RAM_SRV_SEM__M 0x1
271#define HI_RA_RAM_SRV_SEM_FREE 0x0
272#define HI_RA_RAM_SRV_SEM_CLAIMED 0x1
273
274
275#define HI_RA_RAM_SRV_RES__A 0x420031
276#define HI_RA_RAM_SRV_RES__W 3
277#define HI_RA_RAM_SRV_RES__M 0x7
278#define HI_RA_RAM_SRV_RES_OK 0x0
279#define HI_RA_RAM_SRV_RES_START_FOUND_OR_ERROR 0x1
280#define HI_RA_RAM_SRV_RES_STOP_FOUND 0x2
281#define HI_RA_RAM_SRV_RES_ARBITRATION_FAILED 0x3
282#define HI_RA_RAM_SRV_RES_INTERNAL_ERROR 0x4
283
284
285#define HI_RA_RAM_SRV_CMD__A 0x420032
286#define HI_RA_RAM_SRV_CMD__W 3
287#define HI_RA_RAM_SRV_CMD__M 0x7
288#define HI_RA_RAM_SRV_CMD_NULL 0x0
289#define HI_RA_RAM_SRV_CMD_UIO 0x1
290#define HI_RA_RAM_SRV_CMD_RESET 0x2
291#define HI_RA_RAM_SRV_CMD_CONFIG 0x3
292#define HI_RA_RAM_SRV_CMD_COPY 0x4
293#define HI_RA_RAM_SRV_CMD_TRANSMIT 0x5
294#define HI_RA_RAM_SRV_CMD_EXECUTE 0x6
295
296
297#define HI_RA_RAM_SRV_PAR__AX 0x420033
298#define HI_RA_RAM_SRV_PAR__XSZ 5
299#define HI_RA_RAM_SRV_PAR__W 16
300#define HI_RA_RAM_SRV_PAR__M 0xFFFF
301
302
303
304#define HI_RA_RAM_SRV_NOP_RES__A 0x420031
305#define HI_RA_RAM_SRV_NOP_RES__W 3
306#define HI_RA_RAM_SRV_NOP_RES__M 0x7
307#define HI_RA_RAM_SRV_NOP_RES_OK 0x0
308#define HI_RA_RAM_SRV_NOP_RES_INTERNAL_ERROR 0x4
309
310
311
312#define HI_RA_RAM_SRV_UIO_RES__A 0x420031
313#define HI_RA_RAM_SRV_UIO_RES__W 3
314#define HI_RA_RAM_SRV_UIO_RES__M 0x7
315#define HI_RA_RAM_SRV_UIO_RES_LO 0x0
316#define HI_RA_RAM_SRV_UIO_RES_HI 0x1
317
318#define HI_RA_RAM_SRV_UIO_KEY__A 0x420033
319#define HI_RA_RAM_SRV_UIO_KEY__W 16
320#define HI_RA_RAM_SRV_UIO_KEY__M 0xFFFF
321#define HI_RA_RAM_SRV_UIO_KEY_ACT 0x3973
322
323#define HI_RA_RAM_SRV_UIO_SEL__A 0x420034
324#define HI_RA_RAM_SRV_UIO_SEL__W 2
325#define HI_RA_RAM_SRV_UIO_SEL__M 0x3
326#define HI_RA_RAM_SRV_UIO_SEL_ASEL 0x0
327#define HI_RA_RAM_SRV_UIO_SEL_UIO 0x1
328
329#define HI_RA_RAM_SRV_UIO_SET__A 0x420035
330#define HI_RA_RAM_SRV_UIO_SET__W 2
331#define HI_RA_RAM_SRV_UIO_SET__M 0x3
332#define HI_RA_RAM_SRV_UIO_SET_OUT__B 0
333#define HI_RA_RAM_SRV_UIO_SET_OUT__W 1
334#define HI_RA_RAM_SRV_UIO_SET_OUT__M 0x1
335#define HI_RA_RAM_SRV_UIO_SET_OUT_LO 0x0
336#define HI_RA_RAM_SRV_UIO_SET_OUT_HI 0x1
337#define HI_RA_RAM_SRV_UIO_SET_DIR__B 1
338#define HI_RA_RAM_SRV_UIO_SET_DIR__W 1
339#define HI_RA_RAM_SRV_UIO_SET_DIR__M 0x2
340#define HI_RA_RAM_SRV_UIO_SET_DIR_OUT 0x0
341#define HI_RA_RAM_SRV_UIO_SET_DIR_IN 0x2
342
343
344
345#define HI_RA_RAM_SRV_RST_RES__A 0x420031
346#define HI_RA_RAM_SRV_RST_RES__W 1
347#define HI_RA_RAM_SRV_RST_RES__M 0x1
348#define HI_RA_RAM_SRV_RST_RES_OK 0x0
349#define HI_RA_RAM_SRV_RST_RES_ERROR 0x1
350
351#define HI_RA_RAM_SRV_RST_KEY__A 0x420033
352#define HI_RA_RAM_SRV_RST_KEY__W 16
353#define HI_RA_RAM_SRV_RST_KEY__M 0xFFFF
354#define HI_RA_RAM_SRV_RST_KEY_ACT 0x3973
355
356
357
358#define HI_RA_RAM_SRV_CFG_RES__A 0x420031
359#define HI_RA_RAM_SRV_CFG_RES__W 1
360#define HI_RA_RAM_SRV_CFG_RES__M 0x1
361#define HI_RA_RAM_SRV_CFG_RES_OK 0x0
362#define HI_RA_RAM_SRV_CFG_RES_ERROR 0x1
363
364#define HI_RA_RAM_SRV_CFG_KEY__A 0x420033
365#define HI_RA_RAM_SRV_CFG_KEY__W 16
366#define HI_RA_RAM_SRV_CFG_KEY__M 0xFFFF
367#define HI_RA_RAM_SRV_CFG_KEY_ACT 0x3973
368
369
370#define HI_RA_RAM_SRV_CFG_DIV__A 0x420034
371#define HI_RA_RAM_SRV_CFG_DIV__W 5
372#define HI_RA_RAM_SRV_CFG_DIV__M 0x1F
373
374#define HI_RA_RAM_SRV_CFG_BDL__A 0x420035
375#define HI_RA_RAM_SRV_CFG_BDL__W 6
376#define HI_RA_RAM_SRV_CFG_BDL__M 0x3F
377
378#define HI_RA_RAM_SRV_CFG_WUP__A 0x420036
379#define HI_RA_RAM_SRV_CFG_WUP__W 8
380#define HI_RA_RAM_SRV_CFG_WUP__M 0xFF
381
382#define HI_RA_RAM_SRV_CFG_ACT__A 0x420037
383#define HI_RA_RAM_SRV_CFG_ACT__W 4
384#define HI_RA_RAM_SRV_CFG_ACT__M 0xF
385#define HI_RA_RAM_SRV_CFG_ACT_SLV0__B 0
386#define HI_RA_RAM_SRV_CFG_ACT_SLV0__W 1
387#define HI_RA_RAM_SRV_CFG_ACT_SLV0__M 0x1
388#define HI_RA_RAM_SRV_CFG_ACT_SLV0_OFF 0x0
389#define HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1
390#define HI_RA_RAM_SRV_CFG_ACT_SLV1__B 1
391#define HI_RA_RAM_SRV_CFG_ACT_SLV1__W 1
392#define HI_RA_RAM_SRV_CFG_ACT_SLV1__M 0x2
393#define HI_RA_RAM_SRV_CFG_ACT_SLV1_OFF 0x0
394#define HI_RA_RAM_SRV_CFG_ACT_SLV1_ON 0x2
395#define HI_RA_RAM_SRV_CFG_ACT_BRD__B 2
396#define HI_RA_RAM_SRV_CFG_ACT_BRD__W 1
397#define HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4
398#define HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0
399#define HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4
400#define HI_RA_RAM_SRV_CFG_ACT_PWD__B 3
401#define HI_RA_RAM_SRV_CFG_ACT_PWD__W 1
402#define HI_RA_RAM_SRV_CFG_ACT_PWD__M 0x8
403#define HI_RA_RAM_SRV_CFG_ACT_PWD_NOP 0x0
404#define HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8
405
406
407
408#define HI_RA_RAM_SRV_CPY_RES__A 0x420031
409#define HI_RA_RAM_SRV_CPY_RES__W 1
410#define HI_RA_RAM_SRV_CPY_RES__M 0x1
411#define HI_RA_RAM_SRV_CPY_RES_OK 0x0
412#define HI_RA_RAM_SRV_CPY_RES_ERROR 0x1
413
414
415#define HI_RA_RAM_SRV_CPY_SBB__A 0x420033
416#define HI_RA_RAM_SRV_CPY_SBB__W 12
417#define HI_RA_RAM_SRV_CPY_SBB__M 0xFFF
418#define HI_RA_RAM_SRV_CPY_SBB_BNK__B 0
419#define HI_RA_RAM_SRV_CPY_SBB_BNK__W 6
420#define HI_RA_RAM_SRV_CPY_SBB_BNK__M 0x3F
421#define HI_RA_RAM_SRV_CPY_SBB_BLK__B 6
422#define HI_RA_RAM_SRV_CPY_SBB_BLK__W 6
423#define HI_RA_RAM_SRV_CPY_SBB_BLK__M 0xFC0
424
425
426#define HI_RA_RAM_SRV_CPY_SAD__A 0x420034
427#define HI_RA_RAM_SRV_CPY_SAD__W 16
428#define HI_RA_RAM_SRV_CPY_SAD__M 0xFFFF
429
430#define HI_RA_RAM_SRV_CPY_LEN__A 0x420035
431#define HI_RA_RAM_SRV_CPY_LEN__W 16
432#define HI_RA_RAM_SRV_CPY_LEN__M 0xFFFF
433
434#define HI_RA_RAM_SRV_CPY_DBB__A 0x420033
435#define HI_RA_RAM_SRV_CPY_DBB__W 12
436#define HI_RA_RAM_SRV_CPY_DBB__M 0xFFF
437#define HI_RA_RAM_SRV_CPY_DBB_BNK__B 0
438#define HI_RA_RAM_SRV_CPY_DBB_BNK__W 6
439#define HI_RA_RAM_SRV_CPY_DBB_BNK__M 0x3F
440#define HI_RA_RAM_SRV_CPY_DBB_BLK__B 6
441#define HI_RA_RAM_SRV_CPY_DBB_BLK__W 6
442#define HI_RA_RAM_SRV_CPY_DBB_BLK__M 0xFC0
443
444
445#define HI_RA_RAM_SRV_CPY_DAD__A 0x420034
446#define HI_RA_RAM_SRV_CPY_DAD__W 16
447#define HI_RA_RAM_SRV_CPY_DAD__M 0xFFFF
448
449
450
451#define HI_RA_RAM_SRV_TRM_RES__A 0x420031
452#define HI_RA_RAM_SRV_TRM_RES__W 2
453#define HI_RA_RAM_SRV_TRM_RES__M 0x3
454#define HI_RA_RAM_SRV_TRM_RES_OK 0x0
455#define HI_RA_RAM_SRV_TRM_RES_ERROR 0x1
456#define HI_RA_RAM_SRV_TRM_RES_ARBITRATION_FAILED 0x3
457
458
459#define HI_RA_RAM_SRV_TRM_MST__A 0x420033
460#define HI_RA_RAM_SRV_TRM_MST__W 12
461#define HI_RA_RAM_SRV_TRM_MST__M 0xFFF
462
463#define HI_RA_RAM_SRV_TRM_SEQ__A 0x420034
464#define HI_RA_RAM_SRV_TRM_SEQ__W 7
465#define HI_RA_RAM_SRV_TRM_SEQ__M 0x7F
466
467#define HI_RA_RAM_SRV_TRM_TRM__A 0x420035
468#define HI_RA_RAM_SRV_TRM_TRM__W 15
469#define HI_RA_RAM_SRV_TRM_TRM__M 0x7FFF
470#define HI_RA_RAM_SRV_TRM_TRM_DAT__B 0
471#define HI_RA_RAM_SRV_TRM_TRM_DAT__W 8
472#define HI_RA_RAM_SRV_TRM_TRM_DAT__M 0xFF
473
474
475#define HI_RA_RAM_SRV_TRM_DBB__A 0x420033
476#define HI_RA_RAM_SRV_TRM_DBB__W 12
477#define HI_RA_RAM_SRV_TRM_DBB__M 0xFFF
478#define HI_RA_RAM_SRV_TRM_DBB_BNK__B 0
479#define HI_RA_RAM_SRV_TRM_DBB_BNK__W 6
480#define HI_RA_RAM_SRV_TRM_DBB_BNK__M 0x3F
481#define HI_RA_RAM_SRV_TRM_DBB_BLK__B 6
482#define HI_RA_RAM_SRV_TRM_DBB_BLK__W 6
483#define HI_RA_RAM_SRV_TRM_DBB_BLK__M 0xFC0
484
485
486#define HI_RA_RAM_SRV_TRM_DAD__A 0x420034
487#define HI_RA_RAM_SRV_TRM_DAD__W 16
488#define HI_RA_RAM_SRV_TRM_DAD__M 0xFFFF
489
490
491
492
493#define HI_RA_RAM_USR_BEGIN__A 0x420040
494#define HI_RA_RAM_USR_BEGIN__W 16
495#define HI_RA_RAM_USR_BEGIN__M 0xFFFF
496
497#define HI_RA_RAM_USR_END__A 0x42007F
498#define HI_RA_RAM_USR_END__W 16
499#define HI_RA_RAM_USR_END__M 0xFFFF
500
501
502
503
504
505
506#define HI_IF_RAM_TRP_BPT0__AX 0x430000
507#define HI_IF_RAM_TRP_BPT0__XSZ 2
508#define HI_IF_RAM_TRP_BPT0__W 12
509#define HI_IF_RAM_TRP_BPT0__M 0xFFF
510
511#define HI_IF_RAM_TRP_STKU__AX 0x430002
512#define HI_IF_RAM_TRP_STKU__XSZ 2
513#define HI_IF_RAM_TRP_STKU__W 12
514#define HI_IF_RAM_TRP_STKU__M 0xFFF
515
516
517
518
519#define HI_IF_RAM_USR_BEGIN__A 0x430200
520#define HI_IF_RAM_USR_BEGIN__W 12
521#define HI_IF_RAM_USR_BEGIN__M 0xFFF
522
523#define HI_IF_RAM_USR_END__A 0x4303FF
524#define HI_IF_RAM_USR_END__W 12
525#define HI_IF_RAM_USR_END__M 0xFFF
526
527
528
529
530
531#define SC_SID 0x11
532
533
534
535
536
537#define SC_COMM_EXEC__A 0x800000
538#define SC_COMM_EXEC__W 3
539#define SC_COMM_EXEC__M 0x7
540#define SC_COMM_EXEC_CTL__B 0
541#define SC_COMM_EXEC_CTL__W 3
542#define SC_COMM_EXEC_CTL__M 0x7
543#define SC_COMM_EXEC_CTL_STOP 0x0
544#define SC_COMM_EXEC_CTL_ACTIVE 0x1
545#define SC_COMM_EXEC_CTL_HOLD 0x2
546#define SC_COMM_EXEC_CTL_STEP 0x3
547#define SC_COMM_EXEC_CTL_BYPASS_STOP 0x4
548#define SC_COMM_EXEC_CTL_BYPASS_HOLD 0x6
549
550#define SC_COMM_STATE__A 0x800001
551#define SC_COMM_STATE__W 16
552#define SC_COMM_STATE__M 0xFFFF
553#define SC_COMM_MB__A 0x800002
554#define SC_COMM_MB__W 16
555#define SC_COMM_MB__M 0xFFFF
556#define SC_COMM_SERVICE0__A 0x800003
557#define SC_COMM_SERVICE0__W 16
558#define SC_COMM_SERVICE0__M 0xFFFF
559#define SC_COMM_SERVICE1__A 0x800004
560#define SC_COMM_SERVICE1__W 16
561#define SC_COMM_SERVICE1__M 0xFFFF
562#define SC_COMM_INT_STA__A 0x800007
563#define SC_COMM_INT_STA__W 16
564#define SC_COMM_INT_STA__M 0xFFFF
565#define SC_COMM_INT_MSK__A 0x800008
566#define SC_COMM_INT_MSK__W 16
567#define SC_COMM_INT_MSK__M 0xFFFF
568
569
570
571
572
573
574#define SC_CT_REG_COMM_EXEC__A 0x810000
575#define SC_CT_REG_COMM_EXEC__W 3
576#define SC_CT_REG_COMM_EXEC__M 0x7
577#define SC_CT_REG_COMM_EXEC_CTL__B 0
578#define SC_CT_REG_COMM_EXEC_CTL__W 3
579#define SC_CT_REG_COMM_EXEC_CTL__M 0x7
580#define SC_CT_REG_COMM_EXEC_CTL_STOP 0x0
581#define SC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1
582#define SC_CT_REG_COMM_EXEC_CTL_HOLD 0x2
583#define SC_CT_REG_COMM_EXEC_CTL_STEP 0x3
584
585
586#define SC_CT_REG_COMM_STATE__A 0x810001
587#define SC_CT_REG_COMM_STATE__W 10
588#define SC_CT_REG_COMM_STATE__M 0x3FF
589#define SC_CT_REG_COMM_SERVICE0__A 0x810003
590#define SC_CT_REG_COMM_SERVICE0__W 16
591#define SC_CT_REG_COMM_SERVICE0__M 0xFFFF
592#define SC_CT_REG_COMM_SERVICE1__A 0x810004
593#define SC_CT_REG_COMM_SERVICE1__W 16
594#define SC_CT_REG_COMM_SERVICE1__M 0xFFFF
595#define SC_CT_REG_COMM_SERVICE1_SC__B 1
596#define SC_CT_REG_COMM_SERVICE1_SC__W 1
597#define SC_CT_REG_COMM_SERVICE1_SC__M 0x2
598
599
600#define SC_CT_REG_COMM_INT_STA__A 0x810007
601#define SC_CT_REG_COMM_INT_STA__W 1
602#define SC_CT_REG_COMM_INT_STA__M 0x1
603#define SC_CT_REG_COMM_INT_STA_REQUEST__B 0
604#define SC_CT_REG_COMM_INT_STA_REQUEST__W 1
605#define SC_CT_REG_COMM_INT_STA_REQUEST__M 0x1
606
607
608#define SC_CT_REG_COMM_INT_MSK__A 0x810008
609#define SC_CT_REG_COMM_INT_MSK__W 1
610#define SC_CT_REG_COMM_INT_MSK__M 0x1
611#define SC_CT_REG_COMM_INT_MSK_REQUEST__B 0
612#define SC_CT_REG_COMM_INT_MSK_REQUEST__W 1
613#define SC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1
614
615
616
617
618#define SC_CT_REG_CTL_STK__AX 0x810010
619#define SC_CT_REG_CTL_STK__XSZ 4
620#define SC_CT_REG_CTL_STK__W 10
621#define SC_CT_REG_CTL_STK__M 0x3FF
622
623#define SC_CT_REG_CTL_BPT_IDX__A 0x81001F
624#define SC_CT_REG_CTL_BPT_IDX__W 1
625#define SC_CT_REG_CTL_BPT_IDX__M 0x1
626
627#define SC_CT_REG_CTL_BPT__A 0x810020
628#define SC_CT_REG_CTL_BPT__W 10
629#define SC_CT_REG_CTL_BPT__M 0x3FF
630
631
632
633
634
635#define SC_RA_RAM_PARAM0__A 0x820040
636#define SC_RA_RAM_PARAM0__W 16
637#define SC_RA_RAM_PARAM0__M 0xFFFF
638#define SC_RA_RAM_PARAM1__A 0x820041
639#define SC_RA_RAM_PARAM1__W 16
640#define SC_RA_RAM_PARAM1__M 0xFFFF
641#define SC_RA_RAM_CMD_ADDR__A 0x820042
642#define SC_RA_RAM_CMD_ADDR__W 16
643#define SC_RA_RAM_CMD_ADDR__M 0xFFFF
644#define SC_RA_RAM_CMD__A 0x820043
645#define SC_RA_RAM_CMD__W 16
646#define SC_RA_RAM_CMD__M 0xFFFF
647#define SC_RA_RAM_CMD_NULL 0x0
648#define SC_RA_RAM_CMD_PROC_START 0x1
649#define SC_RA_RAM_CMD_PROC_TRIGGER 0x2
650#define SC_RA_RAM_CMD_SET_PREF_PARAM 0x3
651#define SC_RA_RAM_CMD_PROGRAM_PARAM 0x4
652#define SC_RA_RAM_CMD_GET_OP_PARAM 0x5
653#define SC_RA_RAM_CMD_USER_IO 0x6
654#define SC_RA_RAM_CMD_SET_TIMER 0x7
655#define SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8
656#define SC_RA_RAM_CMD_MAX 0x8
657#define SC_RA_RAM_CMDBLOCK__C 0x4
658
659#define SC_RA_RAM_PROC_ACTIVATE__A 0x820044
660#define SC_RA_RAM_PROC_ACTIVATE__W 16
661#define SC_RA_RAM_PROC_ACTIVATE__M 0xFFFF
662#define SC_RA_RAM_PROC_ACTIVATE__PRE 0xFFFF
663#define SC_RA_RAM_PROC_TERMINATED__A 0x820045
664#define SC_RA_RAM_PROC_TERMINATED__W 16
665#define SC_RA_RAM_PROC_TERMINATED__M 0xFFFF
666#define SC_RA_RAM_SW_EVENT__A 0x820046
667#define SC_RA_RAM_SW_EVENT__W 14
668#define SC_RA_RAM_SW_EVENT__M 0x3FFF
669#define SC_RA_RAM_SW_EVENT_RUN_NMASK__B 0
670#define SC_RA_RAM_SW_EVENT_RUN_NMASK__W 1
671#define SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1
672#define SC_RA_RAM_SW_EVENT_RUN__B 1
673#define SC_RA_RAM_SW_EVENT_RUN__W 1
674#define SC_RA_RAM_SW_EVENT_RUN__M 0x2
675#define SC_RA_RAM_SW_EVENT_TERMINATE__B 2
676#define SC_RA_RAM_SW_EVENT_TERMINATE__W 1
677#define SC_RA_RAM_SW_EVENT_TERMINATE__M 0x4
678#define SC_RA_RAM_SW_EVENT_FT_START__B 3
679#define SC_RA_RAM_SW_EVENT_FT_START__W 1
680#define SC_RA_RAM_SW_EVENT_FT_START__M 0x8
681#define SC_RA_RAM_SW_EVENT_FI_START__B 4
682#define SC_RA_RAM_SW_EVENT_FI_START__W 1
683#define SC_RA_RAM_SW_EVENT_FI_START__M 0x10
684#define SC_RA_RAM_SW_EVENT_EQ_TPS__B 5
685#define SC_RA_RAM_SW_EVENT_EQ_TPS__W 1
686#define SC_RA_RAM_SW_EVENT_EQ_TPS__M 0x20
687#define SC_RA_RAM_SW_EVENT_EQ_ERR__B 6
688#define SC_RA_RAM_SW_EVENT_EQ_ERR__W 1
689#define SC_RA_RAM_SW_EVENT_EQ_ERR__M 0x40
690#define SC_RA_RAM_SW_EVENT_CE_IR__B 7
691#define SC_RA_RAM_SW_EVENT_CE_IR__W 1
692#define SC_RA_RAM_SW_EVENT_CE_IR__M 0x80
693#define SC_RA_RAM_SW_EVENT_FE_FD__B 8
694#define SC_RA_RAM_SW_EVENT_FE_FD__W 1
695#define SC_RA_RAM_SW_EVENT_FE_FD__M 0x100
696#define SC_RA_RAM_SW_EVENT_FE_CF__B 9
697#define SC_RA_RAM_SW_EVENT_FE_CF__W 1
698#define SC_RA_RAM_SW_EVENT_FE_CF__M 0x200
699#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_FOUND__B 10
700#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_FOUND__W 1
701#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_FOUND__M 0x400
702#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_LOST__B 11
703#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_LOST__W 1
704#define SC_RA_RAM_SW_EVENT_DEMOD_LOCK_LOST__M 0x800
705
706#define SC_RA_RAM_LOCKTRACK__A 0x820047
707#define SC_RA_RAM_LOCKTRACK__W 16
708#define SC_RA_RAM_LOCKTRACK__M 0xFFFF
709#define SC_RA_RAM_LOCKTRACK_NULL 0x0
710#define SC_RA_RAM_LOCKTRACK_MIN 0x1
711#define SC_RA_RAM_LOCKTRACK_RESET 0x1
712#define SC_RA_RAM_LOCKTRACK_MG_DETECT 0x2
713#define SC_RA_RAM_LOCKTRACK_P_DETECT 0x3
714#define SC_RA_RAM_LOCKTRACK_P_DETECT_SEARCH 0x4
715#define SC_RA_RAM_LOCKTRACK_P_DETECT_MIRROR 0x5
716#define SC_RA_RAM_LOCKTRACK_LC 0x6
717#define SC_RA_RAM_LOCKTRACK_P_ECHO 0x7
718#define SC_RA_RAM_LOCKTRACK_NE_INIT 0x8
719#define SC_RA_RAM_LOCKTRACK_TRACK_INIT 0x9
720#define SC_RA_RAM_LOCKTRACK_TRACK 0xA
721#define SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0xB
722#define SC_RA_RAM_LOCKTRACK_SR_SCANNING 0xC
723#define SC_RA_RAM_LOCKTRACK_MAX 0xD
724
725
726
727#define SC_RA_RAM_OP_PARAM__A 0x820048
728#define SC_RA_RAM_OP_PARAM__W 13
729#define SC_RA_RAM_OP_PARAM__M 0x1FFF
730#define SC_RA_RAM_OP_PARAM_MODE__B 0
731#define SC_RA_RAM_OP_PARAM_MODE__W 2
732#define SC_RA_RAM_OP_PARAM_MODE__M 0x3
733#define SC_RA_RAM_OP_PARAM_MODE_2K 0x0
734#define SC_RA_RAM_OP_PARAM_MODE_8K 0x1
735#define SC_RA_RAM_OP_PARAM_GUARD__B 2
736#define SC_RA_RAM_OP_PARAM_GUARD__W 2
737#define SC_RA_RAM_OP_PARAM_GUARD__M 0xC
738#define SC_RA_RAM_OP_PARAM_GUARD_32 0x0
739#define SC_RA_RAM_OP_PARAM_GUARD_16 0x4
740#define SC_RA_RAM_OP_PARAM_GUARD_8 0x8
741#define SC_RA_RAM_OP_PARAM_GUARD_4 0xC
742#define SC_RA_RAM_OP_PARAM_CONST__B 4
743#define SC_RA_RAM_OP_PARAM_CONST__W 2
744#define SC_RA_RAM_OP_PARAM_CONST__M 0x30
745#define SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0
746#define SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10
747#define SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20
748#define SC_RA_RAM_OP_PARAM_HIER__B 6
749#define SC_RA_RAM_OP_PARAM_HIER__W 3
750#define SC_RA_RAM_OP_PARAM_HIER__M 0x1C0
751#define SC_RA_RAM_OP_PARAM_HIER_NO 0x0
752#define SC_RA_RAM_OP_PARAM_HIER_A1 0x40
753#define SC_RA_RAM_OP_PARAM_HIER_A2 0x80
754#define SC_RA_RAM_OP_PARAM_HIER_A4 0xC0
755#define SC_RA_RAM_OP_PARAM_RATE__B 9
756#define SC_RA_RAM_OP_PARAM_RATE__W 3
757#define SC_RA_RAM_OP_PARAM_RATE__M 0xE00
758#define SC_RA_RAM_OP_PARAM_RATE_1_2 0x0
759#define SC_RA_RAM_OP_PARAM_RATE_2_3 0x200
760#define SC_RA_RAM_OP_PARAM_RATE_3_4 0x400
761#define SC_RA_RAM_OP_PARAM_RATE_5_6 0x600
762#define SC_RA_RAM_OP_PARAM_RATE_7_8 0x800
763#define SC_RA_RAM_OP_PARAM_PRIO__B 12
764#define SC_RA_RAM_OP_PARAM_PRIO__W 1
765#define SC_RA_RAM_OP_PARAM_PRIO__M 0x1000
766#define SC_RA_RAM_OP_PARAM_PRIO_HI 0x0
767#define SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000
768
769#define SC_RA_RAM_OP_AUTO__A 0x820049
770#define SC_RA_RAM_OP_AUTO__W 6
771#define SC_RA_RAM_OP_AUTO__M 0x3F
772#define SC_RA_RAM_OP_AUTO__PRE 0x1F
773#define SC_RA_RAM_OP_AUTO_MODE__B 0
774#define SC_RA_RAM_OP_AUTO_MODE__W 1
775#define SC_RA_RAM_OP_AUTO_MODE__M 0x1
776#define SC_RA_RAM_OP_AUTO_GUARD__B 1
777#define SC_RA_RAM_OP_AUTO_GUARD__W 1
778#define SC_RA_RAM_OP_AUTO_GUARD__M 0x2
779#define SC_RA_RAM_OP_AUTO_CONST__B 2
780#define SC_RA_RAM_OP_AUTO_CONST__W 1
781#define SC_RA_RAM_OP_AUTO_CONST__M 0x4
782#define SC_RA_RAM_OP_AUTO_HIER__B 3
783#define SC_RA_RAM_OP_AUTO_HIER__W 1
784#define SC_RA_RAM_OP_AUTO_HIER__M 0x8
785#define SC_RA_RAM_OP_AUTO_RATE__B 4
786#define SC_RA_RAM_OP_AUTO_RATE__W 1
787#define SC_RA_RAM_OP_AUTO_RATE__M 0x10
788#define SC_RA_RAM_OP_AUTO_PRIO__B 5
789#define SC_RA_RAM_OP_AUTO_PRIO__W 1
790#define SC_RA_RAM_OP_AUTO_PRIO__M 0x20
791
792#define SC_RA_RAM_PILOT_STATUS__A 0x82004A
793#define SC_RA_RAM_PILOT_STATUS__W 16
794#define SC_RA_RAM_PILOT_STATUS__M 0xFFFF
795#define SC_RA_RAM_PILOT_STATUS_OK 0x0
796#define SC_RA_RAM_PILOT_STATUS_SPD_ERROR 0x1
797#define SC_RA_RAM_PILOT_STATUS_CPD_ERROR 0x2
798
799#define SC_RA_RAM_LOCK__A 0x82004B
800#define SC_RA_RAM_LOCK__W 4
801#define SC_RA_RAM_LOCK__M 0xF
802#define SC_RA_RAM_LOCK_DEMOD__B 0
803#define SC_RA_RAM_LOCK_DEMOD__W 1
804#define SC_RA_RAM_LOCK_DEMOD__M 0x1
805#define SC_RA_RAM_LOCK_FEC__B 1
806#define SC_RA_RAM_LOCK_FEC__W 1
807#define SC_RA_RAM_LOCK_FEC__M 0x2
808#define SC_RA_RAM_LOCK_MPEG__B 2
809#define SC_RA_RAM_LOCK_MPEG__W 1
810#define SC_RA_RAM_LOCK_MPEG__M 0x4
811#define SC_RA_RAM_LOCK_NODVBT__B 3
812#define SC_RA_RAM_LOCK_NODVBT__W 1
813#define SC_RA_RAM_LOCK_NODVBT__M 0x8
814
815
816
817#define SC_RA_RAM_BE_OPT_ENA__A 0x82004C
818#define SC_RA_RAM_BE_OPT_ENA__W 5
819#define SC_RA_RAM_BE_OPT_ENA__M 0x1F
820#define SC_RA_RAM_BE_OPT_ENA__PRE 0x14
821#define SC_RA_RAM_BE_OPT_ENA_MOTION 0x0
822#define SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1
823#define SC_RA_RAM_BE_OPT_ENA_COCHANNEL 0x2
824#define SC_RA_RAM_BE_OPT_ENA_FR_WATCH 0x4
825#define SC_RA_RAM_BE_OPT_ENA_MAX 0x5
826
827#define SC_RA_RAM_BE_OPT_DELAY__A 0x82004D
828#define SC_RA_RAM_BE_OPT_DELAY__W 16
829#define SC_RA_RAM_BE_OPT_DELAY__M 0xFFFF
830#define SC_RA_RAM_BE_OPT_DELAY__PRE 0x200
831#define SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x82004E
832#define SC_RA_RAM_BE_OPT_INIT_DELAY__W 16
833#define SC_RA_RAM_BE_OPT_INIT_DELAY__M 0xFFFF
834#define SC_RA_RAM_BE_OPT_INIT_DELAY__PRE 0x400
835#define SC_RA_RAM_ECHO_THRES__A 0x82004F
836#define SC_RA_RAM_ECHO_THRES__W 16
837#define SC_RA_RAM_ECHO_THRES__M 0xFFFF
838#define SC_RA_RAM_ECHO_THRES__PRE 0x2A
839#define SC_RA_RAM_CONFIG__A 0x820050
840#define SC_RA_RAM_CONFIG__W 16
841#define SC_RA_RAM_CONFIG__M 0xFFFF
842#define SC_RA_RAM_CONFIG__PRE 0x54
843#define SC_RA_RAM_CONFIG_ID__B 0
844#define SC_RA_RAM_CONFIG_ID__W 1
845#define SC_RA_RAM_CONFIG_ID__M 0x1
846#define SC_RA_RAM_CONFIG_ID_PRO 0x0
847#define SC_RA_RAM_CONFIG_ID_CONSUMER 0x1
848#define SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__B 1
849#define SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__W 1
850#define SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__M 0x2
851#define SC_RA_RAM_CONFIG_FR_ENABLE__B 2
852#define SC_RA_RAM_CONFIG_FR_ENABLE__W 1
853#define SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4
854#define SC_RA_RAM_CONFIG_MIXMODE__B 3
855#define SC_RA_RAM_CONFIG_MIXMODE__W 1
856#define SC_RA_RAM_CONFIG_MIXMODE__M 0x8
857#define SC_RA_RAM_CONFIG_FREQSCAN__B 4
858#define SC_RA_RAM_CONFIG_FREQSCAN__W 1
859#define SC_RA_RAM_CONFIG_FREQSCAN__M 0x10
860#define SC_RA_RAM_CONFIG_SLAVE__B 5
861#define SC_RA_RAM_CONFIG_SLAVE__W 1
862#define SC_RA_RAM_CONFIG_SLAVE__M 0x20
863#define SC_RA_RAM_CONFIG_FAR_OFF__B 6
864#define SC_RA_RAM_CONFIG_FAR_OFF__W 1
865#define SC_RA_RAM_CONFIG_FAR_OFF__M 0x40
866#define SC_RA_RAM_CONFIG_FEC_CHECK_ON__B 7
867#define SC_RA_RAM_CONFIG_FEC_CHECK_ON__W 1
868#define SC_RA_RAM_CONFIG_FEC_CHECK_ON__M 0x80
869#define SC_RA_RAM_CONFIG_ECHO_UPDATED__B 8
870#define SC_RA_RAM_CONFIG_ECHO_UPDATED__W 1
871#define SC_RA_RAM_CONFIG_ECHO_UPDATED__M 0x100
872#define SC_RA_RAM_CONFIG_ADJUST_OFF__B 15
873#define SC_RA_RAM_CONFIG_ADJUST_OFF__W 1
874#define SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000
875
876
877
878#define SC_RA_RAM_PILOT_THRES_SPD__A 0x820051
879#define SC_RA_RAM_PILOT_THRES_SPD__W 16
880#define SC_RA_RAM_PILOT_THRES_SPD__M 0xFFFF
881#define SC_RA_RAM_PILOT_THRES_SPD__PRE 0x4
882#define SC_RA_RAM_PILOT_THRES_CPD__A 0x820052
883#define SC_RA_RAM_PILOT_THRES_CPD__W 16
884#define SC_RA_RAM_PILOT_THRES_CPD__M 0xFFFF
885#define SC_RA_RAM_PILOT_THRES_CPD__PRE 0x4
886#define SC_RA_RAM_PILOT_THRES_FREQSCAN__A 0x820053
887#define SC_RA_RAM_PILOT_THRES_FREQSCAN__W 16
888#define SC_RA_RAM_PILOT_THRES_FREQSCAN__M 0xFFFF
889#define SC_RA_RAM_PILOT_THRES_FREQSCAN__PRE 0x406
890
891
892
893#define SC_RA_RAM_CO_THRES_8K__A 0x820055
894#define SC_RA_RAM_CO_THRES_8K__W 16
895#define SC_RA_RAM_CO_THRES_8K__M 0xFFFF
896#define SC_RA_RAM_CO_THRES_8K__PRE 0x10E
897#define SC_RA_RAM_CO_THRES_2K__A 0x820056
898#define SC_RA_RAM_CO_THRES_2K__W 16
899#define SC_RA_RAM_CO_THRES_2K__M 0xFFFF
900#define SC_RA_RAM_CO_THRES_2K__PRE 0x208
901#define SC_RA_RAM_CO_LEVEL__A 0x820057
902#define SC_RA_RAM_CO_LEVEL__W 16
903#define SC_RA_RAM_CO_LEVEL__M 0xFFFF
904#define SC_RA_RAM_CO_DETECT__A 0x820058
905#define SC_RA_RAM_CO_DETECT__W 16
906#define SC_RA_RAM_CO_DETECT__M 0xFFFF
907#define SC_RA_RAM_CO_CAL_OFF_Q4_8K__A 0x820059
908#define SC_RA_RAM_CO_CAL_OFF_Q4_8K__W 16
909#define SC_RA_RAM_CO_CAL_OFF_Q4_8K__M 0xFFFF
910#define SC_RA_RAM_CO_CAL_OFF_Q4_8K__PRE 0xFFDB
911#define SC_RA_RAM_CO_CAL_OFF_Q16_8K__A 0x82005A
912#define SC_RA_RAM_CO_CAL_OFF_Q16_8K__W 16
913#define SC_RA_RAM_CO_CAL_OFF_Q16_8K__M 0xFFFF
914#define SC_RA_RAM_CO_CAL_OFF_Q16_8K__PRE 0xFFEB
915#define SC_RA_RAM_CO_CAL_OFF_Q64_8K__A 0x82005B
916#define SC_RA_RAM_CO_CAL_OFF_Q64_8K__W 16
917#define SC_RA_RAM_CO_CAL_OFF_Q64_8K__M 0xFFFF
918#define SC_RA_RAM_CO_CAL_OFF_Q64_8K__PRE 0xFFFB
919#define SC_RA_RAM_CO_CAL_OFF_Q4_2K__A 0x82005C
920#define SC_RA_RAM_CO_CAL_OFF_Q4_2K__W 16
921#define SC_RA_RAM_CO_CAL_OFF_Q4_2K__M 0xFFFF
922#define SC_RA_RAM_CO_CAL_OFF_Q4_2K__PRE 0xFFDD
923#define SC_RA_RAM_CO_CAL_OFF_Q16_2K__A 0x82005D
924#define SC_RA_RAM_CO_CAL_OFF_Q16_2K__W 16
925#define SC_RA_RAM_CO_CAL_OFF_Q16_2K__M 0xFFFF
926#define SC_RA_RAM_CO_CAL_OFF_Q16_2K__PRE 0xFFED
927#define SC_RA_RAM_CO_CAL_OFF_Q64_2K__A 0x82005E
928#define SC_RA_RAM_CO_CAL_OFF_Q64_2K__W 16
929#define SC_RA_RAM_CO_CAL_OFF_Q64_2K__M 0xFFFF
930#define SC_RA_RAM_CO_CAL_OFF_Q64_2K__PRE 0xFFFD
931#define SC_RA_RAM_MOTION_OFFSET__A 0x82005F
932#define SC_RA_RAM_MOTION_OFFSET__W 16
933#define SC_RA_RAM_MOTION_OFFSET__M 0xFFFF
934#define SC_RA_RAM_MOTION_OFFSET__PRE 0x2
935#define SC_RA_RAM_STATE_PROC_STOP__AX 0x820060
936#define SC_RA_RAM_STATE_PROC_STOP__XSZ 12
937#define SC_RA_RAM_STATE_PROC_STOP__W 16
938#define SC_RA_RAM_STATE_PROC_STOP__M 0xFFFF
939#define SC_RA_RAM_STATE_PROC_STOP_1__PRE 0xFFFE
940#define SC_RA_RAM_STATE_PROC_STOP_2__PRE 0x0
941#define SC_RA_RAM_STATE_PROC_STOP_3__PRE 0x4
942#define SC_RA_RAM_STATE_PROC_STOP_4__PRE 0x0
943#define SC_RA_RAM_STATE_PROC_STOP_5__PRE 0x0
944#define SC_RA_RAM_STATE_PROC_STOP_6__PRE 0x0
945#define SC_RA_RAM_STATE_PROC_STOP_7__PRE 0x0
946#define SC_RA_RAM_STATE_PROC_STOP_8__PRE 0x0
947#define SC_RA_RAM_STATE_PROC_STOP_9__PRE 0x0
948#define SC_RA_RAM_STATE_PROC_STOP_10__PRE 0x0
949#define SC_RA_RAM_STATE_PROC_STOP_11__PRE 0xFFFE
950#define SC_RA_RAM_STATE_PROC_STOP_12__PRE 0xFFFE
951#define SC_RA_RAM_STATE_PROC_START__AX 0x820070
952#define SC_RA_RAM_STATE_PROC_START__XSZ 12
953#define SC_RA_RAM_STATE_PROC_START__W 16
954#define SC_RA_RAM_STATE_PROC_START__M 0xFFFF
955#define SC_RA_RAM_STATE_PROC_START_1__PRE 0x80
956#define SC_RA_RAM_STATE_PROC_START_2__PRE 0x2
957#define SC_RA_RAM_STATE_PROC_START_3__PRE 0x4
958#define SC_RA_RAM_STATE_PROC_START_4__PRE 0x4
959#define SC_RA_RAM_STATE_PROC_START_5__PRE 0x4
960#define SC_RA_RAM_STATE_PROC_START_6__PRE 0x0
961#define SC_RA_RAM_STATE_PROC_START_7__PRE 0x10
962#define SC_RA_RAM_STATE_PROC_START_8__PRE 0x0
963#define SC_RA_RAM_STATE_PROC_START_9__PRE 0x0
964#define SC_RA_RAM_STATE_PROC_START_10__PRE 0x30
965#define SC_RA_RAM_STATE_PROC_START_11__PRE 0x0
966#define SC_RA_RAM_STATE_PROC_START_12__PRE 0x0
967#define SC_RA_RAM_IF_SAVE__AX 0x82008E
968#define SC_RA_RAM_IF_SAVE__XSZ 2
969#define SC_RA_RAM_IF_SAVE__W 16
970#define SC_RA_RAM_IF_SAVE__M 0xFFFF
971#define SC_RA_RAM_FR_THRES__A 0x82007D
972#define SC_RA_RAM_FR_THRES__W 16
973#define SC_RA_RAM_FR_THRES__M 0xFFFF
974#define SC_RA_RAM_FR_THRES__PRE 0x1A2C
975#define SC_RA_RAM_STATUS__A 0x82007E
976#define SC_RA_RAM_STATUS__W 16
977#define SC_RA_RAM_STATUS__M 0xFFFF
978#define SC_RA_RAM_NF_BORDER_INIT__A 0x82007F
979#define SC_RA_RAM_NF_BORDER_INIT__W 16
980#define SC_RA_RAM_NF_BORDER_INIT__M 0xFFFF
981#define SC_RA_RAM_NF_BORDER_INIT__PRE 0x500
982#define SC_RA_RAM_TIMER__A 0x820080
983#define SC_RA_RAM_TIMER__W 16
984#define SC_RA_RAM_TIMER__M 0xFFFF
985#define SC_RA_RAM_FI_OFFSET__A 0x820081
986#define SC_RA_RAM_FI_OFFSET__W 16
987#define SC_RA_RAM_FI_OFFSET__M 0xFFFF
988#define SC_RA_RAM_FI_OFFSET__PRE 0x382
989#define SC_RA_RAM_ECHO_GUARD__A 0x820082
990#define SC_RA_RAM_ECHO_GUARD__W 16
991#define SC_RA_RAM_ECHO_GUARD__M 0xFFFF
992#define SC_RA_RAM_ECHO_GUARD__PRE 0x18
993
994
995
996#define SC_RA_RAM_IR_FREQ__A 0x8200D0
997#define SC_RA_RAM_IR_FREQ__W 16
998#define SC_RA_RAM_IR_FREQ__M 0xFFFF
999#define SC_RA_RAM_IR_FREQ__PRE 0x0
1000
1001
1002
1003
1004
1005#define SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1
1006#define SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16
1007#define SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF
1008#define SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9
1009#define SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2
1010#define SC_RA_RAM_IR_COARSE_2K_FREQINC__W 16
1011#define SC_RA_RAM_IR_COARSE_2K_FREQINC__M 0xFFFF
1012#define SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4
1013#define SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3
1014#define SC_RA_RAM_IR_COARSE_2K_KAISINC__W 16
1015#define SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF
1016#define SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100
1017
1018
1019
1020#define SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4
1021#define SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16
1022#define SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF
1023#define SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8
1024#define SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5
1025#define SC_RA_RAM_IR_COARSE_8K_FREQINC__W 16
1026#define SC_RA_RAM_IR_COARSE_8K_FREQINC__M 0xFFFF
1027#define SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8
1028#define SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6
1029#define SC_RA_RAM_IR_COARSE_8K_KAISINC__W 16
1030#define SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF
1031#define SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200
1032
1033
1034
1035
1036
1037#define SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7
1038#define SC_RA_RAM_IR_FINE_2K_LENGTH__W 16
1039#define SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF
1040#define SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9
1041#define SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8
1042#define SC_RA_RAM_IR_FINE_2K_FREQINC__W 16
1043#define SC_RA_RAM_IR_FINE_2K_FREQINC__M 0xFFFF
1044#define SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4
1045#define SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9
1046#define SC_RA_RAM_IR_FINE_2K_KAISINC__W 16
1047#define SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF
1048#define SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100
1049
1050
1051
1052#define SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA
1053#define SC_RA_RAM_IR_FINE_8K_LENGTH__W 16
1054#define SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF
1055#define SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB
1056#define SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB
1057#define SC_RA_RAM_IR_FINE_8K_FREQINC__W 16
1058#define SC_RA_RAM_IR_FINE_8K_FREQINC__M 0xFFFF
1059#define SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1
1060#define SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC
1061#define SC_RA_RAM_IR_FINE_8K_KAISINC__W 16
1062#define SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF
1063#define SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40
1064
1065
1066
1067#define SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD
1068#define SC_RA_RAM_ECHO_SHIFT_LIM__W 16
1069#define SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF
1070#define SC_RA_RAM_ECHO_SHIFT_LIM__PRE 0xFFFF
1071#define SC_RA_RAM_ECHO_AGE__A 0x8200DE
1072#define SC_RA_RAM_ECHO_AGE__W 16
1073#define SC_RA_RAM_ECHO_AGE__M 0xFFFF
1074#define SC_RA_RAM_ECHO_AGE__PRE 0xFFFF
1075#define SC_RA_RAM_ECHO_FILTER__A 0x8200DF
1076#define SC_RA_RAM_ECHO_FILTER__W 16
1077#define SC_RA_RAM_ECHO_FILTER__M 0xFFFF
1078#define SC_RA_RAM_ECHO_FILTER__PRE 0x2
1079
1080
1081
1082
1083
1084#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x8200E0
1085#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16
1086#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF
1087#define SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7
1088#define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x8200E1
1089#define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16
1090#define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF
1091#define SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1
1092#define SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x8200E2
1093#define SC_RA_RAM_NI_INIT_2K_POS_LR__W 16
1094#define SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF
1095#define SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8
1096
1097
1098
1099#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x8200E3
1100#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16
1101#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF
1102#define SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE
1103#define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x8200E4
1104#define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16
1105#define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF
1106#define SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7
1107#define SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x8200E5
1108#define SC_RA_RAM_NI_INIT_8K_POS_LR__W 16
1109#define SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF
1110#define SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0
1111
1112
1113
1114#define SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8
1115#define SC_RA_RAM_SAMPLE_RATE_COUNT__W 16
1116#define SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF
1117#define SC_RA_RAM_SAMPLE_RATE_COUNT__PRE 0x10
1118#define SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9
1119#define SC_RA_RAM_SAMPLE_RATE_STEP__W 16
1120#define SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF
1121#define SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x113
1122
1123
1124
1125#define SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x8200EA
1126#define SC_RA_RAM_TPS_TIMEOUT_LIM__W 16
1127#define SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF
1128#define SC_RA_RAM_TPS_TIMEOUT_LIM__PRE 0xC8
1129#define SC_RA_RAM_TPS_TIMEOUT__A 0x8200EB
1130#define SC_RA_RAM_TPS_TIMEOUT__W 16
1131#define SC_RA_RAM_TPS_TIMEOUT__M 0xFFFF
1132#define SC_RA_RAM_BAND__A 0x8200EC
1133#define SC_RA_RAM_BAND__W 16
1134#define SC_RA_RAM_BAND__M 0xFFFF
1135#define SC_RA_RAM_BAND__PRE 0x0
1136#define SC_RA_RAM_BAND_INTERVAL__B 0
1137#define SC_RA_RAM_BAND_INTERVAL__W 4
1138#define SC_RA_RAM_BAND_INTERVAL__M 0xF
1139#define SC_RA_RAM_BAND_INTERVAL_ENABLE_32__B 8
1140#define SC_RA_RAM_BAND_INTERVAL_ENABLE_32__W 1
1141#define SC_RA_RAM_BAND_INTERVAL_ENABLE_32__M 0x100
1142#define SC_RA_RAM_BAND_INTERVAL_ENABLE_16__B 9
1143#define SC_RA_RAM_BAND_INTERVAL_ENABLE_16__W 1
1144#define SC_RA_RAM_BAND_INTERVAL_ENABLE_16__M 0x200
1145#define SC_RA_RAM_BAND_INTERVAL_ENABLE_8__B 10
1146#define SC_RA_RAM_BAND_INTERVAL_ENABLE_8__W 1
1147#define SC_RA_RAM_BAND_INTERVAL_ENABLE_8__M 0x400
1148#define SC_RA_RAM_BAND_INTERVAL_ENABLE_4__B 11
1149#define SC_RA_RAM_BAND_INTERVAL_ENABLE_4__W 1
1150#define SC_RA_RAM_BAND_INTERVAL_ENABLE_4__M 0x800
1151#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__B 12
1152#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__W 1
1153#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__M 0x1000
1154#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__B 13
1155#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__W 1
1156#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__M 0x2000
1157#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__B 14
1158#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__W 1
1159#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__M 0x4000
1160#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__B 15
1161#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__W 1
1162#define SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__M 0x8000
1163
1164#define SC_RA_RAM_EC_OC_CRA_HIP_INIT__A 0x8200ED
1165#define SC_RA_RAM_EC_OC_CRA_HIP_INIT__W 16
1166#define SC_RA_RAM_EC_OC_CRA_HIP_INIT__M 0xFFFF
1167#define SC_RA_RAM_EC_OC_CRA_HIP_INIT__PRE 0xC0
1168#define SC_RA_RAM_REG__AX 0x8200F0
1169#define SC_RA_RAM_REG__XSZ 2
1170#define SC_RA_RAM_REG__W 16
1171#define SC_RA_RAM_REG__M 0xFFFF
1172#define SC_RA_RAM_BREAK__A 0x8200F2
1173#define SC_RA_RAM_BREAK__W 16
1174#define SC_RA_RAM_BREAK__M 0xFFFF
1175#define SC_RA_RAM_BOOTCOUNT__A 0x8200F3
1176#define SC_RA_RAM_BOOTCOUNT__W 16
1177#define SC_RA_RAM_BOOTCOUNT__M 0xFFFF
1178
1179
1180
1181#define SC_RA_RAM_LC_ABS_2K__A 0x8200F4
1182#define SC_RA_RAM_LC_ABS_2K__W 16
1183#define SC_RA_RAM_LC_ABS_2K__M 0xFFFF
1184#define SC_RA_RAM_LC_ABS_2K__PRE 0x1F
1185#define SC_RA_RAM_LC_ABS_8K__A 0x8200F5
1186#define SC_RA_RAM_LC_ABS_8K__W 16
1187#define SC_RA_RAM_LC_ABS_8K__M 0xFFFF
1188#define SC_RA_RAM_LC_ABS_8K__PRE 0x1F
1189
1190
1191
1192
1193
1194#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__A 0x8200F6
1195#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__W 16
1196#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__M 0xFFFF
1197#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_2K__PRE 0x1
1198#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__A 0x8200F7
1199#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__W 16
1200#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__M 0xFFFF
1201#define SC_RA_RAM_NE_ERR_SELECT_FR_OFF_8K__PRE 0x0
1202
1203
1204
1205#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__A 0x8200F8
1206#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__W 16
1207#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__M 0xFFFF
1208#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_2K__PRE 0x3
1209#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__A 0x8200F9
1210#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__W 16
1211#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__M 0xFFFF
1212#define SC_RA_RAM_NE_ERR_SELECT_FR_ON_8K__PRE 0x2
1213#define SC_RA_RAM_RELOCK__A 0x8200FE
1214#define SC_RA_RAM_RELOCK__W 16
1215#define SC_RA_RAM_RELOCK__M 0xFFFF
1216#define SC_RA_RAM_STACKUNDERFLOW__A 0x8200FF
1217#define SC_RA_RAM_STACKUNDERFLOW__W 16
1218#define SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF
1219
1220
1221
1222#define SC_RA_RAM_NF_MAXECHOTOKEN__A 0x820148
1223#define SC_RA_RAM_NF_MAXECHOTOKEN__W 16
1224#define SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF
1225#define SC_RA_RAM_NF_PREPOST__A 0x820149
1226#define SC_RA_RAM_NF_PREPOST__W 16
1227#define SC_RA_RAM_NF_PREPOST__M 0xFFFF
1228#define SC_RA_RAM_NF_PREBORDER__A 0x82014A
1229#define SC_RA_RAM_NF_PREBORDER__W 16
1230#define SC_RA_RAM_NF_PREBORDER__M 0xFFFF
1231#define SC_RA_RAM_NF_START__A 0x82014B
1232#define SC_RA_RAM_NF_START__W 16
1233#define SC_RA_RAM_NF_START__M 0xFFFF
1234#define SC_RA_RAM_NF_MINISI__AX 0x82014C
1235#define SC_RA_RAM_NF_MINISI__XSZ 2
1236#define SC_RA_RAM_NF_MINISI__W 16
1237#define SC_RA_RAM_NF_MINISI__M 0xFFFF
1238#define SC_RA_RAM_NF_MAXECHO__A 0x82014E
1239#define SC_RA_RAM_NF_MAXECHO__W 16
1240#define SC_RA_RAM_NF_MAXECHO__M 0xFFFF
1241#define SC_RA_RAM_NF_NRECHOES__A 0x82014F
1242#define SC_RA_RAM_NF_NRECHOES__W 16
1243#define SC_RA_RAM_NF_NRECHOES__M 0xFFFF
1244#define SC_RA_RAM_NF_ECHOTABLE__AX 0x820150
1245#define SC_RA_RAM_NF_ECHOTABLE__XSZ 16
1246#define SC_RA_RAM_NF_ECHOTABLE__W 16
1247#define SC_RA_RAM_NF_ECHOTABLE__M 0xFFFF
1248
1249
1250
1251
1252
1253#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x8201A0
1254#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16
1255#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF
1256#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x1D6
1257#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__A 0x8201A1
1258#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__W 16
1259#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF
1260#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4
1261
1262
1263
1264#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x8201A2
1265#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16
1266#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF
1267#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1BB
1268#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A 0x8201A3
1269#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W 16
1270#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF
1271#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x5
1272
1273
1274
1275#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x8201A4
1276#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16
1277#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF
1278#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x1EF
1279#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__A 0x8201A5
1280#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__W 16
1281#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF
1282#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5
1283
1284
1285
1286#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x8201A6
1287#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16
1288#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF
1289#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x15E
1290#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__A 0x8201A7
1291#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__W 16
1292#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF
1293#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x5
1294
1295
1296
1297#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x8201A8
1298#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16
1299#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF
1300#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x11A
1301#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__A 0x8201A9
1302#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__W 16
1303#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF
1304#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x6
1305
1306
1307
1308#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x8201AA
1309#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16
1310#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF
1311#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x1FB
1312#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__A 0x8201AB
1313#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__W 16
1314#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF
1315#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5
1316
1317
1318
1319#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x8201AC
1320#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16
1321#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF
1322#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x12F
1323#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__A 0x8201AD
1324#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__W 16
1325#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF
1326#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x5
1327
1328
1329
1330#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x8201AE
1331#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16
1332#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF
1333#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x197
1334#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__A 0x8201AF
1335#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__W 16
1336#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__M 0xFFFF
1337#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x5
1338#define SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE
1339#define SC_RA_RAM_DRIVER_VERSION__XSZ 2
1340#define SC_RA_RAM_DRIVER_VERSION__W 16
1341#define SC_RA_RAM_DRIVER_VERSION__M 0xFFFF
1342#define SC_RA_RAM_EVENT0_MIN 0x7
1343#define SC_RA_RAM_EVENT0_FE_CU 0x7
1344#define SC_RA_RAM_EVENT0_CE 0xA
1345#define SC_RA_RAM_EVENT0_EQ 0xE
1346#define SC_RA_RAM_EVENT0_MAX 0xF
1347#define SC_RA_RAM_EVENT1_MIN 0x8
1348#define SC_RA_RAM_EVENT1_EC_OD 0x8
1349#define SC_RA_RAM_EVENT1_LC 0xC
1350#define SC_RA_RAM_EVENT1_MAX 0xD
1351#define SC_RA_RAM_PROC_LOCKTRACK 0x0
1352#define SC_RA_RAM_PROC_MODE_GUARD 0x1
1353#define SC_RA_RAM_PROC_PILOTS 0x2
1354#define SC_RA_RAM_PROC_FESTART_ADJUST 0x3
1355#define SC_RA_RAM_PROC_ECHO 0x4
1356#define SC_RA_RAM_PROC_BE_OPT 0x5
1357#define SC_RA_RAM_PROC_EQ 0x7
1358#define SC_RA_RAM_PROC_MAX 0x8
1359
1360
1361
1362
1363
1364
1365#define SC_IF_RAM_TRP_RST__AX 0x830000
1366#define SC_IF_RAM_TRP_RST__XSZ 2
1367#define SC_IF_RAM_TRP_RST__W 12
1368#define SC_IF_RAM_TRP_RST__M 0xFFF
1369
1370#define SC_IF_RAM_TRP_BPT0__AX 0x830002
1371#define SC_IF_RAM_TRP_BPT0__XSZ 2
1372#define SC_IF_RAM_TRP_BPT0__W 12
1373#define SC_IF_RAM_TRP_BPT0__M 0xFFF
1374
1375#define SC_IF_RAM_TRP_STKU__AX 0x830004
1376#define SC_IF_RAM_TRP_STKU__XSZ 2
1377#define SC_IF_RAM_TRP_STKU__W 12
1378#define SC_IF_RAM_TRP_STKU__M 0xFFF
1379
1380
1381
1382
1383#define SC_IF_RAM_VERSION_MA_MI__A 0x830FFE
1384#define SC_IF_RAM_VERSION_MA_MI__W 12
1385#define SC_IF_RAM_VERSION_MA_MI__M 0xFFF
1386
1387#define SC_IF_RAM_VERSION_PATCH__A 0x830FFF
1388#define SC_IF_RAM_VERSION_PATCH__W 12
1389#define SC_IF_RAM_VERSION_PATCH__M 0xFFF
1390
1391
1392
1393
1394
1395
1396
1397
1398
1399#define FE_COMM_EXEC__A 0xC00000
1400#define FE_COMM_EXEC__W 3
1401#define FE_COMM_EXEC__M 0x7
1402#define FE_COMM_EXEC_CTL__B 0
1403#define FE_COMM_EXEC_CTL__W 3
1404#define FE_COMM_EXEC_CTL__M 0x7
1405#define FE_COMM_EXEC_CTL_STOP 0x0
1406#define FE_COMM_EXEC_CTL_ACTIVE 0x1
1407#define FE_COMM_EXEC_CTL_HOLD 0x2
1408#define FE_COMM_EXEC_CTL_STEP 0x3
1409#define FE_COMM_EXEC_CTL_BYPASS_STOP 0x4
1410#define FE_COMM_EXEC_CTL_BYPASS_HOLD 0x6
1411
1412#define FE_COMM_STATE__A 0xC00001
1413#define FE_COMM_STATE__W 16
1414#define FE_COMM_STATE__M 0xFFFF
1415#define FE_COMM_MB__A 0xC00002
1416#define FE_COMM_MB__W 16
1417#define FE_COMM_MB__M 0xFFFF
1418#define FE_COMM_SERVICE0__A 0xC00003
1419#define FE_COMM_SERVICE0__W 16
1420#define FE_COMM_SERVICE0__M 0xFFFF
1421#define FE_COMM_SERVICE1__A 0xC00004
1422#define FE_COMM_SERVICE1__W 16
1423#define FE_COMM_SERVICE1__M 0xFFFF
1424#define FE_COMM_INT_STA__A 0xC00007
1425#define FE_COMM_INT_STA__W 16
1426#define FE_COMM_INT_STA__M 0xFFFF
1427#define FE_COMM_INT_MSK__A 0xC00008
1428#define FE_COMM_INT_MSK__W 16
1429#define FE_COMM_INT_MSK__M 0xFFFF
1430
1431
1432
1433
1434
1435#define FE_AD_SID 0x1
1436
1437
1438
1439
1440
1441
1442#define FE_AD_REG_COMM_EXEC__A 0xC10000
1443#define FE_AD_REG_COMM_EXEC__W 3
1444#define FE_AD_REG_COMM_EXEC__M 0x7
1445#define FE_AD_REG_COMM_EXEC_CTL__B 0
1446#define FE_AD_REG_COMM_EXEC_CTL__W 3
1447#define FE_AD_REG_COMM_EXEC_CTL__M 0x7
1448#define FE_AD_REG_COMM_EXEC_CTL_STOP 0x0
1449#define FE_AD_REG_COMM_EXEC_CTL_ACTIVE 0x1
1450#define FE_AD_REG_COMM_EXEC_CTL_HOLD 0x2
1451#define FE_AD_REG_COMM_EXEC_CTL_STEP 0x3
1452
1453
1454#define FE_AD_REG_COMM_MB__A 0xC10002
1455#define FE_AD_REG_COMM_MB__W 2
1456#define FE_AD_REG_COMM_MB__M 0x3
1457#define FE_AD_REG_COMM_MB_CTR__B 0
1458#define FE_AD_REG_COMM_MB_CTR__W 1
1459#define FE_AD_REG_COMM_MB_CTR__M 0x1
1460#define FE_AD_REG_COMM_MB_CTR_OFF 0x0
1461#define FE_AD_REG_COMM_MB_CTR_ON 0x1
1462#define FE_AD_REG_COMM_MB_OBS__B 1
1463#define FE_AD_REG_COMM_MB_OBS__W 1
1464#define FE_AD_REG_COMM_MB_OBS__M 0x2
1465#define FE_AD_REG_COMM_MB_OBS_OFF 0x0
1466#define FE_AD_REG_COMM_MB_OBS_ON 0x2
1467
1468#define FE_AD_REG_COMM_SERVICE0__A 0xC10003
1469#define FE_AD_REG_COMM_SERVICE0__W 10
1470#define FE_AD_REG_COMM_SERVICE0__M 0x3FF
1471#define FE_AD_REG_COMM_SERVICE0_FE_AD__B 0
1472#define FE_AD_REG_COMM_SERVICE0_FE_AD__W 1
1473#define FE_AD_REG_COMM_SERVICE0_FE_AD__M 0x1
1474
1475#define FE_AD_REG_COMM_SERVICE1__A 0xC10004
1476#define FE_AD_REG_COMM_SERVICE1__W 11
1477#define FE_AD_REG_COMM_SERVICE1__M 0x7FF
1478
1479#define FE_AD_REG_COMM_INT_STA__A 0xC10007
1480#define FE_AD_REG_COMM_INT_STA__W 2
1481#define FE_AD_REG_COMM_INT_STA__M 0x3
1482#define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__B 0
1483#define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__W 1
1484#define FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__M 0x1
1485
1486
1487#define FE_AD_REG_COMM_INT_MSK__A 0xC10008
1488#define FE_AD_REG_COMM_INT_MSK__W 2
1489#define FE_AD_REG_COMM_INT_MSK__M 0x3
1490#define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__B 0
1491#define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__W 1
1492#define FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__M 0x1
1493
1494
1495#define FE_AD_REG_CUR_SEL__A 0xC10010
1496#define FE_AD_REG_CUR_SEL__W 2
1497#define FE_AD_REG_CUR_SEL__M 0x3
1498#define FE_AD_REG_CUR_SEL_INIT 0x2
1499
1500
1501#define FE_AD_REG_OVERFLOW__A 0xC10011
1502#define FE_AD_REG_OVERFLOW__W 1
1503#define FE_AD_REG_OVERFLOW__M 0x1
1504#define FE_AD_REG_OVERFLOW_INIT 0x0
1505
1506
1507#define FE_AD_REG_FDB_IN__A 0xC10012
1508#define FE_AD_REG_FDB_IN__W 1
1509#define FE_AD_REG_FDB_IN__M 0x1
1510#define FE_AD_REG_FDB_IN_INIT 0x0
1511
1512
1513#define FE_AD_REG_PD__A 0xC10013
1514#define FE_AD_REG_PD__W 1
1515#define FE_AD_REG_PD__M 0x1
1516#define FE_AD_REG_PD_INIT 0x1
1517
1518
1519#define FE_AD_REG_INVEXT__A 0xC10014
1520#define FE_AD_REG_INVEXT__W 1
1521#define FE_AD_REG_INVEXT__M 0x1
1522#define FE_AD_REG_INVEXT_INIT 0x0
1523
1524
1525#define FE_AD_REG_CLKNEG__A 0xC10015
1526#define FE_AD_REG_CLKNEG__W 1
1527#define FE_AD_REG_CLKNEG__M 0x1
1528#define FE_AD_REG_CLKNEG_INIT 0x0
1529
1530
1531#define FE_AD_REG_MON_IN_MUX__A 0xC10016
1532#define FE_AD_REG_MON_IN_MUX__W 2
1533#define FE_AD_REG_MON_IN_MUX__M 0x3
1534#define FE_AD_REG_MON_IN_MUX_INIT 0x0
1535
1536
1537#define FE_AD_REG_MON_IN5__A 0xC10017
1538#define FE_AD_REG_MON_IN5__W 10
1539#define FE_AD_REG_MON_IN5__M 0x3FF
1540#define FE_AD_REG_MON_IN5_INIT 0x0
1541
1542
1543#define FE_AD_REG_MON_IN4__A 0xC10018
1544#define FE_AD_REG_MON_IN4__W 10
1545#define FE_AD_REG_MON_IN4__M 0x3FF
1546#define FE_AD_REG_MON_IN4_INIT 0x0
1547
1548
1549#define FE_AD_REG_MON_IN3__A 0xC10019
1550#define FE_AD_REG_MON_IN3__W 10
1551#define FE_AD_REG_MON_IN3__M 0x3FF
1552#define FE_AD_REG_MON_IN3_INIT 0x0
1553
1554
1555#define FE_AD_REG_MON_IN2__A 0xC1001A
1556#define FE_AD_REG_MON_IN2__W 10
1557#define FE_AD_REG_MON_IN2__M 0x3FF
1558#define FE_AD_REG_MON_IN2_INIT 0x0
1559
1560
1561#define FE_AD_REG_MON_IN1__A 0xC1001B
1562#define FE_AD_REG_MON_IN1__W 10
1563#define FE_AD_REG_MON_IN1__M 0x3FF
1564#define FE_AD_REG_MON_IN1_INIT 0x0
1565
1566
1567#define FE_AD_REG_MON_IN0__A 0xC1001C
1568#define FE_AD_REG_MON_IN0__W 10
1569#define FE_AD_REG_MON_IN0__M 0x3FF
1570#define FE_AD_REG_MON_IN0_INIT 0x0
1571
1572
1573#define FE_AD_REG_MON_IN_VAL__A 0xC1001D
1574#define FE_AD_REG_MON_IN_VAL__W 1
1575#define FE_AD_REG_MON_IN_VAL__M 0x1
1576#define FE_AD_REG_MON_IN_VAL_INIT 0x0
1577
1578
1579#define FE_AD_REG_CTR_CLK_O__A 0xC1001E
1580#define FE_AD_REG_CTR_CLK_O__W 1
1581#define FE_AD_REG_CTR_CLK_O__M 0x1
1582#define FE_AD_REG_CTR_CLK_O_INIT 0x0
1583
1584
1585#define FE_AD_REG_CTR_CLK_E_O__A 0xC1001F
1586#define FE_AD_REG_CTR_CLK_E_O__W 1
1587#define FE_AD_REG_CTR_CLK_E_O__M 0x1
1588#define FE_AD_REG_CTR_CLK_E_O_INIT 0x1
1589
1590
1591#define FE_AD_REG_CTR_VAL_O__A 0xC10020
1592#define FE_AD_REG_CTR_VAL_O__W 1
1593#define FE_AD_REG_CTR_VAL_O__M 0x1
1594#define FE_AD_REG_CTR_VAL_O_INIT 0x0
1595
1596
1597#define FE_AD_REG_CTR_VAL_E_O__A 0xC10021
1598#define FE_AD_REG_CTR_VAL_E_O__W 1
1599#define FE_AD_REG_CTR_VAL_E_O__M 0x1
1600#define FE_AD_REG_CTR_VAL_E_O_INIT 0x1
1601
1602
1603#define FE_AD_REG_CTR_DATA_O__A 0xC10022
1604#define FE_AD_REG_CTR_DATA_O__W 10
1605#define FE_AD_REG_CTR_DATA_O__M 0x3FF
1606#define FE_AD_REG_CTR_DATA_O_INIT 0x0
1607
1608
1609#define FE_AD_REG_CTR_DATA_E_O__A 0xC10023
1610#define FE_AD_REG_CTR_DATA_E_O__W 10
1611#define FE_AD_REG_CTR_DATA_E_O__M 0x3FF
1612#define FE_AD_REG_CTR_DATA_E_O_INIT 0x3FF
1613
1614
1615
1616
1617
1618#define FE_AG_SID 0x2
1619
1620
1621
1622
1623
1624
1625#define FE_AG_REG_COMM_EXEC__A 0xC20000
1626#define FE_AG_REG_COMM_EXEC__W 3
1627#define FE_AG_REG_COMM_EXEC__M 0x7
1628#define FE_AG_REG_COMM_EXEC_CTL__B 0
1629#define FE_AG_REG_COMM_EXEC_CTL__W 3
1630#define FE_AG_REG_COMM_EXEC_CTL__M 0x7
1631#define FE_AG_REG_COMM_EXEC_CTL_STOP 0x0
1632#define FE_AG_REG_COMM_EXEC_CTL_ACTIVE 0x1
1633#define FE_AG_REG_COMM_EXEC_CTL_HOLD 0x2
1634#define FE_AG_REG_COMM_EXEC_CTL_STEP 0x3
1635
1636#define FE_AG_REG_COMM_STATE__A 0xC20001
1637#define FE_AG_REG_COMM_STATE__W 4
1638#define FE_AG_REG_COMM_STATE__M 0xF
1639
1640#define FE_AG_REG_COMM_MB__A 0xC20002
1641#define FE_AG_REG_COMM_MB__W 2
1642#define FE_AG_REG_COMM_MB__M 0x3
1643#define FE_AG_REG_COMM_MB_CTR__B 0
1644#define FE_AG_REG_COMM_MB_CTR__W 1
1645#define FE_AG_REG_COMM_MB_CTR__M 0x1
1646#define FE_AG_REG_COMM_MB_CTR_OFF 0x0
1647#define FE_AG_REG_COMM_MB_CTR_ON 0x1
1648#define FE_AG_REG_COMM_MB_OBS__B 1
1649#define FE_AG_REG_COMM_MB_OBS__W 1
1650#define FE_AG_REG_COMM_MB_OBS__M 0x2
1651#define FE_AG_REG_COMM_MB_OBS_OFF 0x0
1652#define FE_AG_REG_COMM_MB_OBS_ON 0x2
1653
1654
1655#define FE_AG_REG_COMM_SERVICE0__A 0xC20003
1656#define FE_AG_REG_COMM_SERVICE0__W 10
1657#define FE_AG_REG_COMM_SERVICE0__M 0x3FF
1658
1659#define FE_AG_REG_COMM_SERVICE1__A 0xC20004
1660#define FE_AG_REG_COMM_SERVICE1__W 11
1661#define FE_AG_REG_COMM_SERVICE1__M 0x7FF
1662
1663#define FE_AG_REG_COMM_INT_STA__A 0xC20007
1664#define FE_AG_REG_COMM_INT_STA__W 8
1665#define FE_AG_REG_COMM_INT_STA__M 0xFF
1666#define FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__B 0
1667#define FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__W 1
1668#define FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__M 0x1
1669#define FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__B 1
1670#define FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__W 1
1671#define FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__M 0x2
1672#define FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__B 2
1673#define FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__W 1
1674#define FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__M 0x4
1675#define FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__B 3
1676#define FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__W 1
1677#define FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__M 0x8
1678#define FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__B 4
1679#define FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__W 1
1680#define FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__M 0x10
1681#define FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__B 5
1682#define FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__W 1
1683#define FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__M 0x20
1684#define FE_AG_REG_COMM_INT_STA_FGA_AVE_UPD__B 6
1685#define FE_AG_REG_COMM_INT_STA_FGA_AVE_UPD__W 1
1686#define FE_AG_REG_COMM_INT_STA_FGA_AVE_UPD__M 0x40
1687#define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__B 7
1688#define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__W 1
1689#define FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__M 0x80
1690
1691
1692#define FE_AG_REG_COMM_INT_MSK__A 0xC20008
1693#define FE_AG_REG_COMM_INT_MSK__W 8
1694#define FE_AG_REG_COMM_INT_MSK__M 0xFF
1695#define FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__B 0
1696#define FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__W 1
1697#define FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__M 0x1
1698#define FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__B 1
1699#define FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__W 1
1700#define FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__M 0x2
1701#define FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__B 2
1702#define FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__W 1
1703#define FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__M 0x4
1704#define FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__B 3
1705#define FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__W 1
1706#define FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__M 0x8
1707#define FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__B 4
1708#define FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__W 1
1709#define FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__M 0x10
1710#define FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__B 5
1711#define FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__W 1
1712#define FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__M 0x20
1713#define FE_AG_REG_COMM_INT_MSK_FGA_AVE_UPD__B 6
1714#define FE_AG_REG_COMM_INT_MSK_FGA_AVE_UPD__W 1
1715#define FE_AG_REG_COMM_INT_MSK_FGA_AVE_UPD__M 0x40
1716#define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__B 7
1717#define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__W 1
1718#define FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__M 0x80
1719
1720
1721#define FE_AG_REG_AG_MODE_LOP__A 0xC20010
1722#define FE_AG_REG_AG_MODE_LOP__W 16
1723#define FE_AG_REG_AG_MODE_LOP__M 0xFFFF
1724#define FE_AG_REG_AG_MODE_LOP_INIT 0x0
1725
1726#define FE_AG_REG_AG_MODE_LOP_MODE_0__B 0
1727#define FE_AG_REG_AG_MODE_LOP_MODE_0__W 1
1728#define FE_AG_REG_AG_MODE_LOP_MODE_0__M 0x1
1729#define FE_AG_REG_AG_MODE_LOP_MODE_0_ENABLE 0x0
1730#define FE_AG_REG_AG_MODE_LOP_MODE_0_DISABLE 0x1
1731
1732#define FE_AG_REG_AG_MODE_LOP_MODE_1__B 1
1733#define FE_AG_REG_AG_MODE_LOP_MODE_1__W 1
1734#define FE_AG_REG_AG_MODE_LOP_MODE_1__M 0x2
1735#define FE_AG_REG_AG_MODE_LOP_MODE_1_STATIC 0x0
1736#define FE_AG_REG_AG_MODE_LOP_MODE_1_DYNAMIC 0x2
1737
1738#define FE_AG_REG_AG_MODE_LOP_MODE_2__B 2
1739#define FE_AG_REG_AG_MODE_LOP_MODE_2__W 1
1740#define FE_AG_REG_AG_MODE_LOP_MODE_2__M 0x4
1741#define FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_B 0x0
1742#define FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_CB 0x4
1743
1744#define FE_AG_REG_AG_MODE_LOP_MODE_3__B 3
1745#define FE_AG_REG_AG_MODE_LOP_MODE_3__W 1
1746#define FE_AG_REG_AG_MODE_LOP_MODE_3__M 0x8
1747#define FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_B 0x0
1748#define FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_CB 0x8
1749
1750#define FE_AG_REG_AG_MODE_LOP_MODE_4__B 4
1751#define FE_AG_REG_AG_MODE_LOP_MODE_4__W 1
1752#define FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10
1753#define FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0
1754#define FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10
1755
1756#define FE_AG_REG_AG_MODE_LOP_MODE_5__B 5
1757#define FE_AG_REG_AG_MODE_LOP_MODE_5__W 1
1758#define FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20
1759#define FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0
1760#define FE_AG_REG_AG_MODE_LOP_MODE_5_DYNAMIC 0x20
1761
1762#define FE_AG_REG_AG_MODE_LOP_MODE_6__B 6
1763#define FE_AG_REG_AG_MODE_LOP_MODE_6__W 1
1764#define FE_AG_REG_AG_MODE_LOP_MODE_6__M 0x40
1765#define FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_B 0x0
1766#define FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_CB 0x40
1767
1768#define FE_AG_REG_AG_MODE_LOP_MODE_7__B 7
1769#define FE_AG_REG_AG_MODE_LOP_MODE_7__W 1
1770#define FE_AG_REG_AG_MODE_LOP_MODE_7__M 0x80
1771#define FE_AG_REG_AG_MODE_LOP_MODE_7_DYNAMIC 0x0
1772#define FE_AG_REG_AG_MODE_LOP_MODE_7_STATIC 0x80
1773
1774#define FE_AG_REG_AG_MODE_LOP_MODE_8__B 8
1775#define FE_AG_REG_AG_MODE_LOP_MODE_8__W 1
1776#define FE_AG_REG_AG_MODE_LOP_MODE_8__M 0x100
1777#define FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_B 0x0
1778#define FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_CB 0x100
1779
1780#define FE_AG_REG_AG_MODE_LOP_MODE_9__B 9
1781#define FE_AG_REG_AG_MODE_LOP_MODE_9__W 1
1782#define FE_AG_REG_AG_MODE_LOP_MODE_9__M 0x200
1783#define FE_AG_REG_AG_MODE_LOP_MODE_9_STATIC 0x0
1784#define FE_AG_REG_AG_MODE_LOP_MODE_9_DYNAMIC 0x200
1785
1786#define FE_AG_REG_AG_MODE_LOP_MODE_A__B 10
1787#define FE_AG_REG_AG_MODE_LOP_MODE_A__W 1
1788#define FE_AG_REG_AG_MODE_LOP_MODE_A__M 0x400
1789#define FE_AG_REG_AG_MODE_LOP_MODE_A_AVE_B 0x0
1790#define FE_AG_REG_AG_MODE_LOP_MODE_A_AVE_CB 0x400
1791
1792#define FE_AG_REG_AG_MODE_LOP_MODE_B__B 11
1793#define FE_AG_REG_AG_MODE_LOP_MODE_B__W 1
1794#define FE_AG_REG_AG_MODE_LOP_MODE_B__M 0x800
1795#define FE_AG_REG_AG_MODE_LOP_MODE_B_START 0x0
1796#define FE_AG_REG_AG_MODE_LOP_MODE_B_ALWAYS 0x800
1797
1798#define FE_AG_REG_AG_MODE_LOP_MODE_C__B 12
1799#define FE_AG_REG_AG_MODE_LOP_MODE_C__W 1
1800#define FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000
1801#define FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0
1802#define FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000
1803
1804#define FE_AG_REG_AG_MODE_LOP_MODE_D__B 13
1805#define FE_AG_REG_AG_MODE_LOP_MODE_D__W 1
1806#define FE_AG_REG_AG_MODE_LOP_MODE_D__M 0x2000
1807#define FE_AG_REG_AG_MODE_LOP_MODE_D_START 0x0
1808#define FE_AG_REG_AG_MODE_LOP_MODE_D_ALWAYS 0x2000
1809
1810#define FE_AG_REG_AG_MODE_LOP_MODE_E__B 14
1811#define FE_AG_REG_AG_MODE_LOP_MODE_E__W 1
1812#define FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000
1813#define FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0
1814#define FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000
1815
1816#define FE_AG_REG_AG_MODE_LOP_MODE_F__B 15
1817#define FE_AG_REG_AG_MODE_LOP_MODE_F__W 1
1818#define FE_AG_REG_AG_MODE_LOP_MODE_F__M 0x8000
1819#define FE_AG_REG_AG_MODE_LOP_MODE_F_DISABLE 0x0
1820#define FE_AG_REG_AG_MODE_LOP_MODE_F_ENABLE 0x8000
1821
1822
1823#define FE_AG_REG_AG_MODE_HIP__A 0xC20011
1824#define FE_AG_REG_AG_MODE_HIP__W 2
1825#define FE_AG_REG_AG_MODE_HIP__M 0x3
1826#define FE_AG_REG_AG_MODE_HIP_INIT 0x0
1827
1828#define FE_AG_REG_AG_MODE_HIP_MODE_G__B 0
1829#define FE_AG_REG_AG_MODE_HIP_MODE_G__W 1
1830#define FE_AG_REG_AG_MODE_HIP_MODE_G__M 0x1
1831#define FE_AG_REG_AG_MODE_HIP_MODE_G_OUTPUT 0x0
1832#define FE_AG_REG_AG_MODE_HIP_MODE_G_ENABLE 0x1
1833
1834#define FE_AG_REG_AG_MODE_HIP_MODE_H__B 1
1835#define FE_AG_REG_AG_MODE_HIP_MODE_H__W 1
1836#define FE_AG_REG_AG_MODE_HIP_MODE_H__M 0x2
1837#define FE_AG_REG_AG_MODE_HIP_MODE_H_OUTPUT 0x0
1838#define FE_AG_REG_AG_MODE_HIP_MODE_H_ENABLE 0x2
1839
1840
1841#define FE_AG_REG_AG_PGA_MODE__A 0xC20012
1842#define FE_AG_REG_AG_PGA_MODE__W 3
1843#define FE_AG_REG_AG_PGA_MODE__M 0x7
1844#define FE_AG_REG_AG_PGA_MODE_INIT 0x0
1845#define FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0
1846#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1
1847#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REN 0x2
1848#define FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REN 0x3
1849#define FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REY 0x4
1850#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REY 0x5
1851#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REY 0x6
1852#define FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REY 0x7
1853
1854
1855#define FE_AG_REG_AG_AGC_SIO__A 0xC20013
1856#define FE_AG_REG_AG_AGC_SIO__W 2
1857#define FE_AG_REG_AG_AGC_SIO__M 0x3
1858#define FE_AG_REG_AG_AGC_SIO_INIT 0x3
1859
1860#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__B 0
1861#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__W 1
1862#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__M 0x1
1863#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_OUTPUT 0x0
1864#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_INPUT 0x1
1865
1866#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__B 1
1867#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__W 1
1868#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2
1869#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0
1870#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2
1871
1872
1873#define FE_AG_REG_AG_AGC_USR_DAT__A 0xC20014
1874#define FE_AG_REG_AG_AGC_USR_DAT__W 2
1875#define FE_AG_REG_AG_AGC_USR_DAT__M 0x3
1876#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__B 0
1877#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__W 1
1878#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__M 0x1
1879#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__B 1
1880#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__W 1
1881#define FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__M 0x2
1882
1883
1884#define FE_AG_REG_AG_PWD__A 0xC20015
1885#define FE_AG_REG_AG_PWD__W 5
1886#define FE_AG_REG_AG_PWD__M 0x1F
1887#define FE_AG_REG_AG_PWD_INIT 0x1F
1888
1889#define FE_AG_REG_AG_PWD_PWD_PD1__B 0
1890#define FE_AG_REG_AG_PWD_PWD_PD1__W 1
1891#define FE_AG_REG_AG_PWD_PWD_PD1__M 0x1
1892#define FE_AG_REG_AG_PWD_PWD_PD1_DISABLE 0x0
1893#define FE_AG_REG_AG_PWD_PWD_PD1_ENABLE 0x1
1894
1895#define FE_AG_REG_AG_PWD_PWD_PD2__B 1
1896#define FE_AG_REG_AG_PWD_PWD_PD2__W 1
1897#define FE_AG_REG_AG_PWD_PWD_PD2__M 0x2
1898#define FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0
1899#define FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2
1900
1901#define FE_AG_REG_AG_PWD_PWD_PGA_F__B 2
1902#define FE_AG_REG_AG_PWD_PWD_PGA_F__W 1
1903#define FE_AG_REG_AG_PWD_PWD_PGA_F__M 0x4
1904#define FE_AG_REG_AG_PWD_PWD_PGA_F_DISABLE 0x0
1905#define FE_AG_REG_AG_PWD_PWD_PGA_F_ENABLE 0x4
1906
1907#define FE_AG_REG_AG_PWD_PWD_PGA_C__B 3
1908#define FE_AG_REG_AG_PWD_PWD_PGA_C__W 1
1909#define FE_AG_REG_AG_PWD_PWD_PGA_C__M 0x8
1910#define FE_AG_REG_AG_PWD_PWD_PGA_C_DISABLE 0x0
1911#define FE_AG_REG_AG_PWD_PWD_PGA_C_ENABLE 0x8
1912
1913#define FE_AG_REG_AG_PWD_PWD_AAF__B 4
1914#define FE_AG_REG_AG_PWD_PWD_AAF__W 1
1915#define FE_AG_REG_AG_PWD_PWD_AAF__M 0x10
1916#define FE_AG_REG_AG_PWD_PWD_AAF_DISABLE 0x0
1917#define FE_AG_REG_AG_PWD_PWD_AAF_ENABLE 0x10
1918
1919
1920#define FE_AG_REG_DCE_AUR_CNT__A 0xC20016
1921#define FE_AG_REG_DCE_AUR_CNT__W 5
1922#define FE_AG_REG_DCE_AUR_CNT__M 0x1F
1923#define FE_AG_REG_DCE_AUR_CNT_INIT 0x0
1924
1925
1926#define FE_AG_REG_DCE_RUR_CNT__A 0xC20017
1927#define FE_AG_REG_DCE_RUR_CNT__W 5
1928#define FE_AG_REG_DCE_RUR_CNT__M 0x1F
1929#define FE_AG_REG_DCE_RUR_CNT_INIT 0x0
1930
1931
1932#define FE_AG_REG_DCE_AVE_DAT__A 0xC20018
1933#define FE_AG_REG_DCE_AVE_DAT__W 10
1934#define FE_AG_REG_DCE_AVE_DAT__M 0x3FF
1935
1936#define FE_AG_REG_DEC_AVE_WRI__A 0xC20019
1937#define FE_AG_REG_DEC_AVE_WRI__W 10
1938#define FE_AG_REG_DEC_AVE_WRI__M 0x3FF
1939#define FE_AG_REG_DEC_AVE_WRI_INIT 0x0
1940
1941
1942#define FE_AG_REG_ACE_AUR_CNT__A 0xC2001A
1943#define FE_AG_REG_ACE_AUR_CNT__W 5
1944#define FE_AG_REG_ACE_AUR_CNT__M 0x1F
1945#define FE_AG_REG_ACE_AUR_CNT_INIT 0x0
1946
1947
1948#define FE_AG_REG_ACE_RUR_CNT__A 0xC2001B
1949#define FE_AG_REG_ACE_RUR_CNT__W 5
1950#define FE_AG_REG_ACE_RUR_CNT__M 0x1F
1951#define FE_AG_REG_ACE_RUR_CNT_INIT 0x0
1952
1953
1954#define FE_AG_REG_ACE_AVE_DAT__A 0xC2001C
1955#define FE_AG_REG_ACE_AVE_DAT__W 10
1956#define FE_AG_REG_ACE_AVE_DAT__M 0x3FF
1957
1958#define FE_AG_REG_AEC_AVE_INC__A 0xC2001D
1959#define FE_AG_REG_AEC_AVE_INC__W 10
1960#define FE_AG_REG_AEC_AVE_INC__M 0x3FF
1961#define FE_AG_REG_AEC_AVE_INC_INIT 0x0
1962
1963
1964#define FE_AG_REG_AEC_AVE_DAT__A 0xC2001E
1965#define FE_AG_REG_AEC_AVE_DAT__W 10
1966#define FE_AG_REG_AEC_AVE_DAT__M 0x3FF
1967
1968#define FE_AG_REG_AEC_CLP_LVL__A 0xC2001F
1969#define FE_AG_REG_AEC_CLP_LVL__W 16
1970#define FE_AG_REG_AEC_CLP_LVL__M 0xFFFF
1971#define FE_AG_REG_AEC_CLP_LVL_INIT 0x0
1972
1973
1974#define FE_AG_REG_CDR_RUR_CNT__A 0xC20020
1975#define FE_AG_REG_CDR_RUR_CNT__W 5
1976#define FE_AG_REG_CDR_RUR_CNT__M 0x1F
1977#define FE_AG_REG_CDR_RUR_CNT_INIT 0x0
1978
1979
1980#define FE_AG_REG_CDR_CLP_DAT__A 0xC20021
1981#define FE_AG_REG_CDR_CLP_DAT__W 16
1982#define FE_AG_REG_CDR_CLP_DAT__M 0xFFFF
1983
1984#define FE_AG_REG_CDR_CLP_POS__A 0xC20022
1985#define FE_AG_REG_CDR_CLP_POS__W 10
1986#define FE_AG_REG_CDR_CLP_POS__M 0x3FF
1987#define FE_AG_REG_CDR_CLP_POS_INIT 0x0
1988
1989
1990#define FE_AG_REG_CDR_CLP_NEG__A 0xC20023
1991#define FE_AG_REG_CDR_CLP_NEG__W 10
1992#define FE_AG_REG_CDR_CLP_NEG__M 0x3FF
1993#define FE_AG_REG_CDR_CLP_NEG_INIT 0x0
1994
1995
1996#define FE_AG_REG_EGC_RUR_CNT__A 0xC20024
1997#define FE_AG_REG_EGC_RUR_CNT__W 5
1998#define FE_AG_REG_EGC_RUR_CNT__M 0x1F
1999#define FE_AG_REG_EGC_RUR_CNT_INIT 0x0
2000
2001
2002#define FE_AG_REG_EGC_SET_LVL__A 0xC20025
2003#define FE_AG_REG_EGC_SET_LVL__W 9
2004#define FE_AG_REG_EGC_SET_LVL__M 0x1FF
2005#define FE_AG_REG_EGC_SET_LVL_INIT 0x0
2006
2007
2008#define FE_AG_REG_EGC_FLA_RGN__A 0xC20026
2009#define FE_AG_REG_EGC_FLA_RGN__W 9
2010#define FE_AG_REG_EGC_FLA_RGN__M 0x1FF
2011#define FE_AG_REG_EGC_FLA_RGN_INIT 0x0
2012
2013
2014#define FE_AG_REG_EGC_SLO_RGN__A 0xC20027
2015#define FE_AG_REG_EGC_SLO_RGN__W 9
2016#define FE_AG_REG_EGC_SLO_RGN__M 0x1FF
2017#define FE_AG_REG_EGC_SLO_RGN_INIT 0x0
2018
2019
2020#define FE_AG_REG_EGC_JMP_PSN__A 0xC20028
2021#define FE_AG_REG_EGC_JMP_PSN__W 4
2022#define FE_AG_REG_EGC_JMP_PSN__M 0xF
2023#define FE_AG_REG_EGC_JMP_PSN_INIT 0x0
2024
2025
2026#define FE_AG_REG_EGC_FLA_INC__A 0xC20029
2027#define FE_AG_REG_EGC_FLA_INC__W 16
2028#define FE_AG_REG_EGC_FLA_INC__M 0xFFFF
2029#define FE_AG_REG_EGC_FLA_INC_INIT 0x0
2030
2031
2032#define FE_AG_REG_EGC_FLA_DEC__A 0xC2002A
2033#define FE_AG_REG_EGC_FLA_DEC__W 16
2034#define FE_AG_REG_EGC_FLA_DEC__M 0xFFFF
2035#define FE_AG_REG_EGC_FLA_DEC_INIT 0x0
2036
2037
2038#define FE_AG_REG_EGC_SLO_INC__A 0xC2002B
2039#define FE_AG_REG_EGC_SLO_INC__W 16
2040#define FE_AG_REG_EGC_SLO_INC__M 0xFFFF
2041#define FE_AG_REG_EGC_SLO_INC_INIT 0x0
2042
2043
2044#define FE_AG_REG_EGC_SLO_DEC__A 0xC2002C
2045#define FE_AG_REG_EGC_SLO_DEC__W 16
2046#define FE_AG_REG_EGC_SLO_DEC__M 0xFFFF
2047#define FE_AG_REG_EGC_SLO_DEC_INIT 0x0
2048
2049
2050#define FE_AG_REG_EGC_FAS_INC__A 0xC2002D
2051#define FE_AG_REG_EGC_FAS_INC__W 16
2052#define FE_AG_REG_EGC_FAS_INC__M 0xFFFF
2053#define FE_AG_REG_EGC_FAS_INC_INIT 0x0
2054
2055
2056#define FE_AG_REG_EGC_FAS_DEC__A 0xC2002E
2057#define FE_AG_REG_EGC_FAS_DEC__W 16
2058#define FE_AG_REG_EGC_FAS_DEC__M 0xFFFF
2059#define FE_AG_REG_EGC_FAS_DEC_INIT 0x0
2060
2061
2062#define FE_AG_REG_EGC_MAP_DAT__A 0xC2002F
2063#define FE_AG_REG_EGC_MAP_DAT__W 16
2064#define FE_AG_REG_EGC_MAP_DAT__M 0xFFFF
2065
2066#define FE_AG_REG_PM1_AGC_WRI__A 0xC20030
2067#define FE_AG_REG_PM1_AGC_WRI__W 11
2068#define FE_AG_REG_PM1_AGC_WRI__M 0x7FF
2069#define FE_AG_REG_PM1_AGC_WRI_INIT 0x0
2070
2071
2072#define FE_AG_REG_GC1_AGC_RIC__A 0xC20031
2073#define FE_AG_REG_GC1_AGC_RIC__W 16
2074#define FE_AG_REG_GC1_AGC_RIC__M 0xFFFF
2075#define FE_AG_REG_GC1_AGC_RIC_INIT 0x0
2076
2077
2078#define FE_AG_REG_GC1_AGC_OFF__A 0xC20032
2079#define FE_AG_REG_GC1_AGC_OFF__W 16
2080#define FE_AG_REG_GC1_AGC_OFF__M 0xFFFF
2081#define FE_AG_REG_GC1_AGC_OFF_INIT 0x0
2082
2083
2084#define FE_AG_REG_GC1_AGC_MAX__A 0xC20033
2085#define FE_AG_REG_GC1_AGC_MAX__W 10
2086#define FE_AG_REG_GC1_AGC_MAX__M 0x3FF
2087#define FE_AG_REG_GC1_AGC_MAX_INIT 0x0
2088
2089
2090#define FE_AG_REG_GC1_AGC_MIN__A 0xC20034
2091#define FE_AG_REG_GC1_AGC_MIN__W 10
2092#define FE_AG_REG_GC1_AGC_MIN__M 0x3FF
2093#define FE_AG_REG_GC1_AGC_MIN_INIT 0x0
2094
2095
2096#define FE_AG_REG_GC1_AGC_DAT__A 0xC20035
2097#define FE_AG_REG_GC1_AGC_DAT__W 10
2098#define FE_AG_REG_GC1_AGC_DAT__M 0x3FF
2099
2100#define FE_AG_REG_PM2_AGC_WRI__A 0xC20036
2101#define FE_AG_REG_PM2_AGC_WRI__W 11
2102#define FE_AG_REG_PM2_AGC_WRI__M 0x7FF
2103#define FE_AG_REG_PM2_AGC_WRI_INIT 0x0
2104
2105
2106#define FE_AG_REG_GC2_AGC_RIC__A 0xC20037
2107#define FE_AG_REG_GC2_AGC_RIC__W 16
2108#define FE_AG_REG_GC2_AGC_RIC__M 0xFFFF
2109#define FE_AG_REG_GC2_AGC_RIC_INIT 0x0
2110
2111
2112#define FE_AG_REG_GC2_AGC_OFF__A 0xC20038
2113#define FE_AG_REG_GC2_AGC_OFF__W 16
2114#define FE_AG_REG_GC2_AGC_OFF__M 0xFFFF
2115#define FE_AG_REG_GC2_AGC_OFF_INIT 0x0
2116
2117
2118#define FE_AG_REG_GC2_AGC_MAX__A 0xC20039
2119#define FE_AG_REG_GC2_AGC_MAX__W 10
2120#define FE_AG_REG_GC2_AGC_MAX__M 0x3FF
2121#define FE_AG_REG_GC2_AGC_MAX_INIT 0x0
2122
2123
2124#define FE_AG_REG_GC2_AGC_MIN__A 0xC2003A
2125#define FE_AG_REG_GC2_AGC_MIN__W 10
2126#define FE_AG_REG_GC2_AGC_MIN__M 0x3FF
2127#define FE_AG_REG_GC2_AGC_MIN_INIT 0x0
2128
2129
2130#define FE_AG_REG_GC2_AGC_DAT__A 0xC2003B
2131#define FE_AG_REG_GC2_AGC_DAT__W 10
2132#define FE_AG_REG_GC2_AGC_DAT__M 0x3FF
2133
2134#define FE_AG_REG_IND_WIN__A 0xC2003C
2135#define FE_AG_REG_IND_WIN__W 5
2136#define FE_AG_REG_IND_WIN__M 0x1F
2137#define FE_AG_REG_IND_WIN_INIT 0x0
2138
2139
2140#define FE_AG_REG_IND_THD_LOL__A 0xC2003D
2141#define FE_AG_REG_IND_THD_LOL__W 6
2142#define FE_AG_REG_IND_THD_LOL__M 0x3F
2143#define FE_AG_REG_IND_THD_LOL_INIT 0x0
2144
2145
2146#define FE_AG_REG_IND_THD_HIL__A 0xC2003E
2147#define FE_AG_REG_IND_THD_HIL__W 6
2148#define FE_AG_REG_IND_THD_HIL__M 0x3F
2149#define FE_AG_REG_IND_THD_HIL_INIT 0x0
2150
2151
2152#define FE_AG_REG_IND_DEL__A 0xC2003F
2153#define FE_AG_REG_IND_DEL__W 7
2154#define FE_AG_REG_IND_DEL__M 0x7F
2155#define FE_AG_REG_IND_DEL_INIT 0x0
2156
2157
2158#define FE_AG_REG_IND_PD1_WRI__A 0xC20040
2159#define FE_AG_REG_IND_PD1_WRI__W 6
2160#define FE_AG_REG_IND_PD1_WRI__M 0x3F
2161#define FE_AG_REG_IND_PD1_WRI_INIT 0x1F
2162
2163
2164#define FE_AG_REG_PDA_AUR_CNT__A 0xC20041
2165#define FE_AG_REG_PDA_AUR_CNT__W 5
2166#define FE_AG_REG_PDA_AUR_CNT__M 0x1F
2167#define FE_AG_REG_PDA_AUR_CNT_INIT 0x0
2168
2169
2170#define FE_AG_REG_PDA_RUR_CNT__A 0xC20042
2171#define FE_AG_REG_PDA_RUR_CNT__W 5
2172#define FE_AG_REG_PDA_RUR_CNT__M 0x1F
2173#define FE_AG_REG_PDA_RUR_CNT_INIT 0x0
2174
2175
2176#define FE_AG_REG_PDA_AVE_DAT__A 0xC20043
2177#define FE_AG_REG_PDA_AVE_DAT__W 6
2178#define FE_AG_REG_PDA_AVE_DAT__M 0x3F
2179
2180#define FE_AG_REG_PDC_RUR_CNT__A 0xC20044
2181#define FE_AG_REG_PDC_RUR_CNT__W 5
2182#define FE_AG_REG_PDC_RUR_CNT__M 0x1F
2183#define FE_AG_REG_PDC_RUR_CNT_INIT 0x0
2184
2185
2186#define FE_AG_REG_PDC_SET_LVL__A 0xC20045
2187#define FE_AG_REG_PDC_SET_LVL__W 6
2188#define FE_AG_REG_PDC_SET_LVL__M 0x3F
2189#define FE_AG_REG_PDC_SET_LVL_INIT 0x10
2190
2191
2192#define FE_AG_REG_PDC_FLA_RGN__A 0xC20046
2193#define FE_AG_REG_PDC_FLA_RGN__W 6
2194#define FE_AG_REG_PDC_FLA_RGN__M 0x3F
2195#define FE_AG_REG_PDC_FLA_RGN_INIT 0x0
2196
2197
2198#define FE_AG_REG_PDC_JMP_PSN__A 0xC20047
2199#define FE_AG_REG_PDC_JMP_PSN__W 3
2200#define FE_AG_REG_PDC_JMP_PSN__M 0x7
2201#define FE_AG_REG_PDC_JMP_PSN_INIT 0x0
2202
2203
2204#define FE_AG_REG_PDC_FLA_STP__A 0xC20048
2205#define FE_AG_REG_PDC_FLA_STP__W 16
2206#define FE_AG_REG_PDC_FLA_STP__M 0xFFFF
2207#define FE_AG_REG_PDC_FLA_STP_INIT 0x0
2208
2209
2210#define FE_AG_REG_PDC_SLO_STP__A 0xC20049
2211#define FE_AG_REG_PDC_SLO_STP__W 16
2212#define FE_AG_REG_PDC_SLO_STP__M 0xFFFF
2213#define FE_AG_REG_PDC_SLO_STP_INIT 0x0
2214
2215
2216#define FE_AG_REG_PDC_PD2_WRI__A 0xC2004A
2217#define FE_AG_REG_PDC_PD2_WRI__W 6
2218#define FE_AG_REG_PDC_PD2_WRI__M 0x3F
2219#define FE_AG_REG_PDC_PD2_WRI_INIT 0x0
2220
2221
2222#define FE_AG_REG_PDC_MAP_DAT__A 0xC2004B
2223#define FE_AG_REG_PDC_MAP_DAT__W 6
2224#define FE_AG_REG_PDC_MAP_DAT__M 0x3F
2225
2226#define FE_AG_REG_PDC_MAX__A 0xC2004C
2227#define FE_AG_REG_PDC_MAX__W 6
2228#define FE_AG_REG_PDC_MAX__M 0x3F
2229#define FE_AG_REG_PDC_MAX_INIT 0x2
2230
2231
2232#define FE_AG_REG_TGA_AUR_CNT__A 0xC2004D
2233#define FE_AG_REG_TGA_AUR_CNT__W 5
2234#define FE_AG_REG_TGA_AUR_CNT__M 0x1F
2235#define FE_AG_REG_TGA_AUR_CNT_INIT 0x0
2236
2237
2238#define FE_AG_REG_TGA_RUR_CNT__A 0xC2004E
2239#define FE_AG_REG_TGA_RUR_CNT__W 5
2240#define FE_AG_REG_TGA_RUR_CNT__M 0x1F
2241#define FE_AG_REG_TGA_RUR_CNT_INIT 0x0
2242
2243
2244#define FE_AG_REG_TGA_AVE_DAT__A 0xC2004F
2245#define FE_AG_REG_TGA_AVE_DAT__W 6
2246#define FE_AG_REG_TGA_AVE_DAT__M 0x3F
2247
2248#define FE_AG_REG_TGC_RUR_CNT__A 0xC20050
2249#define FE_AG_REG_TGC_RUR_CNT__W 5
2250#define FE_AG_REG_TGC_RUR_CNT__M 0x1F
2251#define FE_AG_REG_TGC_RUR_CNT_INIT 0x0
2252
2253
2254#define FE_AG_REG_TGC_SET_LVL__A 0xC20051
2255#define FE_AG_REG_TGC_SET_LVL__W 6
2256#define FE_AG_REG_TGC_SET_LVL__M 0x3F
2257#define FE_AG_REG_TGC_SET_LVL_INIT 0x0
2258
2259
2260#define FE_AG_REG_TGC_FLA_RGN__A 0xC20052
2261#define FE_AG_REG_TGC_FLA_RGN__W 6
2262#define FE_AG_REG_TGC_FLA_RGN__M 0x3F
2263#define FE_AG_REG_TGC_FLA_RGN_INIT 0x0
2264
2265
2266#define FE_AG_REG_TGC_JMP_PSN__A 0xC20053
2267#define FE_AG_REG_TGC_JMP_PSN__W 4
2268#define FE_AG_REG_TGC_JMP_PSN__M 0xF
2269#define FE_AG_REG_TGC_JMP_PSN_INIT 0x0
2270
2271
2272#define FE_AG_REG_TGC_FLA_STP__A 0xC20054
2273#define FE_AG_REG_TGC_FLA_STP__W 16
2274#define FE_AG_REG_TGC_FLA_STP__M 0xFFFF
2275#define FE_AG_REG_TGC_FLA_STP_INIT 0x0
2276
2277
2278#define FE_AG_REG_TGC_SLO_STP__A 0xC20055
2279#define FE_AG_REG_TGC_SLO_STP__W 16
2280#define FE_AG_REG_TGC_SLO_STP__M 0xFFFF
2281#define FE_AG_REG_TGC_SLO_STP_INIT 0x0
2282
2283
2284#define FE_AG_REG_TGC_MAP_DAT__A 0xC20056
2285#define FE_AG_REG_TGC_MAP_DAT__W 10
2286#define FE_AG_REG_TGC_MAP_DAT__M 0x3FF
2287
2288#define FE_AG_REG_FGA_AUR_CNT__A 0xC20057
2289#define FE_AG_REG_FGA_AUR_CNT__W 5
2290#define FE_AG_REG_FGA_AUR_CNT__M 0x1F
2291#define FE_AG_REG_FGA_AUR_CNT_INIT 0x0
2292
2293
2294#define FE_AG_REG_FGA_RUR_CNT__A 0xC20058
2295#define FE_AG_REG_FGA_RUR_CNT__W 5
2296#define FE_AG_REG_FGA_RUR_CNT__M 0x1F
2297#define FE_AG_REG_FGA_RUR_CNT_INIT 0x0
2298
2299
2300#define FE_AG_REG_FGA_AVE_DAT__A 0xC20059
2301#define FE_AG_REG_FGA_AVE_DAT__W 10
2302#define FE_AG_REG_FGA_AVE_DAT__M 0x3FF
2303
2304#define FE_AG_REG_FGC_RUR_CNT__A 0xC2005A
2305#define FE_AG_REG_FGC_RUR_CNT__W 5
2306#define FE_AG_REG_FGC_RUR_CNT__M 0x1F
2307#define FE_AG_REG_FGC_RUR_CNT_INIT 0x0
2308
2309
2310#define FE_AG_REG_FGC_SET_LVL__A 0xC2005B
2311#define FE_AG_REG_FGC_SET_LVL__W 9
2312#define FE_AG_REG_FGC_SET_LVL__M 0x1FF
2313#define FE_AG_REG_FGC_SET_LVL_INIT 0x0
2314
2315
2316#define FE_AG_REG_FGC_FLA_RGN__A 0xC2005C
2317#define FE_AG_REG_FGC_FLA_RGN__W 9
2318#define FE_AG_REG_FGC_FLA_RGN__M 0x1FF
2319#define FE_AG_REG_FGC_FLA_RGN_INIT 0x0
2320
2321
2322#define FE_AG_REG_FGC_JMP_PSN__A 0xC2005D
2323#define FE_AG_REG_FGC_JMP_PSN__W 4
2324#define FE_AG_REG_FGC_JMP_PSN__M 0xF
2325#define FE_AG_REG_FGC_JMP_PSN_INIT 0x0
2326
2327
2328#define FE_AG_REG_FGC_FLA_STP__A 0xC2005E
2329#define FE_AG_REG_FGC_FLA_STP__W 16
2330#define FE_AG_REG_FGC_FLA_STP__M 0xFFFF
2331#define FE_AG_REG_FGC_FLA_STP_INIT 0x0
2332
2333
2334#define FE_AG_REG_FGC_SLO_STP__A 0xC2005F
2335#define FE_AG_REG_FGC_SLO_STP__W 16
2336#define FE_AG_REG_FGC_SLO_STP__M 0xFFFF
2337#define FE_AG_REG_FGC_SLO_STP_INIT 0x0
2338
2339
2340#define FE_AG_REG_FGC_MAP_DAT__A 0xC20060
2341#define FE_AG_REG_FGC_MAP_DAT__W 10
2342#define FE_AG_REG_FGC_MAP_DAT__M 0x3FF
2343
2344#define FE_AG_REG_FGM_WRI__A 0xC20061
2345#define FE_AG_REG_FGM_WRI__W 10
2346#define FE_AG_REG_FGM_WRI__M 0x3FF
2347#define FE_AG_REG_FGM_WRI_INIT 0x20
2348
2349
2350#define FE_AG_REG_BGC_RUR_CNT__A 0xC20062
2351#define FE_AG_REG_BGC_RUR_CNT__W 5
2352#define FE_AG_REG_BGC_RUR_CNT__M 0x1F
2353#define FE_AG_REG_BGC_RUR_CNT_INIT 0x0
2354
2355
2356#define FE_AG_REG_BGC_SET_LVL__A 0xC20063
2357#define FE_AG_REG_BGC_SET_LVL__W 9
2358#define FE_AG_REG_BGC_SET_LVL__M 0x1FF
2359#define FE_AG_REG_BGC_SET_LVL_INIT 0x0
2360
2361
2362#define FE_AG_REG_BGC_FLA_RGN__A 0xC20064
2363#define FE_AG_REG_BGC_FLA_RGN__W 9
2364#define FE_AG_REG_BGC_FLA_RGN__M 0x1FF
2365#define FE_AG_REG_BGC_FLA_RGN_INIT 0x0
2366
2367
2368#define FE_AG_REG_BGC_JMP_PSN__A 0xC20065
2369#define FE_AG_REG_BGC_JMP_PSN__W 4
2370#define FE_AG_REG_BGC_JMP_PSN__M 0xF
2371#define FE_AG_REG_BGC_JMP_PSN_INIT 0x0
2372
2373
2374#define FE_AG_REG_BGC_FLA_STP__A 0xC20066
2375#define FE_AG_REG_BGC_FLA_STP__W 16
2376#define FE_AG_REG_BGC_FLA_STP__M 0xFFFF
2377#define FE_AG_REG_BGC_FLA_STP_INIT 0x0
2378
2379
2380#define FE_AG_REG_BGC_SLO_STP__A 0xC20067
2381#define FE_AG_REG_BGC_SLO_STP__W 16
2382#define FE_AG_REG_BGC_SLO_STP__M 0xFFFF
2383#define FE_AG_REG_BGC_SLO_STP_INIT 0x0
2384
2385
2386#define FE_AG_REG_BGC_FGC_WRI__A 0xC20068
2387#define FE_AG_REG_BGC_FGC_WRI__W 4
2388#define FE_AG_REG_BGC_FGC_WRI__M 0xF
2389#define FE_AG_REG_BGC_FGC_WRI_INIT 0x7
2390
2391
2392#define FE_AG_REG_BGC_CGC_WRI__A 0xC20069
2393#define FE_AG_REG_BGC_CGC_WRI__W 2
2394#define FE_AG_REG_BGC_CGC_WRI__M 0x3
2395#define FE_AG_REG_BGC_CGC_WRI_INIT 0x1
2396
2397
2398#define FE_AG_REG_BGC_FGC_DAT__A 0xC2006A
2399#define FE_AG_REG_BGC_FGC_DAT__W 4
2400#define FE_AG_REG_BGC_FGC_DAT__M 0xF
2401
2402
2403
2404
2405
2406#define FE_FS_SID 0x3
2407
2408
2409
2410
2411
2412
2413#define FE_FS_REG_COMM_EXEC__A 0xC30000
2414#define FE_FS_REG_COMM_EXEC__W 3
2415#define FE_FS_REG_COMM_EXEC__M 0x7
2416#define FE_FS_REG_COMM_EXEC_CTL__B 0
2417#define FE_FS_REG_COMM_EXEC_CTL__W 3
2418#define FE_FS_REG_COMM_EXEC_CTL__M 0x7
2419#define FE_FS_REG_COMM_EXEC_CTL_STOP 0x0
2420#define FE_FS_REG_COMM_EXEC_CTL_ACTIVE 0x1
2421#define FE_FS_REG_COMM_EXEC_CTL_HOLD 0x2
2422#define FE_FS_REG_COMM_EXEC_CTL_STEP 0x3
2423
2424#define FE_FS_REG_COMM_STATE__A 0xC30001
2425#define FE_FS_REG_COMM_STATE__W 4
2426#define FE_FS_REG_COMM_STATE__M 0xF
2427
2428#define FE_FS_REG_COMM_MB__A 0xC30002
2429#define FE_FS_REG_COMM_MB__W 3
2430#define FE_FS_REG_COMM_MB__M 0x7
2431#define FE_FS_REG_COMM_MB_CTR__B 0
2432#define FE_FS_REG_COMM_MB_CTR__W 1
2433#define FE_FS_REG_COMM_MB_CTR__M 0x1
2434#define FE_FS_REG_COMM_MB_CTR_OFF 0x0
2435#define FE_FS_REG_COMM_MB_CTR_ON 0x1
2436#define FE_FS_REG_COMM_MB_OBS__B 1
2437#define FE_FS_REG_COMM_MB_OBS__W 1
2438#define FE_FS_REG_COMM_MB_OBS__M 0x2
2439#define FE_FS_REG_COMM_MB_OBS_OFF 0x0
2440#define FE_FS_REG_COMM_MB_OBS_ON 0x2
2441#define FE_FS_REG_COMM_MB_MUX__B 2
2442#define FE_FS_REG_COMM_MB_MUX__W 1
2443#define FE_FS_REG_COMM_MB_MUX__M 0x4
2444#define FE_FS_REG_COMM_MB_MUX_REAL 0x0
2445#define FE_FS_REG_COMM_MB_MUX_IMAG 0x4
2446
2447
2448#define FE_FS_REG_COMM_SERVICE0__A 0xC30003
2449#define FE_FS_REG_COMM_SERVICE0__W 10
2450#define FE_FS_REG_COMM_SERVICE0__M 0x3FF
2451
2452#define FE_FS_REG_COMM_SERVICE1__A 0xC30004
2453#define FE_FS_REG_COMM_SERVICE1__W 11
2454#define FE_FS_REG_COMM_SERVICE1__M 0x7FF
2455
2456#define FE_FS_REG_COMM_ACT__A 0xC30005
2457#define FE_FS_REG_COMM_ACT__W 2
2458#define FE_FS_REG_COMM_ACT__M 0x3
2459
2460#define FE_FS_REG_COMM_CNT__A 0xC30006
2461#define FE_FS_REG_COMM_CNT__W 16
2462#define FE_FS_REG_COMM_CNT__M 0xFFFF
2463
2464#define FE_FS_REG_ADD_INC_LOP__A 0xC30010
2465#define FE_FS_REG_ADD_INC_LOP__W 16
2466#define FE_FS_REG_ADD_INC_LOP__M 0xFFFF
2467#define FE_FS_REG_ADD_INC_LOP_INIT 0x0
2468
2469
2470#define FE_FS_REG_ADD_INC_HIP__A 0xC30011
2471#define FE_FS_REG_ADD_INC_HIP__W 12
2472#define FE_FS_REG_ADD_INC_HIP__M 0xFFF
2473#define FE_FS_REG_ADD_INC_HIP_INIT 0x0
2474
2475
2476#define FE_FS_REG_ADD_OFF__A 0xC30012
2477#define FE_FS_REG_ADD_OFF__W 12
2478#define FE_FS_REG_ADD_OFF__M 0xFFF
2479#define FE_FS_REG_ADD_OFF_INIT 0x0
2480
2481
2482#define FE_FS_REG_ADD_OFF_VAL__A 0xC30013
2483#define FE_FS_REG_ADD_OFF_VAL__W 1
2484#define FE_FS_REG_ADD_OFF_VAL__M 0x1
2485#define FE_FS_REG_ADD_OFF_VAL_INIT 0x0
2486
2487
2488
2489
2490
2491#define FE_FD_SID 0x4
2492
2493
2494
2495
2496
2497
2498#define FE_FD_REG_COMM_EXEC__A 0xC40000
2499#define FE_FD_REG_COMM_EXEC__W 3
2500#define FE_FD_REG_COMM_EXEC__M 0x7
2501#define FE_FD_REG_COMM_EXEC_CTL__B 0
2502#define FE_FD_REG_COMM_EXEC_CTL__W 3
2503#define FE_FD_REG_COMM_EXEC_CTL__M 0x7
2504#define FE_FD_REG_COMM_EXEC_CTL_STOP 0x0
2505#define FE_FD_REG_COMM_EXEC_CTL_ACTIVE 0x1
2506#define FE_FD_REG_COMM_EXEC_CTL_HOLD 0x2
2507#define FE_FD_REG_COMM_EXEC_CTL_STEP 0x3
2508
2509
2510#define FE_FD_REG_COMM_MB__A 0xC40002
2511#define FE_FD_REG_COMM_MB__W 3
2512#define FE_FD_REG_COMM_MB__M 0x7
2513#define FE_FD_REG_COMM_MB_CTR__B 0
2514#define FE_FD_REG_COMM_MB_CTR__W 1
2515#define FE_FD_REG_COMM_MB_CTR__M 0x1
2516#define FE_FD_REG_COMM_MB_CTR_OFF 0x0
2517#define FE_FD_REG_COMM_MB_CTR_ON 0x1
2518#define FE_FD_REG_COMM_MB_OBS__B 1
2519#define FE_FD_REG_COMM_MB_OBS__W 1
2520#define FE_FD_REG_COMM_MB_OBS__M 0x2
2521#define FE_FD_REG_COMM_MB_OBS_OFF 0x0
2522#define FE_FD_REG_COMM_MB_OBS_ON 0x2
2523
2524#define FE_FD_REG_COMM_SERVICE0__A 0xC40003
2525#define FE_FD_REG_COMM_SERVICE0__W 10
2526#define FE_FD_REG_COMM_SERVICE0__M 0x3FF
2527#define FE_FD_REG_COMM_SERVICE1__A 0xC40004
2528#define FE_FD_REG_COMM_SERVICE1__W 11
2529#define FE_FD_REG_COMM_SERVICE1__M 0x7FF
2530
2531#define FE_FD_REG_COMM_INT_STA__A 0xC40007
2532#define FE_FD_REG_COMM_INT_STA__W 1
2533#define FE_FD_REG_COMM_INT_STA__M 0x1
2534#define FE_FD_REG_COMM_INT_STA_NEW_MEAS__B 0
2535#define FE_FD_REG_COMM_INT_STA_NEW_MEAS__W 1
2536#define FE_FD_REG_COMM_INT_STA_NEW_MEAS__M 0x1
2537
2538
2539#define FE_FD_REG_COMM_INT_MSK__A 0xC40008
2540#define FE_FD_REG_COMM_INT_MSK__W 1
2541#define FE_FD_REG_COMM_INT_MSK__M 0x1
2542#define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__B 0
2543#define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__W 1
2544#define FE_FD_REG_COMM_INT_MSK_NEW_MEAS__M 0x1
2545
2546
2547#define FE_FD_REG_SCL__A 0xC40010
2548#define FE_FD_REG_SCL__W 6
2549#define FE_FD_REG_SCL__M 0x3F
2550
2551#define FE_FD_REG_MAX_LEV__A 0xC40011
2552#define FE_FD_REG_MAX_LEV__W 3
2553#define FE_FD_REG_MAX_LEV__M 0x7
2554
2555#define FE_FD_REG_NR__A 0xC40012
2556#define FE_FD_REG_NR__W 5
2557#define FE_FD_REG_NR__M 0x1F
2558
2559#define FE_FD_REG_MEAS_SEL__A 0xC40013
2560#define FE_FD_REG_MEAS_SEL__W 1
2561#define FE_FD_REG_MEAS_SEL__M 0x1
2562
2563#define FE_FD_REG_MEAS_VAL__A 0xC40014
2564#define FE_FD_REG_MEAS_VAL__W 1
2565#define FE_FD_REG_MEAS_VAL__M 0x1
2566
2567#define FE_FD_REG_MAX__A 0xC40015
2568#define FE_FD_REG_MAX__W 16
2569#define FE_FD_REG_MAX__M 0xFFFF
2570
2571#define FE_FD_REG_POWER__A 0xC40016
2572#define FE_FD_REG_POWER__W 10
2573#define FE_FD_REG_POWER__M 0x3FF
2574
2575
2576
2577
2578
2579#define FE_IF_SID 0x5
2580
2581
2582
2583
2584
2585
2586#define FE_IF_REG_COMM_EXEC__A 0xC50000
2587#define FE_IF_REG_COMM_EXEC__W 3
2588#define FE_IF_REG_COMM_EXEC__M 0x7
2589#define FE_IF_REG_COMM_EXEC_CTL__B 0
2590#define FE_IF_REG_COMM_EXEC_CTL__W 3
2591#define FE_IF_REG_COMM_EXEC_CTL__M 0x7
2592#define FE_IF_REG_COMM_EXEC_CTL_STOP 0x0
2593#define FE_IF_REG_COMM_EXEC_CTL_ACTIVE 0x1
2594#define FE_IF_REG_COMM_EXEC_CTL_HOLD 0x2
2595#define FE_IF_REG_COMM_EXEC_CTL_STEP 0x3
2596
2597
2598#define FE_IF_REG_COMM_MB__A 0xC50002
2599#define FE_IF_REG_COMM_MB__W 3
2600#define FE_IF_REG_COMM_MB__M 0x7
2601#define FE_IF_REG_COMM_MB_CTR__B 0
2602#define FE_IF_REG_COMM_MB_CTR__W 1
2603#define FE_IF_REG_COMM_MB_CTR__M 0x1
2604#define FE_IF_REG_COMM_MB_CTR_OFF 0x0
2605#define FE_IF_REG_COMM_MB_CTR_ON 0x1
2606#define FE_IF_REG_COMM_MB_OBS__B 1
2607#define FE_IF_REG_COMM_MB_OBS__W 1
2608#define FE_IF_REG_COMM_MB_OBS__M 0x2
2609#define FE_IF_REG_COMM_MB_OBS_OFF 0x0
2610#define FE_IF_REG_COMM_MB_OBS_ON 0x2
2611
2612
2613#define FE_IF_REG_INCR0__A 0xC50010
2614#define FE_IF_REG_INCR0__W 16
2615#define FE_IF_REG_INCR0__M 0xFFFF
2616#define FE_IF_REG_INCR0_INIT 0x0
2617
2618
2619#define FE_IF_REG_INCR1__A 0xC50011
2620#define FE_IF_REG_INCR1__W 8
2621#define FE_IF_REG_INCR1__M 0xFF
2622#define FE_IF_REG_INCR1_INIT 0x28
2623
2624
2625
2626
2627
2628#define FE_CF_SID 0x6
2629
2630
2631
2632
2633
2634
2635#define FE_CF_REG_COMM_EXEC__A 0xC60000
2636#define FE_CF_REG_COMM_EXEC__W 3
2637#define FE_CF_REG_COMM_EXEC__M 0x7
2638#define FE_CF_REG_COMM_EXEC_CTL__B 0
2639#define FE_CF_REG_COMM_EXEC_CTL__W 3
2640#define FE_CF_REG_COMM_EXEC_CTL__M 0x7
2641#define FE_CF_REG_COMM_EXEC_CTL_STOP 0x0
2642#define FE_CF_REG_COMM_EXEC_CTL_ACTIVE 0x1
2643#define FE_CF_REG_COMM_EXEC_CTL_HOLD 0x2
2644#define FE_CF_REG_COMM_EXEC_CTL_STEP 0x3
2645
2646
2647#define FE_CF_REG_COMM_MB__A 0xC60002
2648#define FE_CF_REG_COMM_MB__W 3
2649#define FE_CF_REG_COMM_MB__M 0x7
2650#define FE_CF_REG_COMM_MB_CTR__B 0
2651#define FE_CF_REG_COMM_MB_CTR__W 1
2652#define FE_CF_REG_COMM_MB_CTR__M 0x1
2653#define FE_CF_REG_COMM_MB_CTR_OFF 0x0
2654#define FE_CF_REG_COMM_MB_CTR_ON 0x1
2655#define FE_CF_REG_COMM_MB_OBS__B 1
2656#define FE_CF_REG_COMM_MB_OBS__W 1
2657#define FE_CF_REG_COMM_MB_OBS__M 0x2
2658#define FE_CF_REG_COMM_MB_OBS_OFF 0x0
2659#define FE_CF_REG_COMM_MB_OBS_ON 0x2
2660
2661#define FE_CF_REG_COMM_SERVICE0__A 0xC60003
2662#define FE_CF_REG_COMM_SERVICE0__W 10
2663#define FE_CF_REG_COMM_SERVICE0__M 0x3FF
2664#define FE_CF_REG_COMM_SERVICE1__A 0xC60004
2665#define FE_CF_REG_COMM_SERVICE1__W 11
2666#define FE_CF_REG_COMM_SERVICE1__M 0x7FF
2667
2668#define FE_CF_REG_COMM_INT_STA__A 0xC60007
2669#define FE_CF_REG_COMM_INT_STA__W 2
2670#define FE_CF_REG_COMM_INT_STA__M 0x3
2671#define FE_CF_REG_COMM_INT_STA_NEW_MEAS__B 0
2672#define FE_CF_REG_COMM_INT_STA_NEW_MEAS__W 1
2673#define FE_CF_REG_COMM_INT_STA_NEW_MEAS__M 0x1
2674
2675
2676#define FE_CF_REG_COMM_INT_MSK__A 0xC60008
2677#define FE_CF_REG_COMM_INT_MSK__W 2
2678#define FE_CF_REG_COMM_INT_MSK__M 0x3
2679#define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__B 0
2680#define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__W 1
2681#define FE_CF_REG_COMM_INT_MSK_NEW_MEAS__M 0x1
2682
2683
2684#define FE_CF_REG_SCL__A 0xC60010
2685#define FE_CF_REG_SCL__W 9
2686#define FE_CF_REG_SCL__M 0x1FF
2687
2688#define FE_CF_REG_MAX_LEV__A 0xC60011
2689#define FE_CF_REG_MAX_LEV__W 3
2690#define FE_CF_REG_MAX_LEV__M 0x7
2691
2692#define FE_CF_REG_NR__A 0xC60012
2693#define FE_CF_REG_NR__W 5
2694#define FE_CF_REG_NR__M 0x1F
2695
2696#define FE_CF_REG_IMP_VAL__A 0xC60013
2697#define FE_CF_REG_IMP_VAL__W 1
2698#define FE_CF_REG_IMP_VAL__M 0x1
2699
2700#define FE_CF_REG_MEAS_VAL__A 0xC60014
2701#define FE_CF_REG_MEAS_VAL__W 1
2702#define FE_CF_REG_MEAS_VAL__M 0x1
2703
2704#define FE_CF_REG_MAX__A 0xC60015
2705#define FE_CF_REG_MAX__W 16
2706#define FE_CF_REG_MAX__M 0xFFFF
2707
2708#define FE_CF_REG_POWER__A 0xC60016
2709#define FE_CF_REG_POWER__W 10
2710#define FE_CF_REG_POWER__M 0x3FF
2711
2712
2713
2714
2715
2716#define FE_CU_SID 0x7
2717
2718
2719
2720
2721
2722
2723#define FE_CU_REG_COMM_EXEC__A 0xC70000
2724#define FE_CU_REG_COMM_EXEC__W 3
2725#define FE_CU_REG_COMM_EXEC__M 0x7
2726#define FE_CU_REG_COMM_EXEC_CTL__B 0
2727#define FE_CU_REG_COMM_EXEC_CTL__W 3
2728#define FE_CU_REG_COMM_EXEC_CTL__M 0x7
2729#define FE_CU_REG_COMM_EXEC_CTL_STOP 0x0
2730#define FE_CU_REG_COMM_EXEC_CTL_ACTIVE 0x1
2731#define FE_CU_REG_COMM_EXEC_CTL_HOLD 0x2
2732#define FE_CU_REG_COMM_EXEC_CTL_STEP 0x3
2733
2734#define FE_CU_REG_COMM_STATE__A 0xC70001
2735#define FE_CU_REG_COMM_STATE__W 4
2736#define FE_CU_REG_COMM_STATE__M 0xF
2737
2738#define FE_CU_REG_COMM_MB__A 0xC70002
2739#define FE_CU_REG_COMM_MB__W 3
2740#define FE_CU_REG_COMM_MB__M 0x7
2741#define FE_CU_REG_COMM_MB_CTR__B 0
2742#define FE_CU_REG_COMM_MB_CTR__W 1
2743#define FE_CU_REG_COMM_MB_CTR__M 0x1
2744#define FE_CU_REG_COMM_MB_CTR_OFF 0x0
2745#define FE_CU_REG_COMM_MB_CTR_ON 0x1
2746#define FE_CU_REG_COMM_MB_OBS__B 1
2747#define FE_CU_REG_COMM_MB_OBS__W 1
2748#define FE_CU_REG_COMM_MB_OBS__M 0x2
2749#define FE_CU_REG_COMM_MB_OBS_OFF 0x0
2750#define FE_CU_REG_COMM_MB_OBS_ON 0x2
2751#define FE_CU_REG_COMM_MB_MUX__B 2
2752#define FE_CU_REG_COMM_MB_MUX__W 1
2753#define FE_CU_REG_COMM_MB_MUX__M 0x4
2754#define FE_CU_REG_COMM_MB_MUX_REAL 0x0
2755#define FE_CU_REG_COMM_MB_MUX_IMAG 0x4
2756
2757
2758#define FE_CU_REG_COMM_SERVICE0__A 0xC70003
2759#define FE_CU_REG_COMM_SERVICE0__W 10
2760#define FE_CU_REG_COMM_SERVICE0__M 0x3FF
2761
2762#define FE_CU_REG_COMM_SERVICE1__A 0xC70004
2763#define FE_CU_REG_COMM_SERVICE1__W 11
2764#define FE_CU_REG_COMM_SERVICE1__M 0x7FF
2765
2766#define FE_CU_REG_COMM_ACT__A 0xC70005
2767#define FE_CU_REG_COMM_ACT__W 2
2768#define FE_CU_REG_COMM_ACT__M 0x3
2769
2770#define FE_CU_REG_COMM_CNT__A 0xC70006
2771#define FE_CU_REG_COMM_CNT__W 16
2772#define FE_CU_REG_COMM_CNT__M 0xFFFF
2773
2774#define FE_CU_REG_COMM_INT_STA__A 0xC70007
2775#define FE_CU_REG_COMM_INT_STA__W 2
2776#define FE_CU_REG_COMM_INT_STA__M 0x3
2777#define FE_CU_REG_COMM_INT_STA_FE_START__B 0
2778#define FE_CU_REG_COMM_INT_STA_FE_START__W 1
2779#define FE_CU_REG_COMM_INT_STA_FE_START__M 0x1
2780#define FE_CU_REG_COMM_INT_STA_FT_START__B 1
2781#define FE_CU_REG_COMM_INT_STA_FT_START__W 1
2782#define FE_CU_REG_COMM_INT_STA_FT_START__M 0x2
2783
2784
2785#define FE_CU_REG_COMM_INT_MSK__A 0xC70008
2786#define FE_CU_REG_COMM_INT_MSK__W 2
2787#define FE_CU_REG_COMM_INT_MSK__M 0x3
2788#define FE_CU_REG_COMM_INT_MSK_FE_START__B 0
2789#define FE_CU_REG_COMM_INT_MSK_FE_START__W 1
2790#define FE_CU_REG_COMM_INT_MSK_FE_START__M 0x1
2791#define FE_CU_REG_COMM_INT_MSK_FT_START__B 1
2792#define FE_CU_REG_COMM_INT_MSK_FT_START__W 1
2793#define FE_CU_REG_COMM_INT_MSK_FT_START__M 0x2
2794
2795
2796#define FE_CU_REG_MODE__A 0xC70010
2797#define FE_CU_REG_MODE__W 3
2798#define FE_CU_REG_MODE__M 0x7
2799#define FE_CU_REG_MODE_INIT 0x0
2800
2801#define FE_CU_REG_MODE_FFT__B 0
2802#define FE_CU_REG_MODE_FFT__W 1
2803#define FE_CU_REG_MODE_FFT__M 0x1
2804#define FE_CU_REG_MODE_FFT_M8K 0x0
2805#define FE_CU_REG_MODE_FFT_M2K 0x1
2806
2807#define FE_CU_REG_MODE_COR__B 1
2808#define FE_CU_REG_MODE_COR__W 1
2809#define FE_CU_REG_MODE_COR__M 0x2
2810#define FE_CU_REG_MODE_COR_OFF 0x0
2811#define FE_CU_REG_MODE_COR_ON 0x2
2812
2813#define FE_CU_REG_MODE_IFD__B 2
2814#define FE_CU_REG_MODE_IFD__W 1
2815#define FE_CU_REG_MODE_IFD__M 0x4
2816#define FE_CU_REG_MODE_IFD_ENABLE 0x0
2817#define FE_CU_REG_MODE_IFD_DISABLE 0x4
2818
2819
2820#define FE_CU_REG_FRM_CNT_RST__A 0xC70011
2821#define FE_CU_REG_FRM_CNT_RST__W 15
2822#define FE_CU_REG_FRM_CNT_RST__M 0x7FFF
2823#define FE_CU_REG_FRM_CNT_RST_INIT 0x0
2824
2825
2826#define FE_CU_REG_FRM_CNT_STR__A 0xC70012
2827#define FE_CU_REG_FRM_CNT_STR__W 15
2828#define FE_CU_REG_FRM_CNT_STR__M 0x7FFF
2829#define FE_CU_REG_FRM_CNT_STR_INIT 0x0
2830
2831
2832#define FE_CU_REG_FRM_SMP_CNT__A 0xC70013
2833#define FE_CU_REG_FRM_SMP_CNT__W 15
2834#define FE_CU_REG_FRM_SMP_CNT__M 0x7FFF
2835
2836#define FE_CU_REG_FRM_SMB_CNT__A 0xC70014
2837#define FE_CU_REG_FRM_SMB_CNT__W 16
2838#define FE_CU_REG_FRM_SMB_CNT__M 0xFFFF
2839
2840#define FE_CU_REG_CMP_MAX_DAT__A 0xC70015
2841#define FE_CU_REG_CMP_MAX_DAT__W 12
2842#define FE_CU_REG_CMP_MAX_DAT__M 0xFFF
2843
2844#define FE_CU_REG_CMP_MAX_ADR__A 0xC70016
2845#define FE_CU_REG_CMP_MAX_ADR__W 10
2846#define FE_CU_REG_CMP_MAX_ADR__M 0x3FF
2847
2848#define FE_CU_REG_CTR_NF1_WLO__A 0xC70017
2849#define FE_CU_REG_CTR_NF1_WLO__W 15
2850#define FE_CU_REG_CTR_NF1_WLO__M 0x7FFF
2851#define FE_CU_REG_CTR_NF1_WLO_INIT 0x0
2852
2853
2854#define FE_CU_REG_CTR_NF1_WHI__A 0xC70018
2855#define FE_CU_REG_CTR_NF1_WHI__W 15
2856#define FE_CU_REG_CTR_NF1_WHI__M 0x7FFF
2857#define FE_CU_REG_CTR_NF1_WHI_INIT 0x0
2858
2859
2860#define FE_CU_REG_CTR_NF2_WLO__A 0xC70019
2861#define FE_CU_REG_CTR_NF2_WLO__W 15
2862#define FE_CU_REG_CTR_NF2_WLO__M 0x7FFF
2863#define FE_CU_REG_CTR_NF2_WLO_INIT 0x0
2864
2865
2866#define FE_CU_REG_CTR_NF2_WHI__A 0xC7001A
2867#define FE_CU_REG_CTR_NF2_WHI__W 15
2868#define FE_CU_REG_CTR_NF2_WHI__M 0x7FFF
2869#define FE_CU_REG_CTR_NF2_WHI_INIT 0x0
2870
2871
2872#define FE_CU_REG_DIV_NF1_REA__A 0xC7001B
2873#define FE_CU_REG_DIV_NF1_REA__W 12
2874#define FE_CU_REG_DIV_NF1_REA__M 0xFFF
2875
2876#define FE_CU_REG_DIV_NF1_IMA__A 0xC7001C
2877#define FE_CU_REG_DIV_NF1_IMA__W 12
2878#define FE_CU_REG_DIV_NF1_IMA__M 0xFFF
2879
2880#define FE_CU_REG_DIV_NF2_REA__A 0xC7001D
2881#define FE_CU_REG_DIV_NF2_REA__W 12
2882#define FE_CU_REG_DIV_NF2_REA__M 0xFFF
2883
2884#define FE_CU_REG_DIV_NF2_IMA__A 0xC7001E
2885#define FE_CU_REG_DIV_NF2_IMA__W 12
2886#define FE_CU_REG_DIV_NF2_IMA__M 0xFFF
2887
2888
2889
2890#define FE_CU_BUF_RAM__A 0xC80000
2891
2892
2893
2894#define FE_CU_CMP_RAM__A 0xC90000
2895
2896
2897
2898
2899
2900#define FT_SID 0x8
2901
2902
2903
2904
2905
2906#define FT_COMM_EXEC__A 0x1000000
2907#define FT_COMM_EXEC__W 3
2908#define FT_COMM_EXEC__M 0x7
2909#define FT_COMM_EXEC_CTL__B 0
2910#define FT_COMM_EXEC_CTL__W 3
2911#define FT_COMM_EXEC_CTL__M 0x7
2912#define FT_COMM_EXEC_CTL_STOP 0x0
2913#define FT_COMM_EXEC_CTL_ACTIVE 0x1
2914#define FT_COMM_EXEC_CTL_HOLD 0x2
2915#define FT_COMM_EXEC_CTL_STEP 0x3
2916#define FT_COMM_EXEC_CTL_BYPASS_STOP 0x4
2917#define FT_COMM_EXEC_CTL_BYPASS_HOLD 0x6
2918
2919#define FT_COMM_STATE__A 0x1000001
2920#define FT_COMM_STATE__W 16
2921#define FT_COMM_STATE__M 0xFFFF
2922#define FT_COMM_MB__A 0x1000002
2923#define FT_COMM_MB__W 16
2924#define FT_COMM_MB__M 0xFFFF
2925#define FT_COMM_SERVICE0__A 0x1000003
2926#define FT_COMM_SERVICE0__W 16
2927#define FT_COMM_SERVICE0__M 0xFFFF
2928#define FT_COMM_SERVICE1__A 0x1000004
2929#define FT_COMM_SERVICE1__W 16
2930#define FT_COMM_SERVICE1__M 0xFFFF
2931#define FT_COMM_INT_STA__A 0x1000007
2932#define FT_COMM_INT_STA__W 16
2933#define FT_COMM_INT_STA__M 0xFFFF
2934#define FT_COMM_INT_MSK__A 0x1000008
2935#define FT_COMM_INT_MSK__W 16
2936#define FT_COMM_INT_MSK__M 0xFFFF
2937
2938
2939
2940
2941
2942
2943#define FT_REG_COMM_EXEC__A 0x1010000
2944#define FT_REG_COMM_EXEC__W 3
2945#define FT_REG_COMM_EXEC__M 0x7
2946#define FT_REG_COMM_EXEC_CTL__B 0
2947#define FT_REG_COMM_EXEC_CTL__W 3
2948#define FT_REG_COMM_EXEC_CTL__M 0x7
2949#define FT_REG_COMM_EXEC_CTL_STOP 0x0
2950#define FT_REG_COMM_EXEC_CTL_ACTIVE 0x1
2951#define FT_REG_COMM_EXEC_CTL_HOLD 0x2
2952#define FT_REG_COMM_EXEC_CTL_STEP 0x3
2953
2954
2955#define FT_REG_COMM_MB__A 0x1010002
2956#define FT_REG_COMM_MB__W 3
2957#define FT_REG_COMM_MB__M 0x7
2958#define FT_REG_COMM_MB_CTR__B 0
2959#define FT_REG_COMM_MB_CTR__W 1
2960#define FT_REG_COMM_MB_CTR__M 0x1
2961#define FT_REG_COMM_MB_CTR_OFF 0x0
2962#define FT_REG_COMM_MB_CTR_ON 0x1
2963#define FT_REG_COMM_MB_OBS__B 1
2964#define FT_REG_COMM_MB_OBS__W 1
2965#define FT_REG_COMM_MB_OBS__M 0x2
2966#define FT_REG_COMM_MB_OBS_OFF 0x0
2967#define FT_REG_COMM_MB_OBS_ON 0x2
2968
2969#define FT_REG_COMM_SERVICE0__A 0x1010003
2970#define FT_REG_COMM_SERVICE0__W 10
2971#define FT_REG_COMM_SERVICE0__M 0x3FF
2972#define FT_REG_COMM_SERVICE0_FT__B 8
2973#define FT_REG_COMM_SERVICE0_FT__W 1
2974#define FT_REG_COMM_SERVICE0_FT__M 0x100
2975
2976#define FT_REG_COMM_SERVICE1__A 0x1010004
2977#define FT_REG_COMM_SERVICE1__W 11
2978#define FT_REG_COMM_SERVICE1__M 0x7FF
2979
2980#define FT_REG_COMM_INT_STA__A 0x1010007
2981#define FT_REG_COMM_INT_STA__W 2
2982#define FT_REG_COMM_INT_STA__M 0x3
2983#define FT_REG_COMM_INT_STA_NEW_MEAS__B 0
2984#define FT_REG_COMM_INT_STA_NEW_MEAS__W 1
2985#define FT_REG_COMM_INT_STA_NEW_MEAS__M 0x1
2986
2987
2988#define FT_REG_COMM_INT_MSK__A 0x1010008
2989#define FT_REG_COMM_INT_MSK__W 2
2990#define FT_REG_COMM_INT_MSK__M 0x3
2991#define FT_REG_COMM_INT_MSK_NEW_MEAS__B 0
2992#define FT_REG_COMM_INT_MSK_NEW_MEAS__W 1
2993#define FT_REG_COMM_INT_MSK_NEW_MEAS__M 0x1
2994
2995
2996#define FT_REG_MODE_2K__A 0x1010010
2997#define FT_REG_MODE_2K__W 1
2998#define FT_REG_MODE_2K__M 0x1
2999#define FT_REG_MODE_2K_MODE_8K 0x0
3000#define FT_REG_MODE_2K_MODE_2K 0x1
3001#define FT_REG_MODE_2K_INIT 0x0
3002
3003
3004#define FT_REG_BUS_MOD__A 0x1010011
3005#define FT_REG_BUS_MOD__W 1
3006#define FT_REG_BUS_MOD__M 0x1
3007#define FT_REG_BUS_MOD_INPUT 0x0
3008#define FT_REG_BUS_MOD_PILOT 0x1
3009#define FT_REG_BUS_MOD_INIT 0x0
3010
3011
3012#define FT_REG_BUS_REAL__A 0x1010012
3013#define FT_REG_BUS_REAL__W 10
3014#define FT_REG_BUS_REAL__M 0x3FF
3015#define FT_REG_BUS_REAL_INIT 0x0
3016
3017
3018#define FT_REG_BUS_IMAG__A 0x1010013
3019#define FT_REG_BUS_IMAG__W 10
3020#define FT_REG_BUS_IMAG__M 0x3FF
3021#define FT_REG_BUS_IMAG_INIT 0x0
3022
3023
3024#define FT_REG_BUS_VAL__A 0x1010014
3025#define FT_REG_BUS_VAL__W 1
3026#define FT_REG_BUS_VAL__M 0x1
3027#define FT_REG_BUS_VAL_INIT 0x0
3028
3029
3030#define FT_REG_PEAK__A 0x1010015
3031#define FT_REG_PEAK__W 11
3032#define FT_REG_PEAK__M 0x7FF
3033#define FT_REG_PEAK_INIT 0x0
3034
3035
3036#define FT_REG_NORM_OFF__A 0x1010016
3037#define FT_REG_NORM_OFF__W 4
3038#define FT_REG_NORM_OFF__M 0xF
3039#define FT_REG_NORM_OFF_INIT 0x2
3040
3041
3042
3043#define FT_ST1_RAM__A 0x1020000
3044
3045
3046
3047#define FT_ST2_RAM__A 0x1030000
3048
3049
3050
3051#define FT_ST3_RAM__A 0x1040000
3052
3053
3054
3055#define FT_ST5_RAM__A 0x1050000
3056
3057
3058
3059#define FT_ST6_RAM__A 0x1060000
3060
3061
3062
3063#define FT_ST8_RAM__A 0x1070000
3064
3065
3066
3067#define FT_ST9_RAM__A 0x1080000
3068
3069
3070
3071
3072
3073#define CP_SID 0x9
3074
3075
3076
3077
3078
3079#define CP_COMM_EXEC__A 0x1400000
3080#define CP_COMM_EXEC__W 3
3081#define CP_COMM_EXEC__M 0x7
3082#define CP_COMM_EXEC_CTL__B 0
3083#define CP_COMM_EXEC_CTL__W 3
3084#define CP_COMM_EXEC_CTL__M 0x7
3085#define CP_COMM_EXEC_CTL_STOP 0x0
3086#define CP_COMM_EXEC_CTL_ACTIVE 0x1
3087#define CP_COMM_EXEC_CTL_HOLD 0x2
3088#define CP_COMM_EXEC_CTL_STEP 0x3
3089#define CP_COMM_EXEC_CTL_BYPASS_STOP 0x4
3090#define CP_COMM_EXEC_CTL_BYPASS_HOLD 0x6
3091
3092#define CP_COMM_STATE__A 0x1400001
3093#define CP_COMM_STATE__W 16
3094#define CP_COMM_STATE__M 0xFFFF
3095#define CP_COMM_MB__A 0x1400002
3096#define CP_COMM_MB__W 16
3097#define CP_COMM_MB__M 0xFFFF
3098#define CP_COMM_SERVICE0__A 0x1400003
3099#define CP_COMM_SERVICE0__W 16
3100#define CP_COMM_SERVICE0__M 0xFFFF
3101#define CP_COMM_SERVICE1__A 0x1400004
3102#define CP_COMM_SERVICE1__W 16
3103#define CP_COMM_SERVICE1__M 0xFFFF
3104#define CP_COMM_INT_STA__A 0x1400007
3105#define CP_COMM_INT_STA__W 16
3106#define CP_COMM_INT_STA__M 0xFFFF
3107#define CP_COMM_INT_MSK__A 0x1400008
3108#define CP_COMM_INT_MSK__W 16
3109#define CP_COMM_INT_MSK__M 0xFFFF
3110
3111
3112
3113
3114
3115
3116#define CP_REG_COMM_EXEC__A 0x1410000
3117#define CP_REG_COMM_EXEC__W 3
3118#define CP_REG_COMM_EXEC__M 0x7
3119#define CP_REG_COMM_EXEC_CTL__B 0
3120#define CP_REG_COMM_EXEC_CTL__W 3
3121#define CP_REG_COMM_EXEC_CTL__M 0x7
3122#define CP_REG_COMM_EXEC_CTL_STOP 0x0
3123#define CP_REG_COMM_EXEC_CTL_ACTIVE 0x1
3124#define CP_REG_COMM_EXEC_CTL_HOLD 0x2
3125#define CP_REG_COMM_EXEC_CTL_STEP 0x3
3126
3127
3128#define CP_REG_COMM_MB__A 0x1410002
3129#define CP_REG_COMM_MB__W 3
3130#define CP_REG_COMM_MB__M 0x7
3131#define CP_REG_COMM_MB_CTR__B 0
3132#define CP_REG_COMM_MB_CTR__W 1
3133#define CP_REG_COMM_MB_CTR__M 0x1
3134#define CP_REG_COMM_MB_CTR_OFF 0x0
3135#define CP_REG_COMM_MB_CTR_ON 0x1
3136#define CP_REG_COMM_MB_OBS__B 1
3137#define CP_REG_COMM_MB_OBS__W 1
3138#define CP_REG_COMM_MB_OBS__M 0x2
3139#define CP_REG_COMM_MB_OBS_OFF 0x0
3140#define CP_REG_COMM_MB_OBS_ON 0x2
3141
3142#define CP_REG_COMM_SERVICE0__A 0x1410003
3143#define CP_REG_COMM_SERVICE0__W 10
3144#define CP_REG_COMM_SERVICE0__M 0x3FF
3145#define CP_REG_COMM_SERVICE0_CP__B 9
3146#define CP_REG_COMM_SERVICE0_CP__W 1
3147#define CP_REG_COMM_SERVICE0_CP__M 0x200
3148
3149#define CP_REG_COMM_SERVICE1__A 0x1410004
3150#define CP_REG_COMM_SERVICE1__W 11
3151#define CP_REG_COMM_SERVICE1__M 0x7FF
3152
3153#define CP_REG_COMM_INT_STA__A 0x1410007
3154#define CP_REG_COMM_INT_STA__W 2
3155#define CP_REG_COMM_INT_STA__M 0x3
3156#define CP_REG_COMM_INT_STA_NEW_MEAS__B 0
3157#define CP_REG_COMM_INT_STA_NEW_MEAS__W 1
3158#define CP_REG_COMM_INT_STA_NEW_MEAS__M 0x1
3159
3160
3161#define CP_REG_COMM_INT_MSK__A 0x1410008
3162#define CP_REG_COMM_INT_MSK__W 2
3163#define CP_REG_COMM_INT_MSK__M 0x3
3164#define CP_REG_COMM_INT_MSK_NEW_MEAS__B 0
3165#define CP_REG_COMM_INT_MSK_NEW_MEAS__W 1
3166#define CP_REG_COMM_INT_MSK_NEW_MEAS__M 0x1
3167
3168
3169#define CP_REG_MODE_2K__A 0x1410010
3170#define CP_REG_MODE_2K__W 1
3171#define CP_REG_MODE_2K__M 0x1
3172#define CP_REG_MODE_2K_INIT 0x0
3173
3174
3175#define CP_REG_INTERVAL__A 0x1410011
3176#define CP_REG_INTERVAL__W 4
3177#define CP_REG_INTERVAL__M 0xF
3178#define CP_REG_INTERVAL_INIT 0x5
3179
3180
3181#define CP_REG_SKIP_START0__A 0x1410012
3182#define CP_REG_SKIP_START0__W 13
3183#define CP_REG_SKIP_START0__M 0x1FFF
3184#define CP_REG_SKIP_START0_INIT 0x0
3185
3186
3187#define CP_REG_SKIP_STOP0__A 0x1410013
3188#define CP_REG_SKIP_STOP0__W 13
3189#define CP_REG_SKIP_STOP0__M 0x1FFF
3190#define CP_REG_SKIP_STOP0_INIT 0x0
3191
3192
3193#define CP_REG_SKIP_START1__A 0x1410014
3194#define CP_REG_SKIP_START1__W 13
3195#define CP_REG_SKIP_START1__M 0x1FFF
3196#define CP_REG_SKIP_START1_INIT 0x0
3197
3198
3199#define CP_REG_SKIP_STOP1__A 0x1410015
3200#define CP_REG_SKIP_STOP1__W 13
3201#define CP_REG_SKIP_STOP1__M 0x1FFF
3202#define CP_REG_SKIP_STOP1_INIT 0x0
3203
3204
3205#define CP_REG_SKIP_START2__A 0x1410016
3206#define CP_REG_SKIP_START2__W 13
3207#define CP_REG_SKIP_START2__M 0x1FFF
3208#define CP_REG_SKIP_START2_INIT 0x0
3209
3210
3211#define CP_REG_SKIP_STOP2__A 0x1410017
3212#define CP_REG_SKIP_STOP2__W 13
3213#define CP_REG_SKIP_STOP2__M 0x1FFF
3214#define CP_REG_SKIP_STOP2_INIT 0x0
3215
3216
3217#define CP_REG_SKIP_ENA__A 0x1410018
3218#define CP_REG_SKIP_ENA__W 3
3219#define CP_REG_SKIP_ENA__M 0x7
3220
3221#define CP_REG_SKIP_ENA_CPL__B 0
3222#define CP_REG_SKIP_ENA_CPL__W 1
3223#define CP_REG_SKIP_ENA_CPL__M 0x1
3224
3225#define CP_REG_SKIP_ENA_SPD__B 1
3226#define CP_REG_SKIP_ENA_SPD__W 1
3227#define CP_REG_SKIP_ENA_SPD__M 0x2
3228
3229#define CP_REG_SKIP_ENA_CPD__B 2
3230#define CP_REG_SKIP_ENA_CPD__W 1
3231#define CP_REG_SKIP_ENA_CPD__M 0x4
3232#define CP_REG_SKIP_ENA_INIT 0x0
3233
3234
3235#define CP_REG_BR_MODE_MIX__A 0x1410020
3236#define CP_REG_BR_MODE_MIX__W 1
3237#define CP_REG_BR_MODE_MIX__M 0x1
3238#define CP_REG_BR_MODE_MIX_INIT 0x0
3239
3240
3241#define CP_REG_BR_SMB_NR__A 0x1410021
3242#define CP_REG_BR_SMB_NR__W 3
3243#define CP_REG_BR_SMB_NR__M 0x7
3244
3245#define CP_REG_BR_SMB_NR_SMB__B 0
3246#define CP_REG_BR_SMB_NR_SMB__W 2
3247#define CP_REG_BR_SMB_NR_SMB__M 0x3
3248
3249#define CP_REG_BR_SMB_NR_VAL__B 2
3250#define CP_REG_BR_SMB_NR_VAL__W 1
3251#define CP_REG_BR_SMB_NR_VAL__M 0x4
3252#define CP_REG_BR_SMB_NR_INIT 0x0
3253
3254
3255#define CP_REG_BR_CP_SMB_NR__A 0x1410022
3256#define CP_REG_BR_CP_SMB_NR__W 2
3257#define CP_REG_BR_CP_SMB_NR__M 0x3
3258#define CP_REG_BR_CP_SMB_NR_INIT 0x0
3259
3260
3261#define CP_REG_BR_SPL_OFFSET__A 0x1410023
3262#define CP_REG_BR_SPL_OFFSET__W 3
3263#define CP_REG_BR_SPL_OFFSET__M 0x7
3264#define CP_REG_BR_SPL_OFFSET_INIT 0x0
3265
3266
3267#define CP_REG_BR_STR_DEL__A 0x1410024
3268#define CP_REG_BR_STR_DEL__W 10
3269#define CP_REG_BR_STR_DEL__M 0x3FF
3270#define CP_REG_BR_STR_DEL_INIT 0xA
3271
3272
3273#define CP_REG_RT_ANG_INC0__A 0x1410030
3274#define CP_REG_RT_ANG_INC0__W 16
3275#define CP_REG_RT_ANG_INC0__M 0xFFFF
3276#define CP_REG_RT_ANG_INC0_INIT 0x0
3277
3278
3279#define CP_REG_RT_ANG_INC1__A 0x1410031
3280#define CP_REG_RT_ANG_INC1__W 8
3281#define CP_REG_RT_ANG_INC1__M 0xFF
3282#define CP_REG_RT_ANG_INC1_INIT 0x0
3283
3284
3285#define CP_REG_RT_DETECT_ENA__A 0x1410032
3286#define CP_REG_RT_DETECT_ENA__W 2
3287#define CP_REG_RT_DETECT_ENA__M 0x3
3288
3289#define CP_REG_RT_DETECT_ENA_SCATTERED__B 0
3290#define CP_REG_RT_DETECT_ENA_SCATTERED__W 1
3291#define CP_REG_RT_DETECT_ENA_SCATTERED__M 0x1
3292
3293#define CP_REG_RT_DETECT_ENA_CONTINUOUS__B 1
3294#define CP_REG_RT_DETECT_ENA_CONTINUOUS__W 1
3295#define CP_REG_RT_DETECT_ENA_CONTINUOUS__M 0x2
3296#define CP_REG_RT_DETECT_ENA_INIT 0x0
3297
3298
3299#define CP_REG_RT_DETECT_TRH__A 0x1410033
3300#define CP_REG_RT_DETECT_TRH__W 2
3301#define CP_REG_RT_DETECT_TRH__M 0x3
3302#define CP_REG_RT_DETECT_TRH_INIT 0x3
3303
3304
3305#define CP_REG_RT_SPD_RELIABLE__A 0x1410034
3306#define CP_REG_RT_SPD_RELIABLE__W 3
3307#define CP_REG_RT_SPD_RELIABLE__M 0x7
3308#define CP_REG_RT_SPD_RELIABLE_INIT 0x0
3309
3310
3311#define CP_REG_RT_SPD_DIRECTION__A 0x1410035
3312#define CP_REG_RT_SPD_DIRECTION__W 1
3313#define CP_REG_RT_SPD_DIRECTION__M 0x1
3314#define CP_REG_RT_SPD_DIRECTION_INIT 0x0
3315
3316
3317#define CP_REG_RT_SPD_MOD__A 0x1410036
3318#define CP_REG_RT_SPD_MOD__W 2
3319#define CP_REG_RT_SPD_MOD__M 0x3
3320#define CP_REG_RT_SPD_MOD_INIT 0x0
3321
3322
3323#define CP_REG_RT_SPD_SMB__A 0x1410037
3324#define CP_REG_RT_SPD_SMB__W 2
3325#define CP_REG_RT_SPD_SMB__M 0x3
3326#define CP_REG_RT_SPD_SMB_INIT 0x0
3327
3328
3329#define CP_REG_RT_CPD_MODE__A 0x1410038
3330#define CP_REG_RT_CPD_MODE__W 3
3331#define CP_REG_RT_CPD_MODE__M 0x7
3332
3333#define CP_REG_RT_CPD_MODE_MOD3__B 0
3334#define CP_REG_RT_CPD_MODE_MOD3__W 2
3335#define CP_REG_RT_CPD_MODE_MOD3__M 0x3
3336
3337#define CP_REG_RT_CPD_MODE_ADD__B 2
3338#define CP_REG_RT_CPD_MODE_ADD__W 1
3339#define CP_REG_RT_CPD_MODE_ADD__M 0x4
3340#define CP_REG_RT_CPD_MODE_INIT 0x0
3341
3342
3343#define CP_REG_RT_CPD_RELIABLE__A 0x1410039
3344#define CP_REG_RT_CPD_RELIABLE__W 3
3345#define CP_REG_RT_CPD_RELIABLE__M 0x7
3346#define CP_REG_RT_CPD_RELIABLE_INIT 0x0
3347
3348
3349#define CP_REG_RT_CPD_BIN__A 0x141003A
3350#define CP_REG_RT_CPD_BIN__W 5
3351#define CP_REG_RT_CPD_BIN__M 0x1F
3352#define CP_REG_RT_CPD_BIN_INIT 0x0
3353
3354
3355#define CP_REG_RT_CPD_MAX__A 0x141003B
3356#define CP_REG_RT_CPD_MAX__W 4
3357#define CP_REG_RT_CPD_MAX__M 0xF
3358#define CP_REG_RT_CPD_MAX_INIT 0x0
3359
3360
3361#define CP_REG_RT_SUPR_VAL__A 0x141003C
3362#define CP_REG_RT_SUPR_VAL__W 2
3363#define CP_REG_RT_SUPR_VAL__M 0x3
3364
3365#define CP_REG_RT_SUPR_VAL_CE__B 0
3366#define CP_REG_RT_SUPR_VAL_CE__W 1
3367#define CP_REG_RT_SUPR_VAL_CE__M 0x1
3368
3369#define CP_REG_RT_SUPR_VAL_DL__B 1
3370#define CP_REG_RT_SUPR_VAL_DL__W 1
3371#define CP_REG_RT_SUPR_VAL_DL__M 0x2
3372#define CP_REG_RT_SUPR_VAL_INIT 0x0
3373
3374
3375#define CP_REG_RT_EXP_AVE__A 0x141003D
3376#define CP_REG_RT_EXP_AVE__W 5
3377#define CP_REG_RT_EXP_AVE__M 0x1F
3378#define CP_REG_RT_EXP_AVE_INIT 0x0
3379
3380
3381#define CP_REG_RT_EXP_MARG__A 0x141003E
3382#define CP_REG_RT_EXP_MARG__W 5
3383#define CP_REG_RT_EXP_MARG__M 0x1F
3384#define CP_REG_RT_EXP_MARG_INIT 0x0
3385
3386
3387#define CP_REG_AC_NEXP_OFFS__A 0x1410040
3388#define CP_REG_AC_NEXP_OFFS__W 8
3389#define CP_REG_AC_NEXP_OFFS__M 0xFF
3390#define CP_REG_AC_NEXP_OFFS_INIT 0x0
3391
3392
3393#define CP_REG_AC_AVER_POW__A 0x1410041
3394#define CP_REG_AC_AVER_POW__W 8
3395#define CP_REG_AC_AVER_POW__M 0xFF
3396#define CP_REG_AC_AVER_POW_INIT 0x5F
3397
3398
3399#define CP_REG_AC_MAX_POW__A 0x1410042
3400#define CP_REG_AC_MAX_POW__W 8
3401#define CP_REG_AC_MAX_POW__M 0xFF
3402#define CP_REG_AC_MAX_POW_INIT 0x7A
3403
3404
3405#define CP_REG_AC_WEIGHT_MAN__A 0x1410043
3406#define CP_REG_AC_WEIGHT_MAN__W 6
3407#define CP_REG_AC_WEIGHT_MAN__M 0x3F
3408#define CP_REG_AC_WEIGHT_MAN_INIT 0x31
3409
3410
3411#define CP_REG_AC_WEIGHT_EXP__A 0x1410044
3412#define CP_REG_AC_WEIGHT_EXP__W 5
3413#define CP_REG_AC_WEIGHT_EXP__M 0x1F
3414#define CP_REG_AC_WEIGHT_EXP_INIT 0x10
3415
3416
3417#define CP_REG_AC_GAIN_MAN__A 0x1410045
3418#define CP_REG_AC_GAIN_MAN__W 16
3419#define CP_REG_AC_GAIN_MAN__M 0xFFFF
3420#define CP_REG_AC_GAIN_MAN_INIT 0x0
3421
3422
3423#define CP_REG_AC_GAIN_EXP__A 0x1410046
3424#define CP_REG_AC_GAIN_EXP__W 5
3425#define CP_REG_AC_GAIN_EXP__M 0x1F
3426#define CP_REG_AC_GAIN_EXP_INIT 0x0
3427
3428
3429#define CP_REG_AC_AMP_MODE__A 0x1410047
3430#define CP_REG_AC_AMP_MODE__W 2
3431#define CP_REG_AC_AMP_MODE__M 0x3
3432#define CP_REG_AC_AMP_MODE_NEW 0x0
3433#define CP_REG_AC_AMP_MODE_OLD 0x1
3434#define CP_REG_AC_AMP_MODE_FIXED 0x2
3435#define CP_REG_AC_AMP_MODE_INIT 0x2
3436
3437
3438#define CP_REG_AC_AMP_FIX__A 0x1410048
3439#define CP_REG_AC_AMP_FIX__W 14
3440#define CP_REG_AC_AMP_FIX__M 0x3FFF
3441#define CP_REG_AC_AMP_FIX_INIT 0x1FF
3442
3443
3444#define CP_REG_AC_AMP_READ__A 0x1410049
3445#define CP_REG_AC_AMP_READ__W 14
3446#define CP_REG_AC_AMP_READ__M 0x3FFF
3447#define CP_REG_AC_AMP_READ_INIT 0x0
3448
3449
3450#define CP_REG_AC_ANG_MODE__A 0x141004A
3451#define CP_REG_AC_ANG_MODE__W 2
3452#define CP_REG_AC_ANG_MODE__M 0x3
3453#define CP_REG_AC_ANG_MODE_NEW 0x0
3454#define CP_REG_AC_ANG_MODE_OLD 0x1
3455#define CP_REG_AC_ANG_MODE_NO_INT 0x2
3456#define CP_REG_AC_ANG_MODE_OFFSET 0x3
3457#define CP_REG_AC_ANG_MODE_INIT 0x3
3458
3459
3460#define CP_REG_AC_ANG_OFFS__A 0x141004B
3461#define CP_REG_AC_ANG_OFFS__W 14
3462#define CP_REG_AC_ANG_OFFS__M 0x3FFF
3463#define CP_REG_AC_ANG_OFFS_INIT 0x0
3464
3465
3466#define CP_REG_AC_ANG_READ__A 0x141004C
3467#define CP_REG_AC_ANG_READ__W 16
3468#define CP_REG_AC_ANG_READ__M 0xFFFF
3469#define CP_REG_AC_ANG_READ_INIT 0x0
3470
3471
3472#define CP_REG_DL_MB_WR_ADDR__A 0x1410050
3473#define CP_REG_DL_MB_WR_ADDR__W 15
3474#define CP_REG_DL_MB_WR_ADDR__M 0x7FFF
3475#define CP_REG_DL_MB_WR_ADDR_INIT 0x0
3476
3477
3478#define CP_REG_DL_MB_WR_CTR__A 0x1410051
3479#define CP_REG_DL_MB_WR_CTR__W 5
3480#define CP_REG_DL_MB_WR_CTR__M 0x1F
3481
3482#define CP_REG_DL_MB_WR_CTR_WORD__B 2
3483#define CP_REG_DL_MB_WR_CTR_WORD__W 3
3484#define CP_REG_DL_MB_WR_CTR_WORD__M 0x1C
3485
3486#define CP_REG_DL_MB_WR_CTR_OBS__B 1
3487#define CP_REG_DL_MB_WR_CTR_OBS__W 1
3488#define CP_REG_DL_MB_WR_CTR_OBS__M 0x2
3489
3490#define CP_REG_DL_MB_WR_CTR_CTR__B 0
3491#define CP_REG_DL_MB_WR_CTR_CTR__W 1
3492#define CP_REG_DL_MB_WR_CTR_CTR__M 0x1
3493#define CP_REG_DL_MB_WR_CTR_INIT 0x0
3494
3495
3496#define CP_REG_DL_MB_RD_ADDR__A 0x1410052
3497#define CP_REG_DL_MB_RD_ADDR__W 15
3498#define CP_REG_DL_MB_RD_ADDR__M 0x7FFF
3499#define CP_REG_DL_MB_RD_ADDR_INIT 0x0
3500
3501
3502#define CP_REG_DL_MB_RD_CTR__A 0x1410053
3503#define CP_REG_DL_MB_RD_CTR__W 11
3504#define CP_REG_DL_MB_RD_CTR__M 0x7FF
3505
3506#define CP_REG_DL_MB_RD_CTR_TEST__B 10
3507#define CP_REG_DL_MB_RD_CTR_TEST__W 1
3508#define CP_REG_DL_MB_RD_CTR_TEST__M 0x400
3509
3510#define CP_REG_DL_MB_RD_CTR_OFFSET__B 8
3511#define CP_REG_DL_MB_RD_CTR_OFFSET__W 2
3512#define CP_REG_DL_MB_RD_CTR_OFFSET__M 0x300
3513
3514#define CP_REG_DL_MB_RD_CTR_VALID__B 5
3515#define CP_REG_DL_MB_RD_CTR_VALID__W 3
3516#define CP_REG_DL_MB_RD_CTR_VALID__M 0xE0
3517
3518#define CP_REG_DL_MB_RD_CTR_WORD__B 2
3519#define CP_REG_DL_MB_RD_CTR_WORD__W 3
3520#define CP_REG_DL_MB_RD_CTR_WORD__M 0x1C
3521
3522#define CP_REG_DL_MB_RD_CTR_OBS__B 1
3523#define CP_REG_DL_MB_RD_CTR_OBS__W 1
3524#define CP_REG_DL_MB_RD_CTR_OBS__M 0x2
3525
3526#define CP_REG_DL_MB_RD_CTR_CTR__B 0
3527#define CP_REG_DL_MB_RD_CTR_CTR__W 1
3528#define CP_REG_DL_MB_RD_CTR_CTR__M 0x1
3529#define CP_REG_DL_MB_RD_CTR_INIT 0x0
3530
3531
3532
3533#define CP_BR_BUF_RAM__A 0x1420000
3534
3535
3536
3537#define CP_BR_CPL_RAM__A 0x1430000
3538
3539
3540
3541#define CP_PB_DL0_RAM__A 0x1440000
3542
3543
3544
3545#define CP_PB_DL1_RAM__A 0x1450000
3546
3547
3548
3549#define CP_PB_DL2_RAM__A 0x1460000
3550
3551
3552
3553
3554
3555#define CE_SID 0xA
3556
3557
3558
3559
3560
3561#define CE_COMM_EXEC__A 0x1800000
3562#define CE_COMM_EXEC__W 3
3563#define CE_COMM_EXEC__M 0x7
3564#define CE_COMM_EXEC_CTL__B 0
3565#define CE_COMM_EXEC_CTL__W 3
3566#define CE_COMM_EXEC_CTL__M 0x7
3567#define CE_COMM_EXEC_CTL_STOP 0x0
3568#define CE_COMM_EXEC_CTL_ACTIVE 0x1
3569#define CE_COMM_EXEC_CTL_HOLD 0x2
3570#define CE_COMM_EXEC_CTL_STEP 0x3
3571#define CE_COMM_EXEC_CTL_BYPASS_STOP 0x4
3572#define CE_COMM_EXEC_CTL_BYPASS_HOLD 0x6
3573
3574#define CE_COMM_STATE__A 0x1800001
3575#define CE_COMM_STATE__W 16
3576#define CE_COMM_STATE__M 0xFFFF
3577#define CE_COMM_MB__A 0x1800002
3578#define CE_COMM_MB__W 16
3579#define CE_COMM_MB__M 0xFFFF
3580#define CE_COMM_SERVICE0__A 0x1800003
3581#define CE_COMM_SERVICE0__W 16
3582#define CE_COMM_SERVICE0__M 0xFFFF
3583#define CE_COMM_SERVICE1__A 0x1800004
3584#define CE_COMM_SERVICE1__W 16
3585#define CE_COMM_SERVICE1__M 0xFFFF
3586#define CE_COMM_INT_STA__A 0x1800007
3587#define CE_COMM_INT_STA__W 16
3588#define CE_COMM_INT_STA__M 0xFFFF
3589#define CE_COMM_INT_MSK__A 0x1800008
3590#define CE_COMM_INT_MSK__W 16
3591#define CE_COMM_INT_MSK__M 0xFFFF
3592
3593
3594
3595
3596
3597
3598#define CE_REG_COMM_EXEC__A 0x1810000
3599#define CE_REG_COMM_EXEC__W 3
3600#define CE_REG_COMM_EXEC__M 0x7
3601#define CE_REG_COMM_EXEC_CTL__B 0
3602#define CE_REG_COMM_EXEC_CTL__W 3
3603#define CE_REG_COMM_EXEC_CTL__M 0x7
3604#define CE_REG_COMM_EXEC_CTL_STOP 0x0
3605#define CE_REG_COMM_EXEC_CTL_ACTIVE 0x1
3606#define CE_REG_COMM_EXEC_CTL_HOLD 0x2
3607#define CE_REG_COMM_EXEC_CTL_STEP 0x3
3608
3609
3610#define CE_REG_COMM_MB__A 0x1810002
3611#define CE_REG_COMM_MB__W 4
3612#define CE_REG_COMM_MB__M 0xF
3613#define CE_REG_COMM_MB_CTR__B 0
3614#define CE_REG_COMM_MB_CTR__W 1
3615#define CE_REG_COMM_MB_CTR__M 0x1
3616#define CE_REG_COMM_MB_CTR_OFF 0x0
3617#define CE_REG_COMM_MB_CTR_ON 0x1
3618#define CE_REG_COMM_MB_OBS__B 1
3619#define CE_REG_COMM_MB_OBS__W 1
3620#define CE_REG_COMM_MB_OBS__M 0x2
3621#define CE_REG_COMM_MB_OBS_OFF 0x0
3622#define CE_REG_COMM_MB_OBS_ON 0x2
3623#define CE_REG_COMM_MB_OBS_SEL__B 2
3624#define CE_REG_COMM_MB_OBS_SEL__W 2
3625#define CE_REG_COMM_MB_OBS_SEL__M 0xC
3626#define CE_REG_COMM_MB_OBS_SEL_FI 0x0
3627#define CE_REG_COMM_MB_OBS_SEL_TP 0x4
3628#define CE_REG_COMM_MB_OBS_SEL_TI 0x8
3629#define CE_REG_COMM_MB_OBS_SEL_FR 0x8
3630
3631#define CE_REG_COMM_SERVICE0__A 0x1810003
3632#define CE_REG_COMM_SERVICE0__W 10
3633#define CE_REG_COMM_SERVICE0__M 0x3FF
3634#define CE_REG_COMM_SERVICE0_FT__B 8
3635#define CE_REG_COMM_SERVICE0_FT__W 1
3636#define CE_REG_COMM_SERVICE0_FT__M 0x100
3637
3638#define CE_REG_COMM_SERVICE1__A 0x1810004
3639#define CE_REG_COMM_SERVICE1__W 11
3640#define CE_REG_COMM_SERVICE1__M 0x7FF
3641
3642#define CE_REG_COMM_INT_STA__A 0x1810007
3643#define CE_REG_COMM_INT_STA__W 3
3644#define CE_REG_COMM_INT_STA__M 0x7
3645#define CE_REG_COMM_INT_STA_CE_PE__B 0
3646#define CE_REG_COMM_INT_STA_CE_PE__W 1
3647#define CE_REG_COMM_INT_STA_CE_PE__M 0x1
3648#define CE_REG_COMM_INT_STA_CE_IR__B 1
3649#define CE_REG_COMM_INT_STA_CE_IR__W 1
3650#define CE_REG_COMM_INT_STA_CE_IR__M 0x2
3651#define CE_REG_COMM_INT_STA_CE_FI__B 2
3652#define CE_REG_COMM_INT_STA_CE_FI__W 1
3653#define CE_REG_COMM_INT_STA_CE_FI__M 0x4
3654
3655
3656#define CE_REG_COMM_INT_MSK__A 0x1810008
3657#define CE_REG_COMM_INT_MSK__W 3
3658#define CE_REG_COMM_INT_MSK__M 0x7
3659#define CE_REG_COMM_INT_MSK_CE_PE__B 0
3660#define CE_REG_COMM_INT_MSK_CE_PE__W 1
3661#define CE_REG_COMM_INT_MSK_CE_PE__M 0x1
3662#define CE_REG_COMM_INT_MSK_CE_IR__B 1
3663#define CE_REG_COMM_INT_MSK_CE_IR__W 1
3664#define CE_REG_COMM_INT_MSK_CE_IR__M 0x2
3665#define CE_REG_COMM_INT_MSK_CE_FI__B 2
3666#define CE_REG_COMM_INT_MSK_CE_FI__W 1
3667#define CE_REG_COMM_INT_MSK_CE_FI__M 0x4
3668
3669
3670#define CE_REG_2K__A 0x1810010
3671#define CE_REG_2K__W 1
3672#define CE_REG_2K__M 0x1
3673#define CE_REG_2K_INIT 0x0
3674
3675
3676#define CE_REG_TAPSET__A 0x1810011
3677#define CE_REG_TAPSET__W 2
3678#define CE_REG_TAPSET__M 0x3
3679
3680
3681
3682#define CE_REG_TAPSET_MOTION_INIT 0x0
3683
3684#define CE_REG_TAPSET_MOTION_NO 0x0
3685
3686#define CE_REG_TAPSET_MOTION_LOW 0x1
3687
3688#define CE_REG_TAPSET_MOTION_HIGH 0x2
3689
3690#define CE_REG_TAPSET_MOTION_UNDEFINED 0x3
3691
3692
3693#define CE_REG_AVG_POW__A 0x1810012
3694#define CE_REG_AVG_POW__W 8
3695#define CE_REG_AVG_POW__M 0xFF
3696#define CE_REG_AVG_POW_INIT 0x0
3697
3698
3699#define CE_REG_MAX_POW__A 0x1810013
3700#define CE_REG_MAX_POW__W 8
3701#define CE_REG_MAX_POW__M 0xFF
3702#define CE_REG_MAX_POW_INIT 0x0
3703
3704
3705#define CE_REG_ATT__A 0x1810014
3706#define CE_REG_ATT__W 8
3707#define CE_REG_ATT__M 0xFF
3708#define CE_REG_ATT_INIT 0x0
3709
3710
3711#define CE_REG_NRED__A 0x1810015
3712#define CE_REG_NRED__W 6
3713#define CE_REG_NRED__M 0x3F
3714#define CE_REG_NRED_INIT 0x0
3715
3716
3717#define CE_REG_PU_SIGN__A 0x1810020
3718#define CE_REG_PU_SIGN__W 1
3719#define CE_REG_PU_SIGN__M 0x1
3720#define CE_REG_PU_SIGN_INIT 0x0
3721
3722
3723#define CE_REG_PU_MIX__A 0x1810021
3724#define CE_REG_PU_MIX__W 7
3725#define CE_REG_PU_MIX__M 0x7F
3726#define CE_REG_PU_MIX_INIT 0x0
3727
3728
3729#define CE_REG_PB_PILOT_REQ__A 0x1810030
3730#define CE_REG_PB_PILOT_REQ__W 15
3731#define CE_REG_PB_PILOT_REQ__M 0x7FFF
3732#define CE_REG_PB_PILOT_REQ_INIT 0x0
3733#define CE_REG_PB_PILOT_REQ_BUFFER_INDEX__B 12
3734#define CE_REG_PB_PILOT_REQ_BUFFER_INDEX__W 3
3735#define CE_REG_PB_PILOT_REQ_BUFFER_INDEX__M 0x7000
3736#define CE_REG_PB_PILOT_REQ_PILOT_ADR__B 0
3737#define CE_REG_PB_PILOT_REQ_PILOT_ADR__W 12
3738#define CE_REG_PB_PILOT_REQ_PILOT_ADR__M 0xFFF
3739
3740
3741#define CE_REG_PB_PILOT_REQ_VALID__A 0x1810031
3742#define CE_REG_PB_PILOT_REQ_VALID__W 1
3743#define CE_REG_PB_PILOT_REQ_VALID__M 0x1
3744#define CE_REG_PB_PILOT_REQ_VALID_INIT 0x0
3745
3746
3747#define CE_REG_PB_FREEZE__A 0x1810032
3748#define CE_REG_PB_FREEZE__W 1
3749#define CE_REG_PB_FREEZE__M 0x1
3750#define CE_REG_PB_FREEZE_INIT 0x0
3751
3752
3753#define CE_REG_PB_PILOT_EXP__A 0x1810038
3754#define CE_REG_PB_PILOT_EXP__W 4
3755#define CE_REG_PB_PILOT_EXP__M 0xF
3756#define CE_REG_PB_PILOT_EXP_INIT 0x0
3757
3758
3759#define CE_REG_PB_PILOT_REAL__A 0x1810039
3760#define CE_REG_PB_PILOT_REAL__W 10
3761#define CE_REG_PB_PILOT_REAL__M 0x3FF
3762#define CE_REG_PB_PILOT_REAL_INIT 0x0
3763
3764
3765#define CE_REG_PB_PILOT_IMAG__A 0x181003A
3766#define CE_REG_PB_PILOT_IMAG__W 10
3767#define CE_REG_PB_PILOT_IMAG__M 0x3FF
3768#define CE_REG_PB_PILOT_IMAG_INIT 0x0
3769
3770
3771#define CE_REG_PB_SMBNR__A 0x181003B
3772#define CE_REG_PB_SMBNR__W 5
3773#define CE_REG_PB_SMBNR__M 0x1F
3774#define CE_REG_PB_SMBNR_INIT 0x0
3775
3776
3777#define CE_REG_NE_PILOT_REQ__A 0x1810040
3778#define CE_REG_NE_PILOT_REQ__W 12
3779#define CE_REG_NE_PILOT_REQ__M 0xFFF
3780#define CE_REG_NE_PILOT_REQ_INIT 0x0
3781
3782
3783#define CE_REG_NE_PILOT_REQ_VALID__A 0x1810041
3784#define CE_REG_NE_PILOT_REQ_VALID__W 2
3785#define CE_REG_NE_PILOT_REQ_VALID__M 0x3
3786#define CE_REG_NE_PILOT_REQ_VALID_INIT 0x0
3787#define CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__B 1
3788#define CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__W 1
3789#define CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__M 0x2
3790#define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__B 0
3791#define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__W 1
3792#define CE_REG_NE_PILOT_REQ_VALID_READ_VALID__M 0x1
3793
3794
3795#define CE_REG_NE_PILOT_DATA__A 0x1810042
3796#define CE_REG_NE_PILOT_DATA__W 10
3797#define CE_REG_NE_PILOT_DATA__M 0x3FF
3798#define CE_REG_NE_PILOT_DATA_INIT 0x0
3799
3800
3801#define CE_REG_NE_ERR_SELECT__A 0x1810043
3802#define CE_REG_NE_ERR_SELECT__W 3
3803#define CE_REG_NE_ERR_SELECT__M 0x7
3804#define CE_REG_NE_ERR_SELECT_INIT 0x0
3805
3806#define CE_REG_NE_ERR_SELECT_RESET_RAM__B 2
3807#define CE_REG_NE_ERR_SELECT_RESET_RAM__W 1
3808#define CE_REG_NE_ERR_SELECT_RESET_RAM__M 0x4
3809
3810#define CE_REG_NE_ERR_SELECT_FD_ENABLE__B 1
3811#define CE_REG_NE_ERR_SELECT_FD_ENABLE__W 1
3812#define CE_REG_NE_ERR_SELECT_FD_ENABLE__M 0x2
3813
3814#define CE_REG_NE_ERR_SELECT_TD_ENABLE__B 0
3815#define CE_REG_NE_ERR_SELECT_TD_ENABLE__W 1
3816#define CE_REG_NE_ERR_SELECT_TD_ENABLE__M 0x1
3817
3818
3819#define CE_REG_NE_TD_CAL__A 0x1810044
3820#define CE_REG_NE_TD_CAL__W 9
3821#define CE_REG_NE_TD_CAL__M 0x1FF
3822#define CE_REG_NE_TD_CAL_INIT 0x0
3823
3824
3825#define CE_REG_NE_FD_CAL__A 0x1810045
3826#define CE_REG_NE_FD_CAL__W 9
3827#define CE_REG_NE_FD_CAL__M 0x1FF
3828#define CE_REG_NE_FD_CAL_INIT 0x0
3829
3830
3831#define CE_REG_NE_MIXAVG__A 0x1810046
3832#define CE_REG_NE_MIXAVG__W 3
3833#define CE_REG_NE_MIXAVG__M 0x7
3834#define CE_REG_NE_MIXAVG_INIT 0x0
3835
3836
3837#define CE_REG_NE_NUPD_OFS__A 0x1810047
3838#define CE_REG_NE_NUPD_OFS__W 7
3839#define CE_REG_NE_NUPD_OFS__M 0x7F
3840#define CE_REG_NE_NUPD_OFS_INIT 0x0
3841
3842
3843#define CE_REG_NE_TD_POW__A 0x1810048
3844#define CE_REG_NE_TD_POW__W 15
3845#define CE_REG_NE_TD_POW__M 0x7FFF
3846#define CE_REG_NE_TD_POW_INIT 0x0
3847
3848#define CE_REG_NE_TD_POW_EXPONENT__B 10
3849#define CE_REG_NE_TD_POW_EXPONENT__W 5
3850#define CE_REG_NE_TD_POW_EXPONENT__M 0x7C00
3851
3852#define CE_REG_NE_TD_POW_MANTISSA__B 0
3853#define CE_REG_NE_TD_POW_MANTISSA__W 10
3854#define CE_REG_NE_TD_POW_MANTISSA__M 0x3FF
3855
3856
3857#define CE_REG_NE_FD_POW__A 0x1810049
3858#define CE_REG_NE_FD_POW__W 15
3859#define CE_REG_NE_FD_POW__M 0x7FFF
3860#define CE_REG_NE_FD_POW_INIT 0x0
3861
3862#define CE_REG_NE_FD_POW_EXPONENT__B 10
3863#define CE_REG_NE_FD_POW_EXPONENT__W 5
3864#define CE_REG_NE_FD_POW_EXPONENT__M 0x7C00
3865
3866#define CE_REG_NE_FD_POW_MANTISSA__B 0
3867#define CE_REG_NE_FD_POW_MANTISSA__W 10
3868#define CE_REG_NE_FD_POW_MANTISSA__M 0x3FF
3869
3870
3871#define CE_REG_NE_NEXP_AVG__A 0x181004A
3872#define CE_REG_NE_NEXP_AVG__W 8
3873#define CE_REG_NE_NEXP_AVG__M 0xFF
3874#define CE_REG_NE_NEXP_AVG_INIT 0x0
3875
3876
3877#define CE_REG_NE_OFFSET__A 0x181004B
3878#define CE_REG_NE_OFFSET__W 9
3879#define CE_REG_NE_OFFSET__M 0x1FF
3880#define CE_REG_NE_OFFSET_INIT 0x0
3881
3882
3883#define CE_REG_PE_NEXP_OFFS__A 0x1810050
3884#define CE_REG_PE_NEXP_OFFS__W 8
3885#define CE_REG_PE_NEXP_OFFS__M 0xFF
3886#define CE_REG_PE_NEXP_OFFS_INIT 0x0
3887
3888
3889#define CE_REG_PE_TIMESHIFT__A 0x1810051
3890#define CE_REG_PE_TIMESHIFT__W 14
3891#define CE_REG_PE_TIMESHIFT__M 0x3FFF
3892#define CE_REG_PE_TIMESHIFT_INIT 0x0
3893
3894
3895#define CE_REG_PE_DIF_REAL_L__A 0x1810052
3896#define CE_REG_PE_DIF_REAL_L__W 16
3897#define CE_REG_PE_DIF_REAL_L__M 0xFFFF
3898#define CE_REG_PE_DIF_REAL_L_INIT 0x0
3899
3900
3901#define CE_REG_PE_DIF_IMAG_L__A 0x1810053
3902#define CE_REG_PE_DIF_IMAG_L__W 16
3903#define CE_REG_PE_DIF_IMAG_L__M 0xFFFF
3904#define CE_REG_PE_DIF_IMAG_L_INIT 0x0
3905
3906
3907#define CE_REG_PE_DIF_REAL_R__A 0x1810054
3908#define CE_REG_PE_DIF_REAL_R__W 16
3909#define CE_REG_PE_DIF_REAL_R__M 0xFFFF
3910#define CE_REG_PE_DIF_REAL_R_INIT 0x0
3911
3912
3913#define CE_REG_PE_DIF_IMAG_R__A 0x1810055
3914#define CE_REG_PE_DIF_IMAG_R__W 16
3915#define CE_REG_PE_DIF_IMAG_R__M 0xFFFF
3916#define CE_REG_PE_DIF_IMAG_R_INIT 0x0
3917
3918
3919#define CE_REG_PE_ABS_REAL_L__A 0x1810056
3920#define CE_REG_PE_ABS_REAL_L__W 16
3921#define CE_REG_PE_ABS_REAL_L__M 0xFFFF
3922#define CE_REG_PE_ABS_REAL_L_INIT 0x0
3923
3924
3925#define CE_REG_PE_ABS_IMAG_L__A 0x1810057
3926#define CE_REG_PE_ABS_IMAG_L__W 16
3927#define CE_REG_PE_ABS_IMAG_L__M 0xFFFF
3928#define CE_REG_PE_ABS_IMAG_L_INIT 0x0
3929
3930
3931#define CE_REG_PE_ABS_REAL_R__A 0x1810058
3932#define CE_REG_PE_ABS_REAL_R__W 16
3933#define CE_REG_PE_ABS_REAL_R__M 0xFFFF
3934#define CE_REG_PE_ABS_REAL_R_INIT 0x0
3935
3936
3937#define CE_REG_PE_ABS_IMAG_R__A 0x1810059
3938#define CE_REG_PE_ABS_IMAG_R__W 16
3939#define CE_REG_PE_ABS_IMAG_R__M 0xFFFF
3940#define CE_REG_PE_ABS_IMAG_R_INIT 0x0
3941
3942
3943#define CE_REG_PE_ABS_EXP_L__A 0x181005A
3944#define CE_REG_PE_ABS_EXP_L__W 5
3945#define CE_REG_PE_ABS_EXP_L__M 0x1F
3946#define CE_REG_PE_ABS_EXP_L_INIT 0x0
3947
3948
3949#define CE_REG_PE_ABS_EXP_R__A 0x181005B
3950#define CE_REG_PE_ABS_EXP_R__W 5
3951#define CE_REG_PE_ABS_EXP_R__M 0x1F
3952#define CE_REG_PE_ABS_EXP_R_INIT 0x0
3953
3954
3955#define CE_REG_TP_UPDATE_MODE__A 0x1810060
3956#define CE_REG_TP_UPDATE_MODE__W 1
3957#define CE_REG_TP_UPDATE_MODE__M 0x1
3958#define CE_REG_TP_UPDATE_MODE_INIT 0x0
3959
3960
3961#define CE_REG_TP_LMS_TAP_ON__A 0x1810061
3962#define CE_REG_TP_LMS_TAP_ON__W 1
3963#define CE_REG_TP_LMS_TAP_ON__M 0x1
3964
3965#define CE_REG_TP_A0_TAP_NEW__A 0x1810064
3966#define CE_REG_TP_A0_TAP_NEW__W 10
3967#define CE_REG_TP_A0_TAP_NEW__M 0x3FF
3968
3969#define CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065
3970#define CE_REG_TP_A0_TAP_NEW_VALID__W 1
3971#define CE_REG_TP_A0_TAP_NEW_VALID__M 0x1
3972
3973#define CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066
3974#define CE_REG_TP_A0_MU_LMS_STEP__W 5
3975#define CE_REG_TP_A0_MU_LMS_STEP__M 0x1F
3976
3977#define CE_REG_TP_A0_TAP_CURR__A 0x1810067
3978#define CE_REG_TP_A0_TAP_CURR__W 10
3979#define CE_REG_TP_A0_TAP_CURR__M 0x3FF
3980
3981#define CE_REG_TP_A1_TAP_NEW__A 0x1810068
3982#define CE_REG_TP_A1_TAP_NEW__W 10
3983#define CE_REG_TP_A1_TAP_NEW__M 0x3FF
3984
3985#define CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069
3986#define CE_REG_TP_A1_TAP_NEW_VALID__W 1
3987#define CE_REG_TP_A1_TAP_NEW_VALID__M 0x1
3988
3989#define CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A
3990#define CE_REG_TP_A1_MU_LMS_STEP__W 5
3991#define CE_REG_TP_A1_MU_LMS_STEP__M 0x1F
3992
3993#define CE_REG_TP_A1_TAP_CURR__A 0x181006B
3994#define CE_REG_TP_A1_TAP_CURR__W 10
3995#define CE_REG_TP_A1_TAP_CURR__M 0x3FF
3996
3997#define CE_REG_TP_DOPP_ENERGY__A 0x181006C
3998#define CE_REG_TP_DOPP_ENERGY__W 15
3999#define CE_REG_TP_DOPP_ENERGY__M 0x7FFF
4000#define CE_REG_TP_DOPP_ENERGY_INIT 0x0
4001
4002#define CE_REG_TP_DOPP_ENERGY_EXPONENT__B 10
4003#define CE_REG_TP_DOPP_ENERGY_EXPONENT__W 5
4004#define CE_REG_TP_DOPP_ENERGY_EXPONENT__M 0x7C00
4005
4006#define CE_REG_TP_DOPP_ENERGY_MANTISSA__B 0
4007#define CE_REG_TP_DOPP_ENERGY_MANTISSA__W 10
4008#define CE_REG_TP_DOPP_ENERGY_MANTISSA__M 0x3FF
4009
4010
4011#define CE_REG_TP_DOPP_DIFF_ENERGY__A 0x181006D
4012#define CE_REG_TP_DOPP_DIFF_ENERGY__W 15
4013#define CE_REG_TP_DOPP_DIFF_ENERGY__M 0x7FFF
4014#define CE_REG_TP_DOPP_DIFF_ENERGY_INIT 0x0
4015
4016#define CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__B 10
4017#define CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__W 5
4018#define CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__M 0x7C00
4019
4020#define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__B 0
4021#define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10
4022#define CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF
4023
4024
4025#define CE_REG_TP_A0_TAP_ENERGY__A 0x181006E
4026#define CE_REG_TP_A0_TAP_ENERGY__W 15
4027#define CE_REG_TP_A0_TAP_ENERGY__M 0x7FFF
4028#define CE_REG_TP_A0_TAP_ENERGY_INIT 0x0
4029
4030#define CE_REG_TP_A0_TAP_ENERGY_EXPONENT__B 10
4031#define CE_REG_TP_A0_TAP_ENERGY_EXPONENT__W 5
4032#define CE_REG_TP_A0_TAP_ENERGY_EXPONENT__M 0x7C00
4033
4034#define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__B 0
4035#define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__W 10
4036#define CE_REG_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF
4037
4038
4039#define CE_REG_TP_A1_TAP_ENERGY__A 0x181006F
4040#define CE_REG_TP_A1_TAP_ENERGY__W 15
4041#define CE_REG_TP_A1_TAP_ENERGY__M 0x7FFF
4042#define CE_REG_TP_A1_TAP_ENERGY_INIT 0x0
4043
4044#define CE_REG_TP_A1_TAP_ENERGY_EXPONENT__B 10
4045#define CE_REG_TP_A1_TAP_ENERGY_EXPONENT__W 5
4046#define CE_REG_TP_A1_TAP_ENERGY_EXPONENT__M 0x7C00
4047
4048#define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__B 0
4049#define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__W 10
4050#define CE_REG_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF
4051
4052
4053#define CE_REG_TI_NEXP_OFFS__A 0x1810070
4054#define CE_REG_TI_NEXP_OFFS__W 8
4055#define CE_REG_TI_NEXP_OFFS__M 0xFF
4056#define CE_REG_TI_NEXP_OFFS_INIT 0x0
4057
4058
4059#define CE_REG_TI_PEAK__A 0x1810071
4060#define CE_REG_TI_PEAK__W 8
4061#define CE_REG_TI_PEAK__M 0xFF
4062#define CE_REG_TI_PEAK_INIT 0x0
4063
4064
4065#define CE_REG_FI_SHT_INCR__A 0x1810090
4066#define CE_REG_FI_SHT_INCR__W 7
4067#define CE_REG_FI_SHT_INCR__M 0x7F
4068#define CE_REG_FI_SHT_INCR_INIT 0x9
4069
4070
4071#define CE_REG_FI_EXP_NORM__A 0x1810091
4072#define CE_REG_FI_EXP_NORM__W 4
4073#define CE_REG_FI_EXP_NORM__M 0xF
4074#define CE_REG_FI_EXP_NORM_INIT 0x4
4075
4076
4077#define CE_REG_FI_SUPR_VAL__A 0x1810092
4078#define CE_REG_FI_SUPR_VAL__W 1
4079#define CE_REG_FI_SUPR_VAL__M 0x1
4080#define CE_REG_FI_SUPR_VAL_INIT 0x1
4081
4082
4083#define CE_REG_IR_INPUTSEL__A 0x18100A0
4084#define CE_REG_IR_INPUTSEL__W 1
4085#define CE_REG_IR_INPUTSEL__M 0x1
4086#define CE_REG_IR_INPUTSEL_INIT 0x0
4087
4088
4089#define CE_REG_IR_STARTPOS__A 0x18100A1
4090#define CE_REG_IR_STARTPOS__W 8
4091#define CE_REG_IR_STARTPOS__M 0xFF
4092#define CE_REG_IR_STARTPOS_INIT 0x0
4093
4094
4095#define CE_REG_IR_NEXP_THRES__A 0x18100A2
4096#define CE_REG_IR_NEXP_THRES__W 8
4097#define CE_REG_IR_NEXP_THRES__M 0xFF
4098#define CE_REG_IR_NEXP_THRES_INIT 0x0
4099
4100
4101#define CE_REG_IR_LENGTH__A 0x18100A3
4102#define CE_REG_IR_LENGTH__W 4
4103#define CE_REG_IR_LENGTH__M 0xF
4104#define CE_REG_IR_LENGTH_INIT 0x0
4105
4106
4107#define CE_REG_IR_FREQ__A 0x18100A4
4108#define CE_REG_IR_FREQ__W 11
4109#define CE_REG_IR_FREQ__M 0x7FF
4110#define CE_REG_IR_FREQ_INIT 0x0
4111
4112
4113#define CE_REG_IR_FREQINC__A 0x18100A5
4114#define CE_REG_IR_FREQINC__W 11
4115#define CE_REG_IR_FREQINC__M 0x7FF
4116#define CE_REG_IR_FREQINC_INIT 0x0
4117
4118
4119#define CE_REG_IR_KAISINC__A 0x18100A6
4120#define CE_REG_IR_KAISINC__W 15
4121#define CE_REG_IR_KAISINC__M 0x7FFF
4122#define CE_REG_IR_KAISINC_INIT 0x0
4123
4124
4125#define CE_REG_IR_CTL__A 0x18100A7
4126#define CE_REG_IR_CTL__W 3
4127#define CE_REG_IR_CTL__M 0x7
4128#define CE_REG_IR_CTL_INIT 0x0
4129
4130
4131#define CE_REG_IR_REAL__A 0x18100A8
4132#define CE_REG_IR_REAL__W 16
4133#define CE_REG_IR_REAL__M 0xFFFF
4134#define CE_REG_IR_REAL_INIT 0x0
4135
4136
4137#define CE_REG_IR_IMAG__A 0x18100A9
4138#define CE_REG_IR_IMAG__W 16
4139#define CE_REG_IR_IMAG__M 0xFFFF
4140#define CE_REG_IR_IMAG_INIT 0x0
4141
4142
4143#define CE_REG_IR_INDEX__A 0x18100AA
4144#define CE_REG_IR_INDEX__W 12
4145#define CE_REG_IR_INDEX__M 0xFFF
4146#define CE_REG_IR_INDEX_INIT 0x0
4147
4148
4149
4150
4151#define CE_REG_FR_TREAL00__A 0x1820010
4152#define CE_REG_FR_TREAL00__W 11
4153#define CE_REG_FR_TREAL00__M 0x7FF
4154#define CE_REG_FR_TREAL00_INIT 0x52
4155
4156
4157#define CE_REG_FR_TIMAG00__A 0x1820011
4158#define CE_REG_FR_TIMAG00__W 11
4159#define CE_REG_FR_TIMAG00__M 0x7FF
4160#define CE_REG_FR_TIMAG00_INIT 0x0
4161
4162
4163#define CE_REG_FR_TREAL01__A 0x1820012
4164#define CE_REG_FR_TREAL01__W 11
4165#define CE_REG_FR_TREAL01__M 0x7FF
4166#define CE_REG_FR_TREAL01_INIT 0x52
4167
4168
4169#define CE_REG_FR_TIMAG01__A 0x1820013
4170#define CE_REG_FR_TIMAG01__W 11
4171#define CE_REG_FR_TIMAG01__M 0x7FF
4172#define CE_REG_FR_TIMAG01_INIT 0x0
4173
4174
4175#define CE_REG_FR_TREAL02__A 0x1820014
4176#define CE_REG_FR_TREAL02__W 11
4177#define CE_REG_FR_TREAL02__M 0x7FF
4178#define CE_REG_FR_TREAL02_INIT 0x52
4179
4180
4181#define CE_REG_FR_TIMAG02__A 0x1820015
4182#define CE_REG_FR_TIMAG02__W 11
4183#define CE_REG_FR_TIMAG02__M 0x7FF
4184#define CE_REG_FR_TIMAG02_INIT 0x0
4185
4186
4187#define CE_REG_FR_TREAL03__A 0x1820016
4188#define CE_REG_FR_TREAL03__W 11
4189#define CE_REG_FR_TREAL03__M 0x7FF
4190#define CE_REG_FR_TREAL03_INIT 0x52
4191
4192
4193#define CE_REG_FR_TIMAG03__A 0x1820017
4194#define CE_REG_FR_TIMAG03__W 11
4195#define CE_REG_FR_TIMAG03__M 0x7FF
4196#define CE_REG_FR_TIMAG03_INIT 0x0
4197
4198
4199#define CE_REG_FR_TREAL04__A 0x1820018
4200#define CE_REG_FR_TREAL04__W 11
4201#define CE_REG_FR_TREAL04__M 0x7FF
4202#define CE_REG_FR_TREAL04_INIT 0x52
4203
4204
4205#define CE_REG_FR_TIMAG04__A 0x1820019
4206#define CE_REG_FR_TIMAG04__W 11
4207#define CE_REG_FR_TIMAG04__M 0x7FF
4208#define CE_REG_FR_TIMAG04_INIT 0x0
4209
4210
4211#define CE_REG_FR_TREAL05__A 0x182001A
4212#define CE_REG_FR_TREAL05__W 11
4213#define CE_REG_FR_TREAL05__M 0x7FF
4214#define CE_REG_FR_TREAL05_INIT 0x52
4215
4216
4217#define CE_REG_FR_TIMAG05__A 0x182001B
4218#define CE_REG_FR_TIMAG05__W 11
4219#define CE_REG_FR_TIMAG05__M 0x7FF
4220#define CE_REG_FR_TIMAG05_INIT 0x0
4221
4222
4223#define CE_REG_FR_TREAL06__A 0x182001C
4224#define CE_REG_FR_TREAL06__W 11
4225#define CE_REG_FR_TREAL06__M 0x7FF
4226#define CE_REG_FR_TREAL06_INIT 0x52
4227
4228
4229#define CE_REG_FR_TIMAG06__A 0x182001D
4230#define CE_REG_FR_TIMAG06__W 11
4231#define CE_REG_FR_TIMAG06__M 0x7FF
4232#define CE_REG_FR_TIMAG06_INIT 0x0
4233
4234
4235#define CE_REG_FR_TREAL07__A 0x182001E
4236#define CE_REG_FR_TREAL07__W 11
4237#define CE_REG_FR_TREAL07__M 0x7FF
4238#define CE_REG_FR_TREAL07_INIT 0x52
4239
4240
4241#define CE_REG_FR_TIMAG07__A 0x182001F
4242#define CE_REG_FR_TIMAG07__W 11
4243#define CE_REG_FR_TIMAG07__M 0x7FF
4244#define CE_REG_FR_TIMAG07_INIT 0x0
4245
4246
4247#define CE_REG_FR_TREAL08__A 0x1820020
4248#define CE_REG_FR_TREAL08__W 11
4249#define CE_REG_FR_TREAL08__M 0x7FF
4250#define CE_REG_FR_TREAL08_INIT 0x52
4251
4252
4253#define CE_REG_FR_TIMAG08__A 0x1820021
4254#define CE_REG_FR_TIMAG08__W 11
4255#define CE_REG_FR_TIMAG08__M 0x7FF
4256#define CE_REG_FR_TIMAG08_INIT 0x0
4257
4258
4259#define CE_REG_FR_TREAL09__A 0x1820022
4260#define CE_REG_FR_TREAL09__W 11
4261#define CE_REG_FR_TREAL09__M 0x7FF
4262#define CE_REG_FR_TREAL09_INIT 0x52
4263
4264
4265#define CE_REG_FR_TIMAG09__A 0x1820023
4266#define CE_REG_FR_TIMAG09__W 11
4267#define CE_REG_FR_TIMAG09__M 0x7FF
4268#define CE_REG_FR_TIMAG09_INIT 0x0
4269
4270
4271#define CE_REG_FR_TREAL10__A 0x1820024
4272#define CE_REG_FR_TREAL10__W 11
4273#define CE_REG_FR_TREAL10__M 0x7FF
4274#define CE_REG_FR_TREAL10_INIT 0x52
4275
4276
4277#define CE_REG_FR_TIMAG10__A 0x1820025
4278#define CE_REG_FR_TIMAG10__W 11
4279#define CE_REG_FR_TIMAG10__M 0x7FF
4280#define CE_REG_FR_TIMAG10_INIT 0x0
4281
4282
4283#define CE_REG_FR_TREAL11__A 0x1820026
4284#define CE_REG_FR_TREAL11__W 11
4285#define CE_REG_FR_TREAL11__M 0x7FF
4286#define CE_REG_FR_TREAL11_INIT 0x52
4287
4288
4289#define CE_REG_FR_TIMAG11__A 0x1820027
4290#define CE_REG_FR_TIMAG11__W 11
4291#define CE_REG_FR_TIMAG11__M 0x7FF
4292#define CE_REG_FR_TIMAG11_INIT 0x0
4293
4294
4295#define CE_REG_FR_MID_TAP__A 0x1820028
4296#define CE_REG_FR_MID_TAP__W 11
4297#define CE_REG_FR_MID_TAP__M 0x7FF
4298#define CE_REG_FR_MID_TAP_INIT 0x51
4299
4300
4301#define CE_REG_FR_SQS_G00__A 0x1820029
4302#define CE_REG_FR_SQS_G00__W 8
4303#define CE_REG_FR_SQS_G00__M 0xFF
4304#define CE_REG_FR_SQS_G00_INIT 0xB
4305
4306
4307#define CE_REG_FR_SQS_G01__A 0x182002A
4308#define CE_REG_FR_SQS_G01__W 8
4309#define CE_REG_FR_SQS_G01__M 0xFF
4310#define CE_REG_FR_SQS_G01_INIT 0xB
4311
4312
4313#define CE_REG_FR_SQS_G02__A 0x182002B
4314#define CE_REG_FR_SQS_G02__W 8
4315#define CE_REG_FR_SQS_G02__M 0xFF
4316#define CE_REG_FR_SQS_G02_INIT 0xB
4317
4318
4319#define CE_REG_FR_SQS_G03__A 0x182002C
4320#define CE_REG_FR_SQS_G03__W 8
4321#define CE_REG_FR_SQS_G03__M 0xFF
4322#define CE_REG_FR_SQS_G03_INIT 0xB
4323
4324
4325#define CE_REG_FR_SQS_G04__A 0x182002D
4326#define CE_REG_FR_SQS_G04__W 8
4327#define CE_REG_FR_SQS_G04__M 0xFF
4328#define CE_REG_FR_SQS_G04_INIT 0xB
4329
4330
4331#define CE_REG_FR_SQS_G05__A 0x182002E
4332#define CE_REG_FR_SQS_G05__W 8
4333#define CE_REG_FR_SQS_G05__M 0xFF
4334#define CE_REG_FR_SQS_G05_INIT 0xB
4335
4336
4337#define CE_REG_FR_SQS_G06__A 0x182002F
4338#define CE_REG_FR_SQS_G06__W 8
4339#define CE_REG_FR_SQS_G06__M 0xFF
4340#define CE_REG_FR_SQS_G06_INIT 0xB
4341
4342
4343#define CE_REG_FR_SQS_G07__A 0x1820030
4344#define CE_REG_FR_SQS_G07__W 8
4345#define CE_REG_FR_SQS_G07__M 0xFF
4346#define CE_REG_FR_SQS_G07_INIT 0xB
4347
4348
4349#define CE_REG_FR_SQS_G08__A 0x1820031
4350#define CE_REG_FR_SQS_G08__W 8
4351#define CE_REG_FR_SQS_G08__M 0xFF
4352#define CE_REG_FR_SQS_G08_INIT 0xB
4353
4354
4355#define CE_REG_FR_SQS_G09__A 0x1820032
4356#define CE_REG_FR_SQS_G09__W 8
4357#define CE_REG_FR_SQS_G09__M 0xFF
4358#define CE_REG_FR_SQS_G09_INIT 0xB
4359
4360
4361#define CE_REG_FR_SQS_G10__A 0x1820033
4362#define CE_REG_FR_SQS_G10__W 8
4363#define CE_REG_FR_SQS_G10__M 0xFF
4364#define CE_REG_FR_SQS_G10_INIT 0xB
4365
4366
4367#define CE_REG_FR_SQS_G11__A 0x1820034
4368#define CE_REG_FR_SQS_G11__W 8
4369#define CE_REG_FR_SQS_G11__M 0xFF
4370#define CE_REG_FR_SQS_G11_INIT 0xB
4371
4372
4373#define CE_REG_FR_SQS_G12__A 0x1820035
4374#define CE_REG_FR_SQS_G12__W 8
4375#define CE_REG_FR_SQS_G12__M 0xFF
4376#define CE_REG_FR_SQS_G12_INIT 0x5
4377
4378
4379#define CE_REG_FR_RIO_G00__A 0x1820036
4380#define CE_REG_FR_RIO_G00__W 9
4381#define CE_REG_FR_RIO_G00__M 0x1FF
4382#define CE_REG_FR_RIO_G00_INIT 0x1FF
4383
4384
4385#define CE_REG_FR_RIO_G01__A 0x1820037
4386#define CE_REG_FR_RIO_G01__W 9
4387#define CE_REG_FR_RIO_G01__M 0x1FF
4388#define CE_REG_FR_RIO_G01_INIT 0x190
4389
4390
4391#define CE_REG_FR_RIO_G02__A 0x1820038
4392#define CE_REG_FR_RIO_G02__W 9
4393#define CE_REG_FR_RIO_G02__M 0x1FF
4394#define CE_REG_FR_RIO_G02_INIT 0x10B
4395
4396
4397#define CE_REG_FR_RIO_G03__A 0x1820039
4398#define CE_REG_FR_RIO_G03__W 9
4399#define CE_REG_FR_RIO_G03__M 0x1FF
4400#define CE_REG_FR_RIO_G03_INIT 0xC8
4401
4402
4403#define CE_REG_FR_RIO_G04__A 0x182003A
4404#define CE_REG_FR_RIO_G04__W 9
4405#define CE_REG_FR_RIO_G04__M 0x1FF
4406#define CE_REG_FR_RIO_G04_INIT 0xA0
4407
4408
4409#define CE_REG_FR_RIO_G05__A 0x182003B
4410#define CE_REG_FR_RIO_G05__W 9
4411#define CE_REG_FR_RIO_G05__M 0x1FF
4412#define CE_REG_FR_RIO_G05_INIT 0x85
4413
4414
4415#define CE_REG_FR_RIO_G06__A 0x182003C
4416#define CE_REG_FR_RIO_G06__W 9
4417#define CE_REG_FR_RIO_G06__M 0x1FF
4418#define CE_REG_FR_RIO_G06_INIT 0x72
4419
4420
4421#define CE_REG_FR_RIO_G07__A 0x182003D
4422#define CE_REG_FR_RIO_G07__W 9
4423#define CE_REG_FR_RIO_G07__M 0x1FF
4424#define CE_REG_FR_RIO_G07_INIT 0x64
4425
4426
4427#define CE_REG_FR_RIO_G08__A 0x182003E
4428#define CE_REG_FR_RIO_G08__W 9
4429#define CE_REG_FR_RIO_G08__M 0x1FF
4430#define CE_REG_FR_RIO_G08_INIT 0x59
4431
4432
4433#define CE_REG_FR_RIO_G09__A 0x182003F
4434#define CE_REG_FR_RIO_G09__W 9
4435#define CE_REG_FR_RIO_G09__M 0x1FF
4436#define CE_REG_FR_RIO_G09_INIT 0x50
4437
4438
4439#define CE_REG_FR_RIO_G10__A 0x1820040
4440#define CE_REG_FR_RIO_G10__W 9
4441#define CE_REG_FR_RIO_G10__M 0x1FF
4442#define CE_REG_FR_RIO_G10_INIT 0x49
4443
4444
4445#define CE_REG_FR_MODE__A 0x1820041
4446#define CE_REG_FR_MODE__W 6
4447#define CE_REG_FR_MODE__M 0x3F
4448
4449#define CE_REG_FR_MODE_UPDATE_ENABLE__B 0
4450#define CE_REG_FR_MODE_UPDATE_ENABLE__W 1
4451#define CE_REG_FR_MODE_UPDATE_ENABLE__M 0x1
4452
4453#define CE_REG_FR_MODE_ERROR_SHIFT__B 1
4454#define CE_REG_FR_MODE_ERROR_SHIFT__W 1
4455#define CE_REG_FR_MODE_ERROR_SHIFT__M 0x2
4456
4457#define CE_REG_FR_MODE_NEXP_UPDATE__B 2
4458#define CE_REG_FR_MODE_NEXP_UPDATE__W 1
4459#define CE_REG_FR_MODE_NEXP_UPDATE__M 0x4
4460
4461#define CE_REG_FR_MODE_MANUAL_SHIFT__B 3
4462#define CE_REG_FR_MODE_MANUAL_SHIFT__W 1
4463#define CE_REG_FR_MODE_MANUAL_SHIFT__M 0x8
4464
4465#define CE_REG_FR_MODE_SQUASH_MODE__B 4
4466#define CE_REG_FR_MODE_SQUASH_MODE__W 1
4467#define CE_REG_FR_MODE_SQUASH_MODE__M 0x10
4468
4469#define CE_REG_FR_MODE_UPDATE_MODE__B 5
4470#define CE_REG_FR_MODE_UPDATE_MODE__W 1
4471#define CE_REG_FR_MODE_UPDATE_MODE__M 0x20
4472#define CE_REG_FR_MODE_INIT 0x3E
4473
4474
4475#define CE_REG_FR_SQS_TRH__A 0x1820042
4476#define CE_REG_FR_SQS_TRH__W 8
4477#define CE_REG_FR_SQS_TRH__M 0xFF
4478#define CE_REG_FR_SQS_TRH_INIT 0x80
4479
4480
4481#define CE_REG_FR_RIO_GAIN__A 0x1820043
4482#define CE_REG_FR_RIO_GAIN__W 3
4483#define CE_REG_FR_RIO_GAIN__M 0x7
4484#define CE_REG_FR_RIO_GAIN_INIT 0x2
4485
4486
4487#define CE_REG_FR_BYPASS__A 0x1820044
4488#define CE_REG_FR_BYPASS__W 10
4489#define CE_REG_FR_BYPASS__M 0x3FF
4490
4491#define CE_REG_FR_BYPASS_RUN_IN__B 0
4492#define CE_REG_FR_BYPASS_RUN_IN__W 4
4493#define CE_REG_FR_BYPASS_RUN_IN__M 0xF
4494
4495#define CE_REG_FR_BYPASS_RUN_SEMI_IN__B 4
4496#define CE_REG_FR_BYPASS_RUN_SEMI_IN__W 5
4497#define CE_REG_FR_BYPASS_RUN_SEMI_IN__M 0x1F0
4498
4499#define CE_REG_FR_BYPASS_TOTAL__B 9
4500#define CE_REG_FR_BYPASS_TOTAL__W 1
4501#define CE_REG_FR_BYPASS_TOTAL__M 0x200
4502#define CE_REG_FR_BYPASS_INIT 0x13B
4503
4504
4505#define CE_REG_FR_PM_SET__A 0x1820045
4506#define CE_REG_FR_PM_SET__W 4
4507#define CE_REG_FR_PM_SET__M 0xF
4508#define CE_REG_FR_PM_SET_INIT 0x4
4509
4510
4511#define CE_REG_FR_ERR_SH__A 0x1820046
4512#define CE_REG_FR_ERR_SH__W 4
4513#define CE_REG_FR_ERR_SH__M 0xF
4514#define CE_REG_FR_ERR_SH_INIT 0x4
4515
4516
4517#define CE_REG_FR_MAN_SH__A 0x1820047
4518#define CE_REG_FR_MAN_SH__W 4
4519#define CE_REG_FR_MAN_SH__M 0xF
4520#define CE_REG_FR_MAN_SH_INIT 0x7
4521
4522
4523#define CE_REG_FR_TAP_SH__A 0x1820048
4524#define CE_REG_FR_TAP_SH__W 3
4525#define CE_REG_FR_TAP_SH__M 0x7
4526#define CE_REG_FR_TAP_SH_INIT 0x3
4527
4528
4529#define CE_REG_FR_CLIP__A 0x1820049
4530#define CE_REG_FR_CLIP__W 9
4531#define CE_REG_FR_CLIP__M 0x1FF
4532#define CE_REG_FR_CLIP_INIT 0x49
4533
4534
4535
4536#define CE_PB_RAM__A 0x1830000
4537
4538
4539
4540#define CE_NE_RAM__A 0x1840000
4541
4542
4543
4544
4545
4546#define EQ_SID 0xE
4547
4548
4549
4550
4551
4552#define EQ_COMM_EXEC__A 0x1C00000
4553#define EQ_COMM_EXEC__W 3
4554#define EQ_COMM_EXEC__M 0x7
4555#define EQ_COMM_EXEC_CTL__B 0
4556#define EQ_COMM_EXEC_CTL__W 3
4557#define EQ_COMM_EXEC_CTL__M 0x7
4558#define EQ_COMM_EXEC_CTL_STOP 0x0
4559#define EQ_COMM_EXEC_CTL_ACTIVE 0x1
4560#define EQ_COMM_EXEC_CTL_HOLD 0x2
4561#define EQ_COMM_EXEC_CTL_STEP 0x3
4562#define EQ_COMM_EXEC_CTL_BYPASS_STOP 0x4
4563#define EQ_COMM_EXEC_CTL_BYPASS_HOLD 0x6
4564
4565#define EQ_COMM_STATE__A 0x1C00001
4566#define EQ_COMM_STATE__W 16
4567#define EQ_COMM_STATE__M 0xFFFF
4568#define EQ_COMM_MB__A 0x1C00002
4569#define EQ_COMM_MB__W 16
4570#define EQ_COMM_MB__M 0xFFFF
4571#define EQ_COMM_SERVICE0__A 0x1C00003
4572#define EQ_COMM_SERVICE0__W 16
4573#define EQ_COMM_SERVICE0__M 0xFFFF
4574#define EQ_COMM_SERVICE1__A 0x1C00004
4575#define EQ_COMM_SERVICE1__W 16
4576#define EQ_COMM_SERVICE1__M 0xFFFF
4577#define EQ_COMM_INT_STA__A 0x1C00007
4578#define EQ_COMM_INT_STA__W 16
4579#define EQ_COMM_INT_STA__M 0xFFFF
4580#define EQ_COMM_INT_MSK__A 0x1C00008
4581#define EQ_COMM_INT_MSK__W 16
4582#define EQ_COMM_INT_MSK__M 0xFFFF
4583
4584
4585
4586
4587
4588
4589#define EQ_REG_COMM_EXEC__A 0x1C10000
4590#define EQ_REG_COMM_EXEC__W 3
4591#define EQ_REG_COMM_EXEC__M 0x7
4592#define EQ_REG_COMM_EXEC_CTL__B 0
4593#define EQ_REG_COMM_EXEC_CTL__W 3
4594#define EQ_REG_COMM_EXEC_CTL__M 0x7
4595#define EQ_REG_COMM_EXEC_CTL_STOP 0x0
4596#define EQ_REG_COMM_EXEC_CTL_ACTIVE 0x1
4597#define EQ_REG_COMM_EXEC_CTL_HOLD 0x2
4598#define EQ_REG_COMM_EXEC_CTL_STEP 0x3
4599
4600#define EQ_REG_COMM_STATE__A 0x1C10001
4601#define EQ_REG_COMM_STATE__W 4
4602#define EQ_REG_COMM_STATE__M 0xF
4603
4604#define EQ_REG_COMM_MB__A 0x1C10002
4605#define EQ_REG_COMM_MB__W 6
4606#define EQ_REG_COMM_MB__M 0x3F
4607#define EQ_REG_COMM_MB_CTR__B 0
4608#define EQ_REG_COMM_MB_CTR__W 1
4609#define EQ_REG_COMM_MB_CTR__M 0x1
4610#define EQ_REG_COMM_MB_CTR_OFF 0x0
4611#define EQ_REG_COMM_MB_CTR_ON 0x1
4612#define EQ_REG_COMM_MB_OBS__B 1
4613#define EQ_REG_COMM_MB_OBS__W 1
4614#define EQ_REG_COMM_MB_OBS__M 0x2
4615#define EQ_REG_COMM_MB_OBS_OFF 0x0
4616#define EQ_REG_COMM_MB_OBS_ON 0x2
4617#define EQ_REG_COMM_MB_CTR_MUX__B 2
4618#define EQ_REG_COMM_MB_CTR_MUX__W 2
4619#define EQ_REG_COMM_MB_CTR_MUX__M 0xC
4620#define EQ_REG_COMM_MB_CTR_MUX_EQ_OT 0x0
4621#define EQ_REG_COMM_MB_CTR_MUX_EQ_RC 0x4
4622#define EQ_REG_COMM_MB_CTR_MUX_EQ_IS 0x8
4623#define EQ_REG_COMM_MB_OBS_MUX__B 4
4624#define EQ_REG_COMM_MB_OBS_MUX__W 2
4625#define EQ_REG_COMM_MB_OBS_MUX__M 0x30
4626#define EQ_REG_COMM_MB_OBS_MUX_EQ_OT 0x0
4627#define EQ_REG_COMM_MB_OBS_MUX_EQ_RC 0x10
4628#define EQ_REG_COMM_MB_OBS_MUX_EQ_IS 0x20
4629#define EQ_REG_COMM_MB_OBS_MUX_EQ_SN 0x30
4630
4631
4632#define EQ_REG_COMM_SERVICE0__A 0x1C10003
4633#define EQ_REG_COMM_SERVICE0__W 10
4634#define EQ_REG_COMM_SERVICE0__M 0x3FF
4635
4636#define EQ_REG_COMM_SERVICE1__A 0x1C10004
4637#define EQ_REG_COMM_SERVICE1__W 11
4638#define EQ_REG_COMM_SERVICE1__M 0x7FF
4639
4640#define EQ_REG_COMM_INT_STA__A 0x1C10007
4641#define EQ_REG_COMM_INT_STA__W 2
4642#define EQ_REG_COMM_INT_STA__M 0x3
4643#define EQ_REG_COMM_INT_STA_TPS_RDY__B 0
4644#define EQ_REG_COMM_INT_STA_TPS_RDY__W 1
4645#define EQ_REG_COMM_INT_STA_TPS_RDY__M 0x1
4646#define EQ_REG_COMM_INT_STA_ERR_RDY__B 1
4647#define EQ_REG_COMM_INT_STA_ERR_RDY__W 1
4648#define EQ_REG_COMM_INT_STA_ERR_RDY__M 0x2
4649
4650
4651#define EQ_REG_COMM_INT_MSK__A 0x1C10008
4652#define EQ_REG_COMM_INT_MSK__W 2
4653#define EQ_REG_COMM_INT_MSK__M 0x3
4654#define EQ_REG_COMM_INT_MSK_TPS_RDY__B 0
4655#define EQ_REG_COMM_INT_MSK_TPS_RDY__W 1
4656#define EQ_REG_COMM_INT_MSK_TPS_RDY__M 0x1
4657#define EQ_REG_COMM_INT_MSK_MER_RDY__B 1
4658#define EQ_REG_COMM_INT_MSK_MER_RDY__W 1
4659#define EQ_REG_COMM_INT_MSK_MER_RDY__M 0x2
4660
4661
4662#define EQ_REG_IS_MODE__A 0x1C10014
4663#define EQ_REG_IS_MODE__W 4
4664#define EQ_REG_IS_MODE__M 0xF
4665#define EQ_REG_IS_MODE_INIT 0x0
4666
4667#define EQ_REG_IS_MODE_LIM_EXP_SEL__B 0
4668#define EQ_REG_IS_MODE_LIM_EXP_SEL__W 1
4669#define EQ_REG_IS_MODE_LIM_EXP_SEL__M 0x1
4670#define EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_MAX 0x0
4671#define EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_ZER 0x1
4672
4673#define EQ_REG_IS_MODE_LIM_CLP_SEL__B 1
4674#define EQ_REG_IS_MODE_LIM_CLP_SEL__W 1
4675#define EQ_REG_IS_MODE_LIM_CLP_SEL__M 0x2
4676#define EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_ONE 0x0
4677#define EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_TWO 0x2
4678
4679
4680#define EQ_REG_IS_GAIN_MAN__A 0x1C10015
4681#define EQ_REG_IS_GAIN_MAN__W 10
4682#define EQ_REG_IS_GAIN_MAN__M 0x3FF
4683#define EQ_REG_IS_GAIN_MAN_INIT 0x0
4684
4685
4686#define EQ_REG_IS_GAIN_EXP__A 0x1C10016
4687#define EQ_REG_IS_GAIN_EXP__W 5
4688#define EQ_REG_IS_GAIN_EXP__M 0x1F
4689#define EQ_REG_IS_GAIN_EXP_INIT 0x0
4690
4691
4692#define EQ_REG_IS_CLIP_EXP__A 0x1C10017
4693#define EQ_REG_IS_CLIP_EXP__W 5
4694#define EQ_REG_IS_CLIP_EXP__M 0x1F
4695#define EQ_REG_IS_CLIP_EXP_INIT 0x0
4696
4697
4698#define EQ_REG_DV_MODE__A 0x1C1001E
4699#define EQ_REG_DV_MODE__W 4
4700#define EQ_REG_DV_MODE__M 0xF
4701#define EQ_REG_DV_MODE_INIT 0x0
4702
4703#define EQ_REG_DV_MODE_CLP_CNT_EVR__B 0
4704#define EQ_REG_DV_MODE_CLP_CNT_EVR__W 1
4705#define EQ_REG_DV_MODE_CLP_CNT_EVR__M 0x1
4706#define EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_DIS 0x0
4707#define EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_ENA 0x1
4708
4709#define EQ_REG_DV_MODE_CLP_CNT_EVI__B 1
4710#define EQ_REG_DV_MODE_CLP_CNT_EVI__W 1
4711#define EQ_REG_DV_MODE_CLP_CNT_EVI__M 0x2
4712#define EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_DIS 0x0
4713#define EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_ENA 0x2
4714
4715#define EQ_REG_DV_MODE_CLP_REA_ENA__B 2
4716#define EQ_REG_DV_MODE_CLP_REA_ENA__W 1
4717#define EQ_REG_DV_MODE_CLP_REA_ENA__M 0x4
4718#define EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_DIS 0x0
4719#define EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_ENA 0x4
4720
4721#define EQ_REG_DV_MODE_CLP_IMA_ENA__B 3
4722#define EQ_REG_DV_MODE_CLP_IMA_ENA__W 1
4723#define EQ_REG_DV_MODE_CLP_IMA_ENA__M 0x8
4724#define EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_DIS 0x0
4725#define EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_ENA 0x8
4726
4727
4728#define EQ_REG_DV_POS_CLIP_DAT__A 0x1C1001F
4729#define EQ_REG_DV_POS_CLIP_DAT__W 16
4730#define EQ_REG_DV_POS_CLIP_DAT__M 0xFFFF
4731
4732#define EQ_REG_SN_MODE__A 0x1C10028
4733#define EQ_REG_SN_MODE__W 8
4734#define EQ_REG_SN_MODE__M 0xFF
4735#define EQ_REG_SN_MODE_INIT 0x0
4736
4737#define EQ_REG_SN_MODE_MODE_0__B 0
4738#define EQ_REG_SN_MODE_MODE_0__W 1
4739#define EQ_REG_SN_MODE_MODE_0__M 0x1
4740#define EQ_REG_SN_MODE_MODE_0_DISABLE 0x0
4741#define EQ_REG_SN_MODE_MODE_0_ENABLE 0x1
4742
4743#define EQ_REG_SN_MODE_MODE_1__B 1
4744#define EQ_REG_SN_MODE_MODE_1__W 1
4745#define EQ_REG_SN_MODE_MODE_1__M 0x2
4746#define EQ_REG_SN_MODE_MODE_1_DISABLE 0x0
4747#define EQ_REG_SN_MODE_MODE_1_ENABLE 0x2
4748
4749#define EQ_REG_SN_MODE_MODE_2__B 2
4750#define EQ_REG_SN_MODE_MODE_2__W 1
4751#define EQ_REG_SN_MODE_MODE_2__M 0x4
4752#define EQ_REG_SN_MODE_MODE_2_DISABLE 0x0
4753#define EQ_REG_SN_MODE_MODE_2_ENABLE 0x4
4754
4755#define EQ_REG_SN_MODE_MODE_3__B 3
4756#define EQ_REG_SN_MODE_MODE_3__W 1
4757#define EQ_REG_SN_MODE_MODE_3__M 0x8
4758#define EQ_REG_SN_MODE_MODE_3_DISABLE 0x0
4759#define EQ_REG_SN_MODE_MODE_3_ENABLE 0x8
4760
4761#define EQ_REG_SN_MODE_MODE_4__B 4
4762#define EQ_REG_SN_MODE_MODE_4__W 1
4763#define EQ_REG_SN_MODE_MODE_4__M 0x10
4764#define EQ_REG_SN_MODE_MODE_4_DISABLE 0x0
4765#define EQ_REG_SN_MODE_MODE_4_ENABLE 0x10
4766
4767#define EQ_REG_SN_MODE_MODE_5__B 5
4768#define EQ_REG_SN_MODE_MODE_5__W 1
4769#define EQ_REG_SN_MODE_MODE_5__M 0x20
4770#define EQ_REG_SN_MODE_MODE_5_DISABLE 0x0
4771#define EQ_REG_SN_MODE_MODE_5_ENABLE 0x20
4772
4773#define EQ_REG_SN_MODE_MODE_6__B 6
4774#define EQ_REG_SN_MODE_MODE_6__W 1
4775#define EQ_REG_SN_MODE_MODE_6__M 0x40
4776#define EQ_REG_SN_MODE_MODE_6_DYNAMIC 0x0
4777#define EQ_REG_SN_MODE_MODE_6_STATIC 0x40
4778
4779#define EQ_REG_SN_MODE_MODE_7__B 7
4780#define EQ_REG_SN_MODE_MODE_7__W 1
4781#define EQ_REG_SN_MODE_MODE_7__M 0x80
4782#define EQ_REG_SN_MODE_MODE_7_DYNAMIC 0x0
4783#define EQ_REG_SN_MODE_MODE_7_STATIC 0x80
4784
4785
4786#define EQ_REG_SN_PFIX__A 0x1C10029
4787#define EQ_REG_SN_PFIX__W 8
4788#define EQ_REG_SN_PFIX__M 0xFF
4789#define EQ_REG_SN_PFIX_INIT 0x0
4790
4791
4792#define EQ_REG_SN_CEGAIN__A 0x1C1002A
4793#define EQ_REG_SN_CEGAIN__W 8
4794#define EQ_REG_SN_CEGAIN__M 0xFF
4795#define EQ_REG_SN_CEGAIN_INIT 0x0
4796
4797
4798#define EQ_REG_SN_OFFSET__A 0x1C1002B
4799#define EQ_REG_SN_OFFSET__W 6
4800#define EQ_REG_SN_OFFSET__M 0x3F
4801#define EQ_REG_SN_OFFSET_INIT 0x0
4802
4803
4804#define EQ_REG_SN_NULLIFY__A 0x1C1002C
4805#define EQ_REG_SN_NULLIFY__W 6
4806#define EQ_REG_SN_NULLIFY__M 0x3F
4807#define EQ_REG_SN_NULLIFY_INIT 0x0
4808
4809
4810#define EQ_REG_SN_SQUASH__A 0x1C1002D
4811#define EQ_REG_SN_SQUASH__W 10
4812#define EQ_REG_SN_SQUASH__M 0x3FF
4813#define EQ_REG_SN_SQUASH_INIT 0x0
4814
4815#define EQ_REG_SN_SQUASH_MAN__B 0
4816#define EQ_REG_SN_SQUASH_MAN__W 6
4817#define EQ_REG_SN_SQUASH_MAN__M 0x3F
4818
4819#define EQ_REG_SN_SQUASH_EXP__B 6
4820#define EQ_REG_SN_SQUASH_EXP__W 4
4821#define EQ_REG_SN_SQUASH_EXP__M 0x3C0
4822
4823
4824
4825
4826#define EQ_REG_RC_SEL_CAR__A 0x1C10032
4827#define EQ_REG_RC_SEL_CAR__W 6
4828#define EQ_REG_RC_SEL_CAR__M 0x3F
4829#define EQ_REG_RC_SEL_CAR_INIT 0x0
4830#define EQ_REG_RC_SEL_CAR_DIV__B 0
4831#define EQ_REG_RC_SEL_CAR_DIV__W 1
4832#define EQ_REG_RC_SEL_CAR_DIV__M 0x1
4833#define EQ_REG_RC_SEL_CAR_DIV_OFF 0x0
4834#define EQ_REG_RC_SEL_CAR_DIV_ON 0x1
4835
4836#define EQ_REG_RC_SEL_CAR_PASS__B 1
4837#define EQ_REG_RC_SEL_CAR_PASS__W 2
4838#define EQ_REG_RC_SEL_CAR_PASS__M 0x6
4839#define EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0
4840#define EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2
4841#define EQ_REG_RC_SEL_CAR_PASS_C_DRI 0x4
4842#define EQ_REG_RC_SEL_CAR_PASS_D_CC 0x6
4843
4844#define EQ_REG_RC_SEL_CAR_LOCAL__B 3
4845#define EQ_REG_RC_SEL_CAR_LOCAL__W 2
4846#define EQ_REG_RC_SEL_CAR_LOCAL__M 0x18
4847#define EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0
4848#define EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8
4849#define EQ_REG_RC_SEL_CAR_LOCAL_C_DRI 0x10
4850#define EQ_REG_RC_SEL_CAR_LOCAL_D_CC 0x18
4851
4852#define EQ_REG_RC_SEL_CAR_MEAS__B 5
4853#define EQ_REG_RC_SEL_CAR_MEAS__W 1
4854#define EQ_REG_RC_SEL_CAR_MEAS__M 0x20
4855#define EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0
4856#define EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20
4857
4858
4859#define EQ_REG_RC_STS__A 0x1C10033
4860#define EQ_REG_RC_STS__W 12
4861#define EQ_REG_RC_STS__M 0xFFF
4862
4863#define EQ_REG_RC_STS_DIFF__B 0
4864#define EQ_REG_RC_STS_DIFF__W 9
4865#define EQ_REG_RC_STS_DIFF__M 0x1FF
4866
4867#define EQ_REG_RC_STS_FIRST__B 9
4868#define EQ_REG_RC_STS_FIRST__W 1
4869#define EQ_REG_RC_STS_FIRST__M 0x200
4870#define EQ_REG_RC_STS_FIRST_A_CE 0x0
4871#define EQ_REG_RC_STS_FIRST_B_DRI 0x200
4872
4873#define EQ_REG_RC_STS_SELEC__B 10
4874#define EQ_REG_RC_STS_SELEC__W 1
4875#define EQ_REG_RC_STS_SELEC__M 0x400
4876#define EQ_REG_RC_STS_SELEC_A_CE 0x0
4877#define EQ_REG_RC_STS_SELEC_B_DRI 0x400
4878
4879#define EQ_REG_RC_STS_OVERFLOW__B 11
4880#define EQ_REG_RC_STS_OVERFLOW__W 1
4881#define EQ_REG_RC_STS_OVERFLOW__M 0x800
4882#define EQ_REG_RC_STS_OVERFLOW_NO 0x0
4883#define EQ_REG_RC_STS_OVERFLOW_YES 0x800
4884
4885
4886#define EQ_REG_OT_CONST__A 0x1C10046
4887#define EQ_REG_OT_CONST__W 2
4888#define EQ_REG_OT_CONST__M 0x3
4889#define EQ_REG_OT_CONST_INIT 0x0
4890
4891
4892#define EQ_REG_OT_ALPHA__A 0x1C10047
4893#define EQ_REG_OT_ALPHA__W 2
4894#define EQ_REG_OT_ALPHA__M 0x3
4895#define EQ_REG_OT_ALPHA_INIT 0x0
4896
4897
4898#define EQ_REG_OT_QNT_THRES0__A 0x1C10048
4899#define EQ_REG_OT_QNT_THRES0__W 5
4900#define EQ_REG_OT_QNT_THRES0__M 0x1F
4901#define EQ_REG_OT_QNT_THRES0_INIT 0x0
4902
4903
4904#define EQ_REG_OT_QNT_THRES1__A 0x1C10049
4905#define EQ_REG_OT_QNT_THRES1__W 5
4906#define EQ_REG_OT_QNT_THRES1__M 0x1F
4907#define EQ_REG_OT_QNT_THRES1_INIT 0x0
4908
4909
4910#define EQ_REG_OT_CSI_STEP__A 0x1C1004A
4911#define EQ_REG_OT_CSI_STEP__W 4
4912#define EQ_REG_OT_CSI_STEP__M 0xF
4913#define EQ_REG_OT_CSI_STEP_INIT 0x0
4914
4915
4916#define EQ_REG_OT_CSI_OFFSET__A 0x1C1004B
4917#define EQ_REG_OT_CSI_OFFSET__W 7
4918#define EQ_REG_OT_CSI_OFFSET__M 0x7F
4919#define EQ_REG_OT_CSI_OFFSET_INIT 0x0
4920
4921
4922
4923
4924#define EQ_REG_TD_TPS_INIT__A 0x1C10050
4925#define EQ_REG_TD_TPS_INIT__W 1
4926#define EQ_REG_TD_TPS_INIT__M 0x1
4927#define EQ_REG_TD_TPS_INIT_INIT 0x0
4928#define EQ_REG_TD_TPS_INIT_POS 0x0
4929#define EQ_REG_TD_TPS_INIT_NEG 0x1
4930
4931
4932#define EQ_REG_TD_TPS_SYNC__A 0x1C10051
4933#define EQ_REG_TD_TPS_SYNC__W 16
4934#define EQ_REG_TD_TPS_SYNC__M 0xFFFF
4935#define EQ_REG_TD_TPS_SYNC_INIT 0x0
4936#define EQ_REG_TD_TPS_SYNC_ODD 0x35EE
4937#define EQ_REG_TD_TPS_SYNC_EVEN 0xCA11
4938
4939
4940#define EQ_REG_TD_TPS_LEN__A 0x1C10052
4941#define EQ_REG_TD_TPS_LEN__W 6
4942#define EQ_REG_TD_TPS_LEN__M 0x3F
4943#define EQ_REG_TD_TPS_LEN_INIT 0x0
4944#define EQ_REG_TD_TPS_LEN_DEF 0x17
4945#define EQ_REG_TD_TPS_LEN_ID_SUP 0x1F
4946
4947
4948#define EQ_REG_TD_TPS_FRM_NMB__A 0x1C10053
4949#define EQ_REG_TD_TPS_FRM_NMB__W 2
4950#define EQ_REG_TD_TPS_FRM_NMB__M 0x3
4951#define EQ_REG_TD_TPS_FRM_NMB_INIT 0x0
4952#define EQ_REG_TD_TPS_FRM_NMB_1 0x0
4953#define EQ_REG_TD_TPS_FRM_NMB_2 0x1
4954#define EQ_REG_TD_TPS_FRM_NMB_3 0x2
4955#define EQ_REG_TD_TPS_FRM_NMB_4 0x3
4956
4957
4958#define EQ_REG_TD_TPS_CONST__A 0x1C10054
4959#define EQ_REG_TD_TPS_CONST__W 2
4960#define EQ_REG_TD_TPS_CONST__M 0x3
4961#define EQ_REG_TD_TPS_CONST_INIT 0x0
4962#define EQ_REG_TD_TPS_CONST_QPSK 0x0
4963#define EQ_REG_TD_TPS_CONST_16QAM 0x1
4964#define EQ_REG_TD_TPS_CONST_64QAM 0x2
4965
4966
4967#define EQ_REG_TD_TPS_HINFO__A 0x1C10055
4968#define EQ_REG_TD_TPS_HINFO__W 3
4969#define EQ_REG_TD_TPS_HINFO__M 0x7
4970#define EQ_REG_TD_TPS_HINFO_INIT 0x0
4971#define EQ_REG_TD_TPS_HINFO_NH 0x0
4972#define EQ_REG_TD_TPS_HINFO_H1 0x1
4973#define EQ_REG_TD_TPS_HINFO_H2 0x2
4974#define EQ_REG_TD_TPS_HINFO_H4 0x3
4975
4976
4977#define EQ_REG_TD_TPS_CODE_HP__A 0x1C10056
4978#define EQ_REG_TD_TPS_CODE_HP__W 3
4979#define EQ_REG_TD_TPS_CODE_HP__M 0x7
4980#define EQ_REG_TD_TPS_CODE_HP_INIT 0x0
4981#define EQ_REG_TD_TPS_CODE_HP_1_2 0x0
4982#define EQ_REG_TD_TPS_CODE_HP_2_3 0x1
4983#define EQ_REG_TD_TPS_CODE_HP_3_4 0x2
4984#define EQ_REG_TD_TPS_CODE_HP_5_6 0x3
4985#define EQ_REG_TD_TPS_CODE_HP_7_8 0x4
4986
4987
4988#define EQ_REG_TD_TPS_CODE_LP__A 0x1C10057
4989#define EQ_REG_TD_TPS_CODE_LP__W 3
4990#define EQ_REG_TD_TPS_CODE_LP__M 0x7
4991#define EQ_REG_TD_TPS_CODE_LP_INIT 0x0
4992#define EQ_REG_TD_TPS_CODE_LP_1_2 0x0
4993#define EQ_REG_TD_TPS_CODE_LP_2_3 0x1
4994#define EQ_REG_TD_TPS_CODE_LP_3_4 0x2
4995#define EQ_REG_TD_TPS_CODE_LP_5_6 0x3
4996#define EQ_REG_TD_TPS_CODE_LP_7_8 0x4
4997
4998
4999#define EQ_REG_TD_TPS_GUARD__A 0x1C10058
5000#define EQ_REG_TD_TPS_GUARD__W 2
5001#define EQ_REG_TD_TPS_GUARD__M 0x3
5002#define EQ_REG_TD_TPS_GUARD_INIT 0x0
5003#define EQ_REG_TD_TPS_GUARD_32 0x0
5004#define EQ_REG_TD_TPS_GUARD_16 0x1
5005#define EQ_REG_TD_TPS_GUARD_08 0x2
5006#define EQ_REG_TD_TPS_GUARD_04 0x3
5007
5008
5009#define EQ_REG_TD_TPS_TR_MODE__A 0x1C10059
5010#define EQ_REG_TD_TPS_TR_MODE__W 2
5011#define EQ_REG_TD_TPS_TR_MODE__M 0x3
5012#define EQ_REG_TD_TPS_TR_MODE_INIT 0x0
5013#define EQ_REG_TD_TPS_TR_MODE_2K 0x0
5014#define EQ_REG_TD_TPS_TR_MODE_8K 0x1
5015
5016
5017#define EQ_REG_TD_TPS_CELL_ID_HI__A 0x1C1005A
5018#define EQ_REG_TD_TPS_CELL_ID_HI__W 8
5019#define EQ_REG_TD_TPS_CELL_ID_HI__M 0xFF
5020#define EQ_REG_TD_TPS_CELL_ID_HI_INIT 0x0
5021
5022
5023#define EQ_REG_TD_TPS_CELL_ID_LO__A 0x1C1005B
5024#define EQ_REG_TD_TPS_CELL_ID_LO__W 8
5025#define EQ_REG_TD_TPS_CELL_ID_LO__M 0xFF
5026#define EQ_REG_TD_TPS_CELL_ID_LO_INIT 0x0
5027
5028
5029#define EQ_REG_TD_TPS_RSV__A 0x1C1005C
5030#define EQ_REG_TD_TPS_RSV__W 6
5031#define EQ_REG_TD_TPS_RSV__M 0x3F
5032#define EQ_REG_TD_TPS_RSV_INIT 0x0
5033
5034
5035#define EQ_REG_TD_TPS_BCH__A 0x1C1005D
5036#define EQ_REG_TD_TPS_BCH__W 14
5037#define EQ_REG_TD_TPS_BCH__M 0x3FFF
5038#define EQ_REG_TD_TPS_BCH_INIT 0x0
5039
5040
5041#define EQ_REG_TD_SQR_ERR_I__A 0x1C1005E
5042#define EQ_REG_TD_SQR_ERR_I__W 16
5043#define EQ_REG_TD_SQR_ERR_I__M 0xFFFF
5044#define EQ_REG_TD_SQR_ERR_I_INIT 0x0
5045
5046
5047#define EQ_REG_TD_SQR_ERR_Q__A 0x1C1005F
5048#define EQ_REG_TD_SQR_ERR_Q__W 16
5049#define EQ_REG_TD_SQR_ERR_Q__M 0xFFFF
5050#define EQ_REG_TD_SQR_ERR_Q_INIT 0x0
5051
5052
5053#define EQ_REG_TD_SQR_ERR_EXP__A 0x1C10060
5054#define EQ_REG_TD_SQR_ERR_EXP__W 4
5055#define EQ_REG_TD_SQR_ERR_EXP__M 0xF
5056#define EQ_REG_TD_SQR_ERR_EXP_INIT 0x0
5057
5058
5059#define EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061
5060#define EQ_REG_TD_REQ_SMB_CNT__W 16
5061#define EQ_REG_TD_REQ_SMB_CNT__M 0xFFFF
5062#define EQ_REG_TD_REQ_SMB_CNT_INIT 0x0
5063
5064
5065#define EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062
5066#define EQ_REG_TD_TPS_PWR_OFS__W 16
5067#define EQ_REG_TD_TPS_PWR_OFS__M 0xFFFF
5068#define EQ_REG_TD_TPS_PWR_OFS_INIT 0x0
5069
5070
5071
5072
5073
5074
5075
5076
5077
5078#define EC_COMM_EXEC__A 0x2000000
5079#define EC_COMM_EXEC__W 3
5080#define EC_COMM_EXEC__M 0x7
5081#define EC_COMM_EXEC_CTL__B 0
5082#define EC_COMM_EXEC_CTL__W 3
5083#define EC_COMM_EXEC_CTL__M 0x7
5084#define EC_COMM_EXEC_CTL_STOP 0x0
5085#define EC_COMM_EXEC_CTL_ACTIVE 0x1
5086#define EC_COMM_EXEC_CTL_HOLD 0x2
5087#define EC_COMM_EXEC_CTL_STEP 0x3
5088#define EC_COMM_EXEC_CTL_BYPASS_STOP 0x4
5089#define EC_COMM_EXEC_CTL_BYPASS_HOLD 0x6
5090
5091#define EC_COMM_STATE__A 0x2000001
5092#define EC_COMM_STATE__W 16
5093#define EC_COMM_STATE__M 0xFFFF
5094#define EC_COMM_MB__A 0x2000002
5095#define EC_COMM_MB__W 16
5096#define EC_COMM_MB__M 0xFFFF
5097#define EC_COMM_SERVICE0__A 0x2000003
5098#define EC_COMM_SERVICE0__W 16
5099#define EC_COMM_SERVICE0__M 0xFFFF
5100#define EC_COMM_SERVICE1__A 0x2000004
5101#define EC_COMM_SERVICE1__W 16
5102#define EC_COMM_SERVICE1__M 0xFFFF
5103#define EC_COMM_INT_STA__A 0x2000007
5104#define EC_COMM_INT_STA__W 16
5105#define EC_COMM_INT_STA__M 0xFFFF
5106#define EC_COMM_INT_MSK__A 0x2000008
5107#define EC_COMM_INT_MSK__W 16
5108#define EC_COMM_INT_MSK__M 0xFFFF
5109
5110
5111
5112
5113
5114#define EC_SB_SID 0x16
5115
5116
5117
5118
5119
5120#define EC_SB_REG_COMM_EXEC__A 0x2010000
5121#define EC_SB_REG_COMM_EXEC__W 3
5122#define EC_SB_REG_COMM_EXEC__M 0x7
5123#define EC_SB_REG_COMM_EXEC_CTL__B 0
5124#define EC_SB_REG_COMM_EXEC_CTL__W 3
5125#define EC_SB_REG_COMM_EXEC_CTL__M 0x7
5126#define EC_SB_REG_COMM_EXEC_CTL_STOP 0x0
5127#define EC_SB_REG_COMM_EXEC_CTL_ACTIVE 0x1
5128#define EC_SB_REG_COMM_EXEC_CTL_HOLD 0x2
5129
5130#define EC_SB_REG_COMM_STATE__A 0x2010001
5131#define EC_SB_REG_COMM_STATE__W 4
5132#define EC_SB_REG_COMM_STATE__M 0xF
5133#define EC_SB_REG_COMM_MB__A 0x2010002
5134#define EC_SB_REG_COMM_MB__W 2
5135#define EC_SB_REG_COMM_MB__M 0x3
5136#define EC_SB_REG_COMM_MB_CTR__B 0
5137#define EC_SB_REG_COMM_MB_CTR__W 1
5138#define EC_SB_REG_COMM_MB_CTR__M 0x1
5139#define EC_SB_REG_COMM_MB_CTR_OFF 0x0
5140#define EC_SB_REG_COMM_MB_CTR_ON 0x1
5141#define EC_SB_REG_COMM_MB_OBS__B 1
5142#define EC_SB_REG_COMM_MB_OBS__W 1
5143#define EC_SB_REG_COMM_MB_OBS__M 0x2
5144#define EC_SB_REG_COMM_MB_OBS_OFF 0x0
5145#define EC_SB_REG_COMM_MB_OBS_ON 0x2
5146
5147
5148#define EC_SB_REG_TR_MODE__A 0x2010010
5149#define EC_SB_REG_TR_MODE__W 1
5150#define EC_SB_REG_TR_MODE__M 0x1
5151#define EC_SB_REG_TR_MODE_INIT 0x0
5152#define EC_SB_REG_TR_MODE_8K 0x0
5153#define EC_SB_REG_TR_MODE_2K 0x1
5154
5155
5156#define EC_SB_REG_CONST__A 0x2010011
5157#define EC_SB_REG_CONST__W 2
5158#define EC_SB_REG_CONST__M 0x3
5159#define EC_SB_REG_CONST_INIT 0x2
5160#define EC_SB_REG_CONST_QPSK 0x0
5161#define EC_SB_REG_CONST_16QAM 0x1
5162#define EC_SB_REG_CONST_64QAM 0x2
5163
5164
5165#define EC_SB_REG_ALPHA__A 0x2010012
5166#define EC_SB_REG_ALPHA__W 3
5167#define EC_SB_REG_ALPHA__M 0x7
5168
5169#define EC_SB_REG_ALPHA_INIT 0x0
5170
5171#define EC_SB_REG_ALPHA_NH 0x0
5172
5173#define EC_SB_REG_ALPHA_H1 0x1
5174
5175#define EC_SB_REG_ALPHA_H2 0x2
5176
5177#define EC_SB_REG_ALPHA_H4 0x3
5178
5179
5180#define EC_SB_REG_PRIOR__A 0x2010013
5181#define EC_SB_REG_PRIOR__W 1
5182#define EC_SB_REG_PRIOR__M 0x1
5183#define EC_SB_REG_PRIOR_INIT 0x0
5184#define EC_SB_REG_PRIOR_HI 0x0
5185#define EC_SB_REG_PRIOR_LO 0x1
5186
5187
5188#define EC_SB_REG_CSI_HI__A 0x2010014
5189#define EC_SB_REG_CSI_HI__W 5
5190#define EC_SB_REG_CSI_HI__M 0x1F
5191#define EC_SB_REG_CSI_HI_INIT 0x1F
5192#define EC_SB_REG_CSI_HI_MAX 0x1F
5193#define EC_SB_REG_CSI_HI_MIN 0x0
5194#define EC_SB_REG_CSI_HI_TAG 0x0
5195
5196
5197#define EC_SB_REG_CSI_LO__A 0x2010015
5198#define EC_SB_REG_CSI_LO__W 5
5199#define EC_SB_REG_CSI_LO__M 0x1F
5200#define EC_SB_REG_CSI_LO_INIT 0x1F
5201#define EC_SB_REG_CSI_LO_MAX 0x1F
5202#define EC_SB_REG_CSI_LO_MIN 0x0
5203#define EC_SB_REG_CSI_LO_TAG 0x0
5204
5205
5206#define EC_SB_REG_SMB_TGL__A 0x2010016
5207#define EC_SB_REG_SMB_TGL__W 1
5208#define EC_SB_REG_SMB_TGL__M 0x1
5209#define EC_SB_REG_SMB_TGL_OFF 0x0
5210#define EC_SB_REG_SMB_TGL_ON 0x1
5211
5212
5213#define EC_SB_REG_SNR_HI__A 0x2010017
5214#define EC_SB_REG_SNR_HI__W 8
5215#define EC_SB_REG_SNR_HI__M 0xFF
5216#define EC_SB_REG_SNR_HI_INIT 0xFF
5217#define EC_SB_REG_SNR_HI_MAX 0xFF
5218#define EC_SB_REG_SNR_HI_MIN 0x0
5219#define EC_SB_REG_SNR_HI_TAG 0x0
5220
5221
5222#define EC_SB_REG_SNR_MID__A 0x2010018
5223#define EC_SB_REG_SNR_MID__W 8
5224#define EC_SB_REG_SNR_MID__M 0xFF
5225#define EC_SB_REG_SNR_MID_INIT 0xFF
5226#define EC_SB_REG_SNR_MID_MAX 0xFF
5227#define EC_SB_REG_SNR_MID_MIN 0x0
5228#define EC_SB_REG_SNR_MID_TAG 0x0
5229
5230
5231#define EC_SB_REG_SNR_LO__A 0x2010019
5232#define EC_SB_REG_SNR_LO__W 8
5233#define EC_SB_REG_SNR_LO__M 0xFF
5234#define EC_SB_REG_SNR_LO_INIT 0xFF
5235#define EC_SB_REG_SNR_LO_MAX 0xFF
5236#define EC_SB_REG_SNR_LO_MIN 0x0
5237#define EC_SB_REG_SNR_LO_TAG 0x0
5238
5239
5240#define EC_SB_REG_SCALE_MSB__A 0x201001A
5241#define EC_SB_REG_SCALE_MSB__W 6
5242#define EC_SB_REG_SCALE_MSB__M 0x3F
5243#define EC_SB_REG_SCALE_MSB_INIT 0x30
5244#define EC_SB_REG_SCALE_MSB_MAX 0x3F
5245
5246
5247#define EC_SB_REG_SCALE_BIT2__A 0x201001B
5248#define EC_SB_REG_SCALE_BIT2__W 6
5249#define EC_SB_REG_SCALE_BIT2__M 0x3F
5250#define EC_SB_REG_SCALE_BIT2_INIT 0x20
5251#define EC_SB_REG_SCALE_BIT2_MAX 0x3F
5252
5253
5254#define EC_SB_REG_SCALE_LSB__A 0x201001C
5255#define EC_SB_REG_SCALE_LSB__W 6
5256#define EC_SB_REG_SCALE_LSB__M 0x3F
5257#define EC_SB_REG_SCALE_LSB_INIT 0x10
5258#define EC_SB_REG_SCALE_LSB_MAX 0x3F
5259
5260
5261#define EC_SB_REG_CSI_OFS__A 0x201001D
5262#define EC_SB_REG_CSI_OFS__W 4
5263#define EC_SB_REG_CSI_OFS__M 0xF
5264#define EC_SB_REG_CSI_OFS_INIT 0x1
5265#define EC_SB_REG_CSI_OFS_ADD__B 0
5266#define EC_SB_REG_CSI_OFS_ADD__W 3
5267#define EC_SB_REG_CSI_OFS_ADD__M 0x7
5268#define EC_SB_REG_CSI_OFS_DIS__B 3
5269#define EC_SB_REG_CSI_OFS_DIS__W 1
5270#define EC_SB_REG_CSI_OFS_DIS__M 0x8
5271#define EC_SB_REG_CSI_OFS_DIS_ENA 0x0
5272#define EC_SB_REG_CSI_OFS_DIS_DIS 0x8
5273
5274
5275
5276#define EC_SB_SD_RAM__A 0x2020000
5277
5278
5279
5280#define EC_SB_BD0_RAM__A 0x2030000
5281
5282
5283
5284#define EC_SB_BD1_RAM__A 0x2040000
5285
5286
5287
5288
5289
5290#define EC_VD_SID 0x17
5291
5292
5293
5294
5295
5296#define EC_VD_REG_COMM_EXEC__A 0x2090000
5297#define EC_VD_REG_COMM_EXEC__W 3
5298#define EC_VD_REG_COMM_EXEC__M 0x7
5299#define EC_VD_REG_COMM_EXEC_CTL__B 0
5300#define EC_VD_REG_COMM_EXEC_CTL__W 3
5301#define EC_VD_REG_COMM_EXEC_CTL__M 0x7
5302#define EC_VD_REG_COMM_EXEC_CTL_STOP 0x0
5303#define EC_VD_REG_COMM_EXEC_CTL_ACTIVE 0x1
5304#define EC_VD_REG_COMM_EXEC_CTL_HOLD 0x2
5305
5306#define EC_VD_REG_COMM_STATE__A 0x2090001
5307#define EC_VD_REG_COMM_STATE__W 4
5308#define EC_VD_REG_COMM_STATE__M 0xF
5309#define EC_VD_REG_COMM_MB__A 0x2090002
5310#define EC_VD_REG_COMM_MB__W 2
5311#define EC_VD_REG_COMM_MB__M 0x3
5312#define EC_VD_REG_COMM_MB_CTR__B 0
5313#define EC_VD_REG_COMM_MB_CTR__W 1
5314#define EC_VD_REG_COMM_MB_CTR__M 0x1
5315#define EC_VD_REG_COMM_MB_CTR_OFF 0x0
5316#define EC_VD_REG_COMM_MB_CTR_ON 0x1
5317#define EC_VD_REG_COMM_MB_OBS__B 1
5318#define EC_VD_REG_COMM_MB_OBS__W 1
5319#define EC_VD_REG_COMM_MB_OBS__M 0x2
5320#define EC_VD_REG_COMM_MB_OBS_OFF 0x0
5321#define EC_VD_REG_COMM_MB_OBS_ON 0x2
5322
5323#define EC_VD_REG_COMM_SERVICE0__A 0x2090003
5324#define EC_VD_REG_COMM_SERVICE0__W 16
5325#define EC_VD_REG_COMM_SERVICE0__M 0xFFFF
5326#define EC_VD_REG_COMM_SERVICE1__A 0x2090004
5327#define EC_VD_REG_COMM_SERVICE1__W 16
5328#define EC_VD_REG_COMM_SERVICE1__M 0xFFFF
5329#define EC_VD_REG_COMM_INT_STA__A 0x2090007
5330#define EC_VD_REG_COMM_INT_STA__W 1
5331#define EC_VD_REG_COMM_INT_STA__M 0x1
5332#define EC_VD_REG_COMM_INT_STA_BER_RDY__B 0
5333#define EC_VD_REG_COMM_INT_STA_BER_RDY__W 1
5334#define EC_VD_REG_COMM_INT_STA_BER_RDY__M 0x1
5335
5336#define EC_VD_REG_COMM_INT_MSK__A 0x2090008
5337#define EC_VD_REG_COMM_INT_MSK__W 1
5338#define EC_VD_REG_COMM_INT_MSK__M 0x1
5339#define EC_VD_REG_COMM_INT_MSK_BER_RDY__B 0
5340#define EC_VD_REG_COMM_INT_MSK_BER_RDY__W 1
5341#define EC_VD_REG_COMM_INT_MSK_BER_RDY__M 0x1
5342
5343
5344#define EC_VD_REG_FORCE__A 0x2090010
5345#define EC_VD_REG_FORCE__W 2
5346#define EC_VD_REG_FORCE__M 0x3
5347#define EC_VD_REG_FORCE_INIT 0x0
5348#define EC_VD_REG_FORCE_FREE 0x0
5349#define EC_VD_REG_FORCE_PROP 0x1
5350#define EC_VD_REG_FORCE_FORCED 0x2
5351#define EC_VD_REG_FORCE_FIXED 0x3
5352
5353
5354#define EC_VD_REG_SET_CODERATE__A 0x2090011
5355#define EC_VD_REG_SET_CODERATE__W 3
5356#define EC_VD_REG_SET_CODERATE__M 0x7
5357#define EC_VD_REG_SET_CODERATE_INIT 0x0
5358#define EC_VD_REG_SET_CODERATE_C1_2 0x0
5359#define EC_VD_REG_SET_CODERATE_C2_3 0x1
5360#define EC_VD_REG_SET_CODERATE_C3_4 0x2
5361#define EC_VD_REG_SET_CODERATE_C5_6 0x3
5362#define EC_VD_REG_SET_CODERATE_C7_8 0x4
5363
5364
5365#define EC_VD_REG_REQ_SMB_CNT__A 0x2090012
5366#define EC_VD_REG_REQ_SMB_CNT__W 16
5367#define EC_VD_REG_REQ_SMB_CNT__M 0xFFFF
5368#define EC_VD_REG_REQ_SMB_CNT_INIT 0x0
5369
5370
5371#define EC_VD_REG_REQ_BIT_CNT__A 0x2090013
5372#define EC_VD_REG_REQ_BIT_CNT__W 16
5373#define EC_VD_REG_REQ_BIT_CNT__M 0xFFFF
5374#define EC_VD_REG_REQ_BIT_CNT_INIT 0xFFF
5375
5376
5377#define EC_VD_REG_RLK_ENA__A 0x2090014
5378#define EC_VD_REG_RLK_ENA__W 1
5379#define EC_VD_REG_RLK_ENA__M 0x1
5380#define EC_VD_REG_RLK_ENA_INIT 0x0
5381#define EC_VD_REG_RLK_ENA_OFF 0x0
5382#define EC_VD_REG_RLK_ENA_ON 0x1
5383
5384
5385#define EC_VD_REG_VAL__A 0x2090015
5386#define EC_VD_REG_VAL__W 2
5387#define EC_VD_REG_VAL__M 0x3
5388#define EC_VD_REG_VAL_INIT 0x0
5389#define EC_VD_REG_VAL_CODE 0x1
5390#define EC_VD_REG_VAL_CNT 0x2
5391
5392
5393#define EC_VD_REG_GET_CODERATE__A 0x2090016
5394#define EC_VD_REG_GET_CODERATE__W 3
5395#define EC_VD_REG_GET_CODERATE__M 0x7
5396#define EC_VD_REG_GET_CODERATE_INIT 0x0
5397#define EC_VD_REG_GET_CODERATE_C1_2 0x0
5398#define EC_VD_REG_GET_CODERATE_C2_3 0x1
5399#define EC_VD_REG_GET_CODERATE_C3_4 0x2
5400#define EC_VD_REG_GET_CODERATE_C5_6 0x3
5401#define EC_VD_REG_GET_CODERATE_C7_8 0x4
5402
5403
5404#define EC_VD_REG_ERR_BIT_CNT__A 0x2090017
5405#define EC_VD_REG_ERR_BIT_CNT__W 16
5406#define EC_VD_REG_ERR_BIT_CNT__M 0xFFFF
5407#define EC_VD_REG_ERR_BIT_CNT_INIT 0xFFFF
5408
5409
5410#define EC_VD_REG_IN_BIT_CNT__A 0x2090018
5411#define EC_VD_REG_IN_BIT_CNT__W 16
5412#define EC_VD_REG_IN_BIT_CNT__M 0xFFFF
5413#define EC_VD_REG_IN_BIT_CNT_INIT 0x0
5414
5415
5416#define EC_VD_REG_STS__A 0x2090019
5417#define EC_VD_REG_STS__W 1
5418#define EC_VD_REG_STS__M 0x1
5419#define EC_VD_REG_STS_INIT 0x0
5420#define EC_VD_REG_STS_NO_LOCK 0x0
5421#define EC_VD_REG_STS_IN_LOCK 0x1
5422
5423
5424#define EC_VD_REG_RLK_CNT__A 0x209001A
5425#define EC_VD_REG_RLK_CNT__W 16
5426#define EC_VD_REG_RLK_CNT__M 0xFFFF
5427#define EC_VD_REG_RLK_CNT_INIT 0x0
5428
5429
5430
5431#define EC_VD_TB0_RAM__A 0x20A0000
5432
5433
5434
5435#define EC_VD_TB1_RAM__A 0x20B0000
5436
5437
5438
5439#define EC_VD_TB2_RAM__A 0x20C0000
5440
5441
5442
5443#define EC_VD_TB3_RAM__A 0x20D0000
5444
5445
5446
5447#define EC_VD_RE_RAM__A 0x2100000
5448
5449
5450
5451
5452
5453#define EC_OD_SID 0x18
5454
5455
5456
5457
5458
5459
5460#define EC_OD_REG_COMM_EXEC__A 0x2110000
5461#define EC_OD_REG_COMM_EXEC__W 3
5462#define EC_OD_REG_COMM_EXEC__M 0x7
5463#define EC_OD_REG_COMM_EXEC_CTL__B 0
5464#define EC_OD_REG_COMM_EXEC_CTL__W 3
5465#define EC_OD_REG_COMM_EXEC_CTL__M 0x7
5466#define EC_OD_REG_COMM_EXEC_CTL_STOP 0x0
5467#define EC_OD_REG_COMM_EXEC_CTL_ACTIVE 0x1
5468#define EC_OD_REG_COMM_EXEC_CTL_HOLD 0x2
5469#define EC_OD_REG_COMM_EXEC_CTL_STEP 0x3
5470
5471
5472#define EC_OD_REG_COMM_MB__A 0x2110002
5473#define EC_OD_REG_COMM_MB__W 3
5474#define EC_OD_REG_COMM_MB__M 0x7
5475#define EC_OD_REG_COMM_MB_CTR__B 0
5476#define EC_OD_REG_COMM_MB_CTR__W 1
5477#define EC_OD_REG_COMM_MB_CTR__M 0x1
5478#define EC_OD_REG_COMM_MB_CTR_OFF 0x0
5479#define EC_OD_REG_COMM_MB_CTR_ON 0x1
5480#define EC_OD_REG_COMM_MB_OBS__B 1
5481#define EC_OD_REG_COMM_MB_OBS__W 1
5482#define EC_OD_REG_COMM_MB_OBS__M 0x2
5483#define EC_OD_REG_COMM_MB_OBS_OFF 0x0
5484#define EC_OD_REG_COMM_MB_OBS_ON 0x2
5485
5486#define EC_OD_REG_COMM_SERVICE0__A 0x2110003
5487#define EC_OD_REG_COMM_SERVICE0__W 10
5488#define EC_OD_REG_COMM_SERVICE0__M 0x3FF
5489#define EC_OD_REG_COMM_SERVICE1__A 0x2110004
5490#define EC_OD_REG_COMM_SERVICE1__W 11
5491#define EC_OD_REG_COMM_SERVICE1__M 0x7FF
5492
5493#define EC_OD_REG_COMM_ACTIVATE__A 0x2110005
5494#define EC_OD_REG_COMM_ACTIVATE__W 2
5495#define EC_OD_REG_COMM_ACTIVATE__M 0x3
5496
5497#define EC_OD_REG_COMM_COUNT__A 0x2110006
5498#define EC_OD_REG_COMM_COUNT__W 16
5499#define EC_OD_REG_COMM_COUNT__M 0xFFFF
5500
5501#define EC_OD_REG_COMM_INT_STA__A 0x2110007
5502#define EC_OD_REG_COMM_INT_STA__W 2
5503#define EC_OD_REG_COMM_INT_STA__M 0x3
5504#define EC_OD_REG_COMM_INT_STA_IN_SYNC__B 0
5505#define EC_OD_REG_COMM_INT_STA_IN_SYNC__W 1
5506#define EC_OD_REG_COMM_INT_STA_IN_SYNC__M 0x1
5507#define EC_OD_REG_COMM_INT_STA_LOST_SYNC__B 1
5508#define EC_OD_REG_COMM_INT_STA_LOST_SYNC__W 1
5509#define EC_OD_REG_COMM_INT_STA_LOST_SYNC__M 0x2
5510
5511
5512#define EC_OD_REG_COMM_INT_MSK__A 0x2110008
5513#define EC_OD_REG_COMM_INT_MSK__W 2
5514#define EC_OD_REG_COMM_INT_MSK__M 0x3
5515#define EC_OD_REG_COMM_INT_MSK_IN_SYNC__B 0
5516#define EC_OD_REG_COMM_INT_MSK_IN_SYNC__W 1
5517#define EC_OD_REG_COMM_INT_MSK_IN_SYNC__M 0x1
5518#define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__B 1
5519#define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__W 1
5520#define EC_OD_REG_COMM_INT_MSK_LOST_SYNC__M 0x2
5521
5522
5523#define EC_OD_REG_SYNC__A 0x2110010
5524#define EC_OD_REG_SYNC__W 12
5525#define EC_OD_REG_SYNC__M 0xFFF
5526#define EC_OD_REG_SYNC_NR_SYNC__B 0
5527#define EC_OD_REG_SYNC_NR_SYNC__W 5
5528#define EC_OD_REG_SYNC_NR_SYNC__M 0x1F
5529#define EC_OD_REG_SYNC_IN_SYNC__B 5
5530#define EC_OD_REG_SYNC_IN_SYNC__W 4
5531#define EC_OD_REG_SYNC_IN_SYNC__M 0x1E0
5532#define EC_OD_REG_SYNC_OUT_SYNC__B 9
5533#define EC_OD_REG_SYNC_OUT_SYNC__W 3
5534#define EC_OD_REG_SYNC_OUT_SYNC__M 0xE00
5535
5536
5537#define EC_OD_REG_NOSYNC__A 0x2110011
5538#define EC_OD_REG_NOSYNC__W 8
5539#define EC_OD_REG_NOSYNC__M 0xFF
5540
5541
5542
5543#define EC_OD_DEINT_RAM__A 0x2120000
5544
5545
5546
5547
5548
5549#define EC_RS_SID 0x19
5550
5551
5552
5553
5554
5555#define EC_RS_REG_COMM_EXEC__A 0x2130000
5556#define EC_RS_REG_COMM_EXEC__W 3
5557#define EC_RS_REG_COMM_EXEC__M 0x7
5558#define EC_RS_REG_COMM_EXEC_CTL__B 0
5559#define EC_RS_REG_COMM_EXEC_CTL__W 3
5560#define EC_RS_REG_COMM_EXEC_CTL__M 0x7
5561#define EC_RS_REG_COMM_EXEC_CTL_STOP 0x0
5562#define EC_RS_REG_COMM_EXEC_CTL_ACTIVE 0x1
5563#define EC_RS_REG_COMM_EXEC_CTL_HOLD 0x2
5564
5565#define EC_RS_REG_COMM_STATE__A 0x2130001
5566#define EC_RS_REG_COMM_STATE__W 4
5567#define EC_RS_REG_COMM_STATE__M 0xF
5568#define EC_RS_REG_COMM_MB__A 0x2130002
5569#define EC_RS_REG_COMM_MB__W 2
5570#define EC_RS_REG_COMM_MB__M 0x3
5571#define EC_RS_REG_COMM_MB_CTR__B 0
5572#define EC_RS_REG_COMM_MB_CTR__W 1
5573#define EC_RS_REG_COMM_MB_CTR__M 0x1
5574#define EC_RS_REG_COMM_MB_CTR_OFF 0x0
5575#define EC_RS_REG_COMM_MB_CTR_ON 0x1
5576#define EC_RS_REG_COMM_MB_OBS__B 1
5577#define EC_RS_REG_COMM_MB_OBS__W 1
5578#define EC_RS_REG_COMM_MB_OBS__M 0x2
5579#define EC_RS_REG_COMM_MB_OBS_OFF 0x0
5580#define EC_RS_REG_COMM_MB_OBS_ON 0x2
5581
5582#define EC_RS_REG_COMM_SERVICE0__A 0x2130003
5583#define EC_RS_REG_COMM_SERVICE0__W 16
5584#define EC_RS_REG_COMM_SERVICE0__M 0xFFFF
5585#define EC_RS_REG_COMM_SERVICE1__A 0x2130004
5586#define EC_RS_REG_COMM_SERVICE1__W 16
5587#define EC_RS_REG_COMM_SERVICE1__M 0xFFFF
5588#define EC_RS_REG_COMM_INT_STA__A 0x2130007
5589#define EC_RS_REG_COMM_INT_STA__W 1
5590#define EC_RS_REG_COMM_INT_STA__M 0x1
5591#define EC_RS_REG_COMM_INT_STA_BER_RDY__B 0
5592#define EC_RS_REG_COMM_INT_STA_BER_RDY__W 1
5593#define EC_RS_REG_COMM_INT_STA_BER_RDY__M 0x1
5594
5595#define EC_RS_REG_COMM_INT_MSK__A 0x2130008
5596#define EC_RS_REG_COMM_INT_MSK__W 1
5597#define EC_RS_REG_COMM_INT_MSK__M 0x1
5598#define EC_RS_REG_COMM_INT_MSK_BER_RDY__B 0
5599#define EC_RS_REG_COMM_INT_MSK_BER_RDY__W 1
5600#define EC_RS_REG_COMM_INT_MSK_BER_RDY__M 0x1
5601
5602
5603#define EC_RS_REG_REQ_PCK_CNT__A 0x2130010
5604#define EC_RS_REG_REQ_PCK_CNT__W 16
5605#define EC_RS_REG_REQ_PCK_CNT__M 0xFFFF
5606#define EC_RS_REG_REQ_PCK_CNT_INIT 0xFF
5607
5608
5609#define EC_RS_REG_VAL__A 0x2130011
5610#define EC_RS_REG_VAL__W 1
5611#define EC_RS_REG_VAL__M 0x1
5612#define EC_RS_REG_VAL_INIT 0x0
5613#define EC_RS_REG_VAL_PCK 0x1
5614
5615
5616#define EC_RS_REG_ERR_PCK_CNT__A 0x2130012
5617#define EC_RS_REG_ERR_PCK_CNT__W 16
5618#define EC_RS_REG_ERR_PCK_CNT__M 0xFFFF
5619#define EC_RS_REG_ERR_PCK_CNT_INIT 0xFFFF
5620
5621
5622#define EC_RS_REG_ERR_SMB_CNT__A 0x2130013
5623#define EC_RS_REG_ERR_SMB_CNT__W 16
5624#define EC_RS_REG_ERR_SMB_CNT__M 0xFFFF
5625#define EC_RS_REG_ERR_SMB_CNT_INIT 0xFFFF
5626
5627
5628#define EC_RS_REG_ERR_BIT_CNT__A 0x2130014
5629#define EC_RS_REG_ERR_BIT_CNT__W 16
5630#define EC_RS_REG_ERR_BIT_CNT__M 0xFFFF
5631#define EC_RS_REG_ERR_BIT_CNT_INIT 0xFFFF
5632
5633
5634#define EC_RS_REG_IN_PCK_CNT__A 0x2130015
5635#define EC_RS_REG_IN_PCK_CNT__W 16
5636#define EC_RS_REG_IN_PCK_CNT__M 0xFFFF
5637#define EC_RS_REG_IN_PCK_CNT_INIT 0x0
5638
5639
5640
5641#define EC_RS_EC_RAM__A 0x2140000
5642
5643
5644
5645
5646
5647#define EC_OC_SID 0x1A
5648
5649
5650
5651
5652
5653
5654#define EC_OC_REG_COMM_EXEC__A 0x2150000
5655#define EC_OC_REG_COMM_EXEC__W 3
5656#define EC_OC_REG_COMM_EXEC__M 0x7
5657#define EC_OC_REG_COMM_EXEC_CTL__B 0
5658#define EC_OC_REG_COMM_EXEC_CTL__W 3
5659#define EC_OC_REG_COMM_EXEC_CTL__M 0x7
5660#define EC_OC_REG_COMM_EXEC_CTL_STOP 0x0
5661#define EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1
5662#define EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2
5663#define EC_OC_REG_COMM_EXEC_CTL_STEP 0x3
5664
5665#define EC_OC_REG_COMM_STATE__A 0x2150001
5666#define EC_OC_REG_COMM_STATE__W 4
5667#define EC_OC_REG_COMM_STATE__M 0xF
5668
5669#define EC_OC_REG_COMM_MB__A 0x2150002
5670#define EC_OC_REG_COMM_MB__W 2
5671#define EC_OC_REG_COMM_MB__M 0x3
5672#define EC_OC_REG_COMM_MB_CTR__B 0
5673#define EC_OC_REG_COMM_MB_CTR__W 1
5674#define EC_OC_REG_COMM_MB_CTR__M 0x1
5675#define EC_OC_REG_COMM_MB_CTR_OFF 0x0
5676#define EC_OC_REG_COMM_MB_CTR_ON 0x1
5677#define EC_OC_REG_COMM_MB_OBS__B 1
5678#define EC_OC_REG_COMM_MB_OBS__W 1
5679#define EC_OC_REG_COMM_MB_OBS__M 0x2
5680#define EC_OC_REG_COMM_MB_OBS_OFF 0x0
5681#define EC_OC_REG_COMM_MB_OBS_ON 0x2
5682
5683
5684#define EC_OC_REG_COMM_SERVICE0__A 0x2150003
5685#define EC_OC_REG_COMM_SERVICE0__W 10
5686#define EC_OC_REG_COMM_SERVICE0__M 0x3FF
5687
5688#define EC_OC_REG_COMM_SERVICE1__A 0x2150004
5689#define EC_OC_REG_COMM_SERVICE1__W 11
5690#define EC_OC_REG_COMM_SERVICE1__M 0x7FF
5691
5692#define EC_OC_REG_COMM_INT_STA__A 0x2150007
5693#define EC_OC_REG_COMM_INT_STA__W 6
5694#define EC_OC_REG_COMM_INT_STA__M 0x3F
5695#define EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__B 0
5696#define EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__W 1
5697#define EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__M 0x1
5698#define EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__B 1
5699#define EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__W 1
5700#define EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__M 0x2
5701#define EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__B 2
5702#define EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__W 1
5703#define EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__M 0x4
5704#define EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__B 3
5705#define EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__W 1
5706#define EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__M 0x8
5707#define EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__B 4
5708#define EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__W 1
5709#define EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__M 0x10
5710#define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__B 5
5711#define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__W 1
5712#define EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__M 0x20
5713
5714
5715#define EC_OC_REG_COMM_INT_MSK__A 0x2150008
5716#define EC_OC_REG_COMM_INT_MSK__W 6
5717#define EC_OC_REG_COMM_INT_MSK__M 0x3F
5718#define EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__B 0
5719#define EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__W 1
5720#define EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__M 0x1
5721#define EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__B 1
5722#define EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__W 1
5723#define EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__M 0x2
5724#define EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__B 2
5725#define EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__W 1
5726#define EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__M 0x4
5727#define EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__B 3
5728#define EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__W 1
5729#define EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__M 0x8
5730#define EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__B 4
5731#define EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__W 1
5732#define EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__M 0x10
5733#define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__B 5
5734#define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__W 1
5735#define EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__M 0x20
5736
5737
5738#define EC_OC_REG_OC_MODE_LOP__A 0x2150010
5739#define EC_OC_REG_OC_MODE_LOP__W 16
5740#define EC_OC_REG_OC_MODE_LOP__M 0xFFFF
5741#define EC_OC_REG_OC_MODE_LOP_INIT 0x0
5742
5743#define EC_OC_REG_OC_MODE_LOP_PAR_ENA__B 0
5744#define EC_OC_REG_OC_MODE_LOP_PAR_ENA__W 1
5745#define EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1
5746#define EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0
5747#define EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1
5748
5749#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__B 2
5750#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__W 1
5751#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4
5752#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0
5753#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_DYNAMIC 0x4
5754
5755#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__B 4
5756#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__W 1
5757#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__M 0x10
5758#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_DISABLE 0x0
5759#define EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_ENABLE 0x10
5760
5761#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__B 5
5762#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__W 1
5763#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__M 0x20
5764#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_DISABLE 0x0
5765#define EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_ENABLE 0x20
5766
5767#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__B 6
5768#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__W 1
5769#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__M 0x40
5770#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_DISABLE 0x0
5771#define EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_ENABLE 0x40
5772
5773#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__B 7
5774#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__W 1
5775#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80
5776#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_PARALLEL 0x0
5777#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80
5778
5779#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__B 8
5780#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__W 1
5781#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__M 0x100
5782#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_ENABLE 0x0
5783#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_DISABLE 0x100
5784
5785#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__B 9
5786#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__W 1
5787#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__M 0x200
5788#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_STRETCH 0x0
5789#define EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_GATE 0x200
5790
5791#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__B 10
5792#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__W 1
5793#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__M 0x400
5794#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_CONTINOUS 0x0
5795#define EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_BURST 0x400
5796
5797#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__B 11
5798#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__W 1
5799#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__M 0x800
5800#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_ENABLE 0x0
5801#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_DISABLE 0x800
5802
5803#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__B 12
5804#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__W 1
5805#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__M 0x1000
5806#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_ENABLE 0x0
5807#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_DISABLE 0x1000
5808
5809#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__B 13
5810#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__W 1
5811#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__M 0x2000
5812#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_ENABLE 0x0
5813#define EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_DISABLE 0x2000
5814
5815#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__B 14
5816#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__W 1
5817#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__M 0x4000
5818#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_ENABLE 0x0
5819#define EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_DISABLE 0x4000
5820
5821#define EC_OC_REG_OC_MODE_LOP_DER_ENA__B 15
5822#define EC_OC_REG_OC_MODE_LOP_DER_ENA__W 1
5823#define EC_OC_REG_OC_MODE_LOP_DER_ENA__M 0x8000
5824#define EC_OC_REG_OC_MODE_LOP_DER_ENA_ENABLE 0x0
5825#define EC_OC_REG_OC_MODE_LOP_DER_ENA_DISABLE 0x8000
5826
5827
5828#define EC_OC_REG_OC_MODE_HIP__A 0x2150011
5829#define EC_OC_REG_OC_MODE_HIP__W 14
5830#define EC_OC_REG_OC_MODE_HIP__M 0x3FFF
5831#define EC_OC_REG_OC_MODE_HIP_INIT 0x0
5832
5833#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__B 0
5834#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__W 1
5835#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__M 0x1
5836#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_OBSERVE 0x0
5837#define EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_CONTROL 0x1
5838
5839#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__B 1
5840#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__W 1
5841#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__M 0x2
5842#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG_SYNC 0x0
5843#define EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG 0x2
5844
5845#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__B 2
5846#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__W 1
5847#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__M 0x4
5848#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_OBSERVE 0x0
5849#define EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_CONTROL 0x4
5850
5851#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__B 3
5852#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__W 1
5853#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__M 0x8
5854#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MONITOR 0x0
5855#define EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MPEG 0x8
5856
5857#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__B 4
5858#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__W 1
5859#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__M 0x10
5860#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MPEG 0x0
5861#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10
5862
5863#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__B 5
5864#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__W 1
5865#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__M 0x20
5866#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_DISABLE 0x0
5867#define EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_ENABLE 0x20
5868
5869#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__B 6
5870#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__W 1
5871#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__M 0x40
5872#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_ENABLE 0x0
5873#define EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_DISABLE 0x40
5874
5875#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__B 7
5876#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__W 1
5877#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__M 0x80
5878#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_DISABLE 0x0
5879#define EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_ENABLE 0x80
5880
5881#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__B 8
5882#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__W 1
5883#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__M 0x100
5884#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_DISABLE 0x0
5885#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_ENABLE 0x100
5886
5887#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__B 9
5888#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__W 1
5889#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200
5890#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0
5891#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200
5892
5893#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__B 10
5894#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__W 1
5895#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__M 0x400
5896#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_DISABLE 0x0
5897#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_ENABLE 0x400
5898
5899#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__B 11
5900#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__W 1
5901#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__M 0x800
5902#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_DISABLE 0x0
5903#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_ENABLE 0x800
5904
5905#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__B 12
5906#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__W 1
5907#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__M 0x1000
5908#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_ZER 0x0
5909#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_MON 0x1000
5910
5911#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__B 13
5912#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__W 1
5913#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__M 0x2000
5914#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_ZER 0x0
5915#define EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_MPG 0x2000
5916
5917
5918#define EC_OC_REG_OC_MPG_SIO__A 0x2150012
5919#define EC_OC_REG_OC_MPG_SIO__W 12
5920#define EC_OC_REG_OC_MPG_SIO__M 0xFFF
5921#define EC_OC_REG_OC_MPG_SIO_INIT 0xFFF
5922
5923#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__B 0
5924#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__W 1
5925#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__M 0x1
5926#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_OUTPUT 0x0
5927#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_INPUT 0x1
5928
5929#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__B 1
5930#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__W 1
5931#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__M 0x2
5932#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_OUTPUT 0x0
5933#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_INPUT 0x2
5934
5935#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__B 2
5936#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__W 1
5937#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__M 0x4
5938#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_OUTPUT 0x0
5939#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_INPUT 0x4
5940
5941#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__B 3
5942#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__W 1
5943#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__M 0x8
5944#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_OUTPUT 0x0
5945#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_INPUT 0x8
5946
5947#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__B 4
5948#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__W 1
5949#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__M 0x10
5950#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_OUTPUT 0x0
5951#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_INPUT 0x10
5952
5953#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__B 5
5954#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__W 1
5955#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__M 0x20
5956#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_OUTPUT 0x0
5957#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_INPUT 0x20
5958
5959#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__B 6
5960#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__W 1
5961#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__M 0x40
5962#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_OUTPUT 0x0
5963#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_INPUT 0x40
5964
5965#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__B 7
5966#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__W 1
5967#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__M 0x80
5968#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_OUTPUT 0x0
5969#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_INPUT 0x80
5970
5971#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__B 8
5972#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__W 1
5973#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__M 0x100
5974#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_OUTPUT 0x0
5975#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_INPUT 0x100
5976
5977#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__B 9
5978#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__W 1
5979#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__M 0x200
5980#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_OUTPUT 0x0
5981#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_INPUT 0x200
5982
5983#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__B 10
5984#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__W 1
5985#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__M 0x400
5986#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_OUTPUT 0x0
5987#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_INPUT 0x400
5988
5989#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__B 11
5990#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__W 1
5991#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__M 0x800
5992#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_OUTPUT 0x0
5993#define EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_INPUT 0x800
5994
5995
5996#define EC_OC_REG_OC_MON_SIO__A 0x2150013
5997#define EC_OC_REG_OC_MON_SIO__W 12
5998#define EC_OC_REG_OC_MON_SIO__M 0xFFF
5999#define EC_OC_REG_OC_MON_SIO_INIT 0xFFF
6000
6001#define EC_OC_REG_OC_MON_SIO_MON_SIO_0__B 0
6002#define EC_OC_REG_OC_MON_SIO_MON_SIO_0__W 1
6003#define EC_OC_REG_OC_MON_SIO_MON_SIO_0__M 0x1
6004#define EC_OC_REG_OC_MON_SIO_MON_SIO_0_OUTPUT 0x0
6005#define EC_OC_REG_OC_MON_SIO_MON_SIO_0_INPUT 0x1
6006
6007#define EC_OC_REG_OC_MON_SIO_MON_SIO_1__B 1
6008#define EC_OC_REG_OC_MON_SIO_MON_SIO_1__W 1
6009#define EC_OC_REG_OC_MON_SIO_MON_SIO_1__M 0x2
6010#define EC_OC_REG_OC_MON_SIO_MON_SIO_1_OUTPUT 0x0
6011#define EC_OC_REG_OC_MON_SIO_MON_SIO_1_INPUT 0x2
6012
6013#define EC_OC_REG_OC_MON_SIO_MON_SIO_2__B 2
6014#define EC_OC_REG_OC_MON_SIO_MON_SIO_2__W 1
6015#define EC_OC_REG_OC_MON_SIO_MON_SIO_2__M 0x4
6016#define EC_OC_REG_OC_MON_SIO_MON_SIO_2_OUTPUT 0x0
6017#define EC_OC_REG_OC_MON_SIO_MON_SIO_2_INPUT 0x4
6018
6019#define EC_OC_REG_OC_MON_SIO_MON_SIO_3__B 3
6020#define EC_OC_REG_OC_MON_SIO_MON_SIO_3__W 1
6021#define EC_OC_REG_OC_MON_SIO_MON_SIO_3__M 0x8
6022#define EC_OC_REG_OC_MON_SIO_MON_SIO_3_OUTPUT 0x0
6023#define EC_OC_REG_OC_MON_SIO_MON_SIO_3_INPUT 0x8
6024
6025#define EC_OC_REG_OC_MON_SIO_MON_SIO_4__B 4
6026#define EC_OC_REG_OC_MON_SIO_MON_SIO_4__W 1
6027#define EC_OC_REG_OC_MON_SIO_MON_SIO_4__M 0x10
6028#define EC_OC_REG_OC_MON_SIO_MON_SIO_4_OUTPUT 0x0
6029#define EC_OC_REG_OC_MON_SIO_MON_SIO_4_INPUT 0x10
6030
6031#define EC_OC_REG_OC_MON_SIO_MON_SIO_5__B 5
6032#define EC_OC_REG_OC_MON_SIO_MON_SIO_5__W 1
6033#define EC_OC_REG_OC_MON_SIO_MON_SIO_5__M 0x20
6034#define EC_OC_REG_OC_MON_SIO_MON_SIO_5_OUTPUT 0x0
6035#define EC_OC_REG_OC_MON_SIO_MON_SIO_5_INPUT 0x20
6036
6037#define EC_OC_REG_OC_MON_SIO_MON_SIO_6__B 6
6038#define EC_OC_REG_OC_MON_SIO_MON_SIO_6__W 1
6039#define EC_OC_REG_OC_MON_SIO_MON_SIO_6__M 0x40
6040#define EC_OC_REG_OC_MON_SIO_MON_SIO_6_OUTPUT 0x0
6041#define EC_OC_REG_OC_MON_SIO_MON_SIO_6_INPUT 0x40
6042
6043#define EC_OC_REG_OC_MON_SIO_MON_SIO_7__B 7
6044#define EC_OC_REG_OC_MON_SIO_MON_SIO_7__W 1
6045#define EC_OC_REG_OC_MON_SIO_MON_SIO_7__M 0x80
6046#define EC_OC_REG_OC_MON_SIO_MON_SIO_7_OUTPUT 0x0
6047#define EC_OC_REG_OC_MON_SIO_MON_SIO_7_INPUT 0x80
6048
6049#define EC_OC_REG_OC_MON_SIO_MON_SIO_8__B 8
6050#define EC_OC_REG_OC_MON_SIO_MON_SIO_8__W 1
6051#define EC_OC_REG_OC_MON_SIO_MON_SIO_8__M 0x100
6052#define EC_OC_REG_OC_MON_SIO_MON_SIO_8_OUTPUT 0x0
6053#define EC_OC_REG_OC_MON_SIO_MON_SIO_8_INPUT 0x100
6054
6055#define EC_OC_REG_OC_MON_SIO_MON_SIO_9__B 9
6056#define EC_OC_REG_OC_MON_SIO_MON_SIO_9__W 1
6057#define EC_OC_REG_OC_MON_SIO_MON_SIO_9__M 0x200
6058#define EC_OC_REG_OC_MON_SIO_MON_SIO_9_OUTPUT 0x0
6059#define EC_OC_REG_OC_MON_SIO_MON_SIO_9_INPUT 0x200
6060
6061#define EC_OC_REG_OC_MON_SIO_MON_SIO_10__B 10
6062#define EC_OC_REG_OC_MON_SIO_MON_SIO_10__W 1
6063#define EC_OC_REG_OC_MON_SIO_MON_SIO_10__M 0x400
6064#define EC_OC_REG_OC_MON_SIO_MON_SIO_10_OUTPUT 0x0
6065#define EC_OC_REG_OC_MON_SIO_MON_SIO_10_INPUT 0x400
6066
6067#define EC_OC_REG_OC_MON_SIO_MON_SIO_11__B 11
6068#define EC_OC_REG_OC_MON_SIO_MON_SIO_11__W 1
6069#define EC_OC_REG_OC_MON_SIO_MON_SIO_11__M 0x800
6070#define EC_OC_REG_OC_MON_SIO_MON_SIO_11_OUTPUT 0x0
6071#define EC_OC_REG_OC_MON_SIO_MON_SIO_11_INPUT 0x800
6072
6073
6074#define EC_OC_REG_DTO_INC_LOP__A 0x2150014
6075#define EC_OC_REG_DTO_INC_LOP__W 16
6076#define EC_OC_REG_DTO_INC_LOP__M 0xFFFF
6077#define EC_OC_REG_DTO_INC_LOP_INIT 0x0
6078
6079
6080#define EC_OC_REG_DTO_INC_HIP__A 0x2150015
6081#define EC_OC_REG_DTO_INC_HIP__W 8
6082#define EC_OC_REG_DTO_INC_HIP__M 0xFF
6083#define EC_OC_REG_DTO_INC_HIP_INIT 0x0
6084
6085
6086#define EC_OC_REG_SNC_ISC_LVL__A 0x2150016
6087#define EC_OC_REG_SNC_ISC_LVL__W 12
6088#define EC_OC_REG_SNC_ISC_LVL__M 0xFFF
6089#define EC_OC_REG_SNC_ISC_LVL_INIT 0x0
6090
6091#define EC_OC_REG_SNC_ISC_LVL_ISC__B 0
6092#define EC_OC_REG_SNC_ISC_LVL_ISC__W 4
6093#define EC_OC_REG_SNC_ISC_LVL_ISC__M 0xF
6094
6095#define EC_OC_REG_SNC_ISC_LVL_OSC__B 4
6096#define EC_OC_REG_SNC_ISC_LVL_OSC__W 4
6097#define EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0
6098
6099#define EC_OC_REG_SNC_ISC_LVL_NSC__B 8
6100#define EC_OC_REG_SNC_ISC_LVL_NSC__W 4
6101#define EC_OC_REG_SNC_ISC_LVL_NSC__M 0xF00
6102
6103
6104#define EC_OC_REG_SNC_NSC_LVL__A 0x2150017
6105#define EC_OC_REG_SNC_NSC_LVL__W 8
6106#define EC_OC_REG_SNC_NSC_LVL__M 0xFF
6107#define EC_OC_REG_SNC_NSC_LVL_INIT 0x0
6108
6109
6110#define EC_OC_REG_SNC_SNC_MODE__A 0x2150019
6111#define EC_OC_REG_SNC_SNC_MODE__W 2
6112#define EC_OC_REG_SNC_SNC_MODE__M 0x3
6113#define EC_OC_REG_SNC_SNC_MODE_SEARCH 0x0
6114#define EC_OC_REG_SNC_SNC_MODE_TRACK 0x1
6115#define EC_OC_REG_SNC_SNC_MODE_LOCK 0x2
6116
6117
6118#define EC_OC_REG_SNC_PCK_NMB__A 0x215001A
6119#define EC_OC_REG_SNC_PCK_NMB__W 16
6120#define EC_OC_REG_SNC_PCK_NMB__M 0xFFFF
6121
6122#define EC_OC_REG_SNC_PCK_CNT__A 0x215001B
6123#define EC_OC_REG_SNC_PCK_CNT__W 16
6124#define EC_OC_REG_SNC_PCK_CNT__M 0xFFFF
6125
6126#define EC_OC_REG_SNC_PCK_ERR__A 0x215001C
6127#define EC_OC_REG_SNC_PCK_ERR__W 16
6128#define EC_OC_REG_SNC_PCK_ERR__M 0xFFFF
6129
6130#define EC_OC_REG_TMD_TOP_MODE__A 0x215001D
6131#define EC_OC_REG_TMD_TOP_MODE__W 2
6132#define EC_OC_REG_TMD_TOP_MODE__M 0x3
6133#define EC_OC_REG_TMD_TOP_MODE_INIT 0x0
6134#define EC_OC_REG_TMD_TOP_MODE_SELECT_ACT_ACT 0x0
6135#define EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_TOP 0x1
6136#define EC_OC_REG_TMD_TOP_MODE_SELECT_BOT_BOT 0x2
6137#define EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_BOT 0x3
6138
6139
6140#define EC_OC_REG_TMD_TOP_CNT__A 0x215001E
6141#define EC_OC_REG_TMD_TOP_CNT__W 10
6142#define EC_OC_REG_TMD_TOP_CNT__M 0x3FF
6143#define EC_OC_REG_TMD_TOP_CNT_INIT 0x0
6144
6145
6146#define EC_OC_REG_TMD_HIL_MAR__A 0x215001F
6147#define EC_OC_REG_TMD_HIL_MAR__W 10
6148#define EC_OC_REG_TMD_HIL_MAR__M 0x3FF
6149#define EC_OC_REG_TMD_HIL_MAR_INIT 0x0
6150
6151
6152#define EC_OC_REG_TMD_LOL_MAR__A 0x2150020
6153#define EC_OC_REG_TMD_LOL_MAR__W 10
6154#define EC_OC_REG_TMD_LOL_MAR__M 0x3FF
6155#define EC_OC_REG_TMD_LOL_MAR_INIT 0x0
6156
6157
6158#define EC_OC_REG_TMD_CUR_CNT__A 0x2150021
6159#define EC_OC_REG_TMD_CUR_CNT__W 4
6160#define EC_OC_REG_TMD_CUR_CNT__M 0xF
6161#define EC_OC_REG_TMD_CUR_CNT_INIT 0x0
6162
6163
6164#define EC_OC_REG_TMD_IUR_CNT__A 0x2150022
6165#define EC_OC_REG_TMD_IUR_CNT__W 4
6166#define EC_OC_REG_TMD_IUR_CNT__M 0xF
6167#define EC_OC_REG_TMD_IUR_CNT_INIT 0x0
6168
6169
6170#define EC_OC_REG_AVR_ASH_CNT__A 0x2150023
6171#define EC_OC_REG_AVR_ASH_CNT__W 4
6172#define EC_OC_REG_AVR_ASH_CNT__M 0xF
6173#define EC_OC_REG_AVR_ASH_CNT_INIT 0x0
6174
6175
6176#define EC_OC_REG_AVR_BSH_CNT__A 0x2150024
6177#define EC_OC_REG_AVR_BSH_CNT__W 4
6178#define EC_OC_REG_AVR_BSH_CNT__M 0xF
6179#define EC_OC_REG_AVR_BSH_CNT_INIT 0x0
6180
6181
6182#define EC_OC_REG_AVR_AVE_LOP__A 0x2150025
6183#define EC_OC_REG_AVR_AVE_LOP__W 16
6184#define EC_OC_REG_AVR_AVE_LOP__M 0xFFFF
6185
6186#define EC_OC_REG_AVR_AVE_HIP__A 0x2150026
6187#define EC_OC_REG_AVR_AVE_HIP__W 5
6188#define EC_OC_REG_AVR_AVE_HIP__M 0x1F
6189
6190#define EC_OC_REG_RCN_MODE__A 0x2150027
6191#define EC_OC_REG_RCN_MODE__W 3
6192#define EC_OC_REG_RCN_MODE__M 0x7
6193#define EC_OC_REG_RCN_MODE_INIT 0x0
6194
6195#define EC_OC_REG_RCN_MODE_MODE_0__B 0
6196#define EC_OC_REG_RCN_MODE_MODE_0__W 1
6197#define EC_OC_REG_RCN_MODE_MODE_0__M 0x1
6198#define EC_OC_REG_RCN_MODE_MODE_0_ENABLE 0x0
6199#define EC_OC_REG_RCN_MODE_MODE_0_DISABLE 0x1
6200
6201#define EC_OC_REG_RCN_MODE_MODE_1__B 1
6202#define EC_OC_REG_RCN_MODE_MODE_1__W 1
6203#define EC_OC_REG_RCN_MODE_MODE_1__M 0x2
6204#define EC_OC_REG_RCN_MODE_MODE_1_ENABLE 0x0
6205#define EC_OC_REG_RCN_MODE_MODE_1_DISABLE 0x2
6206
6207#define EC_OC_REG_RCN_MODE_MODE_2__B 2
6208#define EC_OC_REG_RCN_MODE_MODE_2__W 1
6209#define EC_OC_REG_RCN_MODE_MODE_2__M 0x4
6210#define EC_OC_REG_RCN_MODE_MODE_2_ENABLE 0x4
6211#define EC_OC_REG_RCN_MODE_MODE_2_DISABLE 0x0
6212
6213
6214#define EC_OC_REG_RCN_CRA_LOP__A 0x2150028
6215#define EC_OC_REG_RCN_CRA_LOP__W 16
6216#define EC_OC_REG_RCN_CRA_LOP__M 0xFFFF
6217#define EC_OC_REG_RCN_CRA_LOP_INIT 0x0
6218
6219
6220#define EC_OC_REG_RCN_CRA_HIP__A 0x2150029
6221#define EC_OC_REG_RCN_CRA_HIP__W 8
6222#define EC_OC_REG_RCN_CRA_HIP__M 0xFF
6223#define EC_OC_REG_RCN_CRA_HIP_INIT 0x0
6224
6225
6226#define EC_OC_REG_RCN_CST_LOP__A 0x215002A
6227#define EC_OC_REG_RCN_CST_LOP__W 16
6228#define EC_OC_REG_RCN_CST_LOP__M 0xFFFF
6229#define EC_OC_REG_RCN_CST_LOP_INIT 0x0
6230
6231
6232#define EC_OC_REG_RCN_CST_HIP__A 0x215002B
6233#define EC_OC_REG_RCN_CST_HIP__W 8
6234#define EC_OC_REG_RCN_CST_HIP__M 0xFF
6235#define EC_OC_REG_RCN_CST_HIP_INIT 0x0
6236
6237
6238#define EC_OC_REG_RCN_SET_LVL__A 0x215002C
6239#define EC_OC_REG_RCN_SET_LVL__W 9
6240#define EC_OC_REG_RCN_SET_LVL__M 0x1FF
6241#define EC_OC_REG_RCN_SET_LVL_INIT 0x0
6242
6243
6244#define EC_OC_REG_RCN_GAI_LVL__A 0x215002D
6245#define EC_OC_REG_RCN_GAI_LVL__W 4
6246#define EC_OC_REG_RCN_GAI_LVL__M 0xF
6247#define EC_OC_REG_RCN_GAI_LVL_INIT 0x0
6248
6249
6250#define EC_OC_REG_RCN_DRA_LOP__A 0x215002E
6251#define EC_OC_REG_RCN_DRA_LOP__W 16
6252#define EC_OC_REG_RCN_DRA_LOP__M 0xFFFF
6253
6254#define EC_OC_REG_RCN_DRA_HIP__A 0x215002F
6255#define EC_OC_REG_RCN_DRA_HIP__W 8
6256#define EC_OC_REG_RCN_DRA_HIP__M 0xFF
6257
6258#define EC_OC_REG_RCN_DOF_LOP__A 0x2150030
6259#define EC_OC_REG_RCN_DOF_LOP__W 16
6260#define EC_OC_REG_RCN_DOF_LOP__M 0xFFFF
6261
6262#define EC_OC_REG_RCN_DOF_HIP__A 0x2150031
6263#define EC_OC_REG_RCN_DOF_HIP__W 8
6264#define EC_OC_REG_RCN_DOF_HIP__M 0xFF
6265
6266#define EC_OC_REG_RCN_CLP_LOP__A 0x2150032
6267#define EC_OC_REG_RCN_CLP_LOP__W 16
6268#define EC_OC_REG_RCN_CLP_LOP__M 0xFFFF
6269#define EC_OC_REG_RCN_CLP_LOP_INIT 0xFFFF
6270
6271
6272#define EC_OC_REG_RCN_CLP_HIP__A 0x2150033
6273#define EC_OC_REG_RCN_CLP_HIP__W 8
6274#define EC_OC_REG_RCN_CLP_HIP__M 0xFF
6275#define EC_OC_REG_RCN_CLP_HIP_INIT 0xFF
6276
6277
6278#define EC_OC_REG_RCN_MAP_LOP__A 0x2150034
6279#define EC_OC_REG_RCN_MAP_LOP__W 16
6280#define EC_OC_REG_RCN_MAP_LOP__M 0xFFFF
6281
6282#define EC_OC_REG_RCN_MAP_HIP__A 0x2150035
6283#define EC_OC_REG_RCN_MAP_HIP__W 8
6284#define EC_OC_REG_RCN_MAP_HIP__M 0xFF
6285
6286#define EC_OC_REG_OCR_MPG_UOS__A 0x2150036
6287#define EC_OC_REG_OCR_MPG_UOS__W 12
6288#define EC_OC_REG_OCR_MPG_UOS__M 0xFFF
6289#define EC_OC_REG_OCR_MPG_UOS_INIT 0x0
6290
6291#define EC_OC_REG_OCR_MPG_UOS_DAT_0__B 0
6292#define EC_OC_REG_OCR_MPG_UOS_DAT_0__W 1
6293#define EC_OC_REG_OCR_MPG_UOS_DAT_0__M 0x1
6294#define EC_OC_REG_OCR_MPG_UOS_DAT_0_DISABLE 0x0
6295#define EC_OC_REG_OCR_MPG_UOS_DAT_0_ENABLE 0x1
6296
6297#define EC_OC_REG_OCR_MPG_UOS_DAT_1__B 1
6298#define EC_OC_REG_OCR_MPG_UOS_DAT_1__W 1
6299#define EC_OC_REG_OCR_MPG_UOS_DAT_1__M 0x2
6300#define EC_OC_REG_OCR_MPG_UOS_DAT_1_DISABLE 0x0
6301#define EC_OC_REG_OCR_MPG_UOS_DAT_1_ENABLE 0x2
6302
6303#define EC_OC_REG_OCR_MPG_UOS_DAT_2__B 2
6304#define EC_OC_REG_OCR_MPG_UOS_DAT_2__W 1
6305#define EC_OC_REG_OCR_MPG_UOS_DAT_2__M 0x4
6306#define EC_OC_REG_OCR_MPG_UOS_DAT_2_DISABLE 0x0
6307#define EC_OC_REG_OCR_MPG_UOS_DAT_2_ENABLE 0x4
6308
6309#define EC_OC_REG_OCR_MPG_UOS_DAT_3__B 3
6310#define EC_OC_REG_OCR_MPG_UOS_DAT_3__W 1
6311#define EC_OC_REG_OCR_MPG_UOS_DAT_3__M 0x8
6312#define EC_OC_REG_OCR_MPG_UOS_DAT_3_DISABLE 0x0
6313#define EC_OC_REG_OCR_MPG_UOS_DAT_3_ENABLE 0x8
6314
6315#define EC_OC_REG_OCR_MPG_UOS_DAT_4__B 4
6316#define EC_OC_REG_OCR_MPG_UOS_DAT_4__W 1
6317#define EC_OC_REG_OCR_MPG_UOS_DAT_4__M 0x10
6318#define EC_OC_REG_OCR_MPG_UOS_DAT_4_DISABLE 0x0
6319#define EC_OC_REG_OCR_MPG_UOS_DAT_4_ENABLE 0x10
6320
6321#define EC_OC_REG_OCR_MPG_UOS_DAT_5__B 5
6322#define EC_OC_REG_OCR_MPG_UOS_DAT_5__W 1
6323#define EC_OC_REG_OCR_MPG_UOS_DAT_5__M 0x20
6324#define EC_OC_REG_OCR_MPG_UOS_DAT_5_DISABLE 0x0
6325#define EC_OC_REG_OCR_MPG_UOS_DAT_5_ENABLE 0x20
6326
6327#define EC_OC_REG_OCR_MPG_UOS_DAT_6__B 6
6328#define EC_OC_REG_OCR_MPG_UOS_DAT_6__W 1
6329#define EC_OC_REG_OCR_MPG_UOS_DAT_6__M 0x40
6330#define EC_OC_REG_OCR_MPG_UOS_DAT_6_DISABLE 0x0
6331#define EC_OC_REG_OCR_MPG_UOS_DAT_6_ENABLE 0x40
6332
6333#define EC_OC_REG_OCR_MPG_UOS_DAT_7__B 7
6334#define EC_OC_REG_OCR_MPG_UOS_DAT_7__W 1
6335#define EC_OC_REG_OCR_MPG_UOS_DAT_7__M 0x80
6336#define EC_OC_REG_OCR_MPG_UOS_DAT_7_DISABLE 0x0
6337#define EC_OC_REG_OCR_MPG_UOS_DAT_7_ENABLE 0x80
6338
6339#define EC_OC_REG_OCR_MPG_UOS_ERR__B 8
6340#define EC_OC_REG_OCR_MPG_UOS_ERR__W 1
6341#define EC_OC_REG_OCR_MPG_UOS_ERR__M 0x100
6342#define EC_OC_REG_OCR_MPG_UOS_ERR_DISABLE 0x0
6343#define EC_OC_REG_OCR_MPG_UOS_ERR_ENABLE 0x100
6344
6345#define EC_OC_REG_OCR_MPG_UOS_STR__B 9
6346#define EC_OC_REG_OCR_MPG_UOS_STR__W 1
6347#define EC_OC_REG_OCR_MPG_UOS_STR__M 0x200
6348#define EC_OC_REG_OCR_MPG_UOS_STR_DISABLE 0x0
6349#define EC_OC_REG_OCR_MPG_UOS_STR_ENABLE 0x200
6350
6351#define EC_OC_REG_OCR_MPG_UOS_VAL__B 10
6352#define EC_OC_REG_OCR_MPG_UOS_VAL__W 1
6353#define EC_OC_REG_OCR_MPG_UOS_VAL__M 0x400
6354#define EC_OC_REG_OCR_MPG_UOS_VAL_DISABLE 0x0
6355#define EC_OC_REG_OCR_MPG_UOS_VAL_ENABLE 0x400
6356
6357#define EC_OC_REG_OCR_MPG_UOS_CLK__B 11
6358#define EC_OC_REG_OCR_MPG_UOS_CLK__W 1
6359#define EC_OC_REG_OCR_MPG_UOS_CLK__M 0x800
6360#define EC_OC_REG_OCR_MPG_UOS_CLK_DISABLE 0x0
6361#define EC_OC_REG_OCR_MPG_UOS_CLK_ENABLE 0x800
6362
6363
6364#define EC_OC_REG_OCR_MPG_WRI__A 0x2150037
6365#define EC_OC_REG_OCR_MPG_WRI__W 12
6366#define EC_OC_REG_OCR_MPG_WRI__M 0xFFF
6367#define EC_OC_REG_OCR_MPG_WRI_INIT 0x0
6368#define EC_OC_REG_OCR_MPG_WRI_DAT_0__B 0
6369#define EC_OC_REG_OCR_MPG_WRI_DAT_0__W 1
6370#define EC_OC_REG_OCR_MPG_WRI_DAT_0__M 0x1
6371#define EC_OC_REG_OCR_MPG_WRI_DAT_0_DISABLE 0x0
6372#define EC_OC_REG_OCR_MPG_WRI_DAT_0_ENABLE 0x1
6373#define EC_OC_REG_OCR_MPG_WRI_DAT_1__B 1
6374#define EC_OC_REG_OCR_MPG_WRI_DAT_1__W 1
6375#define EC_OC_REG_OCR_MPG_WRI_DAT_1__M 0x2
6376#define EC_OC_REG_OCR_MPG_WRI_DAT_1_DISABLE 0x0
6377#define EC_OC_REG_OCR_MPG_WRI_DAT_1_ENABLE 0x2
6378#define EC_OC_REG_OCR_MPG_WRI_DAT_2__B 2
6379#define EC_OC_REG_OCR_MPG_WRI_DAT_2__W 1
6380#define EC_OC_REG_OCR_MPG_WRI_DAT_2__M 0x4
6381#define EC_OC_REG_OCR_MPG_WRI_DAT_2_DISABLE 0x0
6382#define EC_OC_REG_OCR_MPG_WRI_DAT_2_ENABLE 0x4
6383#define EC_OC_REG_OCR_MPG_WRI_DAT_3__B 3
6384#define EC_OC_REG_OCR_MPG_WRI_DAT_3__W 1
6385#define EC_OC_REG_OCR_MPG_WRI_DAT_3__M 0x8
6386#define EC_OC_REG_OCR_MPG_WRI_DAT_3_DISABLE 0x0
6387#define EC_OC_REG_OCR_MPG_WRI_DAT_3_ENABLE 0x8
6388#define EC_OC_REG_OCR_MPG_WRI_DAT_4__B 4
6389#define EC_OC_REG_OCR_MPG_WRI_DAT_4__W 1
6390#define EC_OC_REG_OCR_MPG_WRI_DAT_4__M 0x10
6391#define EC_OC_REG_OCR_MPG_WRI_DAT_4_DISABLE 0x0
6392#define EC_OC_REG_OCR_MPG_WRI_DAT_4_ENABLE 0x10
6393#define EC_OC_REG_OCR_MPG_WRI_DAT_5__B 5
6394#define EC_OC_REG_OCR_MPG_WRI_DAT_5__W 1
6395#define EC_OC_REG_OCR_MPG_WRI_DAT_5__M 0x20
6396#define EC_OC_REG_OCR_MPG_WRI_DAT_5_DISABLE 0x0
6397#define EC_OC_REG_OCR_MPG_WRI_DAT_5_ENABLE 0x20
6398#define EC_OC_REG_OCR_MPG_WRI_DAT_6__B 6
6399#define EC_OC_REG_OCR_MPG_WRI_DAT_6__W 1
6400#define EC_OC_REG_OCR_MPG_WRI_DAT_6__M 0x40
6401#define EC_OC_REG_OCR_MPG_WRI_DAT_6_DISABLE 0x0
6402#define EC_OC_REG_OCR_MPG_WRI_DAT_6_ENABLE 0x40
6403#define EC_OC_REG_OCR_MPG_WRI_DAT_7__B 7
6404#define EC_OC_REG_OCR_MPG_WRI_DAT_7__W 1
6405#define EC_OC_REG_OCR_MPG_WRI_DAT_7__M 0x80
6406#define EC_OC_REG_OCR_MPG_WRI_DAT_7_DISABLE 0x0
6407#define EC_OC_REG_OCR_MPG_WRI_DAT_7_ENABLE 0x80
6408#define EC_OC_REG_OCR_MPG_WRI_ERR__B 8
6409#define EC_OC_REG_OCR_MPG_WRI_ERR__W 1
6410#define EC_OC_REG_OCR_MPG_WRI_ERR__M 0x100
6411#define EC_OC_REG_OCR_MPG_WRI_ERR_DISABLE 0x0
6412#define EC_OC_REG_OCR_MPG_WRI_ERR_ENABLE 0x100
6413#define EC_OC_REG_OCR_MPG_WRI_STR__B 9
6414#define EC_OC_REG_OCR_MPG_WRI_STR__W 1
6415#define EC_OC_REG_OCR_MPG_WRI_STR__M 0x200
6416#define EC_OC_REG_OCR_MPG_WRI_STR_DISABLE 0x0
6417#define EC_OC_REG_OCR_MPG_WRI_STR_ENABLE 0x200
6418#define EC_OC_REG_OCR_MPG_WRI_VAL__B 10
6419#define EC_OC_REG_OCR_MPG_WRI_VAL__W 1
6420#define EC_OC_REG_OCR_MPG_WRI_VAL__M 0x400
6421#define EC_OC_REG_OCR_MPG_WRI_VAL_DISABLE 0x0
6422#define EC_OC_REG_OCR_MPG_WRI_VAL_ENABLE 0x400
6423#define EC_OC_REG_OCR_MPG_WRI_CLK__B 11
6424#define EC_OC_REG_OCR_MPG_WRI_CLK__W 1
6425#define EC_OC_REG_OCR_MPG_WRI_CLK__M 0x800
6426#define EC_OC_REG_OCR_MPG_WRI_CLK_DISABLE 0x0
6427#define EC_OC_REG_OCR_MPG_WRI_CLK_ENABLE 0x800
6428
6429
6430#define EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038
6431#define EC_OC_REG_OCR_MPG_USR_DAT__W 12
6432#define EC_OC_REG_OCR_MPG_USR_DAT__M 0xFFF
6433
6434#define EC_OC_REG_OCR_MON_UOS__A 0x2150039
6435#define EC_OC_REG_OCR_MON_UOS__W 12
6436#define EC_OC_REG_OCR_MON_UOS__M 0xFFF
6437#define EC_OC_REG_OCR_MON_UOS_INIT 0x0
6438
6439#define EC_OC_REG_OCR_MON_UOS_DAT_0__B 0
6440#define EC_OC_REG_OCR_MON_UOS_DAT_0__W 1
6441#define EC_OC_REG_OCR_MON_UOS_DAT_0__M 0x1
6442#define EC_OC_REG_OCR_MON_UOS_DAT_0_DISABLE 0x0
6443#define EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE 0x1
6444
6445#define EC_OC_REG_OCR_MON_UOS_DAT_1__B 1
6446#define EC_OC_REG_OCR_MON_UOS_DAT_1__W 1
6447#define EC_OC_REG_OCR_MON_UOS_DAT_1__M 0x2
6448#define EC_OC_REG_OCR_MON_UOS_DAT_1_DISABLE 0x0
6449#define EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE 0x2
6450
6451#define EC_OC_REG_OCR_MON_UOS_DAT_2__B 2
6452#define EC_OC_REG_OCR_MON_UOS_DAT_2__W 1
6453#define EC_OC_REG_OCR_MON_UOS_DAT_2__M 0x4
6454#define EC_OC_REG_OCR_MON_UOS_DAT_2_DISABLE 0x0
6455#define EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE 0x4
6456
6457#define EC_OC_REG_OCR_MON_UOS_DAT_3__B 3
6458#define EC_OC_REG_OCR_MON_UOS_DAT_3__W 1
6459#define EC_OC_REG_OCR_MON_UOS_DAT_3__M 0x8
6460#define EC_OC_REG_OCR_MON_UOS_DAT_3_DISABLE 0x0
6461#define EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE 0x8
6462
6463#define EC_OC_REG_OCR_MON_UOS_DAT_4__B 4
6464#define EC_OC_REG_OCR_MON_UOS_DAT_4__W 1
6465#define EC_OC_REG_OCR_MON_UOS_DAT_4__M 0x10
6466#define EC_OC_REG_OCR_MON_UOS_DAT_4_DISABLE 0x0
6467#define EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE 0x10
6468
6469#define EC_OC_REG_OCR_MON_UOS_DAT_5__B 5
6470#define EC_OC_REG_OCR_MON_UOS_DAT_5__W 1
6471#define EC_OC_REG_OCR_MON_UOS_DAT_5__M 0x20
6472#define EC_OC_REG_OCR_MON_UOS_DAT_5_DISABLE 0x0
6473#define EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE 0x20
6474
6475#define EC_OC_REG_OCR_MON_UOS_DAT_6__B 6
6476#define EC_OC_REG_OCR_MON_UOS_DAT_6__W 1
6477#define EC_OC_REG_OCR_MON_UOS_DAT_6__M 0x40
6478#define EC_OC_REG_OCR_MON_UOS_DAT_6_DISABLE 0x0
6479#define EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE 0x40
6480
6481#define EC_OC_REG_OCR_MON_UOS_DAT_7__B 7
6482#define EC_OC_REG_OCR_MON_UOS_DAT_7__W 1
6483#define EC_OC_REG_OCR_MON_UOS_DAT_7__M 0x80
6484#define EC_OC_REG_OCR_MON_UOS_DAT_7_DISABLE 0x0
6485#define EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE 0x80
6486
6487#define EC_OC_REG_OCR_MON_UOS_DAT_8__B 8
6488#define EC_OC_REG_OCR_MON_UOS_DAT_8__W 1
6489#define EC_OC_REG_OCR_MON_UOS_DAT_8__M 0x100
6490#define EC_OC_REG_OCR_MON_UOS_DAT_8_DISABLE 0x0
6491#define EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE 0x100
6492
6493#define EC_OC_REG_OCR_MON_UOS_DAT_9__B 9
6494#define EC_OC_REG_OCR_MON_UOS_DAT_9__W 1
6495#define EC_OC_REG_OCR_MON_UOS_DAT_9__M 0x200
6496#define EC_OC_REG_OCR_MON_UOS_DAT_9_DISABLE 0x0
6497#define EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE 0x200
6498
6499#define EC_OC_REG_OCR_MON_UOS_VAL__B 10
6500#define EC_OC_REG_OCR_MON_UOS_VAL__W 1
6501#define EC_OC_REG_OCR_MON_UOS_VAL__M 0x400
6502#define EC_OC_REG_OCR_MON_UOS_VAL_DISABLE 0x0
6503#define EC_OC_REG_OCR_MON_UOS_VAL_ENABLE 0x400
6504
6505#define EC_OC_REG_OCR_MON_UOS_CLK__B 11
6506#define EC_OC_REG_OCR_MON_UOS_CLK__W 1
6507#define EC_OC_REG_OCR_MON_UOS_CLK__M 0x800
6508#define EC_OC_REG_OCR_MON_UOS_CLK_DISABLE 0x0
6509#define EC_OC_REG_OCR_MON_UOS_CLK_ENABLE 0x800
6510
6511
6512#define EC_OC_REG_OCR_MON_WRI__A 0x215003A
6513#define EC_OC_REG_OCR_MON_WRI__W 12
6514#define EC_OC_REG_OCR_MON_WRI__M 0xFFF
6515#define EC_OC_REG_OCR_MON_WRI_INIT 0x0
6516#define EC_OC_REG_OCR_MON_WRI_DAT_0__B 0
6517#define EC_OC_REG_OCR_MON_WRI_DAT_0__W 1
6518#define EC_OC_REG_OCR_MON_WRI_DAT_0__M 0x1
6519#define EC_OC_REG_OCR_MON_WRI_DAT_0_DISABLE 0x0
6520#define EC_OC_REG_OCR_MON_WRI_DAT_0_ENABLE 0x1
6521#define EC_OC_REG_OCR_MON_WRI_DAT_1__B 1
6522#define EC_OC_REG_OCR_MON_WRI_DAT_1__W 1
6523#define EC_OC_REG_OCR_MON_WRI_DAT_1__M 0x2
6524#define EC_OC_REG_OCR_MON_WRI_DAT_1_DISABLE 0x0
6525#define EC_OC_REG_OCR_MON_WRI_DAT_1_ENABLE 0x2
6526#define EC_OC_REG_OCR_MON_WRI_DAT_2__B 2
6527#define EC_OC_REG_OCR_MON_WRI_DAT_2__W 1
6528#define EC_OC_REG_OCR_MON_WRI_DAT_2__M 0x4
6529#define EC_OC_REG_OCR_MON_WRI_DAT_2_DISABLE 0x0
6530#define EC_OC_REG_OCR_MON_WRI_DAT_2_ENABLE 0x4
6531#define EC_OC_REG_OCR_MON_WRI_DAT_3__B 3
6532#define EC_OC_REG_OCR_MON_WRI_DAT_3__W 1
6533#define EC_OC_REG_OCR_MON_WRI_DAT_3__M 0x8
6534#define EC_OC_REG_OCR_MON_WRI_DAT_3_DISABLE 0x0
6535#define EC_OC_REG_OCR_MON_WRI_DAT_3_ENABLE 0x8
6536#define EC_OC_REG_OCR_MON_WRI_DAT_4__B 4
6537#define EC_OC_REG_OCR_MON_WRI_DAT_4__W 1
6538#define EC_OC_REG_OCR_MON_WRI_DAT_4__M 0x10
6539#define EC_OC_REG_OCR_MON_WRI_DAT_4_DISABLE 0x0
6540#define EC_OC_REG_OCR_MON_WRI_DAT_4_ENABLE 0x10
6541#define EC_OC_REG_OCR_MON_WRI_DAT_5__B 5
6542#define EC_OC_REG_OCR_MON_WRI_DAT_5__W 1
6543#define EC_OC_REG_OCR_MON_WRI_DAT_5__M 0x20
6544#define EC_OC_REG_OCR_MON_WRI_DAT_5_DISABLE 0x0
6545#define EC_OC_REG_OCR_MON_WRI_DAT_5_ENABLE 0x20
6546#define EC_OC_REG_OCR_MON_WRI_DAT_6__B 6
6547#define EC_OC_REG_OCR_MON_WRI_DAT_6__W 1
6548#define EC_OC_REG_OCR_MON_WRI_DAT_6__M 0x40
6549#define EC_OC_REG_OCR_MON_WRI_DAT_6_DISABLE 0x0
6550#define EC_OC_REG_OCR_MON_WRI_DAT_6_ENABLE 0x40
6551#define EC_OC_REG_OCR_MON_WRI_DAT_7__B 7
6552#define EC_OC_REG_OCR_MON_WRI_DAT_7__W 1
6553#define EC_OC_REG_OCR_MON_WRI_DAT_7__M 0x80
6554#define EC_OC_REG_OCR_MON_WRI_DAT_7_DISABLE 0x0
6555#define EC_OC_REG_OCR_MON_WRI_DAT_7_ENABLE 0x80
6556#define EC_OC_REG_OCR_MON_WRI_DAT_8__B 8
6557#define EC_OC_REG_OCR_MON_WRI_DAT_8__W 1
6558#define EC_OC_REG_OCR_MON_WRI_DAT_8__M 0x100
6559#define EC_OC_REG_OCR_MON_WRI_DAT_8_DISABLE 0x0
6560#define EC_OC_REG_OCR_MON_WRI_DAT_8_ENABLE 0x100
6561#define EC_OC_REG_OCR_MON_WRI_DAT_9__B 9
6562#define EC_OC_REG_OCR_MON_WRI_DAT_9__W 1
6563#define EC_OC_REG_OCR_MON_WRI_DAT_9__M 0x200
6564#define EC_OC_REG_OCR_MON_WRI_DAT_9_DISABLE 0x0
6565#define EC_OC_REG_OCR_MON_WRI_DAT_9_ENABLE 0x200
6566#define EC_OC_REG_OCR_MON_WRI_VAL__B 10
6567#define EC_OC_REG_OCR_MON_WRI_VAL__W 1
6568#define EC_OC_REG_OCR_MON_WRI_VAL__M 0x400
6569#define EC_OC_REG_OCR_MON_WRI_VAL_DISABLE 0x0
6570#define EC_OC_REG_OCR_MON_WRI_VAL_ENABLE 0x400
6571#define EC_OC_REG_OCR_MON_WRI_CLK__B 11
6572#define EC_OC_REG_OCR_MON_WRI_CLK__W 1
6573#define EC_OC_REG_OCR_MON_WRI_CLK__M 0x800
6574#define EC_OC_REG_OCR_MON_WRI_CLK_DISABLE 0x0
6575#define EC_OC_REG_OCR_MON_WRI_CLK_ENABLE 0x800
6576
6577
6578#define EC_OC_REG_OCR_MON_USR_DAT__A 0x215003B
6579#define EC_OC_REG_OCR_MON_USR_DAT__W 12
6580#define EC_OC_REG_OCR_MON_USR_DAT__M 0xFFF
6581
6582#define EC_OC_REG_OCR_MON_CNT__A 0x215003C
6583#define EC_OC_REG_OCR_MON_CNT__W 14
6584#define EC_OC_REG_OCR_MON_CNT__M 0x3FFF
6585#define EC_OC_REG_OCR_MON_CNT_INIT 0x0
6586
6587
6588#define EC_OC_REG_OCR_MON_RDX__A 0x215003D
6589#define EC_OC_REG_OCR_MON_RDX__W 1
6590#define EC_OC_REG_OCR_MON_RDX__M 0x1
6591#define EC_OC_REG_OCR_MON_RDX_INIT 0x0
6592
6593
6594#define EC_OC_REG_OCR_MON_RD0__A 0x215003E
6595#define EC_OC_REG_OCR_MON_RD0__W 10
6596#define EC_OC_REG_OCR_MON_RD0__M 0x3FF
6597
6598#define EC_OC_REG_OCR_MON_RD1__A 0x215003F
6599#define EC_OC_REG_OCR_MON_RD1__W 10
6600#define EC_OC_REG_OCR_MON_RD1__M 0x3FF
6601
6602#define EC_OC_REG_OCR_MON_RD2__A 0x2150040
6603#define EC_OC_REG_OCR_MON_RD2__W 10
6604#define EC_OC_REG_OCR_MON_RD2__M 0x3FF
6605
6606#define EC_OC_REG_OCR_MON_RD3__A 0x2150041
6607#define EC_OC_REG_OCR_MON_RD3__W 10
6608#define EC_OC_REG_OCR_MON_RD3__M 0x3FF
6609
6610#define EC_OC_REG_OCR_MON_RD4__A 0x2150042
6611#define EC_OC_REG_OCR_MON_RD4__W 10
6612#define EC_OC_REG_OCR_MON_RD4__M 0x3FF
6613
6614#define EC_OC_REG_OCR_MON_RD5__A 0x2150043
6615#define EC_OC_REG_OCR_MON_RD5__W 10
6616#define EC_OC_REG_OCR_MON_RD5__M 0x3FF
6617
6618#define EC_OC_REG_OCR_INV_MON__A 0x2150044
6619#define EC_OC_REG_OCR_INV_MON__W 12
6620#define EC_OC_REG_OCR_INV_MON__M 0xFFF
6621#define EC_OC_REG_OCR_INV_MON_INIT 0x0
6622
6623
6624#define EC_OC_REG_IPR_INV_MPG__A 0x2150045
6625#define EC_OC_REG_IPR_INV_MPG__W 12
6626#define EC_OC_REG_IPR_INV_MPG__M 0xFFF
6627#define EC_OC_REG_IPR_INV_MPG_INIT 0x0
6628
6629
6630#define EC_OC_REG_IPR_MSR_SNC__A 0x2150046
6631#define EC_OC_REG_IPR_MSR_SNC__W 6
6632#define EC_OC_REG_IPR_MSR_SNC__M 0x3F
6633#define EC_OC_REG_IPR_MSR_SNC_INIT 0x0
6634
6635
6636
6637#define EC_OC_RAM__A 0x2160000
6638
6639
6640
6641
6642
6643#define CC_SID 0x1B
6644
6645
6646
6647
6648
6649#define CC_COMM_EXEC__A 0x2400000
6650#define CC_COMM_EXEC__W 3
6651#define CC_COMM_EXEC__M 0x7
6652#define CC_COMM_EXEC_CTL__B 0
6653#define CC_COMM_EXEC_CTL__W 3
6654#define CC_COMM_EXEC_CTL__M 0x7
6655#define CC_COMM_EXEC_CTL_STOP 0x0
6656#define CC_COMM_EXEC_CTL_ACTIVE 0x1
6657#define CC_COMM_EXEC_CTL_HOLD 0x2
6658#define CC_COMM_EXEC_CTL_STEP 0x3
6659#define CC_COMM_EXEC_CTL_BYPASS_STOP 0x4
6660#define CC_COMM_EXEC_CTL_BYPASS_HOLD 0x6
6661
6662#define CC_COMM_STATE__A 0x2400001
6663#define CC_COMM_STATE__W 16
6664#define CC_COMM_STATE__M 0xFFFF
6665#define CC_COMM_MB__A 0x2400002
6666#define CC_COMM_MB__W 16
6667#define CC_COMM_MB__M 0xFFFF
6668#define CC_COMM_SERVICE0__A 0x2400003
6669#define CC_COMM_SERVICE0__W 16
6670#define CC_COMM_SERVICE0__M 0xFFFF
6671#define CC_COMM_SERVICE1__A 0x2400004
6672#define CC_COMM_SERVICE1__W 16
6673#define CC_COMM_SERVICE1__M 0xFFFF
6674#define CC_COMM_INT_STA__A 0x2400007
6675#define CC_COMM_INT_STA__W 16
6676#define CC_COMM_INT_STA__M 0xFFFF
6677#define CC_COMM_INT_MSK__A 0x2400008
6678#define CC_COMM_INT_MSK__W 16
6679#define CC_COMM_INT_MSK__M 0xFFFF
6680
6681
6682
6683
6684
6685
6686
6687#define CC_REG_COMM_EXEC__A 0x2410000
6688#define CC_REG_COMM_EXEC__W 3
6689#define CC_REG_COMM_EXEC__M 0x7
6690#define CC_REG_COMM_EXEC_CTL__B 0
6691#define CC_REG_COMM_EXEC_CTL__W 3
6692#define CC_REG_COMM_EXEC_CTL__M 0x7
6693#define CC_REG_COMM_EXEC_CTL_STOP 0x0
6694#define CC_REG_COMM_EXEC_CTL_ACTIVE 0x1
6695#define CC_REG_COMM_EXEC_CTL_HOLD 0x2
6696#define CC_REG_COMM_EXEC_CTL_STEP 0x3
6697#define CC_REG_COMM_EXEC_CTL_BYPASS_STOP 0x4
6698#define CC_REG_COMM_EXEC_CTL_BYPASS_HOLD 0x6
6699
6700#define CC_REG_COMM_STATE__A 0x2410001
6701#define CC_REG_COMM_STATE__W 16
6702#define CC_REG_COMM_STATE__M 0xFFFF
6703#define CC_REG_COMM_MB__A 0x2410002
6704#define CC_REG_COMM_MB__W 16
6705#define CC_REG_COMM_MB__M 0xFFFF
6706#define CC_REG_COMM_SERVICE0__A 0x2410003
6707#define CC_REG_COMM_SERVICE0__W 16
6708#define CC_REG_COMM_SERVICE0__M 0xFFFF
6709#define CC_REG_COMM_SERVICE1__A 0x2410004
6710#define CC_REG_COMM_SERVICE1__W 16
6711#define CC_REG_COMM_SERVICE1__M 0xFFFF
6712#define CC_REG_COMM_INT_STA__A 0x2410007
6713#define CC_REG_COMM_INT_STA__W 16
6714#define CC_REG_COMM_INT_STA__M 0xFFFF
6715#define CC_REG_COMM_INT_MSK__A 0x2410008
6716#define CC_REG_COMM_INT_MSK__W 16
6717#define CC_REG_COMM_INT_MSK__M 0xFFFF
6718
6719#define CC_REG_OSC_MODE__A 0x2410010
6720#define CC_REG_OSC_MODE__W 2
6721#define CC_REG_OSC_MODE__M 0x3
6722#define CC_REG_OSC_MODE_OHW 0x0
6723#define CC_REG_OSC_MODE_M20 0x1
6724#define CC_REG_OSC_MODE_M48 0x2
6725
6726
6727#define CC_REG_PLL_MODE__A 0x2410011
6728#define CC_REG_PLL_MODE__W 6
6729#define CC_REG_PLL_MODE__M 0x3F
6730#define CC_REG_PLL_MODE_INIT 0xC
6731#define CC_REG_PLL_MODE_BYPASS__B 0
6732#define CC_REG_PLL_MODE_BYPASS__W 2
6733#define CC_REG_PLL_MODE_BYPASS__M 0x3
6734#define CC_REG_PLL_MODE_BYPASS_OHW 0x0
6735#define CC_REG_PLL_MODE_BYPASS_PLL 0x1
6736#define CC_REG_PLL_MODE_BYPASS_BYPASS 0x2
6737#define CC_REG_PLL_MODE_PUMP__B 2
6738#define CC_REG_PLL_MODE_PUMP__W 3
6739#define CC_REG_PLL_MODE_PUMP__M 0x1C
6740#define CC_REG_PLL_MODE_PUMP_OFF 0x0
6741#define CC_REG_PLL_MODE_PUMP_CUR_08 0x4
6742#define CC_REG_PLL_MODE_PUMP_CUR_09 0x8
6743#define CC_REG_PLL_MODE_PUMP_CUR_10 0xC
6744#define CC_REG_PLL_MODE_PUMP_CUR_11 0x10
6745#define CC_REG_PLL_MODE_PUMP_CUR_12 0x14
6746#define CC_REG_PLL_MODE_OUT_EN__B 5
6747#define CC_REG_PLL_MODE_OUT_EN__W 1
6748#define CC_REG_PLL_MODE_OUT_EN__M 0x20
6749#define CC_REG_PLL_MODE_OUT_EN_OFF 0x0
6750#define CC_REG_PLL_MODE_OUT_EN_ON 0x20
6751
6752
6753#define CC_REG_REF_DIVIDE__A 0x2410012
6754#define CC_REG_REF_DIVIDE__W 4
6755#define CC_REG_REF_DIVIDE__M 0xF
6756#define CC_REG_REF_DIVIDE_INIT 0xA
6757#define CC_REG_REF_DIVIDE_OHW 0x0
6758#define CC_REG_REF_DIVIDE_D01 0x1
6759#define CC_REG_REF_DIVIDE_D02 0x2
6760#define CC_REG_REF_DIVIDE_D03 0x3
6761#define CC_REG_REF_DIVIDE_D04 0x4
6762#define CC_REG_REF_DIVIDE_D05 0x5
6763#define CC_REG_REF_DIVIDE_D06 0x6
6764#define CC_REG_REF_DIVIDE_D07 0x7
6765#define CC_REG_REF_DIVIDE_D08 0x8
6766#define CC_REG_REF_DIVIDE_D09 0x9
6767#define CC_REG_REF_DIVIDE_D10 0xA
6768
6769
6770#define CC_REG_REF_DELAY__A 0x2410013
6771#define CC_REG_REF_DELAY__W 3
6772#define CC_REG_REF_DELAY__M 0x7
6773#define CC_REG_REF_DELAY_EDGE__B 0
6774#define CC_REG_REF_DELAY_EDGE__W 1
6775#define CC_REG_REF_DELAY_EDGE__M 0x1
6776#define CC_REG_REF_DELAY_EDGE_POS 0x0
6777#define CC_REG_REF_DELAY_EDGE_NEG 0x1
6778#define CC_REG_REF_DELAY_DELAY__B 1
6779#define CC_REG_REF_DELAY_DELAY__W 2
6780#define CC_REG_REF_DELAY_DELAY__M 0x6
6781#define CC_REG_REF_DELAY_DELAY_DEL_0 0x0
6782#define CC_REG_REF_DELAY_DELAY_DEL_3 0x2
6783#define CC_REG_REF_DELAY_DELAY_DEL_6 0x4
6784#define CC_REG_REF_DELAY_DELAY_DEL_9 0x6
6785
6786
6787#define CC_REG_CLK_DELAY__A 0x2410014
6788#define CC_REG_CLK_DELAY__W 4
6789#define CC_REG_CLK_DELAY__M 0xF
6790#define CC_REG_CLK_DELAY_OFF 0x0
6791
6792
6793#define CC_REG_PWD_MODE__A 0x2410015
6794#define CC_REG_PWD_MODE__W 2
6795#define CC_REG_PWD_MODE__M 0x3
6796#define CC_REG_PWD_MODE_UP 0x0
6797#define CC_REG_PWD_MODE_DOWN_CLK 0x1
6798#define CC_REG_PWD_MODE_DOWN_PLL 0x2
6799#define CC_REG_PWD_MODE_DOWN_OSC 0x3
6800
6801
6802#define CC_REG_SOFT_RST__A 0x2410016
6803#define CC_REG_SOFT_RST__W 2
6804#define CC_REG_SOFT_RST__M 0x3
6805#define CC_REG_SOFT_RST_SYS__B 0
6806#define CC_REG_SOFT_RST_SYS__W 1
6807#define CC_REG_SOFT_RST_SYS__M 0x1
6808#define CC_REG_SOFT_RST_OSC__B 1
6809#define CC_REG_SOFT_RST_OSC__W 1
6810#define CC_REG_SOFT_RST_OSC__M 0x2
6811
6812
6813#define CC_REG_UPDATE__A 0x2410017
6814#define CC_REG_UPDATE__W 16
6815#define CC_REG_UPDATE__M 0xFFFF
6816#define CC_REG_UPDATE_KEY 0x3973
6817
6818
6819#define CC_REG_PLL_LOCK__A 0x2410018
6820#define CC_REG_PLL_LOCK__W 1
6821#define CC_REG_PLL_LOCK__M 0x1
6822#define CC_REG_PLL_LOCK_LOCK 0x1
6823
6824
6825#define CC_REG_JTAGID_L__A 0x2410019
6826#define CC_REG_JTAGID_L__W 16
6827#define CC_REG_JTAGID_L__M 0xFFFF
6828#define CC_REG_JTAGID_L_INIT 0x0
6829
6830
6831#define CC_REG_JTAGID_H__A 0x241001A
6832#define CC_REG_JTAGID_H__W 16
6833#define CC_REG_JTAGID_H__M 0xFFFF
6834#define CC_REG_JTAGID_H_INIT 0x0
6835
6836
6837
6838
6839
6840#define LC_SID 0x1C
6841
6842
6843
6844
6845
6846#define LC_COMM_EXEC__A 0x2800000
6847#define LC_COMM_EXEC__W 3
6848#define LC_COMM_EXEC__M 0x7
6849#define LC_COMM_EXEC_CTL__B 0
6850#define LC_COMM_EXEC_CTL__W 3
6851#define LC_COMM_EXEC_CTL__M 0x7
6852#define LC_COMM_EXEC_CTL_STOP 0x0
6853#define LC_COMM_EXEC_CTL_ACTIVE 0x1
6854#define LC_COMM_EXEC_CTL_HOLD 0x2
6855#define LC_COMM_EXEC_CTL_STEP 0x3
6856#define LC_COMM_EXEC_CTL_BYPASS_STOP 0x4
6857#define LC_COMM_EXEC_CTL_BYPASS_HOLD 0x6
6858
6859#define LC_COMM_STATE__A 0x2800001
6860#define LC_COMM_STATE__W 16
6861#define LC_COMM_STATE__M 0xFFFF
6862#define LC_COMM_MB__A 0x2800002
6863#define LC_COMM_MB__W 16
6864#define LC_COMM_MB__M 0xFFFF
6865#define LC_COMM_SERVICE0__A 0x2800003
6866#define LC_COMM_SERVICE0__W 16
6867#define LC_COMM_SERVICE0__M 0xFFFF
6868#define LC_COMM_SERVICE1__A 0x2800004
6869#define LC_COMM_SERVICE1__W 16
6870#define LC_COMM_SERVICE1__M 0xFFFF
6871#define LC_COMM_INT_STA__A 0x2800007
6872#define LC_COMM_INT_STA__W 16
6873#define LC_COMM_INT_STA__M 0xFFFF
6874#define LC_COMM_INT_MSK__A 0x2800008
6875#define LC_COMM_INT_MSK__W 16
6876#define LC_COMM_INT_MSK__M 0xFFFF
6877
6878
6879
6880
6881
6882
6883#define LC_CT_REG_COMM_EXEC__A 0x2810000
6884#define LC_CT_REG_COMM_EXEC__W 3
6885#define LC_CT_REG_COMM_EXEC__M 0x7
6886#define LC_CT_REG_COMM_EXEC_CTL__B 0
6887#define LC_CT_REG_COMM_EXEC_CTL__W 3
6888#define LC_CT_REG_COMM_EXEC_CTL__M 0x7
6889#define LC_CT_REG_COMM_EXEC_CTL_STOP 0x0
6890#define LC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1
6891#define LC_CT_REG_COMM_EXEC_CTL_HOLD 0x2
6892#define LC_CT_REG_COMM_EXEC_CTL_STEP 0x3
6893
6894
6895#define LC_CT_REG_COMM_STATE__A 0x2810001
6896#define LC_CT_REG_COMM_STATE__W 10
6897#define LC_CT_REG_COMM_STATE__M 0x3FF
6898#define LC_CT_REG_COMM_SERVICE0__A 0x2810003
6899#define LC_CT_REG_COMM_SERVICE0__W 16
6900#define LC_CT_REG_COMM_SERVICE0__M 0xFFFF
6901#define LC_CT_REG_COMM_SERVICE1__A 0x2810004
6902#define LC_CT_REG_COMM_SERVICE1__W 16
6903#define LC_CT_REG_COMM_SERVICE1__M 0xFFFF
6904#define LC_CT_REG_COMM_SERVICE1_LC__B 12
6905#define LC_CT_REG_COMM_SERVICE1_LC__W 1
6906#define LC_CT_REG_COMM_SERVICE1_LC__M 0x1000
6907
6908
6909#define LC_CT_REG_COMM_INT_STA__A 0x2810007
6910#define LC_CT_REG_COMM_INT_STA__W 1
6911#define LC_CT_REG_COMM_INT_STA__M 0x1
6912#define LC_CT_REG_COMM_INT_STA_REQUEST__B 0
6913#define LC_CT_REG_COMM_INT_STA_REQUEST__W 1
6914#define LC_CT_REG_COMM_INT_STA_REQUEST__M 0x1
6915
6916
6917#define LC_CT_REG_COMM_INT_MSK__A 0x2810008
6918#define LC_CT_REG_COMM_INT_MSK__W 1
6919#define LC_CT_REG_COMM_INT_MSK__M 0x1
6920#define LC_CT_REG_COMM_INT_MSK_REQUEST__B 0
6921#define LC_CT_REG_COMM_INT_MSK_REQUEST__W 1
6922#define LC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1
6923
6924
6925
6926
6927#define LC_CT_REG_CTL_STK__AX 0x2810010
6928#define LC_CT_REG_CTL_STK__XSZ 4
6929#define LC_CT_REG_CTL_STK__W 10
6930#define LC_CT_REG_CTL_STK__M 0x3FF
6931
6932#define LC_CT_REG_CTL_BPT_IDX__A 0x281001F
6933#define LC_CT_REG_CTL_BPT_IDX__W 1
6934#define LC_CT_REG_CTL_BPT_IDX__M 0x1
6935
6936#define LC_CT_REG_CTL_BPT__A 0x2810020
6937#define LC_CT_REG_CTL_BPT__W 10
6938#define LC_CT_REG_CTL_BPT__M 0x3FF
6939
6940
6941
6942
6943
6944#define LC_RA_RAM_PROC_DELAY_IF__A 0x2820006
6945#define LC_RA_RAM_PROC_DELAY_IF__W 16
6946#define LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF
6947#define LC_RA_RAM_PROC_DELAY_IF__PRE 0xFFE6
6948#define LC_RA_RAM_PROC_DELAY_FS__A 0x2820007
6949#define LC_RA_RAM_PROC_DELAY_FS__W 16
6950#define LC_RA_RAM_PROC_DELAY_FS__M 0xFFFF
6951#define LC_RA_RAM_PROC_DELAY_FS__PRE 0xFFE3
6952#define LC_RA_RAM_LOCK_TH_CRMM__A 0x2820008
6953#define LC_RA_RAM_LOCK_TH_CRMM__W 16
6954#define LC_RA_RAM_LOCK_TH_CRMM__M 0xFFFF
6955#define LC_RA_RAM_LOCK_TH_CRMM__PRE 0xC8
6956#define LC_RA_RAM_LOCK_TH_SRMM__A 0x2820009
6957#define LC_RA_RAM_LOCK_TH_SRMM__W 16
6958#define LC_RA_RAM_LOCK_TH_SRMM__M 0xFFFF
6959#define LC_RA_RAM_LOCK_TH_SRMM__PRE 0x46
6960#define LC_RA_RAM_LOCK_COUNT__A 0x282000A
6961#define LC_RA_RAM_LOCK_COUNT__W 16
6962#define LC_RA_RAM_LOCK_COUNT__M 0xFFFF
6963#define LC_RA_RAM_CPRTOFS_NOM__A 0x282000B
6964#define LC_RA_RAM_CPRTOFS_NOM__W 16
6965#define LC_RA_RAM_CPRTOFS_NOM__M 0xFFFF
6966#define LC_RA_RAM_IFINCR_NOM_L__A 0x282000C
6967#define LC_RA_RAM_IFINCR_NOM_L__W 16
6968#define LC_RA_RAM_IFINCR_NOM_L__M 0xFFFF
6969#define LC_RA_RAM_IFINCR_NOM_H__A 0x282000D
6970#define LC_RA_RAM_IFINCR_NOM_H__W 16
6971#define LC_RA_RAM_IFINCR_NOM_H__M 0xFFFF
6972#define LC_RA_RAM_FSINCR_NOM_L__A 0x282000E
6973#define LC_RA_RAM_FSINCR_NOM_L__W 16
6974#define LC_RA_RAM_FSINCR_NOM_L__M 0xFFFF
6975#define LC_RA_RAM_FSINCR_NOM_H__A 0x282000F
6976#define LC_RA_RAM_FSINCR_NOM_H__W 16
6977#define LC_RA_RAM_FSINCR_NOM_H__M 0xFFFF
6978#define LC_RA_RAM_MODE_2K__A 0x2820010
6979#define LC_RA_RAM_MODE_2K__W 16
6980#define LC_RA_RAM_MODE_2K__M 0xFFFF
6981#define LC_RA_RAM_MODE_GUARD__A 0x2820011
6982#define LC_RA_RAM_MODE_GUARD__W 16
6983#define LC_RA_RAM_MODE_GUARD__M 0xFFFF
6984#define LC_RA_RAM_MODE_GUARD_32 0x0
6985#define LC_RA_RAM_MODE_GUARD_16 0x1
6986#define LC_RA_RAM_MODE_GUARD_8 0x2
6987#define LC_RA_RAM_MODE_GUARD_4 0x3
6988
6989#define LC_RA_RAM_MODE_ADJUST__A 0x2820012
6990#define LC_RA_RAM_MODE_ADJUST__W 16
6991#define LC_RA_RAM_MODE_ADJUST__M 0xFFFF
6992#define LC_RA_RAM_MODE_ADJUST_CP_CRMM__B 0
6993#define LC_RA_RAM_MODE_ADJUST_CP_CRMM__W 1
6994#define LC_RA_RAM_MODE_ADJUST_CP_CRMM__M 0x1
6995#define LC_RA_RAM_MODE_ADJUST_CE_CRMM__B 1
6996#define LC_RA_RAM_MODE_ADJUST_CE_CRMM__W 1
6997#define LC_RA_RAM_MODE_ADJUST_CE_CRMM__M 0x2
6998#define LC_RA_RAM_MODE_ADJUST_SRMM__B 2
6999#define LC_RA_RAM_MODE_ADJUST_SRMM__W 1
7000#define LC_RA_RAM_MODE_ADJUST_SRMM__M 0x4
7001#define LC_RA_RAM_MODE_ADJUST_PHASE__B 3
7002#define LC_RA_RAM_MODE_ADJUST_PHASE__W 1
7003#define LC_RA_RAM_MODE_ADJUST_PHASE__M 0x8
7004#define LC_RA_RAM_MODE_ADJUST_DELAY__B 4
7005#define LC_RA_RAM_MODE_ADJUST_DELAY__W 1
7006#define LC_RA_RAM_MODE_ADJUST_DELAY__M 0x10
7007#define LC_RA_RAM_MODE_ADJUST_OPENLOOP__B 5
7008#define LC_RA_RAM_MODE_ADJUST_OPENLOOP__W 1
7009#define LC_RA_RAM_MODE_ADJUST_OPENLOOP__M 0x20
7010#define LC_RA_RAM_MODE_ADJUST_NO_CP__B 6
7011#define LC_RA_RAM_MODE_ADJUST_NO_CP__W 1
7012#define LC_RA_RAM_MODE_ADJUST_NO_CP__M 0x40
7013#define LC_RA_RAM_MODE_ADJUST_NO_FS__B 7
7014#define LC_RA_RAM_MODE_ADJUST_NO_FS__W 1
7015#define LC_RA_RAM_MODE_ADJUST_NO_FS__M 0x80
7016#define LC_RA_RAM_MODE_ADJUST_NO_IF__B 8
7017#define LC_RA_RAM_MODE_ADJUST_NO_IF__W 1
7018#define LC_RA_RAM_MODE_ADJUST_NO_IF__M 0x100
7019#define LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__B 9
7020#define LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__W 1
7021#define LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__M 0x200
7022
7023#define LC_RA_RAM_FILTER_SYM_SET__A 0x282001A
7024#define LC_RA_RAM_FILTER_SYM_SET__W 16
7025#define LC_RA_RAM_FILTER_SYM_SET__M 0xFFFF
7026#define LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8
7027#define LC_RA_RAM_FILTER_SYM_CUR__A 0x282001B
7028#define LC_RA_RAM_FILTER_SYM_CUR__W 16
7029#define LC_RA_RAM_FILTER_SYM_CUR__M 0xFFFF
7030#define LC_RA_RAM_FILTER_SYM_CUR__PRE 0x0
7031#define LC_RA_RAM_MAX_ABS_EXP__A 0x282001D
7032#define LC_RA_RAM_MAX_ABS_EXP__W 16
7033#define LC_RA_RAM_MAX_ABS_EXP__M 0xFFFF
7034#define LC_RA_RAM_MAX_ABS_EXP__PRE 0x10
7035#define LC_RA_RAM_ACTUAL_CP_CRMM__A 0x282001F
7036#define LC_RA_RAM_ACTUAL_CP_CRMM__W 16
7037#define LC_RA_RAM_ACTUAL_CP_CRMM__M 0xFFFF
7038#define LC_RA_RAM_ACTUAL_CE_CRMM__A 0x2820020
7039#define LC_RA_RAM_ACTUAL_CE_CRMM__W 16
7040#define LC_RA_RAM_ACTUAL_CE_CRMM__M 0xFFFF
7041#define LC_RA_RAM_ACTUAL_CE_SRMM__A 0x2820021
7042#define LC_RA_RAM_ACTUAL_CE_SRMM__W 16
7043#define LC_RA_RAM_ACTUAL_CE_SRMM__M 0xFFFF
7044#define LC_RA_RAM_ACTUAL_PHASE__A 0x2820022
7045#define LC_RA_RAM_ACTUAL_PHASE__W 16
7046#define LC_RA_RAM_ACTUAL_PHASE__M 0xFFFF
7047#define LC_RA_RAM_ACTUAL_DELAY__A 0x2820023
7048#define LC_RA_RAM_ACTUAL_DELAY__W 16
7049#define LC_RA_RAM_ACTUAL_DELAY__M 0xFFFF
7050#define LC_RA_RAM_ADJUST_CRMM__A 0x2820024
7051#define LC_RA_RAM_ADJUST_CRMM__W 16
7052#define LC_RA_RAM_ADJUST_CRMM__M 0xFFFF
7053#define LC_RA_RAM_ADJUST_SRMM__A 0x2820025
7054#define LC_RA_RAM_ADJUST_SRMM__W 16
7055#define LC_RA_RAM_ADJUST_SRMM__M 0xFFFF
7056#define LC_RA_RAM_ADJUST_PHASE__A 0x2820026
7057#define LC_RA_RAM_ADJUST_PHASE__W 16
7058#define LC_RA_RAM_ADJUST_PHASE__M 0xFFFF
7059#define LC_RA_RAM_ADJUST_DELAY__A 0x2820027
7060#define LC_RA_RAM_ADJUST_DELAY__W 16
7061#define LC_RA_RAM_ADJUST_DELAY__M 0xFFFF
7062
7063
7064
7065
7066
7067#define LC_RA_RAM_PIPE_CP_PHASE_0__A 0x2820028
7068#define LC_RA_RAM_PIPE_CP_PHASE_0__W 16
7069#define LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF
7070#define LC_RA_RAM_PIPE_CP_PHASE_1__A 0x2820029
7071#define LC_RA_RAM_PIPE_CP_PHASE_1__W 16
7072#define LC_RA_RAM_PIPE_CP_PHASE_1__M 0xFFFF
7073#define LC_RA_RAM_PIPE_CP_PHASE_CON__A 0x282002A
7074#define LC_RA_RAM_PIPE_CP_PHASE_CON__W 16
7075#define LC_RA_RAM_PIPE_CP_PHASE_CON__M 0xFFFF
7076#define LC_RA_RAM_PIPE_CP_PHASE_DIF__A 0x282002B
7077#define LC_RA_RAM_PIPE_CP_PHASE_DIF__W 16
7078#define LC_RA_RAM_PIPE_CP_PHASE_DIF__M 0xFFFF
7079#define LC_RA_RAM_PIPE_CP_PHASE_RES__A 0x282002C
7080#define LC_RA_RAM_PIPE_CP_PHASE_RES__W 16
7081#define LC_RA_RAM_PIPE_CP_PHASE_RES__M 0xFFFF
7082#define LC_RA_RAM_PIPE_CP_PHASE_RZ__A 0x282002D
7083#define LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16
7084#define LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF
7085
7086
7087
7088#define LC_RA_RAM_PIPE_CP_CRMM_0__A 0x2820030
7089#define LC_RA_RAM_PIPE_CP_CRMM_0__W 16
7090#define LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF
7091#define LC_RA_RAM_PIPE_CP_CRMM_1__A 0x2820031
7092#define LC_RA_RAM_PIPE_CP_CRMM_1__W 16
7093#define LC_RA_RAM_PIPE_CP_CRMM_1__M 0xFFFF
7094#define LC_RA_RAM_PIPE_CP_CRMM_CON__A 0x2820032
7095#define LC_RA_RAM_PIPE_CP_CRMM_CON__W 16
7096#define LC_RA_RAM_PIPE_CP_CRMM_CON__M 0xFFFF
7097#define LC_RA_RAM_PIPE_CP_CRMM_DIF__A 0x2820033
7098#define LC_RA_RAM_PIPE_CP_CRMM_DIF__W 16
7099#define LC_RA_RAM_PIPE_CP_CRMM_DIF__M 0xFFFF
7100#define LC_RA_RAM_PIPE_CP_CRMM_RES__A 0x2820034
7101#define LC_RA_RAM_PIPE_CP_CRMM_RES__W 16
7102#define LC_RA_RAM_PIPE_CP_CRMM_RES__M 0xFFFF
7103#define LC_RA_RAM_PIPE_CP_CRMM_RZ__A 0x2820035
7104#define LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16
7105#define LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF
7106
7107
7108
7109#define LC_RA_RAM_PIPE_CP_SRMM_0__A 0x2820038
7110#define LC_RA_RAM_PIPE_CP_SRMM_0__W 16
7111#define LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF
7112#define LC_RA_RAM_PIPE_CP_SRMM_1__A 0x2820039
7113#define LC_RA_RAM_PIPE_CP_SRMM_1__W 16
7114#define LC_RA_RAM_PIPE_CP_SRMM_1__M 0xFFFF
7115#define LC_RA_RAM_PIPE_CP_SRMM_CON__A 0x282003A
7116#define LC_RA_RAM_PIPE_CP_SRMM_CON__W 16
7117#define LC_RA_RAM_PIPE_CP_SRMM_CON__M 0xFFFF
7118#define LC_RA_RAM_PIPE_CP_SRMM_DIF__A 0x282003B
7119#define LC_RA_RAM_PIPE_CP_SRMM_DIF__W 16
7120#define LC_RA_RAM_PIPE_CP_SRMM_DIF__M 0xFFFF
7121#define LC_RA_RAM_PIPE_CP_SRMM_RES__A 0x282003C
7122#define LC_RA_RAM_PIPE_CP_SRMM_RES__W 16
7123#define LC_RA_RAM_PIPE_CP_SRMM_RES__M 0xFFFF
7124#define LC_RA_RAM_PIPE_CP_SRMM_RZ__A 0x282003D
7125#define LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16
7126#define LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF
7127
7128
7129
7130
7131
7132#define LC_RA_RAM_FILTER_CRMM_A__A 0x2820060
7133#define LC_RA_RAM_FILTER_CRMM_A__W 16
7134#define LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF
7135#define LC_RA_RAM_FILTER_CRMM_A__PRE 0x4
7136#define LC_RA_RAM_FILTER_CRMM_B__A 0x2820061
7137#define LC_RA_RAM_FILTER_CRMM_B__W 16
7138#define LC_RA_RAM_FILTER_CRMM_B__M 0xFFFF
7139#define LC_RA_RAM_FILTER_CRMM_B__PRE 0x1
7140#define LC_RA_RAM_FILTER_CRMM_Z1__AX 0x2820062
7141#define LC_RA_RAM_FILTER_CRMM_Z1__XSZ 2
7142#define LC_RA_RAM_FILTER_CRMM_Z1__W 16
7143#define LC_RA_RAM_FILTER_CRMM_Z1__M 0xFFFF
7144#define LC_RA_RAM_FILTER_CRMM_Z2__AX 0x2820064
7145#define LC_RA_RAM_FILTER_CRMM_Z2__XSZ 2
7146#define LC_RA_RAM_FILTER_CRMM_Z2__W 16
7147#define LC_RA_RAM_FILTER_CRMM_Z2__M 0xFFFF
7148#define LC_RA_RAM_FILTER_CRMM_TMP__AX 0x2820066
7149#define LC_RA_RAM_FILTER_CRMM_TMP__XSZ 2
7150#define LC_RA_RAM_FILTER_CRMM_TMP__W 16
7151#define LC_RA_RAM_FILTER_CRMM_TMP__M 0xFFFF
7152
7153
7154
7155#define LC_RA_RAM_FILTER_SRMM_A__A 0x2820068
7156#define LC_RA_RAM_FILTER_SRMM_A__W 16
7157#define LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF
7158#define LC_RA_RAM_FILTER_SRMM_A__PRE 0x4
7159#define LC_RA_RAM_FILTER_SRMM_B__A 0x2820069
7160#define LC_RA_RAM_FILTER_SRMM_B__W 16
7161#define LC_RA_RAM_FILTER_SRMM_B__M 0xFFFF
7162#define LC_RA_RAM_FILTER_SRMM_B__PRE 0x1
7163#define LC_RA_RAM_FILTER_SRMM_Z1__AX 0x282006A
7164#define LC_RA_RAM_FILTER_SRMM_Z1__XSZ 2
7165#define LC_RA_RAM_FILTER_SRMM_Z1__W 16
7166#define LC_RA_RAM_FILTER_SRMM_Z1__M 0xFFFF
7167#define LC_RA_RAM_FILTER_SRMM_Z2__AX 0x282006C
7168#define LC_RA_RAM_FILTER_SRMM_Z2__XSZ 2
7169#define LC_RA_RAM_FILTER_SRMM_Z2__W 16
7170#define LC_RA_RAM_FILTER_SRMM_Z2__M 0xFFFF
7171#define LC_RA_RAM_FILTER_SRMM_TMP__AX 0x282006E
7172#define LC_RA_RAM_FILTER_SRMM_TMP__XSZ 2
7173#define LC_RA_RAM_FILTER_SRMM_TMP__W 16
7174#define LC_RA_RAM_FILTER_SRMM_TMP__M 0xFFFF
7175
7176
7177
7178#define LC_RA_RAM_FILTER_PHASE_A__A 0x2820070
7179#define LC_RA_RAM_FILTER_PHASE_A__W 16
7180#define LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF
7181#define LC_RA_RAM_FILTER_PHASE_A__PRE 0x4
7182#define LC_RA_RAM_FILTER_PHASE_B__A 0x2820071
7183#define LC_RA_RAM_FILTER_PHASE_B__W 16
7184#define LC_RA_RAM_FILTER_PHASE_B__M 0xFFFF
7185#define LC_RA_RAM_FILTER_PHASE_B__PRE 0x1
7186#define LC_RA_RAM_FILTER_PHASE_Z1__AX 0x2820072
7187#define LC_RA_RAM_FILTER_PHASE_Z1__XSZ 2
7188#define LC_RA_RAM_FILTER_PHASE_Z1__W 16
7189#define LC_RA_RAM_FILTER_PHASE_Z1__M 0xFFFF
7190#define LC_RA_RAM_FILTER_PHASE_Z2__AX 0x2820074
7191#define LC_RA_RAM_FILTER_PHASE_Z2__XSZ 2
7192#define LC_RA_RAM_FILTER_PHASE_Z2__W 16
7193#define LC_RA_RAM_FILTER_PHASE_Z2__M 0xFFFF
7194#define LC_RA_RAM_FILTER_PHASE_TMP__AX 0x2820076
7195#define LC_RA_RAM_FILTER_PHASE_TMP__XSZ 2
7196#define LC_RA_RAM_FILTER_PHASE_TMP__W 16
7197#define LC_RA_RAM_FILTER_PHASE_TMP__M 0xFFFF
7198
7199
7200
7201#define LC_RA_RAM_FILTER_DELAY_A__A 0x2820078
7202#define LC_RA_RAM_FILTER_DELAY_A__W 16
7203#define LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF
7204#define LC_RA_RAM_FILTER_DELAY_A__PRE 0x4
7205#define LC_RA_RAM_FILTER_DELAY_B__A 0x2820079
7206#define LC_RA_RAM_FILTER_DELAY_B__W 16
7207#define LC_RA_RAM_FILTER_DELAY_B__M 0xFFFF
7208#define LC_RA_RAM_FILTER_DELAY_B__PRE 0x1
7209#define LC_RA_RAM_FILTER_DELAY_Z1__AX 0x282007A
7210#define LC_RA_RAM_FILTER_DELAY_Z1__XSZ 2
7211#define LC_RA_RAM_FILTER_DELAY_Z1__W 16
7212#define LC_RA_RAM_FILTER_DELAY_Z1__M 0xFFFF
7213#define LC_RA_RAM_FILTER_DELAY_Z2__AX 0x282007C
7214#define LC_RA_RAM_FILTER_DELAY_Z2__XSZ 2
7215#define LC_RA_RAM_FILTER_DELAY_Z2__W 16
7216#define LC_RA_RAM_FILTER_DELAY_Z2__M 0xFFFF
7217#define LC_RA_RAM_FILTER_DELAY_TMP__AX 0x282007E
7218#define LC_RA_RAM_FILTER_DELAY_TMP__XSZ 2
7219#define LC_RA_RAM_FILTER_DELAY_TMP__W 16
7220#define LC_RA_RAM_FILTER_DELAY_TMP__M 0xFFFF
7221
7222
7223
7224
7225
7226
7227#define LC_IF_RAM_TRP_BPT0__AX 0x2830000
7228#define LC_IF_RAM_TRP_BPT0__XSZ 2
7229#define LC_IF_RAM_TRP_BPT0__W 12
7230#define LC_IF_RAM_TRP_BPT0__M 0xFFF
7231
7232#define LC_IF_RAM_TRP_STKU__AX 0x2830002
7233#define LC_IF_RAM_TRP_STKU__XSZ 2
7234#define LC_IF_RAM_TRP_STKU__W 12
7235#define LC_IF_RAM_TRP_STKU__M 0xFFF
7236
7237#define LC_IF_RAM_TRP_WARM__AX 0x2830006
7238#define LC_IF_RAM_TRP_WARM__XSZ 2
7239#define LC_IF_RAM_TRP_WARM__W 12
7240#define LC_IF_RAM_TRP_WARM__M 0xFFF
7241
7242
7243
7244
7245
7246
7247
7248#define B_HI_SID 0x10
7249
7250
7251
7252
7253
7254#define B_HI_COMM_EXEC__A 0x400000
7255#define B_HI_COMM_EXEC__W 3
7256#define B_HI_COMM_EXEC__M 0x7
7257#define B_HI_COMM_EXEC_CTL__B 0
7258#define B_HI_COMM_EXEC_CTL__W 3
7259#define B_HI_COMM_EXEC_CTL__M 0x7
7260#define B_HI_COMM_EXEC_CTL_STOP 0x0
7261#define B_HI_COMM_EXEC_CTL_ACTIVE 0x1
7262#define B_HI_COMM_EXEC_CTL_HOLD 0x2
7263#define B_HI_COMM_EXEC_CTL_STEP 0x3
7264#define B_HI_COMM_EXEC_CTL_BYPASS_STOP 0x4
7265#define B_HI_COMM_EXEC_CTL_BYPASS_HOLD 0x6
7266
7267#define B_HI_COMM_STATE__A 0x400001
7268#define B_HI_COMM_STATE__W 16
7269#define B_HI_COMM_STATE__M 0xFFFF
7270#define B_HI_COMM_MB__A 0x400002
7271#define B_HI_COMM_MB__W 16
7272#define B_HI_COMM_MB__M 0xFFFF
7273#define B_HI_COMM_SERVICE0__A 0x400003
7274#define B_HI_COMM_SERVICE0__W 16
7275#define B_HI_COMM_SERVICE0__M 0xFFFF
7276#define B_HI_COMM_SERVICE1__A 0x400004
7277#define B_HI_COMM_SERVICE1__W 16
7278#define B_HI_COMM_SERVICE1__M 0xFFFF
7279#define B_HI_COMM_INT_STA__A 0x400007
7280#define B_HI_COMM_INT_STA__W 16
7281#define B_HI_COMM_INT_STA__M 0xFFFF
7282#define B_HI_COMM_INT_MSK__A 0x400008
7283#define B_HI_COMM_INT_MSK__W 16
7284#define B_HI_COMM_INT_MSK__M 0xFFFF
7285
7286
7287
7288
7289
7290
7291#define B_HI_CT_REG_COMM_EXEC__A 0x410000
7292#define B_HI_CT_REG_COMM_EXEC__W 3
7293#define B_HI_CT_REG_COMM_EXEC__M 0x7
7294#define B_HI_CT_REG_COMM_EXEC_CTL__B 0
7295#define B_HI_CT_REG_COMM_EXEC_CTL__W 3
7296#define B_HI_CT_REG_COMM_EXEC_CTL__M 0x7
7297#define B_HI_CT_REG_COMM_EXEC_CTL_STOP 0x0
7298#define B_HI_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1
7299#define B_HI_CT_REG_COMM_EXEC_CTL_HOLD 0x2
7300#define B_HI_CT_REG_COMM_EXEC_CTL_STEP 0x3
7301
7302
7303#define B_HI_CT_REG_COMM_STATE__A 0x410001
7304#define B_HI_CT_REG_COMM_STATE__W 10
7305#define B_HI_CT_REG_COMM_STATE__M 0x3FF
7306#define B_HI_CT_REG_COMM_SERVICE0__A 0x410003
7307#define B_HI_CT_REG_COMM_SERVICE0__W 16
7308#define B_HI_CT_REG_COMM_SERVICE0__M 0xFFFF
7309#define B_HI_CT_REG_COMM_SERVICE1__A 0x410004
7310#define B_HI_CT_REG_COMM_SERVICE1__W 16
7311#define B_HI_CT_REG_COMM_SERVICE1__M 0xFFFF
7312#define B_HI_CT_REG_COMM_SERVICE1_HI__B 0
7313#define B_HI_CT_REG_COMM_SERVICE1_HI__W 1
7314#define B_HI_CT_REG_COMM_SERVICE1_HI__M 0x1
7315
7316
7317#define B_HI_CT_REG_COMM_INT_STA__A 0x410007
7318#define B_HI_CT_REG_COMM_INT_STA__W 1
7319#define B_HI_CT_REG_COMM_INT_STA__M 0x1
7320#define B_HI_CT_REG_COMM_INT_STA_REQUEST__B 0
7321#define B_HI_CT_REG_COMM_INT_STA_REQUEST__W 1
7322#define B_HI_CT_REG_COMM_INT_STA_REQUEST__M 0x1
7323
7324
7325#define B_HI_CT_REG_COMM_INT_MSK__A 0x410008
7326#define B_HI_CT_REG_COMM_INT_MSK__W 1
7327#define B_HI_CT_REG_COMM_INT_MSK__M 0x1
7328#define B_HI_CT_REG_COMM_INT_MSK_REQUEST__B 0
7329#define B_HI_CT_REG_COMM_INT_MSK_REQUEST__W 1
7330#define B_HI_CT_REG_COMM_INT_MSK_REQUEST__M 0x1
7331
7332
7333
7334
7335#define B_HI_CT_REG_CTL_STK__AX 0x410010
7336#define B_HI_CT_REG_CTL_STK__XSZ 4
7337#define B_HI_CT_REG_CTL_STK__W 10
7338#define B_HI_CT_REG_CTL_STK__M 0x3FF
7339
7340#define B_HI_CT_REG_CTL_BPT_IDX__A 0x41001F
7341#define B_HI_CT_REG_CTL_BPT_IDX__W 1
7342#define B_HI_CT_REG_CTL_BPT_IDX__M 0x1
7343
7344#define B_HI_CT_REG_CTL_BPT__A 0x410020
7345#define B_HI_CT_REG_CTL_BPT__W 10
7346#define B_HI_CT_REG_CTL_BPT__M 0x3FF
7347
7348
7349
7350
7351
7352
7353#define B_HI_RA_RAM_SLV0_FLG_SMM__A 0x420010
7354#define B_HI_RA_RAM_SLV0_FLG_SMM__W 1
7355#define B_HI_RA_RAM_SLV0_FLG_SMM__M 0x1
7356#define B_HI_RA_RAM_SLV0_FLG_SMM_MULTI 0x0
7357#define B_HI_RA_RAM_SLV0_FLG_SMM_SINGLE 0x1
7358
7359
7360#define B_HI_RA_RAM_SLV0_DEV_ID__A 0x420011
7361#define B_HI_RA_RAM_SLV0_DEV_ID__W 7
7362#define B_HI_RA_RAM_SLV0_DEV_ID__M 0x7F
7363
7364#define B_HI_RA_RAM_SLV0_FLG_CRC__A 0x420012
7365#define B_HI_RA_RAM_SLV0_FLG_CRC__W 1
7366#define B_HI_RA_RAM_SLV0_FLG_CRC__M 0x1
7367#define B_HI_RA_RAM_SLV0_FLG_CRC_CONTINUE 0x0
7368#define B_HI_RA_RAM_SLV0_FLG_CRC_RESTART 0x1
7369
7370
7371#define B_HI_RA_RAM_SLV0_FLG_ACC__A 0x420013
7372#define B_HI_RA_RAM_SLV0_FLG_ACC__W 3
7373#define B_HI_RA_RAM_SLV0_FLG_ACC__M 0x7
7374#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM__B 0
7375#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM__W 2
7376#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM__M 0x3
7377#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM_NORMAL 0x0
7378#define B_HI_RA_RAM_SLV0_FLG_ACC_RWM_READ_WRITE 0x3
7379#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC__B 2
7380#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC__W 1
7381#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC__M 0x4
7382#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC_NORMAL 0x0
7383#define B_HI_RA_RAM_SLV0_FLG_ACC_BRC_BROADCAST 0x4
7384
7385
7386#define B_HI_RA_RAM_SLV0_STATE__A 0x420014
7387#define B_HI_RA_RAM_SLV0_STATE__W 1
7388#define B_HI_RA_RAM_SLV0_STATE__M 0x1
7389#define B_HI_RA_RAM_SLV0_STATE_ADDRESS 0x0
7390#define B_HI_RA_RAM_SLV0_STATE_DATA 0x1
7391
7392
7393#define B_HI_RA_RAM_SLV0_BLK_BNK__A 0x420015
7394#define B_HI_RA_RAM_SLV0_BLK_BNK__W 12
7395#define B_HI_RA_RAM_SLV0_BLK_BNK__M 0xFFF
7396#define B_HI_RA_RAM_SLV0_BLK_BNK_BNK__B 0
7397#define B_HI_RA_RAM_SLV0_BLK_BNK_BNK__W 6
7398#define B_HI_RA_RAM_SLV0_BLK_BNK_BNK__M 0x3F
7399#define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__B 6
7400#define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__W 6
7401#define B_HI_RA_RAM_SLV0_BLK_BNK_BLK__M 0xFC0
7402
7403
7404#define B_HI_RA_RAM_SLV0_ADDR__A 0x420016
7405#define B_HI_RA_RAM_SLV0_ADDR__W 16
7406#define B_HI_RA_RAM_SLV0_ADDR__M 0xFFFF
7407
7408#define B_HI_RA_RAM_SLV0_CRC__A 0x420017
7409#define B_HI_RA_RAM_SLV0_CRC__W 16
7410#define B_HI_RA_RAM_SLV0_CRC__M 0xFFFF
7411
7412#define B_HI_RA_RAM_SLV0_READBACK__A 0x420018
7413#define B_HI_RA_RAM_SLV0_READBACK__W 16
7414#define B_HI_RA_RAM_SLV0_READBACK__M 0xFFFF
7415
7416
7417
7418
7419#define B_HI_RA_RAM_SLV1_FLG_SMM__A 0x420020
7420#define B_HI_RA_RAM_SLV1_FLG_SMM__W 1
7421#define B_HI_RA_RAM_SLV1_FLG_SMM__M 0x1
7422#define B_HI_RA_RAM_SLV1_FLG_SMM_MULTI 0x0
7423#define B_HI_RA_RAM_SLV1_FLG_SMM_SINGLE 0x1
7424
7425
7426#define B_HI_RA_RAM_SLV1_DEV_ID__A 0x420021
7427#define B_HI_RA_RAM_SLV1_DEV_ID__W 7
7428#define B_HI_RA_RAM_SLV1_DEV_ID__M 0x7F
7429
7430#define B_HI_RA_RAM_SLV1_FLG_CRC__A 0x420022
7431#define B_HI_RA_RAM_SLV1_FLG_CRC__W 1
7432#define B_HI_RA_RAM_SLV1_FLG_CRC__M 0x1
7433#define B_HI_RA_RAM_SLV1_FLG_CRC_CONTINUE 0x0
7434#define B_HI_RA_RAM_SLV1_FLG_CRC_RESTART 0x1
7435
7436
7437#define B_HI_RA_RAM_SLV1_FLG_ACC__A 0x420023
7438#define B_HI_RA_RAM_SLV1_FLG_ACC__W 3
7439#define B_HI_RA_RAM_SLV1_FLG_ACC__M 0x7
7440#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM__B 0
7441#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM__W 2
7442#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM__M 0x3
7443#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM_NORMAL 0x0
7444#define B_HI_RA_RAM_SLV1_FLG_ACC_RWM_READ_WRITE 0x3
7445#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC__B 2
7446#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC__W 1
7447#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC__M 0x4
7448#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC_NORMAL 0x0
7449#define B_HI_RA_RAM_SLV1_FLG_ACC_BRC_BROADCAST 0x4
7450
7451
7452#define B_HI_RA_RAM_SLV1_STATE__A 0x420024
7453#define B_HI_RA_RAM_SLV1_STATE__W 1
7454#define B_HI_RA_RAM_SLV1_STATE__M 0x1
7455#define B_HI_RA_RAM_SLV1_STATE_ADDRESS 0x0
7456#define B_HI_RA_RAM_SLV1_STATE_DATA 0x1
7457
7458
7459#define B_HI_RA_RAM_SLV1_BLK_BNK__A 0x420025
7460#define B_HI_RA_RAM_SLV1_BLK_BNK__W 12
7461#define B_HI_RA_RAM_SLV1_BLK_BNK__M 0xFFF
7462#define B_HI_RA_RAM_SLV1_BLK_BNK_BNK__B 0
7463#define B_HI_RA_RAM_SLV1_BLK_BNK_BNK__W 6
7464#define B_HI_RA_RAM_SLV1_BLK_BNK_BNK__M 0x3F
7465#define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__B 6
7466#define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__W 6
7467#define B_HI_RA_RAM_SLV1_BLK_BNK_BLK__M 0xFC0
7468
7469
7470#define B_HI_RA_RAM_SLV1_ADDR__A 0x420026
7471#define B_HI_RA_RAM_SLV1_ADDR__W 16
7472#define B_HI_RA_RAM_SLV1_ADDR__M 0xFFFF
7473
7474#define B_HI_RA_RAM_SLV1_CRC__A 0x420027
7475#define B_HI_RA_RAM_SLV1_CRC__W 16
7476#define B_HI_RA_RAM_SLV1_CRC__M 0xFFFF
7477
7478#define B_HI_RA_RAM_SLV1_READBACK__A 0x420028
7479#define B_HI_RA_RAM_SLV1_READBACK__W 16
7480#define B_HI_RA_RAM_SLV1_READBACK__M 0xFFFF
7481
7482
7483
7484
7485#define B_HI_RA_RAM_SRV_SEM__A 0x420030
7486#define B_HI_RA_RAM_SRV_SEM__W 1
7487#define B_HI_RA_RAM_SRV_SEM__M 0x1
7488#define B_HI_RA_RAM_SRV_SEM_FREE 0x0
7489#define B_HI_RA_RAM_SRV_SEM_CLAIMED 0x1
7490
7491
7492#define B_HI_RA_RAM_SRV_RES__A 0x420031
7493#define B_HI_RA_RAM_SRV_RES__W 3
7494#define B_HI_RA_RAM_SRV_RES__M 0x7
7495#define B_HI_RA_RAM_SRV_RES_OK 0x0
7496#define B_HI_RA_RAM_SRV_RES_START_FOUND_OR_ERROR 0x1
7497#define B_HI_RA_RAM_SRV_RES_STOP_FOUND 0x2
7498#define B_HI_RA_RAM_SRV_RES_ARBITRATION_FAILED 0x3
7499#define B_HI_RA_RAM_SRV_RES_INTERNAL_ERROR 0x4
7500
7501
7502#define B_HI_RA_RAM_SRV_CMD__A 0x420032
7503#define B_HI_RA_RAM_SRV_CMD__W 3
7504#define B_HI_RA_RAM_SRV_CMD__M 0x7
7505#define B_HI_RA_RAM_SRV_CMD_NULL 0x0
7506#define B_HI_RA_RAM_SRV_CMD_UIO 0x1
7507#define B_HI_RA_RAM_SRV_CMD_RESET 0x2
7508#define B_HI_RA_RAM_SRV_CMD_CONFIG 0x3
7509#define B_HI_RA_RAM_SRV_CMD_COPY 0x4
7510#define B_HI_RA_RAM_SRV_CMD_TRANSMIT 0x5
7511#define B_HI_RA_RAM_SRV_CMD_EXECUTE 0x6
7512
7513
7514#define B_HI_RA_RAM_SRV_PAR__AX 0x420033
7515#define B_HI_RA_RAM_SRV_PAR__XSZ 5
7516#define B_HI_RA_RAM_SRV_PAR__W 16
7517#define B_HI_RA_RAM_SRV_PAR__M 0xFFFF
7518
7519
7520
7521#define B_HI_RA_RAM_SRV_NOP_RES__A 0x420031
7522#define B_HI_RA_RAM_SRV_NOP_RES__W 3
7523#define B_HI_RA_RAM_SRV_NOP_RES__M 0x7
7524#define B_HI_RA_RAM_SRV_NOP_RES_OK 0x0
7525#define B_HI_RA_RAM_SRV_NOP_RES_INTERNAL_ERROR 0x4
7526
7527
7528
7529#define B_HI_RA_RAM_SRV_UIO_RES__A 0x420031
7530#define B_HI_RA_RAM_SRV_UIO_RES__W 3
7531#define B_HI_RA_RAM_SRV_UIO_RES__M 0x7
7532#define B_HI_RA_RAM_SRV_UIO_RES_LO 0x0
7533#define B_HI_RA_RAM_SRV_UIO_RES_HI 0x1
7534
7535#define B_HI_RA_RAM_SRV_UIO_KEY__A 0x420033
7536#define B_HI_RA_RAM_SRV_UIO_KEY__W 16
7537#define B_HI_RA_RAM_SRV_UIO_KEY__M 0xFFFF
7538#define B_HI_RA_RAM_SRV_UIO_KEY_ACT 0x3973
7539
7540#define B_HI_RA_RAM_SRV_UIO_SEL__A 0x420034
7541#define B_HI_RA_RAM_SRV_UIO_SEL__W 2
7542#define B_HI_RA_RAM_SRV_UIO_SEL__M 0x3
7543#define B_HI_RA_RAM_SRV_UIO_SEL_ASEL 0x0
7544#define B_HI_RA_RAM_SRV_UIO_SEL_UIO 0x1
7545
7546#define B_HI_RA_RAM_SRV_UIO_SET__A 0x420035
7547#define B_HI_RA_RAM_SRV_UIO_SET__W 2
7548#define B_HI_RA_RAM_SRV_UIO_SET__M 0x3
7549#define B_HI_RA_RAM_SRV_UIO_SET_OUT__B 0
7550#define B_HI_RA_RAM_SRV_UIO_SET_OUT__W 1
7551#define B_HI_RA_RAM_SRV_UIO_SET_OUT__M 0x1
7552#define B_HI_RA_RAM_SRV_UIO_SET_OUT_LO 0x0
7553#define B_HI_RA_RAM_SRV_UIO_SET_OUT_HI 0x1
7554#define B_HI_RA_RAM_SRV_UIO_SET_DIR__B 1
7555#define B_HI_RA_RAM_SRV_UIO_SET_DIR__W 1
7556#define B_HI_RA_RAM_SRV_UIO_SET_DIR__M 0x2
7557#define B_HI_RA_RAM_SRV_UIO_SET_DIR_OUT 0x0
7558#define B_HI_RA_RAM_SRV_UIO_SET_DIR_IN 0x2
7559
7560
7561
7562#define B_HI_RA_RAM_SRV_RST_RES__A 0x420031
7563#define B_HI_RA_RAM_SRV_RST_RES__W 1
7564#define B_HI_RA_RAM_SRV_RST_RES__M 0x1
7565#define B_HI_RA_RAM_SRV_RST_RES_OK 0x0
7566#define B_HI_RA_RAM_SRV_RST_RES_ERROR 0x1
7567
7568#define B_HI_RA_RAM_SRV_RST_KEY__A 0x420033
7569#define B_HI_RA_RAM_SRV_RST_KEY__W 16
7570#define B_HI_RA_RAM_SRV_RST_KEY__M 0xFFFF
7571#define B_HI_RA_RAM_SRV_RST_KEY_ACT 0x3973
7572
7573
7574
7575#define B_HI_RA_RAM_SRV_CFG_RES__A 0x420031
7576#define B_HI_RA_RAM_SRV_CFG_RES__W 1
7577#define B_HI_RA_RAM_SRV_CFG_RES__M 0x1
7578#define B_HI_RA_RAM_SRV_CFG_RES_OK 0x0
7579#define B_HI_RA_RAM_SRV_CFG_RES_ERROR 0x1
7580
7581#define B_HI_RA_RAM_SRV_CFG_KEY__A 0x420033
7582#define B_HI_RA_RAM_SRV_CFG_KEY__W 16
7583#define B_HI_RA_RAM_SRV_CFG_KEY__M 0xFFFF
7584#define B_HI_RA_RAM_SRV_CFG_KEY_ACT 0x3973
7585
7586
7587#define B_HI_RA_RAM_SRV_CFG_DIV__A 0x420034
7588#define B_HI_RA_RAM_SRV_CFG_DIV__W 5
7589#define B_HI_RA_RAM_SRV_CFG_DIV__M 0x1F
7590
7591#define B_HI_RA_RAM_SRV_CFG_BDL__A 0x420035
7592#define B_HI_RA_RAM_SRV_CFG_BDL__W 6
7593#define B_HI_RA_RAM_SRV_CFG_BDL__M 0x3F
7594
7595#define B_HI_RA_RAM_SRV_CFG_WUP__A 0x420036
7596#define B_HI_RA_RAM_SRV_CFG_WUP__W 8
7597#define B_HI_RA_RAM_SRV_CFG_WUP__M 0xFF
7598
7599#define B_HI_RA_RAM_SRV_CFG_ACT__A 0x420037
7600#define B_HI_RA_RAM_SRV_CFG_ACT__W 4
7601#define B_HI_RA_RAM_SRV_CFG_ACT__M 0xF
7602#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0__B 0
7603#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0__W 1
7604#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0__M 0x1
7605#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0_OFF 0x0
7606#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1
7607#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1__B 1
7608#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1__W 1
7609#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1__M 0x2
7610#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1_OFF 0x0
7611#define B_HI_RA_RAM_SRV_CFG_ACT_SLV1_ON 0x2
7612#define B_HI_RA_RAM_SRV_CFG_ACT_BRD__B 2
7613#define B_HI_RA_RAM_SRV_CFG_ACT_BRD__W 1
7614#define B_HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4
7615#define B_HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0
7616#define B_HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4
7617#define B_HI_RA_RAM_SRV_CFG_ACT_PWD__B 3
7618#define B_HI_RA_RAM_SRV_CFG_ACT_PWD__W 1
7619#define B_HI_RA_RAM_SRV_CFG_ACT_PWD__M 0x8
7620#define B_HI_RA_RAM_SRV_CFG_ACT_PWD_NOP 0x0
7621#define B_HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8
7622
7623
7624
7625#define B_HI_RA_RAM_SRV_CPY_RES__A 0x420031
7626#define B_HI_RA_RAM_SRV_CPY_RES__W 1
7627#define B_HI_RA_RAM_SRV_CPY_RES__M 0x1
7628#define B_HI_RA_RAM_SRV_CPY_RES_OK 0x0
7629#define B_HI_RA_RAM_SRV_CPY_RES_ERROR 0x1
7630
7631
7632#define B_HI_RA_RAM_SRV_CPY_SBB__A 0x420033
7633#define B_HI_RA_RAM_SRV_CPY_SBB__W 12
7634#define B_HI_RA_RAM_SRV_CPY_SBB__M 0xFFF
7635#define B_HI_RA_RAM_SRV_CPY_SBB_BNK__B 0
7636#define B_HI_RA_RAM_SRV_CPY_SBB_BNK__W 6
7637#define B_HI_RA_RAM_SRV_CPY_SBB_BNK__M 0x3F
7638#define B_HI_RA_RAM_SRV_CPY_SBB_BLK__B 6
7639#define B_HI_RA_RAM_SRV_CPY_SBB_BLK__W 6
7640#define B_HI_RA_RAM_SRV_CPY_SBB_BLK__M 0xFC0
7641
7642
7643#define B_HI_RA_RAM_SRV_CPY_SAD__A 0x420034
7644#define B_HI_RA_RAM_SRV_CPY_SAD__W 16
7645#define B_HI_RA_RAM_SRV_CPY_SAD__M 0xFFFF
7646
7647#define B_HI_RA_RAM_SRV_CPY_LEN__A 0x420035
7648#define B_HI_RA_RAM_SRV_CPY_LEN__W 16
7649#define B_HI_RA_RAM_SRV_CPY_LEN__M 0xFFFF
7650
7651#define B_HI_RA_RAM_SRV_CPY_DBB__A 0x420033
7652#define B_HI_RA_RAM_SRV_CPY_DBB__W 12
7653#define B_HI_RA_RAM_SRV_CPY_DBB__M 0xFFF
7654#define B_HI_RA_RAM_SRV_CPY_DBB_BNK__B 0
7655#define B_HI_RA_RAM_SRV_CPY_DBB_BNK__W 6
7656#define B_HI_RA_RAM_SRV_CPY_DBB_BNK__M 0x3F
7657#define B_HI_RA_RAM_SRV_CPY_DBB_BLK__B 6
7658#define B_HI_RA_RAM_SRV_CPY_DBB_BLK__W 6
7659#define B_HI_RA_RAM_SRV_CPY_DBB_BLK__M 0xFC0
7660
7661
7662#define B_HI_RA_RAM_SRV_CPY_DAD__A 0x420034
7663#define B_HI_RA_RAM_SRV_CPY_DAD__W 16
7664#define B_HI_RA_RAM_SRV_CPY_DAD__M 0xFFFF
7665
7666
7667
7668#define B_HI_RA_RAM_SRV_TRM_RES__A 0x420031
7669#define B_HI_RA_RAM_SRV_TRM_RES__W 2
7670#define B_HI_RA_RAM_SRV_TRM_RES__M 0x3
7671#define B_HI_RA_RAM_SRV_TRM_RES_OK 0x0
7672#define B_HI_RA_RAM_SRV_TRM_RES_ERROR 0x1
7673#define B_HI_RA_RAM_SRV_TRM_RES_ARBITRATION_FAILED 0x3
7674
7675
7676#define B_HI_RA_RAM_SRV_TRM_MST__A 0x420033
7677#define B_HI_RA_RAM_SRV_TRM_MST__W 12
7678#define B_HI_RA_RAM_SRV_TRM_MST__M 0xFFF
7679
7680#define B_HI_RA_RAM_SRV_TRM_SEQ__A 0x420034
7681#define B_HI_RA_RAM_SRV_TRM_SEQ__W 7
7682#define B_HI_RA_RAM_SRV_TRM_SEQ__M 0x7F
7683
7684#define B_HI_RA_RAM_SRV_TRM_TRM__A 0x420035
7685#define B_HI_RA_RAM_SRV_TRM_TRM__W 15
7686#define B_HI_RA_RAM_SRV_TRM_TRM__M 0x7FFF
7687#define B_HI_RA_RAM_SRV_TRM_TRM_DAT__B 0
7688#define B_HI_RA_RAM_SRV_TRM_TRM_DAT__W 8
7689#define B_HI_RA_RAM_SRV_TRM_TRM_DAT__M 0xFF
7690
7691
7692#define B_HI_RA_RAM_SRV_TRM_DBB__A 0x420033
7693#define B_HI_RA_RAM_SRV_TRM_DBB__W 12
7694#define B_HI_RA_RAM_SRV_TRM_DBB__M 0xFFF
7695#define B_HI_RA_RAM_SRV_TRM_DBB_BNK__B 0
7696#define B_HI_RA_RAM_SRV_TRM_DBB_BNK__W 6
7697#define B_HI_RA_RAM_SRV_TRM_DBB_BNK__M 0x3F
7698#define B_HI_RA_RAM_SRV_TRM_DBB_BLK__B 6
7699#define B_HI_RA_RAM_SRV_TRM_DBB_BLK__W 6
7700#define B_HI_RA_RAM_SRV_TRM_DBB_BLK__M 0xFC0
7701
7702
7703#define B_HI_RA_RAM_SRV_TRM_DAD__A 0x420034
7704#define B_HI_RA_RAM_SRV_TRM_DAD__W 16
7705#define B_HI_RA_RAM_SRV_TRM_DAD__M 0xFFFF
7706
7707
7708
7709
7710#define B_HI_RA_RAM_USR_BEGIN__A 0x420040
7711#define B_HI_RA_RAM_USR_BEGIN__W 16
7712#define B_HI_RA_RAM_USR_BEGIN__M 0xFFFF
7713
7714#define B_HI_RA_RAM_USR_END__A 0x42007F
7715#define B_HI_RA_RAM_USR_END__W 16
7716#define B_HI_RA_RAM_USR_END__M 0xFFFF
7717
7718
7719
7720
7721
7722
7723#define B_HI_IF_RAM_TRP_BPT0__AX 0x430000
7724#define B_HI_IF_RAM_TRP_BPT0__XSZ 2
7725#define B_HI_IF_RAM_TRP_BPT0__W 12
7726#define B_HI_IF_RAM_TRP_BPT0__M 0xFFF
7727
7728#define B_HI_IF_RAM_TRP_STKU__AX 0x430002
7729#define B_HI_IF_RAM_TRP_STKU__XSZ 2
7730#define B_HI_IF_RAM_TRP_STKU__W 12
7731#define B_HI_IF_RAM_TRP_STKU__M 0xFFF
7732
7733
7734
7735
7736#define B_HI_IF_RAM_USR_BEGIN__A 0x430200
7737#define B_HI_IF_RAM_USR_BEGIN__W 12
7738#define B_HI_IF_RAM_USR_BEGIN__M 0xFFF
7739
7740#define B_HI_IF_RAM_USR_END__A 0x4303FF
7741#define B_HI_IF_RAM_USR_END__W 12
7742#define B_HI_IF_RAM_USR_END__M 0xFFF
7743
7744
7745
7746
7747
7748#define B_SC_SID 0x11
7749
7750
7751
7752
7753
7754#define B_SC_COMM_EXEC__A 0x800000
7755#define B_SC_COMM_EXEC__W 3
7756#define B_SC_COMM_EXEC__M 0x7
7757#define B_SC_COMM_EXEC_CTL__B 0
7758#define B_SC_COMM_EXEC_CTL__W 3
7759#define B_SC_COMM_EXEC_CTL__M 0x7
7760#define B_SC_COMM_EXEC_CTL_STOP 0x0
7761#define B_SC_COMM_EXEC_CTL_ACTIVE 0x1
7762#define B_SC_COMM_EXEC_CTL_HOLD 0x2
7763#define B_SC_COMM_EXEC_CTL_STEP 0x3
7764#define B_SC_COMM_EXEC_CTL_BYPASS_STOP 0x4
7765#define B_SC_COMM_EXEC_CTL_BYPASS_HOLD 0x6
7766
7767#define B_SC_COMM_STATE__A 0x800001
7768#define B_SC_COMM_STATE__W 16
7769#define B_SC_COMM_STATE__M 0xFFFF
7770#define B_SC_COMM_MB__A 0x800002
7771#define B_SC_COMM_MB__W 16
7772#define B_SC_COMM_MB__M 0xFFFF
7773#define B_SC_COMM_SERVICE0__A 0x800003
7774#define B_SC_COMM_SERVICE0__W 16
7775#define B_SC_COMM_SERVICE0__M 0xFFFF
7776#define B_SC_COMM_SERVICE1__A 0x800004
7777#define B_SC_COMM_SERVICE1__W 16
7778#define B_SC_COMM_SERVICE1__M 0xFFFF
7779#define B_SC_COMM_INT_STA__A 0x800007
7780#define B_SC_COMM_INT_STA__W 16
7781#define B_SC_COMM_INT_STA__M 0xFFFF
7782#define B_SC_COMM_INT_MSK__A 0x800008
7783#define B_SC_COMM_INT_MSK__W 16
7784#define B_SC_COMM_INT_MSK__M 0xFFFF
7785
7786
7787
7788
7789
7790
7791#define B_SC_CT_REG_COMM_EXEC__A 0x810000
7792#define B_SC_CT_REG_COMM_EXEC__W 3
7793#define B_SC_CT_REG_COMM_EXEC__M 0x7
7794#define B_SC_CT_REG_COMM_EXEC_CTL__B 0
7795#define B_SC_CT_REG_COMM_EXEC_CTL__W 3
7796#define B_SC_CT_REG_COMM_EXEC_CTL__M 0x7
7797#define B_SC_CT_REG_COMM_EXEC_CTL_STOP 0x0
7798#define B_SC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1
7799#define B_SC_CT_REG_COMM_EXEC_CTL_HOLD 0x2
7800#define B_SC_CT_REG_COMM_EXEC_CTL_STEP 0x3
7801
7802
7803#define B_SC_CT_REG_COMM_STATE__A 0x810001
7804#define B_SC_CT_REG_COMM_STATE__W 10
7805#define B_SC_CT_REG_COMM_STATE__M 0x3FF
7806#define B_SC_CT_REG_COMM_SERVICE0__A 0x810003
7807#define B_SC_CT_REG_COMM_SERVICE0__W 16
7808#define B_SC_CT_REG_COMM_SERVICE0__M 0xFFFF
7809#define B_SC_CT_REG_COMM_SERVICE1__A 0x810004
7810#define B_SC_CT_REG_COMM_SERVICE1__W 16
7811#define B_SC_CT_REG_COMM_SERVICE1__M 0xFFFF
7812#define B_SC_CT_REG_COMM_SERVICE1_SC__B 1
7813#define B_SC_CT_REG_COMM_SERVICE1_SC__W 1
7814#define B_SC_CT_REG_COMM_SERVICE1_SC__M 0x2
7815
7816
7817#define B_SC_CT_REG_COMM_INT_STA__A 0x810007
7818#define B_SC_CT_REG_COMM_INT_STA__W 1
7819#define B_SC_CT_REG_COMM_INT_STA__M 0x1
7820#define B_SC_CT_REG_COMM_INT_STA_REQUEST__B 0
7821#define B_SC_CT_REG_COMM_INT_STA_REQUEST__W 1
7822#define B_SC_CT_REG_COMM_INT_STA_REQUEST__M 0x1
7823
7824
7825#define B_SC_CT_REG_COMM_INT_MSK__A 0x810008
7826#define B_SC_CT_REG_COMM_INT_MSK__W 1
7827#define B_SC_CT_REG_COMM_INT_MSK__M 0x1
7828#define B_SC_CT_REG_COMM_INT_MSK_REQUEST__B 0
7829#define B_SC_CT_REG_COMM_INT_MSK_REQUEST__W 1
7830#define B_SC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1
7831
7832
7833
7834
7835#define B_SC_CT_REG_CTL_STK__AX 0x810010
7836#define B_SC_CT_REG_CTL_STK__XSZ 4
7837#define B_SC_CT_REG_CTL_STK__W 10
7838#define B_SC_CT_REG_CTL_STK__M 0x3FF
7839
7840#define B_SC_CT_REG_CTL_BPT_IDX__A 0x81001F
7841#define B_SC_CT_REG_CTL_BPT_IDX__W 1
7842#define B_SC_CT_REG_CTL_BPT_IDX__M 0x1
7843
7844#define B_SC_CT_REG_CTL_BPT__A 0x810020
7845#define B_SC_CT_REG_CTL_BPT__W 10
7846#define B_SC_CT_REG_CTL_BPT__M 0x3FF
7847
7848
7849
7850
7851
7852#define B_SC_RA_RAM_PARAM0__A 0x820040
7853#define B_SC_RA_RAM_PARAM0__W 16
7854#define B_SC_RA_RAM_PARAM0__M 0xFFFF
7855#define B_SC_RA_RAM_PARAM1__A 0x820041
7856#define B_SC_RA_RAM_PARAM1__W 16
7857#define B_SC_RA_RAM_PARAM1__M 0xFFFF
7858#define B_SC_RA_RAM_CMD_ADDR__A 0x820042
7859#define B_SC_RA_RAM_CMD_ADDR__W 16
7860#define B_SC_RA_RAM_CMD_ADDR__M 0xFFFF
7861#define B_SC_RA_RAM_CMD__A 0x820043
7862#define B_SC_RA_RAM_CMD__W 16
7863#define B_SC_RA_RAM_CMD__M 0xFFFF
7864#define B_SC_RA_RAM_CMD_NULL 0x0
7865#define B_SC_RA_RAM_CMD_PROC_START 0x1
7866#define B_SC_RA_RAM_CMD_PROC_TRIGGER 0x2
7867#define B_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3
7868#define B_SC_RA_RAM_CMD_PROGRAM_PARAM 0x4
7869#define B_SC_RA_RAM_CMD_GET_OP_PARAM 0x5
7870#define B_SC_RA_RAM_CMD_USER_IO 0x6
7871#define B_SC_RA_RAM_CMD_SET_TIMER 0x7
7872#define B_SC_RA_RAM_CMD_SET_ECHO_TIMING 0x8
7873#define B_SC_RA_RAM_CMD_MAX 0x9
7874#define B_SC_RA_RAM_CMDBLOCK__C 0x4
7875
7876#define B_SC_RA_RAM_PROC_ACTIVATE__A 0x820044
7877#define B_SC_RA_RAM_PROC_ACTIVATE__W 16
7878#define B_SC_RA_RAM_PROC_ACTIVATE__M 0xFFFF
7879#define B_SC_RA_RAM_PROC_ACTIVATE__PRE 0xFFFF
7880#define B_SC_RA_RAM_PROC_TERMINATED__A 0x820045
7881#define B_SC_RA_RAM_PROC_TERMINATED__W 16
7882#define B_SC_RA_RAM_PROC_TERMINATED__M 0xFFFF
7883#define B_SC_RA_RAM_SW_EVENT__A 0x820046
7884#define B_SC_RA_RAM_SW_EVENT__W 14
7885#define B_SC_RA_RAM_SW_EVENT__M 0x3FFF
7886#define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__B 0
7887#define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__W 1
7888#define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1
7889#define B_SC_RA_RAM_SW_EVENT_RUN__B 1
7890#define B_SC_RA_RAM_SW_EVENT_RUN__W 1
7891#define B_SC_RA_RAM_SW_EVENT_RUN__M 0x2
7892#define B_SC_RA_RAM_SW_EVENT_TERMINATE__B 2
7893#define B_SC_RA_RAM_SW_EVENT_TERMINATE__W 1
7894#define B_SC_RA_RAM_SW_EVENT_TERMINATE__M 0x4
7895#define B_SC_RA_RAM_SW_EVENT_FT_START__B 3
7896#define B_SC_RA_RAM_SW_EVENT_FT_START__W 1
7897#define B_SC_RA_RAM_SW_EVENT_FT_START__M 0x8
7898#define B_SC_RA_RAM_SW_EVENT_FI_START__B 4
7899#define B_SC_RA_RAM_SW_EVENT_FI_START__W 1
7900#define B_SC_RA_RAM_SW_EVENT_FI_START__M 0x10
7901#define B_SC_RA_RAM_SW_EVENT_EQ_TPS__B 5
7902#define B_SC_RA_RAM_SW_EVENT_EQ_TPS__W 1
7903#define B_SC_RA_RAM_SW_EVENT_EQ_TPS__M 0x20
7904#define B_SC_RA_RAM_SW_EVENT_EQ_ERR__B 6
7905#define B_SC_RA_RAM_SW_EVENT_EQ_ERR__W 1
7906#define B_SC_RA_RAM_SW_EVENT_EQ_ERR__M 0x40
7907#define B_SC_RA_RAM_SW_EVENT_CE_IR__B 7
7908#define B_SC_RA_RAM_SW_EVENT_CE_IR__W 1
7909#define B_SC_RA_RAM_SW_EVENT_CE_IR__M 0x80
7910#define B_SC_RA_RAM_SW_EVENT_FE_FD__B 8
7911#define B_SC_RA_RAM_SW_EVENT_FE_FD__W 1
7912#define B_SC_RA_RAM_SW_EVENT_FE_FD__M 0x100
7913#define B_SC_RA_RAM_SW_EVENT_FE_CF__B 9
7914#define B_SC_RA_RAM_SW_EVENT_FE_CF__W 1
7915#define B_SC_RA_RAM_SW_EVENT_FE_CF__M 0x200
7916#define B_SC_RA_RAM_SW_EVENT_NF_READY__B 12
7917#define B_SC_RA_RAM_SW_EVENT_NF_READY__W 1
7918#define B_SC_RA_RAM_SW_EVENT_NF_READY__M 0x1000
7919
7920#define B_SC_RA_RAM_LOCKTRACK__A 0x820047
7921#define B_SC_RA_RAM_LOCKTRACK__W 16
7922#define B_SC_RA_RAM_LOCKTRACK__M 0xFFFF
7923#define B_SC_RA_RAM_LOCKTRACK_NULL 0x0
7924#define B_SC_RA_RAM_LOCKTRACK_MIN 0x1
7925#define B_SC_RA_RAM_LOCKTRACK_RESET 0x1
7926#define B_SC_RA_RAM_LOCKTRACK_MG_DETECT 0x2
7927#define B_SC_RA_RAM_LOCKTRACK_P_DETECT 0x3
7928#define B_SC_RA_RAM_LOCKTRACK_P_DETECT_SEARCH 0x4
7929#define B_SC_RA_RAM_LOCKTRACK_LC 0x5
7930#define B_SC_RA_RAM_LOCKTRACK_P_ECHO 0x6
7931#define B_SC_RA_RAM_LOCKTRACK_NE_INIT 0x7
7932#define B_SC_RA_RAM_LOCKTRACK_TRACK_INIT 0x8
7933#define B_SC_RA_RAM_LOCKTRACK_TRACK 0x9
7934#define B_SC_RA_RAM_LOCKTRACK_TRACK_ERROR 0xA
7935#define B_SC_RA_RAM_LOCKTRACK_MAX 0xB
7936
7937
7938
7939#define B_SC_RA_RAM_OP_PARAM__A 0x820048
7940#define B_SC_RA_RAM_OP_PARAM__W 13
7941#define B_SC_RA_RAM_OP_PARAM__M 0x1FFF
7942#define B_SC_RA_RAM_OP_PARAM_MODE__B 0
7943#define B_SC_RA_RAM_OP_PARAM_MODE__W 2
7944#define B_SC_RA_RAM_OP_PARAM_MODE__M 0x3
7945#define B_SC_RA_RAM_OP_PARAM_MODE_2K 0x0
7946#define B_SC_RA_RAM_OP_PARAM_MODE_8K 0x1
7947#define B_SC_RA_RAM_OP_PARAM_GUARD__B 2
7948#define B_SC_RA_RAM_OP_PARAM_GUARD__W 2
7949#define B_SC_RA_RAM_OP_PARAM_GUARD__M 0xC
7950#define B_SC_RA_RAM_OP_PARAM_GUARD_32 0x0
7951#define B_SC_RA_RAM_OP_PARAM_GUARD_16 0x4
7952#define B_SC_RA_RAM_OP_PARAM_GUARD_8 0x8
7953#define B_SC_RA_RAM_OP_PARAM_GUARD_4 0xC
7954#define B_SC_RA_RAM_OP_PARAM_CONST__B 4
7955#define B_SC_RA_RAM_OP_PARAM_CONST__W 2
7956#define B_SC_RA_RAM_OP_PARAM_CONST__M 0x30
7957#define B_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0
7958#define B_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10
7959#define B_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20
7960#define B_SC_RA_RAM_OP_PARAM_HIER__B 6
7961#define B_SC_RA_RAM_OP_PARAM_HIER__W 3
7962#define B_SC_RA_RAM_OP_PARAM_HIER__M 0x1C0
7963#define B_SC_RA_RAM_OP_PARAM_HIER_NO 0x0
7964#define B_SC_RA_RAM_OP_PARAM_HIER_A1 0x40
7965#define B_SC_RA_RAM_OP_PARAM_HIER_A2 0x80
7966#define B_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0
7967#define B_SC_RA_RAM_OP_PARAM_RATE__B 9
7968#define B_SC_RA_RAM_OP_PARAM_RATE__W 3
7969#define B_SC_RA_RAM_OP_PARAM_RATE__M 0xE00
7970#define B_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0
7971#define B_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200
7972#define B_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400
7973#define B_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600
7974#define B_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800
7975#define B_SC_RA_RAM_OP_PARAM_PRIO__B 12
7976#define B_SC_RA_RAM_OP_PARAM_PRIO__W 1
7977#define B_SC_RA_RAM_OP_PARAM_PRIO__M 0x1000
7978#define B_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0
7979#define B_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000
7980
7981#define B_SC_RA_RAM_OP_AUTO__A 0x820049
7982#define B_SC_RA_RAM_OP_AUTO__W 6
7983#define B_SC_RA_RAM_OP_AUTO__M 0x3F
7984#define B_SC_RA_RAM_OP_AUTO__PRE 0x1F
7985#define B_SC_RA_RAM_OP_AUTO_MODE__B 0
7986#define B_SC_RA_RAM_OP_AUTO_MODE__W 1
7987#define B_SC_RA_RAM_OP_AUTO_MODE__M 0x1
7988#define B_SC_RA_RAM_OP_AUTO_GUARD__B 1
7989#define B_SC_RA_RAM_OP_AUTO_GUARD__W 1
7990#define B_SC_RA_RAM_OP_AUTO_GUARD__M 0x2
7991#define B_SC_RA_RAM_OP_AUTO_CONST__B 2
7992#define B_SC_RA_RAM_OP_AUTO_CONST__W 1
7993#define B_SC_RA_RAM_OP_AUTO_CONST__M 0x4
7994#define B_SC_RA_RAM_OP_AUTO_HIER__B 3
7995#define B_SC_RA_RAM_OP_AUTO_HIER__W 1
7996#define B_SC_RA_RAM_OP_AUTO_HIER__M 0x8
7997#define B_SC_RA_RAM_OP_AUTO_RATE__B 4
7998#define B_SC_RA_RAM_OP_AUTO_RATE__W 1
7999#define B_SC_RA_RAM_OP_AUTO_RATE__M 0x10
8000#define B_SC_RA_RAM_OP_AUTO_PRIO__B 5
8001#define B_SC_RA_RAM_OP_AUTO_PRIO__W 1
8002#define B_SC_RA_RAM_OP_AUTO_PRIO__M 0x20
8003
8004#define B_SC_RA_RAM_PILOT_STATUS__A 0x82004A
8005#define B_SC_RA_RAM_PILOT_STATUS__W 16
8006#define B_SC_RA_RAM_PILOT_STATUS__M 0xFFFF
8007#define B_SC_RA_RAM_PILOT_STATUS_OK 0x0
8008#define B_SC_RA_RAM_PILOT_STATUS_SPD_ERROR 0x1
8009#define B_SC_RA_RAM_PILOT_STATUS_CPD_ERROR 0x2
8010#define B_SC_RA_RAM_PILOT_STATUS_SYM_ERROR 0x3
8011
8012#define B_SC_RA_RAM_LOCK__A 0x82004B
8013#define B_SC_RA_RAM_LOCK__W 4
8014#define B_SC_RA_RAM_LOCK__M 0xF
8015#define B_SC_RA_RAM_LOCK_DEMOD__B 0
8016#define B_SC_RA_RAM_LOCK_DEMOD__W 1
8017#define B_SC_RA_RAM_LOCK_DEMOD__M 0x1
8018#define B_SC_RA_RAM_LOCK_FEC__B 1
8019#define B_SC_RA_RAM_LOCK_FEC__W 1
8020#define B_SC_RA_RAM_LOCK_FEC__M 0x2
8021#define B_SC_RA_RAM_LOCK_MPEG__B 2
8022#define B_SC_RA_RAM_LOCK_MPEG__W 1
8023#define B_SC_RA_RAM_LOCK_MPEG__M 0x4
8024#define B_SC_RA_RAM_LOCK_NODVBT__B 3
8025#define B_SC_RA_RAM_LOCK_NODVBT__W 1
8026#define B_SC_RA_RAM_LOCK_NODVBT__M 0x8
8027
8028
8029
8030#define B_SC_RA_RAM_BE_OPT_ENA__A 0x82004C
8031#define B_SC_RA_RAM_BE_OPT_ENA__W 5
8032#define B_SC_RA_RAM_BE_OPT_ENA__M 0x1F
8033#define B_SC_RA_RAM_BE_OPT_ENA__PRE 0x1E
8034#define B_SC_RA_RAM_BE_OPT_ENA_MOTION 0x0
8035#define B_SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1
8036#define B_SC_RA_RAM_BE_OPT_ENA_CSI_OPT 0x2
8037#define B_SC_RA_RAM_BE_OPT_ENA_CAL_OPT 0x3
8038#define B_SC_RA_RAM_BE_OPT_ENA_FR_WATCH 0x4
8039#define B_SC_RA_RAM_BE_OPT_ENA_MAX 0x5
8040
8041#define B_SC_RA_RAM_BE_OPT_DELAY__A 0x82004D
8042#define B_SC_RA_RAM_BE_OPT_DELAY__W 16
8043#define B_SC_RA_RAM_BE_OPT_DELAY__M 0xFFFF
8044#define B_SC_RA_RAM_BE_OPT_DELAY__PRE 0x200
8045#define B_SC_RA_RAM_BE_OPT_INIT_DELAY__A 0x82004E
8046#define B_SC_RA_RAM_BE_OPT_INIT_DELAY__W 16
8047#define B_SC_RA_RAM_BE_OPT_INIT_DELAY__M 0xFFFF
8048#define B_SC_RA_RAM_BE_OPT_INIT_DELAY__PRE 0x400
8049#define B_SC_RA_RAM_ECHO_THRES__A 0x82004F
8050#define B_SC_RA_RAM_ECHO_THRES__W 16
8051#define B_SC_RA_RAM_ECHO_THRES__M 0xFFFF
8052#define B_SC_RA_RAM_ECHO_THRES__PRE 0x2A
8053#define B_SC_RA_RAM_CONFIG__A 0x820050
8054#define B_SC_RA_RAM_CONFIG__W 16
8055#define B_SC_RA_RAM_CONFIG__M 0xFFFF
8056#define B_SC_RA_RAM_CONFIG__PRE 0x14
8057#define B_SC_RA_RAM_CONFIG_ID__B 0
8058#define B_SC_RA_RAM_CONFIG_ID__W 1
8059#define B_SC_RA_RAM_CONFIG_ID__M 0x1
8060#define B_SC_RA_RAM_CONFIG_ID_PRO 0x0
8061#define B_SC_RA_RAM_CONFIG_ID_CONSUMER 0x1
8062#define B_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__B 1
8063#define B_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__W 1
8064#define B_SC_RA_RAM_CONFIG_GLITCHLESS_ENABLE__M 0x2
8065#define B_SC_RA_RAM_CONFIG_FR_ENABLE__B 2
8066#define B_SC_RA_RAM_CONFIG_FR_ENABLE__W 1
8067#define B_SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4
8068#define B_SC_RA_RAM_CONFIG_MIXMODE__B 3
8069#define B_SC_RA_RAM_CONFIG_MIXMODE__W 1
8070#define B_SC_RA_RAM_CONFIG_MIXMODE__M 0x8
8071#define B_SC_RA_RAM_CONFIG_FREQSCAN__B 4
8072#define B_SC_RA_RAM_CONFIG_FREQSCAN__W 1
8073#define B_SC_RA_RAM_CONFIG_FREQSCAN__M 0x10
8074#define B_SC_RA_RAM_CONFIG_SLAVE__B 5
8075#define B_SC_RA_RAM_CONFIG_SLAVE__W 1
8076#define B_SC_RA_RAM_CONFIG_SLAVE__M 0x20
8077#define B_SC_RA_RAM_CONFIG_FAR_OFF__B 6
8078#define B_SC_RA_RAM_CONFIG_FAR_OFF__W 1
8079#define B_SC_RA_RAM_CONFIG_FAR_OFF__M 0x40
8080#define B_SC_RA_RAM_CONFIG_FEC_CHECK_ON__B 7
8081#define B_SC_RA_RAM_CONFIG_FEC_CHECK_ON__W 1
8082#define B_SC_RA_RAM_CONFIG_FEC_CHECK_ON__M 0x80
8083#define B_SC_RA_RAM_CONFIG_ECHO_UPDATED__B 8
8084#define B_SC_RA_RAM_CONFIG_ECHO_UPDATED__W 1
8085#define B_SC_RA_RAM_CONFIG_ECHO_UPDATED__M 0x100
8086#define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__B 9
8087#define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__W 1
8088#define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M 0x200
8089#define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__B 10
8090#define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__W 1
8091#define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M 0x400
8092#define B_SC_RA_RAM_CONFIG_ADJUST_OFF__B 15
8093#define B_SC_RA_RAM_CONFIG_ADJUST_OFF__W 1
8094#define B_SC_RA_RAM_CONFIG_ADJUST_OFF__M 0x8000
8095
8096#define B_SC_RA_RAM_CE_REG_NE_FD_OFF__A 0x820054
8097#define B_SC_RA_RAM_CE_REG_NE_FD_OFF__W 16
8098#define B_SC_RA_RAM_CE_REG_NE_FD_OFF__M 0xFFFF
8099#define B_SC_RA_RAM_CE_REG_NE_FD_OFF__PRE 0xA0
8100
8101
8102
8103
8104
8105#define B_SC_RA_RAM_FR_2K_MAN_SH__A 0x820055
8106#define B_SC_RA_RAM_FR_2K_MAN_SH__W 16
8107#define B_SC_RA_RAM_FR_2K_MAN_SH__M 0xFFFF
8108#define B_SC_RA_RAM_FR_2K_MAN_SH__PRE 0x7
8109#define B_SC_RA_RAM_FR_2K_TAP_SH__A 0x820056
8110#define B_SC_RA_RAM_FR_2K_TAP_SH__W 16
8111#define B_SC_RA_RAM_FR_2K_TAP_SH__M 0xFFFF
8112#define B_SC_RA_RAM_FR_2K_TAP_SH__PRE 0x3
8113#define B_SC_RA_RAM_FR_2K_LEAK_UPD__A 0x820057
8114#define B_SC_RA_RAM_FR_2K_LEAK_UPD__W 16
8115#define B_SC_RA_RAM_FR_2K_LEAK_UPD__M 0xFFFF
8116#define B_SC_RA_RAM_FR_2K_LEAK_UPD__PRE 0x2
8117#define B_SC_RA_RAM_FR_2K_LEAK_SH__A 0x820058
8118#define B_SC_RA_RAM_FR_2K_LEAK_SH__W 16
8119#define B_SC_RA_RAM_FR_2K_LEAK_SH__M 0xFFFF
8120#define B_SC_RA_RAM_FR_2K_LEAK_SH__PRE 0x2
8121
8122
8123
8124#define B_SC_RA_RAM_FR_8K_MAN_SH__A 0x820059
8125#define B_SC_RA_RAM_FR_8K_MAN_SH__W 16
8126#define B_SC_RA_RAM_FR_8K_MAN_SH__M 0xFFFF
8127#define B_SC_RA_RAM_FR_8K_MAN_SH__PRE 0x7
8128#define B_SC_RA_RAM_FR_8K_TAP_SH__A 0x82005A
8129#define B_SC_RA_RAM_FR_8K_TAP_SH__W 16
8130#define B_SC_RA_RAM_FR_8K_TAP_SH__M 0xFFFF
8131#define B_SC_RA_RAM_FR_8K_TAP_SH__PRE 0x4
8132#define B_SC_RA_RAM_FR_8K_LEAK_UPD__A 0x82005B
8133#define B_SC_RA_RAM_FR_8K_LEAK_UPD__W 16
8134#define B_SC_RA_RAM_FR_8K_LEAK_UPD__M 0xFFFF
8135#define B_SC_RA_RAM_FR_8K_LEAK_UPD__PRE 0x2
8136#define B_SC_RA_RAM_FR_8K_LEAK_SH__A 0x82005C
8137#define B_SC_RA_RAM_FR_8K_LEAK_SH__W 16
8138#define B_SC_RA_RAM_FR_8K_LEAK_SH__M 0xFFFF
8139#define B_SC_RA_RAM_FR_8K_LEAK_SH__PRE 0x2
8140
8141
8142
8143#define B_SC_RA_RAM_CO_TD_CAL_2K__A 0x82005D
8144#define B_SC_RA_RAM_CO_TD_CAL_2K__W 16
8145#define B_SC_RA_RAM_CO_TD_CAL_2K__M 0xFFFF
8146#define B_SC_RA_RAM_CO_TD_CAL_2K__PRE 0xFFEB
8147#define B_SC_RA_RAM_CO_TD_CAL_8K__A 0x82005E
8148#define B_SC_RA_RAM_CO_TD_CAL_8K__W 16
8149#define B_SC_RA_RAM_CO_TD_CAL_8K__M 0xFFFF
8150#define B_SC_RA_RAM_CO_TD_CAL_8K__PRE 0xFFE8
8151#define B_SC_RA_RAM_MOTION_OFFSET__A 0x82005F
8152#define B_SC_RA_RAM_MOTION_OFFSET__W 16
8153#define B_SC_RA_RAM_MOTION_OFFSET__M 0xFFFF
8154#define B_SC_RA_RAM_MOTION_OFFSET__PRE 0x2
8155#define B_SC_RA_RAM_STATE_PROC_STOP__AX 0x820060
8156#define B_SC_RA_RAM_STATE_PROC_STOP__XSZ 10
8157#define B_SC_RA_RAM_STATE_PROC_STOP__W 16
8158#define B_SC_RA_RAM_STATE_PROC_STOP__M 0xFFFF
8159#define B_SC_RA_RAM_STATE_PROC_STOP_1__PRE 0xFFFE
8160#define B_SC_RA_RAM_STATE_PROC_STOP_2__PRE 0x0
8161#define B_SC_RA_RAM_STATE_PROC_STOP_3__PRE 0x4
8162#define B_SC_RA_RAM_STATE_PROC_STOP_4__PRE 0x0
8163#define B_SC_RA_RAM_STATE_PROC_STOP_5__PRE 0x0
8164#define B_SC_RA_RAM_STATE_PROC_STOP_6__PRE 0x0
8165#define B_SC_RA_RAM_STATE_PROC_STOP_7__PRE 0x0
8166#define B_SC_RA_RAM_STATE_PROC_STOP_8__PRE 0x0
8167#define B_SC_RA_RAM_STATE_PROC_STOP_9__PRE 0x0
8168#define B_SC_RA_RAM_STATE_PROC_STOP_10__PRE 0xFFFE
8169#define B_SC_RA_RAM_STATE_PROC_START__AX 0x820070
8170#define B_SC_RA_RAM_STATE_PROC_START__XSZ 10
8171#define B_SC_RA_RAM_STATE_PROC_START__W 16
8172#define B_SC_RA_RAM_STATE_PROC_START__M 0xFFFF
8173#define B_SC_RA_RAM_STATE_PROC_START_1__PRE 0x80
8174#define B_SC_RA_RAM_STATE_PROC_START_2__PRE 0x2
8175#define B_SC_RA_RAM_STATE_PROC_START_3__PRE 0x4
8176#define B_SC_RA_RAM_STATE_PROC_START_4__PRE 0x4
8177#define B_SC_RA_RAM_STATE_PROC_START_5__PRE 0x100
8178#define B_SC_RA_RAM_STATE_PROC_START_6__PRE 0x0
8179#define B_SC_RA_RAM_STATE_PROC_START_7__PRE 0x40
8180#define B_SC_RA_RAM_STATE_PROC_START_8__PRE 0x10
8181#define B_SC_RA_RAM_STATE_PROC_START_9__PRE 0x30
8182#define B_SC_RA_RAM_STATE_PROC_START_10__PRE 0x0
8183#define B_SC_RA_RAM_IF_SAVE__AX 0x82008E
8184#define B_SC_RA_RAM_IF_SAVE__XSZ 2
8185#define B_SC_RA_RAM_IF_SAVE__W 16
8186#define B_SC_RA_RAM_IF_SAVE__M 0xFFFF
8187#define B_SC_RA_RAM_FR_THRES__A 0x82007D
8188#define B_SC_RA_RAM_FR_THRES__W 16
8189#define B_SC_RA_RAM_FR_THRES__M 0xFFFF
8190#define B_SC_RA_RAM_FR_THRES__PRE 0x1A2C
8191#define B_SC_RA_RAM_STATUS__A 0x82007E
8192#define B_SC_RA_RAM_STATUS__W 16
8193#define B_SC_RA_RAM_STATUS__M 0xFFFF
8194#define B_SC_RA_RAM_NF_BORDER_INIT__A 0x82007F
8195#define B_SC_RA_RAM_NF_BORDER_INIT__W 16
8196#define B_SC_RA_RAM_NF_BORDER_INIT__M 0xFFFF
8197#define B_SC_RA_RAM_NF_BORDER_INIT__PRE 0x708
8198#define B_SC_RA_RAM_TIMER__A 0x820080
8199#define B_SC_RA_RAM_TIMER__W 16
8200#define B_SC_RA_RAM_TIMER__M 0xFFFF
8201#define B_SC_RA_RAM_FI_OFFSET__A 0x820081
8202#define B_SC_RA_RAM_FI_OFFSET__W 16
8203#define B_SC_RA_RAM_FI_OFFSET__M 0xFFFF
8204#define B_SC_RA_RAM_FI_OFFSET__PRE 0x382
8205#define B_SC_RA_RAM_ECHO_GUARD__A 0x820082
8206#define B_SC_RA_RAM_ECHO_GUARD__W 16
8207#define B_SC_RA_RAM_ECHO_GUARD__M 0xFFFF
8208#define B_SC_RA_RAM_ECHO_GUARD__PRE 0x18
8209#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__A 0x8200BA
8210#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__W 16
8211#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__M 0xFFFF
8212#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_CO__PRE 0x3
8213#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__A 0x8200BB
8214#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__W 16
8215#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__M 0xFFFF
8216#define B_SC_RA_RAM_PILOT_CPD_EXP_MARG_TILT__PRE 0x0
8217
8218
8219
8220
8221
8222#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x820098
8223#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__W 16
8224#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__M 0xFFFF
8225#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__PRE 0x258
8226#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A 0x820099
8227#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__W 16
8228#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__M 0xFFFF
8229#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__PRE 0x258
8230#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A 0x82009A
8231#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__W 16
8232#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__M 0xFFFF
8233#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__PRE 0x258
8234#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A 0x82009B
8235#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__W 16
8236#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__M 0xFFFF
8237#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__PRE 0x258
8238
8239
8240
8241#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x82009C
8242#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__W 16
8243#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__M 0xFFFF
8244#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__PRE 0xDAC
8245#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A 0x82009D
8246#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__W 16
8247#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__M 0xFFFF
8248#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__PRE 0xDAC
8249#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A 0x82009E
8250#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__W 16
8251#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__M 0xFFFF
8252#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__PRE 0xDAC
8253#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A 0x82009F
8254#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__W 16
8255#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__M 0xFFFF
8256#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__PRE 0xDAC
8257
8258
8259
8260#define B_SC_RA_RAM_IR_FREQ__A 0x8200D0
8261#define B_SC_RA_RAM_IR_FREQ__W 16
8262#define B_SC_RA_RAM_IR_FREQ__M 0xFFFF
8263#define B_SC_RA_RAM_IR_FREQ__PRE 0x0
8264
8265
8266
8267
8268
8269#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1
8270#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__W 16
8271#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__M 0xFFFF
8272#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9
8273#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2
8274#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__W 16
8275#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__M 0xFFFF
8276#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4
8277#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3
8278#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__W 16
8279#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__M 0xFFFF
8280#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100
8281
8282
8283
8284#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4
8285#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__W 16
8286#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__M 0xFFFF
8287#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8
8288#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5
8289#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__W 16
8290#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__M 0xFFFF
8291#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8
8292#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6
8293#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__W 16
8294#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__M 0xFFFF
8295#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200
8296
8297
8298
8299
8300
8301#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7
8302#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__W 16
8303#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__M 0xFFFF
8304#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9
8305#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8
8306#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__W 16
8307#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__M 0xFFFF
8308#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4
8309#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9
8310#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__W 16
8311#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__M 0xFFFF
8312#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100
8313
8314
8315
8316#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA
8317#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__W 16
8318#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__M 0xFFFF
8319#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB
8320#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB
8321#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__W 16
8322#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__M 0xFFFF
8323#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1
8324#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC
8325#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__W 16
8326#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__M 0xFFFF
8327#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40
8328
8329
8330
8331#define B_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD
8332#define B_SC_RA_RAM_ECHO_SHIFT_LIM__W 16
8333#define B_SC_RA_RAM_ECHO_SHIFT_LIM__M 0xFFFF
8334#define B_SC_RA_RAM_ECHO_SHIFT_LIM__PRE 0x18
8335#define B_SC_RA_RAM_ECHO_SHT_LIM__A 0x8200DE
8336#define B_SC_RA_RAM_ECHO_SHT_LIM__W 16
8337#define B_SC_RA_RAM_ECHO_SHT_LIM__M 0xFFFF
8338#define B_SC_RA_RAM_ECHO_SHT_LIM__PRE 0x1
8339#define B_SC_RA_RAM_ECHO_SHIFT_TERM__A 0x8200DF
8340#define B_SC_RA_RAM_ECHO_SHIFT_TERM__W 16
8341#define B_SC_RA_RAM_ECHO_SHIFT_TERM__M 0xFFFF
8342#define B_SC_RA_RAM_ECHO_SHIFT_TERM__PRE 0xCC0
8343#define B_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__B 0
8344#define B_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__W 10
8345#define B_SC_RA_RAM_ECHO_SHIFT_TERM_THRES__M 0x3FF
8346#define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__B 10
8347#define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__W 6
8348#define B_SC_RA_RAM_ECHO_SHIFT_TERM_TIMEOUT__M 0xFC00
8349
8350
8351
8352
8353
8354#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A 0x8200E0
8355#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__W 16
8356#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__M 0xFFFF
8357#define B_SC_RA_RAM_NI_INIT_2K_PER_LEFT__PRE 0x7
8358#define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A 0x8200E1
8359#define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__W 16
8360#define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__M 0xFFFF
8361#define B_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__PRE 0x1
8362#define B_SC_RA_RAM_NI_INIT_2K_POS_LR__A 0x8200E2
8363#define B_SC_RA_RAM_NI_INIT_2K_POS_LR__W 16
8364#define B_SC_RA_RAM_NI_INIT_2K_POS_LR__M 0xFFFF
8365#define B_SC_RA_RAM_NI_INIT_2K_POS_LR__PRE 0xE8
8366
8367
8368
8369#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A 0x8200E3
8370#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__W 16
8371#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__M 0xFFFF
8372#define B_SC_RA_RAM_NI_INIT_8K_PER_LEFT__PRE 0xE
8373#define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A 0x8200E4
8374#define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__W 16
8375#define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__M 0xFFFF
8376#define B_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__PRE 0x7
8377#define B_SC_RA_RAM_NI_INIT_8K_POS_LR__A 0x8200E5
8378#define B_SC_RA_RAM_NI_INIT_8K_POS_LR__W 16
8379#define B_SC_RA_RAM_NI_INIT_8K_POS_LR__M 0xFFFF
8380#define B_SC_RA_RAM_NI_INIT_8K_POS_LR__PRE 0xA0
8381
8382
8383
8384#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8
8385#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__W 16
8386#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__M 0xFFFF
8387#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__PRE 0x2
8388#define B_SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9
8389#define B_SC_RA_RAM_SAMPLE_RATE_STEP__W 16
8390#define B_SC_RA_RAM_SAMPLE_RATE_STEP__M 0xFFFF
8391#define B_SC_RA_RAM_SAMPLE_RATE_STEP__PRE 0x44C
8392
8393
8394
8395#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__A 0x8200EA
8396#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__W 16
8397#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__M 0xFFFF
8398#define B_SC_RA_RAM_TPS_TIMEOUT_LIM__PRE 0xC8
8399#define B_SC_RA_RAM_TPS_TIMEOUT__A 0x8200EB
8400#define B_SC_RA_RAM_TPS_TIMEOUT__W 16
8401#define B_SC_RA_RAM_TPS_TIMEOUT__M 0xFFFF
8402#define B_SC_RA_RAM_BAND__A 0x8200EC
8403#define B_SC_RA_RAM_BAND__W 16
8404#define B_SC_RA_RAM_BAND__M 0xFFFF
8405#define B_SC_RA_RAM_BAND__PRE 0x0
8406#define B_SC_RA_RAM_BAND_INTERVAL__B 0
8407#define B_SC_RA_RAM_BAND_INTERVAL__W 4
8408#define B_SC_RA_RAM_BAND_INTERVAL__M 0xF
8409#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__B 8
8410#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__W 1
8411#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_32__M 0x100
8412#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__B 9
8413#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__W 1
8414#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_16__M 0x200
8415#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__B 10
8416#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__W 1
8417#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_8__M 0x400
8418#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__B 11
8419#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__W 1
8420#define B_SC_RA_RAM_BAND_INTERVAL_ENABLE_4__M 0x800
8421#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__B 12
8422#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__W 1
8423#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_32__M 0x1000
8424#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__B 13
8425#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__W 1
8426#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_16__M 0x2000
8427#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__B 14
8428#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__W 1
8429#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_8__M 0x4000
8430#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__B 15
8431#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__W 1
8432#define B_SC_RA_RAM_BAND_HIL_MAR_ENABLE_4__M 0x8000
8433
8434#define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__A 0x8200ED
8435#define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__W 16
8436#define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__M 0xFFFF
8437#define B_SC_RA_RAM_EC_OC_CRA_HIP_INIT__PRE 0xC0
8438#define B_SC_RA_RAM_REG__AX 0x8200F0
8439#define B_SC_RA_RAM_REG__XSZ 2
8440#define B_SC_RA_RAM_REG__W 16
8441#define B_SC_RA_RAM_REG__M 0xFFFF
8442#define B_SC_RA_RAM_BREAK__A 0x8200F2
8443#define B_SC_RA_RAM_BREAK__W 16
8444#define B_SC_RA_RAM_BREAK__M 0xFFFF
8445#define B_SC_RA_RAM_BOOTCOUNT__A 0x8200F3
8446#define B_SC_RA_RAM_BOOTCOUNT__W 16
8447#define B_SC_RA_RAM_BOOTCOUNT__M 0xFFFF
8448
8449
8450
8451#define B_SC_RA_RAM_LC_ABS_2K__A 0x8200F4
8452#define B_SC_RA_RAM_LC_ABS_2K__W 16
8453#define B_SC_RA_RAM_LC_ABS_2K__M 0xFFFF
8454#define B_SC_RA_RAM_LC_ABS_2K__PRE 0x1F
8455#define B_SC_RA_RAM_LC_ABS_8K__A 0x8200F5
8456#define B_SC_RA_RAM_LC_ABS_8K__W 16
8457#define B_SC_RA_RAM_LC_ABS_8K__M 0xFFFF
8458#define B_SC_RA_RAM_LC_ABS_8K__PRE 0x1F
8459#define B_SC_RA_RAM_NE_ERR_SELECT__A 0x8200F6
8460#define B_SC_RA_RAM_NE_ERR_SELECT__W 16
8461#define B_SC_RA_RAM_NE_ERR_SELECT__M 0xFFFF
8462#define B_SC_RA_RAM_NE_ERR_SELECT__PRE 0x19
8463#define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__A 0x8200F7
8464#define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__W 16
8465#define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__M 0xFFFF
8466#define B_SC_RA_RAM_CP_GAIN_PEXP_SUB__PRE 0x14
8467#define B_SC_RA_RAM_RELOCK__A 0x8200FE
8468#define B_SC_RA_RAM_RELOCK__W 16
8469#define B_SC_RA_RAM_RELOCK__M 0xFFFF
8470#define B_SC_RA_RAM_STACKUNDERFLOW__A 0x8200FF
8471#define B_SC_RA_RAM_STACKUNDERFLOW__W 16
8472#define B_SC_RA_RAM_STACKUNDERFLOW__M 0xFFFF
8473
8474
8475
8476#define B_SC_RA_RAM_NF_MAXECHOTOKEN__A 0x820148
8477#define B_SC_RA_RAM_NF_MAXECHOTOKEN__W 16
8478#define B_SC_RA_RAM_NF_MAXECHOTOKEN__M 0xFFFF
8479#define B_SC_RA_RAM_NF_PREPOST__A 0x820149
8480#define B_SC_RA_RAM_NF_PREPOST__W 16
8481#define B_SC_RA_RAM_NF_PREPOST__M 0xFFFF
8482#define B_SC_RA_RAM_NF_PREBORDER__A 0x82014A
8483#define B_SC_RA_RAM_NF_PREBORDER__W 16
8484#define B_SC_RA_RAM_NF_PREBORDER__M 0xFFFF
8485#define B_SC_RA_RAM_NF_START__A 0x82014B
8486#define B_SC_RA_RAM_NF_START__W 16
8487#define B_SC_RA_RAM_NF_START__M 0xFFFF
8488#define B_SC_RA_RAM_NF_MINISI__AX 0x82014C
8489#define B_SC_RA_RAM_NF_MINISI__XSZ 2
8490#define B_SC_RA_RAM_NF_MINISI__W 16
8491#define B_SC_RA_RAM_NF_MINISI__M 0xFFFF
8492#define B_SC_RA_RAM_NF_MAXECHO__A 0x82014E
8493#define B_SC_RA_RAM_NF_MAXECHO__W 16
8494#define B_SC_RA_RAM_NF_MAXECHO__M 0xFFFF
8495#define B_SC_RA_RAM_NF_NRECHOES__A 0x82014F
8496#define B_SC_RA_RAM_NF_NRECHOES__W 16
8497#define B_SC_RA_RAM_NF_NRECHOES__M 0xFFFF
8498#define B_SC_RA_RAM_NF_ECHOTABLE__AX 0x820150
8499#define B_SC_RA_RAM_NF_ECHOTABLE__XSZ 16
8500#define B_SC_RA_RAM_NF_ECHOTABLE__W 16
8501#define B_SC_RA_RAM_NF_ECHOTABLE__M 0xFFFF
8502
8503
8504
8505
8506
8507#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__A 0x8201A0
8508#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__W 16
8509#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__M 0xFFFF
8510#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x100
8511#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__A 0x8201A1
8512#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__W 16
8513#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__M 0xFFFF
8514#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4
8515
8516
8517
8518#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__A 0x8201A2
8519#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__W 16
8520#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__M 0xFFFF
8521#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1E2
8522#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__A 0x8201A3
8523#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__W 16
8524#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__M 0xFFFF
8525#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4
8526
8527
8528
8529#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__A 0x8201A4
8530#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__W 16
8531#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__M 0xFFFF
8532#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x10D
8533#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__A 0x8201A5
8534#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__W 16
8535#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__M 0xFFFF
8536#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5
8537
8538
8539
8540#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__A 0x8201A6
8541#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__W 16
8542#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__M 0xFFFF
8543#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x17D
8544#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__A 0x8201A7
8545#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__W 16
8546#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__M 0xFFFF
8547#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4
8548
8549
8550
8551#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__A 0x8201A8
8552#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__W 16
8553#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__M 0xFFFF
8554#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x133
8555#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__A 0x8201A9
8556#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__W 16
8557#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__M 0xFFFF
8558#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5
8559
8560
8561
8562#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__A 0x8201AA
8563#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__W 16
8564#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__M 0xFFFF
8565#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x114
8566#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__A 0x8201AB
8567#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__W 16
8568#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__M 0xFFFF
8569#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5
8570
8571
8572
8573#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__A 0x8201AC
8574#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__W 16
8575#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__M 0xFFFF
8576#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x14A
8577#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__A 0x8201AD
8578#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__W 16
8579#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__M 0xFFFF
8580#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4
8581
8582
8583
8584#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__A 0x8201AE
8585#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__W 16
8586#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__M 0xFFFF
8587#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x1BB
8588#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__A 0x8201AF
8589#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__W 16
8590#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__M 0xFFFF
8591#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x4
8592#define B_SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE
8593#define B_SC_RA_RAM_DRIVER_VERSION__XSZ 2
8594#define B_SC_RA_RAM_DRIVER_VERSION__W 16
8595#define B_SC_RA_RAM_DRIVER_VERSION__M 0xFFFF
8596#define B_SC_RA_RAM_EVENT0_MIN 0x7
8597#define B_SC_RA_RAM_EVENT0_FE_CU 0x7
8598#define B_SC_RA_RAM_EVENT0_CE 0xA
8599#define B_SC_RA_RAM_EVENT0_EQ 0xE
8600#define B_SC_RA_RAM_EVENT0_MAX 0xF
8601#define B_SC_RA_RAM_PROC_LOCKTRACK 0x0
8602#define B_SC_RA_RAM_PROC_MODE_GUARD 0x1
8603#define B_SC_RA_RAM_PROC_PILOTS 0x2
8604#define B_SC_RA_RAM_PROC_FESTART_ADJUST 0x3
8605#define B_SC_RA_RAM_PROC_ECHO 0x4
8606#define B_SC_RA_RAM_PROC_BE_OPT 0x5
8607#define B_SC_RA_RAM_PROC_LOCK_MON 0x6
8608#define B_SC_RA_RAM_PROC_EQ 0x7
8609#define B_SC_RA_RAM_PROC_ECHO_DIVERSITY 0x8
8610#define B_SC_RA_RAM_PROC_MAX 0x9
8611
8612
8613
8614
8615
8616
8617#define B_SC_IF_RAM_TRP_RST__AX 0x830000
8618#define B_SC_IF_RAM_TRP_RST__XSZ 2
8619#define B_SC_IF_RAM_TRP_RST__W 12
8620#define B_SC_IF_RAM_TRP_RST__M 0xFFF
8621
8622#define B_SC_IF_RAM_TRP_BPT0__AX 0x830002
8623#define B_SC_IF_RAM_TRP_BPT0__XSZ 2
8624#define B_SC_IF_RAM_TRP_BPT0__W 12
8625#define B_SC_IF_RAM_TRP_BPT0__M 0xFFF
8626
8627#define B_SC_IF_RAM_TRP_STKU__AX 0x830004
8628#define B_SC_IF_RAM_TRP_STKU__XSZ 2
8629#define B_SC_IF_RAM_TRP_STKU__W 12
8630#define B_SC_IF_RAM_TRP_STKU__M 0xFFF
8631
8632
8633
8634
8635#define B_SC_IF_RAM_VERSION_MA_MI__A 0x830FFE
8636#define B_SC_IF_RAM_VERSION_MA_MI__W 12
8637#define B_SC_IF_RAM_VERSION_MA_MI__M 0xFFF
8638
8639#define B_SC_IF_RAM_VERSION_PATCH__A 0x830FFF
8640#define B_SC_IF_RAM_VERSION_PATCH__W 12
8641#define B_SC_IF_RAM_VERSION_PATCH__M 0xFFF
8642
8643
8644
8645
8646
8647
8648
8649
8650
8651#define B_FE_COMM_EXEC__A 0xC00000
8652#define B_FE_COMM_EXEC__W 3
8653#define B_FE_COMM_EXEC__M 0x7
8654#define B_FE_COMM_EXEC_CTL__B 0
8655#define B_FE_COMM_EXEC_CTL__W 3
8656#define B_FE_COMM_EXEC_CTL__M 0x7
8657#define B_FE_COMM_EXEC_CTL_STOP 0x0
8658#define B_FE_COMM_EXEC_CTL_ACTIVE 0x1
8659#define B_FE_COMM_EXEC_CTL_HOLD 0x2
8660#define B_FE_COMM_EXEC_CTL_STEP 0x3
8661#define B_FE_COMM_EXEC_CTL_BYPASS_STOP 0x4
8662#define B_FE_COMM_EXEC_CTL_BYPASS_HOLD 0x6
8663
8664#define B_FE_COMM_STATE__A 0xC00001
8665#define B_FE_COMM_STATE__W 16
8666#define B_FE_COMM_STATE__M 0xFFFF
8667#define B_FE_COMM_MB__A 0xC00002
8668#define B_FE_COMM_MB__W 16
8669#define B_FE_COMM_MB__M 0xFFFF
8670#define B_FE_COMM_SERVICE0__A 0xC00003
8671#define B_FE_COMM_SERVICE0__W 16
8672#define B_FE_COMM_SERVICE0__M 0xFFFF
8673#define B_FE_COMM_SERVICE1__A 0xC00004
8674#define B_FE_COMM_SERVICE1__W 16
8675#define B_FE_COMM_SERVICE1__M 0xFFFF
8676#define B_FE_COMM_INT_STA__A 0xC00007
8677#define B_FE_COMM_INT_STA__W 16
8678#define B_FE_COMM_INT_STA__M 0xFFFF
8679#define B_FE_COMM_INT_MSK__A 0xC00008
8680#define B_FE_COMM_INT_MSK__W 16
8681#define B_FE_COMM_INT_MSK__M 0xFFFF
8682
8683
8684
8685
8686
8687#define B_FE_AD_SID 0x1
8688
8689
8690
8691
8692
8693
8694#define B_FE_AD_REG_COMM_EXEC__A 0xC10000
8695#define B_FE_AD_REG_COMM_EXEC__W 3
8696#define B_FE_AD_REG_COMM_EXEC__M 0x7
8697#define B_FE_AD_REG_COMM_EXEC_CTL__B 0
8698#define B_FE_AD_REG_COMM_EXEC_CTL__W 3
8699#define B_FE_AD_REG_COMM_EXEC_CTL__M 0x7
8700#define B_FE_AD_REG_COMM_EXEC_CTL_STOP 0x0
8701#define B_FE_AD_REG_COMM_EXEC_CTL_ACTIVE 0x1
8702#define B_FE_AD_REG_COMM_EXEC_CTL_HOLD 0x2
8703#define B_FE_AD_REG_COMM_EXEC_CTL_STEP 0x3
8704
8705
8706#define B_FE_AD_REG_COMM_MB__A 0xC10002
8707#define B_FE_AD_REG_COMM_MB__W 2
8708#define B_FE_AD_REG_COMM_MB__M 0x3
8709#define B_FE_AD_REG_COMM_MB_CTR__B 0
8710#define B_FE_AD_REG_COMM_MB_CTR__W 1
8711#define B_FE_AD_REG_COMM_MB_CTR__M 0x1
8712#define B_FE_AD_REG_COMM_MB_CTR_OFF 0x0
8713#define B_FE_AD_REG_COMM_MB_CTR_ON 0x1
8714#define B_FE_AD_REG_COMM_MB_OBS__B 1
8715#define B_FE_AD_REG_COMM_MB_OBS__W 1
8716#define B_FE_AD_REG_COMM_MB_OBS__M 0x2
8717#define B_FE_AD_REG_COMM_MB_OBS_OFF 0x0
8718#define B_FE_AD_REG_COMM_MB_OBS_ON 0x2
8719
8720#define B_FE_AD_REG_COMM_SERVICE0__A 0xC10003
8721#define B_FE_AD_REG_COMM_SERVICE0__W 10
8722#define B_FE_AD_REG_COMM_SERVICE0__M 0x3FF
8723#define B_FE_AD_REG_COMM_SERVICE0_FE_AD__B 0
8724#define B_FE_AD_REG_COMM_SERVICE0_FE_AD__W 1
8725#define B_FE_AD_REG_COMM_SERVICE0_FE_AD__M 0x1
8726
8727#define B_FE_AD_REG_COMM_SERVICE1__A 0xC10004
8728#define B_FE_AD_REG_COMM_SERVICE1__W 11
8729#define B_FE_AD_REG_COMM_SERVICE1__M 0x7FF
8730
8731#define B_FE_AD_REG_COMM_INT_STA__A 0xC10007
8732#define B_FE_AD_REG_COMM_INT_STA__W 2
8733#define B_FE_AD_REG_COMM_INT_STA__M 0x3
8734#define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__B 0
8735#define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__W 1
8736#define B_FE_AD_REG_COMM_INT_STA_ADC_OVERFLOW__M 0x1
8737
8738
8739#define B_FE_AD_REG_COMM_INT_MSK__A 0xC10008
8740#define B_FE_AD_REG_COMM_INT_MSK__W 2
8741#define B_FE_AD_REG_COMM_INT_MSK__M 0x3
8742#define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__B 0
8743#define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__W 1
8744#define B_FE_AD_REG_COMM_INT_MSK_ADC_OVERFLOW__M 0x1
8745
8746
8747#define B_FE_AD_REG_CUR_SEL__A 0xC10010
8748#define B_FE_AD_REG_CUR_SEL__W 2
8749#define B_FE_AD_REG_CUR_SEL__M 0x3
8750#define B_FE_AD_REG_CUR_SEL_INIT 0x2
8751
8752
8753#define B_FE_AD_REG_OVERFLOW__A 0xC10011
8754#define B_FE_AD_REG_OVERFLOW__W 1
8755#define B_FE_AD_REG_OVERFLOW__M 0x1
8756#define B_FE_AD_REG_OVERFLOW_INIT 0x0
8757
8758
8759#define B_FE_AD_REG_FDB_IN__A 0xC10012
8760#define B_FE_AD_REG_FDB_IN__W 1
8761#define B_FE_AD_REG_FDB_IN__M 0x1
8762#define B_FE_AD_REG_FDB_IN_INIT 0x0
8763
8764
8765#define B_FE_AD_REG_PD__A 0xC10013
8766#define B_FE_AD_REG_PD__W 1
8767#define B_FE_AD_REG_PD__M 0x1
8768#define B_FE_AD_REG_PD_INIT 0x1
8769
8770
8771#define B_FE_AD_REG_INVEXT__A 0xC10014
8772#define B_FE_AD_REG_INVEXT__W 1
8773#define B_FE_AD_REG_INVEXT__M 0x1
8774#define B_FE_AD_REG_INVEXT_INIT 0x0
8775
8776
8777#define B_FE_AD_REG_CLKNEG__A 0xC10015
8778#define B_FE_AD_REG_CLKNEG__W 1
8779#define B_FE_AD_REG_CLKNEG__M 0x1
8780#define B_FE_AD_REG_CLKNEG_INIT 0x0
8781
8782
8783#define B_FE_AD_REG_MON_IN_MUX__A 0xC10016
8784#define B_FE_AD_REG_MON_IN_MUX__W 2
8785#define B_FE_AD_REG_MON_IN_MUX__M 0x3
8786#define B_FE_AD_REG_MON_IN_MUX_INIT 0x0
8787
8788
8789#define B_FE_AD_REG_MON_IN5__A 0xC10017
8790#define B_FE_AD_REG_MON_IN5__W 10
8791#define B_FE_AD_REG_MON_IN5__M 0x3FF
8792#define B_FE_AD_REG_MON_IN5_INIT 0x0
8793
8794
8795#define B_FE_AD_REG_MON_IN4__A 0xC10018
8796#define B_FE_AD_REG_MON_IN4__W 10
8797#define B_FE_AD_REG_MON_IN4__M 0x3FF
8798#define B_FE_AD_REG_MON_IN4_INIT 0x0
8799
8800
8801#define B_FE_AD_REG_MON_IN3__A 0xC10019
8802#define B_FE_AD_REG_MON_IN3__W 10
8803#define B_FE_AD_REG_MON_IN3__M 0x3FF
8804#define B_FE_AD_REG_MON_IN3_INIT 0x0
8805
8806
8807#define B_FE_AD_REG_MON_IN2__A 0xC1001A
8808#define B_FE_AD_REG_MON_IN2__W 10
8809#define B_FE_AD_REG_MON_IN2__M 0x3FF
8810#define B_FE_AD_REG_MON_IN2_INIT 0x0
8811
8812
8813#define B_FE_AD_REG_MON_IN1__A 0xC1001B
8814#define B_FE_AD_REG_MON_IN1__W 10
8815#define B_FE_AD_REG_MON_IN1__M 0x3FF
8816#define B_FE_AD_REG_MON_IN1_INIT 0x0
8817
8818
8819#define B_FE_AD_REG_MON_IN0__A 0xC1001C
8820#define B_FE_AD_REG_MON_IN0__W 10
8821#define B_FE_AD_REG_MON_IN0__M 0x3FF
8822#define B_FE_AD_REG_MON_IN0_INIT 0x0
8823
8824
8825#define B_FE_AD_REG_MON_IN_VAL__A 0xC1001D
8826#define B_FE_AD_REG_MON_IN_VAL__W 1
8827#define B_FE_AD_REG_MON_IN_VAL__M 0x1
8828#define B_FE_AD_REG_MON_IN_VAL_INIT 0x0
8829
8830
8831#define B_FE_AD_REG_CTR_CLK_O__A 0xC1001E
8832#define B_FE_AD_REG_CTR_CLK_O__W 1
8833#define B_FE_AD_REG_CTR_CLK_O__M 0x1
8834#define B_FE_AD_REG_CTR_CLK_O_INIT 0x0
8835
8836
8837#define B_FE_AD_REG_CTR_CLK_E_O__A 0xC1001F
8838#define B_FE_AD_REG_CTR_CLK_E_O__W 1
8839#define B_FE_AD_REG_CTR_CLK_E_O__M 0x1
8840#define B_FE_AD_REG_CTR_CLK_E_O_INIT 0x1
8841
8842
8843#define B_FE_AD_REG_CTR_VAL_O__A 0xC10020
8844#define B_FE_AD_REG_CTR_VAL_O__W 1
8845#define B_FE_AD_REG_CTR_VAL_O__M 0x1
8846#define B_FE_AD_REG_CTR_VAL_O_INIT 0x0
8847
8848
8849#define B_FE_AD_REG_CTR_VAL_E_O__A 0xC10021
8850#define B_FE_AD_REG_CTR_VAL_E_O__W 1
8851#define B_FE_AD_REG_CTR_VAL_E_O__M 0x1
8852#define B_FE_AD_REG_CTR_VAL_E_O_INIT 0x1
8853
8854
8855#define B_FE_AD_REG_CTR_DATA_O__A 0xC10022
8856#define B_FE_AD_REG_CTR_DATA_O__W 10
8857#define B_FE_AD_REG_CTR_DATA_O__M 0x3FF
8858#define B_FE_AD_REG_CTR_DATA_O_INIT 0x0
8859
8860
8861#define B_FE_AD_REG_CTR_DATA_E_O__A 0xC10023
8862#define B_FE_AD_REG_CTR_DATA_E_O__W 10
8863#define B_FE_AD_REG_CTR_DATA_E_O__M 0x3FF
8864#define B_FE_AD_REG_CTR_DATA_E_O_INIT 0x3FF
8865
8866
8867
8868
8869
8870#define B_FE_AG_SID 0x2
8871
8872
8873
8874
8875
8876
8877#define B_FE_AG_REG_COMM_EXEC__A 0xC20000
8878#define B_FE_AG_REG_COMM_EXEC__W 3
8879#define B_FE_AG_REG_COMM_EXEC__M 0x7
8880#define B_FE_AG_REG_COMM_EXEC_CTL__B 0
8881#define B_FE_AG_REG_COMM_EXEC_CTL__W 3
8882#define B_FE_AG_REG_COMM_EXEC_CTL__M 0x7
8883#define B_FE_AG_REG_COMM_EXEC_CTL_STOP 0x0
8884#define B_FE_AG_REG_COMM_EXEC_CTL_ACTIVE 0x1
8885#define B_FE_AG_REG_COMM_EXEC_CTL_HOLD 0x2
8886#define B_FE_AG_REG_COMM_EXEC_CTL_STEP 0x3
8887
8888#define B_FE_AG_REG_COMM_STATE__A 0xC20001
8889#define B_FE_AG_REG_COMM_STATE__W 4
8890#define B_FE_AG_REG_COMM_STATE__M 0xF
8891
8892#define B_FE_AG_REG_COMM_MB__A 0xC20002
8893#define B_FE_AG_REG_COMM_MB__W 4
8894#define B_FE_AG_REG_COMM_MB__M 0xF
8895#define B_FE_AG_REG_COMM_MB_OBS__B 1
8896#define B_FE_AG_REG_COMM_MB_OBS__W 1
8897#define B_FE_AG_REG_COMM_MB_OBS__M 0x2
8898#define B_FE_AG_REG_COMM_MB_OBS_OFF 0x0
8899#define B_FE_AG_REG_COMM_MB_OBS_ON 0x2
8900#define B_FE_AG_REG_COMM_MB_MUX__B 2
8901#define B_FE_AG_REG_COMM_MB_MUX__W 2
8902#define B_FE_AG_REG_COMM_MB_MUX__M 0xC
8903#define B_FE_AG_REG_COMM_MB_MUX_DAT 0x0
8904#define B_FE_AG_REG_COMM_MB_MUX_DAT_PD2 0x4
8905#define B_FE_AG_REG_COMM_MB_MUX_DAT_PD1 0x8
8906#define B_FE_AG_REG_COMM_MB_MUX_DAT_IND_PD1 0xC
8907
8908
8909#define B_FE_AG_REG_COMM_SERVICE0__A 0xC20003
8910#define B_FE_AG_REG_COMM_SERVICE0__W 10
8911#define B_FE_AG_REG_COMM_SERVICE0__M 0x3FF
8912
8913#define B_FE_AG_REG_COMM_SERVICE1__A 0xC20004
8914#define B_FE_AG_REG_COMM_SERVICE1__W 11
8915#define B_FE_AG_REG_COMM_SERVICE1__M 0x7FF
8916
8917#define B_FE_AG_REG_COMM_INT_STA__A 0xC20007
8918#define B_FE_AG_REG_COMM_INT_STA__W 8
8919#define B_FE_AG_REG_COMM_INT_STA__M 0xFF
8920#define B_FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__B 0
8921#define B_FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__W 1
8922#define B_FE_AG_REG_COMM_INT_STA_DCE_AVE_UPD__M 0x1
8923#define B_FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__B 1
8924#define B_FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__W 1
8925#define B_FE_AG_REG_COMM_INT_STA_ACE_AVE_UPD__M 0x2
8926#define B_FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__B 2
8927#define B_FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__W 1
8928#define B_FE_AG_REG_COMM_INT_STA_CDR_CLP_UPD__M 0x4
8929#define B_FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__B 3
8930#define B_FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__W 1
8931#define B_FE_AG_REG_COMM_INT_STA_AEC_AVE_UPD__M 0x8
8932#define B_FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__B 4
8933#define B_FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__W 1
8934#define B_FE_AG_REG_COMM_INT_STA_PDA_AVE_UPD__M 0x10
8935#define B_FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__B 5
8936#define B_FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__W 1
8937#define B_FE_AG_REG_COMM_INT_STA_TGA_AVE_UPD__M 0x20
8938#define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__B 7
8939#define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__W 1
8940#define B_FE_AG_REG_COMM_INT_STA_BGC_PGA_UPD__M 0x80
8941
8942
8943#define B_FE_AG_REG_COMM_INT_MSK__A 0xC20008
8944#define B_FE_AG_REG_COMM_INT_MSK__W 8
8945#define B_FE_AG_REG_COMM_INT_MSK__M 0xFF
8946#define B_FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__B 0
8947#define B_FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__W 1
8948#define B_FE_AG_REG_COMM_INT_MSK_DCE_AVE_UPD__M 0x1
8949#define B_FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__B 1
8950#define B_FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__W 1
8951#define B_FE_AG_REG_COMM_INT_MSK_ACE_AVE_UPD__M 0x2
8952#define B_FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__B 2
8953#define B_FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__W 1
8954#define B_FE_AG_REG_COMM_INT_MSK_CDR_CLP_UPD__M 0x4
8955#define B_FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__B 3
8956#define B_FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__W 1
8957#define B_FE_AG_REG_COMM_INT_MSK_AEC_AVE_UPD__M 0x8
8958#define B_FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__B 4
8959#define B_FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__W 1
8960#define B_FE_AG_REG_COMM_INT_MSK_PDA_AVE_UPD__M 0x10
8961#define B_FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__B 5
8962#define B_FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__W 1
8963#define B_FE_AG_REG_COMM_INT_MSK_TGA_AVE_UPD__M 0x20
8964#define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__B 7
8965#define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__W 1
8966#define B_FE_AG_REG_COMM_INT_MSK_BGC_PGA_UPD__M 0x80
8967
8968
8969#define B_FE_AG_REG_AG_MODE_LOP__A 0xC20010
8970#define B_FE_AG_REG_AG_MODE_LOP__W 15
8971#define B_FE_AG_REG_AG_MODE_LOP__M 0x7FFF
8972#define B_FE_AG_REG_AG_MODE_LOP_INIT 0x81E
8973
8974#define B_FE_AG_REG_AG_MODE_LOP_MODE_0__B 0
8975#define B_FE_AG_REG_AG_MODE_LOP_MODE_0__W 1
8976#define B_FE_AG_REG_AG_MODE_LOP_MODE_0__M 0x1
8977#define B_FE_AG_REG_AG_MODE_LOP_MODE_0_ENABLE 0x0
8978#define B_FE_AG_REG_AG_MODE_LOP_MODE_0_DISABLE 0x1
8979
8980#define B_FE_AG_REG_AG_MODE_LOP_MODE_1__B 1
8981#define B_FE_AG_REG_AG_MODE_LOP_MODE_1__W 1
8982#define B_FE_AG_REG_AG_MODE_LOP_MODE_1__M 0x2
8983#define B_FE_AG_REG_AG_MODE_LOP_MODE_1_STATIC 0x0
8984#define B_FE_AG_REG_AG_MODE_LOP_MODE_1_DYNAMIC 0x2
8985
8986#define B_FE_AG_REG_AG_MODE_LOP_MODE_2__B 2
8987#define B_FE_AG_REG_AG_MODE_LOP_MODE_2__W 1
8988#define B_FE_AG_REG_AG_MODE_LOP_MODE_2__M 0x4
8989#define B_FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_B 0x0
8990#define B_FE_AG_REG_AG_MODE_LOP_MODE_2_AVE_CB 0x4
8991
8992#define B_FE_AG_REG_AG_MODE_LOP_MODE_3__B 3
8993#define B_FE_AG_REG_AG_MODE_LOP_MODE_3__W 1
8994#define B_FE_AG_REG_AG_MODE_LOP_MODE_3__M 0x8
8995#define B_FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_B 0x0
8996#define B_FE_AG_REG_AG_MODE_LOP_MODE_3_AVE_CB 0x8
8997
8998#define B_FE_AG_REG_AG_MODE_LOP_MODE_4__B 4
8999#define B_FE_AG_REG_AG_MODE_LOP_MODE_4__W 1
9000#define B_FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10
9001#define B_FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0
9002#define B_FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10
9003
9004#define B_FE_AG_REG_AG_MODE_LOP_MODE_5__B 5
9005#define B_FE_AG_REG_AG_MODE_LOP_MODE_5__W 1
9006#define B_FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20
9007#define B_FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0
9008#define B_FE_AG_REG_AG_MODE_LOP_MODE_5_DYNAMIC 0x20
9009
9010#define B_FE_AG_REG_AG_MODE_LOP_MODE_6__B 6
9011#define B_FE_AG_REG_AG_MODE_LOP_MODE_6__W 1
9012#define B_FE_AG_REG_AG_MODE_LOP_MODE_6__M 0x40
9013#define B_FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_B 0x0
9014#define B_FE_AG_REG_AG_MODE_LOP_MODE_6_AVE_CB 0x40
9015
9016#define B_FE_AG_REG_AG_MODE_LOP_MODE_7__B 7
9017#define B_FE_AG_REG_AG_MODE_LOP_MODE_7__W 1
9018#define B_FE_AG_REG_AG_MODE_LOP_MODE_7__M 0x80
9019#define B_FE_AG_REG_AG_MODE_LOP_MODE_7_DYNAMIC 0x0
9020#define B_FE_AG_REG_AG_MODE_LOP_MODE_7_STATIC 0x80
9021
9022#define B_FE_AG_REG_AG_MODE_LOP_MODE_8__B 8
9023#define B_FE_AG_REG_AG_MODE_LOP_MODE_8__W 1
9024#define B_FE_AG_REG_AG_MODE_LOP_MODE_8__M 0x100
9025#define B_FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_B 0x0
9026#define B_FE_AG_REG_AG_MODE_LOP_MODE_8_AVE_CB 0x100
9027
9028#define B_FE_AG_REG_AG_MODE_LOP_MODE_B__B 11
9029#define B_FE_AG_REG_AG_MODE_LOP_MODE_B__W 1
9030#define B_FE_AG_REG_AG_MODE_LOP_MODE_B__M 0x800
9031#define B_FE_AG_REG_AG_MODE_LOP_MODE_B_START 0x0
9032#define B_FE_AG_REG_AG_MODE_LOP_MODE_B_ALWAYS 0x800
9033
9034#define B_FE_AG_REG_AG_MODE_LOP_MODE_9__B 9
9035#define B_FE_AG_REG_AG_MODE_LOP_MODE_9__W 1
9036#define B_FE_AG_REG_AG_MODE_LOP_MODE_9__M 0x200
9037#define B_FE_AG_REG_AG_MODE_LOP_MODE_9_STATIC 0x0
9038#define B_FE_AG_REG_AG_MODE_LOP_MODE_9_DYNAMIC 0x200
9039
9040#define B_FE_AG_REG_AG_MODE_LOP_MODE_C__B 12
9041#define B_FE_AG_REG_AG_MODE_LOP_MODE_C__W 1
9042#define B_FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000
9043#define B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0
9044#define B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000
9045
9046#define B_FE_AG_REG_AG_MODE_LOP_MODE_D__B 13
9047#define B_FE_AG_REG_AG_MODE_LOP_MODE_D__W 1
9048#define B_FE_AG_REG_AG_MODE_LOP_MODE_D__M 0x2000
9049#define B_FE_AG_REG_AG_MODE_LOP_MODE_D_START 0x0
9050#define B_FE_AG_REG_AG_MODE_LOP_MODE_D_ALWAYS 0x2000
9051
9052#define B_FE_AG_REG_AG_MODE_LOP_MODE_E__B 14
9053#define B_FE_AG_REG_AG_MODE_LOP_MODE_E__W 1
9054#define B_FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000
9055#define B_FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0
9056#define B_FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000
9057
9058
9059#define B_FE_AG_REG_AG_MODE_HIP__A 0xC20011
9060#define B_FE_AG_REG_AG_MODE_HIP__W 5
9061#define B_FE_AG_REG_AG_MODE_HIP__M 0x1F
9062#define B_FE_AG_REG_AG_MODE_HIP_INIT 0x0
9063
9064#define B_FE_AG_REG_AG_MODE_HIP_MODE_G__B 0
9065#define B_FE_AG_REG_AG_MODE_HIP_MODE_G__W 1
9066#define B_FE_AG_REG_AG_MODE_HIP_MODE_G__M 0x1
9067#define B_FE_AG_REG_AG_MODE_HIP_MODE_G_OUTPUT 0x0
9068#define B_FE_AG_REG_AG_MODE_HIP_MODE_G_ENABLE 0x1
9069
9070#define B_FE_AG_REG_AG_MODE_HIP_MODE_H__B 1
9071#define B_FE_AG_REG_AG_MODE_HIP_MODE_H__W 1
9072#define B_FE_AG_REG_AG_MODE_HIP_MODE_H__M 0x2
9073#define B_FE_AG_REG_AG_MODE_HIP_MODE_H_OUTPUT 0x0
9074#define B_FE_AG_REG_AG_MODE_HIP_MODE_H_ENABLE 0x2
9075
9076#define B_FE_AG_REG_AG_MODE_HIP_MODE_I__B 2
9077#define B_FE_AG_REG_AG_MODE_HIP_MODE_I__W 1
9078#define B_FE_AG_REG_AG_MODE_HIP_MODE_I__M 0x4
9079#define B_FE_AG_REG_AG_MODE_HIP_MODE_I_GRAPH1 0x0
9080#define B_FE_AG_REG_AG_MODE_HIP_MODE_I_GRAPH2 0x4
9081
9082#define B_FE_AG_REG_AG_MODE_HIP_MODE_J__B 3
9083#define B_FE_AG_REG_AG_MODE_HIP_MODE_J__W 1
9084#define B_FE_AG_REG_AG_MODE_HIP_MODE_J__M 0x8
9085#define B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC 0x0
9086#define B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC 0x8
9087
9088#define B_FE_AG_REG_AG_MODE_HIP_MODE_K__B 4
9089#define B_FE_AG_REG_AG_MODE_HIP_MODE_K__W 1
9090#define B_FE_AG_REG_AG_MODE_HIP_MODE_K__M 0x10
9091#define B_FE_AG_REG_AG_MODE_HIP_MODE_K_GRAPH1 0x0
9092#define B_FE_AG_REG_AG_MODE_HIP_MODE_K_GRAPH2 0x10
9093
9094
9095#define B_FE_AG_REG_AG_PGA_MODE__A 0xC20012
9096#define B_FE_AG_REG_AG_PGA_MODE__W 3
9097#define B_FE_AG_REG_AG_PGA_MODE__M 0x7
9098#define B_FE_AG_REG_AG_PGA_MODE_INIT 0x3
9099#define B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0
9100#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1
9101#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REN 0x2
9102#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REN 0x3
9103#define B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REY 0x4
9104#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REY 0x5
9105#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFN_REY 0x6
9106#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCY_AFY_REY 0x7
9107
9108
9109#define B_FE_AG_REG_AG_AGC_SIO__A 0xC20013
9110#define B_FE_AG_REG_AG_AGC_SIO__W 2
9111#define B_FE_AG_REG_AG_AGC_SIO__M 0x3
9112#define B_FE_AG_REG_AG_AGC_SIO_INIT 0x3
9113
9114#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__B 0
9115#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__W 1
9116#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1__M 0x1
9117#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_OUTPUT 0x0
9118#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_1_INPUT 0x1
9119
9120#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__B 1
9121#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__W 1
9122#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2
9123#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0
9124#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2
9125
9126
9127#define B_FE_AG_REG_AG_AGC_USR_DAT__A 0xC20014
9128#define B_FE_AG_REG_AG_AGC_USR_DAT__W 2
9129#define B_FE_AG_REG_AG_AGC_USR_DAT__M 0x3
9130#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__B 0
9131#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__W 1
9132#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_1__M 0x1
9133#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__B 1
9134#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__W 1
9135#define B_FE_AG_REG_AG_AGC_USR_DAT_USR_DAT_2__M 0x2
9136
9137
9138#define B_FE_AG_REG_AG_PWD__A 0xC20015
9139#define B_FE_AG_REG_AG_PWD__W 5
9140#define B_FE_AG_REG_AG_PWD__M 0x1F
9141#define B_FE_AG_REG_AG_PWD_INIT 0x6
9142
9143#define B_FE_AG_REG_AG_PWD_PWD_PD1__B 0
9144#define B_FE_AG_REG_AG_PWD_PWD_PD1__W 1
9145#define B_FE_AG_REG_AG_PWD_PWD_PD1__M 0x1
9146#define B_FE_AG_REG_AG_PWD_PWD_PD1_DISABLE 0x0
9147#define B_FE_AG_REG_AG_PWD_PWD_PD1_ENABLE 0x1
9148
9149#define B_FE_AG_REG_AG_PWD_PWD_PD2__B 1
9150#define B_FE_AG_REG_AG_PWD_PWD_PD2__W 1
9151#define B_FE_AG_REG_AG_PWD_PWD_PD2__M 0x2
9152#define B_FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0
9153#define B_FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2
9154
9155#define B_FE_AG_REG_AG_PWD_PWD_PGA_F__B 2
9156#define B_FE_AG_REG_AG_PWD_PWD_PGA_F__W 1
9157#define B_FE_AG_REG_AG_PWD_PWD_PGA_F__M 0x4
9158#define B_FE_AG_REG_AG_PWD_PWD_PGA_F_DISABLE 0x0
9159#define B_FE_AG_REG_AG_PWD_PWD_PGA_F_ENABLE 0x4
9160
9161#define B_FE_AG_REG_AG_PWD_PWD_PGA_C__B 3
9162#define B_FE_AG_REG_AG_PWD_PWD_PGA_C__W 1
9163#define B_FE_AG_REG_AG_PWD_PWD_PGA_C__M 0x8
9164#define B_FE_AG_REG_AG_PWD_PWD_PGA_C_DISABLE 0x0
9165#define B_FE_AG_REG_AG_PWD_PWD_PGA_C_ENABLE 0x8
9166
9167#define B_FE_AG_REG_AG_PWD_PWD_AAF__B 4
9168#define B_FE_AG_REG_AG_PWD_PWD_AAF__W 1
9169#define B_FE_AG_REG_AG_PWD_PWD_AAF__M 0x10
9170#define B_FE_AG_REG_AG_PWD_PWD_AAF_DISABLE 0x0
9171#define B_FE_AG_REG_AG_PWD_PWD_AAF_ENABLE 0x10
9172
9173
9174#define B_FE_AG_REG_DCE_AUR_CNT__A 0xC20016
9175#define B_FE_AG_REG_DCE_AUR_CNT__W 5
9176#define B_FE_AG_REG_DCE_AUR_CNT__M 0x1F
9177#define B_FE_AG_REG_DCE_AUR_CNT_INIT 0x10
9178
9179
9180#define B_FE_AG_REG_DCE_RUR_CNT__A 0xC20017
9181#define B_FE_AG_REG_DCE_RUR_CNT__W 5
9182#define B_FE_AG_REG_DCE_RUR_CNT__M 0x1F
9183#define B_FE_AG_REG_DCE_RUR_CNT_INIT 0x0
9184
9185
9186#define B_FE_AG_REG_DCE_AVE_DAT__A 0xC20018
9187#define B_FE_AG_REG_DCE_AVE_DAT__W 10
9188#define B_FE_AG_REG_DCE_AVE_DAT__M 0x3FF
9189
9190#define B_FE_AG_REG_DEC_AVE_WRI__A 0xC20019
9191#define B_FE_AG_REG_DEC_AVE_WRI__W 10
9192#define B_FE_AG_REG_DEC_AVE_WRI__M 0x3FF
9193#define B_FE_AG_REG_DEC_AVE_WRI_INIT 0x0
9194
9195
9196#define B_FE_AG_REG_ACE_AUR_CNT__A 0xC2001A
9197#define B_FE_AG_REG_ACE_AUR_CNT__W 5
9198#define B_FE_AG_REG_ACE_AUR_CNT__M 0x1F
9199#define B_FE_AG_REG_ACE_AUR_CNT_INIT 0xE
9200
9201
9202#define B_FE_AG_REG_ACE_RUR_CNT__A 0xC2001B
9203#define B_FE_AG_REG_ACE_RUR_CNT__W 5
9204#define B_FE_AG_REG_ACE_RUR_CNT__M 0x1F
9205#define B_FE_AG_REG_ACE_RUR_CNT_INIT 0x0
9206
9207
9208#define B_FE_AG_REG_ACE_AVE_DAT__A 0xC2001C
9209#define B_FE_AG_REG_ACE_AVE_DAT__W 10
9210#define B_FE_AG_REG_ACE_AVE_DAT__M 0x3FF
9211
9212#define B_FE_AG_REG_AEC_AVE_INC__A 0xC2001D
9213#define B_FE_AG_REG_AEC_AVE_INC__W 10
9214#define B_FE_AG_REG_AEC_AVE_INC__M 0x3FF
9215#define B_FE_AG_REG_AEC_AVE_INC_INIT 0x0
9216
9217
9218#define B_FE_AG_REG_AEC_AVE_DAT__A 0xC2001E
9219#define B_FE_AG_REG_AEC_AVE_DAT__W 10
9220#define B_FE_AG_REG_AEC_AVE_DAT__M 0x3FF
9221
9222#define B_FE_AG_REG_AEC_CLP_LVL__A 0xC2001F
9223#define B_FE_AG_REG_AEC_CLP_LVL__W 16
9224#define B_FE_AG_REG_AEC_CLP_LVL__M 0xFFFF
9225#define B_FE_AG_REG_AEC_CLP_LVL_INIT 0x0
9226
9227
9228#define B_FE_AG_REG_CDR_RUR_CNT__A 0xC20020
9229#define B_FE_AG_REG_CDR_RUR_CNT__W 5
9230#define B_FE_AG_REG_CDR_RUR_CNT__M 0x1F
9231#define B_FE_AG_REG_CDR_RUR_CNT_INIT 0x10
9232
9233
9234#define B_FE_AG_REG_CDR_CLP_DAT__A 0xC20021
9235#define B_FE_AG_REG_CDR_CLP_DAT__W 16
9236#define B_FE_AG_REG_CDR_CLP_DAT__M 0xFFFF
9237
9238#define B_FE_AG_REG_CDR_CLP_POS__A 0xC20022
9239#define B_FE_AG_REG_CDR_CLP_POS__W 10
9240#define B_FE_AG_REG_CDR_CLP_POS__M 0x3FF
9241#define B_FE_AG_REG_CDR_CLP_POS_INIT 0x16A
9242
9243
9244#define B_FE_AG_REG_CDR_CLP_NEG__A 0xC20023
9245#define B_FE_AG_REG_CDR_CLP_NEG__W 10
9246#define B_FE_AG_REG_CDR_CLP_NEG__M 0x3FF
9247#define B_FE_AG_REG_CDR_CLP_NEG_INIT 0x296
9248
9249
9250#define B_FE_AG_REG_EGC_RUR_CNT__A 0xC20024
9251#define B_FE_AG_REG_EGC_RUR_CNT__W 5
9252#define B_FE_AG_REG_EGC_RUR_CNT__M 0x1F
9253#define B_FE_AG_REG_EGC_RUR_CNT_INIT 0x0
9254
9255
9256#define B_FE_AG_REG_EGC_SET_LVL__A 0xC20025
9257#define B_FE_AG_REG_EGC_SET_LVL__W 9
9258#define B_FE_AG_REG_EGC_SET_LVL__M 0x1FF
9259#define B_FE_AG_REG_EGC_SET_LVL_INIT 0x46
9260
9261
9262#define B_FE_AG_REG_EGC_FLA_RGN__A 0xC20026
9263#define B_FE_AG_REG_EGC_FLA_RGN__W 9
9264#define B_FE_AG_REG_EGC_FLA_RGN__M 0x1FF
9265#define B_FE_AG_REG_EGC_FLA_RGN_INIT 0x4
9266
9267
9268#define B_FE_AG_REG_EGC_SLO_RGN__A 0xC20027
9269#define B_FE_AG_REG_EGC_SLO_RGN__W 9
9270#define B_FE_AG_REG_EGC_SLO_RGN__M 0x1FF
9271#define B_FE_AG_REG_EGC_SLO_RGN_INIT 0x1F
9272
9273
9274#define B_FE_AG_REG_EGC_JMP_PSN__A 0xC20028
9275#define B_FE_AG_REG_EGC_JMP_PSN__W 4
9276#define B_FE_AG_REG_EGC_JMP_PSN__M 0xF
9277#define B_FE_AG_REG_EGC_JMP_PSN_INIT 0x0
9278
9279
9280#define B_FE_AG_REG_EGC_FLA_INC__A 0xC20029
9281#define B_FE_AG_REG_EGC_FLA_INC__W 16
9282#define B_FE_AG_REG_EGC_FLA_INC__M 0xFFFF
9283#define B_FE_AG_REG_EGC_FLA_INC_INIT 0x0
9284
9285
9286#define B_FE_AG_REG_EGC_FLA_DEC__A 0xC2002A
9287#define B_FE_AG_REG_EGC_FLA_DEC__W 16
9288#define B_FE_AG_REG_EGC_FLA_DEC__M 0xFFFF
9289#define B_FE_AG_REG_EGC_FLA_DEC_INIT 0x0
9290
9291
9292#define B_FE_AG_REG_EGC_SLO_INC__A 0xC2002B
9293#define B_FE_AG_REG_EGC_SLO_INC__W 16
9294#define B_FE_AG_REG_EGC_SLO_INC__M 0xFFFF
9295#define B_FE_AG_REG_EGC_SLO_INC_INIT 0x3
9296
9297
9298#define B_FE_AG_REG_EGC_SLO_DEC__A 0xC2002C
9299#define B_FE_AG_REG_EGC_SLO_DEC__W 16
9300#define B_FE_AG_REG_EGC_SLO_DEC__M 0xFFFF
9301#define B_FE_AG_REG_EGC_SLO_DEC_INIT 0x3
9302
9303
9304#define B_FE_AG_REG_EGC_FAS_INC__A 0xC2002D
9305#define B_FE_AG_REG_EGC_FAS_INC__W 16
9306#define B_FE_AG_REG_EGC_FAS_INC__M 0xFFFF
9307#define B_FE_AG_REG_EGC_FAS_INC_INIT 0xE
9308
9309
9310#define B_FE_AG_REG_EGC_FAS_DEC__A 0xC2002E
9311#define B_FE_AG_REG_EGC_FAS_DEC__W 16
9312#define B_FE_AG_REG_EGC_FAS_DEC__M 0xFFFF
9313#define B_FE_AG_REG_EGC_FAS_DEC_INIT 0xE
9314
9315
9316#define B_FE_AG_REG_EGC_MAP_DAT__A 0xC2002F
9317#define B_FE_AG_REG_EGC_MAP_DAT__W 16
9318#define B_FE_AG_REG_EGC_MAP_DAT__M 0xFFFF
9319
9320#define B_FE_AG_REG_PM1_AGC_WRI__A 0xC20030
9321#define B_FE_AG_REG_PM1_AGC_WRI__W 11
9322#define B_FE_AG_REG_PM1_AGC_WRI__M 0x7FF
9323#define B_FE_AG_REG_PM1_AGC_WRI_INIT 0x0
9324
9325
9326#define B_FE_AG_REG_GC1_AGC_RIC__A 0xC20031
9327#define B_FE_AG_REG_GC1_AGC_RIC__W 16
9328#define B_FE_AG_REG_GC1_AGC_RIC__M 0xFFFF
9329#define B_FE_AG_REG_GC1_AGC_RIC_INIT 0x64
9330
9331
9332#define B_FE_AG_REG_GC1_AGC_OFF__A 0xC20032
9333#define B_FE_AG_REG_GC1_AGC_OFF__W 16
9334#define B_FE_AG_REG_GC1_AGC_OFF__M 0xFFFF
9335#define B_FE_AG_REG_GC1_AGC_OFF_INIT 0xFEC8
9336
9337
9338#define B_FE_AG_REG_GC1_AGC_MAX__A 0xC20033
9339#define B_FE_AG_REG_GC1_AGC_MAX__W 10
9340#define B_FE_AG_REG_GC1_AGC_MAX__M 0x3FF
9341#define B_FE_AG_REG_GC1_AGC_MAX_INIT 0x1FF
9342
9343
9344#define B_FE_AG_REG_GC1_AGC_MIN__A 0xC20034
9345#define B_FE_AG_REG_GC1_AGC_MIN__W 10
9346#define B_FE_AG_REG_GC1_AGC_MIN__M 0x3FF
9347#define B_FE_AG_REG_GC1_AGC_MIN_INIT 0x200
9348
9349
9350#define B_FE_AG_REG_GC1_AGC_DAT__A 0xC20035
9351#define B_FE_AG_REG_GC1_AGC_DAT__W 10
9352#define B_FE_AG_REG_GC1_AGC_DAT__M 0x3FF
9353
9354#define B_FE_AG_REG_PM2_AGC_WRI__A 0xC20036
9355#define B_FE_AG_REG_PM2_AGC_WRI__W 11
9356#define B_FE_AG_REG_PM2_AGC_WRI__M 0x7FF
9357#define B_FE_AG_REG_PM2_AGC_WRI_INIT 0x0
9358
9359
9360#define B_FE_AG_REG_GC2_AGC_RIC__A 0xC20037
9361#define B_FE_AG_REG_GC2_AGC_RIC__W 16
9362#define B_FE_AG_REG_GC2_AGC_RIC__M 0xFFFF
9363#define B_FE_AG_REG_GC2_AGC_RIC_INIT 0x64
9364
9365
9366#define B_FE_AG_REG_GC2_AGC_OFF__A 0xC20038
9367#define B_FE_AG_REG_GC2_AGC_OFF__W 16
9368#define B_FE_AG_REG_GC2_AGC_OFF__M 0xFFFF
9369#define B_FE_AG_REG_GC2_AGC_OFF_INIT 0xFEC8
9370
9371
9372#define B_FE_AG_REG_GC2_AGC_MAX__A 0xC20039
9373#define B_FE_AG_REG_GC2_AGC_MAX__W 10
9374#define B_FE_AG_REG_GC2_AGC_MAX__M 0x3FF
9375#define B_FE_AG_REG_GC2_AGC_MAX_INIT 0x1FF
9376
9377
9378#define B_FE_AG_REG_GC2_AGC_MIN__A 0xC2003A
9379#define B_FE_AG_REG_GC2_AGC_MIN__W 10
9380#define B_FE_AG_REG_GC2_AGC_MIN__M 0x3FF
9381#define B_FE_AG_REG_GC2_AGC_MIN_INIT 0x200
9382
9383
9384#define B_FE_AG_REG_GC2_AGC_DAT__A 0xC2003B
9385#define B_FE_AG_REG_GC2_AGC_DAT__W 10
9386#define B_FE_AG_REG_GC2_AGC_DAT__M 0x3FF
9387
9388#define B_FE_AG_REG_IND_WIN__A 0xC2003C
9389#define B_FE_AG_REG_IND_WIN__W 5
9390#define B_FE_AG_REG_IND_WIN__M 0x1F
9391#define B_FE_AG_REG_IND_WIN_INIT 0x0
9392
9393
9394#define B_FE_AG_REG_IND_THD_LOL__A 0xC2003D
9395#define B_FE_AG_REG_IND_THD_LOL__W 6
9396#define B_FE_AG_REG_IND_THD_LOL__M 0x3F
9397#define B_FE_AG_REG_IND_THD_LOL_INIT 0x5
9398
9399
9400#define B_FE_AG_REG_IND_THD_HIL__A 0xC2003E
9401#define B_FE_AG_REG_IND_THD_HIL__W 6
9402#define B_FE_AG_REG_IND_THD_HIL__M 0x3F
9403#define B_FE_AG_REG_IND_THD_HIL_INIT 0xF
9404
9405
9406#define B_FE_AG_REG_IND_DEL__A 0xC2003F
9407#define B_FE_AG_REG_IND_DEL__W 7
9408#define B_FE_AG_REG_IND_DEL__M 0x7F
9409#define B_FE_AG_REG_IND_DEL_INIT 0x32
9410
9411
9412#define B_FE_AG_REG_IND_PD1_WRI__A 0xC20040
9413#define B_FE_AG_REG_IND_PD1_WRI__W 6
9414#define B_FE_AG_REG_IND_PD1_WRI__M 0x3F
9415#define B_FE_AG_REG_IND_PD1_WRI_INIT 0x1E
9416
9417
9418#define B_FE_AG_REG_PDA_AUR_CNT__A 0xC20041
9419#define B_FE_AG_REG_PDA_AUR_CNT__W 5
9420#define B_FE_AG_REG_PDA_AUR_CNT__M 0x1F
9421#define B_FE_AG_REG_PDA_AUR_CNT_INIT 0x10
9422
9423
9424#define B_FE_AG_REG_PDA_RUR_CNT__A 0xC20042
9425#define B_FE_AG_REG_PDA_RUR_CNT__W 5
9426#define B_FE_AG_REG_PDA_RUR_CNT__M 0x1F
9427#define B_FE_AG_REG_PDA_RUR_CNT_INIT 0x0
9428
9429
9430#define B_FE_AG_REG_PDA_AVE_DAT__A 0xC20043
9431#define B_FE_AG_REG_PDA_AVE_DAT__W 6
9432#define B_FE_AG_REG_PDA_AVE_DAT__M 0x3F
9433
9434#define B_FE_AG_REG_PDC_RUR_CNT__A 0xC20044
9435#define B_FE_AG_REG_PDC_RUR_CNT__W 5
9436#define B_FE_AG_REG_PDC_RUR_CNT__M 0x1F
9437#define B_FE_AG_REG_PDC_RUR_CNT_INIT 0x0
9438
9439
9440#define B_FE_AG_REG_PDC_SET_LVL__A 0xC20045
9441#define B_FE_AG_REG_PDC_SET_LVL__W 6
9442#define B_FE_AG_REG_PDC_SET_LVL__M 0x3F
9443#define B_FE_AG_REG_PDC_SET_LVL_INIT 0x10
9444
9445
9446#define B_FE_AG_REG_PDC_FLA_RGN__A 0xC20046
9447#define B_FE_AG_REG_PDC_FLA_RGN__W 6
9448#define B_FE_AG_REG_PDC_FLA_RGN__M 0x3F
9449#define B_FE_AG_REG_PDC_FLA_RGN_INIT 0x0
9450
9451
9452#define B_FE_AG_REG_PDC_JMP_PSN__A 0xC20047
9453#define B_FE_AG_REG_PDC_JMP_PSN__W 3
9454#define B_FE_AG_REG_PDC_JMP_PSN__M 0x7
9455#define B_FE_AG_REG_PDC_JMP_PSN_INIT 0x0
9456
9457
9458#define B_FE_AG_REG_PDC_FLA_STP__A 0xC20048
9459#define B_FE_AG_REG_PDC_FLA_STP__W 16
9460#define B_FE_AG_REG_PDC_FLA_STP__M 0xFFFF
9461#define B_FE_AG_REG_PDC_FLA_STP_INIT 0x0
9462
9463
9464#define B_FE_AG_REG_PDC_SLO_STP__A 0xC20049
9465#define B_FE_AG_REG_PDC_SLO_STP__W 16
9466#define B_FE_AG_REG_PDC_SLO_STP__M 0xFFFF
9467#define B_FE_AG_REG_PDC_SLO_STP_INIT 0x1
9468
9469
9470#define B_FE_AG_REG_PDC_PD2_WRI__A 0xC2004A
9471#define B_FE_AG_REG_PDC_PD2_WRI__W 6
9472#define B_FE_AG_REG_PDC_PD2_WRI__M 0x3F
9473#define B_FE_AG_REG_PDC_PD2_WRI_INIT 0x1F
9474
9475
9476#define B_FE_AG_REG_PDC_MAP_DAT__A 0xC2004B
9477#define B_FE_AG_REG_PDC_MAP_DAT__W 6
9478#define B_FE_AG_REG_PDC_MAP_DAT__M 0x3F
9479
9480#define B_FE_AG_REG_PDC_MAX__A 0xC2004C
9481#define B_FE_AG_REG_PDC_MAX__W 6
9482#define B_FE_AG_REG_PDC_MAX__M 0x3F
9483#define B_FE_AG_REG_PDC_MAX_INIT 0x2
9484
9485
9486#define B_FE_AG_REG_TGA_AUR_CNT__A 0xC2004D
9487#define B_FE_AG_REG_TGA_AUR_CNT__W 5
9488#define B_FE_AG_REG_TGA_AUR_CNT__M 0x1F
9489#define B_FE_AG_REG_TGA_AUR_CNT_INIT 0x10
9490
9491
9492#define B_FE_AG_REG_TGA_RUR_CNT__A 0xC2004E
9493#define B_FE_AG_REG_TGA_RUR_CNT__W 5
9494#define B_FE_AG_REG_TGA_RUR_CNT__M 0x1F
9495#define B_FE_AG_REG_TGA_RUR_CNT_INIT 0x0
9496
9497
9498#define B_FE_AG_REG_TGA_AVE_DAT__A 0xC2004F
9499#define B_FE_AG_REG_TGA_AVE_DAT__W 6
9500#define B_FE_AG_REG_TGA_AVE_DAT__M 0x3F
9501
9502#define B_FE_AG_REG_TGC_RUR_CNT__A 0xC20050
9503#define B_FE_AG_REG_TGC_RUR_CNT__W 5
9504#define B_FE_AG_REG_TGC_RUR_CNT__M 0x1F
9505#define B_FE_AG_REG_TGC_RUR_CNT_INIT 0x0
9506
9507
9508#define B_FE_AG_REG_TGC_SET_LVL__A 0xC20051
9509#define B_FE_AG_REG_TGC_SET_LVL__W 6
9510#define B_FE_AG_REG_TGC_SET_LVL__M 0x3F
9511#define B_FE_AG_REG_TGC_SET_LVL_INIT 0x18
9512
9513
9514#define B_FE_AG_REG_TGC_FLA_RGN__A 0xC20052
9515#define B_FE_AG_REG_TGC_FLA_RGN__W 6
9516#define B_FE_AG_REG_TGC_FLA_RGN__M 0x3F
9517#define B_FE_AG_REG_TGC_FLA_RGN_INIT 0x0
9518
9519
9520#define B_FE_AG_REG_TGC_JMP_PSN__A 0xC20053
9521#define B_FE_AG_REG_TGC_JMP_PSN__W 4
9522#define B_FE_AG_REG_TGC_JMP_PSN__M 0xF
9523#define B_FE_AG_REG_TGC_JMP_PSN_INIT 0x0
9524
9525
9526#define B_FE_AG_REG_TGC_FLA_STP__A 0xC20054
9527#define B_FE_AG_REG_TGC_FLA_STP__W 16
9528#define B_FE_AG_REG_TGC_FLA_STP__M 0xFFFF
9529#define B_FE_AG_REG_TGC_FLA_STP_INIT 0x0
9530
9531
9532#define B_FE_AG_REG_TGC_SLO_STP__A 0xC20055
9533#define B_FE_AG_REG_TGC_SLO_STP__W 16
9534#define B_FE_AG_REG_TGC_SLO_STP__M 0xFFFF
9535#define B_FE_AG_REG_TGC_SLO_STP_INIT 0x1
9536
9537
9538#define B_FE_AG_REG_TGC_MAP_DAT__A 0xC20056
9539#define B_FE_AG_REG_TGC_MAP_DAT__W 10
9540#define B_FE_AG_REG_TGC_MAP_DAT__M 0x3FF
9541
9542#define B_FE_AG_REG_FGM_WRI__A 0xC20061
9543#define B_FE_AG_REG_FGM_WRI__W 10
9544#define B_FE_AG_REG_FGM_WRI__M 0x3FF
9545#define B_FE_AG_REG_FGM_WRI_INIT 0x80
9546
9547
9548#define B_FE_AG_REG_BGC_FGC_WRI__A 0xC20068
9549#define B_FE_AG_REG_BGC_FGC_WRI__W 4
9550#define B_FE_AG_REG_BGC_FGC_WRI__M 0xF
9551#define B_FE_AG_REG_BGC_FGC_WRI_INIT 0x0
9552
9553
9554#define B_FE_AG_REG_BGC_CGC_WRI__A 0xC20069
9555#define B_FE_AG_REG_BGC_CGC_WRI__W 2
9556#define B_FE_AG_REG_BGC_CGC_WRI__M 0x3
9557#define B_FE_AG_REG_BGC_CGC_WRI_INIT 0x0
9558
9559
9560#define B_FE_AG_REG_BGC_THD_LVL__A 0xC2006B
9561#define B_FE_AG_REG_BGC_THD_LVL__W 4
9562#define B_FE_AG_REG_BGC_THD_LVL__M 0xF
9563#define B_FE_AG_REG_BGC_THD_LVL_INIT 0xF
9564
9565
9566#define B_FE_AG_REG_BGC_THD_INC__A 0xC2006C
9567#define B_FE_AG_REG_BGC_THD_INC__W 4
9568#define B_FE_AG_REG_BGC_THD_INC__M 0xF
9569#define B_FE_AG_REG_BGC_THD_INC_INIT 0x8
9570
9571
9572#define B_FE_AG_REG_BGC_DAT__A 0xC2006D
9573#define B_FE_AG_REG_BGC_DAT__W 4
9574#define B_FE_AG_REG_BGC_DAT__M 0xF
9575
9576#define B_FE_AG_REG_IND_PD1_COM__A 0xC2006E
9577#define B_FE_AG_REG_IND_PD1_COM__W 6
9578#define B_FE_AG_REG_IND_PD1_COM__M 0x3F
9579#define B_FE_AG_REG_IND_PD1_COM_INIT 0x7
9580
9581
9582#define B_FE_AG_REG_AG_AGC_BUF__A 0xC2006F
9583#define B_FE_AG_REG_AG_AGC_BUF__W 2
9584#define B_FE_AG_REG_AG_AGC_BUF__M 0x3
9585#define B_FE_AG_REG_AG_AGC_BUF_INIT 0x3
9586
9587#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1__B 0
9588#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1__W 1
9589#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1__M 0x1
9590#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1_SLOW 0x0
9591#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_1_FAST 0x1
9592
9593#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2__B 1
9594#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2__W 1
9595#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2__M 0x2
9596#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2_SLOW 0x0
9597#define B_FE_AG_REG_AG_AGC_BUF_AGC_BUF_2_FAST 0x2
9598
9599
9600#define B_FE_AG_REG_PMX_SPE__A 0xC20070
9601#define B_FE_AG_REG_PMX_SPE__W 3
9602#define B_FE_AG_REG_PMX_SPE__M 0x7
9603#define B_FE_AG_REG_PMX_SPE_INIT 0x1
9604#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_1 0x0
9605#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_2 0x1
9606#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_3 0x2
9607#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_4 0x3
9608#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_5 0x4
9609#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_6 0x5
9610#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_7 0x6
9611#define B_FE_AG_REG_PMX_SPE_48MHZ_DIVIDE_BY_8 0x7
9612
9613
9614
9615
9616
9617#define B_FE_FS_SID 0x3
9618
9619
9620
9621
9622
9623
9624#define B_FE_FS_REG_COMM_EXEC__A 0xC30000
9625#define B_FE_FS_REG_COMM_EXEC__W 3
9626#define B_FE_FS_REG_COMM_EXEC__M 0x7
9627#define B_FE_FS_REG_COMM_EXEC_CTL__B 0
9628#define B_FE_FS_REG_COMM_EXEC_CTL__W 3
9629#define B_FE_FS_REG_COMM_EXEC_CTL__M 0x7
9630#define B_FE_FS_REG_COMM_EXEC_CTL_STOP 0x0
9631#define B_FE_FS_REG_COMM_EXEC_CTL_ACTIVE 0x1
9632#define B_FE_FS_REG_COMM_EXEC_CTL_HOLD 0x2
9633#define B_FE_FS_REG_COMM_EXEC_CTL_STEP 0x3
9634
9635#define B_FE_FS_REG_COMM_STATE__A 0xC30001
9636#define B_FE_FS_REG_COMM_STATE__W 4
9637#define B_FE_FS_REG_COMM_STATE__M 0xF
9638
9639#define B_FE_FS_REG_COMM_MB__A 0xC30002
9640#define B_FE_FS_REG_COMM_MB__W 3
9641#define B_FE_FS_REG_COMM_MB__M 0x7
9642#define B_FE_FS_REG_COMM_MB_CTR__B 0
9643#define B_FE_FS_REG_COMM_MB_CTR__W 1
9644#define B_FE_FS_REG_COMM_MB_CTR__M 0x1
9645#define B_FE_FS_REG_COMM_MB_CTR_OFF 0x0
9646#define B_FE_FS_REG_COMM_MB_CTR_ON 0x1
9647#define B_FE_FS_REG_COMM_MB_OBS__B 1
9648#define B_FE_FS_REG_COMM_MB_OBS__W 1
9649#define B_FE_FS_REG_COMM_MB_OBS__M 0x2
9650#define B_FE_FS_REG_COMM_MB_OBS_OFF 0x0
9651#define B_FE_FS_REG_COMM_MB_OBS_ON 0x2
9652#define B_FE_FS_REG_COMM_MB_MUX__B 2
9653#define B_FE_FS_REG_COMM_MB_MUX__W 1
9654#define B_FE_FS_REG_COMM_MB_MUX__M 0x4
9655#define B_FE_FS_REG_COMM_MB_MUX_REAL 0x0
9656#define B_FE_FS_REG_COMM_MB_MUX_IMAG 0x4
9657
9658
9659#define B_FE_FS_REG_COMM_SERVICE0__A 0xC30003
9660#define B_FE_FS_REG_COMM_SERVICE0__W 10
9661#define B_FE_FS_REG_COMM_SERVICE0__M 0x3FF
9662
9663#define B_FE_FS_REG_COMM_SERVICE1__A 0xC30004
9664#define B_FE_FS_REG_COMM_SERVICE1__W 11
9665#define B_FE_FS_REG_COMM_SERVICE1__M 0x7FF
9666
9667#define B_FE_FS_REG_COMM_ACT__A 0xC30005
9668#define B_FE_FS_REG_COMM_ACT__W 2
9669#define B_FE_FS_REG_COMM_ACT__M 0x3
9670
9671#define B_FE_FS_REG_COMM_CNT__A 0xC30006
9672#define B_FE_FS_REG_COMM_CNT__W 16
9673#define B_FE_FS_REG_COMM_CNT__M 0xFFFF
9674
9675#define B_FE_FS_REG_ADD_INC_LOP__A 0xC30010
9676#define B_FE_FS_REG_ADD_INC_LOP__W 16
9677#define B_FE_FS_REG_ADD_INC_LOP__M 0xFFFF
9678#define B_FE_FS_REG_ADD_INC_LOP_INIT 0x0
9679
9680
9681#define B_FE_FS_REG_ADD_INC_HIP__A 0xC30011
9682#define B_FE_FS_REG_ADD_INC_HIP__W 12
9683#define B_FE_FS_REG_ADD_INC_HIP__M 0xFFF
9684#define B_FE_FS_REG_ADD_INC_HIP_INIT 0xC00
9685
9686
9687#define B_FE_FS_REG_ADD_OFF__A 0xC30012
9688#define B_FE_FS_REG_ADD_OFF__W 12
9689#define B_FE_FS_REG_ADD_OFF__M 0xFFF
9690#define B_FE_FS_REG_ADD_OFF_INIT 0x0
9691
9692
9693#define B_FE_FS_REG_ADD_OFF_VAL__A 0xC30013
9694#define B_FE_FS_REG_ADD_OFF_VAL__W 1
9695#define B_FE_FS_REG_ADD_OFF_VAL__M 0x1
9696#define B_FE_FS_REG_ADD_OFF_VAL_INIT 0x0
9697
9698
9699
9700
9701
9702#define B_FE_FD_SID 0x4
9703
9704
9705
9706
9707
9708
9709#define B_FE_FD_REG_COMM_EXEC__A 0xC40000
9710#define B_FE_FD_REG_COMM_EXEC__W 3
9711#define B_FE_FD_REG_COMM_EXEC__M 0x7
9712#define B_FE_FD_REG_COMM_EXEC_CTL__B 0
9713#define B_FE_FD_REG_COMM_EXEC_CTL__W 3
9714#define B_FE_FD_REG_COMM_EXEC_CTL__M 0x7
9715#define B_FE_FD_REG_COMM_EXEC_CTL_STOP 0x0
9716#define B_FE_FD_REG_COMM_EXEC_CTL_ACTIVE 0x1
9717#define B_FE_FD_REG_COMM_EXEC_CTL_HOLD 0x2
9718#define B_FE_FD_REG_COMM_EXEC_CTL_STEP 0x3
9719
9720
9721#define B_FE_FD_REG_COMM_MB__A 0xC40002
9722#define B_FE_FD_REG_COMM_MB__W 3
9723#define B_FE_FD_REG_COMM_MB__M 0x7
9724#define B_FE_FD_REG_COMM_MB_CTR__B 0
9725#define B_FE_FD_REG_COMM_MB_CTR__W 1
9726#define B_FE_FD_REG_COMM_MB_CTR__M 0x1
9727#define B_FE_FD_REG_COMM_MB_CTR_OFF 0x0
9728#define B_FE_FD_REG_COMM_MB_CTR_ON 0x1
9729#define B_FE_FD_REG_COMM_MB_OBS__B 1
9730#define B_FE_FD_REG_COMM_MB_OBS__W 1
9731#define B_FE_FD_REG_COMM_MB_OBS__M 0x2
9732#define B_FE_FD_REG_COMM_MB_OBS_OFF 0x0
9733#define B_FE_FD_REG_COMM_MB_OBS_ON 0x2
9734
9735#define B_FE_FD_REG_COMM_SERVICE0__A 0xC40003
9736#define B_FE_FD_REG_COMM_SERVICE0__W 10
9737#define B_FE_FD_REG_COMM_SERVICE0__M 0x3FF
9738#define B_FE_FD_REG_COMM_SERVICE1__A 0xC40004
9739#define B_FE_FD_REG_COMM_SERVICE1__W 11
9740#define B_FE_FD_REG_COMM_SERVICE1__M 0x7FF
9741
9742#define B_FE_FD_REG_COMM_INT_STA__A 0xC40007
9743#define B_FE_FD_REG_COMM_INT_STA__W 1
9744#define B_FE_FD_REG_COMM_INT_STA__M 0x1
9745#define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__B 0
9746#define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__W 1
9747#define B_FE_FD_REG_COMM_INT_STA_NEW_MEAS__M 0x1
9748
9749
9750#define B_FE_FD_REG_COMM_INT_MSK__A 0xC40008
9751#define B_FE_FD_REG_COMM_INT_MSK__W 1
9752#define B_FE_FD_REG_COMM_INT_MSK__M 0x1
9753#define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__B 0
9754#define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__W 1
9755#define B_FE_FD_REG_COMM_INT_MSK_NEW_MEAS__M 0x1
9756
9757
9758#define B_FE_FD_REG_SCL__A 0xC40010
9759#define B_FE_FD_REG_SCL__W 6
9760#define B_FE_FD_REG_SCL__M 0x3F
9761
9762#define B_FE_FD_REG_MAX_LEV__A 0xC40011
9763#define B_FE_FD_REG_MAX_LEV__W 3
9764#define B_FE_FD_REG_MAX_LEV__M 0x7
9765
9766#define B_FE_FD_REG_NR__A 0xC40012
9767#define B_FE_FD_REG_NR__W 5
9768#define B_FE_FD_REG_NR__M 0x1F
9769
9770#define B_FE_FD_REG_MEAS_SEL__A 0xC40013
9771#define B_FE_FD_REG_MEAS_SEL__W 1
9772#define B_FE_FD_REG_MEAS_SEL__M 0x1
9773
9774#define B_FE_FD_REG_MEAS_VAL__A 0xC40014
9775#define B_FE_FD_REG_MEAS_VAL__W 1
9776#define B_FE_FD_REG_MEAS_VAL__M 0x1
9777
9778#define B_FE_FD_REG_MAX__A 0xC40015
9779#define B_FE_FD_REG_MAX__W 16
9780#define B_FE_FD_REG_MAX__M 0xFFFF
9781
9782
9783
9784
9785
9786#define B_FE_IF_SID 0x5
9787
9788
9789
9790
9791
9792
9793#define B_FE_IF_REG_COMM_EXEC__A 0xC50000
9794#define B_FE_IF_REG_COMM_EXEC__W 3
9795#define B_FE_IF_REG_COMM_EXEC__M 0x7
9796#define B_FE_IF_REG_COMM_EXEC_CTL__B 0
9797#define B_FE_IF_REG_COMM_EXEC_CTL__W 3
9798#define B_FE_IF_REG_COMM_EXEC_CTL__M 0x7
9799#define B_FE_IF_REG_COMM_EXEC_CTL_STOP 0x0
9800#define B_FE_IF_REG_COMM_EXEC_CTL_ACTIVE 0x1
9801#define B_FE_IF_REG_COMM_EXEC_CTL_HOLD 0x2
9802#define B_FE_IF_REG_COMM_EXEC_CTL_STEP 0x3
9803
9804
9805#define B_FE_IF_REG_COMM_MB__A 0xC50002
9806#define B_FE_IF_REG_COMM_MB__W 3
9807#define B_FE_IF_REG_COMM_MB__M 0x7
9808#define B_FE_IF_REG_COMM_MB_CTR__B 0
9809#define B_FE_IF_REG_COMM_MB_CTR__W 1
9810#define B_FE_IF_REG_COMM_MB_CTR__M 0x1
9811#define B_FE_IF_REG_COMM_MB_CTR_OFF 0x0
9812#define B_FE_IF_REG_COMM_MB_CTR_ON 0x1
9813#define B_FE_IF_REG_COMM_MB_OBS__B 1
9814#define B_FE_IF_REG_COMM_MB_OBS__W 1
9815#define B_FE_IF_REG_COMM_MB_OBS__M 0x2
9816#define B_FE_IF_REG_COMM_MB_OBS_OFF 0x0
9817#define B_FE_IF_REG_COMM_MB_OBS_ON 0x2
9818
9819
9820#define B_FE_IF_REG_INCR0__A 0xC50010
9821#define B_FE_IF_REG_INCR0__W 16
9822#define B_FE_IF_REG_INCR0__M 0xFFFF
9823#define B_FE_IF_REG_INCR0_INIT 0x0
9824
9825
9826#define B_FE_IF_REG_INCR1__A 0xC50011
9827#define B_FE_IF_REG_INCR1__W 8
9828#define B_FE_IF_REG_INCR1__M 0xFF
9829#define B_FE_IF_REG_INCR1_INIT 0x28
9830
9831
9832
9833
9834
9835#define B_FE_CF_SID 0x6
9836
9837
9838
9839
9840
9841
9842#define B_FE_CF_REG_COMM_EXEC__A 0xC60000
9843#define B_FE_CF_REG_COMM_EXEC__W 3
9844#define B_FE_CF_REG_COMM_EXEC__M 0x7
9845#define B_FE_CF_REG_COMM_EXEC_CTL__B 0
9846#define B_FE_CF_REG_COMM_EXEC_CTL__W 3
9847#define B_FE_CF_REG_COMM_EXEC_CTL__M 0x7
9848#define B_FE_CF_REG_COMM_EXEC_CTL_STOP 0x0
9849#define B_FE_CF_REG_COMM_EXEC_CTL_ACTIVE 0x1
9850#define B_FE_CF_REG_COMM_EXEC_CTL_HOLD 0x2
9851#define B_FE_CF_REG_COMM_EXEC_CTL_STEP 0x3
9852
9853
9854#define B_FE_CF_REG_COMM_MB__A 0xC60002
9855#define B_FE_CF_REG_COMM_MB__W 3
9856#define B_FE_CF_REG_COMM_MB__M 0x7
9857#define B_FE_CF_REG_COMM_MB_CTR__B 0
9858#define B_FE_CF_REG_COMM_MB_CTR__W 1
9859#define B_FE_CF_REG_COMM_MB_CTR__M 0x1
9860#define B_FE_CF_REG_COMM_MB_CTR_OFF 0x0
9861#define B_FE_CF_REG_COMM_MB_CTR_ON 0x1
9862#define B_FE_CF_REG_COMM_MB_OBS__B 1
9863#define B_FE_CF_REG_COMM_MB_OBS__W 1
9864#define B_FE_CF_REG_COMM_MB_OBS__M 0x2
9865#define B_FE_CF_REG_COMM_MB_OBS_OFF 0x0
9866#define B_FE_CF_REG_COMM_MB_OBS_ON 0x2
9867
9868#define B_FE_CF_REG_COMM_SERVICE0__A 0xC60003
9869#define B_FE_CF_REG_COMM_SERVICE0__W 10
9870#define B_FE_CF_REG_COMM_SERVICE0__M 0x3FF
9871#define B_FE_CF_REG_COMM_SERVICE1__A 0xC60004
9872#define B_FE_CF_REG_COMM_SERVICE1__W 11
9873#define B_FE_CF_REG_COMM_SERVICE1__M 0x7FF
9874
9875#define B_FE_CF_REG_COMM_INT_STA__A 0xC60007
9876#define B_FE_CF_REG_COMM_INT_STA__W 2
9877#define B_FE_CF_REG_COMM_INT_STA__M 0x3
9878#define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__B 0
9879#define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__W 1
9880#define B_FE_CF_REG_COMM_INT_STA_NEW_MEAS__M 0x1
9881
9882
9883#define B_FE_CF_REG_COMM_INT_MSK__A 0xC60008
9884#define B_FE_CF_REG_COMM_INT_MSK__W 2
9885#define B_FE_CF_REG_COMM_INT_MSK__M 0x3
9886#define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__B 0
9887#define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__W 1
9888#define B_FE_CF_REG_COMM_INT_MSK_NEW_MEAS__M 0x1
9889
9890
9891#define B_FE_CF_REG_SCL__A 0xC60010
9892#define B_FE_CF_REG_SCL__W 9
9893#define B_FE_CF_REG_SCL__M 0x1FF
9894
9895#define B_FE_CF_REG_MAX_LEV__A 0xC60011
9896#define B_FE_CF_REG_MAX_LEV__W 3
9897#define B_FE_CF_REG_MAX_LEV__M 0x7
9898
9899#define B_FE_CF_REG_NR__A 0xC60012
9900#define B_FE_CF_REG_NR__W 5
9901#define B_FE_CF_REG_NR__M 0x1F
9902
9903#define B_FE_CF_REG_IMP_VAL__A 0xC60013
9904#define B_FE_CF_REG_IMP_VAL__W 1
9905#define B_FE_CF_REG_IMP_VAL__M 0x1
9906
9907#define B_FE_CF_REG_MEAS_VAL__A 0xC60014
9908#define B_FE_CF_REG_MEAS_VAL__W 1
9909#define B_FE_CF_REG_MEAS_VAL__M 0x1
9910
9911#define B_FE_CF_REG_MAX__A 0xC60015
9912#define B_FE_CF_REG_MAX__W 16
9913#define B_FE_CF_REG_MAX__M 0xFFFF
9914
9915
9916
9917
9918
9919#define B_FE_CU_SID 0x7
9920
9921
9922
9923
9924
9925
9926#define B_FE_CU_REG_COMM_EXEC__A 0xC70000
9927#define B_FE_CU_REG_COMM_EXEC__W 3
9928#define B_FE_CU_REG_COMM_EXEC__M 0x7
9929#define B_FE_CU_REG_COMM_EXEC_CTL__B 0
9930#define B_FE_CU_REG_COMM_EXEC_CTL__W 3
9931#define B_FE_CU_REG_COMM_EXEC_CTL__M 0x7
9932#define B_FE_CU_REG_COMM_EXEC_CTL_STOP 0x0
9933#define B_FE_CU_REG_COMM_EXEC_CTL_ACTIVE 0x1
9934#define B_FE_CU_REG_COMM_EXEC_CTL_HOLD 0x2
9935#define B_FE_CU_REG_COMM_EXEC_CTL_STEP 0x3
9936
9937#define B_FE_CU_REG_COMM_STATE__A 0xC70001
9938#define B_FE_CU_REG_COMM_STATE__W 4
9939#define B_FE_CU_REG_COMM_STATE__M 0xF
9940
9941#define B_FE_CU_REG_COMM_MB__A 0xC70002
9942#define B_FE_CU_REG_COMM_MB__W 3
9943#define B_FE_CU_REG_COMM_MB__M 0x7
9944#define B_FE_CU_REG_COMM_MB_CTR__B 0
9945#define B_FE_CU_REG_COMM_MB_CTR__W 1
9946#define B_FE_CU_REG_COMM_MB_CTR__M 0x1
9947#define B_FE_CU_REG_COMM_MB_CTR_OFF 0x0
9948#define B_FE_CU_REG_COMM_MB_CTR_ON 0x1
9949#define B_FE_CU_REG_COMM_MB_OBS__B 1
9950#define B_FE_CU_REG_COMM_MB_OBS__W 1
9951#define B_FE_CU_REG_COMM_MB_OBS__M 0x2
9952#define B_FE_CU_REG_COMM_MB_OBS_OFF 0x0
9953#define B_FE_CU_REG_COMM_MB_OBS_ON 0x2
9954#define B_FE_CU_REG_COMM_MB_MUX__B 2
9955#define B_FE_CU_REG_COMM_MB_MUX__W 1
9956#define B_FE_CU_REG_COMM_MB_MUX__M 0x4
9957#define B_FE_CU_REG_COMM_MB_MUX_REAL 0x0
9958#define B_FE_CU_REG_COMM_MB_MUX_IMAG 0x4
9959
9960
9961#define B_FE_CU_REG_COMM_SERVICE0__A 0xC70003
9962#define B_FE_CU_REG_COMM_SERVICE0__W 10
9963#define B_FE_CU_REG_COMM_SERVICE0__M 0x3FF
9964
9965#define B_FE_CU_REG_COMM_SERVICE1__A 0xC70004
9966#define B_FE_CU_REG_COMM_SERVICE1__W 11
9967#define B_FE_CU_REG_COMM_SERVICE1__M 0x7FF
9968
9969#define B_FE_CU_REG_COMM_ACT__A 0xC70005
9970#define B_FE_CU_REG_COMM_ACT__W 2
9971#define B_FE_CU_REG_COMM_ACT__M 0x3
9972
9973#define B_FE_CU_REG_COMM_CNT__A 0xC70006
9974#define B_FE_CU_REG_COMM_CNT__W 16
9975#define B_FE_CU_REG_COMM_CNT__M 0xFFFF
9976
9977#define B_FE_CU_REG_COMM_INT_STA__A 0xC70007
9978#define B_FE_CU_REG_COMM_INT_STA__W 4
9979#define B_FE_CU_REG_COMM_INT_STA__M 0xF
9980#define B_FE_CU_REG_COMM_INT_STA_FE_START__B 0
9981#define B_FE_CU_REG_COMM_INT_STA_FE_START__W 1
9982#define B_FE_CU_REG_COMM_INT_STA_FE_START__M 0x1
9983#define B_FE_CU_REG_COMM_INT_STA_FT_START__B 1
9984#define B_FE_CU_REG_COMM_INT_STA_FT_START__W 1
9985#define B_FE_CU_REG_COMM_INT_STA_FT_START__M 0x2
9986#define B_FE_CU_REG_COMM_INT_STA_SB_START__B 2
9987#define B_FE_CU_REG_COMM_INT_STA_SB_START__W 1
9988#define B_FE_CU_REG_COMM_INT_STA_SB_START__M 0x4
9989#define B_FE_CU_REG_COMM_INT_STA_NF_READY__B 3
9990#define B_FE_CU_REG_COMM_INT_STA_NF_READY__W 1
9991#define B_FE_CU_REG_COMM_INT_STA_NF_READY__M 0x8
9992
9993
9994#define B_FE_CU_REG_COMM_INT_MSK__A 0xC70008
9995#define B_FE_CU_REG_COMM_INT_MSK__W 4
9996#define B_FE_CU_REG_COMM_INT_MSK__M 0xF
9997#define B_FE_CU_REG_COMM_INT_MSK_FE_START__B 0
9998#define B_FE_CU_REG_COMM_INT_MSK_FE_START__W 1
9999#define B_FE_CU_REG_COMM_INT_MSK_FE_START__M 0x1
10000#define B_FE_CU_REG_COMM_INT_MSK_FT_START__B 1
10001#define B_FE_CU_REG_COMM_INT_MSK_FT_START__W 1
10002#define B_FE_CU_REG_COMM_INT_MSK_FT_START__M 0x2
10003#define B_FE_CU_REG_COMM_INT_MSK_SB_START__B 2
10004#define B_FE_CU_REG_COMM_INT_MSK_SB_START__W 1
10005#define B_FE_CU_REG_COMM_INT_MSK_SB_START__M 0x4
10006#define B_FE_CU_REG_COMM_INT_MSK_NF_READY__B 3
10007#define B_FE_CU_REG_COMM_INT_MSK_NF_READY__W 1
10008#define B_FE_CU_REG_COMM_INT_MSK_NF_READY__M 0x8
10009
10010
10011#define B_FE_CU_REG_MODE__A 0xC70010
10012#define B_FE_CU_REG_MODE__W 5
10013#define B_FE_CU_REG_MODE__M 0x1F
10014#define B_FE_CU_REG_MODE_INIT 0x0
10015
10016#define B_FE_CU_REG_MODE_FFT__B 0
10017#define B_FE_CU_REG_MODE_FFT__W 1
10018#define B_FE_CU_REG_MODE_FFT__M 0x1
10019#define B_FE_CU_REG_MODE_FFT_M8K 0x0
10020#define B_FE_CU_REG_MODE_FFT_M2K 0x1
10021
10022#define B_FE_CU_REG_MODE_COR__B 1
10023#define B_FE_CU_REG_MODE_COR__W 1
10024#define B_FE_CU_REG_MODE_COR__M 0x2
10025#define B_FE_CU_REG_MODE_COR_OFF 0x0
10026#define B_FE_CU_REG_MODE_COR_ON 0x2
10027
10028#define B_FE_CU_REG_MODE_IFD__B 2
10029#define B_FE_CU_REG_MODE_IFD__W 1
10030#define B_FE_CU_REG_MODE_IFD__M 0x4
10031#define B_FE_CU_REG_MODE_IFD_ENABLE 0x0
10032#define B_FE_CU_REG_MODE_IFD_DISABLE 0x4
10033
10034#define B_FE_CU_REG_MODE_SEL__B 3
10035#define B_FE_CU_REG_MODE_SEL__W 1
10036#define B_FE_CU_REG_MODE_SEL__M 0x8
10037#define B_FE_CU_REG_MODE_SEL_COR 0x0
10038#define B_FE_CU_REG_MODE_SEL_COR_NFC 0x8
10039
10040#define B_FE_CU_REG_MODE_FES__B 4
10041#define B_FE_CU_REG_MODE_FES__W 1
10042#define B_FE_CU_REG_MODE_FES__M 0x10
10043#define B_FE_CU_REG_MODE_FES_SEL_RST 0x0
10044#define B_FE_CU_REG_MODE_FES_SEL_UPD 0x10
10045
10046
10047#define B_FE_CU_REG_FRM_CNT_RST__A 0xC70011
10048#define B_FE_CU_REG_FRM_CNT_RST__W 15
10049#define B_FE_CU_REG_FRM_CNT_RST__M 0x7FFF
10050#define B_FE_CU_REG_FRM_CNT_RST_INIT 0x20FF
10051
10052
10053#define B_FE_CU_REG_FRM_CNT_STR__A 0xC70012
10054#define B_FE_CU_REG_FRM_CNT_STR__W 15
10055#define B_FE_CU_REG_FRM_CNT_STR__M 0x7FFF
10056#define B_FE_CU_REG_FRM_CNT_STR_INIT 0x1E
10057
10058
10059#define B_FE_CU_REG_FRM_SMP_CNT__A 0xC70013
10060#define B_FE_CU_REG_FRM_SMP_CNT__W 15
10061#define B_FE_CU_REG_FRM_SMP_CNT__M 0x7FFF
10062
10063#define B_FE_CU_REG_FRM_SMB_CNT__A 0xC70014
10064#define B_FE_CU_REG_FRM_SMB_CNT__W 16
10065#define B_FE_CU_REG_FRM_SMB_CNT__M 0xFFFF
10066
10067#define B_FE_CU_REG_CMP_MAX_DAT__A 0xC70015
10068#define B_FE_CU_REG_CMP_MAX_DAT__W 12
10069#define B_FE_CU_REG_CMP_MAX_DAT__M 0xFFF
10070
10071#define B_FE_CU_REG_CMP_MAX_ADR__A 0xC70016
10072#define B_FE_CU_REG_CMP_MAX_ADR__W 10
10073#define B_FE_CU_REG_CMP_MAX_ADR__M 0x3FF
10074
10075#define B_FE_CU_REG_BUF_NFC_DEL__A 0xC7001F
10076#define B_FE_CU_REG_BUF_NFC_DEL__W 14
10077#define B_FE_CU_REG_BUF_NFC_DEL__M 0x3FFF
10078#define B_FE_CU_REG_BUF_NFC_DEL_INIT 0x0
10079
10080
10081#define B_FE_CU_REG_CTR_NFC_ICR__A 0xC70020
10082#define B_FE_CU_REG_CTR_NFC_ICR__W 5
10083#define B_FE_CU_REG_CTR_NFC_ICR__M 0x1F
10084#define B_FE_CU_REG_CTR_NFC_ICR_INIT 0x0
10085
10086
10087#define B_FE_CU_REG_CTR_NFC_OCR__A 0xC70021
10088#define B_FE_CU_REG_CTR_NFC_OCR__W 15
10089#define B_FE_CU_REG_CTR_NFC_OCR__M 0x7FFF
10090#define B_FE_CU_REG_CTR_NFC_OCR_INIT 0x61A8
10091
10092
10093#define B_FE_CU_REG_CTR_NFC_CNT__A 0xC70022
10094#define B_FE_CU_REG_CTR_NFC_CNT__W 15
10095#define B_FE_CU_REG_CTR_NFC_CNT__M 0x7FFF
10096
10097#define B_FE_CU_REG_CTR_NFC_STS__A 0xC70023
10098#define B_FE_CU_REG_CTR_NFC_STS__W 3
10099#define B_FE_CU_REG_CTR_NFC_STS__M 0x7
10100#define B_FE_CU_REG_CTR_NFC_STS_RUN 0x0
10101#define B_FE_CU_REG_CTR_NFC_STS_ACC_MAX_IMA 0x1
10102#define B_FE_CU_REG_CTR_NFC_STS_ACC_MAX_REA 0x2
10103#define B_FE_CU_REG_CTR_NFC_STS_CNT_MAX 0x4
10104
10105
10106#define B_FE_CU_REG_DIV_NFC_REA__A 0xC70024
10107#define B_FE_CU_REG_DIV_NFC_REA__W 14
10108#define B_FE_CU_REG_DIV_NFC_REA__M 0x3FFF
10109
10110#define B_FE_CU_REG_DIV_NFC_IMA__A 0xC70025
10111#define B_FE_CU_REG_DIV_NFC_IMA__W 14
10112#define B_FE_CU_REG_DIV_NFC_IMA__M 0x3FFF
10113
10114#define B_FE_CU_REG_FRM_CNT_UPD__A 0xC70026
10115#define B_FE_CU_REG_FRM_CNT_UPD__W 15
10116#define B_FE_CU_REG_FRM_CNT_UPD__M 0x7FFF
10117#define B_FE_CU_REG_FRM_CNT_UPD_INIT 0x20FF
10118
10119
10120#define B_FE_CU_REG_DIV_NFC_CLP__A 0xC70027
10121#define B_FE_CU_REG_DIV_NFC_CLP__W 2
10122#define B_FE_CU_REG_DIV_NFC_CLP__M 0x3
10123#define B_FE_CU_REG_DIV_NFC_CLP_INIT 0x1
10124#define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S11 0x0
10125#define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S12 0x1
10126#define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S13 0x2
10127#define B_FE_CU_REG_DIV_NFC_CLP_CLIP_S14 0x3
10128
10129
10130
10131#define B_FE_CU_BUF_RAM__A 0xC80000
10132
10133
10134
10135#define B_FE_CU_CMP_RAM__A 0xC90000
10136
10137
10138
10139
10140
10141#define B_FT_SID 0x8
10142
10143
10144
10145
10146
10147#define B_FT_COMM_EXEC__A 0x1000000
10148#define B_FT_COMM_EXEC__W 3
10149#define B_FT_COMM_EXEC__M 0x7
10150#define B_FT_COMM_EXEC_CTL__B 0
10151#define B_FT_COMM_EXEC_CTL__W 3
10152#define B_FT_COMM_EXEC_CTL__M 0x7
10153#define B_FT_COMM_EXEC_CTL_STOP 0x0
10154#define B_FT_COMM_EXEC_CTL_ACTIVE 0x1
10155#define B_FT_COMM_EXEC_CTL_HOLD 0x2
10156#define B_FT_COMM_EXEC_CTL_STEP 0x3
10157#define B_FT_COMM_EXEC_CTL_BYPASS_STOP 0x4
10158#define B_FT_COMM_EXEC_CTL_BYPASS_HOLD 0x6
10159
10160#define B_FT_COMM_STATE__A 0x1000001
10161#define B_FT_COMM_STATE__W 16
10162#define B_FT_COMM_STATE__M 0xFFFF
10163#define B_FT_COMM_MB__A 0x1000002
10164#define B_FT_COMM_MB__W 16
10165#define B_FT_COMM_MB__M 0xFFFF
10166#define B_FT_COMM_SERVICE0__A 0x1000003
10167#define B_FT_COMM_SERVICE0__W 16
10168#define B_FT_COMM_SERVICE0__M 0xFFFF
10169#define B_FT_COMM_SERVICE1__A 0x1000004
10170#define B_FT_COMM_SERVICE1__W 16
10171#define B_FT_COMM_SERVICE1__M 0xFFFF
10172#define B_FT_COMM_INT_STA__A 0x1000007
10173#define B_FT_COMM_INT_STA__W 16
10174#define B_FT_COMM_INT_STA__M 0xFFFF
10175#define B_FT_COMM_INT_MSK__A 0x1000008
10176#define B_FT_COMM_INT_MSK__W 16
10177#define B_FT_COMM_INT_MSK__M 0xFFFF
10178
10179
10180
10181
10182
10183
10184#define B_FT_REG_COMM_EXEC__A 0x1010000
10185#define B_FT_REG_COMM_EXEC__W 3
10186#define B_FT_REG_COMM_EXEC__M 0x7
10187#define B_FT_REG_COMM_EXEC_CTL__B 0
10188#define B_FT_REG_COMM_EXEC_CTL__W 3
10189#define B_FT_REG_COMM_EXEC_CTL__M 0x7
10190#define B_FT_REG_COMM_EXEC_CTL_STOP 0x0
10191#define B_FT_REG_COMM_EXEC_CTL_ACTIVE 0x1
10192#define B_FT_REG_COMM_EXEC_CTL_HOLD 0x2
10193#define B_FT_REG_COMM_EXEC_CTL_STEP 0x3
10194
10195
10196#define B_FT_REG_COMM_MB__A 0x1010002
10197#define B_FT_REG_COMM_MB__W 3
10198#define B_FT_REG_COMM_MB__M 0x7
10199#define B_FT_REG_COMM_MB_CTR__B 0
10200#define B_FT_REG_COMM_MB_CTR__W 1
10201#define B_FT_REG_COMM_MB_CTR__M 0x1
10202#define B_FT_REG_COMM_MB_CTR_OFF 0x0
10203#define B_FT_REG_COMM_MB_CTR_ON 0x1
10204#define B_FT_REG_COMM_MB_OBS__B 1
10205#define B_FT_REG_COMM_MB_OBS__W 1
10206#define B_FT_REG_COMM_MB_OBS__M 0x2
10207#define B_FT_REG_COMM_MB_OBS_OFF 0x0
10208#define B_FT_REG_COMM_MB_OBS_ON 0x2
10209
10210
10211#define B_FT_REG_MODE_2K__A 0x1010010
10212#define B_FT_REG_MODE_2K__W 1
10213#define B_FT_REG_MODE_2K__M 0x1
10214#define B_FT_REG_MODE_2K_MODE_8K 0x0
10215#define B_FT_REG_MODE_2K_MODE_2K 0x1
10216#define B_FT_REG_MODE_2K_INIT 0x0
10217
10218
10219#define B_FT_REG_NORM_OFF__A 0x1010016
10220#define B_FT_REG_NORM_OFF__W 4
10221#define B_FT_REG_NORM_OFF__M 0xF
10222#define B_FT_REG_NORM_OFF_INIT 0x2
10223
10224
10225
10226#define B_FT_ST1_RAM__A 0x1020000
10227
10228
10229
10230#define B_FT_ST2_RAM__A 0x1030000
10231
10232
10233
10234#define B_FT_ST3_RAM__A 0x1040000
10235
10236
10237
10238#define B_FT_ST5_RAM__A 0x1050000
10239
10240
10241
10242#define B_FT_ST6_RAM__A 0x1060000
10243
10244
10245
10246#define B_FT_ST8_RAM__A 0x1070000
10247
10248
10249
10250#define B_FT_ST9_RAM__A 0x1080000
10251
10252
10253
10254
10255
10256#define B_CP_SID 0x9
10257
10258
10259
10260
10261
10262#define B_CP_COMM_EXEC__A 0x1400000
10263#define B_CP_COMM_EXEC__W 3
10264#define B_CP_COMM_EXEC__M 0x7
10265#define B_CP_COMM_EXEC_CTL__B 0
10266#define B_CP_COMM_EXEC_CTL__W 3
10267#define B_CP_COMM_EXEC_CTL__M 0x7
10268#define B_CP_COMM_EXEC_CTL_STOP 0x0
10269#define B_CP_COMM_EXEC_CTL_ACTIVE 0x1
10270#define B_CP_COMM_EXEC_CTL_HOLD 0x2
10271#define B_CP_COMM_EXEC_CTL_STEP 0x3
10272#define B_CP_COMM_EXEC_CTL_BYPASS_STOP 0x4
10273#define B_CP_COMM_EXEC_CTL_BYPASS_HOLD 0x6
10274
10275#define B_CP_COMM_STATE__A 0x1400001
10276#define B_CP_COMM_STATE__W 16
10277#define B_CP_COMM_STATE__M 0xFFFF
10278#define B_CP_COMM_MB__A 0x1400002
10279#define B_CP_COMM_MB__W 16
10280#define B_CP_COMM_MB__M 0xFFFF
10281#define B_CP_COMM_SERVICE0__A 0x1400003
10282#define B_CP_COMM_SERVICE0__W 16
10283#define B_CP_COMM_SERVICE0__M 0xFFFF
10284#define B_CP_COMM_SERVICE1__A 0x1400004
10285#define B_CP_COMM_SERVICE1__W 16
10286#define B_CP_COMM_SERVICE1__M 0xFFFF
10287#define B_CP_COMM_INT_STA__A 0x1400007
10288#define B_CP_COMM_INT_STA__W 16
10289#define B_CP_COMM_INT_STA__M 0xFFFF
10290#define B_CP_COMM_INT_MSK__A 0x1400008
10291#define B_CP_COMM_INT_MSK__W 16
10292#define B_CP_COMM_INT_MSK__M 0xFFFF
10293
10294
10295
10296
10297
10298
10299#define B_CP_REG_COMM_EXEC__A 0x1410000
10300#define B_CP_REG_COMM_EXEC__W 3
10301#define B_CP_REG_COMM_EXEC__M 0x7
10302#define B_CP_REG_COMM_EXEC_CTL__B 0
10303#define B_CP_REG_COMM_EXEC_CTL__W 3
10304#define B_CP_REG_COMM_EXEC_CTL__M 0x7
10305#define B_CP_REG_COMM_EXEC_CTL_STOP 0x0
10306#define B_CP_REG_COMM_EXEC_CTL_ACTIVE 0x1
10307#define B_CP_REG_COMM_EXEC_CTL_HOLD 0x2
10308#define B_CP_REG_COMM_EXEC_CTL_STEP 0x3
10309
10310
10311#define B_CP_REG_COMM_MB__A 0x1410002
10312#define B_CP_REG_COMM_MB__W 3
10313#define B_CP_REG_COMM_MB__M 0x7
10314#define B_CP_REG_COMM_MB_CTR__B 0
10315#define B_CP_REG_COMM_MB_CTR__W 1
10316#define B_CP_REG_COMM_MB_CTR__M 0x1
10317#define B_CP_REG_COMM_MB_CTR_OFF 0x0
10318#define B_CP_REG_COMM_MB_CTR_ON 0x1
10319#define B_CP_REG_COMM_MB_OBS__B 1
10320#define B_CP_REG_COMM_MB_OBS__W 1
10321#define B_CP_REG_COMM_MB_OBS__M 0x2
10322#define B_CP_REG_COMM_MB_OBS_OFF 0x0
10323#define B_CP_REG_COMM_MB_OBS_ON 0x2
10324
10325#define B_CP_REG_COMM_SERVICE0__A 0x1410003
10326#define B_CP_REG_COMM_SERVICE0__W 10
10327#define B_CP_REG_COMM_SERVICE0__M 0x3FF
10328#define B_CP_REG_COMM_SERVICE0_CP__B 9
10329#define B_CP_REG_COMM_SERVICE0_CP__W 1
10330#define B_CP_REG_COMM_SERVICE0_CP__M 0x200
10331
10332#define B_CP_REG_COMM_SERVICE1__A 0x1410004
10333#define B_CP_REG_COMM_SERVICE1__W 11
10334#define B_CP_REG_COMM_SERVICE1__M 0x7FF
10335
10336#define B_CP_REG_COMM_INT_STA__A 0x1410007
10337#define B_CP_REG_COMM_INT_STA__W 2
10338#define B_CP_REG_COMM_INT_STA__M 0x3
10339#define B_CP_REG_COMM_INT_STA_NEW_MEAS__B 0
10340#define B_CP_REG_COMM_INT_STA_NEW_MEAS__W 1
10341#define B_CP_REG_COMM_INT_STA_NEW_MEAS__M 0x1
10342
10343
10344#define B_CP_REG_COMM_INT_MSK__A 0x1410008
10345#define B_CP_REG_COMM_INT_MSK__W 2
10346#define B_CP_REG_COMM_INT_MSK__M 0x3
10347#define B_CP_REG_COMM_INT_MSK_NEW_MEAS__B 0
10348#define B_CP_REG_COMM_INT_MSK_NEW_MEAS__W 1
10349#define B_CP_REG_COMM_INT_MSK_NEW_MEAS__M 0x1
10350
10351
10352#define B_CP_REG_MODE_2K__A 0x1410010
10353#define B_CP_REG_MODE_2K__W 1
10354#define B_CP_REG_MODE_2K__M 0x1
10355#define B_CP_REG_MODE_2K_INIT 0x0
10356
10357
10358#define B_CP_REG_INTERVAL__A 0x1410011
10359#define B_CP_REG_INTERVAL__W 4
10360#define B_CP_REG_INTERVAL__M 0xF
10361#define B_CP_REG_INTERVAL_INIT 0x5
10362
10363
10364#define B_CP_REG_DETECT_ENA__A 0x1410012
10365#define B_CP_REG_DETECT_ENA__W 2
10366#define B_CP_REG_DETECT_ENA__M 0x3
10367
10368#define B_CP_REG_DETECT_ENA_SCATTERED__B 0
10369#define B_CP_REG_DETECT_ENA_SCATTERED__W 1
10370#define B_CP_REG_DETECT_ENA_SCATTERED__M 0x1
10371
10372#define B_CP_REG_DETECT_ENA_CONTINUOUS__B 1
10373#define B_CP_REG_DETECT_ENA_CONTINUOUS__W 1
10374#define B_CP_REG_DETECT_ENA_CONTINUOUS__M 0x2
10375#define B_CP_REG_DETECT_ENA_INIT 0x0
10376
10377
10378#define B_CP_REG_BR_SMB_NR__A 0x1410021
10379#define B_CP_REG_BR_SMB_NR__W 4
10380#define B_CP_REG_BR_SMB_NR__M 0xF
10381
10382#define B_CP_REG_BR_SMB_NR_SMB__B 0
10383#define B_CP_REG_BR_SMB_NR_SMB__W 2
10384#define B_CP_REG_BR_SMB_NR_SMB__M 0x3
10385
10386#define B_CP_REG_BR_SMB_NR_VAL__B 2
10387#define B_CP_REG_BR_SMB_NR_VAL__W 1
10388#define B_CP_REG_BR_SMB_NR_VAL__M 0x4
10389
10390#define B_CP_REG_BR_SMB_NR_OFFSET__B 3
10391#define B_CP_REG_BR_SMB_NR_OFFSET__W 1
10392#define B_CP_REG_BR_SMB_NR_OFFSET__M 0x8
10393#define B_CP_REG_BR_SMB_NR_INIT 0x0
10394
10395
10396#define B_CP_REG_BR_CP_SMB_NR__A 0x1410022
10397#define B_CP_REG_BR_CP_SMB_NR__W 2
10398#define B_CP_REG_BR_CP_SMB_NR__M 0x3
10399#define B_CP_REG_BR_CP_SMB_NR_INIT 0x0
10400
10401
10402#define B_CP_REG_BR_SPL_OFFSET__A 0x1410023
10403#define B_CP_REG_BR_SPL_OFFSET__W 3
10404#define B_CP_REG_BR_SPL_OFFSET__M 0x7
10405#define B_CP_REG_BR_SPL_OFFSET_INIT 0x0
10406
10407
10408#define B_CP_REG_BR_STR_DEL__A 0x1410024
10409#define B_CP_REG_BR_STR_DEL__W 10
10410#define B_CP_REG_BR_STR_DEL__M 0x3FF
10411#define B_CP_REG_BR_STR_DEL_INIT 0xA
10412
10413
10414#define B_CP_REG_BR_EXP_ADJ__A 0x1410025
10415#define B_CP_REG_BR_EXP_ADJ__W 5
10416#define B_CP_REG_BR_EXP_ADJ__M 0x1F
10417#define B_CP_REG_BR_EXP_ADJ_INIT 0x10
10418
10419
10420#define B_CP_REG_RT_ANG_INC0__A 0x1410030
10421#define B_CP_REG_RT_ANG_INC0__W 16
10422#define B_CP_REG_RT_ANG_INC0__M 0xFFFF
10423#define B_CP_REG_RT_ANG_INC0_INIT 0x0
10424
10425
10426#define B_CP_REG_RT_ANG_INC1__A 0x1410031
10427#define B_CP_REG_RT_ANG_INC1__W 8
10428#define B_CP_REG_RT_ANG_INC1__M 0xFF
10429#define B_CP_REG_RT_ANG_INC1_INIT 0x0
10430
10431
10432#define B_CP_REG_RT_SPD_EXP_MARG__A 0x1410032
10433#define B_CP_REG_RT_SPD_EXP_MARG__W 5
10434#define B_CP_REG_RT_SPD_EXP_MARG__M 0x1F
10435#define B_CP_REG_RT_SPD_EXP_MARG_INIT 0x5
10436
10437
10438#define B_CP_REG_RT_DETECT_TRH__A 0x1410033
10439#define B_CP_REG_RT_DETECT_TRH__W 2
10440#define B_CP_REG_RT_DETECT_TRH__M 0x3
10441#define B_CP_REG_RT_DETECT_TRH_INIT 0x3
10442
10443
10444#define B_CP_REG_RT_SPD_RELIABLE__A 0x1410034
10445#define B_CP_REG_RT_SPD_RELIABLE__W 3
10446#define B_CP_REG_RT_SPD_RELIABLE__M 0x7
10447#define B_CP_REG_RT_SPD_RELIABLE_INIT 0x0
10448
10449
10450#define B_CP_REG_RT_SPD_DIRECTION__A 0x1410035
10451#define B_CP_REG_RT_SPD_DIRECTION__W 1
10452#define B_CP_REG_RT_SPD_DIRECTION__M 0x1
10453#define B_CP_REG_RT_SPD_DIRECTION_INIT 0x0
10454
10455
10456#define B_CP_REG_RT_SPD_MOD__A 0x1410036
10457#define B_CP_REG_RT_SPD_MOD__W 2
10458#define B_CP_REG_RT_SPD_MOD__M 0x3
10459#define B_CP_REG_RT_SPD_MOD_INIT 0x0
10460
10461
10462#define B_CP_REG_RT_SPD_SMB__A 0x1410037
10463#define B_CP_REG_RT_SPD_SMB__W 2
10464#define B_CP_REG_RT_SPD_SMB__M 0x3
10465#define B_CP_REG_RT_SPD_SMB_INIT 0x0
10466
10467
10468#define B_CP_REG_RT_CPD_MODE__A 0x1410038
10469#define B_CP_REG_RT_CPD_MODE__W 3
10470#define B_CP_REG_RT_CPD_MODE__M 0x7
10471
10472#define B_CP_REG_RT_CPD_MODE_MOD3__B 0
10473#define B_CP_REG_RT_CPD_MODE_MOD3__W 2
10474#define B_CP_REG_RT_CPD_MODE_MOD3__M 0x3
10475
10476#define B_CP_REG_RT_CPD_MODE_ADD__B 2
10477#define B_CP_REG_RT_CPD_MODE_ADD__W 1
10478#define B_CP_REG_RT_CPD_MODE_ADD__M 0x4
10479#define B_CP_REG_RT_CPD_MODE_INIT 0x0
10480
10481
10482#define B_CP_REG_RT_CPD_RELIABLE__A 0x1410039
10483#define B_CP_REG_RT_CPD_RELIABLE__W 3
10484#define B_CP_REG_RT_CPD_RELIABLE__M 0x7
10485#define B_CP_REG_RT_CPD_RELIABLE_INIT 0x0
10486
10487
10488#define B_CP_REG_RT_CPD_BIN__A 0x141003A
10489#define B_CP_REG_RT_CPD_BIN__W 5
10490#define B_CP_REG_RT_CPD_BIN__M 0x1F
10491#define B_CP_REG_RT_CPD_BIN_INIT 0x0
10492
10493
10494#define B_CP_REG_RT_CPD_MAX__A 0x141003B
10495#define B_CP_REG_RT_CPD_MAX__W 4
10496#define B_CP_REG_RT_CPD_MAX__M 0xF
10497#define B_CP_REG_RT_CPD_MAX_INIT 0x0
10498
10499
10500#define B_CP_REG_RT_SUPR_VAL__A 0x141003C
10501#define B_CP_REG_RT_SUPR_VAL__W 2
10502#define B_CP_REG_RT_SUPR_VAL__M 0x3
10503
10504#define B_CP_REG_RT_SUPR_VAL_CE__B 0
10505#define B_CP_REG_RT_SUPR_VAL_CE__W 1
10506#define B_CP_REG_RT_SUPR_VAL_CE__M 0x1
10507
10508#define B_CP_REG_RT_SUPR_VAL_DL__B 1
10509#define B_CP_REG_RT_SUPR_VAL_DL__W 1
10510#define B_CP_REG_RT_SUPR_VAL_DL__M 0x2
10511#define B_CP_REG_RT_SUPR_VAL_INIT 0x0
10512
10513
10514#define B_CP_REG_RT_EXP_AVE__A 0x141003D
10515#define B_CP_REG_RT_EXP_AVE__W 5
10516#define B_CP_REG_RT_EXP_AVE__M 0x1F
10517#define B_CP_REG_RT_EXP_AVE_INIT 0x0
10518
10519
10520#define B_CP_REG_RT_CPD_EXP_MARG__A 0x141003E
10521#define B_CP_REG_RT_CPD_EXP_MARG__W 5
10522#define B_CP_REG_RT_CPD_EXP_MARG__M 0x1F
10523#define B_CP_REG_RT_CPD_EXP_MARG_INIT 0x3
10524
10525
10526#define B_CP_REG_AC_NEXP_OFFS__A 0x1410040
10527#define B_CP_REG_AC_NEXP_OFFS__W 8
10528#define B_CP_REG_AC_NEXP_OFFS__M 0xFF
10529#define B_CP_REG_AC_NEXP_OFFS_INIT 0x0
10530
10531
10532#define B_CP_REG_AC_AVER_POW__A 0x1410041
10533#define B_CP_REG_AC_AVER_POW__W 8
10534#define B_CP_REG_AC_AVER_POW__M 0xFF
10535#define B_CP_REG_AC_AVER_POW_INIT 0x5F
10536
10537
10538#define B_CP_REG_AC_MAX_POW__A 0x1410042
10539#define B_CP_REG_AC_MAX_POW__W 8
10540#define B_CP_REG_AC_MAX_POW__M 0xFF
10541#define B_CP_REG_AC_MAX_POW_INIT 0x7A
10542
10543
10544#define B_CP_REG_AC_WEIGHT_MAN__A 0x1410043
10545#define B_CP_REG_AC_WEIGHT_MAN__W 6
10546#define B_CP_REG_AC_WEIGHT_MAN__M 0x3F
10547#define B_CP_REG_AC_WEIGHT_MAN_INIT 0x31
10548
10549
10550#define B_CP_REG_AC_WEIGHT_EXP__A 0x1410044
10551#define B_CP_REG_AC_WEIGHT_EXP__W 5
10552#define B_CP_REG_AC_WEIGHT_EXP__M 0x1F
10553#define B_CP_REG_AC_WEIGHT_EXP_INIT 0x10
10554
10555
10556#define B_CP_REG_AC_GAIN_MAN__A 0x1410045
10557#define B_CP_REG_AC_GAIN_MAN__W 16
10558#define B_CP_REG_AC_GAIN_MAN__M 0xFFFF
10559#define B_CP_REG_AC_GAIN_MAN_INIT 0x0
10560
10561
10562#define B_CP_REG_AC_GAIN_EXP__A 0x1410046
10563#define B_CP_REG_AC_GAIN_EXP__W 5
10564#define B_CP_REG_AC_GAIN_EXP__M 0x1F
10565#define B_CP_REG_AC_GAIN_EXP_INIT 0x0
10566
10567
10568#define B_CP_REG_AC_AMP_MODE__A 0x1410047
10569#define B_CP_REG_AC_AMP_MODE__W 2
10570#define B_CP_REG_AC_AMP_MODE__M 0x3
10571#define B_CP_REG_AC_AMP_MODE_NEW 0x0
10572#define B_CP_REG_AC_AMP_MODE_OLD 0x1
10573#define B_CP_REG_AC_AMP_MODE_FIXED 0x2
10574#define B_CP_REG_AC_AMP_MODE_INIT 0x2
10575
10576
10577#define B_CP_REG_AC_AMP_FIX__A 0x1410048
10578#define B_CP_REG_AC_AMP_FIX__W 14
10579#define B_CP_REG_AC_AMP_FIX__M 0x3FFF
10580#define B_CP_REG_AC_AMP_FIX_INIT 0x1FF
10581
10582
10583#define B_CP_REG_AC_AMP_READ__A 0x1410049
10584#define B_CP_REG_AC_AMP_READ__W 14
10585#define B_CP_REG_AC_AMP_READ__M 0x3FFF
10586#define B_CP_REG_AC_AMP_READ_INIT 0x0
10587
10588
10589#define B_CP_REG_AC_ANG_MODE__A 0x141004A
10590#define B_CP_REG_AC_ANG_MODE__W 2
10591#define B_CP_REG_AC_ANG_MODE__M 0x3
10592#define B_CP_REG_AC_ANG_MODE_NEW 0x0
10593#define B_CP_REG_AC_ANG_MODE_OLD 0x1
10594#define B_CP_REG_AC_ANG_MODE_NO_INT 0x2
10595#define B_CP_REG_AC_ANG_MODE_OFFSET 0x3
10596#define B_CP_REG_AC_ANG_MODE_INIT 0x3
10597
10598
10599#define B_CP_REG_AC_ANG_OFFS__A 0x141004B
10600#define B_CP_REG_AC_ANG_OFFS__W 14
10601#define B_CP_REG_AC_ANG_OFFS__M 0x3FFF
10602#define B_CP_REG_AC_ANG_OFFS_INIT 0x0
10603
10604
10605#define B_CP_REG_AC_ANG_READ__A 0x141004C
10606#define B_CP_REG_AC_ANG_READ__W 16
10607#define B_CP_REG_AC_ANG_READ__M 0xFFFF
10608#define B_CP_REG_AC_ANG_READ_INIT 0x0
10609
10610
10611#define B_CP_REG_AC_ACCU_REAL0__A 0x1410060
10612#define B_CP_REG_AC_ACCU_REAL0__W 8
10613#define B_CP_REG_AC_ACCU_REAL0__M 0xFF
10614#define B_CP_REG_AC_ACCU_REAL0_INIT 0x0
10615
10616
10617#define B_CP_REG_AC_ACCU_IMAG0__A 0x1410061
10618#define B_CP_REG_AC_ACCU_IMAG0__W 8
10619#define B_CP_REG_AC_ACCU_IMAG0__M 0xFF
10620#define B_CP_REG_AC_ACCU_IMAG0_INIT 0x0
10621
10622
10623#define B_CP_REG_AC_ACCU_REAL1__A 0x1410062
10624#define B_CP_REG_AC_ACCU_REAL1__W 8
10625#define B_CP_REG_AC_ACCU_REAL1__M 0xFF
10626#define B_CP_REG_AC_ACCU_REAL1_INIT 0x0
10627
10628
10629#define B_CP_REG_AC_ACCU_IMAG1__A 0x1410063
10630#define B_CP_REG_AC_ACCU_IMAG1__W 8
10631#define B_CP_REG_AC_ACCU_IMAG1__M 0xFF
10632#define B_CP_REG_AC_ACCU_IMAG1_INIT 0x0
10633
10634
10635#define B_CP_REG_DL_MB_WR_ADDR__A 0x1410050
10636#define B_CP_REG_DL_MB_WR_ADDR__W 15
10637#define B_CP_REG_DL_MB_WR_ADDR__M 0x7FFF
10638#define B_CP_REG_DL_MB_WR_ADDR_INIT 0x0
10639
10640
10641#define B_CP_REG_DL_MB_WR_CTR__A 0x1410051
10642#define B_CP_REG_DL_MB_WR_CTR__W 5
10643#define B_CP_REG_DL_MB_WR_CTR__M 0x1F
10644
10645#define B_CP_REG_DL_MB_WR_CTR_WORD__B 2
10646#define B_CP_REG_DL_MB_WR_CTR_WORD__W 3
10647#define B_CP_REG_DL_MB_WR_CTR_WORD__M 0x1C
10648
10649#define B_CP_REG_DL_MB_WR_CTR_OBS__B 1
10650#define B_CP_REG_DL_MB_WR_CTR_OBS__W 1
10651#define B_CP_REG_DL_MB_WR_CTR_OBS__M 0x2
10652
10653#define B_CP_REG_DL_MB_WR_CTR_CTR__B 0
10654#define B_CP_REG_DL_MB_WR_CTR_CTR__W 1
10655#define B_CP_REG_DL_MB_WR_CTR_CTR__M 0x1
10656#define B_CP_REG_DL_MB_WR_CTR_INIT 0x0
10657
10658
10659#define B_CP_REG_DL_MB_RD_ADDR__A 0x1410052
10660#define B_CP_REG_DL_MB_RD_ADDR__W 15
10661#define B_CP_REG_DL_MB_RD_ADDR__M 0x7FFF
10662#define B_CP_REG_DL_MB_RD_ADDR_INIT 0x0
10663
10664
10665#define B_CP_REG_DL_MB_RD_CTR__A 0x1410053
10666#define B_CP_REG_DL_MB_RD_CTR__W 11
10667#define B_CP_REG_DL_MB_RD_CTR__M 0x7FF
10668
10669#define B_CP_REG_DL_MB_RD_CTR_TEST__B 10
10670#define B_CP_REG_DL_MB_RD_CTR_TEST__W 1
10671#define B_CP_REG_DL_MB_RD_CTR_TEST__M 0x400
10672
10673#define B_CP_REG_DL_MB_RD_CTR_OFFSET__B 8
10674#define B_CP_REG_DL_MB_RD_CTR_OFFSET__W 2
10675#define B_CP_REG_DL_MB_RD_CTR_OFFSET__M 0x300
10676
10677#define B_CP_REG_DL_MB_RD_CTR_VALID__B 5
10678#define B_CP_REG_DL_MB_RD_CTR_VALID__W 3
10679#define B_CP_REG_DL_MB_RD_CTR_VALID__M 0xE0
10680
10681#define B_CP_REG_DL_MB_RD_CTR_WORD__B 2
10682#define B_CP_REG_DL_MB_RD_CTR_WORD__W 3
10683#define B_CP_REG_DL_MB_RD_CTR_WORD__M 0x1C
10684
10685#define B_CP_REG_DL_MB_RD_CTR_OBS__B 1
10686#define B_CP_REG_DL_MB_RD_CTR_OBS__W 1
10687#define B_CP_REG_DL_MB_RD_CTR_OBS__M 0x2
10688
10689#define B_CP_REG_DL_MB_RD_CTR_CTR__B 0
10690#define B_CP_REG_DL_MB_RD_CTR_CTR__W 1
10691#define B_CP_REG_DL_MB_RD_CTR_CTR__M 0x1
10692#define B_CP_REG_DL_MB_RD_CTR_INIT 0x0
10693
10694
10695
10696#define B_CP_BR_BUF_RAM__A 0x1420000
10697
10698
10699
10700#define B_CP_BR_CPL_RAM__A 0x1430000
10701
10702
10703
10704#define B_CP_PB_DL0_RAM__A 0x1440000
10705
10706
10707
10708#define B_CP_PB_DL1_RAM__A 0x1450000
10709
10710
10711
10712#define B_CP_PB_DL2_RAM__A 0x1460000
10713
10714
10715
10716
10717
10718#define B_CE_SID 0xA
10719
10720
10721
10722
10723
10724#define B_CE_COMM_EXEC__A 0x1800000
10725#define B_CE_COMM_EXEC__W 3
10726#define B_CE_COMM_EXEC__M 0x7
10727#define B_CE_COMM_EXEC_CTL__B 0
10728#define B_CE_COMM_EXEC_CTL__W 3
10729#define B_CE_COMM_EXEC_CTL__M 0x7
10730#define B_CE_COMM_EXEC_CTL_STOP 0x0
10731#define B_CE_COMM_EXEC_CTL_ACTIVE 0x1
10732#define B_CE_COMM_EXEC_CTL_HOLD 0x2
10733#define B_CE_COMM_EXEC_CTL_STEP 0x3
10734#define B_CE_COMM_EXEC_CTL_BYPASS_STOP 0x4
10735#define B_CE_COMM_EXEC_CTL_BYPASS_HOLD 0x6
10736
10737#define B_CE_COMM_STATE__A 0x1800001
10738#define B_CE_COMM_STATE__W 16
10739#define B_CE_COMM_STATE__M 0xFFFF
10740#define B_CE_COMM_MB__A 0x1800002
10741#define B_CE_COMM_MB__W 16
10742#define B_CE_COMM_MB__M 0xFFFF
10743#define B_CE_COMM_SERVICE0__A 0x1800003
10744#define B_CE_COMM_SERVICE0__W 16
10745#define B_CE_COMM_SERVICE0__M 0xFFFF
10746#define B_CE_COMM_SERVICE1__A 0x1800004
10747#define B_CE_COMM_SERVICE1__W 16
10748#define B_CE_COMM_SERVICE1__M 0xFFFF
10749#define B_CE_COMM_INT_STA__A 0x1800007
10750#define B_CE_COMM_INT_STA__W 16
10751#define B_CE_COMM_INT_STA__M 0xFFFF
10752#define B_CE_COMM_INT_MSK__A 0x1800008
10753#define B_CE_COMM_INT_MSK__W 16
10754#define B_CE_COMM_INT_MSK__M 0xFFFF
10755
10756
10757
10758
10759
10760
10761#define B_CE_REG_COMM_EXEC__A 0x1810000
10762#define B_CE_REG_COMM_EXEC__W 3
10763#define B_CE_REG_COMM_EXEC__M 0x7
10764#define B_CE_REG_COMM_EXEC_CTL__B 0
10765#define B_CE_REG_COMM_EXEC_CTL__W 3
10766#define B_CE_REG_COMM_EXEC_CTL__M 0x7
10767#define B_CE_REG_COMM_EXEC_CTL_STOP 0x0
10768#define B_CE_REG_COMM_EXEC_CTL_ACTIVE 0x1
10769#define B_CE_REG_COMM_EXEC_CTL_HOLD 0x2
10770#define B_CE_REG_COMM_EXEC_CTL_STEP 0x3
10771
10772
10773#define B_CE_REG_COMM_MB__A 0x1810002
10774#define B_CE_REG_COMM_MB__W 4
10775#define B_CE_REG_COMM_MB__M 0xF
10776#define B_CE_REG_COMM_MB_CTR__B 0
10777#define B_CE_REG_COMM_MB_CTR__W 1
10778#define B_CE_REG_COMM_MB_CTR__M 0x1
10779#define B_CE_REG_COMM_MB_CTR_OFF 0x0
10780#define B_CE_REG_COMM_MB_CTR_ON 0x1
10781#define B_CE_REG_COMM_MB_OBS__B 1
10782#define B_CE_REG_COMM_MB_OBS__W 1
10783#define B_CE_REG_COMM_MB_OBS__M 0x2
10784#define B_CE_REG_COMM_MB_OBS_OFF 0x0
10785#define B_CE_REG_COMM_MB_OBS_ON 0x2
10786#define B_CE_REG_COMM_MB_OBS_SEL__B 2
10787#define B_CE_REG_COMM_MB_OBS_SEL__W 2
10788#define B_CE_REG_COMM_MB_OBS_SEL__M 0xC
10789#define B_CE_REG_COMM_MB_OBS_SEL_FI 0x0
10790#define B_CE_REG_COMM_MB_OBS_SEL_TP 0x4
10791#define B_CE_REG_COMM_MB_OBS_SEL_TI 0x8
10792#define B_CE_REG_COMM_MB_OBS_SEL_FR 0x8
10793
10794#define B_CE_REG_COMM_SERVICE0__A 0x1810003
10795#define B_CE_REG_COMM_SERVICE0__W 10
10796#define B_CE_REG_COMM_SERVICE0__M 0x3FF
10797#define B_CE_REG_COMM_SERVICE0_FT__B 8
10798#define B_CE_REG_COMM_SERVICE0_FT__W 1
10799#define B_CE_REG_COMM_SERVICE0_FT__M 0x100
10800
10801#define B_CE_REG_COMM_SERVICE1__A 0x1810004
10802#define B_CE_REG_COMM_SERVICE1__W 11
10803#define B_CE_REG_COMM_SERVICE1__M 0x7FF
10804
10805#define B_CE_REG_COMM_INT_STA__A 0x1810007
10806#define B_CE_REG_COMM_INT_STA__W 3
10807#define B_CE_REG_COMM_INT_STA__M 0x7
10808#define B_CE_REG_COMM_INT_STA_CE_PE__B 0
10809#define B_CE_REG_COMM_INT_STA_CE_PE__W 1
10810#define B_CE_REG_COMM_INT_STA_CE_PE__M 0x1
10811#define B_CE_REG_COMM_INT_STA_CE_IR__B 1
10812#define B_CE_REG_COMM_INT_STA_CE_IR__W 1
10813#define B_CE_REG_COMM_INT_STA_CE_IR__M 0x2
10814#define B_CE_REG_COMM_INT_STA_CE_FI__B 2
10815#define B_CE_REG_COMM_INT_STA_CE_FI__W 1
10816#define B_CE_REG_COMM_INT_STA_CE_FI__M 0x4
10817
10818
10819#define B_CE_REG_COMM_INT_MSK__A 0x1810008
10820#define B_CE_REG_COMM_INT_MSK__W 3
10821#define B_CE_REG_COMM_INT_MSK__M 0x7
10822#define B_CE_REG_COMM_INT_MSK_CE_PE__B 0
10823#define B_CE_REG_COMM_INT_MSK_CE_PE__W 1
10824#define B_CE_REG_COMM_INT_MSK_CE_PE__M 0x1
10825#define B_CE_REG_COMM_INT_MSK_CE_IR__B 1
10826#define B_CE_REG_COMM_INT_MSK_CE_IR__W 1
10827#define B_CE_REG_COMM_INT_MSK_CE_IR__M 0x2
10828#define B_CE_REG_COMM_INT_MSK_CE_FI__B 2
10829#define B_CE_REG_COMM_INT_MSK_CE_FI__W 1
10830#define B_CE_REG_COMM_INT_MSK_CE_FI__M 0x4
10831
10832
10833#define B_CE_REG_2K__A 0x1810010
10834#define B_CE_REG_2K__W 1
10835#define B_CE_REG_2K__M 0x1
10836#define B_CE_REG_2K_INIT 0x0
10837
10838
10839#define B_CE_REG_TAPSET__A 0x1810011
10840#define B_CE_REG_TAPSET__W 4
10841#define B_CE_REG_TAPSET__M 0xF
10842
10843
10844
10845#define B_CE_REG_TAPSET_MOTION_INIT 0x0
10846
10847#define B_CE_REG_TAPSET_MOTION_NO 0x0
10848
10849#define B_CE_REG_TAPSET_MOTION_LOW 0x1
10850
10851#define B_CE_REG_TAPSET_MOTION_HIGH 0x2
10852
10853#define B_CE_REG_TAPSET_MOTION_HIGH2 0x4
10854
10855#define B_CE_REG_TAPSET_MOTION_UNDEFINED 0x8
10856
10857
10858#define B_CE_REG_AVG_POW__A 0x1810012
10859#define B_CE_REG_AVG_POW__W 8
10860#define B_CE_REG_AVG_POW__M 0xFF
10861#define B_CE_REG_AVG_POW_INIT 0x0
10862
10863
10864#define B_CE_REG_MAX_POW__A 0x1810013
10865#define B_CE_REG_MAX_POW__W 8
10866#define B_CE_REG_MAX_POW__M 0xFF
10867#define B_CE_REG_MAX_POW_INIT 0x0
10868
10869
10870#define B_CE_REG_ATT__A 0x1810014
10871#define B_CE_REG_ATT__W 8
10872#define B_CE_REG_ATT__M 0xFF
10873#define B_CE_REG_ATT_INIT 0x0
10874
10875
10876#define B_CE_REG_NRED__A 0x1810015
10877#define B_CE_REG_NRED__W 6
10878#define B_CE_REG_NRED__M 0x3F
10879#define B_CE_REG_NRED_INIT 0x0
10880
10881
10882#define B_CE_REG_PU_SIGN__A 0x1810020
10883#define B_CE_REG_PU_SIGN__W 1
10884#define B_CE_REG_PU_SIGN__M 0x1
10885#define B_CE_REG_PU_SIGN_INIT 0x0
10886
10887
10888#define B_CE_REG_PU_MIX__A 0x1810021
10889#define B_CE_REG_PU_MIX__W 1
10890#define B_CE_REG_PU_MIX__M 0x1
10891#define B_CE_REG_PU_MIX_INIT 0x0
10892
10893
10894#define B_CE_REG_PB_PILOT_REQ__A 0x1810030
10895#define B_CE_REG_PB_PILOT_REQ__W 15
10896#define B_CE_REG_PB_PILOT_REQ__M 0x7FFF
10897#define B_CE_REG_PB_PILOT_REQ_INIT 0x0
10898#define B_CE_REG_PB_PILOT_REQ_BUFFER_INDEX__B 12
10899#define B_CE_REG_PB_PILOT_REQ_BUFFER_INDEX__W 3
10900#define B_CE_REG_PB_PILOT_REQ_BUFFER_INDEX__M 0x7000
10901#define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__B 0
10902#define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__W 12
10903#define B_CE_REG_PB_PILOT_REQ_PILOT_ADR__M 0xFFF
10904
10905
10906#define B_CE_REG_PB_PILOT_REQ_VALID__A 0x1810031
10907#define B_CE_REG_PB_PILOT_REQ_VALID__W 1
10908#define B_CE_REG_PB_PILOT_REQ_VALID__M 0x1
10909#define B_CE_REG_PB_PILOT_REQ_VALID_INIT 0x0
10910
10911
10912#define B_CE_REG_PB_FREEZE__A 0x1810032
10913#define B_CE_REG_PB_FREEZE__W 1
10914#define B_CE_REG_PB_FREEZE__M 0x1
10915#define B_CE_REG_PB_FREEZE_INIT 0x0
10916
10917
10918#define B_CE_REG_PB_PILOT_EXP__A 0x1810038
10919#define B_CE_REG_PB_PILOT_EXP__W 4
10920#define B_CE_REG_PB_PILOT_EXP__M 0xF
10921#define B_CE_REG_PB_PILOT_EXP_INIT 0x0
10922
10923
10924#define B_CE_REG_PB_PILOT_REAL__A 0x1810039
10925#define B_CE_REG_PB_PILOT_REAL__W 10
10926#define B_CE_REG_PB_PILOT_REAL__M 0x3FF
10927#define B_CE_REG_PB_PILOT_REAL_INIT 0x0
10928
10929
10930#define B_CE_REG_PB_PILOT_IMAG__A 0x181003A
10931#define B_CE_REG_PB_PILOT_IMAG__W 10
10932#define B_CE_REG_PB_PILOT_IMAG__M 0x3FF
10933#define B_CE_REG_PB_PILOT_IMAG_INIT 0x0
10934
10935
10936#define B_CE_REG_PB_SMBNR__A 0x181003B
10937#define B_CE_REG_PB_SMBNR__W 5
10938#define B_CE_REG_PB_SMBNR__M 0x1F
10939#define B_CE_REG_PB_SMBNR_INIT 0x0
10940
10941
10942#define B_CE_REG_NE_PILOT_REQ__A 0x1810040
10943#define B_CE_REG_NE_PILOT_REQ__W 12
10944#define B_CE_REG_NE_PILOT_REQ__M 0xFFF
10945#define B_CE_REG_NE_PILOT_REQ_INIT 0x0
10946
10947
10948#define B_CE_REG_NE_PILOT_REQ_VALID__A 0x1810041
10949#define B_CE_REG_NE_PILOT_REQ_VALID__W 2
10950#define B_CE_REG_NE_PILOT_REQ_VALID__M 0x3
10951#define B_CE_REG_NE_PILOT_REQ_VALID_INIT 0x0
10952#define B_CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__B 1
10953#define B_CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__W 1
10954#define B_CE_REG_NE_PILOT_REQ_VALID_WRITE_VALID__M 0x2
10955#define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__B 0
10956#define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__W 1
10957#define B_CE_REG_NE_PILOT_REQ_VALID_READ_VALID__M 0x1
10958
10959
10960#define B_CE_REG_NE_PILOT_DATA__A 0x1810042
10961#define B_CE_REG_NE_PILOT_DATA__W 10
10962#define B_CE_REG_NE_PILOT_DATA__M 0x3FF
10963#define B_CE_REG_NE_PILOT_DATA_INIT 0x0
10964
10965
10966#define B_CE_REG_NE_ERR_SELECT__A 0x1810043
10967#define B_CE_REG_NE_ERR_SELECT__W 5
10968#define B_CE_REG_NE_ERR_SELECT__M 0x1F
10969#define B_CE_REG_NE_ERR_SELECT_INIT 0x7
10970
10971#define B_CE_REG_NE_ERR_SELECT_MAX_UPD__B 4
10972#define B_CE_REG_NE_ERR_SELECT_MAX_UPD__W 1
10973#define B_CE_REG_NE_ERR_SELECT_MAX_UPD__M 0x10
10974
10975#define B_CE_REG_NE_ERR_SELECT_MED_MATCH__B 3
10976#define B_CE_REG_NE_ERR_SELECT_MED_MATCH__W 1
10977#define B_CE_REG_NE_ERR_SELECT_MED_MATCH__M 0x8
10978
10979#define B_CE_REG_NE_ERR_SELECT_RESET_RAM__B 2
10980#define B_CE_REG_NE_ERR_SELECT_RESET_RAM__W 1
10981#define B_CE_REG_NE_ERR_SELECT_RESET_RAM__M 0x4
10982
10983#define B_CE_REG_NE_ERR_SELECT_FD_ENABLE__B 1
10984#define B_CE_REG_NE_ERR_SELECT_FD_ENABLE__W 1
10985#define B_CE_REG_NE_ERR_SELECT_FD_ENABLE__M 0x2
10986
10987#define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__B 0
10988#define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__W 1
10989#define B_CE_REG_NE_ERR_SELECT_TD_ENABLE__M 0x1
10990
10991
10992#define B_CE_REG_NE_TD_CAL__A 0x1810044
10993#define B_CE_REG_NE_TD_CAL__W 9
10994#define B_CE_REG_NE_TD_CAL__M 0x1FF
10995#define B_CE_REG_NE_TD_CAL_INIT 0x1E8
10996
10997
10998#define B_CE_REG_NE_FD_CAL__A 0x1810045
10999#define B_CE_REG_NE_FD_CAL__W 9
11000#define B_CE_REG_NE_FD_CAL__M 0x1FF
11001#define B_CE_REG_NE_FD_CAL_INIT 0x1D9
11002
11003
11004#define B_CE_REG_NE_MIXAVG__A 0x1810046
11005#define B_CE_REG_NE_MIXAVG__W 3
11006#define B_CE_REG_NE_MIXAVG__M 0x7
11007#define B_CE_REG_NE_MIXAVG_INIT 0x6
11008
11009
11010#define B_CE_REG_NE_NUPD_OFS__A 0x1810047
11011#define B_CE_REG_NE_NUPD_OFS__W 4
11012#define B_CE_REG_NE_NUPD_OFS__M 0xF
11013#define B_CE_REG_NE_NUPD_OFS_INIT 0x4
11014
11015
11016#define B_CE_REG_NE_TD_POW__A 0x1810048
11017#define B_CE_REG_NE_TD_POW__W 15
11018#define B_CE_REG_NE_TD_POW__M 0x7FFF
11019#define B_CE_REG_NE_TD_POW_INIT 0x0
11020
11021#define B_CE_REG_NE_TD_POW_EXPONENT__B 10
11022#define B_CE_REG_NE_TD_POW_EXPONENT__W 5
11023#define B_CE_REG_NE_TD_POW_EXPONENT__M 0x7C00
11024
11025#define B_CE_REG_NE_TD_POW_MANTISSA__B 0
11026#define B_CE_REG_NE_TD_POW_MANTISSA__W 10
11027#define B_CE_REG_NE_TD_POW_MANTISSA__M 0x3FF
11028
11029
11030#define B_CE_REG_NE_FD_POW__A 0x1810049
11031#define B_CE_REG_NE_FD_POW__W 15
11032#define B_CE_REG_NE_FD_POW__M 0x7FFF
11033#define B_CE_REG_NE_FD_POW_INIT 0x0
11034
11035#define B_CE_REG_NE_FD_POW_EXPONENT__B 10
11036#define B_CE_REG_NE_FD_POW_EXPONENT__W 5
11037#define B_CE_REG_NE_FD_POW_EXPONENT__M 0x7C00
11038
11039#define B_CE_REG_NE_FD_POW_MANTISSA__B 0
11040#define B_CE_REG_NE_FD_POW_MANTISSA__W 10
11041#define B_CE_REG_NE_FD_POW_MANTISSA__M 0x3FF
11042
11043
11044#define B_CE_REG_NE_NEXP_AVG__A 0x181004A
11045#define B_CE_REG_NE_NEXP_AVG__W 8
11046#define B_CE_REG_NE_NEXP_AVG__M 0xFF
11047#define B_CE_REG_NE_NEXP_AVG_INIT 0x0
11048
11049
11050#define B_CE_REG_NE_OFFSET__A 0x181004B
11051#define B_CE_REG_NE_OFFSET__W 9
11052#define B_CE_REG_NE_OFFSET__M 0x1FF
11053#define B_CE_REG_NE_OFFSET_INIT 0x0
11054
11055
11056#define B_CE_REG_NE_NUPD_TRH__A 0x181004C
11057#define B_CE_REG_NE_NUPD_TRH__W 5
11058#define B_CE_REG_NE_NUPD_TRH__M 0x1F
11059#define B_CE_REG_NE_NUPD_TRH_INIT 0x14
11060
11061
11062#define B_CE_REG_PE_NEXP_OFFS__A 0x1810050
11063#define B_CE_REG_PE_NEXP_OFFS__W 8
11064#define B_CE_REG_PE_NEXP_OFFS__M 0xFF
11065#define B_CE_REG_PE_NEXP_OFFS_INIT 0x0
11066
11067
11068#define B_CE_REG_PE_TIMESHIFT__A 0x1810051
11069#define B_CE_REG_PE_TIMESHIFT__W 14
11070#define B_CE_REG_PE_TIMESHIFT__M 0x3FFF
11071#define B_CE_REG_PE_TIMESHIFT_INIT 0x0
11072
11073
11074#define B_CE_REG_PE_DIF_REAL_L__A 0x1810052
11075#define B_CE_REG_PE_DIF_REAL_L__W 16
11076#define B_CE_REG_PE_DIF_REAL_L__M 0xFFFF
11077#define B_CE_REG_PE_DIF_REAL_L_INIT 0x0
11078
11079
11080#define B_CE_REG_PE_DIF_IMAG_L__A 0x1810053
11081#define B_CE_REG_PE_DIF_IMAG_L__W 16
11082#define B_CE_REG_PE_DIF_IMAG_L__M 0xFFFF
11083#define B_CE_REG_PE_DIF_IMAG_L_INIT 0x0
11084
11085
11086#define B_CE_REG_PE_DIF_REAL_R__A 0x1810054
11087#define B_CE_REG_PE_DIF_REAL_R__W 16
11088#define B_CE_REG_PE_DIF_REAL_R__M 0xFFFF
11089#define B_CE_REG_PE_DIF_REAL_R_INIT 0x0
11090
11091
11092#define B_CE_REG_PE_DIF_IMAG_R__A 0x1810055
11093#define B_CE_REG_PE_DIF_IMAG_R__W 16
11094#define B_CE_REG_PE_DIF_IMAG_R__M 0xFFFF
11095#define B_CE_REG_PE_DIF_IMAG_R_INIT 0x0
11096
11097
11098#define B_CE_REG_PE_ABS_REAL_L__A 0x1810056
11099#define B_CE_REG_PE_ABS_REAL_L__W 16
11100#define B_CE_REG_PE_ABS_REAL_L__M 0xFFFF
11101#define B_CE_REG_PE_ABS_REAL_L_INIT 0x0
11102
11103
11104#define B_CE_REG_PE_ABS_IMAG_L__A 0x1810057
11105#define B_CE_REG_PE_ABS_IMAG_L__W 16
11106#define B_CE_REG_PE_ABS_IMAG_L__M 0xFFFF
11107#define B_CE_REG_PE_ABS_IMAG_L_INIT 0x0
11108
11109
11110#define B_CE_REG_PE_ABS_REAL_R__A 0x1810058
11111#define B_CE_REG_PE_ABS_REAL_R__W 16
11112#define B_CE_REG_PE_ABS_REAL_R__M 0xFFFF
11113#define B_CE_REG_PE_ABS_REAL_R_INIT 0x0
11114
11115
11116#define B_CE_REG_PE_ABS_IMAG_R__A 0x1810059
11117#define B_CE_REG_PE_ABS_IMAG_R__W 16
11118#define B_CE_REG_PE_ABS_IMAG_R__M 0xFFFF
11119#define B_CE_REG_PE_ABS_IMAG_R_INIT 0x0
11120
11121
11122#define B_CE_REG_PE_ABS_EXP_L__A 0x181005A
11123#define B_CE_REG_PE_ABS_EXP_L__W 5
11124#define B_CE_REG_PE_ABS_EXP_L__M 0x1F
11125#define B_CE_REG_PE_ABS_EXP_L_INIT 0x0
11126
11127
11128#define B_CE_REG_PE_ABS_EXP_R__A 0x181005B
11129#define B_CE_REG_PE_ABS_EXP_R__W 5
11130#define B_CE_REG_PE_ABS_EXP_R__M 0x1F
11131#define B_CE_REG_PE_ABS_EXP_R_INIT 0x0
11132
11133
11134#define B_CE_REG_TP_UPDATE_MODE__A 0x1810060
11135#define B_CE_REG_TP_UPDATE_MODE__W 1
11136#define B_CE_REG_TP_UPDATE_MODE__M 0x1
11137#define B_CE_REG_TP_UPDATE_MODE_INIT 0x0
11138
11139
11140#define B_CE_REG_TP_LMS_TAP_ON__A 0x1810061
11141#define B_CE_REG_TP_LMS_TAP_ON__W 1
11142#define B_CE_REG_TP_LMS_TAP_ON__M 0x1
11143
11144#define B_CE_REG_TP_A0_TAP_NEW__A 0x1810064
11145#define B_CE_REG_TP_A0_TAP_NEW__W 10
11146#define B_CE_REG_TP_A0_TAP_NEW__M 0x3FF
11147
11148#define B_CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065
11149#define B_CE_REG_TP_A0_TAP_NEW_VALID__W 1
11150#define B_CE_REG_TP_A0_TAP_NEW_VALID__M 0x1
11151
11152#define B_CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066
11153#define B_CE_REG_TP_A0_MU_LMS_STEP__W 5
11154#define B_CE_REG_TP_A0_MU_LMS_STEP__M 0x1F
11155
11156#define B_CE_REG_TP_A0_TAP_CURR__A 0x1810067
11157#define B_CE_REG_TP_A0_TAP_CURR__W 10
11158#define B_CE_REG_TP_A0_TAP_CURR__M 0x3FF
11159
11160#define B_CE_REG_TP_A1_TAP_NEW__A 0x1810068
11161#define B_CE_REG_TP_A1_TAP_NEW__W 10
11162#define B_CE_REG_TP_A1_TAP_NEW__M 0x3FF
11163
11164#define B_CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069
11165#define B_CE_REG_TP_A1_TAP_NEW_VALID__W 1
11166#define B_CE_REG_TP_A1_TAP_NEW_VALID__M 0x1
11167
11168#define B_CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A
11169#define B_CE_REG_TP_A1_MU_LMS_STEP__W 5
11170#define B_CE_REG_TP_A1_MU_LMS_STEP__M 0x1F
11171
11172#define B_CE_REG_TP_A1_TAP_CURR__A 0x181006B
11173#define B_CE_REG_TP_A1_TAP_CURR__W 10
11174#define B_CE_REG_TP_A1_TAP_CURR__M 0x3FF
11175
11176#define B_CE_REG_TP_DOPP_ENERGY__A 0x181006C
11177#define B_CE_REG_TP_DOPP_ENERGY__W 15
11178#define B_CE_REG_TP_DOPP_ENERGY__M 0x7FFF
11179#define B_CE_REG_TP_DOPP_ENERGY_INIT 0x0
11180
11181#define B_CE_REG_TP_DOPP_ENERGY_EXPONENT__B 10
11182#define B_CE_REG_TP_DOPP_ENERGY_EXPONENT__W 5
11183#define B_CE_REG_TP_DOPP_ENERGY_EXPONENT__M 0x7C00
11184
11185#define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__B 0
11186#define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__W 10
11187#define B_CE_REG_TP_DOPP_ENERGY_MANTISSA__M 0x3FF
11188
11189
11190#define B_CE_REG_TP_DOPP_DIFF_ENERGY__A 0x181006D
11191#define B_CE_REG_TP_DOPP_DIFF_ENERGY__W 15
11192#define B_CE_REG_TP_DOPP_DIFF_ENERGY__M 0x7FFF
11193#define B_CE_REG_TP_DOPP_DIFF_ENERGY_INIT 0x0
11194
11195#define B_CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__B 10
11196#define B_CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__W 5
11197#define B_CE_REG_TP_DOPP_DIFF_ENERGY_EXPONENT__M 0x7C00
11198
11199#define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__B 0
11200#define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__W 10
11201#define B_CE_REG_TP_DOPP_DIFF_ENERGY_MANTISSA__M 0x3FF
11202
11203
11204#define B_CE_REG_TP_A0_TAP_ENERGY__A 0x181006E
11205#define B_CE_REG_TP_A0_TAP_ENERGY__W 15
11206#define B_CE_REG_TP_A0_TAP_ENERGY__M 0x7FFF
11207#define B_CE_REG_TP_A0_TAP_ENERGY_INIT 0x0
11208
11209#define B_CE_REG_TP_A0_TAP_ENERGY_EXPONENT__B 10
11210#define B_CE_REG_TP_A0_TAP_ENERGY_EXPONENT__W 5
11211#define B_CE_REG_TP_A0_TAP_ENERGY_EXPONENT__M 0x7C00
11212
11213#define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__B 0
11214#define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__W 10
11215#define B_CE_REG_TP_A0_TAP_ENERGY_MANTISSA__M 0x3FF
11216
11217
11218#define B_CE_REG_TP_A1_TAP_ENERGY__A 0x181006F
11219#define B_CE_REG_TP_A1_TAP_ENERGY__W 15
11220#define B_CE_REG_TP_A1_TAP_ENERGY__M 0x7FFF
11221#define B_CE_REG_TP_A1_TAP_ENERGY_INIT 0x0
11222
11223#define B_CE_REG_TP_A1_TAP_ENERGY_EXPONENT__B 10
11224#define B_CE_REG_TP_A1_TAP_ENERGY_EXPONENT__W 5
11225#define B_CE_REG_TP_A1_TAP_ENERGY_EXPONENT__M 0x7C00
11226
11227#define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__B 0
11228#define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__W 10
11229#define B_CE_REG_TP_A1_TAP_ENERGY_MANTISSA__M 0x3FF
11230
11231
11232#define B_CE_REG_TI_SYM_CNT__A 0x1810072
11233#define B_CE_REG_TI_SYM_CNT__W 6
11234#define B_CE_REG_TI_SYM_CNT__M 0x3F
11235#define B_CE_REG_TI_SYM_CNT_INIT 0x0
11236
11237
11238#define B_CE_REG_TI_PHN_ENABLE__A 0x1810073
11239#define B_CE_REG_TI_PHN_ENABLE__W 1
11240#define B_CE_REG_TI_PHN_ENABLE__M 0x1
11241#define B_CE_REG_TI_PHN_ENABLE_INIT 0x0
11242
11243
11244#define B_CE_REG_TI_SHIFT__A 0x1810074
11245#define B_CE_REG_TI_SHIFT__W 2
11246#define B_CE_REG_TI_SHIFT__M 0x3
11247#define B_CE_REG_TI_SHIFT_INIT 0x0
11248
11249
11250#define B_CE_REG_TI_SLOW__A 0x1810075
11251#define B_CE_REG_TI_SLOW__W 1
11252#define B_CE_REG_TI_SLOW__M 0x1
11253#define B_CE_REG_TI_SLOW_INIT 0x0
11254
11255
11256#define B_CE_REG_TI_MGAIN__A 0x1810076
11257#define B_CE_REG_TI_MGAIN__W 8
11258#define B_CE_REG_TI_MGAIN__M 0xFF
11259#define B_CE_REG_TI_MGAIN_INIT 0x0
11260
11261
11262#define B_CE_REG_TI_ACCU1__A 0x1810077
11263#define B_CE_REG_TI_ACCU1__W 8
11264#define B_CE_REG_TI_ACCU1__M 0xFF
11265#define B_CE_REG_TI_ACCU1_INIT 0x0
11266
11267
11268#define B_CE_REG_NI_PER_LEFT__A 0x18100B0
11269#define B_CE_REG_NI_PER_LEFT__W 5
11270#define B_CE_REG_NI_PER_LEFT__M 0x1F
11271#define B_CE_REG_NI_PER_LEFT_INIT 0xE
11272
11273
11274#define B_CE_REG_NI_PER_RIGHT__A 0x18100B1
11275#define B_CE_REG_NI_PER_RIGHT__W 5
11276#define B_CE_REG_NI_PER_RIGHT__M 0x1F
11277#define B_CE_REG_NI_PER_RIGHT_INIT 0x7
11278
11279
11280#define B_CE_REG_NI_POS_LR__A 0x18100B2
11281#define B_CE_REG_NI_POS_LR__W 9
11282#define B_CE_REG_NI_POS_LR__M 0x1FF
11283#define B_CE_REG_NI_POS_LR_INIT 0xA0
11284
11285
11286#define B_CE_REG_FI_SHT_INCR__A 0x1810090
11287#define B_CE_REG_FI_SHT_INCR__W 7
11288#define B_CE_REG_FI_SHT_INCR__M 0x7F
11289#define B_CE_REG_FI_SHT_INCR_INIT 0x9
11290
11291
11292#define B_CE_REG_FI_EXP_NORM__A 0x1810091
11293#define B_CE_REG_FI_EXP_NORM__W 4
11294#define B_CE_REG_FI_EXP_NORM__M 0xF
11295#define B_CE_REG_FI_EXP_NORM_INIT 0x4
11296
11297
11298#define B_CE_REG_FI_SUPR_VAL__A 0x1810092
11299#define B_CE_REG_FI_SUPR_VAL__W 1
11300#define B_CE_REG_FI_SUPR_VAL__M 0x1
11301#define B_CE_REG_FI_SUPR_VAL_INIT 0x1
11302
11303
11304#define B_CE_REG_IR_INPUTSEL__A 0x18100A0
11305#define B_CE_REG_IR_INPUTSEL__W 1
11306#define B_CE_REG_IR_INPUTSEL__M 0x1
11307#define B_CE_REG_IR_INPUTSEL_INIT 0x0
11308
11309
11310#define B_CE_REG_IR_STARTPOS__A 0x18100A1
11311#define B_CE_REG_IR_STARTPOS__W 8
11312#define B_CE_REG_IR_STARTPOS__M 0xFF
11313#define B_CE_REG_IR_STARTPOS_INIT 0x0
11314
11315
11316#define B_CE_REG_IR_NEXP_THRES__A 0x18100A2
11317#define B_CE_REG_IR_NEXP_THRES__W 8
11318#define B_CE_REG_IR_NEXP_THRES__M 0xFF
11319#define B_CE_REG_IR_NEXP_THRES_INIT 0x0
11320
11321
11322#define B_CE_REG_IR_LENGTH__A 0x18100A3
11323#define B_CE_REG_IR_LENGTH__W 4
11324#define B_CE_REG_IR_LENGTH__M 0xF
11325#define B_CE_REG_IR_LENGTH_INIT 0x0
11326
11327
11328#define B_CE_REG_IR_FREQ__A 0x18100A4
11329#define B_CE_REG_IR_FREQ__W 11
11330#define B_CE_REG_IR_FREQ__M 0x7FF
11331#define B_CE_REG_IR_FREQ_INIT 0x0
11332
11333
11334#define B_CE_REG_IR_FREQINC__A 0x18100A5
11335#define B_CE_REG_IR_FREQINC__W 11
11336#define B_CE_REG_IR_FREQINC__M 0x7FF
11337#define B_CE_REG_IR_FREQINC_INIT 0x0
11338
11339
11340#define B_CE_REG_IR_KAISINC__A 0x18100A6
11341#define B_CE_REG_IR_KAISINC__W 15
11342#define B_CE_REG_IR_KAISINC__M 0x7FFF
11343#define B_CE_REG_IR_KAISINC_INIT 0x0
11344
11345
11346#define B_CE_REG_IR_CTL__A 0x18100A7
11347#define B_CE_REG_IR_CTL__W 3
11348#define B_CE_REG_IR_CTL__M 0x7
11349#define B_CE_REG_IR_CTL_INIT 0x0
11350
11351
11352#define B_CE_REG_IR_REAL__A 0x18100A8
11353#define B_CE_REG_IR_REAL__W 16
11354#define B_CE_REG_IR_REAL__M 0xFFFF
11355#define B_CE_REG_IR_REAL_INIT 0x0
11356
11357
11358#define B_CE_REG_IR_IMAG__A 0x18100A9
11359#define B_CE_REG_IR_IMAG__W 16
11360#define B_CE_REG_IR_IMAG__M 0xFFFF
11361#define B_CE_REG_IR_IMAG_INIT 0x0
11362
11363
11364#define B_CE_REG_IR_INDEX__A 0x18100AA
11365#define B_CE_REG_IR_INDEX__W 12
11366#define B_CE_REG_IR_INDEX__M 0xFFF
11367#define B_CE_REG_IR_INDEX_INIT 0x0
11368
11369
11370
11371
11372#define B_CE_REG_FR_COMM_EXEC__A 0x1820000
11373#define B_CE_REG_FR_COMM_EXEC__W 1
11374#define B_CE_REG_FR_COMM_EXEC__M 0x1
11375
11376#define B_CE_REG_FR_TREAL00__A 0x1820010
11377#define B_CE_REG_FR_TREAL00__W 11
11378#define B_CE_REG_FR_TREAL00__M 0x7FF
11379#define B_CE_REG_FR_TREAL00_INIT 0x52
11380
11381
11382#define B_CE_REG_FR_TIMAG00__A 0x1820011
11383#define B_CE_REG_FR_TIMAG00__W 11
11384#define B_CE_REG_FR_TIMAG00__M 0x7FF
11385#define B_CE_REG_FR_TIMAG00_INIT 0x0
11386
11387
11388#define B_CE_REG_FR_TREAL01__A 0x1820012
11389#define B_CE_REG_FR_TREAL01__W 11
11390#define B_CE_REG_FR_TREAL01__M 0x7FF
11391#define B_CE_REG_FR_TREAL01_INIT 0x52
11392
11393
11394#define B_CE_REG_FR_TIMAG01__A 0x1820013
11395#define B_CE_REG_FR_TIMAG01__W 11
11396#define B_CE_REG_FR_TIMAG01__M 0x7FF
11397#define B_CE_REG_FR_TIMAG01_INIT 0x0
11398
11399
11400#define B_CE_REG_FR_TREAL02__A 0x1820014
11401#define B_CE_REG_FR_TREAL02__W 11
11402#define B_CE_REG_FR_TREAL02__M 0x7FF
11403#define B_CE_REG_FR_TREAL02_INIT 0x52
11404
11405
11406#define B_CE_REG_FR_TIMAG02__A 0x1820015
11407#define B_CE_REG_FR_TIMAG02__W 11
11408#define B_CE_REG_FR_TIMAG02__M 0x7FF
11409#define B_CE_REG_FR_TIMAG02_INIT 0x0
11410
11411
11412#define B_CE_REG_FR_TREAL03__A 0x1820016
11413#define B_CE_REG_FR_TREAL03__W 11
11414#define B_CE_REG_FR_TREAL03__M 0x7FF
11415#define B_CE_REG_FR_TREAL03_INIT 0x52
11416
11417
11418#define B_CE_REG_FR_TIMAG03__A 0x1820017
11419#define B_CE_REG_FR_TIMAG03__W 11
11420#define B_CE_REG_FR_TIMAG03__M 0x7FF
11421#define B_CE_REG_FR_TIMAG03_INIT 0x0
11422
11423
11424#define B_CE_REG_FR_TREAL04__A 0x1820018
11425#define B_CE_REG_FR_TREAL04__W 11
11426#define B_CE_REG_FR_TREAL04__M 0x7FF
11427#define B_CE_REG_FR_TREAL04_INIT 0x52
11428
11429
11430#define B_CE_REG_FR_TIMAG04__A 0x1820019
11431#define B_CE_REG_FR_TIMAG04__W 11
11432#define B_CE_REG_FR_TIMAG04__M 0x7FF
11433#define B_CE_REG_FR_TIMAG04_INIT 0x0
11434
11435
11436#define B_CE_REG_FR_TREAL05__A 0x182001A
11437#define B_CE_REG_FR_TREAL05__W 11
11438#define B_CE_REG_FR_TREAL05__M 0x7FF
11439#define B_CE_REG_FR_TREAL05_INIT 0x52
11440
11441
11442#define B_CE_REG_FR_TIMAG05__A 0x182001B
11443#define B_CE_REG_FR_TIMAG05__W 11
11444#define B_CE_REG_FR_TIMAG05__M 0x7FF
11445#define B_CE_REG_FR_TIMAG05_INIT 0x0
11446
11447
11448#define B_CE_REG_FR_TREAL06__A 0x182001C
11449#define B_CE_REG_FR_TREAL06__W 11
11450#define B_CE_REG_FR_TREAL06__M 0x7FF
11451#define B_CE_REG_FR_TREAL06_INIT 0x52
11452
11453
11454#define B_CE_REG_FR_TIMAG06__A 0x182001D
11455#define B_CE_REG_FR_TIMAG06__W 11
11456#define B_CE_REG_FR_TIMAG06__M 0x7FF
11457#define B_CE_REG_FR_TIMAG06_INIT 0x0
11458
11459
11460#define B_CE_REG_FR_TREAL07__A 0x182001E
11461#define B_CE_REG_FR_TREAL07__W 11
11462#define B_CE_REG_FR_TREAL07__M 0x7FF
11463#define B_CE_REG_FR_TREAL07_INIT 0x52
11464
11465
11466#define B_CE_REG_FR_TIMAG07__A 0x182001F
11467#define B_CE_REG_FR_TIMAG07__W 11
11468#define B_CE_REG_FR_TIMAG07__M 0x7FF
11469#define B_CE_REG_FR_TIMAG07_INIT 0x0
11470
11471
11472#define B_CE_REG_FR_TREAL08__A 0x1820020
11473#define B_CE_REG_FR_TREAL08__W 11
11474#define B_CE_REG_FR_TREAL08__M 0x7FF
11475#define B_CE_REG_FR_TREAL08_INIT 0x52
11476
11477
11478#define B_CE_REG_FR_TIMAG08__A 0x1820021
11479#define B_CE_REG_FR_TIMAG08__W 11
11480#define B_CE_REG_FR_TIMAG08__M 0x7FF
11481#define B_CE_REG_FR_TIMAG08_INIT 0x0
11482
11483
11484#define B_CE_REG_FR_TREAL09__A 0x1820022
11485#define B_CE_REG_FR_TREAL09__W 11
11486#define B_CE_REG_FR_TREAL09__M 0x7FF
11487#define B_CE_REG_FR_TREAL09_INIT 0x52
11488
11489
11490#define B_CE_REG_FR_TIMAG09__A 0x1820023
11491#define B_CE_REG_FR_TIMAG09__W 11
11492#define B_CE_REG_FR_TIMAG09__M 0x7FF
11493#define B_CE_REG_FR_TIMAG09_INIT 0x0
11494
11495
11496#define B_CE_REG_FR_TREAL10__A 0x1820024
11497#define B_CE_REG_FR_TREAL10__W 11
11498#define B_CE_REG_FR_TREAL10__M 0x7FF
11499#define B_CE_REG_FR_TREAL10_INIT 0x52
11500
11501
11502#define B_CE_REG_FR_TIMAG10__A 0x1820025
11503#define B_CE_REG_FR_TIMAG10__W 11
11504#define B_CE_REG_FR_TIMAG10__M 0x7FF
11505#define B_CE_REG_FR_TIMAG10_INIT 0x0
11506
11507
11508#define B_CE_REG_FR_TREAL11__A 0x1820026
11509#define B_CE_REG_FR_TREAL11__W 11
11510#define B_CE_REG_FR_TREAL11__M 0x7FF
11511#define B_CE_REG_FR_TREAL11_INIT 0x52
11512
11513
11514#define B_CE_REG_FR_TIMAG11__A 0x1820027
11515#define B_CE_REG_FR_TIMAG11__W 11
11516#define B_CE_REG_FR_TIMAG11__M 0x7FF
11517#define B_CE_REG_FR_TIMAG11_INIT 0x0
11518
11519
11520#define B_CE_REG_FR_MID_TAP__A 0x1820028
11521#define B_CE_REG_FR_MID_TAP__W 11
11522#define B_CE_REG_FR_MID_TAP__M 0x7FF
11523#define B_CE_REG_FR_MID_TAP_INIT 0x51
11524
11525
11526#define B_CE_REG_FR_SQS_G00__A 0x1820029
11527#define B_CE_REG_FR_SQS_G00__W 8
11528#define B_CE_REG_FR_SQS_G00__M 0xFF
11529#define B_CE_REG_FR_SQS_G00_INIT 0xB
11530
11531
11532#define B_CE_REG_FR_SQS_G01__A 0x182002A
11533#define B_CE_REG_FR_SQS_G01__W 8
11534#define B_CE_REG_FR_SQS_G01__M 0xFF
11535#define B_CE_REG_FR_SQS_G01_INIT 0xB
11536
11537
11538#define B_CE_REG_FR_SQS_G02__A 0x182002B
11539#define B_CE_REG_FR_SQS_G02__W 8
11540#define B_CE_REG_FR_SQS_G02__M 0xFF
11541#define B_CE_REG_FR_SQS_G02_INIT 0xB
11542
11543
11544#define B_CE_REG_FR_SQS_G03__A 0x182002C
11545#define B_CE_REG_FR_SQS_G03__W 8
11546#define B_CE_REG_FR_SQS_G03__M 0xFF
11547#define B_CE_REG_FR_SQS_G03_INIT 0xB
11548
11549
11550#define B_CE_REG_FR_SQS_G04__A 0x182002D
11551#define B_CE_REG_FR_SQS_G04__W 8
11552#define B_CE_REG_FR_SQS_G04__M 0xFF
11553#define B_CE_REG_FR_SQS_G04_INIT 0xB
11554
11555
11556#define B_CE_REG_FR_SQS_G05__A 0x182002E
11557#define B_CE_REG_FR_SQS_G05__W 8
11558#define B_CE_REG_FR_SQS_G05__M 0xFF
11559#define B_CE_REG_FR_SQS_G05_INIT 0xB
11560
11561
11562#define B_CE_REG_FR_SQS_G06__A 0x182002F
11563#define B_CE_REG_FR_SQS_G06__W 8
11564#define B_CE_REG_FR_SQS_G06__M 0xFF
11565#define B_CE_REG_FR_SQS_G06_INIT 0xB
11566
11567
11568#define B_CE_REG_FR_SQS_G07__A 0x1820030
11569#define B_CE_REG_FR_SQS_G07__W 8
11570#define B_CE_REG_FR_SQS_G07__M 0xFF
11571#define B_CE_REG_FR_SQS_G07_INIT 0xB
11572
11573
11574#define B_CE_REG_FR_SQS_G08__A 0x1820031
11575#define B_CE_REG_FR_SQS_G08__W 8
11576#define B_CE_REG_FR_SQS_G08__M 0xFF
11577#define B_CE_REG_FR_SQS_G08_INIT 0xB
11578
11579
11580#define B_CE_REG_FR_SQS_G09__A 0x1820032
11581#define B_CE_REG_FR_SQS_G09__W 8
11582#define B_CE_REG_FR_SQS_G09__M 0xFF
11583#define B_CE_REG_FR_SQS_G09_INIT 0xB
11584
11585
11586#define B_CE_REG_FR_SQS_G10__A 0x1820033
11587#define B_CE_REG_FR_SQS_G10__W 8
11588#define B_CE_REG_FR_SQS_G10__M 0xFF
11589#define B_CE_REG_FR_SQS_G10_INIT 0xB
11590
11591
11592#define B_CE_REG_FR_SQS_G11__A 0x1820034
11593#define B_CE_REG_FR_SQS_G11__W 8
11594#define B_CE_REG_FR_SQS_G11__M 0xFF
11595#define B_CE_REG_FR_SQS_G11_INIT 0xB
11596
11597
11598#define B_CE_REG_FR_SQS_G12__A 0x1820035
11599#define B_CE_REG_FR_SQS_G12__W 8
11600#define B_CE_REG_FR_SQS_G12__M 0xFF
11601#define B_CE_REG_FR_SQS_G12_INIT 0x5
11602
11603
11604#define B_CE_REG_FR_RIO_G00__A 0x1820036
11605#define B_CE_REG_FR_RIO_G00__W 9
11606#define B_CE_REG_FR_RIO_G00__M 0x1FF
11607#define B_CE_REG_FR_RIO_G00_INIT 0x1FF
11608
11609
11610#define B_CE_REG_FR_RIO_G01__A 0x1820037
11611#define B_CE_REG_FR_RIO_G01__W 9
11612#define B_CE_REG_FR_RIO_G01__M 0x1FF
11613#define B_CE_REG_FR_RIO_G01_INIT 0x190
11614
11615
11616#define B_CE_REG_FR_RIO_G02__A 0x1820038
11617#define B_CE_REG_FR_RIO_G02__W 9
11618#define B_CE_REG_FR_RIO_G02__M 0x1FF
11619#define B_CE_REG_FR_RIO_G02_INIT 0x10B
11620
11621
11622#define B_CE_REG_FR_RIO_G03__A 0x1820039
11623#define B_CE_REG_FR_RIO_G03__W 9
11624#define B_CE_REG_FR_RIO_G03__M 0x1FF
11625#define B_CE_REG_FR_RIO_G03_INIT 0xC8
11626
11627
11628#define B_CE_REG_FR_RIO_G04__A 0x182003A
11629#define B_CE_REG_FR_RIO_G04__W 9
11630#define B_CE_REG_FR_RIO_G04__M 0x1FF
11631#define B_CE_REG_FR_RIO_G04_INIT 0xA0
11632
11633
11634#define B_CE_REG_FR_RIO_G05__A 0x182003B
11635#define B_CE_REG_FR_RIO_G05__W 9
11636#define B_CE_REG_FR_RIO_G05__M 0x1FF
11637#define B_CE_REG_FR_RIO_G05_INIT 0x85
11638
11639
11640#define B_CE_REG_FR_RIO_G06__A 0x182003C
11641#define B_CE_REG_FR_RIO_G06__W 9
11642#define B_CE_REG_FR_RIO_G06__M 0x1FF
11643#define B_CE_REG_FR_RIO_G06_INIT 0x72
11644
11645
11646#define B_CE_REG_FR_RIO_G07__A 0x182003D
11647#define B_CE_REG_FR_RIO_G07__W 9
11648#define B_CE_REG_FR_RIO_G07__M 0x1FF
11649#define B_CE_REG_FR_RIO_G07_INIT 0x64
11650
11651
11652#define B_CE_REG_FR_RIO_G08__A 0x182003E
11653#define B_CE_REG_FR_RIO_G08__W 9
11654#define B_CE_REG_FR_RIO_G08__M 0x1FF
11655#define B_CE_REG_FR_RIO_G08_INIT 0x59
11656
11657
11658#define B_CE_REG_FR_RIO_G09__A 0x182003F
11659#define B_CE_REG_FR_RIO_G09__W 9
11660#define B_CE_REG_FR_RIO_G09__M 0x1FF
11661#define B_CE_REG_FR_RIO_G09_INIT 0x50
11662
11663
11664#define B_CE_REG_FR_RIO_G10__A 0x1820040
11665#define B_CE_REG_FR_RIO_G10__W 9
11666#define B_CE_REG_FR_RIO_G10__M 0x1FF
11667#define B_CE_REG_FR_RIO_G10_INIT 0x49
11668
11669
11670#define B_CE_REG_FR_MODE__A 0x1820041
11671#define B_CE_REG_FR_MODE__W 9
11672#define B_CE_REG_FR_MODE__M 0x1FF
11673
11674#define B_CE_REG_FR_MODE_UPDATE_ENABLE__B 0
11675#define B_CE_REG_FR_MODE_UPDATE_ENABLE__W 1
11676#define B_CE_REG_FR_MODE_UPDATE_ENABLE__M 0x1
11677
11678#define B_CE_REG_FR_MODE_ERROR_SHIFT__B 1
11679#define B_CE_REG_FR_MODE_ERROR_SHIFT__W 1
11680#define B_CE_REG_FR_MODE_ERROR_SHIFT__M 0x2
11681
11682#define B_CE_REG_FR_MODE_NEXP_UPDATE__B 2
11683#define B_CE_REG_FR_MODE_NEXP_UPDATE__W 1
11684#define B_CE_REG_FR_MODE_NEXP_UPDATE__M 0x4
11685
11686#define B_CE_REG_FR_MODE_MANUAL_SHIFT__B 3
11687#define B_CE_REG_FR_MODE_MANUAL_SHIFT__W 1
11688#define B_CE_REG_FR_MODE_MANUAL_SHIFT__M 0x8
11689
11690#define B_CE_REG_FR_MODE_SQUASH_MODE__B 4
11691#define B_CE_REG_FR_MODE_SQUASH_MODE__W 1
11692#define B_CE_REG_FR_MODE_SQUASH_MODE__M 0x10
11693
11694#define B_CE_REG_FR_MODE_UPDATE_MODE__B 5
11695#define B_CE_REG_FR_MODE_UPDATE_MODE__W 1
11696#define B_CE_REG_FR_MODE_UPDATE_MODE__M 0x20
11697
11698#define B_CE_REG_FR_MODE_MID_MODE__B 6
11699#define B_CE_REG_FR_MODE_MID_MODE__W 1
11700#define B_CE_REG_FR_MODE_MID_MODE__M 0x40
11701
11702#define B_CE_REG_FR_MODE_NOISE_MODE__B 7
11703#define B_CE_REG_FR_MODE_NOISE_MODE__W 1
11704#define B_CE_REG_FR_MODE_NOISE_MODE__M 0x80
11705
11706#define B_CE_REG_FR_MODE_NOTCH_MODE__B 8
11707#define B_CE_REG_FR_MODE_NOTCH_MODE__W 1
11708#define B_CE_REG_FR_MODE_NOTCH_MODE__M 0x100
11709#define B_CE_REG_FR_MODE_INIT 0xDE
11710
11711
11712#define B_CE_REG_FR_SQS_TRH__A 0x1820042
11713#define B_CE_REG_FR_SQS_TRH__W 8
11714#define B_CE_REG_FR_SQS_TRH__M 0xFF
11715#define B_CE_REG_FR_SQS_TRH_INIT 0x80
11716
11717
11718#define B_CE_REG_FR_RIO_GAIN__A 0x1820043
11719#define B_CE_REG_FR_RIO_GAIN__W 3
11720#define B_CE_REG_FR_RIO_GAIN__M 0x7
11721#define B_CE_REG_FR_RIO_GAIN_INIT 0x2
11722
11723
11724#define B_CE_REG_FR_BYPASS__A 0x1820044
11725#define B_CE_REG_FR_BYPASS__W 10
11726#define B_CE_REG_FR_BYPASS__M 0x3FF
11727
11728#define B_CE_REG_FR_BYPASS_RUN_IN__B 0
11729#define B_CE_REG_FR_BYPASS_RUN_IN__W 4
11730#define B_CE_REG_FR_BYPASS_RUN_IN__M 0xF
11731
11732#define B_CE_REG_FR_BYPASS_RUN_SEMI_IN__B 4
11733#define B_CE_REG_FR_BYPASS_RUN_SEMI_IN__W 5
11734#define B_CE_REG_FR_BYPASS_RUN_SEMI_IN__M 0x1F0
11735
11736#define B_CE_REG_FR_BYPASS_TOTAL__B 9
11737#define B_CE_REG_FR_BYPASS_TOTAL__W 1
11738#define B_CE_REG_FR_BYPASS_TOTAL__M 0x200
11739#define B_CE_REG_FR_BYPASS_INIT 0x13B
11740
11741
11742#define B_CE_REG_FR_PM_SET__A 0x1820045
11743#define B_CE_REG_FR_PM_SET__W 4
11744#define B_CE_REG_FR_PM_SET__M 0xF
11745#define B_CE_REG_FR_PM_SET_INIT 0x4
11746
11747
11748#define B_CE_REG_FR_ERR_SH__A 0x1820046
11749#define B_CE_REG_FR_ERR_SH__W 4
11750#define B_CE_REG_FR_ERR_SH__M 0xF
11751#define B_CE_REG_FR_ERR_SH_INIT 0x4
11752
11753
11754#define B_CE_REG_FR_MAN_SH__A 0x1820047
11755#define B_CE_REG_FR_MAN_SH__W 4
11756#define B_CE_REG_FR_MAN_SH__M 0xF
11757#define B_CE_REG_FR_MAN_SH_INIT 0x7
11758
11759
11760#define B_CE_REG_FR_TAP_SH__A 0x1820048
11761#define B_CE_REG_FR_TAP_SH__W 3
11762#define B_CE_REG_FR_TAP_SH__M 0x7
11763#define B_CE_REG_FR_TAP_SH_INIT 0x3
11764
11765
11766#define B_CE_REG_FR_CLIP__A 0x1820049
11767#define B_CE_REG_FR_CLIP__W 9
11768#define B_CE_REG_FR_CLIP__M 0x1FF
11769#define B_CE_REG_FR_CLIP_INIT 0x49
11770
11771
11772#define B_CE_REG_FR_LEAK_UPD__A 0x182004A
11773#define B_CE_REG_FR_LEAK_UPD__W 3
11774#define B_CE_REG_FR_LEAK_UPD__M 0x7
11775#define B_CE_REG_FR_LEAK_UPD_INIT 0x1
11776
11777
11778#define B_CE_REG_FR_LEAK_SH__A 0x182004B
11779#define B_CE_REG_FR_LEAK_SH__W 3
11780#define B_CE_REG_FR_LEAK_SH__M 0x7
11781#define B_CE_REG_FR_LEAK_SH_INIT 0x1
11782
11783
11784
11785#define B_CE_PB_RAM__A 0x1830000
11786
11787
11788
11789#define B_CE_NE_RAM__A 0x1840000
11790
11791
11792
11793
11794
11795#define B_EQ_SID 0xE
11796
11797
11798
11799
11800
11801#define B_EQ_COMM_EXEC__A 0x1C00000
11802#define B_EQ_COMM_EXEC__W 3
11803#define B_EQ_COMM_EXEC__M 0x7
11804#define B_EQ_COMM_EXEC_CTL__B 0
11805#define B_EQ_COMM_EXEC_CTL__W 3
11806#define B_EQ_COMM_EXEC_CTL__M 0x7
11807#define B_EQ_COMM_EXEC_CTL_STOP 0x0
11808#define B_EQ_COMM_EXEC_CTL_ACTIVE 0x1
11809#define B_EQ_COMM_EXEC_CTL_HOLD 0x2
11810#define B_EQ_COMM_EXEC_CTL_STEP 0x3
11811#define B_EQ_COMM_EXEC_CTL_BYPASS_STOP 0x4
11812#define B_EQ_COMM_EXEC_CTL_BYPASS_HOLD 0x6
11813
11814#define B_EQ_COMM_STATE__A 0x1C00001
11815#define B_EQ_COMM_STATE__W 16
11816#define B_EQ_COMM_STATE__M 0xFFFF
11817#define B_EQ_COMM_MB__A 0x1C00002
11818#define B_EQ_COMM_MB__W 16
11819#define B_EQ_COMM_MB__M 0xFFFF
11820#define B_EQ_COMM_SERVICE0__A 0x1C00003
11821#define B_EQ_COMM_SERVICE0__W 16
11822#define B_EQ_COMM_SERVICE0__M 0xFFFF
11823#define B_EQ_COMM_SERVICE1__A 0x1C00004
11824#define B_EQ_COMM_SERVICE1__W 16
11825#define B_EQ_COMM_SERVICE1__M 0xFFFF
11826#define B_EQ_COMM_INT_STA__A 0x1C00007
11827#define B_EQ_COMM_INT_STA__W 16
11828#define B_EQ_COMM_INT_STA__M 0xFFFF
11829#define B_EQ_COMM_INT_MSK__A 0x1C00008
11830#define B_EQ_COMM_INT_MSK__W 16
11831#define B_EQ_COMM_INT_MSK__M 0xFFFF
11832
11833
11834
11835
11836
11837
11838#define B_EQ_REG_COMM_EXEC__A 0x1C10000
11839#define B_EQ_REG_COMM_EXEC__W 3
11840#define B_EQ_REG_COMM_EXEC__M 0x7
11841#define B_EQ_REG_COMM_EXEC_CTL__B 0
11842#define B_EQ_REG_COMM_EXEC_CTL__W 3
11843#define B_EQ_REG_COMM_EXEC_CTL__M 0x7
11844#define B_EQ_REG_COMM_EXEC_CTL_STOP 0x0
11845#define B_EQ_REG_COMM_EXEC_CTL_ACTIVE 0x1
11846#define B_EQ_REG_COMM_EXEC_CTL_HOLD 0x2
11847#define B_EQ_REG_COMM_EXEC_CTL_STEP 0x3
11848
11849#define B_EQ_REG_COMM_STATE__A 0x1C10001
11850#define B_EQ_REG_COMM_STATE__W 4
11851#define B_EQ_REG_COMM_STATE__M 0xF
11852
11853#define B_EQ_REG_COMM_MB__A 0x1C10002
11854#define B_EQ_REG_COMM_MB__W 6
11855#define B_EQ_REG_COMM_MB__M 0x3F
11856#define B_EQ_REG_COMM_MB_CTR__B 0
11857#define B_EQ_REG_COMM_MB_CTR__W 1
11858#define B_EQ_REG_COMM_MB_CTR__M 0x1
11859#define B_EQ_REG_COMM_MB_CTR_OFF 0x0
11860#define B_EQ_REG_COMM_MB_CTR_ON 0x1
11861#define B_EQ_REG_COMM_MB_OBS__B 1
11862#define B_EQ_REG_COMM_MB_OBS__W 1
11863#define B_EQ_REG_COMM_MB_OBS__M 0x2
11864#define B_EQ_REG_COMM_MB_OBS_OFF 0x0
11865#define B_EQ_REG_COMM_MB_OBS_ON 0x2
11866#define B_EQ_REG_COMM_MB_CTR_MUX__B 2
11867#define B_EQ_REG_COMM_MB_CTR_MUX__W 2
11868#define B_EQ_REG_COMM_MB_CTR_MUX__M 0xC
11869#define B_EQ_REG_COMM_MB_CTR_MUX_EQ_OT 0x0
11870#define B_EQ_REG_COMM_MB_CTR_MUX_EQ_RC 0x4
11871#define B_EQ_REG_COMM_MB_CTR_MUX_EQ_IS 0x8
11872#define B_EQ_REG_COMM_MB_OBS_MUX__B 4
11873#define B_EQ_REG_COMM_MB_OBS_MUX__W 2
11874#define B_EQ_REG_COMM_MB_OBS_MUX__M 0x30
11875#define B_EQ_REG_COMM_MB_OBS_MUX_EQ_OT 0x0
11876#define B_EQ_REG_COMM_MB_OBS_MUX_EQ_RC 0x10
11877#define B_EQ_REG_COMM_MB_OBS_MUX_EQ_IS 0x20
11878#define B_EQ_REG_COMM_MB_OBS_MUX_EQ_SN 0x30
11879
11880
11881#define B_EQ_REG_COMM_SERVICE0__A 0x1C10003
11882#define B_EQ_REG_COMM_SERVICE0__W 10
11883#define B_EQ_REG_COMM_SERVICE0__M 0x3FF
11884
11885#define B_EQ_REG_COMM_SERVICE1__A 0x1C10004
11886#define B_EQ_REG_COMM_SERVICE1__W 11
11887#define B_EQ_REG_COMM_SERVICE1__M 0x7FF
11888
11889#define B_EQ_REG_COMM_INT_STA__A 0x1C10007
11890#define B_EQ_REG_COMM_INT_STA__W 2
11891#define B_EQ_REG_COMM_INT_STA__M 0x3
11892#define B_EQ_REG_COMM_INT_STA_TPS_RDY__B 0
11893#define B_EQ_REG_COMM_INT_STA_TPS_RDY__W 1
11894#define B_EQ_REG_COMM_INT_STA_TPS_RDY__M 0x1
11895#define B_EQ_REG_COMM_INT_STA_ERR_RDY__B 1
11896#define B_EQ_REG_COMM_INT_STA_ERR_RDY__W 1
11897#define B_EQ_REG_COMM_INT_STA_ERR_RDY__M 0x2
11898
11899
11900#define B_EQ_REG_COMM_INT_MSK__A 0x1C10008
11901#define B_EQ_REG_COMM_INT_MSK__W 2
11902#define B_EQ_REG_COMM_INT_MSK__M 0x3
11903#define B_EQ_REG_COMM_INT_MSK_TPS_RDY__B 0
11904#define B_EQ_REG_COMM_INT_MSK_TPS_RDY__W 1
11905#define B_EQ_REG_COMM_INT_MSK_TPS_RDY__M 0x1
11906#define B_EQ_REG_COMM_INT_MSK_MER_RDY__B 1
11907#define B_EQ_REG_COMM_INT_MSK_MER_RDY__W 1
11908#define B_EQ_REG_COMM_INT_MSK_MER_RDY__M 0x2
11909
11910
11911#define B_EQ_REG_IS_MODE__A 0x1C10014
11912#define B_EQ_REG_IS_MODE__W 4
11913#define B_EQ_REG_IS_MODE__M 0xF
11914#define B_EQ_REG_IS_MODE_INIT 0x0
11915
11916#define B_EQ_REG_IS_MODE_LIM_EXP_SEL__B 0
11917#define B_EQ_REG_IS_MODE_LIM_EXP_SEL__W 1
11918#define B_EQ_REG_IS_MODE_LIM_EXP_SEL__M 0x1
11919#define B_EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_MAX 0x0
11920#define B_EQ_REG_IS_MODE_LIM_EXP_SEL_EXP_SEL_ZER 0x1
11921
11922#define B_EQ_REG_IS_MODE_LIM_CLP_SEL__B 1
11923#define B_EQ_REG_IS_MODE_LIM_CLP_SEL__W 1
11924#define B_EQ_REG_IS_MODE_LIM_CLP_SEL__M 0x2
11925#define B_EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_ONE 0x0
11926#define B_EQ_REG_IS_MODE_LIM_CLP_SEL_CLP_SEL_TWO 0x2
11927
11928
11929#define B_EQ_REG_IS_GAIN_MAN__A 0x1C10015
11930#define B_EQ_REG_IS_GAIN_MAN__W 10
11931#define B_EQ_REG_IS_GAIN_MAN__M 0x3FF
11932#define B_EQ_REG_IS_GAIN_MAN_INIT 0x114
11933
11934
11935#define B_EQ_REG_IS_GAIN_EXP__A 0x1C10016
11936#define B_EQ_REG_IS_GAIN_EXP__W 5
11937#define B_EQ_REG_IS_GAIN_EXP__M 0x1F
11938#define B_EQ_REG_IS_GAIN_EXP_INIT 0x5
11939
11940
11941#define B_EQ_REG_IS_CLIP_EXP__A 0x1C10017
11942#define B_EQ_REG_IS_CLIP_EXP__W 5
11943#define B_EQ_REG_IS_CLIP_EXP__M 0x1F
11944#define B_EQ_REG_IS_CLIP_EXP_INIT 0x10
11945
11946
11947#define B_EQ_REG_DV_MODE__A 0x1C1001E
11948#define B_EQ_REG_DV_MODE__W 4
11949#define B_EQ_REG_DV_MODE__M 0xF
11950#define B_EQ_REG_DV_MODE_INIT 0xF
11951
11952#define B_EQ_REG_DV_MODE_CLP_CNT_EVR__B 0
11953#define B_EQ_REG_DV_MODE_CLP_CNT_EVR__W 1
11954#define B_EQ_REG_DV_MODE_CLP_CNT_EVR__M 0x1
11955#define B_EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_DIS 0x0
11956#define B_EQ_REG_DV_MODE_CLP_CNT_EVR_CLP_REA_ENA 0x1
11957
11958#define B_EQ_REG_DV_MODE_CLP_CNT_EVI__B 1
11959#define B_EQ_REG_DV_MODE_CLP_CNT_EVI__W 1
11960#define B_EQ_REG_DV_MODE_CLP_CNT_EVI__M 0x2
11961#define B_EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_DIS 0x0
11962#define B_EQ_REG_DV_MODE_CLP_CNT_EVI_CLP_IMA_ENA 0x2
11963
11964#define B_EQ_REG_DV_MODE_CLP_REA_ENA__B 2
11965#define B_EQ_REG_DV_MODE_CLP_REA_ENA__W 1
11966#define B_EQ_REG_DV_MODE_CLP_REA_ENA__M 0x4
11967#define B_EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_DIS 0x0
11968#define B_EQ_REG_DV_MODE_CLP_REA_ENA_CLP_REA_ENA 0x4
11969
11970#define B_EQ_REG_DV_MODE_CLP_IMA_ENA__B 3
11971#define B_EQ_REG_DV_MODE_CLP_IMA_ENA__W 1
11972#define B_EQ_REG_DV_MODE_CLP_IMA_ENA__M 0x8
11973#define B_EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_DIS 0x0
11974#define B_EQ_REG_DV_MODE_CLP_IMA_ENA_CLP_IMA_ENA 0x8
11975
11976
11977#define B_EQ_REG_DV_POS_CLIP_DAT__A 0x1C1001F
11978#define B_EQ_REG_DV_POS_CLIP_DAT__W 16
11979#define B_EQ_REG_DV_POS_CLIP_DAT__M 0xFFFF
11980
11981#define B_EQ_REG_SN_MODE__A 0x1C10028
11982#define B_EQ_REG_SN_MODE__W 8
11983#define B_EQ_REG_SN_MODE__M 0xFF
11984#define B_EQ_REG_SN_MODE_INIT 0x18
11985
11986#define B_EQ_REG_SN_MODE_MODE_0__B 0
11987#define B_EQ_REG_SN_MODE_MODE_0__W 1
11988#define B_EQ_REG_SN_MODE_MODE_0__M 0x1
11989#define B_EQ_REG_SN_MODE_MODE_0_DISABLE 0x0
11990#define B_EQ_REG_SN_MODE_MODE_0_ENABLE 0x1
11991
11992#define B_EQ_REG_SN_MODE_MODE_1__B 1
11993#define B_EQ_REG_SN_MODE_MODE_1__W 1
11994#define B_EQ_REG_SN_MODE_MODE_1__M 0x2
11995#define B_EQ_REG_SN_MODE_MODE_1_DISABLE 0x0
11996#define B_EQ_REG_SN_MODE_MODE_1_ENABLE 0x2
11997
11998#define B_EQ_REG_SN_MODE_MODE_2__B 2
11999#define B_EQ_REG_SN_MODE_MODE_2__W 1
12000#define B_EQ_REG_SN_MODE_MODE_2__M 0x4
12001#define B_EQ_REG_SN_MODE_MODE_2_DISABLE 0x0
12002#define B_EQ_REG_SN_MODE_MODE_2_ENABLE 0x4
12003
12004#define B_EQ_REG_SN_MODE_MODE_3__B 3
12005#define B_EQ_REG_SN_MODE_MODE_3__W 1
12006#define B_EQ_REG_SN_MODE_MODE_3__M 0x8
12007#define B_EQ_REG_SN_MODE_MODE_3_DISABLE 0x0
12008#define B_EQ_REG_SN_MODE_MODE_3_ENABLE 0x8
12009
12010#define B_EQ_REG_SN_MODE_MODE_4__B 4
12011#define B_EQ_REG_SN_MODE_MODE_4__W 1
12012#define B_EQ_REG_SN_MODE_MODE_4__M 0x10
12013#define B_EQ_REG_SN_MODE_MODE_4_DISABLE 0x0
12014#define B_EQ_REG_SN_MODE_MODE_4_ENABLE 0x10
12015
12016#define B_EQ_REG_SN_MODE_MODE_5__B 5
12017#define B_EQ_REG_SN_MODE_MODE_5__W 1
12018#define B_EQ_REG_SN_MODE_MODE_5__M 0x20
12019#define B_EQ_REG_SN_MODE_MODE_5_DISABLE 0x0
12020#define B_EQ_REG_SN_MODE_MODE_5_ENABLE 0x20
12021
12022#define B_EQ_REG_SN_MODE_MODE_6__B 6
12023#define B_EQ_REG_SN_MODE_MODE_6__W 1
12024#define B_EQ_REG_SN_MODE_MODE_6__M 0x40
12025#define B_EQ_REG_SN_MODE_MODE_6_DYNAMIC 0x0
12026#define B_EQ_REG_SN_MODE_MODE_6_STATIC 0x40
12027
12028#define B_EQ_REG_SN_MODE_MODE_7__B 7
12029#define B_EQ_REG_SN_MODE_MODE_7__W 1
12030#define B_EQ_REG_SN_MODE_MODE_7__M 0x80
12031#define B_EQ_REG_SN_MODE_MODE_7_DYNAMIC 0x0
12032#define B_EQ_REG_SN_MODE_MODE_7_STATIC 0x80
12033
12034
12035#define B_EQ_REG_SN_PFIX__A 0x1C10029
12036#define B_EQ_REG_SN_PFIX__W 8
12037#define B_EQ_REG_SN_PFIX__M 0xFF
12038#define B_EQ_REG_SN_PFIX_INIT 0x0
12039
12040
12041#define B_EQ_REG_SN_CEGAIN__A 0x1C1002A
12042#define B_EQ_REG_SN_CEGAIN__W 8
12043#define B_EQ_REG_SN_CEGAIN__M 0xFF
12044#define B_EQ_REG_SN_CEGAIN_INIT 0x30
12045
12046
12047#define B_EQ_REG_SN_OFFSET__A 0x1C1002B
12048#define B_EQ_REG_SN_OFFSET__W 6
12049#define B_EQ_REG_SN_OFFSET__M 0x3F
12050#define B_EQ_REG_SN_OFFSET_INIT 0x39
12051
12052
12053#define B_EQ_REG_SN_NULLIFY__A 0x1C1002C
12054#define B_EQ_REG_SN_NULLIFY__W 6
12055#define B_EQ_REG_SN_NULLIFY__M 0x3F
12056#define B_EQ_REG_SN_NULLIFY_INIT 0x0
12057
12058
12059#define B_EQ_REG_SN_SQUASH__A 0x1C1002D
12060#define B_EQ_REG_SN_SQUASH__W 10
12061#define B_EQ_REG_SN_SQUASH__M 0x3FF
12062#define B_EQ_REG_SN_SQUASH_INIT 0x7
12063
12064#define B_EQ_REG_SN_SQUASH_MAN__B 0
12065#define B_EQ_REG_SN_SQUASH_MAN__W 6
12066#define B_EQ_REG_SN_SQUASH_MAN__M 0x3F
12067
12068#define B_EQ_REG_SN_SQUASH_EXP__B 6
12069#define B_EQ_REG_SN_SQUASH_EXP__W 4
12070#define B_EQ_REG_SN_SQUASH_EXP__M 0x3C0
12071
12072
12073
12074
12075#define B_EQ_REG_RC_SEL_CAR__A 0x1C10032
12076#define B_EQ_REG_RC_SEL_CAR__W 8
12077#define B_EQ_REG_RC_SEL_CAR__M 0xFF
12078#define B_EQ_REG_RC_SEL_CAR_INIT 0x2
12079#define B_EQ_REG_RC_SEL_CAR_DIV__B 0
12080#define B_EQ_REG_RC_SEL_CAR_DIV__W 1
12081#define B_EQ_REG_RC_SEL_CAR_DIV__M 0x1
12082#define B_EQ_REG_RC_SEL_CAR_DIV_OFF 0x0
12083#define B_EQ_REG_RC_SEL_CAR_DIV_ON 0x1
12084
12085#define B_EQ_REG_RC_SEL_CAR_PASS__B 1
12086#define B_EQ_REG_RC_SEL_CAR_PASS__W 2
12087#define B_EQ_REG_RC_SEL_CAR_PASS__M 0x6
12088#define B_EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0
12089#define B_EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2
12090#define B_EQ_REG_RC_SEL_CAR_PASS_C_DRI 0x4
12091#define B_EQ_REG_RC_SEL_CAR_PASS_D_CC 0x6
12092
12093#define B_EQ_REG_RC_SEL_CAR_LOCAL__B 3
12094#define B_EQ_REG_RC_SEL_CAR_LOCAL__W 2
12095#define B_EQ_REG_RC_SEL_CAR_LOCAL__M 0x18
12096#define B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0
12097#define B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8
12098#define B_EQ_REG_RC_SEL_CAR_LOCAL_C_DRI 0x10
12099#define B_EQ_REG_RC_SEL_CAR_LOCAL_D_CC 0x18
12100
12101#define B_EQ_REG_RC_SEL_CAR_MEAS__B 5
12102#define B_EQ_REG_RC_SEL_CAR_MEAS__W 2
12103#define B_EQ_REG_RC_SEL_CAR_MEAS__M 0x60
12104#define B_EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0
12105#define B_EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20
12106#define B_EQ_REG_RC_SEL_CAR_MEAS_C_DRI 0x40
12107#define B_EQ_REG_RC_SEL_CAR_MEAS_D_CC 0x60
12108
12109#define B_EQ_REG_RC_SEL_CAR_FFTMODE__B 7
12110#define B_EQ_REG_RC_SEL_CAR_FFTMODE__W 1
12111#define B_EQ_REG_RC_SEL_CAR_FFTMODE__M 0x80
12112#define B_EQ_REG_RC_SEL_CAR_FFTMODE_2K 0x0
12113#define B_EQ_REG_RC_SEL_CAR_FFTMODE_8K 0x80
12114
12115
12116#define B_EQ_REG_RC_STS__A 0x1C10033
12117#define B_EQ_REG_RC_STS__W 14
12118#define B_EQ_REG_RC_STS__M 0x3FFF
12119
12120#define B_EQ_REG_RC_STS_DIFF__B 0
12121#define B_EQ_REG_RC_STS_DIFF__W 9
12122#define B_EQ_REG_RC_STS_DIFF__M 0x1FF
12123
12124#define B_EQ_REG_RC_STS_FIRST__B 9
12125#define B_EQ_REG_RC_STS_FIRST__W 1
12126#define B_EQ_REG_RC_STS_FIRST__M 0x200
12127#define B_EQ_REG_RC_STS_FIRST_A_CE 0x0
12128#define B_EQ_REG_RC_STS_FIRST_B_DRI 0x200
12129
12130#define B_EQ_REG_RC_STS_SELEC__B 10
12131#define B_EQ_REG_RC_STS_SELEC__W 1
12132#define B_EQ_REG_RC_STS_SELEC__M 0x400
12133#define B_EQ_REG_RC_STS_SELEC_A_CE 0x0
12134#define B_EQ_REG_RC_STS_SELEC_B_DRI 0x400
12135
12136#define B_EQ_REG_RC_STS_OVERFLOW__B 11
12137#define B_EQ_REG_RC_STS_OVERFLOW__W 1
12138#define B_EQ_REG_RC_STS_OVERFLOW__M 0x800
12139#define B_EQ_REG_RC_STS_OVERFLOW_NO 0x0
12140#define B_EQ_REG_RC_STS_OVERFLOW_YES 0x800
12141
12142#define B_EQ_REG_RC_STS_LOC_PRS__B 12
12143#define B_EQ_REG_RC_STS_LOC_PRS__W 1
12144#define B_EQ_REG_RC_STS_LOC_PRS__M 0x1000
12145#define B_EQ_REG_RC_STS_LOC_PRS_NO 0x0
12146#define B_EQ_REG_RC_STS_LOC_PRS_YES 0x1000
12147
12148#define B_EQ_REG_RC_STS_DRI_PRS__B 13
12149#define B_EQ_REG_RC_STS_DRI_PRS__W 1
12150#define B_EQ_REG_RC_STS_DRI_PRS__M 0x2000
12151#define B_EQ_REG_RC_STS_DRI_PRS_NO 0x0
12152#define B_EQ_REG_RC_STS_DRI_PRS_YES 0x2000
12153
12154
12155#define B_EQ_REG_OT_CONST__A 0x1C10046
12156#define B_EQ_REG_OT_CONST__W 2
12157#define B_EQ_REG_OT_CONST__M 0x3
12158#define B_EQ_REG_OT_CONST_INIT 0x2
12159
12160
12161#define B_EQ_REG_OT_ALPHA__A 0x1C10047
12162#define B_EQ_REG_OT_ALPHA__W 2
12163#define B_EQ_REG_OT_ALPHA__M 0x3
12164#define B_EQ_REG_OT_ALPHA_INIT 0x0
12165
12166
12167#define B_EQ_REG_OT_QNT_THRES0__A 0x1C10048
12168#define B_EQ_REG_OT_QNT_THRES0__W 5
12169#define B_EQ_REG_OT_QNT_THRES0__M 0x1F
12170#define B_EQ_REG_OT_QNT_THRES0_INIT 0x1E
12171
12172
12173#define B_EQ_REG_OT_QNT_THRES1__A 0x1C10049
12174#define B_EQ_REG_OT_QNT_THRES1__W 5
12175#define B_EQ_REG_OT_QNT_THRES1__M 0x1F
12176#define B_EQ_REG_OT_QNT_THRES1_INIT 0x1F
12177
12178
12179#define B_EQ_REG_OT_CSI_STEP__A 0x1C1004A
12180#define B_EQ_REG_OT_CSI_STEP__W 4
12181#define B_EQ_REG_OT_CSI_STEP__M 0xF
12182#define B_EQ_REG_OT_CSI_STEP_INIT 0x5
12183
12184
12185#define B_EQ_REG_OT_CSI_OFFSET__A 0x1C1004B
12186#define B_EQ_REG_OT_CSI_OFFSET__W 7
12187#define B_EQ_REG_OT_CSI_OFFSET__M 0x7F
12188#define B_EQ_REG_OT_CSI_OFFSET_INIT 0x5
12189
12190
12191#define B_EQ_REG_OT_CSI_GAIN__A 0x1C1004C
12192#define B_EQ_REG_OT_CSI_GAIN__W 8
12193#define B_EQ_REG_OT_CSI_GAIN__M 0xFF
12194#define B_EQ_REG_OT_CSI_GAIN_INIT 0x2B
12195
12196
12197#define B_EQ_REG_OT_CSI_MEAN__A 0x1C1004D
12198#define B_EQ_REG_OT_CSI_MEAN__W 7
12199#define B_EQ_REG_OT_CSI_MEAN__M 0x7F
12200
12201#define B_EQ_REG_OT_CSI_VARIANCE__A 0x1C1004E
12202#define B_EQ_REG_OT_CSI_VARIANCE__W 7
12203#define B_EQ_REG_OT_CSI_VARIANCE__M 0x7F
12204
12205
12206
12207
12208#define B_EQ_REG_TD_TPS_INIT__A 0x1C10050
12209#define B_EQ_REG_TD_TPS_INIT__W 1
12210#define B_EQ_REG_TD_TPS_INIT__M 0x1
12211#define B_EQ_REG_TD_TPS_INIT_INIT 0x0
12212#define B_EQ_REG_TD_TPS_INIT_POS 0x0
12213#define B_EQ_REG_TD_TPS_INIT_NEG 0x1
12214
12215
12216#define B_EQ_REG_TD_TPS_SYNC__A 0x1C10051
12217#define B_EQ_REG_TD_TPS_SYNC__W 16
12218#define B_EQ_REG_TD_TPS_SYNC__M 0xFFFF
12219#define B_EQ_REG_TD_TPS_SYNC_INIT 0x0
12220#define B_EQ_REG_TD_TPS_SYNC_ODD 0x35EE
12221#define B_EQ_REG_TD_TPS_SYNC_EVEN 0xCA11
12222
12223
12224#define B_EQ_REG_TD_TPS_LEN__A 0x1C10052
12225#define B_EQ_REG_TD_TPS_LEN__W 6
12226#define B_EQ_REG_TD_TPS_LEN__M 0x3F
12227#define B_EQ_REG_TD_TPS_LEN_INIT 0x0
12228#define B_EQ_REG_TD_TPS_LEN_DEF 0x17
12229#define B_EQ_REG_TD_TPS_LEN_ID_SUP 0x1F
12230
12231
12232#define B_EQ_REG_TD_TPS_FRM_NMB__A 0x1C10053
12233#define B_EQ_REG_TD_TPS_FRM_NMB__W 2
12234#define B_EQ_REG_TD_TPS_FRM_NMB__M 0x3
12235#define B_EQ_REG_TD_TPS_FRM_NMB_INIT 0x0
12236#define B_EQ_REG_TD_TPS_FRM_NMB_1 0x0
12237#define B_EQ_REG_TD_TPS_FRM_NMB_2 0x1
12238#define B_EQ_REG_TD_TPS_FRM_NMB_3 0x2
12239#define B_EQ_REG_TD_TPS_FRM_NMB_4 0x3
12240
12241
12242#define B_EQ_REG_TD_TPS_CONST__A 0x1C10054
12243#define B_EQ_REG_TD_TPS_CONST__W 2
12244#define B_EQ_REG_TD_TPS_CONST__M 0x3
12245#define B_EQ_REG_TD_TPS_CONST_INIT 0x0
12246#define B_EQ_REG_TD_TPS_CONST_QPSK 0x0
12247#define B_EQ_REG_TD_TPS_CONST_16QAM 0x1
12248#define B_EQ_REG_TD_TPS_CONST_64QAM 0x2
12249
12250
12251#define B_EQ_REG_TD_TPS_HINFO__A 0x1C10055
12252#define B_EQ_REG_TD_TPS_HINFO__W 3
12253#define B_EQ_REG_TD_TPS_HINFO__M 0x7
12254#define B_EQ_REG_TD_TPS_HINFO_INIT 0x0
12255#define B_EQ_REG_TD_TPS_HINFO_NH 0x0
12256#define B_EQ_REG_TD_TPS_HINFO_H1 0x1
12257#define B_EQ_REG_TD_TPS_HINFO_H2 0x2
12258#define B_EQ_REG_TD_TPS_HINFO_H4 0x3
12259
12260
12261#define B_EQ_REG_TD_TPS_CODE_HP__A 0x1C10056
12262#define B_EQ_REG_TD_TPS_CODE_HP__W 3
12263#define B_EQ_REG_TD_TPS_CODE_HP__M 0x7
12264#define B_EQ_REG_TD_TPS_CODE_HP_INIT 0x0
12265#define B_EQ_REG_TD_TPS_CODE_HP_1_2 0x0
12266#define B_EQ_REG_TD_TPS_CODE_HP_2_3 0x1
12267#define B_EQ_REG_TD_TPS_CODE_HP_3_4 0x2
12268#define B_EQ_REG_TD_TPS_CODE_HP_5_6 0x3
12269#define B_EQ_REG_TD_TPS_CODE_HP_7_8 0x4
12270
12271
12272#define B_EQ_REG_TD_TPS_CODE_LP__A 0x1C10057
12273#define B_EQ_REG_TD_TPS_CODE_LP__W 3
12274#define B_EQ_REG_TD_TPS_CODE_LP__M 0x7
12275#define B_EQ_REG_TD_TPS_CODE_LP_INIT 0x0
12276#define B_EQ_REG_TD_TPS_CODE_LP_1_2 0x0
12277#define B_EQ_REG_TD_TPS_CODE_LP_2_3 0x1
12278#define B_EQ_REG_TD_TPS_CODE_LP_3_4 0x2
12279#define B_EQ_REG_TD_TPS_CODE_LP_5_6 0x3
12280#define B_EQ_REG_TD_TPS_CODE_LP_7_8 0x4
12281
12282
12283#define B_EQ_REG_TD_TPS_GUARD__A 0x1C10058
12284#define B_EQ_REG_TD_TPS_GUARD__W 2
12285#define B_EQ_REG_TD_TPS_GUARD__M 0x3
12286#define B_EQ_REG_TD_TPS_GUARD_INIT 0x0
12287#define B_EQ_REG_TD_TPS_GUARD_32 0x0
12288#define B_EQ_REG_TD_TPS_GUARD_16 0x1
12289#define B_EQ_REG_TD_TPS_GUARD_08 0x2
12290#define B_EQ_REG_TD_TPS_GUARD_04 0x3
12291
12292
12293#define B_EQ_REG_TD_TPS_TR_MODE__A 0x1C10059
12294#define B_EQ_REG_TD_TPS_TR_MODE__W 2
12295#define B_EQ_REG_TD_TPS_TR_MODE__M 0x3
12296#define B_EQ_REG_TD_TPS_TR_MODE_INIT 0x0
12297#define B_EQ_REG_TD_TPS_TR_MODE_2K 0x0
12298#define B_EQ_REG_TD_TPS_TR_MODE_8K 0x1
12299
12300
12301#define B_EQ_REG_TD_TPS_CELL_ID_HI__A 0x1C1005A
12302#define B_EQ_REG_TD_TPS_CELL_ID_HI__W 8
12303#define B_EQ_REG_TD_TPS_CELL_ID_HI__M 0xFF
12304#define B_EQ_REG_TD_TPS_CELL_ID_HI_INIT 0x0
12305
12306
12307#define B_EQ_REG_TD_TPS_CELL_ID_LO__A 0x1C1005B
12308#define B_EQ_REG_TD_TPS_CELL_ID_LO__W 8
12309#define B_EQ_REG_TD_TPS_CELL_ID_LO__M 0xFF
12310#define B_EQ_REG_TD_TPS_CELL_ID_LO_INIT 0x0
12311
12312
12313#define B_EQ_REG_TD_TPS_RSV__A 0x1C1005C
12314#define B_EQ_REG_TD_TPS_RSV__W 6
12315#define B_EQ_REG_TD_TPS_RSV__M 0x3F
12316#define B_EQ_REG_TD_TPS_RSV_INIT 0x0
12317
12318
12319#define B_EQ_REG_TD_TPS_BCH__A 0x1C1005D
12320#define B_EQ_REG_TD_TPS_BCH__W 14
12321#define B_EQ_REG_TD_TPS_BCH__M 0x3FFF
12322#define B_EQ_REG_TD_TPS_BCH_INIT 0x0
12323
12324
12325#define B_EQ_REG_TD_SQR_ERR_I__A 0x1C1005E
12326#define B_EQ_REG_TD_SQR_ERR_I__W 16
12327#define B_EQ_REG_TD_SQR_ERR_I__M 0xFFFF
12328#define B_EQ_REG_TD_SQR_ERR_I_INIT 0x0
12329
12330
12331#define B_EQ_REG_TD_SQR_ERR_Q__A 0x1C1005F
12332#define B_EQ_REG_TD_SQR_ERR_Q__W 16
12333#define B_EQ_REG_TD_SQR_ERR_Q__M 0xFFFF
12334#define B_EQ_REG_TD_SQR_ERR_Q_INIT 0x0
12335
12336
12337#define B_EQ_REG_TD_SQR_ERR_EXP__A 0x1C10060
12338#define B_EQ_REG_TD_SQR_ERR_EXP__W 4
12339#define B_EQ_REG_TD_SQR_ERR_EXP__M 0xF
12340#define B_EQ_REG_TD_SQR_ERR_EXP_INIT 0x0
12341
12342
12343#define B_EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061
12344#define B_EQ_REG_TD_REQ_SMB_CNT__W 16
12345#define B_EQ_REG_TD_REQ_SMB_CNT__M 0xFFFF
12346#define B_EQ_REG_TD_REQ_SMB_CNT_INIT 0x200
12347
12348
12349#define B_EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062
12350#define B_EQ_REG_TD_TPS_PWR_OFS__W 16
12351#define B_EQ_REG_TD_TPS_PWR_OFS__M 0xFFFF
12352#define B_EQ_REG_TD_TPS_PWR_OFS_INIT 0x19F
12353
12354
12355
12356
12357
12358
12359
12360
12361
12362#define B_EC_COMM_EXEC__A 0x2000000
12363#define B_EC_COMM_EXEC__W 3
12364#define B_EC_COMM_EXEC__M 0x7
12365#define B_EC_COMM_EXEC_CTL__B 0
12366#define B_EC_COMM_EXEC_CTL__W 3
12367#define B_EC_COMM_EXEC_CTL__M 0x7
12368#define B_EC_COMM_EXEC_CTL_STOP 0x0
12369#define B_EC_COMM_EXEC_CTL_ACTIVE 0x1
12370#define B_EC_COMM_EXEC_CTL_HOLD 0x2
12371#define B_EC_COMM_EXEC_CTL_STEP 0x3
12372#define B_EC_COMM_EXEC_CTL_BYPASS_STOP 0x4
12373#define B_EC_COMM_EXEC_CTL_BYPASS_HOLD 0x6
12374
12375#define B_EC_COMM_STATE__A 0x2000001
12376#define B_EC_COMM_STATE__W 16
12377#define B_EC_COMM_STATE__M 0xFFFF
12378#define B_EC_COMM_MB__A 0x2000002
12379#define B_EC_COMM_MB__W 16
12380#define B_EC_COMM_MB__M 0xFFFF
12381#define B_EC_COMM_SERVICE0__A 0x2000003
12382#define B_EC_COMM_SERVICE0__W 16
12383#define B_EC_COMM_SERVICE0__M 0xFFFF
12384#define B_EC_COMM_SERVICE1__A 0x2000004
12385#define B_EC_COMM_SERVICE1__W 16
12386#define B_EC_COMM_SERVICE1__M 0xFFFF
12387#define B_EC_COMM_INT_STA__A 0x2000007
12388#define B_EC_COMM_INT_STA__W 16
12389#define B_EC_COMM_INT_STA__M 0xFFFF
12390#define B_EC_COMM_INT_MSK__A 0x2000008
12391#define B_EC_COMM_INT_MSK__W 16
12392#define B_EC_COMM_INT_MSK__M 0xFFFF
12393
12394
12395
12396
12397
12398#define B_EC_SB_SID 0x16
12399
12400
12401
12402
12403
12404#define B_EC_SB_REG_COMM_EXEC__A 0x2010000
12405#define B_EC_SB_REG_COMM_EXEC__W 3
12406#define B_EC_SB_REG_COMM_EXEC__M 0x7
12407#define B_EC_SB_REG_COMM_EXEC_CTL__B 0
12408#define B_EC_SB_REG_COMM_EXEC_CTL__W 3
12409#define B_EC_SB_REG_COMM_EXEC_CTL__M 0x7
12410#define B_EC_SB_REG_COMM_EXEC_CTL_STOP 0x0
12411#define B_EC_SB_REG_COMM_EXEC_CTL_ACTIVE 0x1
12412#define B_EC_SB_REG_COMM_EXEC_CTL_HOLD 0x2
12413
12414#define B_EC_SB_REG_COMM_STATE__A 0x2010001
12415#define B_EC_SB_REG_COMM_STATE__W 4
12416#define B_EC_SB_REG_COMM_STATE__M 0xF
12417#define B_EC_SB_REG_COMM_MB__A 0x2010002
12418#define B_EC_SB_REG_COMM_MB__W 2
12419#define B_EC_SB_REG_COMM_MB__M 0x3
12420#define B_EC_SB_REG_COMM_MB_CTR__B 0
12421#define B_EC_SB_REG_COMM_MB_CTR__W 1
12422#define B_EC_SB_REG_COMM_MB_CTR__M 0x1
12423#define B_EC_SB_REG_COMM_MB_CTR_OFF 0x0
12424#define B_EC_SB_REG_COMM_MB_CTR_ON 0x1
12425#define B_EC_SB_REG_COMM_MB_OBS__B 1
12426#define B_EC_SB_REG_COMM_MB_OBS__W 1
12427#define B_EC_SB_REG_COMM_MB_OBS__M 0x2
12428#define B_EC_SB_REG_COMM_MB_OBS_OFF 0x0
12429#define B_EC_SB_REG_COMM_MB_OBS_ON 0x2
12430
12431
12432#define B_EC_SB_REG_TR_MODE__A 0x2010010
12433#define B_EC_SB_REG_TR_MODE__W 1
12434#define B_EC_SB_REG_TR_MODE__M 0x1
12435#define B_EC_SB_REG_TR_MODE_INIT 0x0
12436#define B_EC_SB_REG_TR_MODE_8K 0x0
12437#define B_EC_SB_REG_TR_MODE_2K 0x1
12438
12439
12440#define B_EC_SB_REG_CONST__A 0x2010011
12441#define B_EC_SB_REG_CONST__W 2
12442#define B_EC_SB_REG_CONST__M 0x3
12443#define B_EC_SB_REG_CONST_INIT 0x2
12444#define B_EC_SB_REG_CONST_QPSK 0x0
12445#define B_EC_SB_REG_CONST_16QAM 0x1
12446#define B_EC_SB_REG_CONST_64QAM 0x2
12447
12448
12449#define B_EC_SB_REG_ALPHA__A 0x2010012
12450#define B_EC_SB_REG_ALPHA__W 3
12451#define B_EC_SB_REG_ALPHA__M 0x7
12452
12453#define B_EC_SB_REG_ALPHA_INIT 0x0
12454
12455#define B_EC_SB_REG_ALPHA_NH 0x0
12456
12457#define B_EC_SB_REG_ALPHA_H1 0x1
12458
12459#define B_EC_SB_REG_ALPHA_H2 0x2
12460
12461#define B_EC_SB_REG_ALPHA_H4 0x3
12462
12463
12464#define B_EC_SB_REG_PRIOR__A 0x2010013
12465#define B_EC_SB_REG_PRIOR__W 1
12466#define B_EC_SB_REG_PRIOR__M 0x1
12467#define B_EC_SB_REG_PRIOR_INIT 0x0
12468#define B_EC_SB_REG_PRIOR_HI 0x0
12469#define B_EC_SB_REG_PRIOR_LO 0x1
12470
12471
12472#define B_EC_SB_REG_CSI_HI__A 0x2010014
12473#define B_EC_SB_REG_CSI_HI__W 5
12474#define B_EC_SB_REG_CSI_HI__M 0x1F
12475#define B_EC_SB_REG_CSI_HI_INIT 0x1F
12476#define B_EC_SB_REG_CSI_HI_MAX 0x1F
12477#define B_EC_SB_REG_CSI_HI_MIN 0x0
12478#define B_EC_SB_REG_CSI_HI_TAG 0x0
12479
12480
12481#define B_EC_SB_REG_CSI_LO__A 0x2010015
12482#define B_EC_SB_REG_CSI_LO__W 5
12483#define B_EC_SB_REG_CSI_LO__M 0x1F
12484#define B_EC_SB_REG_CSI_LO_INIT 0x1E
12485#define B_EC_SB_REG_CSI_LO_MAX 0x1F
12486#define B_EC_SB_REG_CSI_LO_MIN 0x0
12487#define B_EC_SB_REG_CSI_LO_TAG 0x0
12488
12489
12490#define B_EC_SB_REG_SMB_TGL__A 0x2010016
12491#define B_EC_SB_REG_SMB_TGL__W 1
12492#define B_EC_SB_REG_SMB_TGL__M 0x1
12493#define B_EC_SB_REG_SMB_TGL_OFF 0x0
12494#define B_EC_SB_REG_SMB_TGL_ON 0x1
12495#define B_EC_SB_REG_SMB_TGL_INIT 0x1
12496
12497
12498#define B_EC_SB_REG_SNR_HI__A 0x2010017
12499#define B_EC_SB_REG_SNR_HI__W 8
12500#define B_EC_SB_REG_SNR_HI__M 0xFF
12501#define B_EC_SB_REG_SNR_HI_INIT 0x6E
12502#define B_EC_SB_REG_SNR_HI_MAX 0xFF
12503#define B_EC_SB_REG_SNR_HI_MIN 0x0
12504#define B_EC_SB_REG_SNR_HI_TAG 0x0
12505
12506
12507#define B_EC_SB_REG_SNR_MID__A 0x2010018
12508#define B_EC_SB_REG_SNR_MID__W 8
12509#define B_EC_SB_REG_SNR_MID__M 0xFF
12510#define B_EC_SB_REG_SNR_MID_INIT 0x6C
12511#define B_EC_SB_REG_SNR_MID_MAX 0xFF
12512#define B_EC_SB_REG_SNR_MID_MIN 0x0
12513#define B_EC_SB_REG_SNR_MID_TAG 0x0
12514
12515
12516#define B_EC_SB_REG_SNR_LO__A 0x2010019
12517#define B_EC_SB_REG_SNR_LO__W 8
12518#define B_EC_SB_REG_SNR_LO__M 0xFF
12519#define B_EC_SB_REG_SNR_LO_INIT 0x68
12520#define B_EC_SB_REG_SNR_LO_MAX 0xFF
12521#define B_EC_SB_REG_SNR_LO_MIN 0x0
12522#define B_EC_SB_REG_SNR_LO_TAG 0x0
12523
12524
12525#define B_EC_SB_REG_SCALE_MSB__A 0x201001A
12526#define B_EC_SB_REG_SCALE_MSB__W 6
12527#define B_EC_SB_REG_SCALE_MSB__M 0x3F
12528#define B_EC_SB_REG_SCALE_MSB_INIT 0x30
12529#define B_EC_SB_REG_SCALE_MSB_MAX 0x3F
12530
12531
12532#define B_EC_SB_REG_SCALE_BIT2__A 0x201001B
12533#define B_EC_SB_REG_SCALE_BIT2__W 6
12534#define B_EC_SB_REG_SCALE_BIT2__M 0x3F
12535#define B_EC_SB_REG_SCALE_BIT2_INIT 0xC
12536#define B_EC_SB_REG_SCALE_BIT2_MAX 0x3F
12537
12538
12539#define B_EC_SB_REG_SCALE_LSB__A 0x201001C
12540#define B_EC_SB_REG_SCALE_LSB__W 6
12541#define B_EC_SB_REG_SCALE_LSB__M 0x3F
12542#define B_EC_SB_REG_SCALE_LSB_INIT 0x3
12543#define B_EC_SB_REG_SCALE_LSB_MAX 0x3F
12544
12545
12546#define B_EC_SB_REG_CSI_OFS0__A 0x201001D
12547#define B_EC_SB_REG_CSI_OFS0__W 4
12548#define B_EC_SB_REG_CSI_OFS0__M 0xF
12549#define B_EC_SB_REG_CSI_OFS0_INIT 0x4
12550
12551
12552#define B_EC_SB_REG_CSI_OFS1__A 0x201001E
12553#define B_EC_SB_REG_CSI_OFS1__W 4
12554#define B_EC_SB_REG_CSI_OFS1__M 0xF
12555#define B_EC_SB_REG_CSI_OFS1_INIT 0x1
12556
12557
12558#define B_EC_SB_REG_CSI_OFS2__A 0x201001F
12559#define B_EC_SB_REG_CSI_OFS2__W 4
12560#define B_EC_SB_REG_CSI_OFS2__M 0xF
12561#define B_EC_SB_REG_CSI_OFS2_INIT 0x2
12562
12563
12564#define B_EC_SB_REG_MAX0__A 0x2010020
12565#define B_EC_SB_REG_MAX0__W 6
12566#define B_EC_SB_REG_MAX0__M 0x3F
12567#define B_EC_SB_REG_MAX0_INIT 0x3F
12568
12569
12570#define B_EC_SB_REG_MAX1__A 0x2010021
12571#define B_EC_SB_REG_MAX1__W 6
12572#define B_EC_SB_REG_MAX1__M 0x3F
12573#define B_EC_SB_REG_MAX1_INIT 0x3F
12574
12575
12576#define B_EC_SB_REG_MAX2__A 0x2010022
12577#define B_EC_SB_REG_MAX2__W 6
12578#define B_EC_SB_REG_MAX2__M 0x3F
12579#define B_EC_SB_REG_MAX2_INIT 0x3F
12580
12581
12582#define B_EC_SB_REG_CSI_DIS__A 0x2010023
12583#define B_EC_SB_REG_CSI_DIS__W 1
12584#define B_EC_SB_REG_CSI_DIS__M 0x1
12585#define B_EC_SB_REG_CSI_DIS_INIT 0x0
12586
12587
12588
12589#define B_EC_SB_SD_RAM__A 0x2020000
12590
12591
12592
12593#define B_EC_SB_BD0_RAM__A 0x2030000
12594
12595
12596
12597#define B_EC_SB_BD1_RAM__A 0x2040000
12598
12599
12600
12601
12602
12603#define B_EC_VD_SID 0x17
12604
12605
12606
12607
12608
12609#define B_EC_VD_REG_COMM_EXEC__A 0x2090000
12610#define B_EC_VD_REG_COMM_EXEC__W 3
12611#define B_EC_VD_REG_COMM_EXEC__M 0x7
12612#define B_EC_VD_REG_COMM_EXEC_CTL__B 0
12613#define B_EC_VD_REG_COMM_EXEC_CTL__W 3
12614#define B_EC_VD_REG_COMM_EXEC_CTL__M 0x7
12615#define B_EC_VD_REG_COMM_EXEC_CTL_STOP 0x0
12616#define B_EC_VD_REG_COMM_EXEC_CTL_ACTIVE 0x1
12617#define B_EC_VD_REG_COMM_EXEC_CTL_HOLD 0x2
12618
12619#define B_EC_VD_REG_COMM_STATE__A 0x2090001
12620#define B_EC_VD_REG_COMM_STATE__W 4
12621#define B_EC_VD_REG_COMM_STATE__M 0xF
12622#define B_EC_VD_REG_COMM_MB__A 0x2090002
12623#define B_EC_VD_REG_COMM_MB__W 2
12624#define B_EC_VD_REG_COMM_MB__M 0x3
12625#define B_EC_VD_REG_COMM_MB_CTR__B 0
12626#define B_EC_VD_REG_COMM_MB_CTR__W 1
12627#define B_EC_VD_REG_COMM_MB_CTR__M 0x1
12628#define B_EC_VD_REG_COMM_MB_CTR_OFF 0x0
12629#define B_EC_VD_REG_COMM_MB_CTR_ON 0x1
12630#define B_EC_VD_REG_COMM_MB_OBS__B 1
12631#define B_EC_VD_REG_COMM_MB_OBS__W 1
12632#define B_EC_VD_REG_COMM_MB_OBS__M 0x2
12633#define B_EC_VD_REG_COMM_MB_OBS_OFF 0x0
12634#define B_EC_VD_REG_COMM_MB_OBS_ON 0x2
12635
12636#define B_EC_VD_REG_COMM_SERVICE0__A 0x2090003
12637#define B_EC_VD_REG_COMM_SERVICE0__W 16
12638#define B_EC_VD_REG_COMM_SERVICE0__M 0xFFFF
12639#define B_EC_VD_REG_COMM_SERVICE1__A 0x2090004
12640#define B_EC_VD_REG_COMM_SERVICE1__W 16
12641#define B_EC_VD_REG_COMM_SERVICE1__M 0xFFFF
12642#define B_EC_VD_REG_COMM_INT_STA__A 0x2090007
12643#define B_EC_VD_REG_COMM_INT_STA__W 1
12644#define B_EC_VD_REG_COMM_INT_STA__M 0x1
12645#define B_EC_VD_REG_COMM_INT_STA_BER_RDY__B 0
12646#define B_EC_VD_REG_COMM_INT_STA_BER_RDY__W 1
12647#define B_EC_VD_REG_COMM_INT_STA_BER_RDY__M 0x1
12648
12649#define B_EC_VD_REG_COMM_INT_MSK__A 0x2090008
12650#define B_EC_VD_REG_COMM_INT_MSK__W 1
12651#define B_EC_VD_REG_COMM_INT_MSK__M 0x1
12652#define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__B 0
12653#define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__W 1
12654#define B_EC_VD_REG_COMM_INT_MSK_BER_RDY__M 0x1
12655
12656
12657#define B_EC_VD_REG_FORCE__A 0x2090010
12658#define B_EC_VD_REG_FORCE__W 2
12659#define B_EC_VD_REG_FORCE__M 0x3
12660#define B_EC_VD_REG_FORCE_INIT 0x2
12661#define B_EC_VD_REG_FORCE_FREE 0x0
12662#define B_EC_VD_REG_FORCE_PROP 0x1
12663#define B_EC_VD_REG_FORCE_FORCED 0x2
12664#define B_EC_VD_REG_FORCE_FIXED 0x3
12665
12666
12667#define B_EC_VD_REG_SET_CODERATE__A 0x2090011
12668#define B_EC_VD_REG_SET_CODERATE__W 3
12669#define B_EC_VD_REG_SET_CODERATE__M 0x7
12670#define B_EC_VD_REG_SET_CODERATE_INIT 0x1
12671#define B_EC_VD_REG_SET_CODERATE_C1_2 0x0
12672#define B_EC_VD_REG_SET_CODERATE_C2_3 0x1
12673#define B_EC_VD_REG_SET_CODERATE_C3_4 0x2
12674#define B_EC_VD_REG_SET_CODERATE_C5_6 0x3
12675#define B_EC_VD_REG_SET_CODERATE_C7_8 0x4
12676
12677
12678#define B_EC_VD_REG_REQ_SMB_CNT__A 0x2090012
12679#define B_EC_VD_REG_REQ_SMB_CNT__W 16
12680#define B_EC_VD_REG_REQ_SMB_CNT__M 0xFFFF
12681#define B_EC_VD_REG_REQ_SMB_CNT_INIT 0x1
12682
12683
12684#define B_EC_VD_REG_REQ_BIT_CNT__A 0x2090013
12685#define B_EC_VD_REG_REQ_BIT_CNT__W 16
12686#define B_EC_VD_REG_REQ_BIT_CNT__M 0xFFFF
12687#define B_EC_VD_REG_REQ_BIT_CNT_INIT 0xFFF
12688
12689
12690#define B_EC_VD_REG_RLK_ENA__A 0x2090014
12691#define B_EC_VD_REG_RLK_ENA__W 1
12692#define B_EC_VD_REG_RLK_ENA__M 0x1
12693#define B_EC_VD_REG_RLK_ENA_INIT 0x1
12694#define B_EC_VD_REG_RLK_ENA_OFF 0x0
12695#define B_EC_VD_REG_RLK_ENA_ON 0x1
12696
12697
12698#define B_EC_VD_REG_VAL__A 0x2090015
12699#define B_EC_VD_REG_VAL__W 2
12700#define B_EC_VD_REG_VAL__M 0x3
12701#define B_EC_VD_REG_VAL_INIT 0x0
12702#define B_EC_VD_REG_VAL_CODE 0x1
12703#define B_EC_VD_REG_VAL_CNT 0x2
12704
12705
12706#define B_EC_VD_REG_GET_CODERATE__A 0x2090016
12707#define B_EC_VD_REG_GET_CODERATE__W 3
12708#define B_EC_VD_REG_GET_CODERATE__M 0x7
12709#define B_EC_VD_REG_GET_CODERATE_INIT 0x0
12710#define B_EC_VD_REG_GET_CODERATE_C1_2 0x0
12711#define B_EC_VD_REG_GET_CODERATE_C2_3 0x1
12712#define B_EC_VD_REG_GET_CODERATE_C3_4 0x2
12713#define B_EC_VD_REG_GET_CODERATE_C5_6 0x3
12714#define B_EC_VD_REG_GET_CODERATE_C7_8 0x4
12715
12716
12717#define B_EC_VD_REG_ERR_BIT_CNT__A 0x2090017
12718#define B_EC_VD_REG_ERR_BIT_CNT__W 16
12719#define B_EC_VD_REG_ERR_BIT_CNT__M 0xFFFF
12720#define B_EC_VD_REG_ERR_BIT_CNT_INIT 0xFFFF
12721
12722
12723#define B_EC_VD_REG_IN_BIT_CNT__A 0x2090018
12724#define B_EC_VD_REG_IN_BIT_CNT__W 16
12725#define B_EC_VD_REG_IN_BIT_CNT__M 0xFFFF
12726#define B_EC_VD_REG_IN_BIT_CNT_INIT 0x0
12727
12728
12729#define B_EC_VD_REG_STS__A 0x2090019
12730#define B_EC_VD_REG_STS__W 1
12731#define B_EC_VD_REG_STS__M 0x1
12732#define B_EC_VD_REG_STS_INIT 0x0
12733#define B_EC_VD_REG_STS_NO_LOCK 0x0
12734#define B_EC_VD_REG_STS_IN_LOCK 0x1
12735
12736
12737#define B_EC_VD_REG_RLK_CNT__A 0x209001A
12738#define B_EC_VD_REG_RLK_CNT__W 16
12739#define B_EC_VD_REG_RLK_CNT__M 0xFFFF
12740#define B_EC_VD_REG_RLK_CNT_INIT 0x0
12741
12742
12743
12744#define B_EC_VD_TB0_RAM__A 0x20A0000
12745
12746
12747
12748#define B_EC_VD_TB1_RAM__A 0x20B0000
12749
12750
12751
12752#define B_EC_VD_TB2_RAM__A 0x20C0000
12753
12754
12755
12756#define B_EC_VD_TB3_RAM__A 0x20D0000
12757
12758
12759
12760#define B_EC_VD_RE_RAM__A 0x2100000
12761
12762
12763
12764
12765
12766#define B_EC_OD_SID 0x18
12767
12768
12769
12770
12771
12772
12773#define B_EC_OD_REG_COMM_EXEC__A 0x2110000
12774#define B_EC_OD_REG_COMM_EXEC__W 3
12775#define B_EC_OD_REG_COMM_EXEC__M 0x7
12776#define B_EC_OD_REG_COMM_EXEC_CTL__B 0
12777#define B_EC_OD_REG_COMM_EXEC_CTL__W 3
12778#define B_EC_OD_REG_COMM_EXEC_CTL__M 0x7
12779#define B_EC_OD_REG_COMM_EXEC_CTL_STOP 0x0
12780#define B_EC_OD_REG_COMM_EXEC_CTL_ACTIVE 0x1
12781#define B_EC_OD_REG_COMM_EXEC_CTL_HOLD 0x2
12782#define B_EC_OD_REG_COMM_EXEC_CTL_STEP 0x3
12783
12784#define B_EC_OD_REG_COMM_STATE__A 0x2110001
12785#define B_EC_OD_REG_COMM_STATE__W 1
12786#define B_EC_OD_REG_COMM_STATE__M 0x1
12787#define B_EC_OD_REG_COMM_STATE_DI_LOCKED__B 0
12788#define B_EC_OD_REG_COMM_STATE_DI_LOCKED__W 1
12789#define B_EC_OD_REG_COMM_STATE_DI_LOCKED__M 0x1
12790
12791
12792#define B_EC_OD_REG_COMM_MB__A 0x2110002
12793#define B_EC_OD_REG_COMM_MB__W 3
12794#define B_EC_OD_REG_COMM_MB__M 0x7
12795#define B_EC_OD_REG_COMM_MB_CTR__B 0
12796#define B_EC_OD_REG_COMM_MB_CTR__W 1
12797#define B_EC_OD_REG_COMM_MB_CTR__M 0x1
12798#define B_EC_OD_REG_COMM_MB_CTR_OFF 0x0
12799#define B_EC_OD_REG_COMM_MB_CTR_ON 0x1
12800#define B_EC_OD_REG_COMM_MB_OBS__B 1
12801#define B_EC_OD_REG_COMM_MB_OBS__W 1
12802#define B_EC_OD_REG_COMM_MB_OBS__M 0x2
12803#define B_EC_OD_REG_COMM_MB_OBS_OFF 0x0
12804#define B_EC_OD_REG_COMM_MB_OBS_ON 0x2
12805
12806#define B_EC_OD_REG_COMM_SERVICE0__A 0x2110003
12807#define B_EC_OD_REG_COMM_SERVICE0__W 10
12808#define B_EC_OD_REG_COMM_SERVICE0__M 0x3FF
12809#define B_EC_OD_REG_COMM_SERVICE1__A 0x2110004
12810#define B_EC_OD_REG_COMM_SERVICE1__W 11
12811#define B_EC_OD_REG_COMM_SERVICE1__M 0x7FF
12812
12813#define B_EC_OD_REG_COMM_ACTIVATE__A 0x2110005
12814#define B_EC_OD_REG_COMM_ACTIVATE__W 2
12815#define B_EC_OD_REG_COMM_ACTIVATE__M 0x3
12816
12817#define B_EC_OD_REG_COMM_COUNT__A 0x2110006
12818#define B_EC_OD_REG_COMM_COUNT__W 16
12819#define B_EC_OD_REG_COMM_COUNT__M 0xFFFF
12820
12821#define B_EC_OD_REG_COMM_INT_STA__A 0x2110007
12822#define B_EC_OD_REG_COMM_INT_STA__W 2
12823#define B_EC_OD_REG_COMM_INT_STA__M 0x3
12824#define B_EC_OD_REG_COMM_INT_STA_IN_SYNC__B 0
12825#define B_EC_OD_REG_COMM_INT_STA_IN_SYNC__W 1
12826#define B_EC_OD_REG_COMM_INT_STA_IN_SYNC__M 0x1
12827#define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__B 1
12828#define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__W 1
12829#define B_EC_OD_REG_COMM_INT_STA_LOST_SYNC__M 0x2
12830
12831
12832#define B_EC_OD_REG_COMM_INT_MSK__A 0x2110008
12833#define B_EC_OD_REG_COMM_INT_MSK__W 2
12834#define B_EC_OD_REG_COMM_INT_MSK__M 0x3
12835#define B_EC_OD_REG_COMM_INT_MSK_IN_SYNC__B 0
12836#define B_EC_OD_REG_COMM_INT_MSK_IN_SYNC__W 1
12837#define B_EC_OD_REG_COMM_INT_MSK_IN_SYNC__M 0x1
12838#define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__B 1
12839#define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__W 1
12840#define B_EC_OD_REG_COMM_INT_MSK_LOST_SYNC__M 0x2
12841
12842
12843#define B_EC_OD_REG_SYNC__A 0x2110664
12844#define B_EC_OD_REG_SYNC__W 12
12845#define B_EC_OD_REG_SYNC__M 0xFFF
12846#define B_EC_OD_REG_SYNC_NR_SYNC__B 0
12847#define B_EC_OD_REG_SYNC_NR_SYNC__W 5
12848#define B_EC_OD_REG_SYNC_NR_SYNC__M 0x1F
12849#define B_EC_OD_REG_SYNC_IN_SYNC__B 5
12850#define B_EC_OD_REG_SYNC_IN_SYNC__W 4
12851#define B_EC_OD_REG_SYNC_IN_SYNC__M 0x1E0
12852#define B_EC_OD_REG_SYNC_OUT_SYNC__B 9
12853#define B_EC_OD_REG_SYNC_OUT_SYNC__W 3
12854#define B_EC_OD_REG_SYNC_OUT_SYNC__M 0xE00
12855
12856
12857#define B_EC_OD_REG_NOSYNC__A 0x2110004
12858#define B_EC_OD_REG_NOSYNC__W 8
12859#define B_EC_OD_REG_NOSYNC__M 0xFF
12860
12861
12862
12863#define B_EC_OD_DEINT_RAM__A 0x2120000
12864
12865
12866
12867
12868
12869#define B_EC_RS_SID 0x19
12870
12871
12872
12873
12874
12875#define B_EC_RS_REG_COMM_EXEC__A 0x2130000
12876#define B_EC_RS_REG_COMM_EXEC__W 3
12877#define B_EC_RS_REG_COMM_EXEC__M 0x7
12878#define B_EC_RS_REG_COMM_EXEC_CTL__B 0
12879#define B_EC_RS_REG_COMM_EXEC_CTL__W 3
12880#define B_EC_RS_REG_COMM_EXEC_CTL__M 0x7
12881#define B_EC_RS_REG_COMM_EXEC_CTL_STOP 0x0
12882#define B_EC_RS_REG_COMM_EXEC_CTL_ACTIVE 0x1
12883#define B_EC_RS_REG_COMM_EXEC_CTL_HOLD 0x2
12884
12885#define B_EC_RS_REG_COMM_STATE__A 0x2130001
12886#define B_EC_RS_REG_COMM_STATE__W 4
12887#define B_EC_RS_REG_COMM_STATE__M 0xF
12888#define B_EC_RS_REG_COMM_MB__A 0x2130002
12889#define B_EC_RS_REG_COMM_MB__W 2
12890#define B_EC_RS_REG_COMM_MB__M 0x3
12891#define B_EC_RS_REG_COMM_MB_CTR__B 0
12892#define B_EC_RS_REG_COMM_MB_CTR__W 1
12893#define B_EC_RS_REG_COMM_MB_CTR__M 0x1
12894#define B_EC_RS_REG_COMM_MB_CTR_OFF 0x0
12895#define B_EC_RS_REG_COMM_MB_CTR_ON 0x1
12896#define B_EC_RS_REG_COMM_MB_OBS__B 1
12897#define B_EC_RS_REG_COMM_MB_OBS__W 1
12898#define B_EC_RS_REG_COMM_MB_OBS__M 0x2
12899#define B_EC_RS_REG_COMM_MB_OBS_OFF 0x0
12900#define B_EC_RS_REG_COMM_MB_OBS_ON 0x2
12901
12902#define B_EC_RS_REG_COMM_SERVICE0__A 0x2130003
12903#define B_EC_RS_REG_COMM_SERVICE0__W 16
12904#define B_EC_RS_REG_COMM_SERVICE0__M 0xFFFF
12905#define B_EC_RS_REG_COMM_SERVICE1__A 0x2130004
12906#define B_EC_RS_REG_COMM_SERVICE1__W 16
12907#define B_EC_RS_REG_COMM_SERVICE1__M 0xFFFF
12908#define B_EC_RS_REG_COMM_INT_STA__A 0x2130007
12909#define B_EC_RS_REG_COMM_INT_STA__W 1
12910#define B_EC_RS_REG_COMM_INT_STA__M 0x1
12911#define B_EC_RS_REG_COMM_INT_STA_BER_RDY__B 0
12912#define B_EC_RS_REG_COMM_INT_STA_BER_RDY__W 1
12913#define B_EC_RS_REG_COMM_INT_STA_BER_RDY__M 0x1
12914
12915#define B_EC_RS_REG_COMM_INT_MSK__A 0x2130008
12916#define B_EC_RS_REG_COMM_INT_MSK__W 1
12917#define B_EC_RS_REG_COMM_INT_MSK__M 0x1
12918#define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__B 0
12919#define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__W 1
12920#define B_EC_RS_REG_COMM_INT_MSK_BER_RDY__M 0x1
12921
12922
12923#define B_EC_RS_REG_REQ_PCK_CNT__A 0x2130010
12924#define B_EC_RS_REG_REQ_PCK_CNT__W 16
12925#define B_EC_RS_REG_REQ_PCK_CNT__M 0xFFFF
12926#define B_EC_RS_REG_REQ_PCK_CNT_INIT 0x200
12927
12928
12929#define B_EC_RS_REG_VAL__A 0x2130011
12930#define B_EC_RS_REG_VAL__W 1
12931#define B_EC_RS_REG_VAL__M 0x1
12932#define B_EC_RS_REG_VAL_INIT 0x0
12933#define B_EC_RS_REG_VAL_PCK 0x1
12934
12935
12936#define B_EC_RS_REG_ERR_PCK_CNT__A 0x2130012
12937#define B_EC_RS_REG_ERR_PCK_CNT__W 16
12938#define B_EC_RS_REG_ERR_PCK_CNT__M 0xFFFF
12939#define B_EC_RS_REG_ERR_PCK_CNT_INIT 0xFFFF
12940
12941
12942#define B_EC_RS_REG_ERR_SMB_CNT__A 0x2130013
12943#define B_EC_RS_REG_ERR_SMB_CNT__W 16
12944#define B_EC_RS_REG_ERR_SMB_CNT__M 0xFFFF
12945#define B_EC_RS_REG_ERR_SMB_CNT_INIT 0xFFFF
12946
12947
12948#define B_EC_RS_REG_ERR_BIT_CNT__A 0x2130014
12949#define B_EC_RS_REG_ERR_BIT_CNT__W 16
12950#define B_EC_RS_REG_ERR_BIT_CNT__M 0xFFFF
12951#define B_EC_RS_REG_ERR_BIT_CNT_INIT 0xFFFF
12952
12953
12954#define B_EC_RS_REG_IN_PCK_CNT__A 0x2130015
12955#define B_EC_RS_REG_IN_PCK_CNT__W 16
12956#define B_EC_RS_REG_IN_PCK_CNT__M 0xFFFF
12957#define B_EC_RS_REG_IN_PCK_CNT_INIT 0x0
12958
12959
12960
12961#define B_EC_RS_EC_RAM__A 0x2140000
12962
12963
12964
12965
12966
12967#define B_EC_OC_SID 0x1A
12968
12969
12970
12971
12972
12973
12974#define B_EC_OC_REG_COMM_EXEC__A 0x2150000
12975#define B_EC_OC_REG_COMM_EXEC__W 3
12976#define B_EC_OC_REG_COMM_EXEC__M 0x7
12977#define B_EC_OC_REG_COMM_EXEC_CTL__B 0
12978#define B_EC_OC_REG_COMM_EXEC_CTL__W 3
12979#define B_EC_OC_REG_COMM_EXEC_CTL__M 0x7
12980#define B_EC_OC_REG_COMM_EXEC_CTL_STOP 0x0
12981#define B_EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1
12982#define B_EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2
12983#define B_EC_OC_REG_COMM_EXEC_CTL_STEP 0x3
12984
12985#define B_EC_OC_REG_COMM_STATE__A 0x2150001
12986#define B_EC_OC_REG_COMM_STATE__W 4
12987#define B_EC_OC_REG_COMM_STATE__M 0xF
12988
12989#define B_EC_OC_REG_COMM_MB__A 0x2150002
12990#define B_EC_OC_REG_COMM_MB__W 2
12991#define B_EC_OC_REG_COMM_MB__M 0x3
12992#define B_EC_OC_REG_COMM_MB_CTR__B 0
12993#define B_EC_OC_REG_COMM_MB_CTR__W 1
12994#define B_EC_OC_REG_COMM_MB_CTR__M 0x1
12995#define B_EC_OC_REG_COMM_MB_CTR_OFF 0x0
12996#define B_EC_OC_REG_COMM_MB_CTR_ON 0x1
12997#define B_EC_OC_REG_COMM_MB_OBS__B 1
12998#define B_EC_OC_REG_COMM_MB_OBS__W 1
12999#define B_EC_OC_REG_COMM_MB_OBS__M 0x2
13000#define B_EC_OC_REG_COMM_MB_OBS_OFF 0x0
13001#define B_EC_OC_REG_COMM_MB_OBS_ON 0x2
13002
13003
13004#define B_EC_OC_REG_COMM_SERVICE0__A 0x2150003
13005#define B_EC_OC_REG_COMM_SERVICE0__W 10
13006#define B_EC_OC_REG_COMM_SERVICE0__M 0x3FF
13007
13008#define B_EC_OC_REG_COMM_SERVICE1__A 0x2150004
13009#define B_EC_OC_REG_COMM_SERVICE1__W 11
13010#define B_EC_OC_REG_COMM_SERVICE1__M 0x7FF
13011
13012#define B_EC_OC_REG_COMM_INT_STA__A 0x2150007
13013#define B_EC_OC_REG_COMM_INT_STA__W 6
13014#define B_EC_OC_REG_COMM_INT_STA__M 0x3F
13015#define B_EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__B 0
13016#define B_EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__W 1
13017#define B_EC_OC_REG_COMM_INT_STA_MEM_FUL_STS__M 0x1
13018#define B_EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__B 1
13019#define B_EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__W 1
13020#define B_EC_OC_REG_COMM_INT_STA_MEM_EMP_STS__M 0x2
13021#define B_EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__B 2
13022#define B_EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__W 1
13023#define B_EC_OC_REG_COMM_INT_STA_SNC_ISS_STS__M 0x4
13024#define B_EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__B 3
13025#define B_EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__W 1
13026#define B_EC_OC_REG_COMM_INT_STA_SNC_OSS_STS__M 0x8
13027#define B_EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__B 4
13028#define B_EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__W 1
13029#define B_EC_OC_REG_COMM_INT_STA_SNC_NSS_STS__M 0x10
13030#define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__B 5
13031#define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__W 1
13032#define B_EC_OC_REG_COMM_INT_STA_PCK_ERR_UPD__M 0x20
13033
13034
13035#define B_EC_OC_REG_COMM_INT_MSK__A 0x2150008
13036#define B_EC_OC_REG_COMM_INT_MSK__W 6
13037#define B_EC_OC_REG_COMM_INT_MSK__M 0x3F
13038#define B_EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__B 0
13039#define B_EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__W 1
13040#define B_EC_OC_REG_COMM_INT_MSK_MEM_FUL_STS__M 0x1
13041#define B_EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__B 1
13042#define B_EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__W 1
13043#define B_EC_OC_REG_COMM_INT_MSK_MEM_EMP_STS__M 0x2
13044#define B_EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__B 2
13045#define B_EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__W 1
13046#define B_EC_OC_REG_COMM_INT_MSK_SNC_ISS_STS__M 0x4
13047#define B_EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__B 3
13048#define B_EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__W 1
13049#define B_EC_OC_REG_COMM_INT_MSK_SNC_OSS_STS__M 0x8
13050#define B_EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__B 4
13051#define B_EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__W 1
13052#define B_EC_OC_REG_COMM_INT_MSK_SNC_NSS_STS__M 0x10
13053#define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__B 5
13054#define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__W 1
13055#define B_EC_OC_REG_COMM_INT_MSK_PCK_ERR_UPD__M 0x20
13056
13057
13058#define B_EC_OC_REG_OC_MODE_LOP__A 0x2150010
13059#define B_EC_OC_REG_OC_MODE_LOP__W 16
13060#define B_EC_OC_REG_OC_MODE_LOP__M 0xFFFF
13061#define B_EC_OC_REG_OC_MODE_LOP_INIT 0x0
13062
13063#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__B 0
13064#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__W 1
13065#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1
13066#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0
13067#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1
13068
13069#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__B 2
13070#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__W 1
13071#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4
13072#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0
13073#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_DYNAMIC 0x4
13074
13075#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__B 4
13076#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__W 1
13077#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA__M 0x10
13078#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_DISABLE 0x0
13079#define B_EC_OC_REG_OC_MODE_LOP_DAT_PRP_ENA_ENABLE 0x10
13080
13081#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__B 5
13082#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__W 1
13083#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE__M 0x20
13084#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_DISABLE 0x0
13085#define B_EC_OC_REG_OC_MODE_LOP_SNC_LCK_MDE_ENABLE 0x20
13086
13087#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__B 6
13088#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__W 1
13089#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV__M 0x40
13090#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_DISABLE 0x0
13091#define B_EC_OC_REG_OC_MODE_LOP_MPG_BIT_REV_ENABLE 0x40
13092
13093#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__B 7
13094#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__W 1
13095#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80
13096#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_PARALLEL 0x0
13097#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80
13098
13099#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__B 8
13100#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__W 1
13101#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE__M 0x100
13102#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_ENABLE 0x0
13103#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_MDE_DISABLE 0x100
13104
13105#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__B 9
13106#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__W 1
13107#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK__M 0x200
13108#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_STRETCH 0x0
13109#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_CLK_GATE 0x200
13110
13111#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__B 10
13112#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__W 1
13113#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR__M 0x400
13114#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_CONTINOUS 0x0
13115#define B_EC_OC_REG_OC_MODE_LOP_MPG_SER_BUR_BURST 0x400
13116
13117#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__B 11
13118#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__W 1
13119#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC__M 0x800
13120#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_ENABLE 0x0
13121#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_SNC_DISABLE 0x800
13122
13123#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__B 12
13124#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__W 1
13125#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO__M 0x1000
13126#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_ENABLE 0x0
13127#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_RSO_DISABLE 0x1000
13128
13129#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__B 13
13130#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__W 1
13131#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT__M 0x2000
13132#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_ENABLE 0x0
13133#define B_EC_OC_REG_OC_MODE_LOP_MPG_ERR_BIT_DISABLE 0x2000
13134
13135#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__B 14
13136#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__W 1
13137#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS__M 0x4000
13138#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_ENABLE 0x0
13139#define B_EC_OC_REG_OC_MODE_LOP_MPG_SNC_INS_DISABLE 0x4000
13140
13141#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA__B 15
13142#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA__W 1
13143#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA__M 0x8000
13144#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA_ENABLE 0x0
13145#define B_EC_OC_REG_OC_MODE_LOP_DER_ENA_DISABLE 0x8000
13146
13147
13148#define B_EC_OC_REG_OC_MODE_HIP__A 0x2150011
13149#define B_EC_OC_REG_OC_MODE_HIP__W 15
13150#define B_EC_OC_REG_OC_MODE_HIP__M 0x7FFF
13151#define B_EC_OC_REG_OC_MODE_HIP_INIT 0x5
13152
13153#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__B 0
13154#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__W 1
13155#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS__M 0x1
13156#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_OBSERVE 0x0
13157#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_RDS_CONTROL 0x1
13158
13159#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__B 1
13160#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__W 1
13161#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC__M 0x2
13162#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG_SYNC 0x0
13163#define B_EC_OC_REG_OC_MODE_HIP_MPG_SER_SNC_MPEG 0x2
13164
13165#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__B 2
13166#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__W 1
13167#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE__M 0x4
13168#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_OBSERVE 0x0
13169#define B_EC_OC_REG_OC_MODE_HIP_MON_OBS_MDE_CONTROL 0x4
13170
13171#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__B 3
13172#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__W 1
13173#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC__M 0x8
13174#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MONITOR 0x0
13175#define B_EC_OC_REG_OC_MODE_HIP_MON_BUS_SRC_MPEG 0x8
13176
13177#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__B 4
13178#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__W 1
13179#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC__M 0x10
13180#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MPEG 0x0
13181#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10
13182
13183#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__B 5
13184#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__W 1
13185#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE__M 0x20
13186#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_DISABLE 0x0
13187#define B_EC_OC_REG_OC_MODE_HIP_MON_RDC_MDE_ENABLE 0x20
13188
13189#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__B 6
13190#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__W 1
13191#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE__M 0x40
13192#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_ENABLE 0x0
13193#define B_EC_OC_REG_OC_MODE_HIP_DER_SNC_MDE_DISABLE 0x40
13194
13195#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__B 7
13196#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__W 1
13197#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP__M 0x80
13198#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_DISABLE 0x0
13199#define B_EC_OC_REG_OC_MODE_HIP_MPG_CLK_SUP_ENABLE 0x80
13200
13201#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__B 8
13202#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__W 1
13203#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK__M 0x100
13204#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_DISABLE 0x0
13205#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_CLK_ENABLE 0x100
13206
13207#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__B 9
13208#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__W 1
13209#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200
13210#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0
13211#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200
13212
13213#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__B 10
13214#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__W 1
13215#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR__M 0x400
13216#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_DISABLE 0x0
13217#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_ERR_ENABLE 0x400
13218
13219#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__B 11
13220#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__W 1
13221#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT__M 0x800
13222#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_DISABLE 0x0
13223#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_DAT_ENABLE 0x800
13224
13225#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__B 12
13226#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__W 1
13227#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON__M 0x1000
13228#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_ZER 0x0
13229#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MON_SEL_MON 0x1000
13230
13231#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__B 13
13232#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__W 1
13233#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG__M 0x2000
13234#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_ZER 0x0
13235#define B_EC_OC_REG_OC_MODE_HIP_FDB_SEL_MPG_SEL_MPG 0x2000
13236
13237#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF__B 14
13238#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF__W 1
13239#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF__M 0x4000
13240#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF_SEL_ZER 0x0
13241#define B_EC_OC_REG_OC_MODE_HIP_SNC_OFF_SEL_CLC 0x4000
13242
13243
13244#define B_EC_OC_REG_OC_MPG_SIO__A 0x2150012
13245#define B_EC_OC_REG_OC_MPG_SIO__W 12
13246#define B_EC_OC_REG_OC_MPG_SIO__M 0xFFF
13247#define B_EC_OC_REG_OC_MPG_SIO_INIT 0xFFF
13248
13249#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__B 0
13250#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__W 1
13251#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0__M 0x1
13252#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_OUTPUT 0x0
13253#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_0_INPUT 0x1
13254
13255#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__B 1
13256#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__W 1
13257#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1__M 0x2
13258#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_OUTPUT 0x0
13259#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_1_INPUT 0x2
13260
13261#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__B 2
13262#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__W 1
13263#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2__M 0x4
13264#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_OUTPUT 0x0
13265#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_2_INPUT 0x4
13266
13267#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__B 3
13268#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__W 1
13269#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3__M 0x8
13270#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_OUTPUT 0x0
13271#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_3_INPUT 0x8
13272
13273#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__B 4
13274#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__W 1
13275#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4__M 0x10
13276#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_OUTPUT 0x0
13277#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_4_INPUT 0x10
13278
13279#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__B 5
13280#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__W 1
13281#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5__M 0x20
13282#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_OUTPUT 0x0
13283#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_5_INPUT 0x20
13284
13285#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__B 6
13286#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__W 1
13287#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6__M 0x40
13288#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_OUTPUT 0x0
13289#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_6_INPUT 0x40
13290
13291#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__B 7
13292#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__W 1
13293#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7__M 0x80
13294#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_OUTPUT 0x0
13295#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_7_INPUT 0x80
13296
13297#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__B 8
13298#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__W 1
13299#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8__M 0x100
13300#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_OUTPUT 0x0
13301#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_8_INPUT 0x100
13302
13303#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__B 9
13304#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__W 1
13305#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9__M 0x200
13306#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_OUTPUT 0x0
13307#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_9_INPUT 0x200
13308
13309#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__B 10
13310#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__W 1
13311#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10__M 0x400
13312#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_OUTPUT 0x0
13313#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_10_INPUT 0x400
13314
13315#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__B 11
13316#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__W 1
13317#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11__M 0x800
13318#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_OUTPUT 0x0
13319#define B_EC_OC_REG_OC_MPG_SIO_MPG_SIO_11_INPUT 0x800
13320
13321
13322#define B_EC_OC_REG_DTO_INC_LOP__A 0x2150014
13323#define B_EC_OC_REG_DTO_INC_LOP__W 16
13324#define B_EC_OC_REG_DTO_INC_LOP__M 0xFFFF
13325#define B_EC_OC_REG_DTO_INC_LOP_INIT 0x0
13326
13327
13328#define B_EC_OC_REG_DTO_INC_HIP__A 0x2150015
13329#define B_EC_OC_REG_DTO_INC_HIP__W 8
13330#define B_EC_OC_REG_DTO_INC_HIP__M 0xFF
13331#define B_EC_OC_REG_DTO_INC_HIP_INIT 0xC0
13332
13333
13334#define B_EC_OC_REG_SNC_ISC_LVL__A 0x2150016
13335#define B_EC_OC_REG_SNC_ISC_LVL__W 12
13336#define B_EC_OC_REG_SNC_ISC_LVL__M 0xFFF
13337#define B_EC_OC_REG_SNC_ISC_LVL_INIT 0x422
13338
13339#define B_EC_OC_REG_SNC_ISC_LVL_ISC__B 0
13340#define B_EC_OC_REG_SNC_ISC_LVL_ISC__W 4
13341#define B_EC_OC_REG_SNC_ISC_LVL_ISC__M 0xF
13342
13343#define B_EC_OC_REG_SNC_ISC_LVL_OSC__B 4
13344#define B_EC_OC_REG_SNC_ISC_LVL_OSC__W 4
13345#define B_EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0
13346
13347#define B_EC_OC_REG_SNC_ISC_LVL_NSC__B 8
13348#define B_EC_OC_REG_SNC_ISC_LVL_NSC__W 4
13349#define B_EC_OC_REG_SNC_ISC_LVL_NSC__M 0xF00
13350
13351
13352#define B_EC_OC_REG_SNC_NSC_LVL__A 0x2150017
13353#define B_EC_OC_REG_SNC_NSC_LVL__W 8
13354#define B_EC_OC_REG_SNC_NSC_LVL__M 0xFF
13355#define B_EC_OC_REG_SNC_NSC_LVL_INIT 0x0
13356
13357
13358#define B_EC_OC_REG_SNC_SNC_MODE__A 0x2150019
13359#define B_EC_OC_REG_SNC_SNC_MODE__W 2
13360#define B_EC_OC_REG_SNC_SNC_MODE__M 0x3
13361#define B_EC_OC_REG_SNC_SNC_MODE_SEARCH 0x0
13362#define B_EC_OC_REG_SNC_SNC_MODE_TRACK 0x1
13363#define B_EC_OC_REG_SNC_SNC_MODE_LOCK 0x2
13364
13365
13366#define B_EC_OC_REG_SNC_PCK_NMB__A 0x215001A
13367#define B_EC_OC_REG_SNC_PCK_NMB__W 16
13368#define B_EC_OC_REG_SNC_PCK_NMB__M 0xFFFF
13369
13370#define B_EC_OC_REG_SNC_PCK_CNT__A 0x215001B
13371#define B_EC_OC_REG_SNC_PCK_CNT__W 16
13372#define B_EC_OC_REG_SNC_PCK_CNT__M 0xFFFF
13373
13374#define B_EC_OC_REG_SNC_PCK_ERR__A 0x215001C
13375#define B_EC_OC_REG_SNC_PCK_ERR__W 16
13376#define B_EC_OC_REG_SNC_PCK_ERR__M 0xFFFF
13377
13378#define B_EC_OC_REG_TMD_TOP_MODE__A 0x215001D
13379#define B_EC_OC_REG_TMD_TOP_MODE__W 2
13380#define B_EC_OC_REG_TMD_TOP_MODE__M 0x3
13381#define B_EC_OC_REG_TMD_TOP_MODE_INIT 0x3
13382#define B_EC_OC_REG_TMD_TOP_MODE_SELECT_ACT_ACT 0x0
13383#define B_EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_TOP 0x1
13384#define B_EC_OC_REG_TMD_TOP_MODE_SELECT_BOT_BOT 0x2
13385#define B_EC_OC_REG_TMD_TOP_MODE_SELECT_TOP_BOT 0x3
13386
13387
13388#define B_EC_OC_REG_TMD_TOP_CNT__A 0x215001E
13389#define B_EC_OC_REG_TMD_TOP_CNT__W 10
13390#define B_EC_OC_REG_TMD_TOP_CNT__M 0x3FF
13391#define B_EC_OC_REG_TMD_TOP_CNT_INIT 0x1F4
13392
13393
13394#define B_EC_OC_REG_TMD_HIL_MAR__A 0x215001F
13395#define B_EC_OC_REG_TMD_HIL_MAR__W 10
13396#define B_EC_OC_REG_TMD_HIL_MAR__M 0x3FF
13397#define B_EC_OC_REG_TMD_HIL_MAR_INIT 0x3C0
13398
13399
13400#define B_EC_OC_REG_TMD_LOL_MAR__A 0x2150020
13401#define B_EC_OC_REG_TMD_LOL_MAR__W 10
13402#define B_EC_OC_REG_TMD_LOL_MAR__M 0x3FF
13403#define B_EC_OC_REG_TMD_LOL_MAR_INIT 0x40
13404
13405
13406#define B_EC_OC_REG_TMD_CUR_CNT__A 0x2150021
13407#define B_EC_OC_REG_TMD_CUR_CNT__W 4
13408#define B_EC_OC_REG_TMD_CUR_CNT__M 0xF
13409#define B_EC_OC_REG_TMD_CUR_CNT_INIT 0x3
13410
13411
13412#define B_EC_OC_REG_TMD_IUR_CNT__A 0x2150022
13413#define B_EC_OC_REG_TMD_IUR_CNT__W 4
13414#define B_EC_OC_REG_TMD_IUR_CNT__M 0xF
13415#define B_EC_OC_REG_TMD_IUR_CNT_INIT 0x0
13416
13417
13418#define B_EC_OC_REG_AVR_ASH_CNT__A 0x2150023
13419#define B_EC_OC_REG_AVR_ASH_CNT__W 4
13420#define B_EC_OC_REG_AVR_ASH_CNT__M 0xF
13421#define B_EC_OC_REG_AVR_ASH_CNT_INIT 0x6
13422
13423
13424#define B_EC_OC_REG_AVR_BSH_CNT__A 0x2150024
13425#define B_EC_OC_REG_AVR_BSH_CNT__W 4
13426#define B_EC_OC_REG_AVR_BSH_CNT__M 0xF
13427#define B_EC_OC_REG_AVR_BSH_CNT_INIT 0x2
13428
13429
13430#define B_EC_OC_REG_AVR_AVE_LOP__A 0x2150025
13431#define B_EC_OC_REG_AVR_AVE_LOP__W 16
13432#define B_EC_OC_REG_AVR_AVE_LOP__M 0xFFFF
13433
13434#define B_EC_OC_REG_AVR_AVE_HIP__A 0x2150026
13435#define B_EC_OC_REG_AVR_AVE_HIP__W 5
13436#define B_EC_OC_REG_AVR_AVE_HIP__M 0x1F
13437
13438#define B_EC_OC_REG_RCN_MODE__A 0x2150027
13439#define B_EC_OC_REG_RCN_MODE__W 3
13440#define B_EC_OC_REG_RCN_MODE__M 0x7
13441#define B_EC_OC_REG_RCN_MODE_INIT 0x7
13442
13443#define B_EC_OC_REG_RCN_MODE_MODE_0__B 0
13444#define B_EC_OC_REG_RCN_MODE_MODE_0__W 1
13445#define B_EC_OC_REG_RCN_MODE_MODE_0__M 0x1
13446#define B_EC_OC_REG_RCN_MODE_MODE_0_ENABLE 0x0
13447#define B_EC_OC_REG_RCN_MODE_MODE_0_DISABLE 0x1
13448
13449#define B_EC_OC_REG_RCN_MODE_MODE_1__B 1
13450#define B_EC_OC_REG_RCN_MODE_MODE_1__W 1
13451#define B_EC_OC_REG_RCN_MODE_MODE_1__M 0x2
13452#define B_EC_OC_REG_RCN_MODE_MODE_1_ENABLE 0x0
13453#define B_EC_OC_REG_RCN_MODE_MODE_1_DISABLE 0x2
13454
13455#define B_EC_OC_REG_RCN_MODE_MODE_2__B 2
13456#define B_EC_OC_REG_RCN_MODE_MODE_2__W 1
13457#define B_EC_OC_REG_RCN_MODE_MODE_2__M 0x4
13458#define B_EC_OC_REG_RCN_MODE_MODE_2_ENABLE 0x4
13459#define B_EC_OC_REG_RCN_MODE_MODE_2_DISABLE 0x0
13460
13461
13462#define B_EC_OC_REG_RCN_CRA_LOP__A 0x2150028
13463#define B_EC_OC_REG_RCN_CRA_LOP__W 16
13464#define B_EC_OC_REG_RCN_CRA_LOP__M 0xFFFF
13465#define B_EC_OC_REG_RCN_CRA_LOP_INIT 0x0
13466
13467
13468#define B_EC_OC_REG_RCN_CRA_HIP__A 0x2150029
13469#define B_EC_OC_REG_RCN_CRA_HIP__W 8
13470#define B_EC_OC_REG_RCN_CRA_HIP__M 0xFF
13471#define B_EC_OC_REG_RCN_CRA_HIP_INIT 0xC0
13472
13473
13474#define B_EC_OC_REG_RCN_CST_LOP__A 0x215002A
13475#define B_EC_OC_REG_RCN_CST_LOP__W 16
13476#define B_EC_OC_REG_RCN_CST_LOP__M 0xFFFF
13477#define B_EC_OC_REG_RCN_CST_LOP_INIT 0x1000
13478
13479
13480#define B_EC_OC_REG_RCN_CST_HIP__A 0x215002B
13481#define B_EC_OC_REG_RCN_CST_HIP__W 8
13482#define B_EC_OC_REG_RCN_CST_HIP__M 0xFF
13483#define B_EC_OC_REG_RCN_CST_HIP_INIT 0x0
13484
13485
13486#define B_EC_OC_REG_RCN_SET_LVL__A 0x215002C
13487#define B_EC_OC_REG_RCN_SET_LVL__W 9
13488#define B_EC_OC_REG_RCN_SET_LVL__M 0x1FF
13489#define B_EC_OC_REG_RCN_SET_LVL_INIT 0x1FF
13490
13491
13492#define B_EC_OC_REG_RCN_GAI_LVL__A 0x215002D
13493#define B_EC_OC_REG_RCN_GAI_LVL__W 4
13494#define B_EC_OC_REG_RCN_GAI_LVL__M 0xF
13495#define B_EC_OC_REG_RCN_GAI_LVL_INIT 0xA
13496
13497
13498#define B_EC_OC_REG_RCN_DRA_LOP__A 0x215002E
13499#define B_EC_OC_REG_RCN_DRA_LOP__W 16
13500#define B_EC_OC_REG_RCN_DRA_LOP__M 0xFFFF
13501
13502#define B_EC_OC_REG_RCN_DRA_HIP__A 0x215002F
13503#define B_EC_OC_REG_RCN_DRA_HIP__W 8
13504#define B_EC_OC_REG_RCN_DRA_HIP__M 0xFF
13505
13506#define B_EC_OC_REG_RCN_DOF_LOP__A 0x2150030
13507#define B_EC_OC_REG_RCN_DOF_LOP__W 16
13508#define B_EC_OC_REG_RCN_DOF_LOP__M 0xFFFF
13509
13510#define B_EC_OC_REG_RCN_DOF_HIP__A 0x2150031
13511#define B_EC_OC_REG_RCN_DOF_HIP__W 8
13512#define B_EC_OC_REG_RCN_DOF_HIP__M 0xFF
13513
13514#define B_EC_OC_REG_RCN_CLP_LOP__A 0x2150032
13515#define B_EC_OC_REG_RCN_CLP_LOP__W 16
13516#define B_EC_OC_REG_RCN_CLP_LOP__M 0xFFFF
13517#define B_EC_OC_REG_RCN_CLP_LOP_INIT 0x0
13518
13519
13520#define B_EC_OC_REG_RCN_CLP_HIP__A 0x2150033
13521#define B_EC_OC_REG_RCN_CLP_HIP__W 8
13522#define B_EC_OC_REG_RCN_CLP_HIP__M 0xFF
13523#define B_EC_OC_REG_RCN_CLP_HIP_INIT 0xC0
13524
13525
13526#define B_EC_OC_REG_RCN_MAP_LOP__A 0x2150034
13527#define B_EC_OC_REG_RCN_MAP_LOP__W 16
13528#define B_EC_OC_REG_RCN_MAP_LOP__M 0xFFFF
13529
13530#define B_EC_OC_REG_RCN_MAP_HIP__A 0x2150035
13531#define B_EC_OC_REG_RCN_MAP_HIP__W 8
13532#define B_EC_OC_REG_RCN_MAP_HIP__M 0xFF
13533
13534#define B_EC_OC_REG_OCR_MPG_UOS__A 0x2150036
13535#define B_EC_OC_REG_OCR_MPG_UOS__W 12
13536#define B_EC_OC_REG_OCR_MPG_UOS__M 0xFFF
13537#define B_EC_OC_REG_OCR_MPG_UOS_INIT 0x0
13538
13539#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0__B 0
13540#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0__W 1
13541#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0__M 0x1
13542#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0_DISABLE 0x0
13543#define B_EC_OC_REG_OCR_MPG_UOS_DAT_0_ENABLE 0x1
13544
13545#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1__B 1
13546#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1__W 1
13547#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1__M 0x2
13548#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1_DISABLE 0x0
13549#define B_EC_OC_REG_OCR_MPG_UOS_DAT_1_ENABLE 0x2
13550
13551#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2__B 2
13552#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2__W 1
13553#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2__M 0x4
13554#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2_DISABLE 0x0
13555#define B_EC_OC_REG_OCR_MPG_UOS_DAT_2_ENABLE 0x4
13556
13557#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3__B 3
13558#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3__W 1
13559#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3__M 0x8
13560#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3_DISABLE 0x0
13561#define B_EC_OC_REG_OCR_MPG_UOS_DAT_3_ENABLE 0x8
13562
13563#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4__B 4
13564#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4__W 1
13565#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4__M 0x10
13566#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4_DISABLE 0x0
13567#define B_EC_OC_REG_OCR_MPG_UOS_DAT_4_ENABLE 0x10
13568
13569#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5__B 5
13570#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5__W 1
13571#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5__M 0x20
13572#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5_DISABLE 0x0
13573#define B_EC_OC_REG_OCR_MPG_UOS_DAT_5_ENABLE 0x20
13574
13575#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6__B 6
13576#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6__W 1
13577#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6__M 0x40
13578#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6_DISABLE 0x0
13579#define B_EC_OC_REG_OCR_MPG_UOS_DAT_6_ENABLE 0x40
13580
13581#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7__B 7
13582#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7__W 1
13583#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7__M 0x80
13584#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7_DISABLE 0x0
13585#define B_EC_OC_REG_OCR_MPG_UOS_DAT_7_ENABLE 0x80
13586
13587#define B_EC_OC_REG_OCR_MPG_UOS_ERR__B 8
13588#define B_EC_OC_REG_OCR_MPG_UOS_ERR__W 1
13589#define B_EC_OC_REG_OCR_MPG_UOS_ERR__M 0x100
13590#define B_EC_OC_REG_OCR_MPG_UOS_ERR_DISABLE 0x0
13591#define B_EC_OC_REG_OCR_MPG_UOS_ERR_ENABLE 0x100
13592
13593#define B_EC_OC_REG_OCR_MPG_UOS_STR__B 9
13594#define B_EC_OC_REG_OCR_MPG_UOS_STR__W 1
13595#define B_EC_OC_REG_OCR_MPG_UOS_STR__M 0x200
13596#define B_EC_OC_REG_OCR_MPG_UOS_STR_DISABLE 0x0
13597#define B_EC_OC_REG_OCR_MPG_UOS_STR_ENABLE 0x200
13598
13599#define B_EC_OC_REG_OCR_MPG_UOS_VAL__B 10
13600#define B_EC_OC_REG_OCR_MPG_UOS_VAL__W 1
13601#define B_EC_OC_REG_OCR_MPG_UOS_VAL__M 0x400
13602#define B_EC_OC_REG_OCR_MPG_UOS_VAL_DISABLE 0x0
13603#define B_EC_OC_REG_OCR_MPG_UOS_VAL_ENABLE 0x400
13604
13605#define B_EC_OC_REG_OCR_MPG_UOS_CLK__B 11
13606#define B_EC_OC_REG_OCR_MPG_UOS_CLK__W 1
13607#define B_EC_OC_REG_OCR_MPG_UOS_CLK__M 0x800
13608#define B_EC_OC_REG_OCR_MPG_UOS_CLK_DISABLE 0x0
13609#define B_EC_OC_REG_OCR_MPG_UOS_CLK_ENABLE 0x800
13610
13611
13612#define B_EC_OC_REG_OCR_MPG_WRI__A 0x2150037
13613#define B_EC_OC_REG_OCR_MPG_WRI__W 12
13614#define B_EC_OC_REG_OCR_MPG_WRI__M 0xFFF
13615#define B_EC_OC_REG_OCR_MPG_WRI_INIT 0x0
13616#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0__B 0
13617#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0__W 1
13618#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0__M 0x1
13619#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0_DISABLE 0x0
13620#define B_EC_OC_REG_OCR_MPG_WRI_DAT_0_ENABLE 0x1
13621#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1__B 1
13622#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1__W 1
13623#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1__M 0x2
13624#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1_DISABLE 0x0
13625#define B_EC_OC_REG_OCR_MPG_WRI_DAT_1_ENABLE 0x2
13626#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2__B 2
13627#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2__W 1
13628#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2__M 0x4
13629#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2_DISABLE 0x0
13630#define B_EC_OC_REG_OCR_MPG_WRI_DAT_2_ENABLE 0x4
13631#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3__B 3
13632#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3__W 1
13633#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3__M 0x8
13634#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3_DISABLE 0x0
13635#define B_EC_OC_REG_OCR_MPG_WRI_DAT_3_ENABLE 0x8
13636#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4__B 4
13637#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4__W 1
13638#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4__M 0x10
13639#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4_DISABLE 0x0
13640#define B_EC_OC_REG_OCR_MPG_WRI_DAT_4_ENABLE 0x10
13641#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5__B 5
13642#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5__W 1
13643#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5__M 0x20
13644#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5_DISABLE 0x0
13645#define B_EC_OC_REG_OCR_MPG_WRI_DAT_5_ENABLE 0x20
13646#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6__B 6
13647#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6__W 1
13648#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6__M 0x40
13649#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6_DISABLE 0x0
13650#define B_EC_OC_REG_OCR_MPG_WRI_DAT_6_ENABLE 0x40
13651#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7__B 7
13652#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7__W 1
13653#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7__M 0x80
13654#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7_DISABLE 0x0
13655#define B_EC_OC_REG_OCR_MPG_WRI_DAT_7_ENABLE 0x80
13656#define B_EC_OC_REG_OCR_MPG_WRI_ERR__B 8
13657#define B_EC_OC_REG_OCR_MPG_WRI_ERR__W 1
13658#define B_EC_OC_REG_OCR_MPG_WRI_ERR__M 0x100
13659#define B_EC_OC_REG_OCR_MPG_WRI_ERR_DISABLE 0x0
13660#define B_EC_OC_REG_OCR_MPG_WRI_ERR_ENABLE 0x100
13661#define B_EC_OC_REG_OCR_MPG_WRI_STR__B 9
13662#define B_EC_OC_REG_OCR_MPG_WRI_STR__W 1
13663#define B_EC_OC_REG_OCR_MPG_WRI_STR__M 0x200
13664#define B_EC_OC_REG_OCR_MPG_WRI_STR_DISABLE 0x0
13665#define B_EC_OC_REG_OCR_MPG_WRI_STR_ENABLE 0x200
13666#define B_EC_OC_REG_OCR_MPG_WRI_VAL__B 10
13667#define B_EC_OC_REG_OCR_MPG_WRI_VAL__W 1
13668#define B_EC_OC_REG_OCR_MPG_WRI_VAL__M 0x400
13669#define B_EC_OC_REG_OCR_MPG_WRI_VAL_DISABLE 0x0
13670#define B_EC_OC_REG_OCR_MPG_WRI_VAL_ENABLE 0x400
13671#define B_EC_OC_REG_OCR_MPG_WRI_CLK__B 11
13672#define B_EC_OC_REG_OCR_MPG_WRI_CLK__W 1
13673#define B_EC_OC_REG_OCR_MPG_WRI_CLK__M 0x800
13674#define B_EC_OC_REG_OCR_MPG_WRI_CLK_DISABLE 0x0
13675#define B_EC_OC_REG_OCR_MPG_WRI_CLK_ENABLE 0x800
13676
13677
13678#define B_EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038
13679#define B_EC_OC_REG_OCR_MPG_USR_DAT__W 12
13680#define B_EC_OC_REG_OCR_MPG_USR_DAT__M 0xFFF
13681
13682#define B_EC_OC_REG_OCR_MON_CNT__A 0x215003C
13683#define B_EC_OC_REG_OCR_MON_CNT__W 14
13684#define B_EC_OC_REG_OCR_MON_CNT__M 0x3FFF
13685#define B_EC_OC_REG_OCR_MON_CNT_INIT 0x0
13686
13687
13688#define B_EC_OC_REG_OCR_MON_RDX__A 0x215003D
13689#define B_EC_OC_REG_OCR_MON_RDX__W 1
13690#define B_EC_OC_REG_OCR_MON_RDX__M 0x1
13691#define B_EC_OC_REG_OCR_MON_RDX_INIT 0x0
13692
13693
13694#define B_EC_OC_REG_OCR_MON_RD0__A 0x215003E
13695#define B_EC_OC_REG_OCR_MON_RD0__W 10
13696#define B_EC_OC_REG_OCR_MON_RD0__M 0x3FF
13697
13698#define B_EC_OC_REG_OCR_MON_RD1__A 0x215003F
13699#define B_EC_OC_REG_OCR_MON_RD1__W 10
13700#define B_EC_OC_REG_OCR_MON_RD1__M 0x3FF
13701
13702#define B_EC_OC_REG_OCR_MON_RD2__A 0x2150040
13703#define B_EC_OC_REG_OCR_MON_RD2__W 10
13704#define B_EC_OC_REG_OCR_MON_RD2__M 0x3FF
13705
13706#define B_EC_OC_REG_OCR_MON_RD3__A 0x2150041
13707#define B_EC_OC_REG_OCR_MON_RD3__W 10
13708#define B_EC_OC_REG_OCR_MON_RD3__M 0x3FF
13709
13710#define B_EC_OC_REG_OCR_MON_RD4__A 0x2150042
13711#define B_EC_OC_REG_OCR_MON_RD4__W 10
13712#define B_EC_OC_REG_OCR_MON_RD4__M 0x3FF
13713
13714#define B_EC_OC_REG_OCR_MON_RD5__A 0x2150043
13715#define B_EC_OC_REG_OCR_MON_RD5__W 10
13716#define B_EC_OC_REG_OCR_MON_RD5__M 0x3FF
13717
13718#define B_EC_OC_REG_OCR_INV_MON__A 0x2150044
13719#define B_EC_OC_REG_OCR_INV_MON__W 12
13720#define B_EC_OC_REG_OCR_INV_MON__M 0xFFF
13721#define B_EC_OC_REG_OCR_INV_MON_INIT 0x0
13722
13723
13724#define B_EC_OC_REG_IPR_INV_MPG__A 0x2150045
13725#define B_EC_OC_REG_IPR_INV_MPG__W 12
13726#define B_EC_OC_REG_IPR_INV_MPG__M 0xFFF
13727#define B_EC_OC_REG_IPR_INV_MPG_INIT 0x0
13728
13729
13730#define B_EC_OC_REG_IPR_MSR_SNC__A 0x2150046
13731#define B_EC_OC_REG_IPR_MSR_SNC__W 6
13732#define B_EC_OC_REG_IPR_MSR_SNC__M 0x3F
13733#define B_EC_OC_REG_IPR_MSR_SNC_INIT 0x0
13734
13735
13736#define B_EC_OC_REG_DTO_CLKMODE__A 0x2150047
13737#define B_EC_OC_REG_DTO_CLKMODE__W 2
13738#define B_EC_OC_REG_DTO_CLKMODE__M 0x3
13739#define B_EC_OC_REG_DTO_CLKMODE_INIT 0x2
13740
13741#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD__B 0
13742#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD__W 1
13743#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD__M 0x1
13744#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD_EVEN_ODD 0x0
13745#define B_EC_OC_REG_DTO_CLKMODE_EVEN_ODD_ODD_EVEN 0x1
13746
13747#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER__B 1
13748#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER__W 1
13749#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER__M 0x2
13750#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER_SERIAL_MODE 0x0
13751#define B_EC_OC_REG_DTO_CLKMODE_PAR_SER_PARALLEL_MODE 0x2
13752
13753
13754#define B_EC_OC_REG_DTO_PER__A 0x2150048
13755#define B_EC_OC_REG_DTO_PER__W 8
13756#define B_EC_OC_REG_DTO_PER__M 0xFF
13757#define B_EC_OC_REG_DTO_PER_INIT 0x6
13758
13759
13760#define B_EC_OC_REG_DTO_BUR__A 0x2150049
13761#define B_EC_OC_REG_DTO_BUR__W 2
13762#define B_EC_OC_REG_DTO_BUR__M 0x3
13763#define B_EC_OC_REG_DTO_BUR_INIT 0x1
13764#define B_EC_OC_REG_DTO_BUR_SELECT_1 0x0
13765#define B_EC_OC_REG_DTO_BUR_SELECT_188 0x1
13766#define B_EC_OC_REG_DTO_BUR_SELECT_204 0x2
13767#define B_EC_OC_REG_DTO_BUR_SELECT_47 0x3
13768
13769
13770#define B_EC_OC_REG_RCR_CLKMODE__A 0x215004A
13771#define B_EC_OC_REG_RCR_CLKMODE__W 3
13772#define B_EC_OC_REG_RCR_CLKMODE__M 0x7
13773#define B_EC_OC_REG_RCR_CLKMODE_INIT 0x0
13774
13775#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE__B 0
13776#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE__W 1
13777#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE__M 0x1
13778#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE_FIFO_FRACIONAL 0x0
13779#define B_EC_OC_REG_RCR_CLKMODE_FIFO_SOURCE_FIFO_RATIONAL 0x1
13780
13781#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE__B 1
13782#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE__W 1
13783#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE__M 0x2
13784#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE_FEEDBACKLOOP_FRACTIONAL 0x0
13785#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SOURCE_FEEDBACKLOOP_RATIONAL 0x2
13786
13787#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT__B 2
13788#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT__W 1
13789#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT__M 0x4
13790#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT_SELECT_FIFO 0x0
13791#define B_EC_OC_REG_RCR_CLKMODE_FEEDBACKLOOP_SELECT_SELECT_FEEDBACKLOOP 0x4
13792
13793
13794
13795#define B_EC_OC_RAM__A 0x2160000
13796
13797
13798
13799
13800
13801#define B_CC_SID 0x1B
13802
13803
13804
13805
13806
13807#define B_CC_COMM_EXEC__A 0x2400000
13808#define B_CC_COMM_EXEC__W 3
13809#define B_CC_COMM_EXEC__M 0x7
13810#define B_CC_COMM_EXEC_CTL__B 0
13811#define B_CC_COMM_EXEC_CTL__W 3
13812#define B_CC_COMM_EXEC_CTL__M 0x7
13813#define B_CC_COMM_EXEC_CTL_STOP 0x0
13814#define B_CC_COMM_EXEC_CTL_ACTIVE 0x1
13815#define B_CC_COMM_EXEC_CTL_HOLD 0x2
13816#define B_CC_COMM_EXEC_CTL_STEP 0x3
13817#define B_CC_COMM_EXEC_CTL_BYPASS_STOP 0x4
13818#define B_CC_COMM_EXEC_CTL_BYPASS_HOLD 0x6
13819
13820#define B_CC_COMM_STATE__A 0x2400001
13821#define B_CC_COMM_STATE__W 16
13822#define B_CC_COMM_STATE__M 0xFFFF
13823#define B_CC_COMM_MB__A 0x2400002
13824#define B_CC_COMM_MB__W 16
13825#define B_CC_COMM_MB__M 0xFFFF
13826#define B_CC_COMM_SERVICE0__A 0x2400003
13827#define B_CC_COMM_SERVICE0__W 16
13828#define B_CC_COMM_SERVICE0__M 0xFFFF
13829#define B_CC_COMM_SERVICE1__A 0x2400004
13830#define B_CC_COMM_SERVICE1__W 16
13831#define B_CC_COMM_SERVICE1__M 0xFFFF
13832#define B_CC_COMM_INT_STA__A 0x2400007
13833#define B_CC_COMM_INT_STA__W 16
13834#define B_CC_COMM_INT_STA__M 0xFFFF
13835#define B_CC_COMM_INT_MSK__A 0x2400008
13836#define B_CC_COMM_INT_MSK__W 16
13837#define B_CC_COMM_INT_MSK__M 0xFFFF
13838
13839
13840
13841
13842
13843
13844
13845#define B_CC_REG_COMM_EXEC__A 0x2410000
13846#define B_CC_REG_COMM_EXEC__W 3
13847#define B_CC_REG_COMM_EXEC__M 0x7
13848#define B_CC_REG_COMM_EXEC_CTL__B 0
13849#define B_CC_REG_COMM_EXEC_CTL__W 3
13850#define B_CC_REG_COMM_EXEC_CTL__M 0x7
13851#define B_CC_REG_COMM_EXEC_CTL_STOP 0x0
13852#define B_CC_REG_COMM_EXEC_CTL_ACTIVE 0x1
13853#define B_CC_REG_COMM_EXEC_CTL_HOLD 0x2
13854#define B_CC_REG_COMM_EXEC_CTL_STEP 0x3
13855#define B_CC_REG_COMM_EXEC_CTL_BYPASS_STOP 0x4
13856#define B_CC_REG_COMM_EXEC_CTL_BYPASS_HOLD 0x6
13857
13858#define B_CC_REG_COMM_STATE__A 0x2410001
13859#define B_CC_REG_COMM_STATE__W 16
13860#define B_CC_REG_COMM_STATE__M 0xFFFF
13861#define B_CC_REG_COMM_MB__A 0x2410002
13862#define B_CC_REG_COMM_MB__W 16
13863#define B_CC_REG_COMM_MB__M 0xFFFF
13864#define B_CC_REG_COMM_SERVICE0__A 0x2410003
13865#define B_CC_REG_COMM_SERVICE0__W 16
13866#define B_CC_REG_COMM_SERVICE0__M 0xFFFF
13867#define B_CC_REG_COMM_SERVICE1__A 0x2410004
13868#define B_CC_REG_COMM_SERVICE1__W 16
13869#define B_CC_REG_COMM_SERVICE1__M 0xFFFF
13870#define B_CC_REG_COMM_INT_STA__A 0x2410007
13871#define B_CC_REG_COMM_INT_STA__W 16
13872#define B_CC_REG_COMM_INT_STA__M 0xFFFF
13873#define B_CC_REG_COMM_INT_MSK__A 0x2410008
13874#define B_CC_REG_COMM_INT_MSK__W 16
13875#define B_CC_REG_COMM_INT_MSK__M 0xFFFF
13876
13877#define B_CC_REG_OSC_MODE__A 0x2410010
13878#define B_CC_REG_OSC_MODE__W 2
13879#define B_CC_REG_OSC_MODE__M 0x3
13880#define B_CC_REG_OSC_MODE_OHW 0x0
13881#define B_CC_REG_OSC_MODE_M20 0x1
13882#define B_CC_REG_OSC_MODE_M48 0x2
13883
13884
13885#define B_CC_REG_PLL_MODE__A 0x2410011
13886#define B_CC_REG_PLL_MODE__W 6
13887#define B_CC_REG_PLL_MODE__M 0x3F
13888#define B_CC_REG_PLL_MODE_INIT 0xC
13889#define B_CC_REG_PLL_MODE_BYPASS__B 0
13890#define B_CC_REG_PLL_MODE_BYPASS__W 2
13891#define B_CC_REG_PLL_MODE_BYPASS__M 0x3
13892#define B_CC_REG_PLL_MODE_BYPASS_OHW 0x0
13893#define B_CC_REG_PLL_MODE_BYPASS_PLL 0x1
13894#define B_CC_REG_PLL_MODE_BYPASS_BYPASS 0x2
13895#define B_CC_REG_PLL_MODE_PUMP__B 2
13896#define B_CC_REG_PLL_MODE_PUMP__W 3
13897#define B_CC_REG_PLL_MODE_PUMP__M 0x1C
13898#define B_CC_REG_PLL_MODE_PUMP_OFF 0x0
13899#define B_CC_REG_PLL_MODE_PUMP_CUR_08 0x4
13900#define B_CC_REG_PLL_MODE_PUMP_CUR_09 0x8
13901#define B_CC_REG_PLL_MODE_PUMP_CUR_10 0xC
13902#define B_CC_REG_PLL_MODE_PUMP_CUR_11 0x10
13903#define B_CC_REG_PLL_MODE_PUMP_CUR_12 0x14
13904#define B_CC_REG_PLL_MODE_OUT_EN__B 5
13905#define B_CC_REG_PLL_MODE_OUT_EN__W 1
13906#define B_CC_REG_PLL_MODE_OUT_EN__M 0x20
13907#define B_CC_REG_PLL_MODE_OUT_EN_OFF 0x0
13908#define B_CC_REG_PLL_MODE_OUT_EN_ON 0x20
13909
13910
13911#define B_CC_REG_REF_DIVIDE__A 0x2410012
13912#define B_CC_REG_REF_DIVIDE__W 4
13913#define B_CC_REG_REF_DIVIDE__M 0xF
13914#define B_CC_REG_REF_DIVIDE_INIT 0xA
13915#define B_CC_REG_REF_DIVIDE_OHW 0x0
13916#define B_CC_REG_REF_DIVIDE_D01 0x1
13917#define B_CC_REG_REF_DIVIDE_D02 0x2
13918#define B_CC_REG_REF_DIVIDE_D03 0x3
13919#define B_CC_REG_REF_DIVIDE_D04 0x4
13920#define B_CC_REG_REF_DIVIDE_D05 0x5
13921#define B_CC_REG_REF_DIVIDE_D06 0x6
13922#define B_CC_REG_REF_DIVIDE_D07 0x7
13923#define B_CC_REG_REF_DIVIDE_D08 0x8
13924#define B_CC_REG_REF_DIVIDE_D09 0x9
13925#define B_CC_REG_REF_DIVIDE_D10 0xA
13926
13927
13928#define B_CC_REG_REF_DELAY__A 0x2410013
13929#define B_CC_REG_REF_DELAY__W 3
13930#define B_CC_REG_REF_DELAY__M 0x7
13931#define B_CC_REG_REF_DELAY_EDGE__B 0
13932#define B_CC_REG_REF_DELAY_EDGE__W 1
13933#define B_CC_REG_REF_DELAY_EDGE__M 0x1
13934#define B_CC_REG_REF_DELAY_EDGE_POS 0x0
13935#define B_CC_REG_REF_DELAY_EDGE_NEG 0x1
13936#define B_CC_REG_REF_DELAY_DELAY__B 1
13937#define B_CC_REG_REF_DELAY_DELAY__W 2
13938#define B_CC_REG_REF_DELAY_DELAY__M 0x6
13939#define B_CC_REG_REF_DELAY_DELAY_DEL_0 0x0
13940#define B_CC_REG_REF_DELAY_DELAY_DEL_3 0x2
13941#define B_CC_REG_REF_DELAY_DELAY_DEL_6 0x4
13942#define B_CC_REG_REF_DELAY_DELAY_DEL_9 0x6
13943
13944
13945#define B_CC_REG_CLK_DELAY__A 0x2410014
13946#define B_CC_REG_CLK_DELAY__W 5
13947#define B_CC_REG_CLK_DELAY__M 0x1F
13948#define B_CC_REG_CLK_DELAY_DELAY__B 0
13949#define B_CC_REG_CLK_DELAY_DELAY__W 4
13950#define B_CC_REG_CLK_DELAY_DELAY__M 0xF
13951#define B_CC_REG_CLK_DELAY_DELAY_DEL_00 0x0
13952#define B_CC_REG_CLK_DELAY_DELAY_DEL_05 0x1
13953#define B_CC_REG_CLK_DELAY_DELAY_DEL_10 0x2
13954#define B_CC_REG_CLK_DELAY_DELAY_DEL_15 0x3
13955#define B_CC_REG_CLK_DELAY_DELAY_DEL_20 0x4
13956#define B_CC_REG_CLK_DELAY_DELAY_DEL_25 0x5
13957#define B_CC_REG_CLK_DELAY_DELAY_DEL_30 0x6
13958#define B_CC_REG_CLK_DELAY_DELAY_DEL_35 0x7
13959#define B_CC_REG_CLK_DELAY_DELAY_DEL_40 0x8
13960#define B_CC_REG_CLK_DELAY_DELAY_DEL_45 0x9
13961#define B_CC_REG_CLK_DELAY_DELAY_DEL_50 0xA
13962#define B_CC_REG_CLK_DELAY_DELAY_DEL_55 0xB
13963#define B_CC_REG_CLK_DELAY_DELAY_DEL_60 0xC
13964#define B_CC_REG_CLK_DELAY_DELAY_DEL_65 0xD
13965#define B_CC_REG_CLK_DELAY_DELAY_DEL_70 0xE
13966#define B_CC_REG_CLK_DELAY_DELAY_DEL_75 0xF
13967#define B_CC_REG_CLK_DELAY_EDGE__B 4
13968#define B_CC_REG_CLK_DELAY_EDGE__W 1
13969#define B_CC_REG_CLK_DELAY_EDGE__M 0x10
13970#define B_CC_REG_CLK_DELAY_EDGE_POS 0x0
13971#define B_CC_REG_CLK_DELAY_EDGE_NEG 0x10
13972
13973
13974#define B_CC_REG_PWD_MODE__A 0x2410015
13975#define B_CC_REG_PWD_MODE__W 2
13976#define B_CC_REG_PWD_MODE__M 0x3
13977#define B_CC_REG_PWD_MODE_UP 0x0
13978#define B_CC_REG_PWD_MODE_DOWN_CLK 0x1
13979#define B_CC_REG_PWD_MODE_DOWN_PLL 0x2
13980#define B_CC_REG_PWD_MODE_DOWN_OSC 0x3
13981
13982
13983#define B_CC_REG_SOFT_RST__A 0x2410016
13984#define B_CC_REG_SOFT_RST__W 2
13985#define B_CC_REG_SOFT_RST__M 0x3
13986#define B_CC_REG_SOFT_RST_SYS__B 0
13987#define B_CC_REG_SOFT_RST_SYS__W 1
13988#define B_CC_REG_SOFT_RST_SYS__M 0x1
13989#define B_CC_REG_SOFT_RST_OSC__B 1
13990#define B_CC_REG_SOFT_RST_OSC__W 1
13991#define B_CC_REG_SOFT_RST_OSC__M 0x2
13992
13993
13994#define B_CC_REG_UPDATE__A 0x2410017
13995#define B_CC_REG_UPDATE__W 16
13996#define B_CC_REG_UPDATE__M 0xFFFF
13997#define B_CC_REG_UPDATE_KEY 0x3973
13998
13999
14000#define B_CC_REG_PLL_LOCK__A 0x2410018
14001#define B_CC_REG_PLL_LOCK__W 1
14002#define B_CC_REG_PLL_LOCK__M 0x1
14003#define B_CC_REG_PLL_LOCK_LOCK 0x1
14004
14005
14006#define B_CC_REG_JTAGID_L__A 0x2410019
14007#define B_CC_REG_JTAGID_L__W 16
14008#define B_CC_REG_JTAGID_L__M 0xFFFF
14009#define B_CC_REG_JTAGID_L_INIT 0x0
14010
14011
14012#define B_CC_REG_JTAGID_H__A 0x241001A
14013#define B_CC_REG_JTAGID_H__W 16
14014#define B_CC_REG_JTAGID_H__M 0xFFFF
14015#define B_CC_REG_JTAGID_H_INIT 0x0
14016
14017
14018#define B_CC_REG_DIVERSITY__A 0x241001B
14019#define B_CC_REG_DIVERSITY__W 1
14020#define B_CC_REG_DIVERSITY__M 0x1
14021#define B_CC_REG_DIVERSITY_INIT 0x0
14022
14023
14024#define B_CC_REG_BACKUP3V__A 0x241001C
14025#define B_CC_REG_BACKUP3V__W 1
14026#define B_CC_REG_BACKUP3V__M 0x1
14027#define B_CC_REG_BACKUP3V_INIT 0x0
14028
14029
14030#define B_CC_REG_DRV_IO__A 0x241001D
14031#define B_CC_REG_DRV_IO__W 3
14032#define B_CC_REG_DRV_IO__M 0x7
14033#define B_CC_REG_DRV_IO_INIT 0x2
14034
14035
14036#define B_CC_REG_DRV_MPG__A 0x241001E
14037#define B_CC_REG_DRV_MPG__W 3
14038#define B_CC_REG_DRV_MPG__M 0x7
14039#define B_CC_REG_DRV_MPG_INIT 0x2
14040
14041
14042#define B_CC_REG_DRV_I2C1__A 0x241001F
14043#define B_CC_REG_DRV_I2C1__W 3
14044#define B_CC_REG_DRV_I2C1__M 0x7
14045#define B_CC_REG_DRV_I2C1_INIT 0x2
14046
14047
14048#define B_CC_REG_DRV_I2C2__A 0x2410020
14049#define B_CC_REG_DRV_I2C2__W 1
14050#define B_CC_REG_DRV_I2C2__M 0x1
14051#define B_CC_REG_DRV_I2C2_INIT 0x0
14052
14053
14054
14055
14056
14057#define B_LC_SID 0x1C
14058
14059
14060
14061
14062
14063#define B_LC_COMM_EXEC__A 0x2800000
14064#define B_LC_COMM_EXEC__W 3
14065#define B_LC_COMM_EXEC__M 0x7
14066#define B_LC_COMM_EXEC_CTL__B 0
14067#define B_LC_COMM_EXEC_CTL__W 3
14068#define B_LC_COMM_EXEC_CTL__M 0x7
14069#define B_LC_COMM_EXEC_CTL_STOP 0x0
14070#define B_LC_COMM_EXEC_CTL_ACTIVE 0x1
14071#define B_LC_COMM_EXEC_CTL_HOLD 0x2
14072#define B_LC_COMM_EXEC_CTL_STEP 0x3
14073#define B_LC_COMM_EXEC_CTL_BYPASS_STOP 0x4
14074#define B_LC_COMM_EXEC_CTL_BYPASS_HOLD 0x6
14075
14076#define B_LC_COMM_STATE__A 0x2800001
14077#define B_LC_COMM_STATE__W 16
14078#define B_LC_COMM_STATE__M 0xFFFF
14079#define B_LC_COMM_MB__A 0x2800002
14080#define B_LC_COMM_MB__W 16
14081#define B_LC_COMM_MB__M 0xFFFF
14082#define B_LC_COMM_SERVICE0__A 0x2800003
14083#define B_LC_COMM_SERVICE0__W 16
14084#define B_LC_COMM_SERVICE0__M 0xFFFF
14085#define B_LC_COMM_SERVICE1__A 0x2800004
14086#define B_LC_COMM_SERVICE1__W 16
14087#define B_LC_COMM_SERVICE1__M 0xFFFF
14088#define B_LC_COMM_INT_STA__A 0x2800007
14089#define B_LC_COMM_INT_STA__W 16
14090#define B_LC_COMM_INT_STA__M 0xFFFF
14091#define B_LC_COMM_INT_MSK__A 0x2800008
14092#define B_LC_COMM_INT_MSK__W 16
14093#define B_LC_COMM_INT_MSK__M 0xFFFF
14094
14095
14096
14097
14098
14099
14100#define B_LC_CT_REG_COMM_EXEC__A 0x2810000
14101#define B_LC_CT_REG_COMM_EXEC__W 3
14102#define B_LC_CT_REG_COMM_EXEC__M 0x7
14103#define B_LC_CT_REG_COMM_EXEC_CTL__B 0
14104#define B_LC_CT_REG_COMM_EXEC_CTL__W 3
14105#define B_LC_CT_REG_COMM_EXEC_CTL__M 0x7
14106#define B_LC_CT_REG_COMM_EXEC_CTL_STOP 0x0
14107#define B_LC_CT_REG_COMM_EXEC_CTL_ACTIVE 0x1
14108#define B_LC_CT_REG_COMM_EXEC_CTL_HOLD 0x2
14109#define B_LC_CT_REG_COMM_EXEC_CTL_STEP 0x3
14110
14111
14112#define B_LC_CT_REG_COMM_STATE__A 0x2810001
14113#define B_LC_CT_REG_COMM_STATE__W 10
14114#define B_LC_CT_REG_COMM_STATE__M 0x3FF
14115#define B_LC_CT_REG_COMM_SERVICE0__A 0x2810003
14116#define B_LC_CT_REG_COMM_SERVICE0__W 16
14117#define B_LC_CT_REG_COMM_SERVICE0__M 0xFFFF
14118#define B_LC_CT_REG_COMM_SERVICE1__A 0x2810004
14119#define B_LC_CT_REG_COMM_SERVICE1__W 16
14120#define B_LC_CT_REG_COMM_SERVICE1__M 0xFFFF
14121#define B_LC_CT_REG_COMM_SERVICE1_LC__B 12
14122#define B_LC_CT_REG_COMM_SERVICE1_LC__W 1
14123#define B_LC_CT_REG_COMM_SERVICE1_LC__M 0x1000
14124
14125
14126#define B_LC_CT_REG_COMM_INT_STA__A 0x2810007
14127#define B_LC_CT_REG_COMM_INT_STA__W 1
14128#define B_LC_CT_REG_COMM_INT_STA__M 0x1
14129#define B_LC_CT_REG_COMM_INT_STA_REQUEST__B 0
14130#define B_LC_CT_REG_COMM_INT_STA_REQUEST__W 1
14131#define B_LC_CT_REG_COMM_INT_STA_REQUEST__M 0x1
14132
14133
14134#define B_LC_CT_REG_COMM_INT_MSK__A 0x2810008
14135#define B_LC_CT_REG_COMM_INT_MSK__W 1
14136#define B_LC_CT_REG_COMM_INT_MSK__M 0x1
14137#define B_LC_CT_REG_COMM_INT_MSK_REQUEST__B 0
14138#define B_LC_CT_REG_COMM_INT_MSK_REQUEST__W 1
14139#define B_LC_CT_REG_COMM_INT_MSK_REQUEST__M 0x1
14140
14141
14142
14143
14144#define B_LC_CT_REG_CTL_STK__AX 0x2810010
14145#define B_LC_CT_REG_CTL_STK__XSZ 4
14146#define B_LC_CT_REG_CTL_STK__W 10
14147#define B_LC_CT_REG_CTL_STK__M 0x3FF
14148
14149#define B_LC_CT_REG_CTL_BPT_IDX__A 0x281001F
14150#define B_LC_CT_REG_CTL_BPT_IDX__W 1
14151#define B_LC_CT_REG_CTL_BPT_IDX__M 0x1
14152
14153#define B_LC_CT_REG_CTL_BPT__A 0x2810020
14154#define B_LC_CT_REG_CTL_BPT__W 10
14155#define B_LC_CT_REG_CTL_BPT__M 0x3FF
14156
14157
14158
14159
14160
14161#define B_LC_RA_RAM_PROC_DELAY_IF__A 0x2820006
14162#define B_LC_RA_RAM_PROC_DELAY_IF__W 16
14163#define B_LC_RA_RAM_PROC_DELAY_IF__M 0xFFFF
14164#define B_LC_RA_RAM_PROC_DELAY_IF__PRE 0xFFE6
14165#define B_LC_RA_RAM_PROC_DELAY_FS__A 0x2820007
14166#define B_LC_RA_RAM_PROC_DELAY_FS__W 16
14167#define B_LC_RA_RAM_PROC_DELAY_FS__M 0xFFFF
14168#define B_LC_RA_RAM_PROC_DELAY_FS__PRE 0xFFE3
14169#define B_LC_RA_RAM_LOCK_TH_CRMM__A 0x2820008
14170#define B_LC_RA_RAM_LOCK_TH_CRMM__W 16
14171#define B_LC_RA_RAM_LOCK_TH_CRMM__M 0xFFFF
14172#define B_LC_RA_RAM_LOCK_TH_CRMM__PRE 0xC8
14173#define B_LC_RA_RAM_LOCK_TH_SRMM__A 0x2820009
14174#define B_LC_RA_RAM_LOCK_TH_SRMM__W 16
14175#define B_LC_RA_RAM_LOCK_TH_SRMM__M 0xFFFF
14176#define B_LC_RA_RAM_LOCK_TH_SRMM__PRE 0x46
14177#define B_LC_RA_RAM_LOCK_COUNT__A 0x282000A
14178#define B_LC_RA_RAM_LOCK_COUNT__W 16
14179#define B_LC_RA_RAM_LOCK_COUNT__M 0xFFFF
14180#define B_LC_RA_RAM_CPRTOFS_NOM__A 0x282000B
14181#define B_LC_RA_RAM_CPRTOFS_NOM__W 16
14182#define B_LC_RA_RAM_CPRTOFS_NOM__M 0xFFFF
14183#define B_LC_RA_RAM_IFINCR_NOM_L__A 0x282000C
14184#define B_LC_RA_RAM_IFINCR_NOM_L__W 16
14185#define B_LC_RA_RAM_IFINCR_NOM_L__M 0xFFFF
14186#define B_LC_RA_RAM_IFINCR_NOM_H__A 0x282000D
14187#define B_LC_RA_RAM_IFINCR_NOM_H__W 16
14188#define B_LC_RA_RAM_IFINCR_NOM_H__M 0xFFFF
14189#define B_LC_RA_RAM_FSINCR_NOM_L__A 0x282000E
14190#define B_LC_RA_RAM_FSINCR_NOM_L__W 16
14191#define B_LC_RA_RAM_FSINCR_NOM_L__M 0xFFFF
14192#define B_LC_RA_RAM_FSINCR_NOM_H__A 0x282000F
14193#define B_LC_RA_RAM_FSINCR_NOM_H__W 16
14194#define B_LC_RA_RAM_FSINCR_NOM_H__M 0xFFFF
14195#define B_LC_RA_RAM_MODE_2K__A 0x2820010
14196#define B_LC_RA_RAM_MODE_2K__W 16
14197#define B_LC_RA_RAM_MODE_2K__M 0xFFFF
14198#define B_LC_RA_RAM_MODE_GUARD__A 0x2820011
14199#define B_LC_RA_RAM_MODE_GUARD__W 16
14200#define B_LC_RA_RAM_MODE_GUARD__M 0xFFFF
14201#define B_LC_RA_RAM_MODE_GUARD_32 0x0
14202#define B_LC_RA_RAM_MODE_GUARD_16 0x1
14203#define B_LC_RA_RAM_MODE_GUARD_8 0x2
14204#define B_LC_RA_RAM_MODE_GUARD_4 0x3
14205
14206#define B_LC_RA_RAM_MODE_ADJUST__A 0x2820012
14207#define B_LC_RA_RAM_MODE_ADJUST__W 16
14208#define B_LC_RA_RAM_MODE_ADJUST__M 0xFFFF
14209#define B_LC_RA_RAM_MODE_ADJUST_CP_CRMM__B 0
14210#define B_LC_RA_RAM_MODE_ADJUST_CP_CRMM__W 1
14211#define B_LC_RA_RAM_MODE_ADJUST_CP_CRMM__M 0x1
14212#define B_LC_RA_RAM_MODE_ADJUST_CE_CRMM__B 1
14213#define B_LC_RA_RAM_MODE_ADJUST_CE_CRMM__W 1
14214#define B_LC_RA_RAM_MODE_ADJUST_CE_CRMM__M 0x2
14215#define B_LC_RA_RAM_MODE_ADJUST_SRMM__B 2
14216#define B_LC_RA_RAM_MODE_ADJUST_SRMM__W 1
14217#define B_LC_RA_RAM_MODE_ADJUST_SRMM__M 0x4
14218#define B_LC_RA_RAM_MODE_ADJUST_PHASE__B 3
14219#define B_LC_RA_RAM_MODE_ADJUST_PHASE__W 1
14220#define B_LC_RA_RAM_MODE_ADJUST_PHASE__M 0x8
14221#define B_LC_RA_RAM_MODE_ADJUST_DELAY__B 4
14222#define B_LC_RA_RAM_MODE_ADJUST_DELAY__W 1
14223#define B_LC_RA_RAM_MODE_ADJUST_DELAY__M 0x10
14224#define B_LC_RA_RAM_MODE_ADJUST_OPENLOOP__B 5
14225#define B_LC_RA_RAM_MODE_ADJUST_OPENLOOP__W 1
14226#define B_LC_RA_RAM_MODE_ADJUST_OPENLOOP__M 0x20
14227#define B_LC_RA_RAM_MODE_ADJUST_NO_CP__B 6
14228#define B_LC_RA_RAM_MODE_ADJUST_NO_CP__W 1
14229#define B_LC_RA_RAM_MODE_ADJUST_NO_CP__M 0x40
14230#define B_LC_RA_RAM_MODE_ADJUST_NO_FS__B 7
14231#define B_LC_RA_RAM_MODE_ADJUST_NO_FS__W 1
14232#define B_LC_RA_RAM_MODE_ADJUST_NO_FS__M 0x80
14233#define B_LC_RA_RAM_MODE_ADJUST_NO_IF__B 8
14234#define B_LC_RA_RAM_MODE_ADJUST_NO_IF__W 1
14235#define B_LC_RA_RAM_MODE_ADJUST_NO_IF__M 0x100
14236#define B_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__B 9
14237#define B_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__W 1
14238#define B_LC_RA_RAM_MODE_ADJUST_NO_PH_PIPE__M 0x200
14239#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__B 10
14240#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__W 1
14241#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_CRMM__M 0x400
14242#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__B 11
14243#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__W 1
14244#define B_LC_RA_RAM_MODE_ADJUST_CP_DIF_SRMM__M 0x800
14245
14246#define B_LC_RA_RAM_RC_STS__A 0x2820014
14247#define B_LC_RA_RAM_RC_STS__W 16
14248#define B_LC_RA_RAM_RC_STS__M 0xFFFF
14249#define B_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__A 0x2820018
14250#define B_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__W 16
14251#define B_LC_RA_RAM_ACTUAL_CP_DIF_CRMM__M 0xFFFF
14252#define B_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__A 0x2820019
14253#define B_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__W 16
14254#define B_LC_RA_RAM_ACTUAL_CP_DIF_SRMM__M 0xFFFF
14255#define B_LC_RA_RAM_FILTER_SYM_SET__A 0x282001A
14256#define B_LC_RA_RAM_FILTER_SYM_SET__W 16
14257#define B_LC_RA_RAM_FILTER_SYM_SET__M 0xFFFF
14258#define B_LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8
14259#define B_LC_RA_RAM_FILTER_SYM_CUR__A 0x282001B
14260#define B_LC_RA_RAM_FILTER_SYM_CUR__W 16
14261#define B_LC_RA_RAM_FILTER_SYM_CUR__M 0xFFFF
14262#define B_LC_RA_RAM_FILTER_SYM_CUR__PRE 0x0
14263#define B_LC_RA_RAM_DIVERSITY_DELAY__A 0x282001C
14264#define B_LC_RA_RAM_DIVERSITY_DELAY__W 16
14265#define B_LC_RA_RAM_DIVERSITY_DELAY__M 0xFFFF
14266#define B_LC_RA_RAM_DIVERSITY_DELAY__PRE 0x3E8
14267#define B_LC_RA_RAM_MAX_ABS_EXP__A 0x282001D
14268#define B_LC_RA_RAM_MAX_ABS_EXP__W 16
14269#define B_LC_RA_RAM_MAX_ABS_EXP__M 0xFFFF
14270#define B_LC_RA_RAM_MAX_ABS_EXP__PRE 0x10
14271#define B_LC_RA_RAM_ACTUAL_CP_CRMM__A 0x282001F
14272#define B_LC_RA_RAM_ACTUAL_CP_CRMM__W 16
14273#define B_LC_RA_RAM_ACTUAL_CP_CRMM__M 0xFFFF
14274#define B_LC_RA_RAM_ACTUAL_CE_CRMM__A 0x2820020
14275#define B_LC_RA_RAM_ACTUAL_CE_CRMM__W 16
14276#define B_LC_RA_RAM_ACTUAL_CE_CRMM__M 0xFFFF
14277#define B_LC_RA_RAM_ACTUAL_CE_SRMM__A 0x2820021
14278#define B_LC_RA_RAM_ACTUAL_CE_SRMM__W 16
14279#define B_LC_RA_RAM_ACTUAL_CE_SRMM__M 0xFFFF
14280#define B_LC_RA_RAM_ACTUAL_PHASE__A 0x2820022
14281#define B_LC_RA_RAM_ACTUAL_PHASE__W 16
14282#define B_LC_RA_RAM_ACTUAL_PHASE__M 0xFFFF
14283#define B_LC_RA_RAM_ACTUAL_DELAY__A 0x2820023
14284#define B_LC_RA_RAM_ACTUAL_DELAY__W 16
14285#define B_LC_RA_RAM_ACTUAL_DELAY__M 0xFFFF
14286#define B_LC_RA_RAM_ADJUST_CRMM__A 0x2820024
14287#define B_LC_RA_RAM_ADJUST_CRMM__W 16
14288#define B_LC_RA_RAM_ADJUST_CRMM__M 0xFFFF
14289#define B_LC_RA_RAM_ADJUST_SRMM__A 0x2820025
14290#define B_LC_RA_RAM_ADJUST_SRMM__W 16
14291#define B_LC_RA_RAM_ADJUST_SRMM__M 0xFFFF
14292#define B_LC_RA_RAM_ADJUST_PHASE__A 0x2820026
14293#define B_LC_RA_RAM_ADJUST_PHASE__W 16
14294#define B_LC_RA_RAM_ADJUST_PHASE__M 0xFFFF
14295#define B_LC_RA_RAM_ADJUST_DELAY__A 0x2820027
14296#define B_LC_RA_RAM_ADJUST_DELAY__W 16
14297#define B_LC_RA_RAM_ADJUST_DELAY__M 0xFFFF
14298
14299
14300
14301
14302
14303#define B_LC_RA_RAM_PIPE_CP_PHASE_0__A 0x2820028
14304#define B_LC_RA_RAM_PIPE_CP_PHASE_0__W 16
14305#define B_LC_RA_RAM_PIPE_CP_PHASE_0__M 0xFFFF
14306#define B_LC_RA_RAM_PIPE_CP_PHASE_1__A 0x2820029
14307#define B_LC_RA_RAM_PIPE_CP_PHASE_1__W 16
14308#define B_LC_RA_RAM_PIPE_CP_PHASE_1__M 0xFFFF
14309#define B_LC_RA_RAM_PIPE_CP_PHASE_CON__A 0x282002A
14310#define B_LC_RA_RAM_PIPE_CP_PHASE_CON__W 16
14311#define B_LC_RA_RAM_PIPE_CP_PHASE_CON__M 0xFFFF
14312#define B_LC_RA_RAM_PIPE_CP_PHASE_DIF__A 0x282002B
14313#define B_LC_RA_RAM_PIPE_CP_PHASE_DIF__W 16
14314#define B_LC_RA_RAM_PIPE_CP_PHASE_DIF__M 0xFFFF
14315#define B_LC_RA_RAM_PIPE_CP_PHASE_RES__A 0x282002C
14316#define B_LC_RA_RAM_PIPE_CP_PHASE_RES__W 16
14317#define B_LC_RA_RAM_PIPE_CP_PHASE_RES__M 0xFFFF
14318#define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__A 0x282002D
14319#define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__W 16
14320#define B_LC_RA_RAM_PIPE_CP_PHASE_RZ__M 0xFFFF
14321
14322
14323
14324#define B_LC_RA_RAM_PIPE_CP_CRMM_0__A 0x2820030
14325#define B_LC_RA_RAM_PIPE_CP_CRMM_0__W 16
14326#define B_LC_RA_RAM_PIPE_CP_CRMM_0__M 0xFFFF
14327#define B_LC_RA_RAM_PIPE_CP_CRMM_1__A 0x2820031
14328#define B_LC_RA_RAM_PIPE_CP_CRMM_1__W 16
14329#define B_LC_RA_RAM_PIPE_CP_CRMM_1__M 0xFFFF
14330#define B_LC_RA_RAM_PIPE_CP_CRMM_CON__A 0x2820032
14331#define B_LC_RA_RAM_PIPE_CP_CRMM_CON__W 16
14332#define B_LC_RA_RAM_PIPE_CP_CRMM_CON__M 0xFFFF
14333#define B_LC_RA_RAM_PIPE_CP_CRMM_DIF__A 0x2820033
14334#define B_LC_RA_RAM_PIPE_CP_CRMM_DIF__W 16
14335#define B_LC_RA_RAM_PIPE_CP_CRMM_DIF__M 0xFFFF
14336#define B_LC_RA_RAM_PIPE_CP_CRMM_RES__A 0x2820034
14337#define B_LC_RA_RAM_PIPE_CP_CRMM_RES__W 16
14338#define B_LC_RA_RAM_PIPE_CP_CRMM_RES__M 0xFFFF
14339#define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__A 0x2820035
14340#define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__W 16
14341#define B_LC_RA_RAM_PIPE_CP_CRMM_RZ__M 0xFFFF
14342
14343
14344
14345#define B_LC_RA_RAM_PIPE_CP_SRMM_0__A 0x2820038
14346#define B_LC_RA_RAM_PIPE_CP_SRMM_0__W 16
14347#define B_LC_RA_RAM_PIPE_CP_SRMM_0__M 0xFFFF
14348#define B_LC_RA_RAM_PIPE_CP_SRMM_1__A 0x2820039
14349#define B_LC_RA_RAM_PIPE_CP_SRMM_1__W 16
14350#define B_LC_RA_RAM_PIPE_CP_SRMM_1__M 0xFFFF
14351#define B_LC_RA_RAM_PIPE_CP_SRMM_CON__A 0x282003A
14352#define B_LC_RA_RAM_PIPE_CP_SRMM_CON__W 16
14353#define B_LC_RA_RAM_PIPE_CP_SRMM_CON__M 0xFFFF
14354#define B_LC_RA_RAM_PIPE_CP_SRMM_DIF__A 0x282003B
14355#define B_LC_RA_RAM_PIPE_CP_SRMM_DIF__W 16
14356#define B_LC_RA_RAM_PIPE_CP_SRMM_DIF__M 0xFFFF
14357#define B_LC_RA_RAM_PIPE_CP_SRMM_RES__A 0x282003C
14358#define B_LC_RA_RAM_PIPE_CP_SRMM_RES__W 16
14359#define B_LC_RA_RAM_PIPE_CP_SRMM_RES__M 0xFFFF
14360#define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__A 0x282003D
14361#define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__W 16
14362#define B_LC_RA_RAM_PIPE_CP_SRMM_RZ__M 0xFFFF
14363
14364
14365
14366
14367
14368#define B_LC_RA_RAM_FILTER_CRMM_A__A 0x2820060
14369#define B_LC_RA_RAM_FILTER_CRMM_A__W 16
14370#define B_LC_RA_RAM_FILTER_CRMM_A__M 0xFFFF
14371#define B_LC_RA_RAM_FILTER_CRMM_A__PRE 0x4
14372#define B_LC_RA_RAM_FILTER_CRMM_B__A 0x2820061
14373#define B_LC_RA_RAM_FILTER_CRMM_B__W 16
14374#define B_LC_RA_RAM_FILTER_CRMM_B__M 0xFFFF
14375#define B_LC_RA_RAM_FILTER_CRMM_B__PRE 0x1
14376#define B_LC_RA_RAM_FILTER_CRMM_Z1__AX 0x2820062
14377#define B_LC_RA_RAM_FILTER_CRMM_Z1__XSZ 2
14378#define B_LC_RA_RAM_FILTER_CRMM_Z1__W 16
14379#define B_LC_RA_RAM_FILTER_CRMM_Z1__M 0xFFFF
14380#define B_LC_RA_RAM_FILTER_CRMM_Z2__AX 0x2820064
14381#define B_LC_RA_RAM_FILTER_CRMM_Z2__XSZ 2
14382#define B_LC_RA_RAM_FILTER_CRMM_Z2__W 16
14383#define B_LC_RA_RAM_FILTER_CRMM_Z2__M 0xFFFF
14384#define B_LC_RA_RAM_FILTER_CRMM_TMP__AX 0x2820066
14385#define B_LC_RA_RAM_FILTER_CRMM_TMP__XSZ 2
14386#define B_LC_RA_RAM_FILTER_CRMM_TMP__W 16
14387#define B_LC_RA_RAM_FILTER_CRMM_TMP__M 0xFFFF
14388
14389
14390
14391#define B_LC_RA_RAM_FILTER_SRMM_A__A 0x2820068
14392#define B_LC_RA_RAM_FILTER_SRMM_A__W 16
14393#define B_LC_RA_RAM_FILTER_SRMM_A__M 0xFFFF
14394#define B_LC_RA_RAM_FILTER_SRMM_A__PRE 0x4
14395#define B_LC_RA_RAM_FILTER_SRMM_B__A 0x2820069
14396#define B_LC_RA_RAM_FILTER_SRMM_B__W 16
14397#define B_LC_RA_RAM_FILTER_SRMM_B__M 0xFFFF
14398#define B_LC_RA_RAM_FILTER_SRMM_B__PRE 0x1
14399#define B_LC_RA_RAM_FILTER_SRMM_Z1__AX 0x282006A
14400#define B_LC_RA_RAM_FILTER_SRMM_Z1__XSZ 2
14401#define B_LC_RA_RAM_FILTER_SRMM_Z1__W 16
14402#define B_LC_RA_RAM_FILTER_SRMM_Z1__M 0xFFFF
14403#define B_LC_RA_RAM_FILTER_SRMM_Z2__AX 0x282006C
14404#define B_LC_RA_RAM_FILTER_SRMM_Z2__XSZ 2
14405#define B_LC_RA_RAM_FILTER_SRMM_Z2__W 16
14406#define B_LC_RA_RAM_FILTER_SRMM_Z2__M 0xFFFF
14407#define B_LC_RA_RAM_FILTER_SRMM_TMP__AX 0x282006E
14408#define B_LC_RA_RAM_FILTER_SRMM_TMP__XSZ 2
14409#define B_LC_RA_RAM_FILTER_SRMM_TMP__W 16
14410#define B_LC_RA_RAM_FILTER_SRMM_TMP__M 0xFFFF
14411
14412
14413
14414#define B_LC_RA_RAM_FILTER_PHASE_A__A 0x2820070
14415#define B_LC_RA_RAM_FILTER_PHASE_A__W 16
14416#define B_LC_RA_RAM_FILTER_PHASE_A__M 0xFFFF
14417#define B_LC_RA_RAM_FILTER_PHASE_A__PRE 0x4
14418#define B_LC_RA_RAM_FILTER_PHASE_B__A 0x2820071
14419#define B_LC_RA_RAM_FILTER_PHASE_B__W 16
14420#define B_LC_RA_RAM_FILTER_PHASE_B__M 0xFFFF
14421#define B_LC_RA_RAM_FILTER_PHASE_B__PRE 0x1
14422#define B_LC_RA_RAM_FILTER_PHASE_Z1__AX 0x2820072
14423#define B_LC_RA_RAM_FILTER_PHASE_Z1__XSZ 2
14424#define B_LC_RA_RAM_FILTER_PHASE_Z1__W 16
14425#define B_LC_RA_RAM_FILTER_PHASE_Z1__M 0xFFFF
14426#define B_LC_RA_RAM_FILTER_PHASE_Z2__AX 0x2820074
14427#define B_LC_RA_RAM_FILTER_PHASE_Z2__XSZ 2
14428#define B_LC_RA_RAM_FILTER_PHASE_Z2__W 16
14429#define B_LC_RA_RAM_FILTER_PHASE_Z2__M 0xFFFF
14430#define B_LC_RA_RAM_FILTER_PHASE_TMP__AX 0x2820076
14431#define B_LC_RA_RAM_FILTER_PHASE_TMP__XSZ 2
14432#define B_LC_RA_RAM_FILTER_PHASE_TMP__W 16
14433#define B_LC_RA_RAM_FILTER_PHASE_TMP__M 0xFFFF
14434
14435
14436
14437#define B_LC_RA_RAM_FILTER_DELAY_A__A 0x2820078
14438#define B_LC_RA_RAM_FILTER_DELAY_A__W 16
14439#define B_LC_RA_RAM_FILTER_DELAY_A__M 0xFFFF
14440#define B_LC_RA_RAM_FILTER_DELAY_A__PRE 0x4
14441#define B_LC_RA_RAM_FILTER_DELAY_B__A 0x2820079
14442#define B_LC_RA_RAM_FILTER_DELAY_B__W 16
14443#define B_LC_RA_RAM_FILTER_DELAY_B__M 0xFFFF
14444#define B_LC_RA_RAM_FILTER_DELAY_B__PRE 0x1
14445#define B_LC_RA_RAM_FILTER_DELAY_Z1__AX 0x282007A
14446#define B_LC_RA_RAM_FILTER_DELAY_Z1__XSZ 2
14447#define B_LC_RA_RAM_FILTER_DELAY_Z1__W 16
14448#define B_LC_RA_RAM_FILTER_DELAY_Z1__M 0xFFFF
14449#define B_LC_RA_RAM_FILTER_DELAY_Z2__AX 0x282007C
14450#define B_LC_RA_RAM_FILTER_DELAY_Z2__XSZ 2
14451#define B_LC_RA_RAM_FILTER_DELAY_Z2__W 16
14452#define B_LC_RA_RAM_FILTER_DELAY_Z2__M 0xFFFF
14453#define B_LC_RA_RAM_FILTER_DELAY_TMP__AX 0x282007E
14454#define B_LC_RA_RAM_FILTER_DELAY_TMP__XSZ 2
14455#define B_LC_RA_RAM_FILTER_DELAY_TMP__W 16
14456#define B_LC_RA_RAM_FILTER_DELAY_TMP__M 0xFFFF
14457
14458
14459
14460
14461
14462
14463#define B_LC_IF_RAM_TRP_BPT0__AX 0x2830000
14464#define B_LC_IF_RAM_TRP_BPT0__XSZ 2
14465#define B_LC_IF_RAM_TRP_BPT0__W 12
14466#define B_LC_IF_RAM_TRP_BPT0__M 0xFFF
14467
14468#define B_LC_IF_RAM_TRP_STKU__AX 0x2830002
14469#define B_LC_IF_RAM_TRP_STKU__XSZ 2
14470#define B_LC_IF_RAM_TRP_STKU__W 12
14471#define B_LC_IF_RAM_TRP_STKU__M 0xFFF
14472
14473#define B_LC_IF_RAM_TRP_WARM__AX 0x2830006
14474#define B_LC_IF_RAM_TRP_WARM__XSZ 2
14475#define B_LC_IF_RAM_TRP_WARM__W 12
14476#define B_LC_IF_RAM_TRP_WARM__M 0xFFF
14477
14478#ifdef __cplusplus
14479}
14480#endif
14481
14482#endif
14483
14484
diff --git a/drivers/media/dvb/frontends/drxd_micro.h b/drivers/media/dvb/frontends/drxd_micro.h
new file mode 100644
index 000000000000..237296d35e55
--- /dev/null
+++ b/drivers/media/dvb/frontends/drxd_micro.h
@@ -0,0 +1,1498 @@
1/*-----------------------------------------------------------------------------
2*
3* $(c) 2003-2007 Micronas GmbH. All rights reserved.
4*
5* This software and related documentation (the 'Software') are intellectual
6* property owned by Micronas and are copyright of Micronas, unless specifically
7* noted otherwise.
8*
9* Any use of the Software is permitted only pursuant to the terms of the
10* license agreement, if any, which accompanies, is included with or applicable
11* to the Software ('License Agreement') or upon express written consent of
12* Micronas. Any copying, reproduction or redistribution of the Software in
13* whole or in part by any means not in accordance with the License Agreement
14* or as agreed in writing by Micronas is expressly prohibited.
15*
16* THE SOFTWARE IS WARRANTED, IF AT ALL, ONLY ACCORDING TO THE TERMS OF THE
17* LICENSE AGREEMENT. EXCEPT AS WARRANTED IN THE LICENSE AGREEMENT THE SOFTWARE
18* IS DELIVERED 'AS IS' AND MICRONAS HEREBY DISCLAIMS ALL WARRANTIES AND
19* CONDITIONS WITH REGARD TO THE SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES
20* AND CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, QUIT
21* ENJOYMENT, TITLE AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
22* PROPERTY OR OTHER RIGHTS WHICH MAY RESULT FROM THE USE OR THE INABILITY
23* TO USE THE SOFTWARE.
24*
25* IN NO EVENT SHALL MICRONAS BE LIABLE FOR INDIRECT, INCIDENTAL, CONSEQUENTIAL,
26* PUNITIVE, SPECIAL OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION,
27* DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS
28* INFORMATION, AND THE LIKE, ARISING OUT OF OR RELATING TO THE USE OF OR THE
29* INABILITY TO USE THE SOFTWARE, EVEN IF MICRONAS HAS BEEN ADVISED OF THE
30* POSSIBILITY OF SUCH DAMAGES, EXCEPT PERSONAL INJURY OR DEATH RESULTING FROM
31* MICRONAS' NEGLIGENCE. $
32*
33----------------------------------------------------------------------------*/
34
35
36
37/*
38 Permission is granted by Micronas to distribute this file, either
39 in this form (hex-dump) or converted to a binary file, together
40 with the DRX397X Linux driver.
41*/
42
43
44u8_t DRXD_A2_microcode[] = {
450x48, 0x4c, 0x00, 0x04, 0x00, 0x83, 0x00, 0x00, 0x10, 0x00, 0x00, 0x01, 0xe4, 0x47, 0xf6, 0x07,
460x11, 0x00, 0xf6, 0x07, 0x4a, 0x00, 0xf6, 0x07, 0x4c, 0x00, 0xf6, 0x07, 0xed, 0x07, 0xf6, 0x07,
470xf7, 0x07, 0xf6, 0x07, 0x9a, 0x04, 0xf6, 0x07, 0xf8, 0x04, 0x09, 0x00, 0xf6, 0x07, 0xe8, 0x04,
480xf7, 0x07, 0x13, 0x08, 0xc4, 0x07, 0x4b, 0x00, 0x00, 0x00, 0xc4, 0x07, 0xf3, 0x00, 0x0f, 0x04,
490x50, 0x00, 0x00, 0x06, 0xc4, 0x07, 0x20, 0x00, 0xfe, 0x01, 0xfd, 0x07, 0x21, 0x00, 0x02, 0x00,
500x02, 0x00, 0xc4, 0x07, 0x30, 0x00, 0xfe, 0x01, 0xfd, 0x07, 0x28, 0x00, 0x02, 0x00, 0x02, 0x00,
510xc4, 0x07, 0xc0, 0x00, 0xfe, 0x01, 0xfd, 0x07, 0x2f, 0x00, 0x02, 0x00, 0x02, 0x00, 0xc4, 0x07,
520x84, 0x00, 0x00, 0x00, 0xc4, 0x07, 0x87, 0x00, 0x00, 0x00, 0xc4, 0x07, 0x85, 0x00, 0x00, 0x00,
530xc4, 0x07, 0x40, 0x00, 0xfe, 0x00, 0xfd, 0x07, 0x3f, 0x00, 0x02, 0x00, 0x02, 0x00, 0x15, 0x00,
540xf7, 0x07, 0xc5, 0x0a, 0xf7, 0x07, 0xb9, 0x0a, 0xf7, 0x07, 0xcc, 0x0a, 0xf7, 0x07, 0xee, 0x0a,
550xb8, 0x02, 0xba, 0x07, 0x3f, 0x00, 0xc4, 0x07, 0xff, 0x00, 0x0f, 0x04, 0x50, 0x00, 0x00, 0x06,
560x04, 0x00, 0x80, 0x00, 0xe2, 0x07, 0x81, 0x00, 0x23, 0x00, 0x25, 0x00, 0x26, 0x00, 0x60, 0x02,
570xf6, 0x07, 0x59, 0x00, 0xc4, 0x07, 0xb4, 0x00, 0x0f, 0x04, 0x17, 0x00, 0xc9, 0x07, 0xd1, 0x00,
580xc9, 0x0f, 0xd7, 0x00, 0xf7, 0x07, 0xa2, 0x0a, 0xcf, 0x00, 0x0f, 0x08, 0x50, 0x05, 0x04, 0x06,
590x88, 0x04, 0xae, 0x04, 0xa7, 0x04, 0xc4, 0x07, 0xd0, 0x00, 0x09, 0x04, 0xf7, 0x07, 0x17, 0x0b,
600xc4, 0x07, 0xac, 0x00, 0x00, 0x00, 0xe2, 0x07, 0x81, 0x01, 0xee, 0x07, 0xff, 0x0f, 0xf7, 0x07,
610x5e, 0x08, 0xf7, 0x07, 0x48, 0x01, 0xf7, 0x07, 0x5a, 0x01, 0xf7, 0x07, 0xf8, 0x01, 0xf7, 0x07,
620x3e, 0x02, 0x0f, 0x05, 0x17, 0x00, 0xf6, 0x0f, 0x30, 0x01, 0xf7, 0x07, 0x63, 0x02, 0xf7, 0x07,
630xde, 0x02, 0xf7, 0x07, 0x86, 0x02, 0xf7, 0x07, 0x0f, 0x02, 0xf7, 0x07, 0x25, 0x02, 0xf7, 0x07,
640x2e, 0x03, 0xf7, 0x07, 0x46, 0x03, 0xc4, 0x07, 0xa7, 0x00, 0x0f, 0x04, 0x1e, 0x00, 0xf6, 0x0f,
650x30, 0x01, 0x08, 0x02, 0xb9, 0x03, 0xee, 0x00, 0x08, 0x02, 0xf7, 0x07, 0x3c, 0x09, 0x08, 0x01,
660xb9, 0x03, 0xc4, 0x07, 0x86, 0x00, 0x0f, 0x04, 0xde, 0x00, 0xb8, 0x0a, 0xc4, 0x07, 0x50, 0x00,
670x0f, 0x04, 0x9f, 0x01, 0xc5, 0x07, 0xb0, 0x00, 0x81, 0x08, 0xc4, 0x07, 0xa7, 0x00, 0x0f, 0x04,
680x1e, 0x00, 0x01, 0x08, 0x4f, 0x04, 0x17, 0x00, 0xf6, 0x0f, 0x30, 0x01, 0x97, 0x00, 0xf6, 0x0f,
690x2b, 0x01, 0xd8, 0x00, 0xf6, 0x0f, 0xd3, 0x00, 0xf7, 0x07, 0xa2, 0x0a, 0xf6, 0x0f, 0x2b, 0x01,
700x41, 0x00, 0xcf, 0x07, 0x8f, 0x01, 0xc5, 0x07, 0xc1, 0x01, 0x50, 0x04, 0x05, 0x06, 0x45, 0x04,
710x4f, 0x04, 0xc5, 0x07, 0x90, 0x01, 0x45, 0x04, 0x53, 0x04, 0x0f, 0x06, 0xd6, 0x07, 0xc8, 0x00,
720xf6, 0x0f, 0x2b, 0x01, 0xc8, 0x07, 0x10, 0x00, 0x09, 0x02, 0xf9, 0x03, 0xe5, 0x07, 0x38, 0x00,
730xe7, 0x07, 0x61, 0x07, 0x6e, 0x00, 0xb9, 0x01, 0x00, 0x02, 0xf7, 0x07, 0xe9, 0x07, 0xc8, 0x07,
740x40, 0x00, 0xb9, 0x03, 0xc8, 0x07, 0x40, 0x00, 0xb9, 0x03, 0xa6, 0x00, 0xe7, 0x07, 0x5e, 0x07,
750x6e, 0x00, 0xb9, 0x01, 0xe5, 0x07, 0x38, 0x00, 0xe7, 0x07, 0x61, 0x07, 0x6e, 0x00, 0x39, 0x02,
760x8f, 0x04, 0x92, 0x04, 0x08, 0x06, 0x09, 0x00, 0x49, 0x08, 0x0f, 0x04, 0xf7, 0x07, 0xd4, 0x0e,
770xc5, 0x07, 0xb1, 0x00, 0x0f, 0x05, 0xd4, 0x04, 0x4f, 0x05, 0x56, 0x04, 0xc5, 0x07, 0xb1, 0x00,
780x03, 0x0d, 0x43, 0x0d, 0xc4, 0x07, 0x4a, 0x01, 0x01, 0x0c, 0xc4, 0x07, 0xac, 0x00, 0x0f, 0x04,
790x57, 0x00, 0x00, 0x06, 0xf6, 0x0f, 0x1d, 0x01, 0xc4, 0x07, 0x90, 0x01, 0x85, 0x04, 0x4f, 0x04,
800x05, 0x04, 0x50, 0x04, 0x27, 0x06, 0x6d, 0x00, 0x67, 0x06, 0xe8, 0x07, 0xff, 0x07, 0xc4, 0x07,
810x4a, 0x01, 0x40, 0x06, 0xf6, 0x07, 0x7e, 0x00, 0xc4, 0x07, 0xb0, 0x00, 0x80, 0x00, 0xc4, 0x07,
820xb3, 0x00, 0xc5, 0x07, 0x4a, 0x01, 0x0f, 0x04, 0x57, 0x04, 0x01, 0x04, 0xf6, 0x0f, 0x30, 0x01,
830xf6, 0x07, 0x7e, 0x00, 0x01, 0x00, 0x08, 0x02, 0xc9, 0x07, 0xc8, 0x00, 0xf9, 0x03, 0xc4, 0x07,
840xb4, 0x00, 0x0f, 0x04, 0x56, 0x00, 0x00, 0x06, 0x00, 0x08, 0x58, 0x00, 0x38, 0x0b, 0xc4, 0x07,
850x4b, 0x00, 0x0f, 0x04, 0x5f, 0x00, 0x9f, 0x08, 0x38, 0x0b, 0xc4, 0x07, 0x20, 0x00, 0x00, 0x00,
860xc4, 0x07, 0x30, 0x00, 0x80, 0x00, 0xc4, 0x07, 0x47, 0x00, 0x00, 0x03, 0x38, 0x03, 0xc5, 0x07,
870x90, 0x01, 0xc4, 0x07, 0x70, 0x01, 0xc8, 0x07, 0x8e, 0x01, 0xfe, 0x07, 0x10, 0x00, 0xfd, 0x07,
880x58, 0x01, 0x93, 0x00, 0x03, 0x05, 0x0f, 0x05, 0x08, 0x06, 0xc2, 0x07, 0xff, 0x0f, 0x02, 0x00,
890xb8, 0x07, 0xc4, 0x07, 0xca, 0x01, 0x80, 0x07, 0xc8, 0x07, 0x80, 0x00, 0xb9, 0x03, 0xf7, 0x07,
900xc0, 0x01, 0xc5, 0x07, 0xc5, 0x01, 0x41, 0x05, 0x0f, 0x05, 0xc5, 0x07, 0x4f, 0x00, 0x55, 0x04,
910xf7, 0x0f, 0xd8, 0x01, 0xc8, 0x07, 0x80, 0x00, 0xb9, 0x03, 0xf7, 0x07, 0xc0, 0x01, 0xc4, 0x07,
920xc5, 0x01, 0x0f, 0x04, 0x57, 0x05, 0xf6, 0x0f, 0xb5, 0x01, 0x0f, 0x05, 0xc5, 0x07, 0x4f, 0x00,
930x56, 0x04, 0xc4, 0x07, 0x1c, 0x00, 0xb8, 0x0a, 0x27, 0x04, 0x6c, 0x01, 0x4f, 0x05, 0x56, 0x06,
940x0f, 0x0e, 0xd3, 0x0f, 0x00, 0x08, 0x31, 0x06, 0x4f, 0x05, 0x50, 0x06, 0x0f, 0x06, 0x1b, 0x02,
950x16, 0x06, 0x13, 0x08, 0x31, 0x06, 0xc5, 0x07, 0x90, 0x01, 0xfe, 0x07, 0x10, 0x00, 0xfd, 0x07,
960xae, 0x01, 0x3f, 0x00, 0x44, 0x04, 0x0f, 0x04, 0x52, 0x00, 0xf6, 0x0f, 0xaf, 0x01, 0xcf, 0x06,
970xd5, 0x06, 0xf6, 0x0f, 0xa6, 0x01, 0x0f, 0x04, 0xd6, 0x06, 0xcf, 0x06, 0xf6, 0x0f, 0xae, 0x01,
980x16, 0x04, 0xf6, 0x0f, 0xae, 0x01, 0xf6, 0x07, 0xb2, 0x01, 0x0f, 0x04, 0xd5, 0x06, 0xcf, 0x06,
990xf6, 0x0f, 0xb2, 0x01, 0x15, 0x04, 0xf6, 0x0f, 0xb2, 0x01, 0xff, 0x04, 0xf7, 0x07, 0xd8, 0x01,
1000xb8, 0x02, 0xf7, 0x07, 0xda, 0x01, 0xb8, 0x02, 0xc5, 0x07, 0x90, 0x01, 0xc4, 0x07, 0xc5, 0x01,
1010x40, 0x04, 0x44, 0x04, 0x0f, 0x04, 0x52, 0x00, 0xc4, 0x07, 0xca, 0x01, 0x38, 0x04, 0xa6, 0x00,
1020xe7, 0x07, 0xa8, 0x06, 0x6e, 0x00, 0xb9, 0x01, 0x33, 0x01, 0x32, 0x04, 0xb0, 0x04, 0x33, 0x03,
1030x32, 0x04, 0xb0, 0x04, 0xc8, 0x06, 0xc9, 0x06, 0xcf, 0x01, 0xf7, 0x07, 0xd4, 0x0e, 0x48, 0x05,
1040x33, 0x01, 0x32, 0x04, 0xc4, 0x07, 0x1b, 0x00, 0x30, 0x04, 0xc9, 0x06, 0xb8, 0x07, 0xc5, 0x07,
1050x9f, 0x01, 0x44, 0x04, 0xbf, 0x04, 0x0f, 0x04, 0x15, 0x05, 0x6e, 0x04, 0xb8, 0x0f, 0x44, 0x06,
1060x42, 0x05, 0x00, 0x05, 0xc5, 0x07, 0x90, 0x01, 0x4f, 0x04, 0x57, 0x06, 0x44, 0x04, 0xb8, 0x0f,
1070xbf, 0x04, 0x0f, 0x04, 0x15, 0x05, 0xff, 0x0c, 0xf6, 0x0f, 0xe5, 0x01, 0x49, 0x06, 0x48, 0x04,
1080x43, 0x05, 0x09, 0x05, 0x4f, 0x05, 0x58, 0x06, 0xf6, 0x0f, 0xf0, 0x01, 0xb8, 0x07, 0xc4, 0x07,
1090xb0, 0x00, 0x0f, 0x04, 0xd7, 0x00, 0xc4, 0x07, 0x50, 0x00, 0x0f, 0x04, 0x9f, 0x09, 0xc4, 0x07,
1100xc5, 0x01, 0x04, 0x04, 0x0f, 0x00, 0x0f, 0x0c, 0xc4, 0x07, 0x4a, 0x01, 0xc5, 0x07, 0xc0, 0x01,
1110x10, 0x04, 0x27, 0x06, 0xe8, 0x07, 0xff, 0x07, 0x41, 0x06, 0xb8, 0x07, 0xc5, 0x07, 0x4a, 0x01,
1120xc4, 0x07, 0xc0, 0x01, 0x03, 0x04, 0xc4, 0x07, 0xc2, 0x01, 0x03, 0x04, 0xc4, 0x07, 0xc8, 0x01,
1130x83, 0x04, 0x03, 0x04, 0xc4, 0x07, 0xc5, 0x01, 0x0f, 0x04, 0xd3, 0x07, 0x70, 0x01, 0x03, 0x06,
1140xc4, 0x07, 0xc1, 0x01, 0x03, 0x04, 0xb8, 0x07, 0xc4, 0x07, 0xc1, 0x01, 0x08, 0x04, 0xc9, 0x07,
1150x90, 0x01, 0xc5, 0x07, 0x50, 0x01, 0x44, 0x05, 0x04, 0x04, 0x83, 0x04, 0x03, 0x04, 0x0f, 0x05,
1160x58, 0x00, 0x08, 0x06, 0x4f, 0x05, 0x50, 0x00, 0x09, 0x06, 0xf6, 0x0f, 0x2c, 0x02, 0xc4, 0x07,
1170x50, 0x00, 0x0f, 0x04, 0x1d, 0x02, 0x00, 0x06, 0xb8, 0x07, 0xc4, 0x07, 0xc0, 0x01, 0x32, 0x00,
1180x32, 0x04, 0xc5, 0x07, 0x90, 0x01, 0xfe, 0x07, 0x10, 0x00, 0xfd, 0x07, 0x59, 0x02, 0x08, 0x00,
1190xc4, 0x04, 0x0f, 0x04, 0x52, 0x00, 0xf6, 0x0f, 0x5a, 0x02, 0x27, 0x04, 0xe8, 0x07, 0xff, 0x07,
1200x40, 0x06, 0x4f, 0x06, 0x15, 0x07, 0xd0, 0x07, 0x00, 0x08, 0x00, 0x0e, 0x0f, 0x05, 0x50, 0x00,
1210x08, 0x06, 0xc4, 0x07, 0xac, 0x00, 0x0f, 0x04, 0x17, 0x00, 0x00, 0x0d, 0xc4, 0x07, 0xc1, 0x01,
1220x00, 0x05, 0xb8, 0x07, 0xc9, 0x07, 0x90, 0x01, 0xc4, 0x07, 0xc1, 0x01, 0xfd, 0x07, 0x84, 0x02,
1230x3e, 0x04, 0x45, 0x05, 0x48, 0x04, 0x32, 0x00, 0x72, 0x04, 0xc5, 0x07, 0x90, 0x01, 0x4f, 0x04,
1240x17, 0x07, 0xf6, 0x0f, 0x82, 0x02, 0x04, 0x05, 0x0f, 0x04, 0x44, 0x04, 0x19, 0x04, 0xff, 0x0c,
1250xf6, 0x0f, 0x70, 0x02, 0x6e, 0x04, 0x03, 0x05, 0x48, 0x06, 0x0f, 0x05, 0x18, 0x07, 0xf6, 0x0f,
1260x7b, 0x02, 0x4f, 0x05, 0x50, 0x00, 0x09, 0x06, 0xb8, 0x07, 0xf7, 0x07, 0x3b, 0x0a, 0x29, 0x00,
1270x4f, 0x06, 0x50, 0x06, 0x10, 0x06, 0x2e, 0x06, 0xc4, 0x07, 0xc6, 0x01, 0xc5, 0x07, 0x90, 0x01,
1280x45, 0x04, 0x48, 0x04, 0xc5, 0x07, 0xc1, 0x01, 0x4f, 0x04, 0xd0, 0x07, 0x8f, 0x01, 0x05, 0x06,
1290x45, 0x04, 0x4f, 0x04, 0x53, 0x06, 0x09, 0x06, 0x02, 0x05, 0x40, 0x05, 0xc4, 0x07, 0xc8, 0x01,
1300xc2, 0x07, 0xff, 0x0f, 0xc2, 0x07, 0xff, 0x0f, 0xf7, 0x07, 0x06, 0x03, 0x49, 0x00, 0xf6, 0x07,
1310xc6, 0x02, 0x4f, 0x05, 0xd0, 0x07, 0x90, 0x01, 0x05, 0x06, 0x45, 0x04, 0x48, 0x04, 0xc5, 0x07,
1320xc6, 0x01, 0xcf, 0x04, 0x1a, 0x05, 0x0f, 0x05, 0xda, 0x0c, 0xf7, 0x0f, 0x06, 0x03, 0x0f, 0x05,
1330x53, 0x06, 0x08, 0x06, 0xc5, 0x07, 0xc6, 0x01, 0xcf, 0x04, 0x1a, 0x05, 0x0f, 0x05, 0xda, 0x0c,
1340xf7, 0x0f, 0x06, 0x03, 0x4f, 0x05, 0x50, 0x00, 0x09, 0x06, 0x4f, 0x05, 0xc4, 0x07, 0xc1, 0x01,
1350x16, 0x04, 0xf6, 0x0f, 0xaa, 0x02, 0x48, 0x06, 0xc4, 0x07, 0xc8, 0x01, 0x0f, 0x00, 0xa7, 0x04,
1360xa9, 0x04, 0x57, 0x06, 0xc5, 0x07, 0x82, 0x00, 0xc4, 0x07, 0xc2, 0x01, 0x0f, 0x04, 0x53, 0x04,
1370x00, 0x0e, 0xc4, 0x07, 0xab, 0x00, 0x00, 0x0e, 0xb8, 0x07, 0xc4, 0x07, 0xb0, 0x00, 0x0f, 0x04,
1380x57, 0x00, 0xc4, 0x07, 0xac, 0x00, 0x0f, 0x04, 0xc4, 0x07, 0xc1, 0x01, 0x17, 0x0c, 0xc4, 0x07,
1390x48, 0x01, 0xc5, 0x07, 0xc5, 0x01, 0x45, 0x04, 0x40, 0x0c, 0xb8, 0x0f, 0x27, 0x04, 0x6a, 0x04,
1400x4f, 0x06, 0xde, 0x03, 0xb8, 0x0f, 0x0f, 0x04, 0x55, 0x04, 0x1b, 0x02, 0x08, 0x06, 0xc8, 0x0f,
1410x00, 0x08, 0xc4, 0x07, 0xc1, 0x01, 0xc5, 0x07, 0x90, 0x01, 0x3e, 0x04, 0xfd, 0x07, 0x04, 0x03,
1420x0f, 0x05, 0xc4, 0x04, 0x10, 0x04, 0x00, 0x06, 0xb8, 0x07, 0x33, 0x03, 0x31, 0x00, 0x31, 0x00,
1430xc5, 0x07, 0x90, 0x01, 0xc4, 0x07, 0xc1, 0x01, 0x3e, 0x04, 0xfd, 0x07, 0x1c, 0x03, 0xc4, 0x04,
1440x8f, 0x04, 0x32, 0x04, 0x1a, 0x05, 0x13, 0x0e, 0x0f, 0x08, 0x30, 0x0e, 0xf6, 0x0f, 0x1c, 0x03,
1450x0f, 0x06, 0x55, 0x06, 0x30, 0x0e, 0xc4, 0x04, 0xc4, 0x07, 0xc8, 0x01, 0xcf, 0x06, 0x94, 0x04,
1460xcf, 0x06, 0x96, 0x04, 0xc4, 0x07, 0xc8, 0x01, 0xc2, 0x0e, 0xc2, 0x0e, 0xc4, 0x07, 0xc2, 0x01,
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7290x25, 0x00, 0xe2, 0x07, 0xc3, 0x00, 0xe3, 0x07, 0x10, 0x00, 0x66, 0x00, 0x60, 0x0a, 0x21, 0x00,
7300xc2, 0x07, 0x2c, 0x00, 0x2a, 0x04, 0xc2, 0x07, 0x3f, 0x00, 0x08, 0x04, 0x10, 0x06, 0x00, 0x05,
7310x08, 0x05, 0xc2, 0x02, 0x10, 0x04, 0x02, 0x00, 0x01, 0x05, 0xc2, 0x07, 0x12, 0x00, 0xc8, 0x07,
7320x40, 0x00, 0x1c, 0x04, 0x15, 0x05, 0x25, 0x00, 0xe2, 0x07, 0x41, 0x01, 0xe3, 0x07, 0x4b, 0x00,
7330x26, 0x00, 0x60, 0x0a, 0x21, 0x00, 0xb8, 0x07, 0x03, 0x00, 0x2a, 0x04, 0x41, 0x06, 0x29, 0x04,
7340x01, 0x06, 0x6d, 0x04, 0x48, 0x04, 0x2c, 0x04, 0xc1, 0x05, 0x80, 0x06, 0xae, 0x00, 0xc3, 0x00,
7350x41, 0x06, 0x53, 0x06, 0x08, 0x05, 0x11, 0x04, 0x00, 0x05, 0xb8, 0x07, 0xc2, 0x07, 0x2e, 0x00,
7360x2a, 0x04, 0xc2, 0x07, 0x68, 0x00, 0x00, 0x06, 0xc2, 0x07, 0x1a, 0x00, 0x6a, 0x04, 0x00, 0x06,
7370xb8, 0x07, 0xc2, 0x07, 0x1a, 0x00, 0x6a, 0x04, 0x08, 0x06, 0x14, 0x00, 0xb8, 0x0f, 0x08, 0x04,
7380x56, 0x00, 0x00, 0x05, 0xb8, 0x0f, 0x00, 0x06, 0xc2, 0x07, 0x68, 0x00, 0x08, 0x04, 0x96, 0x01,
7390x50, 0x00, 0x00, 0x05, 0xc0, 0x09, 0xb8, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7400x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7410x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7420x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7430x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7440x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7450x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7460x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7470x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7480x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7490x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7500x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
7510x92, 0x00, 0x02, 0x82, 0x00, 0x00, 0x00, 0x80, 0x00, 0x01, 0x4a, 0x7f, 0x00, 0x00, 0x00, 0x00,
7520x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe6, 0xff, 0xe3, 0xff, 0xc8, 0x00, 0x46, 0x00,
7530x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7540x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7550xe8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7560x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7570x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7580x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7590x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7600x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7610x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7620x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7630x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x01, 0x00,
7640x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x01, 0x00,
7650x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x01, 0x00,
7660x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x01, 0x00,
7670x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
768};
769u32_t DRXD_A2_microcode_length = (sizeof(DRXD_A2_microcode));
770
771
772u8_t DRXD_B1_microcode[] = {
7730x48, 0x4c, 0x00, 0x04, 0x00, 0x83, 0x00, 0x00, 0x10, 0x00, 0x00, 0x01, 0xc0, 0x7d, 0xf6, 0x07,
7740xa0, 0x0f, 0xf6, 0x07, 0xdb, 0x0f, 0xf6, 0x07, 0xdd, 0x0f, 0xf6, 0x07, 0x79, 0x00, 0xf6, 0x07,
7750x83, 0x00, 0xf6, 0x07, 0x03, 0x04, 0xf6, 0x07, 0x5d, 0x04, 0x09, 0x00, 0xf6, 0x07, 0x4d, 0x04,
7760xbf, 0x07, 0x38, 0x04, 0xf6, 0x07, 0x9e, 0x01, 0xf6, 0x07, 0xbf, 0x01, 0xf6, 0x07, 0xd1, 0x01,
7770xf6, 0x07, 0xd8, 0x01, 0xf6, 0x07, 0x61, 0x02, 0xf6, 0x07, 0x66, 0x02, 0xf6, 0x07, 0x6d, 0x02,
7780xf6, 0x07, 0x70, 0x02, 0xf6, 0x07, 0x54, 0x06, 0xf6, 0x07, 0x96, 0x06, 0xf6, 0x07, 0xd2, 0x06,
7790xf6, 0x07, 0xf4, 0x06, 0xf6, 0x07, 0x24, 0x07, 0xf6, 0x07, 0x6c, 0x07, 0xf6, 0x07, 0x7b, 0x07,
7800xf6, 0x07, 0x97, 0x07, 0xf6, 0x07, 0xb2, 0x07, 0xf6, 0x07, 0xd8, 0x07, 0xb8, 0x02, 0x3f, 0x00,
7810xf6, 0x07, 0x14, 0x0f, 0xf6, 0x07, 0x3c, 0x0f, 0xf6, 0x07, 0xea, 0x0e, 0xf6, 0x07, 0x71, 0x0f,
7820xf6, 0x07, 0xc8, 0x02, 0xb8, 0x07, 0x3f, 0x00, 0xb8, 0x07, 0x3f, 0x00, 0xf6, 0x07, 0xdf, 0x02,
7830xb8, 0x07, 0x3f, 0x00, 0xb8, 0x07, 0x3f, 0x00, 0xb8, 0x07, 0x3f, 0x00, 0xf6, 0x07, 0x0b, 0x03,
7840xf6, 0x07, 0x13, 0x06, 0xf6, 0x07, 0x52, 0x08, 0xf6, 0x07, 0x42, 0x0a, 0xf6, 0x07, 0xa7, 0x09,
7850xf6, 0x07, 0x07, 0x0b, 0xf6, 0x07, 0xc9, 0x0e, 0xf6, 0x07, 0x20, 0x03, 0xf6, 0x07, 0x39, 0x03,
7860xf6, 0x07, 0x95, 0x0e, 0xe5, 0x07, 0xd0, 0x01, 0x26, 0x00, 0xf7, 0x07, 0x71, 0x00, 0x4f, 0x06,
7870xea, 0x07, 0xff, 0x0f, 0x67, 0x06, 0x28, 0x04, 0x50, 0x06, 0x00, 0x06, 0xf6, 0x07, 0x75, 0x00,
7880xa0, 0x02, 0x21, 0x00, 0xf6, 0x07, 0x9f, 0x00, 0x60, 0x02, 0x21, 0x00, 0xf6, 0x07, 0x9f, 0x00,
7890xc4, 0x07, 0x3c, 0x00, 0x80, 0x02, 0xf6, 0x07, 0x8d, 0x00, 0xc4, 0x07, 0x3c, 0x00, 0x80, 0x03,
7900xf6, 0x07, 0x8d, 0x00, 0xc4, 0x07, 0x3c, 0x00, 0x40, 0x02, 0xf6, 0x07, 0x8d, 0x00, 0xc4, 0x07,
7910x3c, 0x00, 0xc0, 0x02, 0xf6, 0x07, 0x8d, 0x00, 0xc4, 0x07, 0x3b, 0x00, 0x40, 0x06, 0xe8, 0x07,
7920xff, 0x00, 0x63, 0x06, 0x6a, 0x06, 0x67, 0x06, 0x2b, 0x01, 0x67, 0x06, 0xac, 0x01, 0x67, 0x06,
7930xa9, 0x04, 0x62, 0x06, 0x20, 0x04, 0x21, 0x00, 0xf6, 0x07, 0x9f, 0x00, 0xa4, 0x00, 0xe5, 0x07,
7940xd0, 0x01, 0x26, 0x00, 0xc4, 0x07, 0xd0, 0x01, 0xb8, 0x07, 0xfe, 0x07, 0x20, 0x00, 0xf5, 0x07,
7950xb6, 0x00, 0x2e, 0x00, 0x0f, 0x05, 0x11, 0x05, 0x08, 0x06, 0x4f, 0x05, 0x51, 0x05, 0x09, 0x06,
7960x4f, 0x06, 0x50, 0x06, 0x2e, 0x06, 0x4f, 0x06, 0x15, 0x07, 0x2e, 0x0e, 0x48, 0x06, 0xb8, 0x07,
7970x33, 0x03, 0x31, 0x00, 0x31, 0x00, 0x4f, 0x05, 0xdf, 0x03, 0x04, 0x00, 0x00, 0x00, 0x40, 0x08,
7980x0f, 0x00, 0x14, 0x05, 0x08, 0x0e, 0x53, 0x05, 0x09, 0x0e, 0x44, 0x00, 0x00, 0x00, 0xf5, 0x07,
7990xe0, 0x00, 0x29, 0x00, 0x0f, 0x05, 0x11, 0x05, 0x08, 0x06, 0x4f, 0x05, 0x51, 0x05, 0x09, 0x06,
8000x0f, 0x04, 0x10, 0x04, 0x00, 0x06, 0x0f, 0x06, 0x55, 0x06, 0x00, 0x0e, 0x0f, 0x00, 0x54, 0x08,
8010xcf, 0x06, 0xee, 0x06, 0xd1, 0x06, 0x31, 0x06, 0x4f, 0x06, 0x50, 0x06, 0x31, 0x06, 0x29, 0x00,
8020xc8, 0x06, 0xc9, 0x06, 0x0f, 0x04, 0x10, 0x04, 0x0f, 0x06, 0x55, 0x06, 0x0f, 0x05, 0x51, 0x00,
8030x08, 0x0e, 0x4f, 0x05, 0x10, 0x00, 0x09, 0x0e, 0x04, 0x00, 0x0f, 0x00, 0x16, 0x04, 0x14, 0x05,
8040x08, 0x0e, 0x53, 0x05, 0x09, 0x0e, 0xb8, 0x07, 0x0f, 0x04, 0x5a, 0x00, 0x00, 0x06, 0x00, 0x08,
8050xb8, 0x07, 0x27, 0x05, 0x2c, 0x03, 0x4f, 0x06, 0x2b, 0x01, 0x67, 0x06, 0x2d, 0x01, 0x48, 0x06,
8060x67, 0x05, 0x2b, 0x02, 0x67, 0x06, 0x2d, 0x01, 0x50, 0x06, 0x09, 0x06, 0xb8, 0x07, 0xd5, 0x07,
8070x20, 0x00, 0x08, 0x08, 0x09, 0x08, 0xb8, 0x0f, 0xd5, 0x07, 0x10, 0x00, 0x09, 0x0d, 0x08, 0x08,
8080x0f, 0x0e, 0x17, 0x00, 0xb8, 0x0f, 0x67, 0x05, 0x2b, 0x06, 0x49, 0x06, 0x27, 0x05, 0x2b, 0x06,
8090x08, 0x06, 0xcf, 0x07, 0x10, 0x00, 0x13, 0x05, 0x48, 0x06, 0x2c, 0x06, 0x67, 0x06, 0x69, 0x05,
8100x49, 0x06, 0xb8, 0x07, 0xd5, 0x07, 0x10, 0x00, 0x48, 0x0d, 0x67, 0x0d, 0xed, 0x0b, 0x49, 0x0e,
8110x0f, 0x0e, 0xd5, 0x0f, 0x10, 0x00, 0x48, 0x0d, 0xb8, 0x0f, 0x17, 0x00, 0xb8, 0x0f, 0x27, 0x05,
8120x2c, 0x06, 0x48, 0x06, 0x67, 0x05, 0x2d, 0x06, 0x09, 0x06, 0xcf, 0x07, 0x10, 0x00, 0x53, 0x05,
8130x49, 0x06, 0x2b, 0x06, 0x67, 0x06, 0x29, 0x05, 0x48, 0x06, 0xb8, 0x07, 0x0f, 0x05, 0x12, 0x05,
8140x50, 0x00, 0x13, 0x08, 0x08, 0x06, 0x33, 0x03, 0x0f, 0x05, 0x12, 0x05, 0x31, 0x00, 0xcf, 0x0f,
8150xaa, 0x00, 0xdb, 0x0f, 0xaa, 0x00, 0x10, 0x0e, 0x31, 0x0e, 0x31, 0x00, 0x32, 0x05, 0xcf, 0x07,
8160x56, 0x00, 0xdb, 0x07, 0x55, 0x00, 0x10, 0x06, 0x30, 0x06, 0xff, 0x06, 0xb8, 0x07, 0x32, 0x00,
8170x32, 0x05, 0xf7, 0x07, 0x64, 0x01, 0x32, 0x00, 0x72, 0x05, 0xf7, 0x07, 0x64, 0x01, 0xb3, 0x00,
8180x71, 0x05, 0x30, 0x05, 0xb8, 0x07, 0x0f, 0x07, 0xdf, 0x03, 0x0f, 0x00, 0x13, 0x07, 0x32, 0x08,
8190x32, 0x0e, 0xcf, 0x07, 0xf3, 0x00, 0xdb, 0x07, 0x36, 0x00, 0x10, 0x06, 0x2e, 0x06, 0x0f, 0x07,
8200x55, 0x06, 0x32, 0x00, 0x32, 0x00, 0x72, 0x08, 0x0f, 0x0e, 0x55, 0x0e, 0xb2, 0x08, 0x27, 0x05,
8210x2d, 0x07, 0x48, 0x06, 0x67, 0x05, 0x2d, 0x07, 0x49, 0x06, 0xb8, 0x07, 0x04, 0x01, 0x80, 0x07,
8220xc5, 0x07, 0x43, 0x00, 0x4f, 0x04, 0x56, 0x02, 0xd0, 0x07, 0x11, 0x00, 0x10, 0x06, 0xc5, 0x07,
8230x40, 0x00, 0xc8, 0x04, 0xc9, 0x04, 0xee, 0x04, 0x37, 0x0e, 0xc5, 0x07, 0x40, 0x00, 0x03, 0x05,
8240x43, 0x05, 0xee, 0x07, 0xff, 0x0f, 0x29, 0x08, 0x43, 0x06, 0x01, 0x00, 0x04, 0x01, 0x38, 0x04,
8250x16, 0x00, 0xb8, 0x07, 0x27, 0x00, 0x15, 0x00, 0xb8, 0x07, 0x4f, 0x06, 0x55, 0x02, 0xf6, 0x0f,
8260x99, 0x01, 0xd0, 0x07, 0x20, 0x00, 0x04, 0x06, 0x0f, 0x00, 0x18, 0x04, 0x00, 0x00, 0x17, 0x0d,
8270xc4, 0x07, 0x46, 0x00, 0x0f, 0x04, 0x9d, 0x00, 0x00, 0x0e, 0xc4, 0x07, 0x85, 0x00, 0x0f, 0x04,
8280x5d, 0x06, 0x00, 0x0e, 0xc4, 0x07, 0x45, 0x00, 0x0f, 0x04, 0x5d, 0x06, 0x00, 0x0e, 0xc4, 0x07,
8290x84, 0x00, 0x0f, 0x04, 0x5c, 0x06, 0x00, 0x0e, 0xf6, 0x07, 0xbf, 0x01, 0x4f, 0x06, 0x55, 0x02,
8300xf6, 0x0f, 0x99, 0x01, 0xd0, 0x07, 0x30, 0x00, 0x04, 0x06, 0x00, 0x05, 0x18, 0x00, 0xf6, 0x0f,
8310xcf, 0x01, 0x4f, 0x05, 0x18, 0x00, 0xc4, 0x07, 0x47, 0x00, 0x40, 0x0d, 0xf6, 0x07, 0x9b, 0x01,
8320xc4, 0x07, 0x48, 0x00, 0x00, 0x05, 0xc4, 0x07, 0x49, 0x00, 0x40, 0x05, 0xc9, 0x01, 0xc4, 0x07,
8330x48, 0x00, 0x85, 0x00, 0x03, 0x04, 0x00, 0x05, 0x81, 0x07, 0x4f, 0x05, 0x1f, 0x00, 0x6e, 0x00,
8340xf7, 0x0f, 0xfe, 0x01, 0x4f, 0x05, 0x5f, 0x00, 0xf7, 0x0f, 0x21, 0x02, 0x4f, 0x05, 0x9f, 0x00,
8350xf7, 0x0f, 0x2a, 0x02, 0x4f, 0x05, 0xdf, 0x00, 0xf7, 0x0f, 0x3d, 0x02, 0x4f, 0x05, 0x1f, 0x01,
8360xf7, 0x0f, 0x4a, 0x02, 0x4f, 0x05, 0x5f, 0x01, 0xf7, 0x0f, 0x54, 0x02, 0x27, 0x00, 0x15, 0x00,
8370xc5, 0x07, 0x48, 0x00, 0x84, 0x00, 0x81, 0x04, 0x38, 0x04, 0xf7, 0x07, 0xfd, 0x04, 0xc4, 0x07,
8380xd0, 0x01, 0x00, 0x00, 0x40, 0x08, 0x4f, 0x06, 0x18, 0x00, 0xe7, 0x0f, 0x10, 0x08, 0x6e, 0x08,
8390x39, 0x0a, 0xe7, 0x07, 0x10, 0x05, 0x6e, 0x00, 0x39, 0x02, 0xe7, 0x07, 0x10, 0x06, 0x6e, 0x00,
8400x39, 0x02, 0xe7, 0x07, 0x10, 0x0a, 0xae, 0x00, 0x39, 0x02, 0xe7, 0x07, 0x10, 0x04, 0x6e, 0x00,
8410x39, 0x02, 0x17, 0x00, 0xb8, 0x0f, 0xf7, 0x07, 0xfd, 0x04, 0xf7, 0x07, 0xf4, 0x05, 0xb8, 0x07,
8420xf7, 0x07, 0xac, 0x04, 0xc4, 0x07, 0xd0, 0x01, 0x40, 0x06, 0xe7, 0x07, 0x11, 0x0a, 0xae, 0x00,
8430x38, 0x02, 0x04, 0x00, 0x42, 0x05, 0x80, 0x07, 0xf7, 0x07, 0xb4, 0x04, 0xc5, 0x07, 0xd0, 0x01,
8440x41, 0x06, 0xe7, 0x07, 0x46, 0x07, 0x6e, 0x00, 0x39, 0x02, 0xe7, 0x07, 0x11, 0x08, 0x6e, 0x00,
8450x39, 0x02, 0x04, 0x00, 0x89, 0x04, 0x38, 0x04, 0xf7, 0x07, 0xd6, 0x04, 0xc4, 0x07, 0xd0, 0x01,
8460x40, 0x06, 0xe7, 0x07, 0x47, 0x07, 0x6e, 0x00, 0x39, 0x02, 0xe7, 0x07, 0x12, 0x08, 0x6e, 0x00,
8470x38, 0x02, 0xf7, 0x07, 0xdf, 0x04, 0xc4, 0x07, 0xd0, 0x01, 0x40, 0x06, 0xe7, 0x0f, 0x11, 0x08,
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1496};
1497u32_t DRXD_B1_microcode_length = (sizeof(DRXD_B1_microcode));
1498
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-28 10:14:04 -0500